diff --git a/CMakeLists.txt b/CMakeLists.txt index 1a26bab9..12bba297 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,3 +1,4 @@ add_subdirectory(simplelink) +add_subdirectory(simplelink_lpf2) add_subdirectory(simplelink_lpf3) add_subdirectory(mspm0) diff --git a/simplelink/CMakeLists.txt b/simplelink/CMakeLists.txt index 521173af..fc868fcb 100644 --- a/simplelink/CMakeLists.txt +++ b/simplelink/CMakeLists.txt @@ -1,5 +1,3 @@ -add_subdirectory(source/ti/devices) - if(CONFIG_SIMPLELINK_HOST_DRIVER) zephyr_include_directories( . @@ -14,6 +12,8 @@ if(CONFIG_SIMPLELINK_HOST_DRIVER) endif() if(CONFIG_HAS_CC3220SDK) + add_subdirectory(source/ti/devices) + if(CONFIG_SIMPLELINK_HOST_DRIVER) zephyr_library() zephyr_library_compile_definitions(${COMPILER}) @@ -58,16 +58,13 @@ if(CONFIG_HAS_CC3220SDK) PROPERTIES COMPILE_FLAGS -Wno-incompatible-pointer-types) # driver.c warns on incompatible-pointer-types endif() -elseif(CONFIG_HAS_CC13X2_CC26X2_SDK OR CONFIG_HAS_CC13X2X7_CC26X2X7_SDK) +elseif(CONFIG_HAS_CC13X2_CC26X2_SDK) + add_subdirectory(source/ti/devices) if(CONFIG_SOC_CC1352R OR CONFIG_SOC_CC1352P) zephyr_compile_definitions(DeviceFamily_CC13X2 ${COMPILER}) - elseif(CONFIG_SOC_CC1352R7 OR CONFIG_SOC_CC1352P7) - zephyr_compile_definitions(DeviceFamily_CC13X2X7 ${COMPILER}) elseif(CONFIG_SOC_CC2652R OR CONFIG_SOC_CC2652P) zephyr_compile_definitions(DeviceFamily_CC26X2 ${COMPILER}) - elseif(CONFIG_SOC_CC2652R7 OR CONFIG_SOC_CC2652P7) - zephyr_compile_definitions(DeviceFamily_CC26X2X7 ${COMPILER}) endif() zephyr_include_directories( @@ -93,6 +90,8 @@ elseif(CONFIG_HAS_CC13X2_CC26X2_SDK OR CONFIG_HAS_CC13X2X7_CC26X2X7_SDK) ) elseif(CONFIG_HAS_MSP432P4XXSDK) + add_subdirectory(source/ti/devices) + zephyr_include_directories( source ) diff --git a/simplelink_lpf2/CMakeLists.txt b/simplelink_lpf2/CMakeLists.txt new file mode 100644 index 00000000..a5ca2122 --- /dev/null +++ b/simplelink_lpf2/CMakeLists.txt @@ -0,0 +1,58 @@ +if(CONFIG_HAS_CC13X2X7_CC26X2X7_SDK) + if(CONFIG_SOC_CC1352R7 OR CONFIG_SOC_CC1352P7) + zephyr_compile_definitions(DeviceFamily_CC13X2X7 ${COMPILER}) + elseif(CONFIG_SOC_CC2652R7 OR CONFIG_SOC_CC2652P7) + zephyr_compile_definitions(DeviceFamily_CC26X2X7 ${COMPILER}) + endif() + + zephyr_include_directories( + . + source + source/ti/devices/cc13x2x7_cc26x2x7 + ) + + zephyr_library() + zephyr_library_sources( + # device driverlib files + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.c + + # PM + source/ti/drivers/power/PowerCC26X2.c + source/ti/drivers/power/PowerCC26X2_helpers.c + source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c + source/ti/drivers/power/PowerCC26X2_calibrateRCOSC_helpers.c + source/ti/drivers/utils/List.c + source/ti/drivers/rf/RFCC26X2_multiMode.c + + # DPL + kernel/zephyr/dpl/ClockP_zephyr.c + kernel/zephyr/dpl/HwiP_zephyr.c + kernel/zephyr/dpl/SemaphoreP_zephyr.c + kernel/zephyr/dpl/SwiP_zephyr.c + kernel/zephyr/dpl/QueueP_zephyr.c + ) + + # Required for on-chip flash support + zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC13XX_CC26XX source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.c) + + # Required for IEEE 802.15.4 support + zephyr_library_sources_ifdef(CONFIG_IEEE802154_CC13XX_CC26XX + source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.c + source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.c + ) + + # Required for IEEE 802.15.4g support + zephyr_library_sources_ifdef(CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ + source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.c + source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.c + ) + + zephyr_library_sources_ifdef(CONFIG_ADC_CC13XX_CC26XX source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.c) +endif() diff --git a/simplelink_lpf2/README.md b/simplelink_lpf2/README.md new file mode 100644 index 00000000..9670cf1a --- /dev/null +++ b/simplelink_lpf2/README.md @@ -0,0 +1,21 @@ +# Simplelink LPF2 + +This folder contains the low-level support required from the +Simplelink LPF2 SDK. + +### Version + +The current version of simplelink_lpf2 is based on +[Simplelink LPF2 8.31.00.11](https://github.com/TexasInstruments/simplelink-lowpower-f2-sdk). + +## Contents + +The folder-structure herein reflects the folder-structure in the +Simplelink SDK. All files required to support Zephyr have been copied +manually from the Simplelink SDK, with the exception of DPL files under +`kernel/zephyr/dpl`, which are original and maintained in this repository. + +When updating to a new SDK, a comparison of the files in the 'devices' +and 'drivers' directories should be performed to pick up any new changes. + +There is a simple helper script present to copy the relevant directories. diff --git a/simplelink_lpf2/kernel/zephyr/dpl/ClockP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/ClockP_zephyr.c new file mode 100644 index 00000000..afb2add8 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/ClockP_zephyr.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define CLOCKP_TICK_PERIOD (USEC_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC); + +/* + * ClockP_STRUCT_SIZE in ClockP.h must be updated to match the size of this + * struct + */ +typedef struct _ClockP_Obj { + struct k_timer timer; + ClockP_Fxn clock_fxn; + uintptr_t arg; + uint32_t timeout; /* in sys clock uptime ticks */ + uint32_t period; /* in sys clock uptime ticks */ + bool active; +} ClockP_Obj; + +static ClockP_Params ClockP_defaultParams = { + .startFlag = false, + .period = 0, + .arg = 0, +}; + +static void expiry_fxn(struct k_timer *timer_id) +{ + ClockP_Obj *obj = (ClockP_Obj *)k_timer_user_data_get(timer_id); + + obj->clock_fxn(obj->arg); +} + +/* + * ======== ClockP_construct ======== + * @param timeout in sys clock uptime ticks + */ +ClockP_Handle ClockP_construct(ClockP_Struct *handle, ClockP_Fxn clockFxn, + uint32_t timeout, ClockP_Params *params) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + if (handle == NULL) { + return NULL; + } + + if (params == NULL) { + params = &ClockP_defaultParams; + } + + obj->clock_fxn = clockFxn; + obj->arg = params->arg; + obj->period = params->period; + obj->timeout = timeout; + obj->active = false; + + k_timer_init(&obj->timer, expiry_fxn, NULL); + k_timer_user_data_set(&obj->timer, obj); + + if (params->startFlag) { + ClockP_start(obj); + } + + return ((ClockP_Handle)handle); +} + +/* + * ======== ClockP_getSystemTickFreq ======== + */ +inline uint32_t ClockP_getSystemTickFreq() +{ + return CONFIG_SYS_CLOCK_TICKS_PER_SEC; +} + +/* + * ======== ClockP_getSystemTickPeriod ======== + * + * This implementation rounds the system tick period down by ~17250ppm + * which makes it useless for any precision timing. Use + * (timeUs * ClockP_getSystemTickFreq() for these purposes instead. + */ +inline uint32_t ClockP_getSystemTickPeriod() +{ + return CLOCKP_TICK_PERIOD; +} + +uint32_t ClockP_getSystemTicks() +{ + /* may wrap */ + return k_uptime_ticks(); +} + +/* + * ======== ClockP_Params_init ======== + */ +void ClockP_Params_init(ClockP_Params *params) +{ + params->arg = 0; + params->startFlag = false; + params->period = 0; +} + +/* + * ======== ClockP_setTimeout ======== + * @param timeout in sys clock uptime ticks + */ +void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + obj->timeout = timeout; +} + +/* + * ======== ClockP_start ======== + */ +void ClockP_start(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + k_timer_start(&obj->timer, K_TICKS(obj->timeout), K_TICKS(obj->period)); + obj->active = true; +} + +/* + * ======== ClockP_stop ======== + */ +void ClockP_stop(ClockP_Handle handle) +{ + ClockP_Obj *obj = (ClockP_Obj *)handle; + + k_timer_stop(&obj->timer); + obj->active = false; +} + +/* + * ======== ClockP_usleep ======== + */ +void ClockP_usleep(uint32_t usec) +{ + k_sleep(K_USEC(usec)); +} + +/* + * ======== ClockP_getTimeout ======== + */ +uint32_t ClockP_getTimeout(ClockP_Handle handle) { + ClockP_Obj *obj = (ClockP_Obj *)handle; + return obj->active ? k_timer_remaining_ticks(&obj->timer) : obj->timeout; +} + +/* + * ======== ClockP_isActive ======== + */ +bool ClockP_isActive(ClockP_Handle handle) { + ClockP_Obj *obj = (ClockP_Obj *)handle; + return obj->active; +} + +void ClockP_destruct(ClockP_Struct *clockP) +{ + ClockP_Obj *obj = (ClockP_Obj *)clockP->data; + + obj->clock_fxn = NULL; + obj->arg = 0; + obj->period = 0; + obj->timeout = 0; + obj->active = false; + + k_timer_stop(&obj->timer); +} diff --git a/simplelink_lpf2/kernel/zephyr/dpl/HwiP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/HwiP_zephyr.c new file mode 100644 index 00000000..25fbe8af --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/HwiP_zephyr.c @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include +#include +#include +#include + +#include +#include +#include +#if defined(CONFIG_SOC_SERIES_CC32XX) +#include +#endif +#include + +/* + * IRQ_CONNECT requires we know the ISR signature and argument + * at build time; whereas SimpleLink plugs the interrupts + * at run time, so we create an ISR shim, and register that. + * The callback argument doesn't change after the ISR is registered. + */ +struct sl_isr_args +{ + HwiP_Fxn cb; + uintptr_t arg; +}; + +static void sl_isr(const void *isr_arg) +{ + HwiP_Fxn cb = ((struct sl_isr_args *)isr_arg)->cb; + uintptr_t arg = ((struct sl_isr_args *)isr_arg)->arg; + + /* Call the SimpleLink ISR Handler: */ + if (cb) { + cb(arg); + } +} + +#if defined(CONFIG_SOC_SERIES_CC32XX) +static struct sl_isr_args sl_UDMA_cb = {NULL, 0}; +static struct sl_isr_args sl_UDMAERR_cb = {NULL, 0}; +static struct sl_isr_args sl_NWPIC_cb = {NULL, 0}; +static struct sl_isr_args sl_LSPI_cb = {NULL, 0}; + +/* Must hardcode the IRQ for IRQ_CONNECT macro. Must be <= CONFIG_NUM_IRQS.*/ +#define EXCEPTION_UDMA 46 /* == INT_UDMA (62) - 16 */ +#define EXCEPTION_UDMAERR 47 /* == INT_UDMAERR (63) - 16 */ +#define EXCEPTION_NWPIC 171 /* == INT_NWPIC (187) - 16 */ +#define EXCEPTION_LSPI 177 /* == INT_LSPI (193) - 16 */ + +HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Handle handle = 0; + uint32_t priority = ~0; + uintptr_t arg = 0; + + if (params) { + priority = params->priority; + arg = params->arg; + } + + /* + * SimpleLink only uses the NWPIC, UDMA, UDMAERR and LSPI interrupts: + */ + __ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum || + INT_UDMAERR == interruptNum || INT_LSPI == interruptNum, + "Unexpected interruptNum: %d\r\n", + interruptNum); + /* + * Priority expected is either: + * INT_PRIORITY_LVL_1, + * or ~0 or 255 (meaning lowest priority) + * ~0 and 255 are meant to be the same as INT_PRIORITY_LVL_7. + * For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1, + * so we pass 6 for those TI drivers passing prio = ~0. + */ + __ASSERT((INT_PRIORITY_LVL_1 == priority) || + (0xff == (priority & 0xff)), + "Expected priority: 0x%x or 0x%x, got: 0x%x\r\n", + INT_PRIORITY_LVL_1, 0xff, (unsigned int)priority); + + switch(interruptNum) { + case INT_UDMA: + sl_UDMA_cb.cb = hwiFxn; + sl_UDMA_cb.arg = arg; + IRQ_CONNECT(EXCEPTION_UDMA, 6, sl_isr, &sl_UDMA_cb, 0); + break; + case INT_UDMAERR: + sl_UDMAERR_cb.cb = hwiFxn; + sl_UDMAERR_cb.arg = arg; + IRQ_CONNECT(EXCEPTION_UDMAERR, 6, sl_isr, &sl_UDMAERR_cb, 0); + break; + case INT_NWPIC: + sl_NWPIC_cb.cb = hwiFxn; + sl_NWPIC_cb.arg = arg; + IRQ_CONNECT(EXCEPTION_NWPIC, 1, sl_isr, &sl_NWPIC_cb, 0); + break; + case INT_LSPI: + sl_LSPI_cb.cb = hwiFxn; + sl_LSPI_cb.arg = arg; + IRQ_CONNECT(EXCEPTION_LSPI, 6, sl_isr, &sl_LSPI_cb, 0); + break; + default: + return(handle); + } + irq_enable(interruptNum - 16); + + return (HwiP_Handle)interruptNum; +} + +/* Can't actually de-register an interrupt in Zephyr, so just disable: */ +void HwiP_delete(HwiP_Handle handle) +{ + int interruptNum = (int)handle; + + __ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum || + INT_UDMAERR == interruptNum || INT_LSPI == interruptNum, + "Unexpected interruptNum: %d\r\n", + interruptNum); + + irq_disable(interruptNum - 16); +} +#elif defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) || defined(CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7) +/* INT_PENDSV is already taken by Zephyr, so let's use INT_SWEV0 to support + * SwiP since this line is usually unused. Change this to a different + * interrupt if desired. + */ +int HwiP_swiPIntNum = INT_SWEV0; + +typedef struct _HwiP_Obj { + uint32_t intNum; + struct sl_isr_args * cb; +} HwiP_Obj; + +static struct sl_isr_args sl_OSC_COMB_cb = {NULL, 0}; +static struct sl_isr_args sl_AUX_COMB_cb = {NULL, 0}; +static struct sl_isr_args sl_RFC_HW_COMB_cb = {NULL, 0}; +static struct sl_isr_args sl_RFC_CPE_0_cb = {NULL, 0}; +static struct sl_isr_args sl_SWEV0_cb = {NULL, 0}; +static struct sl_isr_args sl_AUX_SWEV0_cb = {NULL, 0}; +static struct sl_isr_args sl_AUX_SWEV1_cb = {NULL, 0}; + +/* + * ======== HwiP_construct ======== + */ +HwiP_Handle HwiP_construct(HwiP_Struct *handle, int interruptNum, + HwiP_Fxn hwiFxn, HwiP_Params *params) +{ + HwiP_Obj *obj = (HwiP_Obj *)handle; + uintptr_t arg = 0; + uint8_t priority = INT_PRI_LEVEL7; /* default to lowest priority */ + bool enable = true; + + if (handle == NULL) { + return NULL; + } + + if (params) { + priority = params->priority; + arg = params->arg; + enable = params->enableInt; + } + + /* + * Currently only support INT_OSC_COMB, INT_AUX_COMB, INT_SWEV0 + */ + __ASSERT(INT_OSC_COMB == interruptNum || INT_AUX_COMB == interruptNum + || INT_RFC_HW_COMB == interruptNum + || INT_RFC_CPE_0 == interruptNum + || INT_SWEV0 == interruptNum + || INT_AUX_SWEV0 == interruptNum + || INT_AUX_SWEV1 == interruptNum, + "Unexpected interruptNum: %d\r\n", + interruptNum); + + /* + * Priority expected is either: + * INT_PRI_LEVEL1 to INT_PRI_LEVEL7, + * or ~0 or 255 (meaning lowest priority) + * ~0 and 255 are meant to be the same as INT_PRI_LEVEL7. + * For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1 + * to reserve INT_PRI_LEVEL0, + * so we pass 6 for those TI drivers passing prio = ~0. + */ + __ASSERT((INT_PRI_LEVEL7 == priority) || + (INT_PRI_LEVEL6 == priority) || + (INT_PRI_LEVEL5 == priority) || + (INT_PRI_LEVEL4 == priority) || + (INT_PRI_LEVEL3 == priority) || + (INT_PRI_LEVEL2 == priority) || + (INT_PRI_LEVEL1 == priority) || + (0xFF == priority), + "Unexpected priority level, got: 0x%x\r\n", + (unsigned int)priority); + + if (0xFF == priority) { + priority = INT_PRI_LEVEL7; + } + + /* The priority for IRQ_CONNECT is encoded in the top 3 bits */ + priority = (priority >> 5) - 1; + + switch(interruptNum) { + case INT_RFC_CPE_0: + sl_RFC_CPE_0_cb.cb = hwiFxn; + sl_RFC_CPE_0_cb.arg = arg; + obj->cb = &sl_RFC_CPE_0_cb; + irq_connect_dynamic(INT_RFC_CPE_0 - 16, priority, sl_isr, &sl_RFC_CPE_0_cb, 0); + break; + case INT_RFC_HW_COMB: + sl_RFC_HW_COMB_cb.cb = hwiFxn; + sl_RFC_HW_COMB_cb.arg = arg; + obj->cb = &sl_RFC_HW_COMB_cb; + irq_connect_dynamic(INT_RFC_HW_COMB - 16, priority, sl_isr, &sl_RFC_HW_COMB_cb, 0); + break; + case INT_OSC_COMB: + sl_OSC_COMB_cb.cb = hwiFxn; + sl_OSC_COMB_cb.arg = arg; + obj->cb = &sl_OSC_COMB_cb; + irq_connect_dynamic(INT_OSC_COMB - 16, priority, sl_isr, &sl_OSC_COMB_cb, 0); + break; + case INT_AUX_COMB: + sl_AUX_COMB_cb.cb = hwiFxn; + sl_AUX_COMB_cb.arg = arg; + obj->cb = &sl_AUX_COMB_cb; + irq_connect_dynamic(INT_AUX_COMB - 16, priority, sl_isr, &sl_AUX_COMB_cb, 0); + break; + case INT_SWEV0: + sl_SWEV0_cb.cb = hwiFxn; + sl_SWEV0_cb.arg = arg; + obj->cb = &sl_SWEV0_cb; + irq_connect_dynamic(INT_SWEV0 - 16, priority, sl_isr, &sl_SWEV0_cb, 0); + break; + case INT_AUX_SWEV0: + sl_AUX_SWEV0_cb.cb = hwiFxn; + sl_AUX_SWEV0_cb.arg = arg; + obj->cb = &sl_AUX_SWEV0_cb; + irq_connect_dynamic(INT_AUX_SWEV0 - 16, priority, sl_isr, &sl_AUX_SWEV0_cb, 0); + break; + case INT_AUX_SWEV1: + sl_AUX_SWEV1_cb.cb = hwiFxn; + sl_AUX_SWEV1_cb.arg = arg; + obj->cb = &sl_AUX_SWEV1_cb; + irq_connect_dynamic(INT_AUX_SWEV1 - 16, priority, sl_isr, &sl_AUX_SWEV1_cb, 0); + break; + default: + return(NULL); + } + if (enable) + { + irq_enable(interruptNum - 16); + } + + obj->intNum = interruptNum; + + return (HwiP_Handle)handle; +} +#endif + +void HwiP_Params_init(HwiP_Params *params) +{ + params->arg = 0; + params->priority = ~0; + params->enableInt = true; +} + +/* Zephyr has no functions for clearing an interrupt, so use driverlib: */ +void HwiP_clearInterrupt(int interruptNum) +{ +#if defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) || defined(CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7) + IntPendClear((unsigned long)interruptNum); +#elif defined(CONFIG_SOC_SERIES_CC32XX) + MAP_IntPendClear((unsigned long)interruptNum); +#endif +} + +void HwiP_enableInterrupt(int interruptNum) +{ + irq_enable(interruptNum - 16); +} + +void HwiP_disableInterrupt(int interruptNum) +{ + irq_disable(interruptNum - 16); +} + +uintptr_t HwiP_disable(void) +{ + uintptr_t key; + + key = irq_lock(); + + return (key); +} + +void HwiP_restore(uintptr_t key) +{ + irq_unlock(key); +} + +#if defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) || defined(CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7) +void HwiP_post(int interruptNum) +{ + IntPendSet((uint32_t)interruptNum); +} + +void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP; + + uintptr_t key = HwiP_disable(); + + obj->cb->cb = fxn; + obj->cb->arg = arg; + + HwiP_restore(key); +} + +void HwiP_destruct(HwiP_Struct *hwiP) +{ + HwiP_Obj *obj = (HwiP_Obj *)hwiP->data; + + int interruptNum = obj->intNum; + + irq_disable(interruptNum - 16); + + obj->cb->cb = NULL; + obj->cb->arg = (uintptr_t)NULL; + obj->cb = NULL; +} +#endif diff --git a/simplelink_lpf2/kernel/zephyr/dpl/MutexP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/MutexP_zephyr.c new file mode 100644 index 00000000..82e6c999 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/MutexP_zephyr.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/* + * Zephyr kernel object pools: + * + * This bit of code enables the simplelink host driver, which assumes dynamic + * allocation of kernel objects (semaphores, mutexes, hwis), to be + * more easily ported to Zephyr (which supports static allocation). + * + * It leverages the Zephyr memory slab, enabling us to define a mutex object + * pool for use by the SimpleLink host driver. + */ + +/* Define a Mutex pool: */ +#define DPL_MAX_MUTEXES 4 /* From simplelink driver code inspection */ +K_MEM_SLAB_DEFINE(mutex_slab, sizeof(struct k_mutex), DPL_MAX_MUTEXES,\ + MEM_ALIGN); + +static struct k_mutex *dpl_mutex_pool_alloc() +{ + struct k_mutex *mutex_ptr = NULL; + + if (k_mem_slab_alloc(&mutex_slab, (void **)&mutex_ptr, + K_NO_WAIT) < 0) { + /* + * We assert, as this is a logic error, due to a change in # + * of mutexes needed by the simplelink driver. In that case, + * the mutex pool must be increased programmatically to match. + */ + __ASSERT(0, "Increase size of DPL mutex pool"); + } + return mutex_ptr; +} + +static MutexP_Status dpl_mutex_pool_free(struct k_mutex *mutex) +{ + k_mem_slab_free(&mutex_slab, (void **)&mutex); + return MutexP_OK; +} + +MutexP_Handle MutexP_create(MutexP_Params *params) +{ + struct k_mutex *mutex; + + ARG_UNUSED(params); + + mutex = dpl_mutex_pool_alloc(); + __ASSERT(mutex, "MutexP_create failed\r\n"); + + if (mutex) { + k_mutex_init(mutex); + } + return ((MutexP_Handle)mutex); +} + +void MutexP_delete(MutexP_Handle handle) +{ + /* No way in Zephyr to "reset" the lock, so just re-init: */ + k_mutex_init((struct k_mutex *)handle); + + dpl_mutex_pool_free((struct k_mutex *)handle); +} + +uintptr_t MutexP_lock(MutexP_Handle handle) +{ + unsigned int key = 0; + int retval; + + retval = k_mutex_lock((struct k_mutex *)handle, K_FOREVER); + __ASSERT(retval == 0, + "MutexP_lock: retval: %d\r\n", retval); + + return ((uintptr_t)key); +} + +void MutexP_Params_init(MutexP_Params *params) +{ + params->callback = NULL; +} + +void MutexP_unlock(MutexP_Handle handle, uintptr_t key) +{ + ARG_UNUSED(key); + + k_mutex_unlock((struct k_mutex *)handle); +} diff --git a/simplelink_lpf2/kernel/zephyr/dpl/QueueP.h b/simplelink_lpf2/kernel/zephyr/dpl/QueueP.h new file mode 100644 index 00000000..276c3d38 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/QueueP.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP.h ======== + */ + +typedef struct _QueueP_Elem { + struct _QueueP_Elem *volatile next; + struct _QueueP_Elem *volatile prev; +} QueueP_Elem; + +typedef struct _QueueP_Obj { + QueueP_Elem elem; +} QueueP_Obj; + +typedef QueueP_Obj *QueueP_Handle; + +void QueueP_init(QueueP_Obj *obj); +uintptr_t QueueP_head(QueueP_Obj *obj); +uintptr_t QueueP_next(QueueP_Elem *qelem); +uintptr_t QueueP_prev(QueueP_Elem *qelem); +uintptr_t QueueP_get(QueueP_Obj *obj); +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem); +void QueueP_remove(QueueP_Elem *qelem) ; +bool QueueP_empty(QueueP_Obj *obj); diff --git a/simplelink_lpf2/kernel/zephyr/dpl/QueueP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/QueueP_zephyr.c new file mode 100644 index 00000000..6cd04056 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/QueueP_zephyr.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== QueueP_zephyr.c ======== + */ + +#include +#include "QueueP.h" + +/* + * ======== QueueP_init ======== + */ +void QueueP_init(QueueP_Obj *obj) +{ + obj->elem.next = obj->elem.prev = &(obj->elem); +} + +/* + * ======== QueueP_empty ======== + */ +bool QueueP_empty(QueueP_Obj *obj) +{ + return (obj->elem.next == &(obj->elem)); +} + +/* + * ======== QueueP_get ======== + */ +uintptr_t QueueP_get(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.next; + + obj->elem.next = elem->next; + elem->next->prev = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); + +} + +/* + * ======== QueueP_getTail ======== + */ +uintptr_t QueueP_getTail(QueueP_Obj *obj) +{ + QueueP_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = obj->elem.prev; + + obj->elem.prev = elem->prev; + elem->prev->next = &(obj->elem); + + HwiP_restore(key); + + return ((uintptr_t)elem); + +} + +/* + * ======== QueueP_head ======== + */ +uintptr_t QueueP_head(QueueP_Obj *obj) +{ + return ((uintptr_t)(obj->elem.next)); +} + +/* + * ======== elemClear ======== + */ +void QueueP_elemClear(QueueP_Elem *qelem) +{ + qelem->next = qelem->prev = qelem; +} + +/* + * ======== insert ======== + */ +void QueueP_insert(QueueP_Elem *qelem, QueueP_Elem *elem) +{ + QueueP_put((QueueP_Obj *)qelem, elem); +} + +/* + * ======== next ======== + */ +uintptr_t QueueP_next(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->next); +} + +/* + * ======== QueueP_prev ======== + */ +uintptr_t QueueP_prev(QueueP_Elem *qelem) +{ + return ((uintptr_t)qelem->prev); +} + +/* + * ======== QueueP_put ======== + */ +void QueueP_put(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = &(obj->elem); + elem->prev = obj->elem.prev; + obj->elem.prev->next = elem; + obj->elem.prev = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_putHead ======== + */ +void QueueP_putHead(QueueP_Obj *obj, QueueP_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->prev = &(obj->elem); + elem->next = obj->elem.next; + obj->elem.next->prev = elem; + obj->elem.next = elem; + + HwiP_restore(key); +} + +/* + * ======== QueueP_remove ======== + */ +void QueueP_remove(QueueP_Elem *qelem) +{ +#if defined(__IAR_SYSTEMS_ICC__) + QueueP_Elem *temp; + temp = qelem->next; + qelem->prev->next = temp; + temp = qelem->prev; + qelem->next->prev = temp; +#else + qelem->prev->next = qelem->next; + qelem->next->prev = qelem->prev; +#endif +} + +/* + * ======== isQueued ======== + */ +bool QueueP_isQueued(QueueP_Elem *qelem) +{ + if ((qelem->prev == qelem) && (qelem->next == qelem)) { + return (false); + } + else { + return (true); + } +} diff --git a/simplelink_lpf2/kernel/zephyr/dpl/SemaphoreP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/SemaphoreP_zephyr.c new file mode 100644 index 00000000..e5640682 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/SemaphoreP_zephyr.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/* + * Zephyr kernel object pools: + * + * This bit of code enables the simplelink host driver, which assumes dynamic + * allocation of kernel objects (semaphores, mutexes, hwis), to be + * more easily ported to Zephyr (which supports static allocation). + * + * It leverages the Zephyr memory slab, enabling us to define a semaphore + * object pool for use by the SimpleLink host driver. + */ +#define DPL_MAX_SEMAPHORES 14 /* (user.h:MAX_CONCURRENT_ACTIONS+4) = 14 */ +K_MEM_SLAB_DEFINE(sem_slab, sizeof(struct k_sem), DPL_MAX_SEMAPHORES,\ + MEM_ALIGN); + +static struct k_sem *dpl_sem_pool_alloc() +{ + struct k_sem *sem_ptr = NULL; + + if (k_mem_slab_alloc(&sem_slab, (void **)&sem_ptr, K_NO_WAIT) < 0) { + /* + * We assert, as this is a logic error, due to a change in # + * of semaphores needed by the simplelink driver. In that case, + * the sem pool must be increased programmatically to match. + */ + __ASSERT(0, "Increase size of DPL semaphore pool"); + } + return sem_ptr; +} + +static SemaphoreP_Status dpl_sem_pool_free(struct k_sem *sem) +{ + k_mem_slab_free(&sem_slab, (void **)&sem); + + return SemaphoreP_OK; +} + +/* timeout comes in and out in ticks */ +static k_timeout_t dpl_convert_timeout(uint32_t timeout) +{ + switch(timeout) { + case SemaphoreP_NO_WAIT: + return K_NO_WAIT; + case SemaphoreP_WAIT_FOREVER: + return K_FOREVER; + default: + return K_TICKS(timeout); + } +} + + +SemaphoreP_Handle SemaphoreP_create(unsigned int count, + SemaphoreP_Params *params) +{ + unsigned int limit = UINT_MAX; + struct k_sem *sem; + + if (params) { + limit = (params->mode == SemaphoreP_Mode_BINARY) ? + 1 : UINT_MAX; + } + + sem = dpl_sem_pool_alloc(); + if (sem) { + k_sem_init(sem, count, limit); + } + + return (SemaphoreP_Handle)sem; +} + +SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) +{ + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_create(count, ¶ms)); +} + + +void SemaphoreP_delete(SemaphoreP_Handle handle) +{ + k_sem_reset((struct k_sem *)handle); + + (void)dpl_sem_pool_free((struct k_sem *)handle); +} + +void SemaphoreP_Params_init(SemaphoreP_Params *params) +{ + params->mode = SemaphoreP_Mode_COUNTING; + params->callback = NULL; +} + +/* + * The SimpleLink driver calls this function with a timeout of 0 to "clear" + * the SyncObject, rather than calling dpl_SyncObjClear() directly. + * See: /source/ti/drivers/net/wifi/source/driver.h + * #define SL_DRV_SYNC_OBJ_CLEAR(pObj) + * (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT); + * + * So, we claim (via simplelink driver code inspection), that SyncObjWait + * will *only* be called with timeout == 0 if the intention is to clear the + * semaphore: in that case, we just call k_sem_reset. + */ +SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) +{ + int retval; + + if (0 == timeout) { + k_sem_reset((struct k_sem *)handle); + retval = SemaphoreP_OK; + } else { + retval = k_sem_take((struct k_sem *)handle, + dpl_convert_timeout(timeout)); + __ASSERT_NO_MSG(retval != -EBUSY); + retval = (retval >= 0) ? SemaphoreP_OK : SemaphoreP_TIMEOUT; + } + return retval; +} + +void SemaphoreP_post(SemaphoreP_Handle handle) +{ + k_sem_give((struct k_sem *)handle); +} + +SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, + unsigned int count, SemaphoreP_Params *params) +{ + unsigned int limit = UINT_MAX; + struct k_sem *sem; + + if (params) { + limit = (params->mode == SemaphoreP_Mode_BINARY) ? + 1 : UINT_MAX; + } + + sem = (struct k_sem *)handle; + if (sem) { + k_sem_init(sem, count, limit); + } + + return (SemaphoreP_Handle)sem; +} + +SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, unsigned int count) { + SemaphoreP_Params params; + + SemaphoreP_Params_init(¶ms); + params.mode = SemaphoreP_Mode_BINARY; + + return (SemaphoreP_construct(handle, count, ¶ms)); +} + +void SemaphoreP_destruct(SemaphoreP_Struct *semP) { + struct k_sem *sem; + + sem = (struct k_sem *)semP->data; + if (sem) { + k_sem_reset(sem); + } +} diff --git a/simplelink_lpf2/kernel/zephyr/dpl/SwiP_zephyr.c b/simplelink_lpf2/kernel/zephyr/dpl/SwiP_zephyr.c new file mode 100644 index 00000000..213441c9 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/SwiP_zephyr.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2019, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +#include "QueueP.h" + +/* Lowest priority interrupt */ +#define INT_PRI_LEVEL7 0xe0 + +#define NUMPRI 4 + +typedef enum { + SwiP_State_Idle = 0, + SwiP_State_Posted, + SwiP_State_Running, + SwiP_State_Interrupted +} SwiP_State; + +typedef uint32_t SwiP_LockState; + +enum { + SwiP_LockState_Locked, + SwiP_LockState_Unlocked +}; + +typedef struct SwiP_Obj { + QueueP_Elem elem; + QueueP_Handle readyList; + SwiP_Params params; + SwiP_Fxn fxn; + uint32_t trigger; + uint32_t state; +} SwiP_Obj; + +static void SwiP_handleHwi(); + +static const SwiP_Params SwiP_defaultParams = { + .arg0 = (uintptr_t) NULL, + .arg1 = (uintptr_t) NULL, + .priority = ~0, /* max priority */ + .trigger = 0, +}; + +static volatile int SwiP_readyMask; +static volatile SwiP_LockState SwiP_lockState; +static volatile uint32_t SwiP_currentTrigger; +static volatile bool SwiP_schedulerRunning; +static volatile bool SwiP_initialized = false; +static HwiP_Struct SwiP_hwiStruct; +static QueueP_Obj SwiP_readyList[NUMPRI]; + +/* don't call with n == 0 */ +static int maxbit(int n) +{ + int mask = 1 << (NUMPRI - 1); + int max = NUMPRI - 1; + + while (mask) { + if (n & mask) { + return max; + } + max--; + mask >>= 1; + } + + return 0; +} + +/* + * ======== SwiP_Params_init ======== + */ +void SwiP_Params_init(SwiP_Params *params) +{ + /* structure copy */ + *params = SwiP_defaultParams; +} + +/* + * ======== SwiP_construct ======== + */ +SwiP_Handle SwiP_construct(SwiP_Struct *handle, SwiP_Fxn swiFxn, + SwiP_Params *params) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + HwiP_Params hwiParams; + uintptr_t hwiKey; + uint32_t priority; + int i; + + if (handle != NULL) { + hwiKey = HwiP_disable(); + + if (SwiP_initialized == false) { + for (i = 0; i < NUMPRI; i++) { + QueueP_init(&SwiP_readyList[i]); + } + SwiP_readyMask = 0; + SwiP_currentTrigger = 0; + SwiP_lockState = SwiP_LockState_Unlocked; + SwiP_schedulerRunning = false; + + HwiP_Params_init(&hwiParams); + hwiParams.priority = INT_PRI_LEVEL7; // use the lowest priority + HwiP_construct(&SwiP_hwiStruct, HwiP_swiPIntNum, SwiP_handleHwi, + &hwiParams); + + SwiP_initialized = true; + } + + HwiP_restore(hwiKey); + + if (params == NULL) { + params = (SwiP_Params *)&SwiP_defaultParams; + } + + if (params->priority == (~0)) { + priority = NUMPRI - 1; + } + else { + priority = params->priority; + } + + if (priority >= NUMPRI) { + return NULL; + } + else { + QueueP_init((QueueP_Obj *)&swi->elem); + swi->params = *params; + swi->params.priority = priority; + swi->fxn = swiFxn; + swi->trigger = swi->params.trigger; + swi->state = SwiP_State_Idle; + swi->readyList = &SwiP_readyList[priority]; + } + } + + return ((SwiP_Handle)swi); +} + +/* + * ======== SwiP_destruct ======== + */ +void SwiP_destruct(SwiP_Struct *handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* if on SwiP_readyList, remove it */ + QueueP_remove(&swi->elem); + if (QueueP_empty(swi->readyList)) { + SwiP_readyMask &= ~(1 << swi->params.priority); + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_disable ======== + */ +uintptr_t SwiP_disable(void) +{ + uintptr_t previousHwiState = HwiP_disable(); + + SwiP_LockState previousLockState = SwiP_lockState; + SwiP_lockState = SwiP_LockState_Locked; + + HwiP_restore(previousHwiState); + + return previousLockState; +} + +/* + * This is a non-preemptive fixed-priority scheduler implementation. + * It runs with interrupts disabled, but enables them for each swi. + */ +void SwiP_dispatch(uintptr_t hwiKey) +{ + SwiP_Obj *swi; + int maxpri; + + while (SwiP_readyMask && (SwiP_lockState == SwiP_LockState_Unlocked)) { + maxpri = maxbit(SwiP_readyMask); + swi = (SwiP_Obj *)QueueP_get(&SwiP_readyList[maxpri]); + + if (QueueP_empty(&SwiP_readyList[maxpri])) { + SwiP_readyMask &= ~(1 << maxpri); + } + + /* + * Prepare the swi for execution. The trigger has to be saved + * because the swi might re-post itself with another trigger value. + */ + swi->state = SwiP_State_Running; + SwiP_currentTrigger = swi->trigger; + swi->trigger = swi->params.trigger; + + /* run the swi with interrupts enabled */ + HwiP_restore(hwiKey); + swi->fxn(swi->params.arg0, swi->params.arg1); + hwiKey = HwiP_disable(); + + /* If the swi didn't get re-posted, set it to idle now */ + if (swi->state == SwiP_State_Running) { + swi->state = SwiP_State_Idle; + } + } + + /* Scheduler was set to running immediately after posting the interrupt */ + SwiP_schedulerRunning = false; +} + +static void SwiP_handleHwi() +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_dispatch(hwiKey); + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_getTrigger ======== + */ +uint32_t SwiP_getTrigger() +{ + return (SwiP_currentTrigger); +} + + +/* + * ======== SwiP_or ======== + */ +void SwiP_or(SwiP_Handle handle, uint32_t mask) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + swi->trigger |= mask; + + HwiP_restore(hwiKey); + SwiP_post(swi); +} + +/* + * ======== SwiP_post ======== + */ +void SwiP_post(SwiP_Handle handle) +{ + SwiP_Obj *swi = (SwiP_Obj *)handle; + uintptr_t hwiKey = HwiP_disable(); + + /* (Re-)post an swi only once */ + if (swi->state != SwiP_State_Posted) { + swi->state = SwiP_State_Posted; + + QueueP_put(&SwiP_readyList[swi->params.priority], + (QueueP_Elem *)&swi->elem); + SwiP_readyMask |= 1 << swi->params.priority; + } + + /* Activate the scheduler when not already running */ + if ((SwiP_schedulerRunning == false) && + (SwiP_lockState == SwiP_LockState_Unlocked)) { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} + +/* + * ======== SwiP_restore ======== + */ +void SwiP_restore(uintptr_t key) +{ + uintptr_t hwiKey = HwiP_disable(); + + SwiP_lockState = key; + + /* Determine whether the scheduler needs to run */ + if (SwiP_readyMask && (key == SwiP_LockState_Unlocked) && + (SwiP_schedulerRunning == false)) { + HwiP_post(HwiP_swiPIntNum); + /* Set the scheduler into running state to avoid double posts */ + SwiP_schedulerRunning = true; + } + + HwiP_restore(hwiKey); +} diff --git a/simplelink_lpf2/kernel/zephyr/dpl/dpl.h b/simplelink_lpf2/kernel/zephyr/dpl/dpl.h new file mode 100644 index 00000000..7ebacce6 --- /dev/null +++ b/simplelink_lpf2/kernel/zephyr/dpl/dpl.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2017, Texas Instruments Incorporated + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define MEM_ALIGN (sizeof(uint32_t)) diff --git a/simplelink_lpf2/simplelink_lpf2.sh b/simplelink_lpf2/simplelink_lpf2.sh new file mode 100755 index 00000000..cd83edde --- /dev/null +++ b/simplelink_lpf2/simplelink_lpf2.sh @@ -0,0 +1,18 @@ +#!/bin/sh + +# A simple script to copy relevant files from TI Simplelink F2 SDK. + +SOURCE=$1 +OUTPUT=$2 + +mkdir -p ${OUTPUT}/source/ti +rsync --include='*/' --include='*.c' --include='*.h' --exclude='*' -amv ${SOURCE}/source/ti/drivers $OUTPUT/source/ti/ + +rsync --include='*/' --include='*.c' --include='*.h' --exclude='*' -amv ${SOURCE}/source/ti/log $OUTPUT/source/ti/ + +mkdir -p ${OUTPUT}/source/ti/devices +rsync --include='*/' --include='*.c' --include='*.h' --exclude='*' -amv ${SOURCE}/source/ti/devices/DeviceFamily.h $OUTPUT/source/ti/devices/ +rsync --include='*/' --include='*.c' --include='*.h' --exclude='*' -amv ${SOURCE}/source/ti/devices/cc13x2x7_cc26x2x7 $OUTPUT/source/ti/devices/ + +echo "Please make Zephyr specific changes to source/ti/devices/cc13x2x7_cc26x2x7/startup_files/ccfg.c" +echo "Please make Zephyr specific changes to source/ti/drivers/power/PowerCC26X2.c" diff --git a/simplelink_lpf2/source/ti/devices/DeviceFamily.h b/simplelink_lpf2/source/ti/devices/DeviceFamily.h new file mode 100644 index 00000000..1c8f3a5e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/DeviceFamily.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DeviceFamily.h + * + * @brief Infrastructure to select correct driverlib path and identify devices + * + * This module enables the selection of the correct driverlib path for the current + * device. It also facilitates the use of per-device conditional compilation + * to enable minor variations in drivers between devices. + * + * In order to use this functionality, DeviceFamily_XYZ must be defined as one of + * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines + * are set based on DeviceFamily_XYZ. + */ + +#ifndef ti_devices_DeviceFamily__include +#define ti_devices_DeviceFamily__include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * DeviceFamily_ID_XYZ values. + * + * DeviceFamily_ID may be used in the preprocessor for conditional compilation. + * DeviceFamily_ID is set to one of these values based on the top level + * DeviceFamily_XYZ define. + */ +#define DeviceFamily_ID_CC13X0 1 +#define DeviceFamily_ID_CC26X0 2 +#define DeviceFamily_ID_CC26X0R2 3 +#define DeviceFamily_ID_CC13X2 4 +#define DeviceFamily_ID_CC26X2 5 +#define DeviceFamily_ID_CC3200 6 +#define DeviceFamily_ID_CC3220 7 +#define DeviceFamily_ID_CC13X1 8 +#define DeviceFamily_ID_CC26X1 9 +#define DeviceFamily_ID_CC13X2X7 10 +#define DeviceFamily_ID_CC26X2X7 11 +#define DeviceFamily_ID_CC13X1_CC26X1 12 +#define DeviceFamily_ID_CC13X2_CC26X2 13 +#define DeviceFamily_ID_CC13X2X7_CC26X2X7 14 +#define DeviceFamily_ID_CC13X4_CC26X4 15 +#define DeviceFamily_ID_CC13X4 16 +#define DeviceFamily_ID_CC26X4 17 +#define DeviceFamily_ID_CC26X3 18 +#define DeviceFamily_ID_CC23X0R5 19 +#define DeviceFamily_ID_CC23X0R2 20 +#define DeviceFamily_ID_CC27XX 21 +#define DeviceFamily_ID_CC35XX 22 +#define DeviceFamily_ID_CC33XX 23 +#define DeviceFamily_ID_CC23X0R22 24 + +/* + * DeviceFamily_PARENT_XYZ values. + * + * DeviceFamily_PARENT may be used in the preprocessor for conditional + * compilation. DeviceFamily_PARENT is set to one of these values based + * on the top-level DeviceFamily_XYZ define. + */ +#define DeviceFamily_PARENT_CC13X0_CC26X0 1 +#define DeviceFamily_PARENT_CC13X2_CC26X2 2 +#define DeviceFamily_PARENT_CC13X1_CC26X1 3 +#define DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 4 +#define DeviceFamily_PARENT_CC32XX 5 +#define DeviceFamily_PARENT_CC23X0 6 +#define DeviceFamily_PARENT_CC27XX 7 +#define DeviceFamily_PARENT_CC35XX 8 + +/* + * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and + * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. + * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If + * multiple DeviceFamily_XYZ are defined, the first one encountered is used. + */ +#if defined(DeviceFamily_CC13X0) + #define DeviceFamily_ID DeviceFamily_ID_CC13X0 + #define DeviceFamily_DIRECTORY cc13x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC13X1) + #define DeviceFamily_ID DeviceFamily_ID_CC13X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC13X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X4) + #define DeviceFamily_ID DeviceFamily_ID_CC13X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC26X0) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0 + #define DeviceFamily_DIRECTORY cc26x0 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 + #define DeviceFamily_DIRECTORY cc26x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 + +#elif defined(DeviceFamily_CC26X1) + #define DeviceFamily_ID DeviceFamily_ID_CC26X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC26X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC26X3) + /* The CC2653 is very similar to CC26X4 from a software point of view, + * so we use the same directory and parent defines. + */ + #define DeviceFamily_ID DeviceFamily_ID_CC26X3 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC26X4) + #define DeviceFamily_ID DeviceFamily_ID_CC26X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC23X0R5) + #define DeviceFamily_ID DeviceFamily_ID_CC23X0R5 + #define DeviceFamily_DIRECTORY cc23x0r5 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC23X0 + +#elif defined(DeviceFamily_CC23X0R2) + #define DeviceFamily_ID DeviceFamily_ID_CC23X0R2 + #define DeviceFamily_DIRECTORY cc23x0r2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC23X0 + +#elif defined(DeviceFamily_CC27XX) + #define DeviceFamily_ID DeviceFamily_ID_CC27XX + #define DeviceFamily_DIRECTORY cc27xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC27XX + +#elif defined(DeviceFamily_CC13X1_CC26X1) + #define DeviceFamily_ID DeviceFamily_ID_CC13X1_CC26X1 + #define DeviceFamily_DIRECTORY cc13x1_cc26x1 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X1_CC26X1 + +#elif defined(DeviceFamily_CC13X2_CC26X2) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2_CC26X2 + #define DeviceFamily_DIRECTORY cc13x2_cc26x2 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X2X7_CC26X2X7) + #define DeviceFamily_ID DeviceFamily_ID_CC13X2X7_CC26X2X7 + #define DeviceFamily_DIRECTORY cc13x2x7_cc26x2x7 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 + +#elif defined(DeviceFamily_CC13X4_CC26X4) + #define DeviceFamily_ID DeviceFamily_ID_CC13X4_CC26X4 + #define DeviceFamily_DIRECTORY cc13x4_cc26x4 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 + +#elif defined(DeviceFamily_CC3200) + #define DeviceFamily_ID DeviceFamily_ID_CC3200 + #define DeviceFamily_DIRECTORY cc32xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC32XX + +#elif defined(DeviceFamily_CC3220) + #define DeviceFamily_ID DeviceFamily_ID_CC3220 + #define DeviceFamily_DIRECTORY cc32xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC32XX + +#elif defined(DeviceFamily_CC35XX) + #define DeviceFamily_ID DeviceFamily_ID_CC35XX + #define DeviceFamily_DIRECTORY cc35xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC35XX + +#elif defined(DeviceFamily_CC33XX) + #define DeviceFamily_ID DeviceFamily_ID_CC33XX + #define DeviceFamily_DIRECTORY cc33xx + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC35XX + +#elif defined(DeviceFamily_CC23X0R22) + #define DeviceFamily_ID DeviceFamily_ID_CC23X0R22 + #define DeviceFamily_DIRECTORY cc23x0r5 + #define DeviceFamily_PARENT DeviceFamily_PARENT_CC23X0 + +#else + #error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!" +#endif + +/* Ensure that only one DeviceFamily was specified */ +#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X1) + defined(DeviceFamily_CC13X2) + \ + defined(DeviceFamily_CC13X2X7) + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) + \ + defined(DeviceFamily_CC26X1) + defined(DeviceFamily_CC26X2) + defined(DeviceFamily_CC26X2X7) + \ + defined(DeviceFamily_CC26X3) + defined(DeviceFamily_CC26X4) + defined(DeviceFamily_CC13X4) + \ + defined(DeviceFamily_CC23X0R5) + defined(DeviceFamily_CC23X0R2) + defined(DeviceFamily_CC27XX) + \ + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) + defined(DeviceFamily_CC35XX) + \ + defined(DeviceFamily_CC33XX) + defined(DeviceFamily_CC23X0R22)) > 1 + #error More then one DeviceFamily has been defined! +#endif + +/*! + * @brief Macro to include correct driverlib path. + * + * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined + * first. + * + * @param x A token containing the path of the file to include based on + * the root device folder. The preceding forward slash must be + * omitted. For example: + * - #include DeviceFamily_constructPath(inc/hw_memmap.h) + * - #include DeviceFamily_constructPath(driverlib/uart.h) + * + * @return Returns an include path. + * + */ +#define DeviceFamily_constructPath(x) + +#ifdef __cplusplus +} +#endif + +#endif /* ti_devices_DeviceFamily__include */ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.c new file mode 100644 index 00000000..fa45a1d9 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.c @@ -0,0 +1,37 @@ +/****************************************************************************** +* Filename: adi.c +* +* Description: Driver for the ADI interface +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "adi.h" diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.h new file mode 100644 index 00000000..d110f648 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi.h @@ -0,0 +1,789 @@ +/****************************************************************************** +* Filename: adi.h +* +* Description: Defines and prototypes for the ADI master interface. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup adi_api +//! @{ +// +//***************************************************************************** + +#ifndef __ADI_H__ +#define __ADI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_adi.h" +#include "debug.h" +#include "ddi.h" + +//***************************************************************************** +// +// Number of registers in the ADI slave +// +//***************************************************************************** +#define ADI_SLAVE_REGS 16 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an ADI base address. +//! +//! This function determines if an ADI port base address is valid. +//! +//! \param ui32Base is the base address of the ADI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +ADIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || + ui32Base == AUX_ADI4_BASE); +} +#endif + + + + + +//***************************************************************************** +// +//! \brief Write an 8 bit value to a register in an ADI slave. +//! +//! This function will write a value to a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16, or 32 bit +//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly +//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses +//! for the registers and values being written to the registers will be +//! truncated according to this access scheme. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui8Val is the 8 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI16RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREGB(ui32Base + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Write a 16 bit value to 2 registers in the ADI slave. +//! +//! This function will write a value to 2 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui16Val is the 16 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI32RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint16_t ui16Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to 4 registers in the ADI slave. +//! +//! This function will write a value to 4 consecutive registers in the analog +//! domain. The access to the registers in the analog domain is either 8, 16 +//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, +//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, +//! etc. Addresses for the registers and values being written +//! to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \note This operation is write only for the specified register. No +//! previous value of the register will be kept (i.e. this is NOT +//! read-modify-write on the register). +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +//! +//! \sa ADI8RegWrite(), ADI16RegWrite() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Read the value of an 8 bit register in the ADI slave. +//! +//! This function will read an 8 bit register in the analog domain and return +//! the value as the lower 8 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 8 bit register to read. +//! +//! \return Returns the 8 bit value of the analog register in the least +//! significant byte of the \c uint32_t. +//! +//! \sa ADI16RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the register and return the value. + return(HWREGB(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! \brief Read the value in a 16 bit register. +//! +//! This function will read 2 x 8 bit registers in the analog domain and return +//! the value as the lower 16 bits of an \c uint32_t. The access to the +//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can +//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses +//! are always performed on register 0-3 / 4-7, etc. Addresses for the +//! registers and values being written to the registers will be truncated +//! according to this access scheme. +//! +//! \note The byte addressing bit will be ignored, to ensure 16 bit access +//! to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 16 bit register to read. +//! +//! \return Returns the 16 bit value of the 2 analog register in the 2 least +//! significant bytes of the \c uint32_t. +//! +//! \sa ADI8RegRead(), ADI32RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + return(HWREGH(ui32Base + (ui32Reg & 0xFE))); +} + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read 4 x 8 bit registers in the analog domain and return +//! the value as an \c uint32_t. The access to the registers in the analog +//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on +//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on +//! register 0-3 / 4-7, etc. Addresses for the registers and values being +//! written to the registers will be truncated according to this access scheme. +//! +//! \note The byte and half word addressing bits will be ignored, to ensure +//! 32 bit access to the ADI slave. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the 4 analog registers. +//! +//! \sa ADI8RegRead(), ADI16RegRead() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Read the registers and return the value. + return(HWREG(ui32Base + (ui32Reg & 0xFC))); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a single 8 bit ADI register. +//! +//! This function will set bits in a single register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in a specific 8 bit register in the +//! ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +//! +//! \sa ADI16BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Set specific bits in 2 x 8 bit ADI slave registers. +//! +//! This function will set bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 2 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI32BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Set specific bits in 4 x 8 bit ADI slave registers. +//! +//! This function will set bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in 4 consecutive 8 bit registers in the +//! ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsSet(), ADI16BitsSet() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_SET; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in an 8 bit ADI register. +//! +//! This function will clear bits in a register in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in a specific 8 bit register in +//! the ADI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui8Val is the 8 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +//! +//! \sa ADI16BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in two 8 bit ADI register. +//! +//! This function will clear bits in 2 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 2 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui16Val is the 16 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI32BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in four 8 bit ADI register. +//! +//! This function will clear bits in 4 registers in the analog domain. +//! The access to the registers in the analog domain is either 8, 16 or 32 bit +//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access +//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always +//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values +//! being written to the registers will be truncated according to this access +//! scheme. +//! +//! \note This operation is write only for the specified register. +//! This function is used to clear bits in 4 consecutive 8 bit registers in +//! the ADI slave. Only bits in the selected registers are affected by the +//! operation. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is ADI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the registers. +//! +//! \return None +//! +//! \sa ADI8BitsClear(), ADI16BitsClear() +// +//***************************************************************************** +__STATIC_INLINE void +ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_CLR; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. +//! +//! This function allows halfbyte (4 bit) access to the ADI slave registers. +//! The parameter \c bWriteHigh determines whether to write to the lower +//! or higher part of the 8 bit register. +//! +//! Use this function to write any value in the range 0-3 bits aligned on a +//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the +//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by +//! the operation, as the corresponding bit is not set in the \c ui8Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param bWriteHigh defines which part of the register to write in. +//! - \c true: Write upper half byte of register. +//! - \c false: Write lower half byte of register. +//! \param ui8Mask is the mask defining which of the 4 bits that should be +//! overwritten. The mask must be defined in the lower half of the 8 bits of +//! the parameter. +//! \param ui8Val is the value to write. The value must be defined in the lower +//! half of the 8 bits of the parameter. +//! +//! \return None +//! +//! \sa ADI8SetValBit(), ADI16SetValBit +// +//***************************************************************************** +__STATIC_INLINE void +ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint8_t ui8Mask, uint8_t ui8Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui8Val & 0xF0)); + ASSERT(!(ui8Mask & 0xF0)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); + + // Set the selected bits. + HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. +//! +//! This function allows byte (8 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected +//! by the operation, as the corresponding bits are not set in the +//! \c ui16Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui16Mask is the mask defining which of the 8 bit that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI16SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, + uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a +//! half-word (byte) boundary in the ADI slave. +//! +//! This function allows 2 byte (16 bit) access to the ADI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the +//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not +//! be affected by the operation, as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be +//! enabled before calling this function. +//! +//! \param ui32Base is the base address of the ADI port. +//! \param ui32Reg is the Least Significant Register in the ADI slave that +//! will be affected by the write operation. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +//! +//! \sa ADI4SetValBit(), ADI8SetValBit() +// +//***************************************************************************** +__STATIC_INLINE void +ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(ADIBaseValid(ui32Base)); + ASSERT(ui32Reg < ADI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the ADI slave. + ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ADI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi_doc.h new file mode 100644 index 00000000..22507080 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/adi_doc.h @@ -0,0 +1,66 @@ +/****************************************************************************** +* Filename: adi_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup adi_api +//! @{ +//! \section sec_adi Introduction +//! \n +//! +//! \section sec_adi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref ADI8RegWrite() +//! - \ref ADI16RegWrite() +//! - \ref ADI32RegWrite() +//! - Set individual bits: +//! - \ref ADI8BitsSet() +//! - \ref ADI16BitsSet() +//! - \ref ADI32BitsSet() +//! - Clear individual bits: +//! - \ref ADI8BitsClear() +//! - \ref ADI16BitsClear() +//! - \ref ADI32BitsClear() +//! - Masked: +//! - \ref ADI4SetValBit() +//! - \ref ADI8SetValBit() +//! - \ref ADI16SetValBit() +//! +//! Read: +//! - \ref ADI8RegRead() +//! - \ref ADI16RegRead() +//! - \ref ADI32RegRead() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.c new file mode 100644 index 00000000..eca99525 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.c @@ -0,0 +1,551 @@ +/****************************************************************************** +* Filename: aes.c +* +* Description: Driver for the AES functions of the crypto module +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aes.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AESStartDMAOperation + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #undef AESSetInitializationVector + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #undef AESReadTag + #define AESReadTag NOROM_AESReadTag + #undef AESVerifyTag + #define AESVerifyTag NOROM_AESVerifyTag + #undef AESWriteToKeyStore + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + + +#ifndef CRYPTO_SWRESET_SW_RESET +/* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */ +#define CRYPTO_SWRESET_SW_RESET 0x00000001 +#endif + +#ifndef CRYPTO_DMASWRESET_SWRES +/* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */ +#define CRYPTO_DMASWRESET_SWRES 0x00000001 +#endif + +#ifndef CRYPTO_DMASTAT_CH0_ACT +/* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */ +#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 +#endif + +#ifndef CRYPTO_DMASTAT_CH1_ACT +/* This definition is missing in hw_crypto.h for CC26X0 and CC13X0 devices */ +#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 +#endif + +//***************************************************************************** +// +// Load the initialization vector. +// +//***************************************************************************** +void AESSetInitializationVector(const uint32_t *initializationVector) +{ + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +//***************************************************************************** +// +// Read the IV for Authenticated Modes (CCM or GCM) after the tag has been read. +// +//***************************************************************************** +void AESReadAuthenticationModeIV(uint32_t *iv) +{ + /* Read the computed IV out from the hw registers */ + iv[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0); + iv[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1); + iv[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2); + /* This read will clear the saved_context_ready bit + * and allow the AES core to start the next operation. + */ + iv[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3); +} + +//***************************************************************************** +// +// Read the IV for Non-Authenticated Modes (CBC or CTR). +// +//***************************************************************************** +void AESReadNonAuthenticationModeIV(uint32_t *iv) +{ + /* Wait until the saved context is ready */ + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + AESReadAuthenticationModeIV(iv); +} + +//***************************************************************************** +// +// Start a crypto DMA operation. +// +//***************************************************************************** +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +//***************************************************************************** +// +// Transfer a key from CPU memory to a key store location. +// +//***************************************************************************** +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + // This buffer must be declared at function scope to prevent LLVM compiler from optimizing out memcpy. + uint8_t paddedKey[AES_256_KEY_LENGTH_BYTES] = {0}; + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + if (aesKeyLength == AES_192_KEY_LENGTH_BYTES) + { + // Writing a 192-bit key to the key store RAM must be done by writing + // 256 bits of data with the 64 most significant bits set to zero. + memcpy(paddedKey, aesKey, AES_192_KEY_LENGTH_BYTES); + + AESStartDMAOperation(paddedKey, AES_256_KEY_LENGTH_BYTES, 0, 0); + } + else + { + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + } + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Transfer a key from the keyStoreArea to the internal buffer of the module. +// +//***************************************************************************** +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) +{ + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +//***************************************************************************** +// +// Read the tag after a completed CCM, GCM, or CBC-MAC operation. +// +//***************************************************************************** +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) +{ + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Verify the provided tag against the computed tag after a completed CCM or +// GCM operation. +// +//***************************************************************************** +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) +{ + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +//***************************************************************************** +// +// Configure the AES module for CCM mode +// +//***************************************************************************** +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) +{ + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +//***************************************************************************** +// +// Configure an IV for CCM mode of operation +// +//***************************************************************************** +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) +{ + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} + +//***************************************************************************** +// +// Write AES_KEY2 registers +// +//***************************************************************************** +void AESWriteKey2(const uint32_t *key2) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY20) = key2[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY21) = key2[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY22) = key2[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY23) = key2[3]; +} + +//***************************************************************************** +// +// Write AES_KEY3 register +// +//***************************************************************************** +void AESWriteKey3(const uint32_t *key3) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY30) = key3[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY31) = key3[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY32) = key3[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY33) = key3[3]; +} + +//***************************************************************************** +// +// Clear AES_DATA_IN registers +// +//***************************************************************************** +void AESClearDataIn(void) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN0) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN1) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN2) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN3) = 0; +} + +//***************************************************************************** +// +// Write AES_DATA_IN registers +// +//***************************************************************************** +void AESWriteDataIn(const uint32_t *dataInBuffer) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN0) = dataInBuffer[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN1) = dataInBuffer[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN2) = dataInBuffer[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAIN3) = dataInBuffer[3]; +} + +//***************************************************************************** +// +// Read AES_DATA_OUT registers +// +//***************************************************************************** +void AESReadDataOut(uint32_t *dataOutBuffer) { + dataOutBuffer[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAOUT0); + dataOutBuffer[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAOUT1); + dataOutBuffer[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAOUT2); + dataOutBuffer[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESDATAOUT3); +} + +//***************************************************************************** +// +// Clear AES_KEY2 registers +// +//***************************************************************************** +void AESClearKey2(void) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY20) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY21) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY22) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY23) = 0; +} + +//***************************************************************************** +// +// Clear AES_KEY3 registers +// +//***************************************************************************** +void AESClearKey3(void) { + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY30) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY31) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY32) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_AESKEY33) = 0; +} + + +//***************************************************************************** +// +// Reset crypto engine +// +//***************************************************************************** +void AESReset(void) +{ + /* Soft reset routine per SafeXcel */ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = CRYPTO_SWRESET_SW_RESET; + AESSetCtrl(0); + AESSetDataLength(0); + AESSetAuthLength(0); + + /* Only CC26X2, CC13X2, CC26X2F6, CC13X2F6, CC26X4, and CC13X4 devices have hash support */ + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = 0; + HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = 0; + /* CRYPTO_O_HASHINLENH is automatically set to 0 by HW */ +} + +//***************************************************************************** +// +// Reset crypto DMA +// +//***************************************************************************** +void AESDMAReset(void) +{ + /* Reset DMA */ + HWREG(CRYPTO_BASE + CRYPTO_O_DMASWRESET) = CRYPTO_DMASWRESET_SWRES; + + /* Wait for DMA channels to be inactive */ + while (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT) & + (CRYPTO_DMASTAT_CH0_ACT | CRYPTO_DMASTAT_CH1_ACT)); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.h new file mode 100644 index 00000000..beb9a028 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes.h @@ -0,0 +1,989 @@ +/****************************************************************************** +* Filename: aes.h +* +* Description: AES header file. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#ifndef __AES_H__ +#define __AES_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AESStartDMAOperation NOROM_AESStartDMAOperation + #define AESSetInitializationVector NOROM_AESSetInitializationVector + #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector + #define AESReadTag NOROM_AESReadTag + #define AESVerifyTag NOROM_AESVerifyTag + #define AESWriteToKeyStore NOROM_AESWriteToKeyStore + #define AESReadFromKeyStore NOROM_AESReadFromKeyStore + #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags + #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#endif + + +//***************************************************************************** +// +// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear +// as the intFlags parameter, and returned from AESIntStatus. +// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// AES module return codes +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 + +// Key store module defines +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) + +#define AES_BLOCK_SIZE 16 + +// DMA status codes +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M + +// Crypto module operation types +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M + + +//***************************************************************************** +// +// For 128-bit keys, all 8 key area locations from 0 to 7 are valid. +// A 256-bit key requires two consecutive Key Area locations. The base key area +// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. +// +//***************************************************************************** +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 + +//***************************************************************************** +// +// Defines for the AES-CTR mode counter width +// +//***************************************************************************** +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length Length of the data in bytes to be read from or +//! written to at channel0Addr. Set to 0 to not set up +//! this channel. Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \param [out] channel1Addr A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length Length of the data in bytes to be read from or +//! written to at channel1Addr. Set to 0 to not set up +//! this channel.Permitted ranges are mode dependent +//! and displayed below. +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [1, sizeof(RAM)] +//! +//! \return None +// +//***************************************************************************** +extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, + uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Write the initialization vector (IV) to the crypto module. +//! +//! Depending on the mode of operation, the tag must be constructed +//! differently: +//! - CBC: No special care must be taken. Any 128-bit IV +//! (initialization vector) will suffice. +//! - CBC-MAC: IV's must be all 0's. +//! - CCM: Only 12 and 13 byte IV's are permitted. See code +//! below for formatting. +//! \code +//! uint8_t initVectorLength = 12; // Could also be 13 +//! +//! union { +//! uint32_t word[4]; +//! uint8_t byte[16]; +//! } initVector; +//! +//! uint8_t initVectorUnformatted[initVectorLength]; +//! +//! // This is the same field length value that is written to the ctrl register +//! initVector.byte[0] = L - 1; +//! +//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength); +//! +//! // Fill the remaining bytes with zeros +//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) { +//! initVector.byte[initVectorLength] = 0; +//! } +//! \endcode +//! +//! \param [in] initializationVector Pointer to an array with four 32-bit elements +//! to be used as initialization vector. +//! Elements of array must be word aligned in memory. +//! +//! \return None +// +//***************************************************************************** +extern void AESSetInitializationVector(const uint32_t *initializationVector); + +//***************************************************************************** +// +//! \brief Read the initialization vector (IV) out from the crypto module +//! for Non-Authenticated Modes (CBC or CTR). +//! +//! This function copies the IV calculated by the crypto module in CBC or CTR +//! mode to \c iv. +//! +//! \param [out] iv Pointer to an array with four 32-bit elements (16-bytes). +//! +//! \return None +// +//***************************************************************************** +void AESReadNonAuthenticationModeIV(uint32_t *iv); + +//***************************************************************************** +// +//! \brief Read the initialization vector (IV) out from the crypto module +//! for Authenticated Modes (CCM or GCM). +//! +//! This function copies the IV calculated by the crypto module in CCM or GCM +//! mode to \c iv. +//! +//! \pre #AESReadTag() must be called first. +//! +//! \param [out] iv Pointer to an array with four 32-bit elements (16-bytes). +//! +//! \return None +//! +//! \sa #AESReadTag() +// +//***************************************************************************** +void AESReadAuthenticationModeIV(uint32_t *iv); + + +//***************************************************************************** +// +//! \brief Generate and load the initialization vector for a CCM operation. +//! +//! +//! \param [in] nonce Pointer to a nonce of length \c nonceLength. +//! +//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating +//! the CCM IV. The L-value is also derived from it. +//! +//! \return None +// +//***************************************************************************** +extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength); + +//***************************************************************************** +// +//! \brief Read the tag out from the crypto module. +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [out] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to copy to \c tag. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_NOT_READY if the tag is not ready yet +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Verifies the provided \c tag against calculated one +//! +//! This function compares the provided tag against the tag calculated by the +//! crypto module during the last CCM, GCM, or CBC-MAC +//! +//! This function copies the \c tagLength bytes from the tag calculated by the +//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. +//! +//! \param [in] tag Pointer to an array of \c tagLength bytes. +//! +//! \param [in] tagLength Number of bytes to compare. +//! +//! \return Returns a status code depending on the result of the transfer. +//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed +//! - \ref AES_SUCCESS otherwise +// +//***************************************************************************** +extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength); + +//***************************************************************************** +// +//! \brief Transfer a key from main memory to a key area within the key store. +//! +//! The crypto DMA transfers the key and function does not return until +//! the operation completes. +//! The keyStore can only contain valid keys of one \c aesKeyLength at +//! any one point in time. The keyStore cannot contain both 128-bit and +//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength +//! from the previous \c aesKeyLength is loaded, all previous keys are +//! invalidated. +//! +//! \param [in] aesKey Pointer to key. Does not need to be word-aligned. +//! +//! \param [in] aesKeyLength The key size in bytes. +//! Currently, 128-bit, 192-bit, and 256-bit keys are supported. +//! - \ref AES_128_KEY_LENGTH_BYTES +//! - \ref AES_192_KEY_LENGTH_BYTES +//! - \ref AES_256_KEY_LENGTH_BYTES +//! +//! \param [in] keyStoreArea The key store area to transfer the key to. +//! When using 128-bit keys, only the specified key store +//! area will be occupied. +//! When using 256-bit or 192-bit keys, two consecutive +//! key areas are used to store the key. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are +//! split into four sets of two. Selecting any \c keyStoreArea automatically +//! occupies the second \c keyStoreArea of the tuples below: +//! +//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1) +//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3) +//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5) +//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7) +//! +//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2, +//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied. +//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied. +//! +//! \return Returns a status code depending on the result of the transfer. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESReadFromKeyStore +// +//***************************************************************************** +extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea); + +//***************************************************************************** +// +//! \brief Transfer a key from key store area to the internal buffers within +//! the hardware module. +//! +//! The function polls until the transfer is complete. +//! +//! \param [in] keyStoreArea The key store area to transfer the key from. +//! When using 256-bit keys, either of the occupied key areas +//! may be specified to load the key. There is no need to specify +//! the length of the key here as the key store keeps track +//! of how long a key associated with any valid key area is +//! and where is starts. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return Returns a status code depending on the result of the transfer. +//! When specifying a \c keyStoreArea value without a valid key in it an +//! error is returned. +//! If there was an error in the read process itself, an error is +//! returned. +//! Otherwise, a success code is returned. +//! - \ref AES_KEYSTORE_AREA_INVALID +//! - \ref AES_KEYSTORE_ERROR +//! - \ref AES_SUCCESS +//! +//! \sa AESWriteToKeyStore +// +//***************************************************************************** +extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); + + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be +//! masked with. May consist of any bitwise OR of the flags +//! below that includes at least one of +//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY : +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Configure AES engine for CCM operation. +//! +//! \param [in] nonceLength Length of the nonce. Must be <= 14. +//! +//! \param [in] macLength Length of the MAC. Must be <= 16. +//! +//! \param [in] encrypt Whether to set up an encrypt or decrypt operation. +//! - true: encrypt +//! - false: decrypt +//! +//! \return None +// +//***************************************************************************** +extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt); + +//***************************************************************************** +// +//! \brief Invalidate a key in the key store +//! +//! \param [in] keyStoreArea is the entry in the key store to invalidate. This +//! permanently deletes the key from the key store. +//! - \ref AES_KEY_AREA_0 +//! - \ref AES_KEY_AREA_1 +//! - \ref AES_KEY_AREA_2 +//! - \ref AES_KEY_AREA_3 +//! - \ref AES_KEY_AREA_4 +//! - \ref AES_KEY_AREA_5 +//! - \ref AES_KEY_AREA_6 +//! - \ref AES_KEY_AREA_7 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea) +{ + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Clear any previously written key at the key location + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); +} + +//***************************************************************************** +// +//! \brief Select type of operation +//! +//! \param [in] algorithm Flags that specify which type of operation the crypto +//! module shall perform. The flags are mutually exclusive. +//! - 0 : Reset the module +//! - \ref AES_ALGSEL_AES +//! - \ref AES_ALGSEL_TAG +//! - \ref AES_ALGSEL_KEY_STORE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == AES_ALGSEL_AES) || + (algorithm == AES_ALGSEL_TAG) || + (algorithm == AES_ALGSEL_KEY_STORE)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + +//***************************************************************************** +// +//! \brief Set up the next crypto module operation. +//! +//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL +//! register. The relevant field names have the format: +//! - CRYPTO_AESCTL_[field name] +//! +//! \param [in] ctrlMask Specifies which register fields shall be set. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; +} + +//***************************************************************************** +// +//! \brief Specify length of the crypto operation. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! \param [in] length Data length in bytes. If this +//! value is set to 0, only authentication of the AAD is +//! performed in CCM-mode and AESWriteAuthLength() must be set to +//! >0. +//! Range depends on the mode: +//! - ECB: [16] +//! - CBC: [1, sizeof(RAM)] +//! - CBC-MAC: [1, sizeof(RAM)] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteAuthLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetDataLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; + HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; +} + +//***************************************************************************** +// +//! \brief Specify the length of the additional authentication data (AAD). +//! +//! Despite specifying it here, the crypto DMA must still be set up with +//! the correct AAD length. +//! +//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode, +//! set this to 0 if no AAD is required. If set to 0, +//! AESWriteDataLength() must be set to >0. +//! Range depends on the mode: +//! - ECB: Do not call. +//! - CBC: [0] +//! - CBC-MAC: [0] +//! - CCM: [0, sizeof(RAM)] +//! +//! \return None +//! +//! \sa AESWriteDataLength +// +//***************************************************************************** +__STATIC_INLINE void AESSetAuthLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; +} + +//***************************************************************************** +// +//! \brief Reset the accelerator and cancel ongoing operations. +//! +//! \pre AESDMAReset +//! +//! \return None +// +//***************************************************************************** +void AESReset(void); + +//***************************************************************************** +// +//! \brief Reset the accelerator DMA. +//! +//! \return None +//! +//! \sa AESReset +// +//***************************************************************************** +void AESDMAReset(void); + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! - \ref AES_DMA_BUS_ERR +//! - \ref AES_KEY_ST_WR_ERR +//! - \ref AES_KEY_ST_RD_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESIntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref AES_DMA_IN_DONE +//! - \ref AES_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESIntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & AES_DMA_IN_DONE) || + (intFlags & AES_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt. +//! +//! This function does the actual registering of the interrupt handler. This +//! function enables the global interrupt in the interrupt controller; specific +//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void AESIntUnregister(void) +{ + // + // Disable the interrupt. + // + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // + // Unregister the interrupt handler. + // + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Read the Crypto module control and mode register value. +//! +//! \return Returns the AES_CTL register value +// +//***************************************************************************** +__STATIC_INLINE uint32_t AESGetCtrl(void) +{ + return(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL)); +} + +//***************************************************************************** +// +//! \brief Write the crypto module KEY2 registers +//! +//! \param [in] key2 Pointer to the 4 x 32-bit key-material to be written to +//! AES_KEY2_0 .. AES_KEY2_3 registers. +//! +//! \return None +// +//***************************************************************************** +void AESWriteKey2(const uint32_t *key2); + +//***************************************************************************** +// +//! \brief Write the crypto module KEY3 registers +//! +//! \param [in] key3 Pointer to the 4 x 32-bit key-material to be written to +//! AES_KEY3_0 .. AES_KEY3_3 registers. +//! +//! \return None +// +//***************************************************************************** +void AESWriteKey3(const uint32_t *key3); + +//***************************************************************************** +// +//! \brief Clear the crypto module DATA_IN registers +//! +//! \return None +// +//***************************************************************************** +void AESClearDataIn(void); + +//***************************************************************************** +// +//! \brief Write the crypto module DATA_IN registers. +//! +//! \param [in] dataInBuffer Pointer to the 4 x 32-bit buffer containing data +//! to be written to AES_DATA_IN_0 .. AES_DATA_IN_3 +//! registers. +//! +//! \return None +// +//***************************************************************************** +void AESWriteDataIn(const uint32_t *dataInBuffer); + +//***************************************************************************** +// +//! \brief Read the crypto module DATA_OUT registers. +//! +//! \param [out] dataOutBuffer Pointer to the 4 x 32-bit buffer to output +//! data from AES_DATA_OUT_0 .. AES_DATA_OUT_3 +//! registers. +//! +//! \return None +// +//***************************************************************************** +void AESReadDataOut(uint32_t *dataOutBuffer); + +//***************************************************************************** +// +//! \brief Clear the crypto module KEY2 registers +//! +//! \return None +// +//***************************************************************************** +void AESClearKey2(void); + +//***************************************************************************** +// +//! \brief Clear the crypto module KEY3 registers +//! +//! \return None +// +//***************************************************************************** +void AESClearKey3(void); + +//***************************************************************************** +// +//! \brief Clear key registers as required for AES CBC-MAC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void AESCBCMACClearKeys(void) +{ + AESClearKey2(); + AESClearKey3(); +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AESStartDMAOperation + #undef AESStartDMAOperation + #define AESStartDMAOperation ROM_AESStartDMAOperation + #endif + #ifdef ROM_AESSetInitializationVector + #undef AESSetInitializationVector + #define AESSetInitializationVector ROM_AESSetInitializationVector + #endif + #ifdef ROM_AESWriteCCMInitializationVector + #undef AESWriteCCMInitializationVector + #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector + #endif + #ifdef ROM_AESReadTag + #undef AESReadTag + #define AESReadTag ROM_AESReadTag + #endif + #ifdef ROM_AESVerifyTag + #undef AESVerifyTag + #define AESVerifyTag ROM_AESVerifyTag + #endif + #ifdef ROM_AESWriteToKeyStore + #undef AESWriteToKeyStore + #define AESWriteToKeyStore ROM_AESWriteToKeyStore + #endif + #ifdef ROM_AESReadFromKeyStore + #undef AESReadFromKeyStore + #define AESReadFromKeyStore ROM_AESReadFromKeyStore + #endif + #ifdef ROM_AESWaitForIRQFlags + #undef AESWaitForIRQFlags + #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags + #endif + #ifdef ROM_AESConfigureCCMCtrl + #undef AESConfigureCCMCtrl + #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AES_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes_doc.h new file mode 100644 index 00000000..c7449b55 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aes_doc.h @@ -0,0 +1,64 @@ +/****************************************************************************** +* Filename: aes_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aes_api +//! @{ +//! \section sec_aes Introduction +//! +//! The AES (advanced encryption standard) API provides access to the AES and key +//! store functionality of the crypto core. The SHA2 accelerator is also +//! contained within the crypto core. Hence, only one of SHA2 and AES may be +//! used at the same time. +//! This module offers hardware acceleration for several protocols using the +//! AES block cypher. The protocols below are supported by the hardware. The +//! driverlib documentation only explicitly references the most commonly used ones. +//! - ECB +//! - CBC +//! - CCM +//! - CBC-MAC +//! - GCM +//! +//! The key store is a section of crypto memory that is only accessible to the crypto module +//! and may be written to by the application via the crypto DMA. It is not possible to +//! read from the key store to main memory. Thereby, it is not possible to +//! compromise the key should the application be hacked if the original key in main +//! memory was overwritten already. +//! +//! The crypto core does not have retention and all configuration settings and +//! keys in the keystore are lost when going into standby or shutdown. +//! The typical security advantages a key store offers are not available in these +//! low power modes as the key must be saved in regular memory to reload +//! it after going into standby or shutdown. +//! Consequently, the keystore primarily serves as an interface to the AES accelerator. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.c new file mode 100644 index 00000000..a6546990 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.c @@ -0,0 +1,78 @@ +/****************************************************************************** +* Filename: aon_batmon.c +* +* Description: Driver for the AON Battery and Temperature Monitor +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_batmon.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + +//***************************************************************************** +// +// AONBatMonTemperatureGetDegC() +// Returns sign extended temperature in Deg C (-256 .. +255) +// +//***************************************************************************** +int32_t +AONBatMonTemperatureGetDegC( void ) +{ + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + + +// See aon_batmon.h for implementation of remaining functions diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.h new file mode 100644 index 00000000..cbfc2944 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_batmon.h @@ -0,0 +1,304 @@ +/****************************************************************************** +* Filename: aon_batmon.h +* +* Description: Defines and prototypes for the AON Battery and Temperature +* Monitor +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonbatmon_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_BATMON_H__ +#define __AON_BATMON_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_batmon.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the temperature and battery monitoring. +//! +//! This function will enable the measurements of the temperature and the +//! battery voltage. +//! +//! To speed up the measurement of the levels the measurement can be enabled +//! before configuring the battery and temperature settings. When all of the +//! AON_BATMON registers are configured, the calculation of the voltage and +//! temperature values can be enabled (the measurement will now take +//! effect/propagate to other blocks). +//! +//! It is possible to enable both at the same time, after the AON_BATMON +//! registers are configured, but then the first values will be ready at a +//! later point compared to the scenario above. +//! +//! \note Temperature and battery voltage measurements are not done in +//! parallel. The measurement cycle is controlled by a hardware Finite State +//! Machine. First the temperature and then the battery voltage each taking +//! one cycle to complete. However, if the comparator measuring the battery +//! voltage detects a change on the reference value, a new measurement of the +//! battery voltage only is performed immediately after. This has no impact on +//! the cycle count. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonEnable(void) +{ + // Enable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = + AON_BATMON_CTL_CALC_EN | + AON_BATMON_CTL_MEAS_EN; +} + +//***************************************************************************** +// +//! \brief Disable the temperature and battery monitoring. +//! +//! This function will disable the measurements of the temperature and the +//! battery voltage. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONBatMonDisable(void) +{ + // Disable the measurements. + HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; +} + + +//***************************************************************************** +// +//! \brief Get the current temperature measurement as a signed value in Deg Celsius. +//! +//! This function returns an calibrated and rounded value in degree Celsius. +//! The temperature measurements are updated every cycle. +//! +//! \note The temperature drifts slightly depending on the battery voltage. +//! This function compensates for this drift and returns a calibrated temperature. +//! +//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. +//! +//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) +//! +//! \sa AONBatMonNewTempMeasureReady() +// +//***************************************************************************** +extern int32_t AONBatMonTemperatureGetDegC( void ); + +//***************************************************************************** +// +//! \brief Get the battery monitor measurement. +//! +//! This function will return the current battery monitor measurement. +//! The battery voltage measurements are updated every cycle. +//! +//! \note The returned value is NOT sign-extended! +//! +//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for +//! a change in measurement. +//! +//! \return Returns the current battery monitor value of the battery voltage +//! measurement in a format size <3.8> in units of volt. +//! +//! \sa AONBatMonNewBatteryMeasureReady() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONBatMonBatteryVoltageGet(void) +{ + uint32_t ui32CurrentBattery; + + ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); + + // Return the current battery voltage measurement. + return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); +} + +//***************************************************************************** +// +//! \brief Check if battery monitor measurement has changed. +//! +//! This function checks if a new battery monitor value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! battery level using AONBatMonBatteryVoltageGet() but this function can be +//! used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewBatteryMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & + AON_BATMON_BATUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +//! \brief Check if temperature monitor measurement has changed. +//! +//! This function checks if a new temperature value is available. If the +//! measurement value has \b changed since last clear the function returns \c true. +//! +//! If the measurement has changed the function will automatically clear the +//! status bit. +//! +//! \note It is always possible to read out the current value of the +//! temperature using \ref AONBatMonTemperatureGetDegC() +//! but this function can be used to check if the measurement has changed. +//! +//! \return Returns \c true if the measurement value has changed and \c false +//! otherwise. +//! +//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +__STATIC_INLINE bool +AONBatMonNewTempMeasureReady(void) +{ + bool bStatus; + + // Check the status bit. + bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & + AON_BATMON_TEMPUPD_STAT ? true : false; + + // Clear status bit if set. + if(bStatus) + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; + } + + // Return status. + return (bStatus); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONBatMonTemperatureGetDegC + #undef AONBatMonTemperatureGetDegC + #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_BATMON_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.c new file mode 100644 index 00000000..140c87bd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.c @@ -0,0 +1,178 @@ +/****************************************************************************** +* Filename: aon_event.c +* +* Description: Driver for the AON Event fabric. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #undef AONEventMcuSet + #define AONEventMcuSet NOROM_AONEventMcuSet + #undef AONEventMcuGet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Select event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +void +AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Shift ; + uint32_t ui32Mask ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + ASSERT( ui32EventSrc <= AON_EVENT_NONE ); + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32Mask = ( 0x3F << ui32Shift ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift ); +} + +//***************************************************************************** +// +// Get event source for the specified MCU wakeup programmable event +// +//***************************************************************************** +uint32_t +AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) +{ + uint32_t ui32Shift ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F ); +} + +//***************************************************************************** +// +// Select event source for the specified programmable event forwarded to the +// MCU event fabric +// +//***************************************************************************** +void +AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +// Get source for the specified programmable event forwarded to the MCU event +// fabric. +// +//***************************************************************************** +uint32_t +AONEventMcuGet(uint32_t ui32MCUEvent) +{ + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.h new file mode 100644 index 00000000..888e4dae --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event.h @@ -0,0 +1,562 @@ +/****************************************************************************** +* Filename: aon_event.h +* +* Description: Defines and prototypes for the AON Event fabric. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonevent_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_EVENT_H__ +#define __AON_EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_event.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet + #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet + #define AONEventMcuSet NOROM_AONEventMcuSet + #define AONEventMcuGet NOROM_AONEventMcuGet +#endif + +//***************************************************************************** +// +// Event sources for the event AON fabric. +// Note: Events are level-triggered active high +// +//***************************************************************************** +#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2 +#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit +#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit +#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit +#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit +#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. + // Event ID 33 is reserved for future use + // Event ID 34 is reserved for future use +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B + // Event ID 57-62 is reserved for future use +#define AON_EVENT_NONE 63 // No event, always low + +// Keeping backward compatibility until major revision number is incremented +#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) + +//***************************************************************************** +// +// Values that can be passed to AONEventMCUWakeUpSet() and returned +// by AONEventMCUWakeUpGet(). +// +//***************************************************************************** +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 +#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4 +#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5 +#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6 +#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7 + +//***************************************************************************** +// +// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() +// +//***************************************************************************** +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Select event source for the specified MCU wake-up programmable event. +//! +//! The AON event fabric has several programmable events that can wake up the MCU. +//! +//! \note The programmable event sources are effectively OR'ed together +//! to form a single wake-up event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! - \ref AON_EVENT_MCU_WU4 +//! - \ref AON_EVENT_MCU_WU5 +//! - \ref AON_EVENT_MCU_WU6 +//! - \ref AON_EVENT_MCU_WU7 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuWakeUpGet() +// +//***************************************************************************** +extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, + uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get event source for the specified MCU wake-up programmable event. +//! +//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. +//! - \ref AON_EVENT_MCU_WU0 +//! - \ref AON_EVENT_MCU_WU1 +//! - \ref AON_EVENT_MCU_WU2 +//! - \ref AON_EVENT_MCU_WU3 +//! - \ref AON_EVENT_MCU_WU4 +//! - \ref AON_EVENT_MCU_WU5 +//! - \ref AON_EVENT_MCU_WU6 +//! - \ref AON_EVENT_MCU_WU7 +//! +//! \return Returns the event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuWakeUpSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); + +//***************************************************************************** +// +//! \brief Select event source for the specified programmable event forwarded to the +//! MCU event fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \note The three programmable event sources are forwarded to the MCU Event +//! Fabric as: +//! - AON_PROG0 +//! - AON_PROG1 +//! - AON_PROG2 +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventMcuGet() +// +//***************************************************************************** +extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); + +//***************************************************************************** +// +//! \brief Get source for the specified programmable event forwarded to the MCU event +//! fabric. +//! +//! The AON event fabric has a total of three programmable events that can +//! be forwarded to the MCU event fabric. +//! +//! \param ui32MCUEvent is one of three programmable events forwarded to the +//! MCU event fabric. +//! - \ref AON_EVENT_MCU_EVENT0 +//! - \ref AON_EVENT_MCU_EVENT1 +//! - \ref AON_EVENT_MCU_EVENT2 +//! +//! \return Returns the event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventMcuSet() +// +//***************************************************************************** +extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); + +//***************************************************************************** +// +//! \brief Select event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \param ui32EventSrc is an event source for the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \return None +//! +//! \sa AONEventRtcGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONEventRtcSet(uint32_t ui32EventSrc) +{ + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; + + HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; +} + +//***************************************************************************** +// +//! \brief Get event source forwarded to AON Real Time Clock (RTC). +//! +//! A programmable event can be forwarded to the AON real time clock +//! for triggering a capture event on RTC channel 1. +//! +//! \return Returns the event source to the event AON fabric. +//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 +//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 +//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit +//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit +//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit +//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit +//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON +//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. +//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 +//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 +//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 +//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event +//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event +//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event +//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event +//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +//! - \ref AON_EVENT_JTAG : JTAG generated event +//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 +//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 +//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 +//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) +//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed +//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out +//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event +//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event +//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event +//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event +//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B +//! - \ref AON_EVENT_NONE : No event, always low +//! +//! \sa AONEventRtcSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONEventRtcGet(void) +{ + uint32_t ui32EventSrc; + + // Return the active event. + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); + + return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> + AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONEventMcuWakeUpSet + #undef AONEventMcuWakeUpSet + #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet + #endif + #ifdef ROM_AONEventMcuWakeUpGet + #undef AONEventMcuWakeUpGet + #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet + #endif + #ifdef ROM_AONEventMcuSet + #undef AONEventMcuSet + #define AONEventMcuSet ROM_AONEventMcuSet + #endif + #ifdef ROM_AONEventMcuGet + #undef AONEventMcuGet + #define AONEventMcuGet ROM_AONEventMcuGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event_doc.h new file mode 100644 index 00000000..58d71b2b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_event_doc.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* Filename: aon_event_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonevent_api +//! @{ +//! \section sec_aonevent Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). +//! +//! The AON event fabric is a configurable combinatorial router between AON event sources and event +//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration +//! can be grouped based on the event subscriber to configure: +//! +//! - Wake-up events. +//! - MCU wake-up event +//! - @ref AONEventMcuWakeUpSet() +//! - @ref AONEventMcuWakeUpGet() +//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). +//! - @ref AONEventRtcSet() +//! - @ref AONEventRtcGet() +//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). +//! - @ref AONEventMcuSet() +//! - @ref AONEventMcuGet() +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.c new file mode 100644 index 00000000..9f67629d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.c @@ -0,0 +1,37 @@ +/****************************************************************************** +* Filename: aon_ioc.c +* +* Description: Driver for the AON IO Controller +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_ioc.h" diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.h new file mode 100644 index 00000000..8d10ebc4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: aon_ioc.h +* +* Description: Defines and prototypes for the AON IO Controller +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_IOC_H__ +#define __AON_IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aon_ioc.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the drive strength +// +//***************************************************************************** +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength + +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure drive strength values for the manual drive strength options. +//! +//! This function defines the general drive strength settings for the non-AUTO +//! drive strength options in the MCU IOC. Consequently, if all IOs are using the +//! automatic drive strength option this function has no effect. +//! +//! Changing the drive strength values affects all current modes (Low-Current, +//! High-Current, and Extended-Current). Current mode for individual IOs is set in +//! MCU IOC by \ref IOCIODrvStrengthSet(). +//! +//! \note Values are Gray encoded. Simply incrementing values to increase drive +//! strength will not work. +//! +//! \param ui32DriveLevel +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected +//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, +//! and Extended-Current mode respectively. +//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \return None +//! +//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) +{ + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || + (ui32DriveStrength == AONIOC_DRV_STR_2) || + (ui32DriveStrength == AONIOC_DRV_STR_3) || + (ui32DriveStrength == AONIOC_DRV_STR_4) || + (ui32DriveStrength == AONIOC_DRV_STR_5) || + (ui32DriveStrength == AONIOC_DRV_STR_6) || + (ui32DriveStrength == AONIOC_DRV_STR_7) || + (ui32DriveStrength == AONIOC_DRV_STR_8)); + + // Set the drive strength. + HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; +} + +//***************************************************************************** +// +//! \brief Get a specific drive level setting for all IOs. +//! +//! Use this function to read the drive strength setting for a specific +//! IO drive level. +//! +//! \note Values are Gray encoded. +//! +//! \param ui32DriveLevel is the specific drive level to get the setting for. +//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. +//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. +//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. +//! +//! \return Returns the requested drive strength level setting for all IOs. +//! Possible values are: +//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength +//! - \ref AONIOC_DRV_STR_2 +//! - \ref AONIOC_DRV_STR_3 +//! - \ref AONIOC_DRV_STR_4 +//! - \ref AONIOC_DRV_STR_5 +//! - \ref AONIOC_DRV_STR_6 +//! - \ref AONIOC_DRV_STR_7 +//! - \ref AONIOC_DRV_STR_8 : Highest drive strength +//! +//! \sa AONIOCDriveStrengthSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) +{ + // Check the arguments. + ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || + (ui32DriveLevel == AONIOC_DRV_LVL_MED) || + (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); + + // Return the drive strength value. + return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); +} + +//***************************************************************************** +// +//! \brief Freeze the IOs. +//! +//! To retain the values of the output IOs during a powerdown/shutdown of the +//! device all IO latches in the AON domain should be frozen in their current +//! state. This ensures that software can regain control of the IOs after a +//! reboot without the IOs first falling back to the default values (i.e. input +//! and no pull). +//! +//! \return None +//! +//! \sa AONIOCFreezeDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeEnable(void) +{ + // Set the AON IO latches as static. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; +} + +//***************************************************************************** +// +//! \brief Un-freeze the IOs. +//! +//! When rebooting the chip after it has entered powerdown/shutdown mode, the +//! software can regain control of the IOs by setting the IO latches as +//! transparent. The IOs should not be unfrozen before software has restored +//! the functionality of the IO. +//! +//! \return None +//! +//! \sa AONIOCFreezeEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOCFreezeDisable(void) +{ + // Set the AON IOC latches as transparent. + HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; +} + +//***************************************************************************** +// +//! \brief Disable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to disable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputDisable(void) +{ + // Disable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; +} + +//***************************************************************************** +// +//! \brief Enable the 32kHz clock output. +//! +//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality +//! in the IOC is bypassed. Therefore, the programmer needs to call this +//! function to enable the clock output. +//! +//! \return None +//! +//! \sa AONIOC32kHzOutputDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONIOC32kHzOutputEnable(void) +{ + // Enable the LF clock output. + HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc_doc.h new file mode 100644 index 00000000..16d229dc --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_ioc_doc.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* Filename: aon_ioc_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonioc_api +//! @{ +//! \section sec_aonioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). +//! +//! \section sec_aonioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Freeze IOs while MCU domain is powered down: +//! - \ref AONIOCFreezeEnable() +//! - \ref AONIOCFreezeDisable() +//! +//! Output LF clock to a DIO: +//! - \ref AONIOC32kHzOutputEnable() +//! - \ref AONIOC32kHzOutputDisable() +//! +//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): +//! - \ref AONIOCDriveStrengthSet() +//! - \ref AONIOCDriveStrengthGet() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.c new file mode 100644 index 00000000..ca1d0002 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aon_pmctl.c +* +* Description: Driver for the AON Power-Management Controller. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_pmctl.h" + +// See aon_pmctl.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.h new file mode 100644 index 00000000..d8dbd2e1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl.h @@ -0,0 +1,200 @@ +/****************************************************************************** +* Filename: aon_pmctl.h +* +* Description: Defines and prototypes for the AON Power-Management Controller +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonpmctl_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_PMCTL_H__ +#define __AON_PMCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_memmap_common.h" +#include "../inc/hw_aon_pmctl.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines that can be be used to enable/disable the retention on the SRAM +// banks during power off of the MCU BUS domain. The defines can be passed to +// AONPMCTLMcuSRamConfig) . +// +//***************************************************************************** +#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE +#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 +#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 +#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 +#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL + +//***************************************************************************** +// +// Defines for all the different power modes available through +// AONPMCTLPowerStatusGet() . +// +//***************************************************************************** +#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the retention on the block SRAM in the MCU BUS domain. +//! +//! MCU SRAM is partitioned into 5 banks of 16 KB each. The SRAM supports +//! retention on all 5 banks during MCU BUS domain power off. The retention +//! on the SRAM can be turned on and off. Use this function to enable the +//! retention on the banks. +//! +//! If a group of banks is not represented in the parameter \c ui32Retention +//! then the retention will be disabled for that bank group during MCU BUS +//! domain power off. +//! +//! \note Retention on all SRAM banks is enabled by default. Configuration of +//! individual SRAM banks is not supported. Configuration is only supported +//! on bank group level. +//! +//! \param ui32Retention defines which groups of SRAM banks to enable/disable +//! retention on: +//! - \ref MCU_RAM_RET_NONE Retention is disabled +//! - \ref MCU_RAM_RET_LVL1 Retention on for banks 0 and 1 +//! - \ref MCU_RAM_RET_LVL2 Retention on for banks 0, 1 and 2 +//! - \ref MCU_RAM_RET_LVL3 Retention on for banks 0, 1, 2 and 3 +//! - \ref MCU_RAM_RET_FULL Retention on for all five banks +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONPMCTLMcuSRamRetConfig(uint32_t ui32Retention) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32Retention == MCU_RAM_RET_NONE) || + (ui32Retention == MCU_RAM_RET_LVL1) || + (ui32Retention == MCU_RAM_RET_LVL2) || + (ui32Retention == MCU_RAM_RET_LVL3) || + (ui32Retention == MCU_RAM_RET_FULL)); + + // Configure the retention. + ui32Reg = HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M; + ui32Reg |= ui32Retention; + HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_RAMCFG) = ui32Reg; +} + +//***************************************************************************** +// +//! \brief Get the power status of the Always On (AON) domain. +//! +//! This function reports the power management status in AON. +//! +//! \return Returns the current power status of the device as a bitwise OR'ed +//! combination of these values: +//! - \ref AONPMCTL_JTAG_POWER_ON +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONPMCTLPowerStatusGet(void) +{ + // Return the power status. + return (HWREG(AON_PMCTL_BASE + NONSECURE_OFFSET + AON_PMCTL_O_PWRSTAT)); +} + + +//***************************************************************************** +// +//! \brief Request power off of the JTAG domain. +//! +//! The JTAG domain is automatically powered up on if a debugger is connected. +//! If a debugger is not connected this function can be used to power off the +//! JTAG domain. +//! +//! \note Achieving the lowest power modes (shutdown/powerdown) requires the +//! JTAG domain to be turned off. In general the JTAG domain should never be +//! powered in production code. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONPMCTLJtagPowerOff(void) +{ + // Request the power off of the JTAG domain + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_PMCTL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl_doc.h new file mode 100644 index 00000000..ed77c0d1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_pmctl_doc.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* Filename: aon_pmctl_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonpmctl_api +//! @{ +//! \section sec_aonpmctl Introduction +//! +//! This API provides a set of functions for using the AON Power Management +//! Controller module (AON_PMCTL). +//! +//! The AON_PMCTL module contains the following functional options: +//! - Selection of voltage regulator for the digital domain. +//! - Control of retention of MCU SRAM banks during power off of the BUS power domain. +//! - Control of power and retention of AUX SRAM. +//! - Control of power, reset, and clock for the following domains: +//! - MCU_VD +//! - JTAG_PD +//! - AUX +//! - Control of the recharging of VDDR while in uLDO state. +//! - Control of the generation of a periodic request to the OSCDIG to initiate +//! an XOSC_HF amplitude calibration sequence. +//! +//! The main clock for the AON_PMCTL module is the 2 MHz SCLK MF clock. +//! +//! AON_PMCTL supports the MCU_voltage domain with a 48 MHz clock (SCLK_HF) that is divided +//! and gated by the PRCM module before being distributed to all modules in the +//! MCU voltage domain. +//! +//! The AON_PMCTL controls the SCLK_HF clock to ensure that it is available in the +//! Active and Idle power modes, and disabled for all other modes. SCLK_HF is not +//! allowed in uLDO state since it uses too much power. +//! The SCLK_HF clock is also available for the AUX module in the Active and Idle +//! power modes. +//! +//! The AON_PMCTL selects the clock source for the AUX domain in the different +//! power modes. +//! +//! Main functionality to control power management of the JTAG power domain is +//! supported. Note that no clock control is supported, as the JTAG is clocked +//! on the TCK clock. +//! +//! +//! \section sec_aonpmctl_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform status report: +//! - \ref AONPMCTLPowerStatusGet() +//! +//! +//! Functions to perform device configuration: +//! - \ref AONPMCTLJtagPowerOff() +//! - \ref AONPMCTLMcuSRamRetConfig() +//! +//! Please note that due to legacy software compatibility some functionalities controlled +//! by the AON Power Management Controller module are supported through the APIs of +//! the [System Controller](@ref sysctrl_api) and [Power Controller](@ref pwrctrl_api). Relevant functions are: +//! - \ref PowerCtrlSourceGet() +//! - \ref PowerCtrlSourceSet() +//! - \ref PowerCtrlResetSourceGet() +//! - \ref SysCtrl_DCDC_VoltageConditionalControl() +//! - \ref SysCtrlClockLossResetDisable() +//! - \ref SysCtrlClockLossResetEnable() +//! - \ref SysCtrlSystemReset() +//! - \ref SysCtrlResetSourceGet() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.c new file mode 100644 index 00000000..ae5f06f8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* Filename: aon_rtc.c +* +* Description: Driver for the AON RTC. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aon_rtc.h" +#include "cpu.h" +#include "../inc/hw_memmap_common.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + +//***************************************************************************** +// +// Get the current 64-bit value of the RTC counter. +// +//***************************************************************************** +uint64_t +AONRTCCurrent64BitValueGet( void ) +{ + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.h new file mode 100644 index 00000000..5d2a8724 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc.h @@ -0,0 +1,930 @@ +/****************************************************************************** +* Filename: aon_rtc.h +* +* Description: Defines and prototypes for the AON RTC +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aon_group +//! @{ +//! \addtogroup aonrtc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AON_RTC_H__ +#define __AON_RTC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_memmap_common.h" +#include "../inc/hw_aon_rtc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#endif + +//***************************************************************************** +// +// Values that can be passed to most of the AON_RTC APIs as the ui32Channel +// parameter. +// +//***************************************************************************** +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active + +//***************************************************************************** +// +// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. +// +//***************************************************************************** +#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode + +//***************************************************************************** +// +// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode +// parameter. +// +//***************************************************************************** +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode + +//***************************************************************************** +// +// Mutliplication factor for converting from seconds to corresponding time in +// the "CompareValue" format. +// The factor correspond to the compare value format described in the registers +// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. +// Example1: +// 4 milliseconds in CompareValue format can be written like this: +// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) +// Example2: +// 4 seconds in CompareValue format can be written like this: +// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) +// +//***************************************************************************** +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RTC. +//! +//! Enable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels must also be enabled +//! using the function AONRTCChannelEnable(). +//! +//! \return None +//! +//! \sa AONRTCChannelEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEnable(void) +{ + // Enable RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the RTC. +//! +//! Disable the AON Real Time Clock. +//! +//! \note Event generation for each of the three channels can also be disabled +//! using the function AONRTCChannelDisable(). +//! +//! \return None +//! +//! \sa AONRTCChannelDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDisable(void) +{ + // Disable RTC + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Reset the RTC. +//! +//! Reset the AON Real Time Clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCReset(void) +{ + // Reset RTC. + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Check if the RTC is active (enabled). +//! +//! \return Returns the status of the RTC. +//! - false : RTC is disabled +//! - true : RTC is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCActive(void) +{ + // Read if RTC is enabled + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Check if an RTC channel is active (enabled). +//! +//! \param ui32Channel specifies the RTC channel to check status of. +//! Parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the status of the requested channel: +//! - false : Channel is disabled +//! - true : Channel is enabled +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCChannelActive(uint32_t ui32Channel) +{ + uint32_t uint32Status = 0; + + if(ui32Channel & AON_RTC_CH0) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); + } + + return(uint32Status); +} + +//***************************************************************************** +// +//! \brief Configure Event Delay for the RTC. +//! +//! Each event from the three individual channels can generate a delayed +//! event. The delay time for these events is set using this function. +//! The delay is measured in clock cycles. +//! +//! \note There is only one delay setting shared for all three channels. +//! +//! \param ui32Delay specifies the delay time for delayed events. +//! Parameter must be one of the following: +//! - \ref AON_RTC_CONFIG_DELAY_NODELAY +//! - \ref AON_RTC_CONFIG_DELAY_1 +//! - \ref AON_RTC_CONFIG_DELAY_2 +//! - \ref AON_RTC_CONFIG_DELAY_4 +//! - \ref AON_RTC_CONFIG_DELAY_8 +//! - \ref AON_RTC_CONFIG_DELAY_16 +//! - \ref AON_RTC_CONFIG_DELAY_32 +//! - \ref AON_RTC_CONFIG_DELAY_48 +//! - \ref AON_RTC_CONFIG_DELAY_64 +//! - \ref AON_RTC_CONFIG_DELAY_80 +//! - \ref AON_RTC_CONFIG_DELAY_96 +//! - \ref AON_RTC_CONFIG_DELAY_112 +//! - \ref AON_RTC_CONFIG_DELAY_128 +//! - \ref AON_RTC_CONFIG_DELAY_144 +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCDelayConfig(uint32_t ui32Delay) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); + + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); + ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Configure the source of the combined event. +//! +//! A combined delayed event can be generated from a combination of the three +//! delayed events. Delayed events form the specified channels are OR'ed +//! together to generate the combined event. +//! +//! \param ui32Channels specifies the channels that are to be used for +//! generating the combined event. +//! The parameter must be the bitwise OR of any of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! - \ref AON_RTC_CH_NONE +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCombinedEventConfig(uint32_t ui32Channels) +{ + uint32_t ui32Cfg; + + // Check the arguments. + ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE) ); + + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); + ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); + + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; +} + +//***************************************************************************** +// +//! \brief Clear event from a specified channel. +//! +//! In case of an active event from the specified channel, the event +//! will be cleared (de-asserted). +//! +//! \param ui32Channel clears the event from one or more RTC channels: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCEventClear(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS + NONSECURE_OFFSET) = AON_RTC_EVFLAGS_CH2; + } +} + +//***************************************************************************** +// +//! \brief Get event status for a specified channel. +//! +//! In case of an active event from the specified channel, +//! this call will return \c true otherwise \c false. +//! +//! \param ui32Channel specifies the channel from which to query the event state. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns \c true if an event has occurred for the given channel, +//! otherwise \c false. +// +//***************************************************************************** +__STATIC_INLINE bool +AONRTCEventGet(uint32_t ui32Channel) +{ + uint32_t uint32Event = 0; + + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); + } + + if(ui32Channel & AON_RTC_CH1) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); + } + + if(ui32Channel & AON_RTC_CH2) + { + uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); + } + + return(uint32Event); +} + +//***************************************************************************** +// +//! \brief Get integer part (seconds) of RTC free-running timer. +//! +//! Get the value in seconds of RTC free-running timer, i.e. the integer part. +//! The fractional part is returned from a call to AONRTCFractionGet(). +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the integer part of RTC free running timer. +//! +//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSecGet(void) +{ + // The following read gets the seconds, but also latches the fractional + // part. + return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC + NONSECURE_OFFSET)); +} + +//***************************************************************************** +// +//! \brief Get fractional part (sub-seconds) of RTC free-running timer. +//! +//! Get the value of the fractional part of RTC free-running timer, i.e. the +//! sub-second part. +//! +//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead +//! of this function if the <16.16> format is sufficient. +//! +//! \note To read a consistent pair of integer and fractional parts, +//! \ref AONRTCSecGet() must be called first to trigger latching of the +//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts +//! must be disabled to ensure that these operations are performed atomically. +//! +//! \return Returns the fractional part of RTC free running timer. +//! +//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCFractionGet(void) +{ + // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead + // of this function if the <16.16> format is sufficient. + // Note2: AONRTCSecGet() must be called before this function to get a + // consistent reading. + // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this + // call since there are interrupt functions that reads AON_RTC_O_SEC + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC + NONSECURE_OFFSET)); +} + +//***************************************************************************** +// +//! \brief Get the sub second increment of the RTC. +//! +//! Get the value of the sub-second increment which is added to the RTC +//! absolute time on every clock tick. +//! +//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) +//! this value would stay the same across temperature. For temperatue +//! dependent clock sources like an RC oscillator, this value will change +//! over time if the application includes functionality for doing temperature +//! compensation of the RTC clock source. The default value corresponds to a +//! LF clock frequency of exactly 32.768 kHz. +//! +//! \return Returns the sub-second increment of the RTC added to the overall +//! value on every RTC clock tick. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCSubSecIncrGet(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC + NONSECURE_OFFSET)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 1. +//! +//! Set the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \note The default mode is compare. +//! +//! \param ui32Mode specifies the mode for channel 1. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \return None +//! +//! \sa AONRTCModeCh1Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh1Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || + (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 1. +//! +//! Get the operational mode of channel 1. It can be capture or compare mode. +//! In capture mode, an external event causes the value of the free running +//! counter to be stored, to remember the time of the event. +//! +//! \return Returns the operational mode of channel 1, one of: +//! - \ref AON_RTC_MODE_CH1_CAPTURE +//! - \ref AON_RTC_MODE_CH1_COMPARE +//! +//! \sa AONRTCModeCh1Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh1Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Set operational mode of channel 2. +//! +//! Set the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \note The default mode is normal compare. +//! +//! \param ui32Mode specifies the mode for channel 2. +//! The parameter must be one of the following: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCModeCh2Set(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || + (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); + + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; +} + +//***************************************************************************** +// +//! \brief Get operational mode of channel 2. +//! +//! Get the operational mode of channel 2. It can be in continuous compare +//! mode or normal compare mode. +//! In continuous mode, a value is automatically incremented to the channel 2 +//! compare register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! The increment value is set by the AONRTCIncValueCh2Set() call. +//! +//! \return Returns the operational mode of channel 2, i.e. one of: +//! - \ref AON_RTC_MODE_CH2_CONTINUOUS +//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE +//! +//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCModeCh2Get(void) +{ + return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); +} + +//***************************************************************************** +// +//! \brief Enable event operation for the specified channel. +//! +//! Enable the event generation for the specified channel. +//! +//! \note The RTC free running clock must also be enabled globally using the +//! AONRTCEnable() call. +//! +//! \param ui32Channel specifies one or more channels to enable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCEnable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelEnable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; + } +} + +//***************************************************************************** +// +//! \brief Disable event operation for the specified channel. +//! +//! Disable the event generation for the specified channel. +//! +//! \note The RTC free running clock can also be disabled globally using the +//! AONRTCDisable() call. +//! +//! \param ui32Channel specifies one or more channels to disable: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return None +//! +//! \sa AONRTCDisable() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCChannelDisable(uint32_t ui32Channel) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; + } +} + +//***************************************************************************** +// +//! \brief Set the compare value for the given channel. +//! +//! Set compare value for the specified channel. +//! +//! The format of the compare value is a 16 bit integer and 16 bit fractional +//! format <16 sec.16 subsec>. The current value of the RTC counter +//! can be retrieved in a format compatible to the compare register using +//! \ref AONRTCCurrentCompareValueGet() +//! +//! \param ui32Channel specifies one or more channels to set compare value for: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! \param ui32CompValue is the compare value to set for the specified channel. +//! - Format: <16 sec.16 subsec> +//! +//! \return None +//! +//! \sa AONRTCCurrentCompareValueGet() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) +{ + // Check the arguments. + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP + NONSECURE_OFFSET) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH1) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP + NONSECURE_OFFSET) = ui32CompValue; + } + + if(ui32Channel & AON_RTC_CH2) + { + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP + NONSECURE_OFFSET) = ui32CompValue; + } +} + +//***************************************************************************** +// +//! \brief Get the compare value for the given channel. +//! +//! Get compare value for the specified channel. +//! +//! \param ui32Channel specifies a channel. +//! The parameter must be one (and only one) of the following: +//! - \ref AON_RTC_CH0 +//! - \ref AON_RTC_CH1 +//! - \ref AON_RTC_CH2 +//! +//! \return Returns the stored compare value for the given channel. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCompareValueGet(uint32_t ui32Channel) +{ + uint32_t ui32Value = 0; + + // Check the arguments + ASSERT((ui32Channel == AON_RTC_CH0) || + (ui32Channel == AON_RTC_CH1) || + (ui32Channel == AON_RTC_CH2)); + + if(ui32Channel & AON_RTC_CH0) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP + NONSECURE_OFFSET); + } + + if(ui32Channel & AON_RTC_CH1) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP + NONSECURE_OFFSET); + } + + if(ui32Channel & AON_RTC_CH2) + { + ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP + NONSECURE_OFFSET); + } + + return(ui32Value); +} + +//***************************************************************************** +// +//! \brief Get the current value of the RTC counter in a format that matches +//! RTC compare values. +//! +//! The compare value registers contains 16 integer and 16 fractional bits. +//! This function will return the current value of the RTC counter in an +//! identical format. +//! +//! \return Returns the current value of the RTC counter in a <16.16> format +//! (SEC[15:0].SUBSEC[31:16]). +//! +//! \sa \ref AONRTCCompareValueSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCurrentCompareValueGet( void ) +{ + return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME + NONSECURE_OFFSET )); +} + +//***************************************************************************** +// +//! \brief Get the current 64-bit value of the RTC counter. +//! +//! \note Reading SEC both before and after SUBSEC in order to detect if SEC +//! incremented while reading SUBSEC. If SEC incremented, we can't be sure +//! which SEC the SUBSEC belongs to, so repeating the sequence then. +//! +//! \return Returns the current value of the RTC counter in a 64-bits format +//! (SEC[31:0].SUBSEC[31:0]). +// +//***************************************************************************** +extern uint64_t AONRTCCurrent64BitValueGet(void); + +//***************************************************************************** +// +//! \brief Set the channel 2 increment value when operating in continuous mode. +//! +//! Set the channel 2 increment value when operating in continuous mode. +//! The specified value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to generate +//! a series of completely equidistant events. +//! +//! \param ui32IncValue is the increment value when operating in continuous mode. +//! +//! \return None +//! +//! \sa AONRTCIncValueCh2Get() +// +//***************************************************************************** +__STATIC_INLINE void +AONRTCIncValueCh2Set(uint32_t ui32IncValue) +{ + HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC + NONSECURE_OFFSET) = ui32IncValue; +} + +//***************************************************************************** +// +//! \brief Get the channel2 increment value when operating in continuous mode. +//! +//! Get the channel 2 increment value, when channel 2 is operating in +//! continuous mode. +//! This value is automatically incremented to the channel 2 compare +//! register, upon a channel 2 compare event. This allows channel 2 to +//! generate a series of completely equidistant events. +//! +//! \return Returns the channel 2 increment value when operating in continuous +//! mode. +//! +//! \sa AONRTCIncValueCh2Set() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCIncValueCh2Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC + NONSECURE_OFFSET)); +} + +//***************************************************************************** +// +//! \brief Get the channel 1 capture value. +//! +//! Get the channel 1 capture value. +//! The upper 16 bits of the returned value is the lower 16 bits of the +//! integer part of the RTC timer. The lower 16 bits of the returned part +//! is the upper 16 bits of the fractional part. +//! +//! \return Returns the channel 1 capture value. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AONRTCCaptureValueCh1Get(void) +{ + return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT + NONSECURE_OFFSET)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AONRTCCurrent64BitValueGet + #undef AONRTCCurrent64BitValueGet + #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AON_RTC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc_doc.h new file mode 100644 index 00000000..e3c34306 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aon_rtc_doc.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aon_rtc_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aonrtc_api +//! @{ +//! \section sec_aonrtc Introduction +//! +//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.c new file mode 100644 index 00000000..afaace34 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.c @@ -0,0 +1,370 @@ +/****************************************************************************** +* Filename: aux_adc.c +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_adc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_fcfg1.h" +#include "adi.h" +#include "event.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXADCDisable + #define AUXADCDisable NOROM_AUXADCDisable + #undef AUXADCEnableAsync + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #undef AUXADCEnableSync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #undef AUXADCEnableSyncNoBugWorkaround + #define AUXADCEnableSyncNoBugWorkaround NOROM_AUXADCEnableSyncNoBugWorkaround + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #undef AUXADCFlushFifo + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Disables the ADC +// +//***************************************************************************** +void +AUXADCDisable(void) +{ + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +//***************************************************************************** +// +// Enables the ADC for asynchronous operation +// +//***************************************************************************** +void +AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Enables the ADC for synchronous operation +// +// On CC26X2, this function needs a different name to enable a wrapper function +// in flash to implement a workaround for a HW bug. +//***************************************************************************** +void +AUXADCEnableSyncNoBugWorkaround(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) +{ + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Enables the ADC for synchronous operation +// +//***************************************************************************** +void +AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) +{ + // The original AUXADCEnableSync() implementation requires a workaround, + // consisting of a delay, after its invocation. This delay is implemented by + // repeating the last ADI write operation three times. + // + // We need to make a call to the ROM symbol directly. Otherwise, the + // current build process will call the implementation in flash instead even + // if a ROM version is available. +#if defined(ROM_AUXADCEnableSyncNoBugWorkaround) && !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + ROM_AUXADCEnableSyncNoBugWorkaround(refSource, sampleTime, trigger); +#else + AUXADCEnableSyncNoBugWorkaround(refSource, sampleTime, trigger); +#endif + + + // Repeat this write another three times to add a delay. This is required + // to prevent the device from hanging if we generate a manual ADC trigger + // immediately after enabling the ADC and the Sensor Controller turns on + // or off the XOSC_HF as a reference for the TDC at the same time. + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +//***************************************************************************** +// +// Disables scaling of the ADC input +// +//***************************************************************************** +void +AUXADCDisableInputScaling(void) +{ + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +//***************************************************************************** +// +// Flushes the ADC FIFO +// +//***************************************************************************** +void +AUXADCFlushFifo(void) +{ + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +//***************************************************************************** +// +// Waits for and returns the first sample in the ADC FIFO +// +//***************************************************************************** +uint32_t +AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the first sample in the ADC FIFO, without waiting +// +//***************************************************************************** +uint32_t +AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +//***************************************************************************** +// +// Returns the gain value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentGain(uint32_t refSource) +{ + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +//***************************************************************************** +// +// Returns the offset value used when adjusting for ADC gain/offset +// +//***************************************************************************** +int32_t +AUXADCGetAdjustmentOffset(uint32_t refSource) +{ + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +//***************************************************************************** +// +// Converts an "ideal" ADC value to microvolts +// +//***************************************************************************** +int32_t +AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +//***************************************************************************** +// +// Converts a number of microvolts to corresponding "ideal" ADC value +// +//***************************************************************************** +int32_t +AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) +{ + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +//***************************************************************************** +// +// Performs ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +//***************************************************************************** +// +// Performs the inverse of the ADC value gain and offset adjustment +// +//***************************************************************************** +int32_t +AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) +{ + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.h new file mode 100644 index 00000000..3675faed --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_adc.h @@ -0,0 +1,658 @@ +/****************************************************************************** +* Filename: aux_adc.h +* +* Description: Defines and prototypes for the AUX Analog-to-Digital +* Converter +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxadc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_ADC_H__ +#define __AUX_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aux_anaif.h" +#include "rom.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXADCDisable NOROM_AUXADCDisable + #define AUXADCEnableAsync NOROM_AUXADCEnableAsync + #define AUXADCEnableSync NOROM_AUXADCEnableSync + #define AUXADCEnableSyncNoBugWorkaround NOROM_AUXADCEnableSyncNoBugWorkaround + #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling + #define AUXADCFlushFifo NOROM_AUXADCFlushFifo + #define AUXADCReadFifo NOROM_AUXADCReadFifo + #define AUXADCPopFifo NOROM_AUXADCPopFifo + #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset + #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts + #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue + #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset +#endif + +//***************************************************************************** +// +// Defines for ADC reference sources. +// +//***************************************************************************** +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) + +//***************************************************************************** +// +// Defines for the ADC FIFO status bits. +// +//***************************************************************************** +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) + +//***************************************************************************** +// +// Defines for supported ADC triggers. +// +//***************************************************************************** +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) +#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP) +#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP) +#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP) +#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP) +#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP) +#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP) +#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP) +#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP) + +//***************************************************************************** +// +// Defines for ADC sampling type for synchronous operation. +// +//***************************************************************************** +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 + +//***************************************************************************** +// +// Equivalent voltages for fixed ADC reference, in microvolts. +// +//***************************************************************************** +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief Disables the ADC. +//! +//! This function must be called: +//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or +//! \ref AUXADCEnableSync() +//! - Before entering system standby +// +//***************************************************************************** +extern void AUXADCDisable(void); + +//***************************************************************************** +// +//! \brief Enables the ADC for asynchronous operation. +//! +//! In asynchronous operation, the ADC samples continuously between +//! conversions. +//! +//! The ADC trigger starts the conversion. Note that the first conversion may +//! be invalid if the sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Enables the ADC for synchronous operation. +//! +//! In synchronous operation, the ADC is idle between a conversion and +//! subsequent samplings. +//! +//! The ADC trigger starts sampling with specified duration, followed by the +//! conversion. Note that the first conversion may be invalid if the initial +//! sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param sampleTime +//! ADC sampling time: +//! - \ref AUXADC_SAMPLE_TIME_2P7_US +//! - \ref AUXADC_SAMPLE_TIME_5P3_US +//! - \ref AUXADC_SAMPLE_TIME_10P6_US +//! - \ref AUXADC_SAMPLE_TIME_21P3_US +//! - \ref AUXADC_SAMPLE_TIME_42P6_US +//! - \ref AUXADC_SAMPLE_TIME_85P3_US +//! - \ref AUXADC_SAMPLE_TIME_170_US +//! - \ref AUXADC_SAMPLE_TIME_341_US +//! - \ref AUXADC_SAMPLE_TIME_682_US +//! - \ref AUXADC_SAMPLE_TIME_1P37_MS +//! - \ref AUXADC_SAMPLE_TIME_2P73_MS +//! - \ref AUXADC_SAMPLE_TIME_5P46_MS +//! - \ref AUXADC_SAMPLE_TIME_10P9_MS +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); + +//***************************************************************************** +// +//! The device can hang if we generate a manual ADC trigger +//! immediately after enabling the ADC with this function and the Sensor +//! Controller turns on or off the XOSC_HF as a reference for the TDC at the +//! same time. +//! +//! An application should be calling AUXADCEnableSync() instead. +//! +//! \brief Enables the ADC for synchronous operation. +//! +//! In synchronous operation, the ADC is idle between a conversion and +//! subsequent samplings. +//! +//! The ADC trigger starts sampling with specified duration, followed by the +//! conversion. Note that the first conversion may be invalid if the initial +//! sampling period is too short. +//! +//! ADC input scaling is enabled by default after device reset, and is also re- +//! enabled by \ref AUXADCDisable(). To disable input scaling, call +//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). +//! +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! \param sampleTime +//! ADC sampling time: +//! - \ref AUXADC_SAMPLE_TIME_2P7_US +//! - \ref AUXADC_SAMPLE_TIME_5P3_US +//! - \ref AUXADC_SAMPLE_TIME_10P6_US +//! - \ref AUXADC_SAMPLE_TIME_21P3_US +//! - \ref AUXADC_SAMPLE_TIME_42P6_US +//! - \ref AUXADC_SAMPLE_TIME_85P3_US +//! - \ref AUXADC_SAMPLE_TIME_170_US +//! - \ref AUXADC_SAMPLE_TIME_341_US +//! - \ref AUXADC_SAMPLE_TIME_682_US +//! - \ref AUXADC_SAMPLE_TIME_1P37_MS +//! - \ref AUXADC_SAMPLE_TIME_2P73_MS +//! - \ref AUXADC_SAMPLE_TIME_5P46_MS +//! - \ref AUXADC_SAMPLE_TIME_10P9_MS +//! \param trigger +//! ADC conversion trigger: +//! - \ref AUXADC_TRIGGER_MANUAL +//! - \ref AUXADC_TRIGGER_GPT0A +//! - \ref AUXADC_TRIGGER_GPT0B +//! - \ref AUXADC_TRIGGER_GPT1A +//! - \ref AUXADC_TRIGGER_GPT1B +//! - \ref AUXADC_TRIGGER_GPT2A +//! - \ref AUXADC_TRIGGER_GPT2B +//! - \ref AUXADC_TRIGGER_GPT3A +//! - \ref AUXADC_TRIGGER_GPT3B +// +//***************************************************************************** +extern void AUXADCEnableSyncNoBugWorkaround(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); + +//***************************************************************************** +// +//! \brief Disables scaling of the ADC input. +//! +//! By default, the ADC operates internally on a version of the input signal +//! that has been scaled down by a factor 1408 / 4095. This function +//! disables that scaling, allowing for a trade-off between dynamic range and +//! and resolution. +//! +//! \note This function must only be called while the ADC is disabled, before +//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). +//! \note Different input maximum ratings apply when input scaling is disabled. +//! Violating these may damage the device. +// +//***************************************************************************** +extern void AUXADCDisableInputScaling(void); + +//***************************************************************************** +// +//! \brief Flushes the ADC FIFO. +//! +//! This empties the FIFO and clears the underflow/overflow flags. +//! +//! Note: This function must only be called while the ADC is enabled. +// +//***************************************************************************** +extern void AUXADCFlushFifo(void); + +//***************************************************************************** +// +//! \brief Generates a single manual ADC trigger. +//! +//! For synchronous mode, the trigger starts sampling followed by conversion. +//! For asynchronous mode, the trigger starts conversion. +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCGenManualTrigger(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; +} + +//***************************************************************************** +// +//! \brief Returns flags indicating the status of the ADC FIFO. +//! +//! The flags indicate FIFO empty, full and almost full, and whether +//! overflow/underflow has occurred. +//! +//! \return +//! A combination (bitwise OR) of the following flags: +//! - \ref AUXADC_FIFO_EMPTY_M +//! - \ref AUXADC_FIFO_ALMOST_FULL_M +//! - \ref AUXADC_FIFO_FULL_M +//! - \ref AUXADC_FIFO_UNDERFLOW_M +//! - \ref AUXADC_FIFO_OVERFLOW_M +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXADCGetFifoStatus(void) +{ + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); +} + +//***************************************************************************** +// +//! \brief Waits for and returns the first sample in the ADC FIFO. +//! +//! This function waits until there is at least one sample in the ADC FIFO. It +//! then pops and returns the first sample from the FIFO. +//! +//! \note This procedure will deadlock if called without setting up ADC trigger +//! generation in advance. The trigger can either be manual or periodical +//! (using a GPT). +//! +//! \return The first (12-bit) sample from the ADC FIFO +// +//***************************************************************************** +extern uint32_t AUXADCReadFifo(void); + +//***************************************************************************** +// +//! \brief Returns the first sample in the ADC FIFO, without waiting. +//! +//! This function does not wait, and must only be called when there is at least +//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow +//! (\ref AUXADC_FIFO_UNDERFLOW_M). +//! +//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value +//! if the FIFO is empty +// +//***************************************************************************** +extern uint32_t AUXADCPopFifo(void); + +//***************************************************************************** +// +//! \brief Selects internal or external input for the ADC. +//! +//! Note that calling this function also selects the same input for AUX_COMPB. +//! +//! \param input +//! Internal/external input selection: +//! - \ref ADC_COMPB_IN_DCOUPL +//! - \ref ADC_COMPB_IN_VSS +//! - \ref ADC_COMPB_IN_VDDS +//! - \ref ADC_COMPB_IN_AUXIO7 +//! - \ref ADC_COMPB_IN_AUXIO6 +//! - \ref ADC_COMPB_IN_AUXIO5 +//! - \ref ADC_COMPB_IN_AUXIO4 +//! - \ref ADC_COMPB_IN_AUXIO3 +//! - \ref ADC_COMPB_IN_AUXIO2 +//! - \ref ADC_COMPB_IN_AUXIO1 +//! - \ref ADC_COMPB_IN_AUXIO0 +// +//***************************************************************************** +__STATIC_INLINE void +AUXADCSelectInput(uint32_t input) +{ + HapiSelectADCCompBInput(input); +} + +//***************************************************************************** +// +//! \brief Returns the gain value used when adjusting for ADC gain/offset. +//! +//! The function returns the gain value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during +//! chip manufacturing and is stored in the factory configuration, FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The gain value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Returns the offset value used when adjusting for ADC gain/offset. +//! +//! The function returns the offset value to be used with +//! \ref AUXADCAdjustValueForGainAndOffset() or +//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found +//! during chip manufacturing and is stored in the factory configuration, +//! FCFG1. +//! +//! \param refSource +//! ADC reference source: +//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) +//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) +//! +//! \return +//! The offset value to be used in adjustments +// +//***************************************************************************** +extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); + +//***************************************************************************** +// +//! \brief Converts an "adjusted" ADC value to microvolts. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param adcValue +//! The ADC value +//! +//! \return +//! The corresponding number of microvolts +// +//***************************************************************************** +extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); + +//***************************************************************************** +// +//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. +//! +//! This function can only be used when measuring with fixed ADC reference +//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for +//! whether the sampled ADC input is scaled down before conversion or not. +//! +//! \param fixedRefVoltage +//! Fixed reference voltage, in microvolts +//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) +//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input +//! \param microvolts +//! The number of microvolts +//! +//! \return +//! The corresponding expected ADC value (adjusted for ADC gain/offset) +// +//***************************************************************************** +extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); + +//***************************************************************************** +// +//! \brief Performs ADC value gain and offset adjustment. +//! +//! This function takes a measured ADC value compensates for the internal gain +//! and offset in the ADC. +//! +//! \param adcValue +//! 12-bit ADC unadjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC adjusted value +// +//***************************************************************************** +extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +//! \brief Performs the inverse of the ADC value gain and offset adjustment. +//! +//! This function finds the expected measured ADC value, without gain and +//! offset compensation, for a given "ideal" ADC value. The function can for +//! example be used to find ADC value thresholds to be used in Sensor +//! Controller task configurations. +//! +//! \param adcValue +//! 12-bit ADC adjusted value +//! \param gain +//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() +//! \param offset +//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() +//! +//! \return +//! 12-bit ADC unadjusted value +// +//***************************************************************************** +extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXADCDisable + #undef AUXADCDisable + #define AUXADCDisable ROM_AUXADCDisable + #endif + #ifdef ROM_AUXADCEnableAsync + #undef AUXADCEnableAsync + #define AUXADCEnableAsync ROM_AUXADCEnableAsync + #endif + #ifdef ROM_AUXADCEnableSync + #undef AUXADCEnableSync + #define AUXADCEnableSync ROM_AUXADCEnableSync + #endif + #ifdef ROM_AUXADCEnableSyncNoBugWorkaround + #undef AUXADCEnableSyncNoBugWorkaround + #define AUXADCEnableSyncNoBugWorkaround ROM_AUXADCEnableSyncNoBugWorkaround + #endif + #ifdef ROM_AUXADCDisableInputScaling + #undef AUXADCDisableInputScaling + #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling + #endif + #ifdef ROM_AUXADCFlushFifo + #undef AUXADCFlushFifo + #define AUXADCFlushFifo ROM_AUXADCFlushFifo + #endif + #ifdef ROM_AUXADCReadFifo + #undef AUXADCReadFifo + #define AUXADCReadFifo ROM_AUXADCReadFifo + #endif + #ifdef ROM_AUXADCPopFifo + #undef AUXADCPopFifo + #define AUXADCPopFifo ROM_AUXADCPopFifo + #endif + #ifdef ROM_AUXADCGetAdjustmentGain + #undef AUXADCGetAdjustmentGain + #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain + #endif + #ifdef ROM_AUXADCGetAdjustmentOffset + #undef AUXADCGetAdjustmentOffset + #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset + #endif + #ifdef ROM_AUXADCValueToMicrovolts + #undef AUXADCValueToMicrovolts + #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts + #endif + #ifdef ROM_AUXADCMicrovoltsToValue + #undef AUXADCMicrovoltsToValue + #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue + #endif + #ifdef ROM_AUXADCAdjustValueForGainAndOffset + #undef AUXADCAdjustValueForGainAndOffset + #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset + #endif + #ifdef ROM_AUXADCUnadjustValueForGainAndOffset + #undef AUXADCUnadjustValueForGainAndOffset + #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_ADC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.c new file mode 100644 index 00000000..e7603fe0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.c @@ -0,0 +1,305 @@ +/****************************************************************************** +* Filename: aux_dac.c +* +* Description: Driver for the AUX Digital-to-Analog Converter interface. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#include "aux_dac.h" + +/*********** Defines for values used in the DACSMPLCFG1 register. ***********/ + +// Number of inactive sample clock periods (0) between each active sample clock +// period during hold phase +#define SAMPLE_CLK_HOLD_PERIOD (0 << AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S) + +// Number of active sample clock periods (16) during the setup phase. +#define SAMPLE_CLK_SETUP_COUNT (15 << AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S) + +// This encoding means that the sample clock is held low for 4 periods. +#define SAMPLE_CLK_LOW_PERIOD (3 << AUX_ANAIF_DACSMPLCFG1_L_PER_S) + +// This encoding means that the sample clock is held high for 4 periods. +#define SAMPLE_CLK_HIGH_PERIOD (1 << AUX_ANAIF_DACSMPLCFG1_H_PER_S) + +//***************************************************************************** +// +// Sets the DAC's voltage reference +// +//***************************************************************************** +void +AUXDACSetVref(uint8_t refSource) +{ + HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) = refSource; + + if(refSource == AUXDAC_VREF_SEL_ADCREF) + { + // Enable the ADC reference module. + HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF0) |= ADI_4_AUX_ADCREF0_REF_ON_IDLE | ADI_4_AUX_ADCREF0_EN; + } +} + +//***************************************************************************** +// +// Enables precharge +// +//***************************************************************************** +void +AUXDACEnablePreCharge(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) |= AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN; +} + +//***************************************************************************** +// +// Disables precharge +// +//***************************************************************************** +void +AUXDACDisablePreCharge(void) +{ + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) &= ~(0x1 << AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S); +} + +//***************************************************************************** +// +// Returns maximum DAC voltage in uV +// +//***************************************************************************** +uint32_t +AUXDACCalcMax(void) +{ + uint32_t prechargeStatus; + uint32_t refSource; + uint32_t dacMax; + + // Depending on the selected DAC voltage reference, obtain calibration value C2 in millivolts. + refSource = ((HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) & ADI_4_AUX_MUX2_DAC_VREF_SEL_M) >> ADI_4_AUX_MUX2_DAC_VREF_SEL_S); + + switch (refSource) + { + // Nothing connected. Input is floating. + case AUXDAC_VREF_SEL_NC: + + dacMax = 0; + break; + + // Core Voltage Decoupling pin as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_DCOUPL: + + prechargeStatus = ((HWREG( AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) & AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M) >> AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S); + dacMax = (prechargeStatus == 0) ? ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL0) & FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M) >> FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S) \ + : ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL1) & FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M) >> FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S); + break; + + // ADC reference voltage as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_ADCREF: + + dacMax = ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL2) & FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M) >> FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S); + break; + + // Main supply voltage VDDS as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_VDDS: + + // Note: The calibration value is measured at a VDDS of 3.0V. If VDDS is selected as reference, + // measure VDDS and scale the calibration value. + dacMax = ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL3) & FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M) >> FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S); + break; + + // Nothing connected. Input is floating. + default: + + dacMax = 0; + } + + return dacMax; +} + +//***************************************************************************** +// +// Returns minimum DAC voltage in uV +// +//***************************************************************************** +uint32_t +AUXDACCalcMin(void) +{ + uint32_t refSource; + uint32_t prechargeStatus; + uint32_t dacMin; + + // Depending on the selected DAC voltage reference, obtain calibration value C1 in millivolts. + refSource = ((HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX2) & ADI_4_AUX_MUX2_DAC_VREF_SEL_M) >> ADI_4_AUX_MUX2_DAC_VREF_SEL_S); + + switch (refSource) + { + // Nothing connected. Input is floating. + case AUXDAC_VREF_SEL_NC: + dacMin = 0; + break; + + // Core Voltage Decoupling pin as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_DCOUPL: + + prechargeStatus = ((HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) & AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M) >> AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S); + dacMin = (prechargeStatus == 0) ? ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL0) & FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M) >> FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S) \ + : ((HWREG(FCFG1_BASE + FCFG1_O_DAC_CAL1) & FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M) >> FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S); + break; + + // ADC reference voltage as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_ADCREF: + dacMin = ((HWREG( FCFG1_BASE + FCFG1_O_DAC_CAL2) & FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M) >> FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S); + break; + + // Main supply voltage VDDS as the DAC's voltage reference source. + case AUXDAC_VREF_SEL_VDDS: + dacMin = ((HWREG( FCFG1_BASE + FCFG1_O_DAC_CAL3) & FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M) >> FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S); + break; + + // Nothing connected. Input is floating. + default: + + dacMin = 0; + } + + return dacMin; +} + +//***************************************************************************** +// +// Returns 8-bit DAC code from requested voltage in (uV) +// +//***************************************************************************** +uint32_t +AUXDACCalcCode(uint32_t uVoltOut, uint32_t uVoltOutMin, uint32_t uVoltOutMax) +{ + uint32_t dacCode = 0; + + if(uVoltOut != 0) + { + // Rounding (by adding 0.5 before truncating) + dacCode = (((254 * (uVoltOut - uVoltOutMin) * 2) / (uVoltOutMax - uVoltOutMin) + 1) / 2) + 1; + } + return (uint32_t)dacCode; +} + +//***************************************************************************** +// +// Sets the DAC sample clock +// +//***************************************************************************** +void +AUXDACSetSampleClock(uint8_t dacClkDiv) +{ + + // Set the peripheral operational rate to the AUX bus rate of 24 MHz. + HWREGB(AUX_SYSIF_BASE + AUX_SYSIF_O_PEROPRATE) |= AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE; + + // Configure sample base clock (SBCLK). SBCLK = 24 MHz / (dacClkDiv + 1). + // Max possible dacCLKDiv value = 63. + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCFG0) = dacClkDiv; + + // Configure DAC sample clock: + // + // - Set 16 active sample clock periods during setup phase. + // - Set 0 inactive sample clock periods between each active sample clock + // period during hold phase. + // - Set high and low hold period to 4, resulting in a DAC sample clock of + // SBCLK/8. + // + // This makes DAC clock frequency = (24 MHz / (dacCLKDiv + 1)) / 8 + + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCFG1) = (SAMPLE_CLK_HOLD_PERIOD)| + (SAMPLE_CLK_SETUP_COUNT)| + (SAMPLE_CLK_LOW_PERIOD)| + (SAMPLE_CLK_HIGH_PERIOD); +} + +//***************************************************************************** +// +// Sets the DAC's code +// +//***************************************************************************** +void +AUXDACSetCode(uint8_t dacCode) +{ + // Update the DAC's output value. + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACVALUE) = dacCode; +} + +//***************************************************************************** +// +// Enables the DAC +// +//***************************************************************************** +void +AUXDACEnable(uint8_t dacPinId) +{ + // Set the operational mode to active + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = AUX_SYSIF_OPMODEREQ_REQ_A; + + // Disable the low power bias control + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_LPMBIASCTL) = 0x0; + + // Enable the DAC sample clock + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCTL) = AUX_ANAIF_DACSMPLCTL_EN; + + // Enable DAC and buffer and set COMPA_IN + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) |= AUX_ANAIF_DACCTL_DAC_EN | AUX_ANAIF_DACCTL_DAC_BUFFER_EN | AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN; + + // Select COMPA output (0 will disconnect from DIOs) + HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX1) = dacPinId; +} + +//***************************************************************************** +// +// Disables the DAC +// +//***************************************************************************** +void +AUXDACDisable(void) +{ + // Disable the DAC sample clock + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACSMPLCTL) = 0x0; + + // Disable DAC, the DAC's buffer, and disconnect internally. + HWREGB(AUX_ANAIF_BASE + AUX_ANAIF_O_DACCTL) &= ~(0x1 << AUX_ANAIF_DACCTL_DAC_EN_S) & \ + ~(0x1 << AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S) & \ + ~(AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M << AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S); + + // Disconnect COMPA_IN from DIOs + HWREGB(AUX_ADI4_BASE + ADI_4_AUX_O_MUX1) = 0x0; + + // Set operational mode to Power-Down + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = AUX_SYSIF_OPMODEREQ_REQ_PDA; + + // Set the peripheral operational rate to the SCE rate + HWREGB(AUX_SYSIF_BASE + AUX_SYSIF_O_PEROPRATE) = AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.h new file mode 100644 index 00000000..437cb7d2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_dac.h @@ -0,0 +1,331 @@ +/****************************************************************************** +* Filename: aux_dac.h +* +* Description: Defines and prototypes for the AUX Digital-to-Analog +* Converter +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxdac_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_DAC_H__ +#define __AUX_DAC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aux_anaif.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_fcfg1.h" + + +//***************************************************************************** +// +// Defines for COMPA_IN connection to IO pins. +// +//***************************************************************************** +#define AUXDAC_COMPA_IN_NC 0x00 +#define AUXDAC_COMPA_IN_AUXIO26 0x01 +#define AUXDAC_COMPA_IN_AUXIO25 0x02 +#define AUXDAC_COMPA_IN_AUXIO24 0x04 +#define AUXDAC_COMPA_IN_AUXIO23 0x08 +#define AUXDAC_COMPA_IN_AUXIO22 0x10 +#define AUXDAC_COMPA_IN_AUXIO21 0x20 +#define AUXDAC_COMPA_IN_AUXIO20 0x40 +#define AUXDAC_COMPA_IN_AUXIO19 0x80 +#define AUXDAC_COMPA_IN_AUXIO7 AUXDAC_COMPA_IN_AUXIO26 +#define AUXDAC_COMPA_IN_AUXIO6 AUXDAC_COMPA_IN_AUXIO25 +#define AUXDAC_COMPA_IN_AUXIO5 AUXDAC_COMPA_IN_AUXIO24 +#define AUXDAC_COMPA_IN_AUXIO4 AUXDAC_COMPA_IN_AUXIO23 +#define AUXDAC_COMPA_IN_AUXIO3 AUXDAC_COMPA_IN_AUXIO22 +#define AUXDAC_COMPA_IN_AUXIO2 AUXDAC_COMPA_IN_AUXIO21 +#define AUXDAC_COMPA_IN_AUXIO1 AUXDAC_COMPA_IN_AUXIO20 +#define AUXDAC_COMPA_IN_AUXIO0 AUXDAC_COMPA_IN_AUXIO19 + +//***************************************************************************** +// +// Defines for DAC reference sources. +// +//***************************************************************************** +#define AUXDAC_VREF_SEL_VDDS ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS +#define AUXDAC_VREF_SEL_ADCREF ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF +#define AUXDAC_VREF_SEL_DCOUPL ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL +#define AUXDAC_VREF_SEL_NC ADI_4_AUX_MUX2_DAC_VREF_SEL_NC + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief Sets the voltage reference source. +//! +//! The DAC's output range depends on the selection of a voltage reference +//! source. This function must be called before enabling the DAC using +//! \ref AUXDACEnable() or before setting a DAC code using +//! \ref AUXDACCalcCode(). +//! +//! \param refSource +//! DAC voltage reference source: +//! - \ref AUXDAC_VREF_SEL_VDDS +//! - \ref AUXDAC_VREF_SEL_ADCREF +//! - \ref AUXDAC_VREF_SEL_DCOUPL +//! - \ref AUXDAC_VREF_SEL_NC +// +//***************************************************************************** +extern void AUXDACSetVref(uint8_t refSource); + +//***************************************************************************** +// +//! \brief Enables DAC precharge. +//! +//! If \ref AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference +//! source, the DAC's output voltage range can be further controlled by +//! enabling or disabling precharge. +//! +//! When precharge is enabled the DAC's output voltage will range from 1.28 V +//! to 2.56 V. +//! +//! \note This function must only be called if \ref AUXDAC_VREF_SEL_DCOUPL +//! has been selected as a voltage reference source and while the DAC is +//! disabled, before calling \ref AUXDACEnable(). +// +//***************************************************************************** +extern void AUXDACEnablePreCharge(void); + +//***************************************************************************** +// +//! \brief Disables DAC precharge. +//! +//! If \ref AUXDAC_VREF_SEL_DCOUPL has been selected as a voltage reference +//! source, the DAC's output voltage range can be further controlled by +//! enabling or disabling precharge. +//! +//! When precharge is disabled the DAC's output voltage will range from 0 V +//! to 1.28 V. +//! +//! \note This function must only be called if \ref AUXDAC_VREF_SEL_DCOUPL +//! has been selected as a voltage reference source and while the DAC is +//! disabled, before calling \ref AUXDACEnable(). +// +//***************************************************************************** +extern void AUXDACDisablePreCharge(void); + +//***************************************************************************** +// +//! \brief Calculates the upper limit voltage the DAC can output. +//! +//! This function uses calibration coefficients stored in the factory +//! configuration area (FCFG1) to determine the DAC's output voltage that +//! corresponds to DAC code 255. This voltage depends on the selected voltage +//! reference source. +//! +//! \note This function must only be called after \ref AUXDACSetVref has been +//! called. +//! +//! \return +//! The maximum voltage in mV that the DAC can output given a specific +//! reference voltage. +// +//***************************************************************************** +extern uint32_t AUXDACCalcMax(void); + +//***************************************************************************** +// +//! \brief Calculates the lower limit voltage the DAC can output. +//! +//! This function uses calibration coefficients stored in the factory +//! configuration area (FCFG1) to determine the DAC's output voltage that +//! corresponds to DAC code 1. This voltage depends on the selected voltage +//! reference source. +//! +//! DAC Code 0 corresponds to 0 V. Therefore, the DAC can only output 0 V and +//! values between the lower limit defined by this function and the upper limit +//! defined by \ref AUXDACCalcMax. +//! +//! \note This function must only be called after \ref AUXDACSetVref has been +//! called. +//! +//! \return +//! The minimum voltage (other than 0 V) in mV that the DAC can output +//! given a specific reference voltage. +// +//***************************************************************************** +extern uint32_t AUXDACCalcMin(void); + +//***************************************************************************** +// +//! \brief Calculates the appropriate DAC code for a specific voltage value. +//! +//! Once a voltage reference source has been selected with \ref AUXDACSetVref +//! and the DAC's output voltage range has been defined with \ref AUXDACCalcMin +//! and \ref AUXDACCalcMax, a DAC code can be derived. +//! +//! \param uVoltOut +//! The desired output voltage in millivolts [mV]. +//! \param uVoltOutMin +//! The minimum output voltage in millivolts [mV] which can be output by +//! the DAC in the current configuration. It should be the value returned +//! by \ref AUXDACCalcMin. +//! \param uVoltOutMax +//! The maximum output voltage in millivolts [mV] which can be output by +//! the DAC in the current configuration. It should be the value returned +//! by \ref AUXDACCalcMax. +//! \return +//! The dac code corresponding to the desired output value. +// +//***************************************************************************** +extern uint32_t AUXDACCalcCode(uint32_t uVoltOut, uint32_t uVoltOutMin, uint32_t uVoltOutMax); + +//***************************************************************************** +// +//! \brief Configures and sets the DAC sample clock. +//! +//! This function determines the sample clock frequency assuming that +//! the operational rate for the DAC sample clock state machine is the AUX Bus +//! Rate. + +//! AUX Bus frequency (24 MHz) divided by (dacClkDiv + 1) determines the sample +//! base clock frequency(SBCLK). +//! +//! In this implementation, the high and low hold period (H_PER and L_PER) are +//! both set to 4 periods, resulting in a DAC sample clock of SBCLK/8. +//! +//! The formula (24 MHz / (dacCLKDiv +1)) / 8 describes the final DAC Sample +//! Clock Frequency. For example, dacCLKDiv = 11 gives SBCLK frequency = 24 MHz +//! / (11+1) = 2 MHz, which gives DAC sample clock frequency = 2 MHz / 8 = 250 +//! KHz. +//! +//! \note The max sample clock frequency supported by the DAC is 1 MHz for +//! internal load and 250 kHz for external load. The current implementation of +//! the DAC driver assumes that it will be used to drive an internal load. +//! Please refer to the register description before changing sample clock +//! configuration settings. The DAC may behave unexpectedly if the sample clock +//! operates at unsupported frequencies. +//! +//! \note This function must be called before \ref AUXDACEnable. +//! +//! \param dacClkDiv The clock division factor +// +//***************************************************************************** +extern void AUXDACSetSampleClock(uint8_t dacClkDiv); + +//***************************************************************************** +// +//! \brief Updates the current DAC code. +//! +//! This function is meant to be used after \ref AUXDACEnable has been +//! called. It allows to update the DAC code by rapidly disabling the DAC, +//! setting the new DAC code, and then rapidly re-enabling the DAC. +//! +//! \param dacCode +//! The new DAC code +// +//***************************************************************************** +extern void AUXDACSetCode(uint8_t dacCode); + +//***************************************************************************** +// +//! \brief Enables the DAC. +//! +//! This function enables the DAC sample clock and the DAC buffer. It selects +//! COMPA_IN as output, and it routes the DAC's output to the given I/O pin. +//! +//! \param dacPinId +//! Analog capable I/O pin: +//! - \ref AUXDAC_COMPA_IN_AUXIO26 +//! - \ref AUXDAC_COMPA_IN_AUXIO25 +//! - \ref AUXDAC_COMPA_IN_AUXIO24 +//! - \ref AUXDAC_COMPA_IN_AUXIO23 +//! - \ref AUXDAC_COMPA_IN_AUXIO22 +//! - \ref AUXDAC_COMPA_IN_AUXIO21 +//! - \ref AUXDAC_COMPA_IN_AUXIO20 +//! - \ref AUXDAC_COMPA_IN_AUXIO19 +// +//***************************************************************************** +extern void AUXDACEnable(uint8_t dacPinId); + +//***************************************************************************** +// +//! \brief Disables the DAC. +//! +//! This function disables the DAC sample clock, the DAC buffer, the DAC. +//! It also disconnects COMPA_IN internally. +//! +//! \note This function must be called only after \ref AUXDACEnable has been +//! called. +// +//***************************************************************************** +extern void AUXDACDisable(void); + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_DAC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.c new file mode 100644 index 00000000..bdd31bcb --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: aux_smph.c +* +* Description: Driver for the AUX Semaphore. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_smph.h" + +// See aux_smph.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.h new file mode 100644 index 00000000..ee615352 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_smph.h @@ -0,0 +1,256 @@ +/****************************************************************************** +* Filename: aux_smph.h +* +* Description: Defines and prototypes for the AUX Semaphore +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsmph_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SMPH_H__ +#define __AUX_SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire an AUX semaphore. +//! +//! This function acquires the given AUX semaphore, blocking the call until +//! the semaphore is available. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // Wait for semaphore to be released such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. AUX_SMPH_CLAIMED). + while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == + AUX_SMPH_CLAIMED) + { + } +} + +//***************************************************************************** +// +//! \brief Try to acquire an AUX semaphore. +//! +//! This function tries to acquire the given AUX semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return Returns true if semaphore was acquired, false otherwise +//! +//! \sa AUXSMPHAcquire(), AUXSMPHRelease() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXSMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // AUX Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE when read) but subsequent reads will read 0. + ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == AUX_SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release an AUX semaphore by System CPU master. +//! +//! This function releases the given AUX semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \note The semaphore can also be acquired by the dedicated Sensor Controller. +//! The System CPU master can thus be competing for the shared resource, i.e. +//! the specified semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref AUX_SMPH_0 +//! - \ref AUX_SMPH_1 +//! - \ref AUX_SMPH_2 +//! - \ref AUX_SMPH_3 +//! - \ref AUX_SMPH_4 +//! - \ref AUX_SMPH_5 +//! - \ref AUX_SMPH_6 +//! - \ref AUX_SMPH_7 +//! +//! \return None +//! +//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() +// +//***************************************************************************** +__STATIC_INLINE void +AUXSMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == AUX_SMPH_0) || + (ui32Semaphore == AUX_SMPH_1) || + (ui32Semaphore == AUX_SMPH_2) || + (ui32Semaphore == AUX_SMPH_3) || + (ui32Semaphore == AUX_SMPH_4) || + (ui32Semaphore == AUX_SMPH_5) || + (ui32Semaphore == AUX_SMPH_6) || + (ui32Semaphore == AUX_SMPH_7)); + + // No check before release. It is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = + AUX_SMPH_FREE; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.c new file mode 100644 index 00000000..aab24814 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.c @@ -0,0 +1,95 @@ +/****************************************************************************** +* Filename: aux_sysif.c +* +* Description: Driver for the AUX System Interface +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_sysif.h" +#include "../inc/hw_memmap_common.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXSYSIFOpModeChange + #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange +#endif + + +//***************************************************************************** +// +// Used in AUXSYSIFOpModeChange() to control the change of the operational mode. +// +//***************************************************************************** +static const uint8_t g_OpMode_to_order[4] = {1,2,0,3}; +static const uint8_t g_Order_to_OpMode[4] = {2,0,1,3}; + +//***************************************************************************** +// +// Controls AUX operational mode change +// +//***************************************************************************** +void +AUXSYSIFOpModeChange(uint32_t targetOpMode) +{ + uint32_t currentOpMode; + uint32_t currentOrder; + uint32_t nextMode; + + // Check the argument + ASSERT((targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDLP)|| + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDA) || + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_LP) || + (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_A)); + + do { + currentOpMode = HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEREQ); + while ( currentOpMode != HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEACK)); + if (currentOpMode != targetOpMode) + { + currentOrder = g_OpMode_to_order[currentOpMode]; + if ( currentOrder < g_OpMode_to_order[targetOpMode]) + { + nextMode = g_Order_to_OpMode[currentOrder + 1]; + } + else + { + nextMode = g_Order_to_OpMode[currentOrder - 1]; + } + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_OPMODEREQ) = nextMode; + } + } while ( currentOpMode != targetOpMode ); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.h new file mode 100644 index 00000000..58a3ae44 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_sysif.h @@ -0,0 +1,152 @@ +/****************************************************************************** +* Filename: aux_sysif.h +* +* Description: Defines and prototypes for the AUX System Interface +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxsysif_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_SYSIF_H__ +#define __AUX_SYSIF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_aux_sysif.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange +#endif + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +// Defines for AUX operational modes. +// +//***************************************************************************** +#define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP) +#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA) +#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP) +#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A) + +//***************************************************************************** +// +//! \brief Changes the AUX operational mode to the requested target mode. +//! +//! This function controls the change of the AUX operational mode. +//! The function controls the change of the current operational mode to the +//! operational mode target by adhering to rules specified by HW. +//! +//! \param targetOpMode +//! AUX operational mode: +//! - \ref AUX_SYSIF_OPMODE_TARGET_PDLP (Powerdown operational mode with wakeup to lowpower mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_PDA (Powerdown operational mode with wakeup to active mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_LP (Lowpower operational mode) +//! - \ref AUX_SYSIF_OPMODE_TARGET_A (Active operational mode) +//! +//! \return None +// +//***************************************************************************** +extern void AUXSYSIFOpModeChange(uint32_t targetOpMode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXSYSIFOpModeChange + #undef AUXSYSIFOpModeChange + #define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SYSIF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.c new file mode 100644 index 00000000..21907d4d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.c @@ -0,0 +1,109 @@ +/****************************************************************************** +* Filename: aux_tdc.c +* +* Description: Driver for the AUX Time to Digital Converter interface. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "aux_tdc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef AUXTDCConfigSet + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Configure the operation of the AUX TDC +// +//***************************************************************************** +void +AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +//***************************************************************************** +// +// Check if the AUX TDC is done measuring +// +//***************************************************************************** +uint32_t +AUXTDCMeasurementDone(uint32_t ui32Base) +{ + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.h new file mode 100644 index 00000000..ceaf93db --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/aux_tdc.h @@ -0,0 +1,902 @@ +/****************************************************************************** +* Filename: aux_tdc.h +* +* Description: Defines and prototypes for the AUX Time-to-Digital Converter +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup aux_group +//! @{ +//! \addtogroup auxtdc_api +//! @{ +// +//***************************************************************************** + +#ifndef __AUX_TDC_H__ +#define __AUX_TDC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aux_tdc.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define AUXTDCConfigSet NOROM_AUXTDCConfigSet + #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#endif + +//***************************************************************************** +// +// Defines for the status of a AUX TDC measurement. +// +//***************************************************************************** +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 + +//***************************************************************************** +// +// Defines for the control of a AUX TDC. +// +//***************************************************************************** +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 + +//***************************************************************************** +// +// Defines for possible states of the TDC internal state machine. +// +//***************************************************************************** +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) + +//***************************************************************************** +// +// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). +// +//***************************************************************************** +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event + +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16) +#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17) +#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18) +#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19) +#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20) +#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21) +#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22) +#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23) +#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24) +#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25) +#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26) +#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27) +#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28) +#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29) +#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30) +#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31) +#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV) +#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ) +#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF) +#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN) +#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE) +#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE) +#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0) +#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1) +#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2) +#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3) +#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE) +#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ) +#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) + +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event + +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16) +#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17) +#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18) +#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19) +#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20) +#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21) +#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22) +#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23) +#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24) +#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25) +#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26) +#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27) +#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28) +#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29) +#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30) +#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31) +#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV) +#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ) +#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF) +#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN) +#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE) +#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE) +#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0) +#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1) +#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2) +#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3) +#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE) +#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ) +#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE) +#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) + +//***************************************************************************** +// +// Defines for the possible saturation values set using AUXTDCLimitSet(). +// +//***************************************************************************** +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! \brief Checks an AUX TDC base address. +//! +//! This function determines if a AUX TDC port base address is valid. +//! +//! \param ui32Base is the base address of the AUX TDC port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +AUXTDCBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_TDC_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Get the status of the AUX TDC internal state machine. +//! +//! This function will return the current state of the AUX TDC internal state +//! machine. +//! \param ui32Base is base address of the AUX TDC +//! +//! \return Returns the current state of the state machine. +//! Possible states for the state machine are: +//! - \ref AUXTDC_WAIT_START +//! - \ref AUXTDC_WAIT_START_CNTEN +//! - \ref AUXTDC_IDLE +//! - \ref AUXTDC_CLRCNT +//! - \ref AUXTDC_WAIT_STOP +//! - \ref AUXTDC_WAIT_STOP_CNTDOWN +//! - \ref AUXTDC_GETRESULTS +//! - \ref AUXTDC_POR +//! - \ref AUXTDC_WAIT_CLRCNT_DONE +//! - \ref AUXTDC_START_FALL +//! - \ref AUXTDC_FORCE_STOP. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the status value for the correct ADI Slave. + return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> + AUX_TDC_STAT_STATE_S); +} + +//***************************************************************************** +// +//! \brief Configure the operation of the AUX TDC. +//! +//! Use this function to configure the start and stop event for the AUX TDC. +//! +//! The \c ui32StartCondition must be a bitwise OR of the start event and the +//! polarity of the start event. The start events are: +//! - \ref AUXTDC_START_AUXIO0 +//! - \ref AUXTDC_START_AUXIO1 +//! - \ref AUXTDC_START_AUXIO2 +//! - \ref AUXTDC_START_AUXIO3 +//! - \ref AUXTDC_START_AUXIO4 +//! - \ref AUXTDC_START_AUXIO5 +//! - \ref AUXTDC_START_AUXIO6 +//! - \ref AUXTDC_START_AUXIO7 +//! - \ref AUXTDC_START_AUXIO8 +//! - \ref AUXTDC_START_AUXIO9 +//! - \ref AUXTDC_START_AUXIO10 +//! - \ref AUXTDC_START_AUXIO11 +//! - \ref AUXTDC_START_AUXIO12 +//! - \ref AUXTDC_START_AUXIO13 +//! - \ref AUXTDC_START_AUXIO14 +//! - \ref AUXTDC_START_AUXIO15 +//! - \ref AUXTDC_START_AUXIO16 +//! - \ref AUXTDC_START_AUXIO17 +//! - \ref AUXTDC_START_AUXIO18 +//! - \ref AUXTDC_START_AUXIO19 +//! - \ref AUXTDC_START_AUXIO20 +//! - \ref AUXTDC_START_AUXIO21 +//! - \ref AUXTDC_START_AUXIO22 +//! - \ref AUXTDC_START_AUXIO23 +//! - \ref AUXTDC_START_AUXIO24 +//! - \ref AUXTDC_START_AUXIO25 +//! - \ref AUXTDC_START_AUXIO26 +//! - \ref AUXTDC_START_AUXIO27 +//! - \ref AUXTDC_START_AUXIO28 +//! - \ref AUXTDC_START_AUXIO29 +//! - \ref AUXTDC_START_AUXIO30 +//! - \ref AUXTDC_START_AUXIO31 +//! - \ref AUXTDC_START_MANUAL_EV +//! - \ref AUXTDC_START_AON_RTC_CH2_DLY +//! - \ref AUXTDC_START_AON_RTC_4KHZ +//! - \ref AUXTDC_START_AON_BATMON_BAT_UPD +//! - \ref AUXTDC_START_AON_BATMON_TEMP_UPD +//! - \ref AUXTDC_START_SCLK_LF +//! - \ref AUXTDC_START_PWR_DWN +//! - \ref AUXTDC_START_MCU_ACTIVE +//! - \ref AUXTDC_START_VDDR_RECHARGE +//! - \ref AUXTDC_START_TIMER2_EV0 +//! - \ref AUXTDC_START_TIMER2_EV1 +//! - \ref AUXTDC_START_TIMER2_EV2 +//! - \ref AUXTDC_START_TIMER2_EV3 +//! - \ref AUXTDC_START_TIMER2_PULSE +//! - \ref AUXTDC_START_TDC_DONE +//! - \ref AUXTDC_START_ADC_IRQ +//! - \ref AUXTDC_START_ADC_FIFO_NOT_EMPTY +//! - \ref AUXTDC_START_NO_EVENT +//! - \ref AUXTDC_START_ADC_DONE +//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_START_ISRC_RESET +//! - \ref AUXTDC_START_OBSMUX0 +//! - \ref AUXTDC_START_OBSMUX1 +//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_START_TDC_PRE +//! - \ref AUXTDC_START_TIMER0_EV +//! - \ref AUXTDC_START_TIMER1_EV +//! - \ref AUXTDC_START_AON_RTC_CH2 +//! - \ref AUXTDC_START_AUX_COMPA +//! - \ref AUXTDC_START_AUX_COMPB +//! - \ref AUXTDC_START_ACLK_REF +//! - \ref AUXTDC_START_MCU_EV +//! +//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS +//! or falling \ref AUXTDC_STARTPOL_FALL. +//! +//! The \c ui32StopCondition must be a bitwise OR of the stop event and the +//! polarity of the stop event. The stop events are: +//! - \ref AUXTDC_STOP_AUXIO0 +//! - \ref AUXTDC_STOP_AUXIO1 +//! - \ref AUXTDC_STOP_AUXIO2 +//! - \ref AUXTDC_STOP_AUXIO3 +//! - \ref AUXTDC_STOP_AUXIO4 +//! - \ref AUXTDC_STOP_AUXIO5 +//! - \ref AUXTDC_STOP_AUXIO6 +//! - \ref AUXTDC_STOP_AUXIO7 +//! - \ref AUXTDC_STOP_AUXIO8 +//! - \ref AUXTDC_STOP_AUXIO9 +//! - \ref AUXTDC_STOP_AUXIO10 +//! - \ref AUXTDC_STOP_AUXIO11 +//! - \ref AUXTDC_STOP_AUXIO12 +//! - \ref AUXTDC_STOP_AUXIO13 +//! - \ref AUXTDC_STOP_AUXIO14 +//! - \ref AUXTDC_STOP_AUXIO15 +//! - \ref AUXTDC_STOP_AUXIO16 +//! - \ref AUXTDC_STOP_AUXIO17 +//! - \ref AUXTDC_STOP_AUXIO18 +//! - \ref AUXTDC_STOP_AUXIO19 +//! - \ref AUXTDC_STOP_AUXIO20 +//! - \ref AUXTDC_STOP_AUXIO21 +//! - \ref AUXTDC_STOP_AUXIO22 +//! - \ref AUXTDC_STOP_AUXIO23 +//! - \ref AUXTDC_STOP_AUXIO24 +//! - \ref AUXTDC_STOP_AUXIO25 +//! - \ref AUXTDC_STOP_AUXIO26 +//! - \ref AUXTDC_STOP_AUXIO27 +//! - \ref AUXTDC_STOP_AUXIO28 +//! - \ref AUXTDC_STOP_AUXIO29 +//! - \ref AUXTDC_STOP_AUXIO30 +//! - \ref AUXTDC_STOP_AUXIO31 +//! - \ref AUXTDC_STOP_MANUAL_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2_DLY +//! - \ref AUXTDC_STOP_AON_RTC_4KHZ +//! - \ref AUXTDC_STOP_AON_BATMON_BAT_UPD +//! - \ref AUXTDC_STOP_AON_BATMON_TEMP_UPD +//! - \ref AUXTDC_STOP_SCLK_LF +//! - \ref AUXTDC_STOP_PWR_DWN +//! - \ref AUXTDC_STOP_MCU_ACTIVE +//! - \ref AUXTDC_STOP_VDDR_RECHARGE +//! - \ref AUXTDC_STOP_TIMER2_EV0 +//! - \ref AUXTDC_STOP_TIMER2_EV1 +//! - \ref AUXTDC_STOP_TIMER2_EV2 +//! - \ref AUXTDC_STOP_TIMER2_EV3 +//! - \ref AUXTDC_STOP_TIMER2_PULSE +//! - \ref AUXTDC_STOP_TDC_DONE +//! - \ref AUXTDC_STOP_ADC_IRQ +//! - \ref AUXTDC_STOP_ADC_FIFO_NOT_EMPTY +//! - \ref AUXTDC_STOP_NO_EVENT +//! - \ref AUXTDC_STOP_ADC_DONE +//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL +//! - \ref AUXTDC_STOP_ISRC_RESET +//! - \ref AUXTDC_STOP_OBSMUX0 +//! - \ref AUXTDC_STOP_OBSMUX1 +//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE +//! - \ref AUXTDC_STOP_TDC_PRE +//! - \ref AUXTDC_STOP_TIMER0_EV +//! - \ref AUXTDC_STOP_TIMER1_EV +//! - \ref AUXTDC_STOP_AON_RTC_CH2 +//! - \ref AUXTDC_STOP_AUX_COMPA +//! - \ref AUXTDC_STOP_AUX_COMPB +//! - \ref AUXTDC_STOP_ACLK_REF +//! - \ref AUXTDC_STOP_MCU_EV +//! +//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS +//! or falling \ref AUXTDC_STOPPOL_FALL. +//! +//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle +//! state. To ensure that software does not lock up, it is recommended to +//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). +//! This can be tested using \ref AUXTDCIdle(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. +//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. +//! +//! \return None +//! +//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() +// +//***************************************************************************** +extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, + uint32_t ui32StopCondition); + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is in idle mode. +//! +//! This function can be used to check whether the AUX TDC internal state +//! machine is in idle mode. This is required before setting the polarity +//! of the start and stop event. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns \c true if state machine is in idle and returns \c false +//! if the state machine is in any other state. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCIdle(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in the Idle state. + return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enable the AUX TDC for a measurement. +//! +//! This function is used for arming the AUX TDC to begin a measurement as +//! soon as the start condition is met. There are two run modes: +//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before +//! starting measurement on next rising edge of start. This guarantees an edge +//! triggered start and is recommended for frequency measurements. If the +//! first falling edge is close to the start command it may be missed, but +//! the TDC shall catch later falling edges and in any case guarantee a +//! measurement start synchronous to the rising edge of the start event. +//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using +//! this a TDC measurement may start immediately if start is high and hence it +//! may not give precise edge to edge measurements. This mode is only +//! recommended when start pulse is guaranteed to arrive at least 7 clock +//! periods after command. +//! +//! \note The AUX TDC should be configured and in Idle mode before calling this +//! function. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! \param ui32RunMode is the run mode for the AUX TDC. +//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. +//! - \ref AUX_TDC_RUN : Asynchronous run mode. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT((ui32RunMode == AUX_TDC_RUN) || + (ui32RunMode == AUX_TDC_RUNSYNC)); + + // Enable the AUX TDC. + HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; +} + +//***************************************************************************** +// +//! \brief Force the AUX TDC back to Idle mode. +//! +//! This function will force the AUX TDC in Idle mode. The internal state +//! machine will not go directly to Idle mode, so it is left to the programmer to +//! ensure that the state machine is in Idle mode before doing any new +//! configuration. This can be checked using \ref AUXTDCIdle(). +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return None +//! +//! \sa \ref AUXTDCIdle() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCIdleForce(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Abort operation of AUX TDC and force into Idle mode. + HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; +} + +//***************************************************************************** +// +//! \brief Check if the AUX TDC is done measuring. +//! +//! This function can be used to check whether the AUX TDC has finished a +//! measurement. The AUX TDC may have completed a measurement for two reasons. +//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout +//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function +//! will return \ref AUX_TDC_BUSY. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the current status of a measurement: +//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. +//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. +//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. +// +//***************************************************************************** +extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Get the value of the latest measurement. +//! +//! This function is used for retrieving the value of the latest measurement +//! performed by the AUX TDC. +//! +//! \param ui32Base is the base address of the AUX TDC. +//! +//! \return Returns the result of the latest measurement. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCMeasurementGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the measurement. + return (HWREG(ui32Base + AUX_TDC_O_RESULT)); +} + +//***************************************************************************** +// +//! \brief Set the saturation limit of the measurement. +//! +//! This function is used to set a saturation limit for the event accumulation +//! register. The saturation limit is defined as a bit width of the +//! accumulation register and therefore increases in power of 2. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Limit is the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 (default) +//! +//! \return None +//! +//! \note The actual value of the accumulation register might increase slightly beyond +//! the saturation value before the saturation takes effect. +//! +//! \sa \ref AUXTDCLimitGet() +// +//***************************************************************************** +__STATIC_INLINE void +AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); + + // Set the saturation limit. + HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; +} + +//***************************************************************************** +// +//! \brief Get the saturation limit of the measurement. +//! +//! This function is used to retrieve the current saturation for the +//! accumulator register. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the saturation limit. +//! - \ref AUXTDC_SAT_4096 +//! - \ref AUXTDC_SAT_8192 +//! - \ref AUXTDC_SAT_16384 +//! - \ref AUXTDC_SAT_32768 +//! - \ref AUXTDC_SAT_65536 +//! - \ref AUXTDC_SAT_131072 +//! - \ref AUXTDC_SAT_262144 +//! - \ref AUXTDC_SAT_524288 +//! - \ref AUXTDC_SAT_1048576 +//! - \ref AUXTDC_SAT_2097152 +//! - \ref AUXTDC_SAT_4194304 +//! - \ref AUXTDC_SAT_8388608 +//! - \ref AUXTDC_SAT_16777216 +//! +//! \sa \ref AUXTDCLimitSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCLimitGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the saturation limit. + return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); +} + +//***************************************************************************** +// +//! \brief Enables the counter if possible. +//! +//! This function can be used to enable the AUX TDC stop/compare event counter. +//! The counter can be used to measure multiple periods of a clock signal. +//! For each stop/compare event the counter will be decremented by one and +//! the measurement will continue running until the value of the counter +//! reaches 0. The current value of the counter can be read using +//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using +//! \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully enabled. If the +//! AUX TDC is not in Idle mode, the counter can not be enabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter + // will not be enabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Enable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + // Counter successfully enabled. + return true; +} + +//***************************************************************************** +// +//! \brief Disables the counter if possible. +//! +//! This function can be used to disable the AUX TDC stop/compare event counter. +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns \c true if the counter was successfully disabled. If the +//! AUX TDC is not in Idle mode, the counter can not be disabled, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Disable the counter. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; + + // Counter successfully disabled. + return true; +} + +//***************************************************************************** +// +//! \brief Set the reset number of counter compare/stop event to ignore before taking +//! a measurement. +//! +//! This function loads the reset value of the counter with the specified +//! number of events to ignore. A reset in this context means the counter +//! has been disabled and then enabled. +//! +//! \param ui32Base is base address of the AUX TDC. +//! \param ui32Events is the number of compare/stop events to load into the +//! counter. +//! +//! \return Returns \c true if the counter was successfully updated. If the +//! AUX TDC is not in Idle mode, the counter can not be updated, and the +//! return value will be \c false. +//! +//! \sa \ref AUXTDCCounterEnable() +// +//***************************************************************************** +__STATIC_INLINE bool +AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is in idle mode. If not in idle mode, the counter + // will not be disabled. + if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + return false; + } + + // Update the reset counter value. + HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; + + // Counter successfully updated. + return true; +} + +//***************************************************************************** +// +//! \brief Get the current number of counter compare/stop event to ignore before +//! taking a measurement. +//! +//! This function returns the current value of compare/stop events before +//! a measurement is registered. This value is decremented by one for each +//! registered compare/stop event and will always be less than or equal the +//! reset value of the counter set using \ref AUXTDCCounterSet(). +//! +//! \param ui32Base is base address of the AUX TDC. +//! +//! \return Returns the current value of compare/stop events ignored before a +//! measurement is performed. +//! +//! \sa \ref AUXTDCCounterEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +AUXTDCCounterGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Return the current counter value. + return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_AUXTDCConfigSet + #undef AUXTDCConfigSet + #define AUXTDCConfigSet ROM_AUXTDCConfigSet + #endif + #ifdef ROM_AUXTDCMeasurementDone + #undef AUXTDCMeasurementDone + #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_TDC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.c new file mode 100644 index 00000000..279a7f7c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: ccfgread.c +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ccfgread.h" + +// See ccfgread.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.h new file mode 100644 index 00000000..b33c2aec --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread.h @@ -0,0 +1,219 @@ +/****************************************************************************** +* Filename: ccfgread.h +* +* Description: API for reading CCFG. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ccfgread_api +//! @{ +// +//***************************************************************************** + +#ifndef __CCFGREAD_H__ +#define __CCFGREAD_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ccfg.h" + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Read DIS_GPRAM from CCFG. +//! +//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// +//***************************************************************************** +__STATIC_INLINE bool +CCFGRead_DIS_GPRAM( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; +} + +//***************************************************************************** +// +//! \brief Read EXT_LF_CLK_DIO from CCFG. +//! +//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_EXT_LF_CLK_DIO( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & + CCFG_EXT_LF_CLK_DIO_M ) >> + CCFG_EXT_LF_CLK_DIO_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() +// +//***************************************************************************** +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) + +//***************************************************************************** +// +//! \brief Read SCLK_LF_OPTION from CCFG. +//! +//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field. +//! Returns one of the following: +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF +//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF +//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_SCLK_LF_OPTION( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; +} + +//***************************************************************************** +// +// Defines the possible values returned from CCFGRead_XOSC_FREQ() +// +//***************************************************************************** +#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_TCXO ( CCFG_MODE_CONF_XOSC_FREQ_TCXO >> CCFG_MODE_CONF_XOSC_FREQ_S ) + +//***************************************************************************** +// +//! \brief Read XOSC_FREQ setting CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field. +//! Returns one of the following: +//! - \ref CCFGREAD_XOSC_FREQ_24M +//! - \ref CCFGREAD_XOSC_FREQ_48M +//! - \ref CCFGREAD_XOSC_FREQ_HPOSC +//! - \ref CCFGREAD_XOSC_FREQ_TCXO +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_XOSC_FREQ( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & + CCFG_MODE_CONF_XOSC_FREQ_M ) >> + CCFG_MODE_CONF_XOSC_FREQ_S ) ; +} + +//***************************************************************************** +// +//! \brief Read TCXO_MAX_START setting from CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_1_TCXO_MAX_START field. +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_TCXO_MAX_START( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_TCXO_MAX_START_M ) >> + CCFG_MODE_CONF_1_TCXO_MAX_START_S ) ; +} + +//***************************************************************************** +// +//! \brief Read TCXO_TYPE setting from CCFG. +//! +//! \return Returns the value of the CCFG_MODE_CONF_1_TCXO_TYPE field. +//! +// +//***************************************************************************** +__STATIC_INLINE uint32_t +CCFGRead_TCXO_TYPE( void ) +{ + return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_TCXO_TYPE_M ) >> + CCFG_MODE_CONF_1_TCXO_TYPE_S ) ; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __AUX_SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread_doc.h new file mode 100644 index 00000000..5367661d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ccfgread_doc.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: ccfgread_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ccfgread_api +//! @{ +//! \section sec_ccfgread Introduction +//! +//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically +//! a user application does not need to read these CCFG values as they are used mainly during ROM boot +//! and device trimming. However, a subset of the CCFG settings need to be read by application +//! code thus DriverLib provides this API to allow easy read access to these specific settings. +//! +//! The remaining settings not accessible through this API can of course be read directly at the CCFG +//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines. +//! CCFG settings are documented as part of the register descriptions in the CPU memory map. +//! +//! \note CCFG settings are located in flash and should be considered read-only from an application +//! point-of-view. +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.c new file mode 100644 index 00000000..4c809b42 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.c @@ -0,0 +1,203 @@ +/****************************************************************************** +* Filename: chipinfo.c +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #undef ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated + #define ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated +#endif + + +//***************************************************************************** +// +// ChipInfo_GetSupportedProtocol_BV() +// +//***************************************************************************** +ProtocolBitVector_t +ChipInfo_GetSupportedProtocol_BV( void ) +{ + return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); +} + +//***************************************************************************** +// +// ChipInfo_GetPackageType() +// +//***************************************************************************** +PackageType_t +ChipInfo_GetPackageType( void ) +{ + PackageType_t packType = (PackageType_t)(( + HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) & + FCFG1_USER_ID_PKG_M ) >> + FCFG1_USER_ID_PKG_S ); + + if (( packType < PACKAGE_4x4 ) || + ( packType > PACKAGE_7x7_SIP ) ) + { + packType = PACKAGE_Unknown; + } + + return ( packType ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipFamily() +// +//***************************************************************************** +ChipFamily_t +ChipInfo_GetChipFamily( void ) +{ + uint32_t waferId; + ChipFamily_t chipFam = FAMILY_Unknown; + + waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) & + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >> + FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ); + if ( waferId == 0xBB77 ) { + chipFam = FAMILY_CC13x2x7_CC26x2x7; + } + + return ( chipFam ); +} + +//***************************************************************************** +// +// ChipInfo_GetChipType() +// +//***************************************************************************** +ChipType_t +ChipInfo_GetChipType( void ) +{ + ChipType_t chipType = CHIP_TYPE_Unknown; + ChipFamily_t chipFam = ChipInfo_GetChipFamily(); + uint32_t fcfg1UserId = ChipInfo_GetUserId(); + uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >> FCFG1_USER_ID_PROTOCOL_S ); + uint32_t fcfg1Cc13 = (( fcfg1UserId & FCFG1_USER_ID_CC13_M ) >> FCFG1_USER_ID_CC13_S ); + uint32_t fcfg1Pa = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >> FCFG1_USER_ID_PA_S ); + + if ( chipFam == FAMILY_CC13x2x7_CC26x2x7 ) { + switch ( fcfg1Protocol ) { + case 0x8 : + if ( fcfg1Cc13 ) { + if ( ! fcfg1Pa ) { + chipType = CHIP_TYPE_CC1312R7; + } + } + break; + case 0xF : + if ( fcfg1Cc13 ) { + if ( fcfg1Pa ) { + chipType = CHIP_TYPE_CC1352P7; + } + else { + chipType = CHIP_TYPE_CC1352R7; + } + } else { + // ! fcfg1Cc13 + if ( fcfg1Pa ) { + chipType = CHIP_TYPE_CC2652P7; + } else { + chipType = CHIP_TYPE_CC2652R7; + } + } + break; + } + } + + return ( chipType ); +} + +//***************************************************************************** +// +// ChipInfo_GetHwRevision() +// +//***************************************************************************** +HwRevision_t +ChipInfo_GetHwRevision( void ) +{ + HwRevision_t hwRev = HWREV_Unknown; + uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode(); + uint32_t minorHwRev = ChipInfo_GetMinorHwRev(); + ChipFamily_t chipFam = ChipInfo_GetChipFamily(); + + if ( chipFam == FAMILY_CC13x2x7_CC26x2x7 ) { + switch ( fcfg1Rev ) { + case 0 : // CC13x2x1x7, CC26x2x1x7 - rev. 1.0 + hwRev = (HwRevision_t)(((uint32_t)HWREV_1_0 ) + minorHwRev ); + break; + case 1 : // CC13x2x1x7, CC26x2x1x7 - rev. 1.1 (or later) + hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev ); + break; + } + } + + return ( hwRev ); +} + +//***************************************************************************** +// ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated() +//***************************************************************************** +void +ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated( void ) +{ + if ( ! ChipInfo_ChipFamilyIs_CC13x2x7_CC26x2x7() ) + { + while(1) + { + // This driverlib version is for the CC13x2x7/CC26x2x7 chips. + // Do nothing - stay here forever + } + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.h new file mode 100644 index 00000000..6c7bb331 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/chipinfo.h @@ -0,0 +1,755 @@ +/****************************************************************************** +* Filename: chipinfo.h +* +* Description: Collection of functions returning chip information. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup ChipInfo +//! @{ +// +//***************************************************************************** + +#ifndef __CHIP_INFO_H__ +#define __CHIP_INFO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_fcfg1.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType + #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType + #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily + #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision + #define ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated +#endif + + +//***************************************************************************** +// +//! \brief Enumeration identifying the protocols supported. +//! +//! \note +//! This is a bit vector enumeration that indicates supported protocols. +//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4 +// +//***************************************************************************** +typedef enum { + PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. +} ProtocolBitVector_t; + +//***************************************************************************** +// +//! \brief Returns bit vector showing supported protocols. +//! +//! \return +//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. +// +//***************************************************************************** +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the BLE protocol. +//! +//! \return +//! Returns \c true if supporting the BLE protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsBLE( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol. +//! +//! \return +//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsIEEE_802_15_4( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if the chip supports proprietary protocols. +//! +//! \return +//! Returns \c true if supporting proprietary protocols, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_SupportsPROPRIETARY( void ) +{ + return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); +} + +//***************************************************************************** +// +//! \brief Package type enumeration +//! +//! \note +//! Packages available for a specific device are shown in the device datasheet. +// +//***************************************************************************** +typedef enum { + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5, //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. + PACKAGE_7x7_SIP = 6 //!< 6 means that this is a 7x7 mm SiP module (Sytem in Package). +} PackageType_t; + +//***************************************************************************** +// +//! \brief Returns package type. +//! +//! \return +//! Returns \ref PackageType_t +// +//***************************************************************************** +extern PackageType_t ChipInfo_GetPackageType( void ); + +//***************************************************************************** +// +//! \brief Returns true if this is a 4x4mm chip. +//! +//! \return +//! Returns \c true if this is a 4x4mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs4x4( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 5x5mm chip. +//! +//! \return +//! Returns \c true if this is a 5x5mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs5x5( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7mm chip. +//! +//! \return +//! Returns \c true if this is a 7x7mm chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a wafer sale chip (naked die). +//! +//! \return +//! Returns \c true if this is a wafer sale chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWAFER( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a WCSP chip (flip chip). +//! +//! \return +//! Returns \c true if this is a WCSP chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIsWCSP( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); +} + +//***************************************************************************** +// +//! \brief Returns true if this is a 7x7 Q1 chip. +//! +//! \return +//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_PackageTypeIs7x7Q1( void ) +{ + return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); +} + +//***************************************************************************** +// +//! \brief Returns the internal chip HW revision code. +//! +//! \return +//! Returns the internal chip HW revision code (in range 0-15) +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetDeviceIdHwRevCode( void ) +{ + // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] + return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); +} + +//***************************************************************************** +// +//! \brief Returns minor hardware revision number +//! +//! The minor revision number is set to 0 for the first market released chip +//! and thereafter incremented by 1 for each minor hardware change. +//! +//! \return +//! Returns the minor hardware revision number (in range 0-127) +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetMinorHwRev( void ) +{ + uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + + if ( minorRev >= 0x80 ) { + minorRev = 0; + } + + return( minorRev ); +} + +//***************************************************************************** +// +//! \brief Returns the 32 bits USER_ID field +//! +//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM) +//! +//! \return +//! Returns the 32 bits USER_ID field +// +//***************************************************************************** +__STATIC_INLINE uint32_t +ChipInfo_GetUserId( void ) +{ + return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); +} + +//***************************************************************************** +// +//! \brief Chip type enumeration +// +//***************************************************************************** +typedef enum { + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_CC1312P = 10, //!< 10 means that this is a CC1312P chip. + CHIP_TYPE_CC2652 = 11, //!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12, //!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13, //!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14, //!< 14 means that this is a CC1352P chip. + CHIP_TYPE_CC2652P = 15, //!< 15 means that this is a CC2652P chip. + CHIP_TYPE_CC2652RB = 16, //!< 16 means that this is a CC2652RB chip. + CHIP_TYPE_CC2652PB = 17, //!< 17 means that this is a CC2652PB chip. + CHIP_TYPE_CC1311R3 = 18, //!< 18 means that this is a CC1311R3 chip. + CHIP_TYPE_CC1311P3 = 19, //!< 19 means that this is a CC1311P3 chip. + CHIP_TYPE_CC2651R3 = 20, //!< 20 means that this is a CC2651R3 chip. + CHIP_TYPE_CC2651P3 = 21, //!< 21 means that this is a CC2651P3 chip. + CHIP_TYPE_CC2641R3 = 22, //!< 22 means that this is a CC2641R3 chip. + CHIP_TYPE_CC1312R7 = 23, //!< 23 means that this is a CC1312R7 chip. + CHIP_TYPE_unused0 = 24, //!< 24 unused value + CHIP_TYPE_CC1352R7 = 25, //!< 25 means that this is a CC1352R7 chip. + CHIP_TYPE_CC1352P7 = 26, //!< 26 means that this is a CC1352P7 chip. + CHIP_TYPE_CC2652R7 = 27, //!< 27 means that this is a CC2652R7 chip. + CHIP_TYPE_CC2652P7 = 28, //!< 28 means that this is a CC2652P7 chip. + CHIP_TYPE_unused1 = 29, //!< 29 unused value + CHIP_TYPE_CC1314R10 = 30, //!< 30 means that this is a CC1314R10 chip. + CHIP_TYPE_CC1354P10 = 31, //!< 31 means that this is a CC1354P10 chip. + CHIP_TYPE_CC1354R10 = 32, //!< 32 means that this is a CC1354R10 chip. + CHIP_TYPE_CC2653P10 = 33, //!< 33 means that this is a CC2653P10 chip. + CHIP_TYPE_unused2 = 34, //!< 34 unused value + CHIP_TYPE_CC2674P10 = 35, //!< 35 means that this is a CC2674P10 chip. + CHIP_TYPE_CC2674R10 = 36, //!< 36 means that this is a CC2674R10 chip. +} ChipType_t; + +//***************************************************************************** +// +//! \brief Returns chip type. +//! +//! \return +//! Returns \ref ChipType_t +// +//***************************************************************************** +extern ChipType_t ChipInfo_GetChipType( void ); + +//***************************************************************************** +// +//! \brief Chip family enumeration +// +//***************************************************************************** +typedef enum { + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC13x1_CC26x1 = 2, //!< 2 means that the chip is a CC13x1, CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4, //!< 4 means that the chip is a CC13x2, CC26x2 family member. + FAMILY_CC13x2x7_CC26x2x7 = 5, //!< 5 means that the chip is a CC13x2x7, CC26x2x7 family member. + FAMILY_CC13x4_CC26x4 = 6, //!< 6 means that the chip is a CC13x4, CC26x4 family member. +} ChipFamily_t; + +//***************************************************************************** +// +//! \brief Returns chip family member. +//! +//! \return +//! Returns \ref ChipFamily_t +// +//***************************************************************************** +extern ChipFamily_t ChipInfo_GetChipFamily( void ); + +//***************************************************************************** +// +// Options for the define THIS_DRIVERLIB_BUILD +// +//***************************************************************************** +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC13X1_CC26X1 2 //!< 2 is the driverlib build ID for the cc13x1_cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. +#define DRIVERLIB_BUILD_CC13X2X7_CC26X2X7 5 //!< 5 is the driverlib build ID for the cc13x2x7_cc26x2x7 driverlib. +#define DRIVERLIB_BUILD_CC13X4_CC26X4 6 //!< 6 is the driverlib build ID for the cc13x4_cc26x4 driverlib. + + +//***************************************************************************** +// +//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID. +//! +//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). +// +//***************************************************************************** +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2X7_CC26X2X7 + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC26x0R2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC26x0R2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x1, CC26x1 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x1, CC26x1 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x1_CC26x1( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x1_CC26x1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x2x7, CC26x2x7 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x2x7, CC26x2x7 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x2x7_CC26x2x7( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2x7_CC26x2x7 ); +} + +//***************************************************************************** +// +//! \brief Returns true if this chip is member of the CC13x4, CC26x4 family. +//! +//! \return +//! Returns \c true if this chip is member of the CC13x4, CC26x4 family, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_ChipFamilyIs_CC13x4_CC26x4( void ) +{ + return ( ChipInfo_GetChipFamily() == FAMILY_CC13x4_CC26x4 ); +} + +//***************************************************************************** +// +//! \brief HW revision enumeration. +// +//***************************************************************************** +typedef enum { + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24, //!< 24 means that the chip's HW revision is 2.4 + HWREV_3_0 = 30 //!< 30 means that the chip's HW revision is 3.0 +} HwRevision_t; + +//***************************************************************************** +// +//! \brief Returns chip HW revision. +//! +//! \return +//! Returns \ref HwRevision_t +// +//***************************************************************************** +extern HwRevision_t ChipInfo_GetHwRevision( void ); + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 1.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_1_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.0 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.1 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.2 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.3 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 2.4 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); +} + +//***************************************************************************** +// +//! \brief Returns true if HW revision for this chip is 3.0 or greater. +//! +//! \return +//! Returns \c true if HW revision for this chip is 3.0 or greater, \c false otherwise. +// +//***************************************************************************** +__STATIC_INLINE bool +ChipInfo_HwRevisionIs_GTEQ_3_0( void ) +{ + return ( ChipInfo_GetHwRevision() >= HWREV_3_0 ); +} + +//***************************************************************************** +// +//! \brief Verifies that current chip is CC13x2x7 or CC26x2x7 and never returns if violated. +//! +//! \return None +// +//***************************************************************************** +extern void ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_ChipInfo_GetSupportedProtocol_BV + #undef ChipInfo_GetSupportedProtocol_BV + #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV + #endif + #ifdef ROM_ChipInfo_GetPackageType + #undef ChipInfo_GetPackageType + #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType + #endif + #ifdef ROM_ChipInfo_GetChipType + #undef ChipInfo_GetChipType + #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType + #endif + #ifdef ROM_ChipInfo_GetChipFamily + #undef ChipInfo_GetChipFamily + #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily + #endif + #ifdef ROM_ChipInfo_GetHwRevision + #undef ChipInfo_GetHwRevision + #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision + #endif + #ifdef ROM_ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated + #undef ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated + #define ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CHIP_INFO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.c new file mode 100644 index 00000000..926a6dff --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.c @@ -0,0 +1,483 @@ +/****************************************************************************** +* Filename: cpu.c +* +* Description: Instruction wrappers for special CPU instructions needed by +* the drivers. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "cpu.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef CPUcpsid + #define CPUcpsid NOROM_CPUcpsid + #undef CPUprimask + #define CPUprimask NOROM_CPUprimask + #undef CPUcpsie + #define CPUcpsie NOROM_CPUcpsie + #undef CPUbasepriGet + #define CPUbasepriGet NOROM_CPUbasepriGet + #undef CPUdelay + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#elif defined(__clang__) +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + // Naked function, that is, the compiler does not help us with anything. + // ARM's calling convention states that the return variable shall be stored + // in R0. + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs r0, PRIMASK\n" // Store PRIMASK in R0 + " cpsid i\n" // Disable interrupts + " bx lr\n" // Branch back to caller + : // No output operands + : // No input operands + : "r0" // Clobbers + ); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the current interrupt state +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUprimask(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + mrs r0, PRIMASK; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUprimask(void) +{ + // Read PRIMASK. + __asm(" mrs r0, PRIMASK\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#elif defined(__clang__) +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + // Naked function, that is, the compiler does not help us with anything. + // ARM's calling convention states that the return variable shall be stored + // in R0. + + // Read PRIMASK + __asm volatile (" mrs r0, PRIMASK\n" // Store PRIMASK in R0 + " bx lr\n" // Branch back to caller + : // No output + : // No input + : "r0" // Clobbers + ); +} +#else +uint32_t __attribute__((naked)) +CPUprimask(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK + __asm volatile (" mrs %0, PRIMASK\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#elif defined(__clang__) +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + // Naked function, that is, the compiler does not help us with anything. + // ARM's calling convention states that the return variable shall be stored + // in R0. + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs r0, PRIMASK\n" // Store PRIMASK in R0 + " cpsie i\n" // Enable interrupts + " bx lr\n" // Branch back to caller + : // No output operands + : // No input operands + : "r0" // Clobbers + ); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Get the interrupt priority disable level +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUbasepriGet(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + mrs r0, BASEPRI; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +uint32_t +CPUbasepriGet(void) +{ + // Read BASEPRI. + __asm(" mrs r0, BASEPRI\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#elif defined(__clang__) +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + // Naked function, that is, the compiler does not help us with anything. + // ARM's calling convention states that the return variable shall be stored + // in R0. + + // Read BASEPRI. + __asm volatile (" mrs r0, BASEPRI\n" // Store BASEPRI in R0 + " bx lr\n" // Branch back to caller + : // No output + : // No input + : "r0" // Clobbers + ); +} +#else +uint32_t __attribute__((naked)) +CPUbasepriGet(void) +{ + uint32_t ui32Ret; + + // Read BASEPRI. + __asm volatile (" mrs %0, BASEPRI\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif + +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:NOROM_CPUdelay\"\n" + " .clink\n" + " .thumbfunc NOROM_CPUdelay\n" + " .thumb\n" + " .global NOROM_CPUdelay\n" + "NOROM_CPUdelay:\n" + " subs r0, #1\n" + " bne.n NOROM_CPUdelay\n" + " bx lr\n"); +#elif defined(__clang__) +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times. + // The naked attribute tells the compiler that the function is effectively + // hand-coded assembly implemented using inlined assembly without operands. + // As such, it assumes that the C calling conventions are obeyed, and we can + // assume ui32Count is in R0. + __asm volatile ("CPUdel%=:\n" + " subs r0, #1\n" + " bne CPUdel%=\n" + " bx lr\n" + : /* No output */ + : /* No input */ + : "r0", "cc" /* Clobbers. "cc" is the flags */ + ); +} +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times. + // GCC supports input parameters in naked functions, so we use the parameter + // in the inline assembly and let the compiler decide on which register to + // use for it. + __asm volatile ("CPUdel%=:\n" + " subs %0, #1\n" + " bne CPUdel%=\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.h new file mode 100644 index 00000000..8d6c2785 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu.h @@ -0,0 +1,463 @@ +/****************************************************************************** +* Filename: cpu.h +* +* Description: Defines and prototypes for the CPU instruction wrapper +* functions. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup cpu_api +//! @{ +// +//***************************************************************************** + +#ifndef __CPU_H__ +#define __CPU_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_cpu_scs.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define CPUcpsid NOROM_CPUcpsid + #define CPUprimask NOROM_CPUprimask + #define CPUcpsie NOROM_CPUcpsie + #define CPUbasepriGet NOROM_CPUbasepriGet + #define CPUdelay NOROM_CPUdelay +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Disable all external interrupts. +//! +//! Use this function to disable all system interrupts. This function is +//! implemented as a wrapper function for the CPSID instruction. +//! +//! \return Returns the state of \b PRIMASK on entry +// +//***************************************************************************** +extern uint32_t CPUcpsid(void); + +//***************************************************************************** +// +//! \brief Get the current interrupt state. +//! +//! Use this function to retrieve the current state of the interrupts. This +//! function is implemented as a wrapper function returning the state of +//! PRIMASK. +//! +//! \return Returns the state of the \b PRIMASK (indicating whether interrupts +//! are enabled or disabled). +// +//***************************************************************************** +extern uint32_t CPUprimask(void); + +//***************************************************************************** +// +//! \brief Enable all external interrupts. +//! +//! Use this function to enable all system interrupts. This function is +//! implemented as a wrapper function for the CPSIE instruction. +//! +//! \return Returns the state of \b PRIMASK on entry. +// +//***************************************************************************** +extern uint32_t CPUcpsie(void); + +//***************************************************************************** +// +//! \brief Get the interrupt priority disable level. +//! +//! Use this function to get the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \return Returns the value of the \b BASEPRI register. +// +//***************************************************************************** +extern uint32_t CPUbasepriGet(void); + +//***************************************************************************** +// +//! \brief Provide a small non-zero delay using a simple loop counter. +//! +//! This function provides means for generating a constant length delay. It +//! is written in assembly to keep the delay consistent across tool chains, +//! avoiding the need to tune the delay based on the tool chain in use. +//! +//! \note It is not recommended using this function for long delays. +//! +//! Notice that interrupts can affect the delay if not manually disabled in advance. +//! +//! The delay depends on where code resides and the path for code fetching: +//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) +//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop +//! - Code in flash, cache disabled : 7 cycles per loop +//! - Code in SRAM : 6 cycles per loop +//! - Code in GPRAM : 3 cycles per loop +//! +//! \note If using an RTOS, consider using RTOS provided delay functions because +//! these will not block task scheduling and will potentially save power. +//! +//! Calculate delay count based on the wanted delay in microseconds (us): +//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop] +//! +//! Example: 250 us delay with code in flash and with cache and prefetch enabled: +//! - ui32Count = 250 * 48 / 4 = 3000 +//! +//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero. +//! +//! \return None +// +//***************************************************************************** +extern void CPUdelay(uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Wait for interrupt. +//! +//! Use this function to let the System CPU wait for the next interrupt. This +//! function is implemented as a wrapper function for the WFI instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfi(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + wfi; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm(" wfi\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfi(void) +{ + // Wait for the next interrupt. + __asm volatile (" wfi\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Wait for event. +//! +//! Use this function to let the System CPU wait for the next event. This +//! function is implemented as a wrapper function for the WFE instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUwfe(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + wfe; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUwfe(void) +{ + // Wait for the next event. + __asm(" wfe\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUwfe(void) +{ + // Wait for the next event. + __asm volatile (" wfe\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Send event. +//! +//! Use this function to let the System CPU send an event. This function is +//! implemented as a wrapper function for the SEV instruction. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUsev(void) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUsev(void) +{ + // Send event. + sev; + bx lr +} +#elif defined(__TI_COMPILER_VERSION__) +__STATIC_INLINE void +CPUsev(void) +{ + // Send event. + __asm(" sev\n"); +} +#else +__STATIC_INLINE void __attribute__((always_inline)) +CPUsev(void) +{ + // Send event. + __asm volatile (" sev\n"); +} +#endif + +//***************************************************************************** +// +//! \brief Update the interrupt priority disable level. +//! +//! Use this function to change the level of priority that will disable +//! interrupts with a lower priority level. +//! +//! \param ui32NewBasepri is the new basis priority level to set. +//! +//! \return None +// +//***************************************************************************** +#if defined(DOXYGEN) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // This function is written in assembly. See cpu.h for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm __STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + msr BASEPRI, r0; + bx lr +} +#elif (defined(__TI_COMPILER_VERSION__) || defined(__clang__)) +__STATIC_INLINE void +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm(" msr BASEPRI, r0\n"); +} +#else +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wattributes" +__STATIC_INLINE void __attribute__ ((naked)) +CPUbasepriSet(uint32_t ui32NewBasepri) +{ + // Set the BASEPRI register. + __asm volatile (" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r" (ui32NewBasepri) + ); +} +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// +//! \brief Disable CPU write buffering (recommended for debug purpose only). +//! +//! This function helps debugging "bus fault crashes". +//! Disables write buffer use during default memory map accesses. +//! +//! This causes all bus faults to be precise bus faults but decreases the +//! performance of the processor because the stores to memory have to complete +//! before the next instruction can be executed. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferEnable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferDisable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; +} + +//***************************************************************************** +// +//! \brief Enable CPU write buffering (default setting). +//! +//! Re-enables write buffer during default memory map accesses if +//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging. +//! +//! \return None +//! +//! \sa \ref CPU_WriteBufferDisable() +// +//***************************************************************************** +__STATIC_INLINE void +CPU_WriteBufferEnable( void ) +{ + HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_CPUcpsid + #undef CPUcpsid + #define CPUcpsid ROM_CPUcpsid + #endif + #ifdef ROM_CPUprimask + #undef CPUprimask + #define CPUprimask ROM_CPUprimask + #endif + #ifdef ROM_CPUcpsie + #undef CPUcpsie + #define CPUcpsie ROM_CPUcpsie + #endif + #ifdef ROM_CPUbasepriGet + #undef CPUbasepriGet + #define CPUbasepriGet ROM_CPUbasepriGet + #endif + #ifdef ROM_CPUdelay + #undef CPUdelay + #define CPUdelay ROM_CPUdelay + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __CPU_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu_doc.h new file mode 100644 index 00000000..be9bb497 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/cpu_doc.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* Filename: cpu_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup cpu_api +//! @{ +//! \section sec_cpu Introduction +//! +//! The CPU API provides a set of functions performing very low-level control of the system CPU. +//! All functions in this API are written in assembler in order to either access special registers +//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: +//! One version for each supported compiler. +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.c new file mode 100644 index 00000000..3effe54c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.c @@ -0,0 +1,212 @@ +/****************************************************************************** +* Filename: ddi.c +* +* Description: Driver for the DDI master interface +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ddi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef DDI32RegWrite + #define DDI32RegWrite NOROM_DDI32RegWrite + #undef DDI16BitWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #undef DDI16BitRead + #define DDI16BitRead NOROM_DDI16BitRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Write a 32 bit value to a register in the DDI slave. +// +//***************************************************************************** +void +DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +// Write a single bit using a 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData) +{ + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; +} + +//***************************************************************************** +// +// Write a bit field via the DDI using 16-bit maskable write +// +//***************************************************************************** +void +DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data) +{ + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; +} + +//***************************************************************************** +// +// Read a bit via the DDI using 16-bit READ. +// +//***************************************************************************** +uint16_t +DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +//***************************************************************************** +// +// Read a bit field via the DDI using 16-bit read. +// +//***************************************************************************** +uint16_t +DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift) +{ + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.h new file mode 100644 index 00000000..195b4de5 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi.h @@ -0,0 +1,459 @@ +/****************************************************************************** +* Filename: ddi.h +* +* Description: Defines and prototypes for the DDI master interface. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup analog_group +//! @{ +//! \addtogroup ddi_api +//! @{ +// +//***************************************************************************** + +#ifndef __DDI_H__ +#define __DDI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_aux_smph.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define DDI32RegWrite NOROM_DDI32RegWrite + #define DDI16BitWrite NOROM_DDI16BitWrite + #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite + #define DDI16BitRead NOROM_DDI16BitRead + #define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#endif + +//***************************************************************************** +// +// Number of register in the DDI slave +// +//***************************************************************************** +#define DDI_SLAVE_REGS 64 + + +//***************************************************************************** +// +// Defines that is used to control the ADI slave and master +// +//***************************************************************************** +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + + +//***************************************************************************** +// +// Helper functions +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Check a DDI base address. +//! +//! This function determines if a DDI port base address is valid. +//! +//! \param ui32Base is the base address of the DDI port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +//! +//! \endinternal +// +//***************************************************************************** +static bool +DDIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == AUX_DDI0_OSC_BASE); +} +#endif + + +//***************************************************************************** +// +//! \brief Read the value in a 32 bit register. +//! +//! This function will read a register in the analog domain and return +//! the value as an \c uint32_t. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the 32 bit register to read. +//! +//! \return Returns the 32 bit value of the analog register. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) +{ + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Read the register and return the value. + return(HWREG(ui32Base + ui32Reg)); +} + +//***************************************************************************** +// +//! \brief Set specific bits in a DDI slave register. +//! +//! This function will set bits in a register in the analog domain. +//! +//! \note This operation is write only for the specified register. +//! This function is used to set bits in specific register in the +//! DDI slave. Only bits in the selected register are affected by the +//! operation. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base register to assert the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to set in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_SET; + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clear specific bits in a 32 bit DDI register. +//! +//! This function will clear bits in a register in the analog domain. +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the base registers to clear the bits in. +//! \param ui32Val is the 32 bit one-hot encoded value specifying which +//! bits to clear in the register. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_CLR; + + // Clear the selected bits. + HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave. +//! +//! This function allows byte (8 bit access) to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-7 bits aligned on a +//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui16Val = 0x0A and ui16Mask = 0x0E. Bits 0 and 5-7 will +//! not be affected by the operation, as long as the corresponding bits are +//! not set in the \c ui16Mask. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is the Least Significant Register in the DDI slave that +//! will be affected by the write operation. +//! \param ui32Byte is the byte number to access within the 32 bit register. +//! \param ui16Mask is the mask defining which of the 8 bits that should be +//! overwritten. The mask must be defined in the lower half of the 16 bits. +//! \param ui16Val is the value to write. The value must be defined in the lower +//! half of the 16 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, + uint16_t ui16Mask, uint16_t ui16Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui16Val & 0xFF00)); + ASSERT(!(ui16Mask & 0xFF00)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1); + + // Set the selected bits. + HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; +} + +//***************************************************************************** +// +//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a +//! half-word boundary in the DDI slave. +//! +//! This function allows 16 bit masked access to the DDI slave registers. +//! +//! Use this function to write any value in the range 0-15 bits aligned on a +//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set +//! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be +//! affected by the operation, as long as the corresponding bits are not set +//! in the \c ui32Mask. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param bWriteHigh defines which part of the register to write in. +//! \param ui32Mask is the mask defining which of the 16 bit that should be +//! overwritten. The mask must be defined in the lower half of the 32 bits. +//! \param ui32Val is the value to write. The value must be defined in the lower +//! half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, + uint32_t ui32Mask, uint32_t ui32Val) +{ + uint32_t ui32RegOffset; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + ASSERT(!(ui32Val & 0xFFFF0000)); + ASSERT(!(ui32Mask & 0xFFFF0000)); + + // Get the correct address of the first register used for setting bits + // in the DDI slave. + ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0); + + // Set the selected bits. + HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; +} + +//***************************************************************************** +// +//! \brief Write a 32 bit value to a register in the DDI slave. +//! +//! This function will write a value to a register in the analog +//! domain. +//! +//! \note This operation is write only for the specified register. No +//! conservation of the previous value of the register will be kept (i.e. this +//! is NOT read-modify-write on the register). +//! +//! \param ui32Base is DDI base address. +//! \param ui32Reg is the register to write. +//! \param ui32Val is the 32 bit value to write to the register. +//! +//! \return None +// +//***************************************************************************** +extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val); + +//***************************************************************************** +// +//! \brief Write a single bit using a 16-bit maskable write. +//! +//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. +//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32WrData); + + +//***************************************************************************** +// +//! \brief Write a bit field via the DDI using 16-bit maskable write. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift is the shift value for the bit field. +//! \param ui32Data is the data aligned to bit 0. +//! +//! \return None +// +//***************************************************************************** +extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift, + uint16_t ui32Data); + +//***************************************************************************** +// +//! \brief Read a bit via the DDI using 16-bit read. +//! +//! \param ui32Base is the base address of the DDI module. +//! \param ui32Reg is the register to read. +//! \param ui32Mask defines the bit which should be read. +//! +//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask. +// +//***************************************************************************** +extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask); + +//***************************************************************************** +// +//! \brief Read a bit field via the DDI using 16-bit read. +//! +//! Requires that entire bit field is within the half word boundary. +//! +//! \param ui32Base is the base address of the DDI port. +//! \param ui32Reg is register to access. +//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. +//! \param ui32Shift defines the required shift of the data to align with bit 0. +//! +//! \return Returns data aligned to bit 0. +// +//***************************************************************************** +extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, + uint32_t ui32Mask, uint32_t ui32Shift); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_DDI32RegWrite + #undef DDI32RegWrite + #define DDI32RegWrite ROM_DDI32RegWrite + #endif + #ifdef ROM_DDI16BitWrite + #undef DDI16BitWrite + #define DDI16BitWrite ROM_DDI16BitWrite + #endif + #ifdef ROM_DDI16BitfieldWrite + #undef DDI16BitfieldWrite + #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite + #endif + #ifdef ROM_DDI16BitRead + #undef DDI16BitRead + #define DDI16BitRead ROM_DDI16BitRead + #endif + #ifdef ROM_DDI16BitfieldRead + #undef DDI16BitfieldRead + #define DDI16BitfieldRead ROM_DDI16BitfieldRead + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DDI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi_doc.h new file mode 100644 index 00000000..091a48e0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ddi_doc.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* Filename: ddi_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ddi_api +//! @{ +//! \section sec_ddi Introduction +//! \n +//! +//! \section sec_ddi_api API +//! +//! The API functions can be grouped like this: +//! +//! Write: +//! - Direct (all bits): +//! - \ref DDI32RegWrite() +//! - Set individual bits: +//! - \ref DDI32BitsSet() +//! - Clear individual bits: +//! - \ref DDI32BitsClear() +//! - Masked: +//! - \ref DDI8SetValBit() +//! - \ref DDI16SetValBit() +//! - Special functions using masked write: +//! - \ref DDI16BitWrite() +//! - \ref DDI16BitfieldWrite() +//! +//! Read: +//! - Direct (all bits): +//! - \ref DDI32RegRead() +//! - Special functions using masked read: +//! - \ref DDI16BitRead() +//! - \ref DDI16BitfieldRead() +//! +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.c new file mode 100644 index 00000000..5e678b18 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* Filename: debug.c +* +* Description: Driver for the Debug functionality (NB. This is a stub which +* should never be included in a release). +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include +#include "../inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +void +__error__(char *pcFilename, uint32_t ui32Line) +{ + // Error catching. + // User can implement custom error handling for failing ASSERTs. + // Setting breakpoint here allows tracing of the failing ASSERT. + while( true ); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.h new file mode 100644 index 00000000..3986b3a7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/debug.h @@ -0,0 +1,82 @@ +/****************************************************************************** +* Filename: debug.h +* +* Description: Macros for assisting debug of the driver library. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup debug_api +//! @{ +// +//***************************************************************************** + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +//***************************************************************************** +// +//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. +// +//***************************************************************************** +extern void __error__(char *pcFilename, uint32_t ui32Line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#define ASSERT(expr) { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } + +#else +#define ASSERT(expr) +#endif + +#endif // __DEBUG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.c new file mode 100644 index 00000000..78d5282c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: event.c +* +* Description: Driver for the Event Fabric. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "event.h" + +// See event.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.h new file mode 100644 index 00000000..e5d458c2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event.h @@ -0,0 +1,265 @@ +/****************************************************************************** +* Filename: event.h +* +* Description: Defines and prototypes for the Event Handler. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup event_api +//! @{ +// +//***************************************************************************** + +#ifndef __EVENT_H__ +#define __EVENT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_event.h" +#include "debug.h" + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Connects an event to an event subscriber via Event Fabric. +//! +//! This function connects event sources to event subscribers. +//! +//! It is not possible to read event status in this module (except software events). +//! Event status must be read in the module that contains the event source. How a +//! specific event subscriber reacts to an event is configured and documented in +//! the respective modules. +//! +//! For a full list of configurable and constant mapped event sources to event +//! subscribers see the register descriptions for +//! Event Fabric. +//! +//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format: +//! - \ti_code{EVENT_O_[subscriber_name]} +//! +//! Defines for event source argument (\c ui32EventSource) must have the +//! following format where valid \c event_enum values are found in the +//! register description : +//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} +//! +//! Examples of valid defines for \c ui32EventSource: +//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE +//! - EVENT_RFCSEL9_EV_AUX_COMPA +//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD +//! +//! \note Each event subscriber can only receive a sub-set of the event sources! +//! +//! \note Switching the event source is not glitch free, so it is imperative +//! that the subscriber is disabled for interrupts when switching the event +//! source. The behavior is undefined if not disabled. +//! +//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event. +//! Click the event subscriber to see the list of valid event sources in the +//! register description. +//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30 +//! - EVENT_O_RFCSEL9 : RF Core event 9 +//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event +//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event +//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event +//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event +//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event +//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event +//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event +//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event +//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request +//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request +//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request +//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request +//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request +//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request +//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request +//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request +//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request +//! - EVENT_O_AUXSEL0 : AUX +//! - EVENT_O_I2SSTMPSEL0 : I2S +//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt) +//! \param ui32EventSource is the specific event that must be acted upon. +//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) +{ + // Check the arguments. + ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || + ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || + ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || + ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || + ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || + ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || + ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + + // Map the event source to the event subscriber + HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; +} + +//***************************************************************************** +// +//! \brief Sets software event. +//! +//! Setting a software event triggers the event if the value was 0 before. +//! +//! \note The software event must be cleared manually after the event has +//! triggered the event subscriber. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +//! +//! \sa \ref EventSwEventClear() +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventSet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; +} + +//***************************************************************************** +// +//! \brief Clears software event. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +EventSwEventClear(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; +} + +//***************************************************************************** +// +//! \brief Gets software event status. +//! +//! \param ui32SwEvent is the software event number. +//! - 0 : SW Event 0 +//! - 1 : SW Event 1 +//! - 2 : SW Event 2 +//! - 3 : SW Event 3 +//! +//! \return Returns current value of requested software event. +//! - 0 : Software event is de-asserted. +//! - 1 : Software event is asserted. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +EventSwEventGet(uint32_t ui32SwEvent) +{ + // Check the arguments. + ASSERT( ui32SwEvent <= 3 ); + + // Each software event is byte accessible + return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __EVENT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event_doc.h new file mode 100644 index 00000000..8c530ac7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/event_doc.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* Filename: event_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup event_api +//! @{ +//! \section sec_event Introduction +//! +//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and +//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers +//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api). +//! +//! The MCU event fabric is a combinational router between event sources and event subscribers. Most +//! event subscribers have statically routed event sources but several event subscribers have +//! configurable event sources which is configured in the MCU event fabric through this API. Although +//! configurable only a subset of event sources are available to each of the configurable event subscribers. +//! This is explained in more details in the function @ref EventRegister() which does all the event routing +//! configuration. +//! +//! MCU event fabric also contains four software events which allow software to trigger certain event +//! subscribers. Each of the four software events is an independent event source which must be set and +//! cleared in the MCU event fabric through the functions: +//! - @ref EventSwEventSet() +//! - @ref EventSwEventClear() +//! - @ref EventSwEventGet() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.c new file mode 100644 index 00000000..7f4858da --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.c @@ -0,0 +1,708 @@ +/****************************************************************************** +* Filename: flash.c +* +* Description: Driver for on chip Flash. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "flash.h" +#include "rom.h" +#include "chipinfo.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef FlashPowerModeSet + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #undef FlashPowerModeGet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #undef FlashProtectionSet + #define FlashProtectionSet NOROM_FlashProtectionSet + #undef FlashProtectionGet + #define FlashProtectionGet NOROM_FlashProtectionGet + #undef FlashProtectionSave + #define FlashProtectionSave NOROM_FlashProtectionSave + #undef FlashSectorErase + #define FlashSectorErase NOROM_FlashSectorErase + #undef FlashProgram + #define FlashProgram NOROM_FlashProgram + #undef FlashEfuseReadRow + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t); + +typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t); + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void SetReadMode(void); + +//***************************************************************************** +// +// Set power mode +// +//***************************************************************************** +void +FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod) +{ + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + // Initialize flag requesting deprecated power mode + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) &= ~FW_PWRMODE_DEPRECATED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR1_M) | (FBFALLBACK_ACTIVE << FLASH_FBFALLBACK_BANKPWR1_S); + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Deprecated power mode requested. Set flag. + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_PWRMODE_DEPRECATED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; + // Fall through to force FLASH_PWR_OFF_MODE power mode + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR1_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +//***************************************************************************** +// +// Get current configured power mode +// +//***************************************************************************** +uint32_t +FlashPowerModeGet(void) +{ + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if((ui32BankPwrMode == FBFALLBACK_SLEEP) && + ((HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_PWRMODE_DEPRECATED) == FW_PWRMODE_DEPRECATED)) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else if((ui32BankPwrMode == FBFALLBACK_SLEEP) && + ((HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_PWRMODE_DEPRECATED) == 0)) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +//***************************************************************************** +// +// Set sector protection +// +//***************************************************************************** +void +FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) +{ + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 43) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + else if(ui32SectorNumber <= 75) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x1; + ui32SectorNumber -= 44; + + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 87) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 76; + + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= (1 << ui32SectorNumber); + } + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +//***************************************************************************** +// +// Get sector protection +// +//***************************************************************************** +uint32_t +FlashProtectionGet(uint32_t ui32SectorAddress) +{ + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 43) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 75) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 44; + + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 87) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 76; + + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + return(ui32SectorProtect); +} + +//***************************************************************************** +// +// Save sector protection to make it permanent +// +//***************************************************************************** +uint32_t +FlashProtectionSave(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// Erase a flash sector +// +//***************************************************************************** +uint32_t +FlashSectorErase(uint32_t ui32SectorAddress) +{ + uint32_t ui32ErrorReturn; + FlashSectorErasePointer_t FuncPointer; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Call ROM function that handles the actual erase operation + FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]); + ui32ErrorReturn = FuncPointer(ui32SectorAddress); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + + +//***************************************************************************** +// +// Programs unprotected main bank flash sectors +// +//***************************************************************************** +uint32_t +FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + // Call ROM function that handles the actual program operation + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); + +} + +//***************************************************************************** +// +// Reads efuse data from specified row +// +//***************************************************************************** +bool +FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) +{ + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + + +//***************************************************************************** +// +// Disables all sectors for erase and programming on the active bank +// +//***************************************************************************** +void +FlashDisableSectorsForWrite(void) +{ + uint32_t ui32BankNo; + // Configure flash back to read mode + SetReadMode(); + + for(ui32BankNo = 0; ui32BankNo < ((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_NUM_BANK_M) + >> FLASH_FCFG_BANK_MAIN_NUM_BANK_S); ui32BankNo++) + { + // Select bank + HWREG(FLASH_BASE + FLASH_O_FMAC) = ui32BankNo; + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS_M; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0; +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +// HAPI Flash program function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address, + uint32_t ui32Count) +{ + uint32_t ui32ErrorReturn; + FlashPrgPointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} + +//***************************************************************************** +// +// HAPI Flash sector erase function +// +//***************************************************************************** +uint32_t +MemBusWrkAroundHapiEraseSector(uint32_t ui32Address) +{ + uint32_t ui32ErrorReturn; + + FlashSectorErasePointer_t FuncPointer; + uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4)); + + // Call ROM function + FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr); + ui32ErrorReturn = FuncPointer(ui32Address); + + // Enable standby in flash bank since ROM function might have disabled it + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Return status of operation. + return(ui32ErrorReturn); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.h new file mode 100644 index 00000000..7706457a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/flash.h @@ -0,0 +1,822 @@ +/****************************************************************************** +* Filename: flash.h +* +* Description: Defines and prototypes for the Flash driver. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#ifndef __FLASH_H__ +#define __FLASH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define FlashPowerModeSet NOROM_FlashPowerModeSet + #define FlashPowerModeGet NOROM_FlashPowerModeGet + #define FlashProtectionSet NOROM_FlashProtectionSet + #define FlashProtectionGet NOROM_FlashProtectionGet + #define FlashProtectionSave NOROM_FlashProtectionSave + #define FlashSectorErase NOROM_FlashSectorErase + #define FlashProgram NOROM_FlashProgram + #define FlashEfuseReadRow NOROM_FlashEfuseReadRow + #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#endif + +//***************************************************************************** +// +// Values that can be returned from the API functions +// +//***************************************************************************** +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + +//***************************************************************************** +// +// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and +// returned from FlashIntStatus(). +// +//***************************************************************************** +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask + +//***************************************************************************** +// +// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). +// +//***************************************************************************** +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_DEEP_STDBY_MODE \ + 0x00000002 // Deprecated. Will force same + // power mode as for FLASH_PWR_OFF_MODE + +//***************************************************************************** +// +// Values passed to FlashSetProtection() and returned from FlashGetProtection(). +// +//***************************************************************************** +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program + // protected + +//***************************************************************************** +// +// Define used by the flash programming and erase functions +// +//***************************************************************************** +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +//***************************************************************************** +// +// Define used for access to factory configuration area. +// +//***************************************************************************** +#define FCFG1_OFFSET 0x1000 + +//***************************************************************************** +// +// Define for the clock frequency input to the flash module in number of MHz +// +//***************************************************************************** +#define FLASH_MODULE_CLK_FREQ 48 + +//***************************************************************************** +// +//! \brief Defined values for Flash State Machine commands +// +//***************************************************************************** +typedef enum +{ + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. +} tFlashStateCommandsType; + +//***************************************************************************** +// +// Defines for values written to the FLASH_O_FSM_WR_ENA register +// +//***************************************************************************** +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +//***************************************************************************** +// +// Defines for the bank power mode field the FLASH_O_FBFALLBACK register +// +//***************************************************************************** +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +//***************************************************************************** +// +// Defines for the bank grace period and pump grace period +// +//***************************************************************************** +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +//***************************************************************************** +// +// Defines used by the FlashProgramPattern() function +// +//***************************************************************************** +#define PATTERN_BITS 0x20 // No of bits in data pattern to program + +//***************************************************************************** +// +// Defines for the FW flag bits in the FLASH_O_FWFLAG register +// +//***************************************************************************** +#define FW_WRT_TRIMMED 0x00000001 +#define FW_PWRMODE_DEPRECATED 0x00000002 + +//***************************************************************************** +// +// Defines used by the flash programming functions +// +//***************************************************************************** +typedef volatile uint8_t tFwpWriteByte; +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +//***************************************************************************** +// +// Define for efuse instruction +// +//***************************************************************************** +#define DUMPWORD_INSTR 0x04 + +//***************************************************************************** +// +// Define for FSM command execution +// +//***************************************************************************** +#define FLASH_CMD_EXEC 0x15 + +//***************************************************************************** +// +//! \brief Get size of a flash sector in number of bytes. +//! +//! This function will return the size of a flash sector in number of bytes. +//! +//! \return Returns size of a flash sector in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSectorSizeGet(void) +{ + uint32_t ui32SectorSizeInKbyte; + + ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + // Return flash sector size in number of bytes. + return(ui32SectorSizeInKbyte * 1024); +} + +//***************************************************************************** +// +//! \brief Get the size of the flash. +//! +//! This function returns the size of the flash main bank in number of bytes. +//! +//! \return Returns the flash size in number of bytes. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashSizeGet(void) +{ + uint32_t ui32NoOfSectors; + + // Get number of flash sectors + ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + // Return flash size in number of bytes + return(ui32NoOfSectors * FlashSectorSizeGet()); +} + +//***************************************************************************** +// +//! \brief Set power mode. +//! +//! This function will set the specified power mode. +//! +//! Any access to the bank causes a reload of the specified bank grace period +//! input value into the bank down counter. After the last access to the +//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock +//! cycles before putting the bank into one of the fallback power modes as +//! determined by \c ui32PowerMode. This value must be greater than 1 when the +//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Note: The prescaled clock used for the down counter is a clock divided by +//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if +//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! Any access to flash memory causes the pump grace period down counter to +//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep, +//! the down counter delays this number of prescaled HCLK clock cycles before +//! entering one of the charge pump fallback power modes as determined by +//! \c ui32PowerMode. The prescaled clock used for the pump grace period down +//! counter is a clock divided by 16 from input HCLK. This parameter is ignored +//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. +//! +//! Note: The \ref FLASH_PWR_DEEP_STDBY_MODE power mode is deprecated and +//! shall not be used. When used this mode will force the same power mode as +//! for \ref FLASH_PWR_OFF_MODE. +//! This function should not be called at any time before powering off Vims. +//! +//! Changing the power mode of the flash module must be a part within a +//! device power mode transition requiring configuration of multiple modules. +//! Refer to documents describing the device power modes. +//! +//! \param ui32PowerMode is the wanted power mode. +//! The defined flash power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE (Not to be used. This mode is deprecated.) +//! \param ui32BankGracePeriod is the starting count value for the bank grace +//! period down counter. +//! \param ui32PumpGracePeriod is the starting count value for the pump grace +//! period down counter. +//! +//! \return None +// +//***************************************************************************** +extern void FlashPowerModeSet(uint32_t ui32PowerMode, + uint32_t ui32BankGracePeriod, + uint32_t ui32PumpGracePeriod); + +//***************************************************************************** +// +//! \brief Get current configured power mode. +//! +//! This function will return the current configured power mode. +//! +//! \return Returns the current configured power mode. +//! The defined power modes are: +//! - \ref FLASH_PWR_ACTIVE_MODE +//! - \ref FLASH_PWR_OFF_MODE +//! - \ref FLASH_PWR_DEEP_STDBY_MODE (Not to be used. This mode is deprecated.) +// +//***************************************************************************** +extern uint32_t FlashPowerModeGet(void); + +//***************************************************************************** +// +//! \brief Set sector protection. +//! +//! This function will set the specified protection on specified flash bank +//! sector. A sector can either have no protection or have write protection +//! which guards for both program and erase of that sector. +//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to +//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can +//! only be set back to unprotected by a device reset. +//! +//! \param ui32SectorAddress is the start address of the sector to protect. +//! \param ui32ProtectMode is the enumerated sector protection mode. +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +//! +//! \return None +// +//***************************************************************************** +extern void FlashProtectionSet(uint32_t ui32SectorAddress, + uint32_t ui32ProtectMode); + +//***************************************************************************** +// +//! \brief Get sector protection. +//! +//! This return the protection mode for the specified flash bank sector. +//! +//! \param ui32SectorAddress is the start address of the desired sector. +//! +//! \return Returns the sector protection: +//! - \ref FLASH_NO_PROTECT +//! - \ref FLASH_WRITE_PROTECT +// +//***************************************************************************** +extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Save sector protection to make it permanent. +//! +//! This function will save the current protection mode for the specified +//! flash bank sector. +//! +//! This function must only be executed from ROM or SRAM. +//! +//! \note A write protected sector will become permanent write +//! protected!! A device reset will not change the write protection! +//! +//! \param ui32SectorAddress is the start address of the sector to be protected. +//! +//! \return Returns the status of the sector protection: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress); + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine has detected an error. +//! +//! This function returns the status of the Flash State Machine indicating if +//! an error is detected or not. Primary use is to check if an Erase or +//! Program operation has failed. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAM while any part of the flash is being programmed or erased. +//! +//! \return Returns status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_ERROR +//! - \ref FAPI_STATUS_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForError(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + { + return(FAPI_STATUS_FSM_ERROR); + } + else + { + return(FAPI_STATUS_SUCCESS); + } +} + +//***************************************************************************** +// +//! \brief Checks if the Flash state machine is ready. +//! +//! This function returns the status of the Flash State Machine indicating if +//! it is ready to accept a new command or not. Primary use is to check if an +//! Erase or Program operation has finished. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. This function must be called from ROM or +//! SRAMh while any part of the flash is being programmed or erased. +//! +//! \return Returns readiness status of Flash state machine: +//! - \ref FAPI_STATUS_FSM_READY +//! - \ref FAPI_STATUS_FSM_BUSY +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashCheckFsmForReady(void) +{ + if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY_M) + { + return(FAPI_STATUS_FSM_BUSY); + } + else + { + return(FAPI_STATUS_FSM_READY); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the flash +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_FLASH, pfnHandler); + + // Enable the flash interrupt. + IntEnable(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a FLASH interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_FLASH); + + // Unregister the interrupt handler. + IntUnregister(INT_FLASH); +} + +//***************************************************************************** +// +//! \brief Enables flash controller interrupt sources. +//! +//! This function enables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntEnable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Disables individual flash controller interrupt sources. +//! +//! This function disables the flash controller interrupt sources. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. +//! - \ref FLASH_INT_RV : Read verify error interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntDisable(uint32_t ui32IntFlags) +{ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the Flash. +//! +//! \return Returns the current interrupt status as values described in +//! \ref FlashIntEnable(). +// +//***************************************************************************** +__STATIC_INLINE uint32_t +FlashIntStatus(void) +{ + uint32_t ui32IntFlags; + + ui32IntFlags = 0; + + // Check if FSM_DONE interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE) + { + ui32IntFlags = FLASH_INT_FSM_DONE; + } + + // Check if RVF_INT interrupt status is set. + if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT) + { + ui32IntFlags |= FLASH_INT_RV; + } + + return(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears flash controller interrupt source. +//! +//! The flash controller interrupt source is cleared, so that it no longer +//! asserts. This must be done in the interrupt handler to keep it from being +//! called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. +//! Can be any of: +//! - \ref FLASH_INT_FSM_DONE +//! - \ref FLASH_INT_RV +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +FlashIntClear(uint32_t ui32IntFlags) +{ + uint32_t ui32TempVal; + + ui32TempVal = 0; + + if(ui32IntFlags & FLASH_INT_FSM_DONE) + { + ui32TempVal = FLASH_FEDACSTAT_FSM_DONE; + } + + if(ui32IntFlags & FLASH_INT_RV) + { + ui32TempVal |= FLASH_FEDACSTAT_RVF_INT; + } + + // Clear the flash interrupt source. + HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal; +} + +//***************************************************************************** +// +//! \brief Erase a flash sector. +//! +//! This function will erase the specified flash sector. The function will +//! not return until the flash sector has been erased or an error condition +//! occurred. If flash top sector is erased the function will program the +//! the device security data bytes with default values. The device security +//! data located in the customer configuration area of the flash top sector, +//! must have valid values at all times. These values affect the configuration +//! of the device during boot. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! \param ui32SectorAddress is the starting address in flash of the sector to be +//! erased. +//! +//! \return Returns the status of the sector erase: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); + + +//***************************************************************************** +// +//! \brief Programs unprotected flash sectors in the main bank. +//! +//! This function programs a sequence of bytes into the on-chip flash. +//! Programming each location consists of the result of an AND operation +//! of the new data and the existing data; in other words bits that contain +//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +//! to 1. Therefore, a byte can be programmed multiple times as long as these +//! rules are followed; if a program operation attempts to change a 0 bit to +//! a 1 bit, that bit will not have its value changed. +//! +//! This function does not return until the data has been programmed or a +//! programming error occurs. +//! +//! \note It is recommended to disable cache and line buffer before programming the +//! flash. Cache and line buffer are not automatically updated if a flash program +//! causes a mismatch between new flash content and old content in cache and +//! line buffer. Remember to enable cache and line buffer when the program +//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(), +//! and \ref VIMSLineBufEnable() for more information. +//! +//! \warning Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. The application must disable interrupts that have +//! interrupt routines in flash. This function calls a ROM function which handles the +//! actual program operation. +//! +//! The \c pui8DataBuffer pointer can not point to flash. +//! +//! \param pui8DataBuffer is a pointer to the data to be programmed. +//! \param ui32Address is the starting address in flash to be programmed. +//! \param ui32Count is the number of bytes to be programmed. +//! +//! \return Returns status of the flash programming: +//! - \ref FAPI_STATUS_SUCCESS : Success. +//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. +// +//***************************************************************************** +extern uint32_t FlashProgram(uint8_t *pui8DataBuffer, + uint32_t ui32Address, uint32_t ui32Count); + +//***************************************************************************** +// +//! \brief Reads efuse data from specified row. +//! +//! This function will read one efuse row. +//! It is assumed that any previous efuse operation has finished. +//! +//! \param pui32EfuseData is pointer to variable to be updated with efuse data. +//! \param ui32RowAddress is the efuse row number to be read. First row is row +//! number 0. +//! +//! \return Returns the status of the efuse read operation. +//! - \c false : OK status. +//! - \c true : Error status +// +//***************************************************************************** +extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData, + uint32_t ui32RowAddress); + +//***************************************************************************** +// +//! \brief Disables all sectors for erase and programming on the active bank. +//! +//! This function disables all sectors for erase and programming on the active +//! bank and enables the Idle Reading Power reduction mode if no low power +//! mode is configured. Furthermore, an additional level of protection from +//! erase is enabled. +//! +//! \note Please note that code can not execute in flash while any part of the flash +//! is being programmed or erased. +//! +//! \return None +// +//***************************************************************************** +extern void FlashDisableSectorsForWrite(void); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_FlashPowerModeSet + #undef FlashPowerModeSet + #define FlashPowerModeSet ROM_FlashPowerModeSet + #endif + #ifdef ROM_FlashPowerModeGet + #undef FlashPowerModeGet + #define FlashPowerModeGet ROM_FlashPowerModeGet + #endif + #ifdef ROM_FlashProtectionSet + #undef FlashProtectionSet + #define FlashProtectionSet ROM_FlashProtectionSet + #endif + #ifdef ROM_FlashProtectionGet + #undef FlashProtectionGet + #define FlashProtectionGet ROM_FlashProtectionGet + #endif + #ifdef ROM_FlashProtectionSave + #undef FlashProtectionSave + #define FlashProtectionSave ROM_FlashProtectionSave + #endif + #ifdef ROM_FlashSectorErase + #undef FlashSectorErase + #define FlashSectorErase ROM_FlashSectorErase + #endif + #ifdef ROM_FlashProgram + #undef FlashProgram + #define FlashProgram ROM_FlashProgram + #endif + #ifdef ROM_FlashEfuseReadRow + #undef FlashEfuseReadRow + #define FlashEfuseReadRow ROM_FlashEfuseReadRow + #endif + #ifdef ROM_FlashDisableSectorsForWrite + #undef FlashDisableSectorsForWrite + #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __FLASH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.c new file mode 100644 index 00000000..88e28548 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: gpio.c +* +* Description: Driver for the GPIO +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "gpio.h" + +// see gpio.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.h new file mode 100644 index 00000000..a9729aba --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio.h @@ -0,0 +1,332 @@ +/****************************************************************************** +* Filename: gpio.h +* +* Description: Defines and prototypes for the GPIO. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpio.h" +#include "debug.h" + +//***************************************************************************** +// +// Check for legal range of variable dioNumber +// +//***************************************************************************** +#ifdef DRIVERLIB_DEBUG +#include "../inc/hw_fcfg1.h" +#include "chipinfo.h" + +static bool +dioNumberLegal( uint32_t dioNumber ) +{ + uint32_t ioCount = + (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> + FCFG1_IOCONF_GPIO_CNT_S ) ; + + // CC13x2 + CC26x2 + if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + { + return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ); + } + // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 + // for all other chips legal range is 0..(dioNumber-1) + else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + { + return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + } + else + { + return ( dioNumber < ioCount ); + } +} +#endif + +//***************************************************************************** +// +// Define constants that shall be passed as the outputEnableValue parameter to +// GPIO_setOutputEnableDio() and will be returned from the function +// GPIO_getOutputEnableDio(). +// +//***************************************************************************** +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Reads a specific DIO. +//! +//! \param dioNumber specifies the DIO to read (0-31). +//! +//! \return Returns 0 or 1 reflecting the input value of the specified DIO. +//! +//! \sa \ref GPIO_writeDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_readDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the input value from the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Writes a value to a specific DIO. +//! +//! \param dioNumber specifies the DIO to update (0-31). +//! \param value specifies the value to write +//! - 0 : Logic zero (low) +//! - 1 : Logic one (high) +//! +//! \return None +//! +//! \sa \ref GPIO_readDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( value == 0 ) || ( value == 1 )); + + // Write 0 or 1 to the byte indexed DOUT map + HWREGB( GPIO_BASE + dioNumber ) = value; +} + +//***************************************************************************** +// +//! \brief Sets a specific DIO to 1 (high). +//! +//! \param dioNumber specifies the DIO to set (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_clearDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setDio( uint32_t dioNumber ) +{ + GPIO_writeDio(dioNumber, 1); +} + +//***************************************************************************** +// +//! \brief Clears a specific DIO to 0 (low). +//! +//! \param dioNumber specifies the DIO to clear (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_setDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearDio( uint32_t dioNumber ) +{ + GPIO_writeDio(dioNumber, 0); +} + +//***************************************************************************** +// +//! \brief Toggles a specific DIO. +//! +//! \param dioNumber specifies the DIO to toggle (0-31). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_toggleDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Toggle the specified DIO. + HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +//! \brief Gets the output enable status of a specific DIO. +//! +//! This function returns the output enable status for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). +//! +//! \return Returns one of the enumerated data types (0 or 1): +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \sa \ref GPIO_setOutputEnableDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getOutputEnableDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the output enable status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Sets output enable of a specific DIO. +//! +//! This function sets the GPIO output enable bit for the specified DIO. +//! The DIO can be configured as either input or output under software control. +//! +//! \param dioNumber specifies the DIO to configure (0-31). +//! \param outputEnableValue specifies the output enable setting of the specified DIO: +//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. +//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. +//! +//! \return None +//! +//! \sa \ref GPIO_getOutputEnableDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || + ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + + // Update the output enable bit for the specified DIO. + HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; +} + +//***************************************************************************** +// +//! \brief Gets the event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO to get the event status from (0-31). +//! +//! \return Returns the current event status on the specified DIO. +//! - 0 : Non-triggered event. +//! - 1 : Triggered event. +//! +//! \sa \ref GPIO_clearEventDio() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +GPIO_getEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Return the event status for the specified DIO. + return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); +} + +//***************************************************************************** +// +//! \brief Clears the IO event status of a specific DIO. +//! +//! \param dioNumber specifies the DIO on which to clear the event status (0-31). +//! +//! \return None +//! +//! \sa \ref GPIO_getEventDio() +// +//***************************************************************************** +__STATIC_INLINE void +GPIO_clearEventDio( uint32_t dioNumber ) +{ + // Check the arguments. + ASSERT( dioNumberLegal( dioNumber )); + + // Clear the event status for the specified DIO. + HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPIO_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio_doc.h new file mode 100644 index 00000000..ad1ef6d8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/gpio_doc.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* Filename: gpio_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup gpio_api +//! @{ +//! \section sec_gpio Introduction +//! +//! The GPIO module allows software to control the pins of the device directly if the IOC module has +//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can +//! be hardware controlled by other peripheral modules. For more information about the IOC module, +//! how to configure physical pins, and how to select between software controlled and hardware controlled, +//! see the [IOC API](\ref ioc_api). +//! +//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC +//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the +//! System CPU can write these DIOs through the GPIO module. +//! +//! The IOC module can also be configured to generate events on edge detection and these events can be +//! read and cleared in the GPIO module by the System CPU. +//! +//! \section sec_gpio_api API +//! +//! The API functions can be grouped like this: +//! +//! Set and get direction of DIO (output enable): +//! - \ref GPIO_setOutputEnableDio() +//! - \ref GPIO_getOutputEnableDio() +//! +//! Write DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_writeDio() +//! +//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): +//! - \ref GPIO_setDio() +//! - \ref GPIO_clearDio() +//! - \ref GPIO_toggleDio() +//! +//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_readDio() +//! +//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): +//! - \ref GPIO_getEventDio() +//! - \ref GPIO_clearEventDio() +//! +//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using +//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage: +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_analog_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_analog_doc.h new file mode 100644 index 00000000..d54dc943 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_analog_doc.h @@ -0,0 +1,103 @@ +/****************************************************************************** +* Filename: group_analog_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup analog_group +//! @{ +//! \section sec_analog Introduction +//! +//! Access to registers in the analog domain of the device goes through master modules controlling slave +//! modules which contain the actual registers. The master module is located in the digital domain of the +//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface) +//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave +//! modules are referred to as ADI slave and DDI slave. +//! +//! The ADI and DDI APIs provide access to these registers: +//! - ADI_2_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - SOC LDO control +//! - ADI_3_REFSYS : Reference System for generating reference voltages and reference currents. +//! - Reference system control +//! - DC/DC control +//! - ADI_4_AUX : Controlling analog peripherals of AUX. +//! - Multiplexers +//! - Current source +//! - Comparators +//! - ADCs +//! - DDI_0_OSC : Controlling the oscillators (via AUX domain) +//! +//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of +//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the +//! slave registers of interest without being concerned with the ADI/DDI master part of the interface. +//! +//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about +//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs. +//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read +//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8 +//! transactions in the ADI protocol. +//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete. +//! - ADI slave registers are 8-bit wide. +//! - DDI slave registers are 32-bit wide. +//! - ADI/DDI master supports multiple data width accesses seen from the system CPU +//! (however, not all bit width accesses are supported by the APIs): +//! - Read: 8, 16, 32-bit +//! - Write +//! - Direct (write, set, clear): 8, 16, 32-bit +//! - Masked: 4, 8, 16-bit +//! +//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue +//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered +//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing +//! execution. +//! +//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU +//! receives the response thus the programmer must understand that the response time depends on the number of bytes +//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done +//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum. +//! +//! Consequently, if making posted/buffered writes then the written value will not take effect in the +//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make +//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU +//! waiting until both the write and the read have completed. +//! +//! \note +//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible +//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a +//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions. +//! Thus to use masked writes: +//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]). +//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]). +//! +//! \note +//! If masked write is not allowed, a regular read-modify-write is necessary. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aon_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aon_doc.h new file mode 100644 index 00000000..37837e0e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aon_doc.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* Filename: group_aon_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aon_group +//! @{ +//! \section sec_aon Introduction +//! +//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain. +//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain +//! see the [AUX API](@ref aux_group). +//! +//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode +//! (digital supply is off), and the AON power domain is clocked at 32-kHz. +//! +//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the +//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant +//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF +//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU: +//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers +//! by the AON IF every AON clock cycle. +//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can +//! continue executing without waiting for this. +//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously. +//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since) +//! thus the value can be up to one AON clock cycle old. +//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register +//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported. +//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling +//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes. +//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for +//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize. +//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read +//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been +//! synchronized at least once before reading the values. +//! +//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers. +//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to +//! minimize the number of required synchronizations. +//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields, +//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay). +//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered +//! writes will generate a delay similar to a read access. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aux_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aux_doc.h new file mode 100644 index 00000000..cdbdf568 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/group_aux_doc.h @@ -0,0 +1,56 @@ +/****************************************************************************** +* Filename: group_aux_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup aux_group +//! @{ +//! \section sec_aux Introduction +//! +//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and +//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital +//! converter, etc. AUX_PD is located within the AON voltage domain of the device. +//! +//! The sensor controller has the ability to +//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor +//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited +//! resources compared to the larger MCU domain. +//! +//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring +//! that all modules connected to the AUX bus are accessible from the system CPU. +//! Accessing the analog peripherals from the system CPU must be done by using TI-provided +//! drivers to ensure proper control of power management. +//! +//! \note To ease development of program code running on the sensor controller, TI provides a tool +//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully +//! integrated tool consisting of an IDE, compiler, assembler, and linker. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.c new file mode 100644 index 00000000..45125aa7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* Filename: i2c.c +* +* Description: Driver for the I2C module +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2c.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #undef I2CMasterErr + #define I2CMasterErr NOROM_I2CMasterErr + #undef I2CIntRegister + #define I2CIntRegister NOROM_I2CIntRegister + #undef I2CIntUnregister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// Initializes the I2C Master block +// +//***************************************************************************** +void +I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast) +{ + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(ui32Base); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; +} + +//***************************************************************************** +// +// Gets the error status of the I2C Master module +// +//***************************************************************************** +uint32_t +I2CMasterErr(uint32_t ui32Base) +{ + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(ui32Base + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the I2C interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the I2C module +// +//***************************************************************************** +void +I2CIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the interrupt number. + ui32Int = INT_I2C_IRQ; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.h new file mode 100644 index 00000000..5093e713 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c.h @@ -0,0 +1,972 @@ +/****************************************************************************** +* Filename: i2c.h +* +* Description: Defines and prototypes for the I2C. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2c_api +//! @{ +// +//***************************************************************************** + +#ifndef __I2C_H__ +#define __I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_i2c.h" +#include "../inc/hw_sysctl.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk + #define I2CMasterErr NOROM_I2CMasterErr + #define I2CIntRegister NOROM_I2CIntRegister + #define I2CIntUnregister NOROM_I2CIntUnregister +#endif + +//***************************************************************************** +// +// I2C Master commands +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master error status +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte + +//***************************************************************************** +// +// I2C Slave interrupts +// +//***************************************************************************** +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2C base address. +//! +//! This function determines if a I2C port base address is valid. +//! +//! \param ui32Base is the base address of the I2C port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise +// +//***************************************************************************** +static bool +I2CBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2C0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master, and will have enabled the I2C Master block. +//! +//! If the parameter \c bFast is \c true, then the master block will be set up +//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data +//! at 100 kbps. +//! +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. +//! \param bFast set up for fast data transfers. +//! +//! \return None +// +//***************************************************************************** +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); + +//***************************************************************************** +// +//! \brief Controls the state of the I2C Master module. +//! +//! This function is used to control the state of the Master module send and +//! receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32Cmd is the command to be issued by the I2C Master module +//! The parameter can be one of the following values: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT +//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH +//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || + // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || + (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); + + // Send the command. + HWREG(ui32Base + I2C_O_MCTRL) = ui32Cmd; + + // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT + // register has been correctly updated before function exit + CPUdelay(2); +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. When the \e bReceive parameter is set +//! to \b true, the address will indicate that the I2C Master is initiating a +//! read from the slave; otherwise the address will indicate that the I2C +//! Master is initiating a write to the slave. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8SlaveAddr is a 7-bit slave address +//! \param bReceive flag indicates the type of communication with the slave. +//! - \c true : I2C Master is initiating a read from the slave. +//! - \c false : I2C Master is initiating a write to the slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, + bool bReceive) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set the address of the slave with which the master will communicate. + HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; +} + +//***************************************************************************** +// +//! \brief Enables the I2C Master block. +//! +//! This will enable operation of the I2C Master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock for the master. + HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; + + // Enable the master block. + HWREG(ui32Base + I2C_O_MCTRL) = I2C_MCTRL_RUN; +} + +//***************************************************************************** +// +//! \brief Disables the I2C master block. +//! +//! This will disable operation of the I2C master block. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master block. + HWREG(ui32Base + I2C_O_MCTRL) = 0; + + // Disable the clock for the master. + HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C Master is busy. +//! +//! This function returns an indication of whether or not the I2C Master is +//! busy transmitting or receiving data. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of I2C Master: +//! - \c true : I2C Master is busy. +//! - \c false : I2C Master is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the busy status. + if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-master environment to determine if +//! another master is currently using the bus. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns status of the I2C bus: +//! - \c true : I2C bus is busy. +//! - \c false : I2C bus is not busy. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterBusBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the bus busy status. + if(HWREG(ui32Base + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) + { + return(true); + } + else + { + return(false); + } +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master. +//! +//! This function reads a byte of data from the I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C Master, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CMasterDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(ui32Base + I2C_O_MDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Master. +//! +//! This function will place the supplied data into I2C Master Data Register. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui8Data is the data to be transmitted by the I2C Master +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(ui32Base + I2C_O_MDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Gets the error status of the I2C Master module. +//! +//! This function is used to obtain the error status of the Master module send +//! and receive operations. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return Returns the error status of the Master module: +//! - \ref I2C_MASTER_ERR_NONE +//! - \ref I2C_MASTER_ERR_ADDR_ACK +//! - \ref I2C_MASTER_ERR_DATA_ACK +//! - \ref I2C_MASTER_ERR_ARB_LOST +// +//***************************************************************************** +extern uint32_t I2CMasterErr(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the I2C Master interrupt. +//! +//! Enables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the master interrupt. + HWREG(ui32Base + I2C_O_MIMR) = I2C_MIMR_IM; +} + +//***************************************************************************** +// +//! \brief Disables the I2C Master interrupt. +//! +//! Disables the I2C Master interrupt source. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the master interrupt. + HWREG(ui32Base + I2C_O_MIMR) = 0; +} + +//***************************************************************************** +// +//! \brief Clears I2C Master interrupt sources. +//! +//! The I2C Master interrupt source is cleared, so that it no longer asserts. +//! This must be done in the interrupt handler to keep it from being called +//! again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CMasterIntClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C master interrupt source. + HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Master interrupt status. +//! +//! This returns the interrupt status for the I2C Master module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status. +//! - \c true : Active. +//! - \c false : Not active. +// +//***************************************************************************** +__STATIC_INLINE bool +I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); + } + else + { + return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); + } +} + +//***************************************************************************** +// +//! \brief Enables the I2C Slave block. +//! +//! This will enable operation of the I2C Slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Enable the clock to the slave block. + HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; + + // Enable the slave. + HWREG(ui32Base + I2C_O_SCTL) = I2C_SCTL_DA; +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C Slave block. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address and have enabled the I2C Slave block. +//! +//! The parameter \c ui8SlaveAddr is the value that will be compared against the +//! slave address sent by an I2C master. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Must enable the device before doing anything else. + I2CSlaveEnable(ui32Base); + + // Set up the slave address. + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Sets the I2C slave address. +//! +//! This function writes the specified slave address. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8SlaveAddr is the 7-bit slave address +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(!(ui8SlaveAddr & 0x80)); + + // Set up the primary slave address. + HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; +} + +//***************************************************************************** +// +//! \brief Disables the I2C slave block. +//! +//! This will disable operation of the I2C slave block. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Disable the slave. + HWREG(ui32Base + I2C_O_SCTL) = 0x0; + + // Disable the clock to the slave block. + HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the I2C Slave module status. +//! +//! This function will return the action requested from a master, if any. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the status of the I2C Slave module: +//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module. +//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data. +//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave +//! and the first byte following the slave's own address has been received. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return the slave status. + return(HWREG(ui32Base + I2C_O_SSTAT)); +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Slave. +//! +//! This function reads a byte of data from the I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C Slave, cast as an +//! uint32_t. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveDataGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Read a byte. + return(HWREG(ui32Base + I2C_O_SDR)); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Slave. +//! +//! This function will place the supplied data into I2C Slave Data Register. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui8Data data to be transmitted from the I2C Slave. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Write the byte. + HWREG(ui32Base + I2C_O_SDR) = ui8Data; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C Slave interrupt sources. +//! +//! Enables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Enable the slave interrupt. + ui32Val = HWREG(ui32Base + I2C_O_SIMR); + ui32Val |= ui32IntFlags; + HWREG(ui32Base + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C Slave interrupt sources. +//! +//! Disables the indicated I2C Slave interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + uint32_t ui32Val; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | + I2C_SLAVE_INT_DATA)); + + // Disable the slave interrupt. + ui32Val = HWREG(ui32Base + I2C_O_SIMR); + ui32Val &= ~ui32IntFlags; + HWREG(ui32Base + I2C_O_SIMR) = ui32Val; +} + +//***************************************************************************** +// +//! \brief Clears I2C Slave interrupt sources. +//! +//! The specified I2C Slave interrupt sources are cleared, so that they no +//! longer assert. This must be done in the interrupt handler to keep it from +//! being called again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2C module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Clear the I2C slave interrupt source. + HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current I2C Slave interrupt status. +//! +//! This returns the interrupt status for the I2C Slave module. Either the raw +//! interrupt status or the status of interrupts that are allowed to reflect to +//! the processor can be returned. +//! +//! \param ui32Base is the base address of the I2C Slave module. +//! \param bMasked selects either raw or masked interrupt status. +//! - \c false : Raw interrupt status is requested. +//! - \c true : Masked interrupt status is requested. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref I2C_SLAVE_INT_STOP +//! - \ref I2C_SLAVE_INT_START +//! - \ref I2C_SLAVE_INT_DATA +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + I2C_O_SMIS)); + } + else + { + return(HWREG(ui32Base + I2C_O_SRIS)); + } +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and +//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's +//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and +//! \ref I2CSlaveIntClear(). +//! +//! \param ui32Base is the base address of the I2C Master module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2C interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when an I2C interrupt +//! occurs. This will also mask off the interrupt in the interrupt controller +//! so that the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2C Master module. +//! +//! \return None +//! +//! \sa \brief IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void I2CIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2CMasterInitExpClk + #undef I2CMasterInitExpClk + #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk + #endif + #ifdef ROM_I2CMasterErr + #undef I2CMasterErr + #define I2CMasterErr ROM_I2CMasterErr + #endif + #ifdef ROM_I2CIntRegister + #undef I2CIntRegister + #define I2CIntRegister ROM_I2CIntRegister + #endif + #ifdef ROM_I2CIntUnregister + #undef I2CIntUnregister + #define I2CIntUnregister ROM_I2CIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2C_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c_doc.h new file mode 100644 index 00000000..53e5a1cd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2c_doc.h @@ -0,0 +1,160 @@ +/****************************************************************************** +* Filename: i2c_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2c_api +//! @{ +//! \section sec_i2c Introduction +//! +//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using +//! the \ti_device \i2c master and slave module. Functions are provided to perform +//! the following actions: +//! - Initialize the \i2c module. +//! - Send and receive data. +//! - Obtain status. +//! - Manage interrupts for the \i2c module. +//! +//! The \i2c master and slave module provide the ability to communicate to other IC +//! devices over an \i2c bus. The \i2c bus is specified to support devices that can +//! both transmit and receive (write and read) data. Also, devices on the \i2c bus +//! can be designated as either a master or a slave. The \ti_device \i2c module +//! supports both sending and receiving data as either a master or a slave, and also +//! support the simultaneous operation as both a master and a slave. Finally, the +//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast +//! (400 kb/s). +//! +//! The master and slave \i2c module can generate interrupts. The \i2c master +//! module generates interrupts when a transmit or receive operation +//! completes (or aborts due to an error). +//! The \i2c slave module can generate interrupts when data is +//! sent or requested by a master and when a START or STOP condition is present. +//! +//! \section sec_i2c_master Master Operations +//! +//! When using this API to drive the \i2c master module, the user must first +//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This +//! function sets the bus speed and enables the master module. +//! +//! The user may transmit or receive data after the successful initialization of +//! the \i2c master module. Data is transferred by first setting the slave address +//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether +//! the transfer is a send (a write to the slave from the master) or a receive (a +//! read from the slave by the master). Then, if connected to an \i2c bus that has +//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy() +//! before trying to initiate the desired transaction. After determining that +//! the bus is not busy, if trying to send data, the user must call the +//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus +//! by calling the \ref I2CMasterControl() function with any of the following commands: +//! - \ref I2C_MASTER_CMD_SINGLE_SEND +//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE +//! - \ref I2C_MASTER_CMD_BURST_SEND_START +//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START +//! +//! Any of these commands result in the master arbitrating for the bus, +//! driving the start sequence onto the bus, and sending the slave address and +//! direction bit across the bus. The remainder of the transaction can then be +//! driven using either a polling or interrupt-driven method. +//! +//! For the single send and receive cases, the polling method involves looping +//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c +//! master is no longer busy, the bus transaction is complete and can be +//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data +//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst +//! send and receive cases, the polling method also involves calling the +//! \ref I2CMasterControl() function for each byte transmitted or received +//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT +//! commands), and for the last byte sent or received (using either the +//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH +//! commands). +//! +//! If any error is detected during the burst transfer, +//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or +//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the +//! \ref I2CMasterControl() function. +//! +//! For the interrupt-driven transaction, the user must register an interrupt +//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt +//! occurs when the master is no longer busy. +//! +//! \section sec_i2c_slave Slave Operations +//! +//! When using this API to drive the \i2c slave module, the user must first +//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function +//! enables the \i2c slave module and initializes the address of the slave. After the +//! initialization completes, the user may poll the slave status using +//! \ref I2CSlaveStatus() to determine if a master requested a send or receive +//! operation. Depending on the type of operation requested, the user can call +//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction. +//! Alternatively, the \i2c slave can handle transactions using an interrupt handler +//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt. +//! +//! \section sec_i2c_api API +//! +//! The \i2c API is broken into three groups of functions: +//! those that handle status and initialization, those that +//! deal with sending and receiving data, and those that deal with +//! interrupts. +//! +//! Status and initialization functions for the \i2c module are: +//! - \ref I2CMasterInitExpClk() +//! - \ref I2CMasterEnable() +//! - \ref I2CMasterDisable() +//! - \ref I2CMasterBusBusy() +//! - \ref I2CMasterBusy() +//! - \ref I2CMasterErr() +//! - \ref I2CSlaveInit() +//! - \ref I2CSlaveEnable() +//! - \ref I2CSlaveDisable() +//! - \ref I2CSlaveStatus() +//! +//! Sending and receiving data from the \i2c module is handled by the following functions: +//! - \ref I2CMasterSlaveAddrSet() +//! - \ref I2CSlaveAddressSet() +//! - \ref I2CMasterControl() +//! - \ref I2CMasterDataGet() +//! - \ref I2CMasterDataPut() +//! - \ref I2CSlaveDataGet() +//! - \ref I2CSlaveDataPut() +//! +//! The \i2c master and slave interrupts are handled by the following functions: +//! - \ref I2CIntRegister() +//! - \ref I2CIntUnregister() +//! - \ref I2CMasterIntEnable() +//! - \ref I2CMasterIntDisable() +//! - \ref I2CMasterIntClear() +//! - \ref I2CMasterIntStatus() +//! - \ref I2CSlaveIntEnable() +//! - \ref I2CSlaveIntDisable() +//! - \ref I2CSlaveIntClear() +//! - \ref I2CSlaveIntStatus() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.c new file mode 100644 index 00000000..ffe9fd3c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.c @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: i2s.c +* +* Description: Driver for the I2S. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "i2s.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef I2SEnable + #define I2SEnable NOROM_I2SEnable + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #undef I2SBufferConfig + #define I2SBufferConfig NOROM_I2SBufferConfig + #undef I2SPointerUpdate + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #undef I2SPointerSet + #define I2SPointerSet NOROM_I2SPointerSet + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #undef I2SSampleStampGet + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +// Global pointer to the current I2S data structure +// +//***************************************************************************** +I2SControlTable *g_pControlTable; + +//***************************************************************************** +// +// Enables the I2S module for operation +// +//***************************************************************************** +void +I2SEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Make sure the control table pointer is setup to a memory location. + if(!(g_pControlTable)) + { + return; + } + + // Write the address to the first input/output buffer. + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase; + g_pControlTable->ui32InOffset = 0; + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase; + g_pControlTable->ui32OutOffset = 0; + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1; +} + +//***************************************************************************** +// +// Configures the I2S module +// +//***************************************************************************** +void +I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32BitClkDelay <= 255); + + // Save the length of the audio words stored in memory. + g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16; + + // Write the configuration. + HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S); +} + +//**************************************************************************** +// +// Setup the audio channel configuration +// +//**************************************************************************** +void +I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg) +{ + uint32_t ui32InChan; + uint32_t ui32OutChan; + uint32_t ui32ChanMask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) + + ui32InChan = 0; + ui32OutChan = 0; + + // Configure input/output channels. + HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = ( + (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) | + (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) ); + + // Configure the valid channel mask. + HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M; + HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M; + + // Resolve and save the number of input and output channels. + ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan0Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + + } + else if(ui32Chan0Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8; + if(ui32Chan1Cfg & I2S_LINE_INPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32InChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + else if(ui32Chan1Cfg & I2S_LINE_OUTPUT) + { + while(ui32ChanMask) + { + if(ui32ChanMask & 0x1) + { + ui32OutChan++; + } + // Shift down channel mask + ui32ChanMask >>= 1; + } + } + + g_pControlTable->ui8InChan = (uint8_t)ui32InChan; + g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan; +} + +//**************************************************************************** +// +// Set the input buffer pointers +// +//**************************************************************************** +void +I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui16DMABufSize > 0); + + // Setup the input data pointer and buffer sizes. + g_pControlTable->ui16DMABufSize = ui16DMABufSize; + g_pControlTable->ui16ChBufSize = ui16ChanBufSize; + g_pControlTable->ui32InBase = ui32InBufBase; + g_pControlTable->ui32OutBase = ui32OutBufBase; +} + +//**************************************************************************** +// +// Set the buffer pointers +// +//**************************************************************************** +void +I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +//**************************************************************************** +// +// Update the buffer pointers +// +//**************************************************************************** +void +I2SPointerUpdate(uint32_t ui32Base, bool bInput) +{ + uint32_t ui32NextPtr; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + ui32NextPtr = (g_pControlTable->ui8InChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset + + g_pControlTable->ui32InBase; + } + else + { + ui32NextPtr = (g_pControlTable->ui8OutChan * + (g_pControlTable->ui16MemLen >> 3)) * + g_pControlTable->ui16DMABufSize; + g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset + + ui32NextPtr) % + g_pControlTable->ui16ChBufSize); + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = + g_pControlTable->ui32OutOffset + + g_pControlTable->ui32OutBase; + } +} + +//***************************************************************************** +// +// Configure the sample stamp generator +// +//***************************************************************************** +void +I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput) +{ + uint32_t ui32Trigger; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT); + ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize; + + // Setup the sample stamp trigger for input streams. + if(bInput) + { + HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger; + } + + // Setup the sample stamp trigger for output streams. + if(bOutput) + { + HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger; + } + +} + +//***************************************************************************** +// +// Get the current value of a sample stamp counter +// +//***************************************************************************** +uint32_t +I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) +{ + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.h new file mode 100644 index 00000000..cabf449a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s.h @@ -0,0 +1,1357 @@ +/****************************************************************************** +* Filename: i2s.h +* +* Description: Defines and prototypes for the I2S. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup i2s_api +//! @{ +// +//**************************************************************************** + +#ifndef __I2S_H__ +#define __I2S_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_i2s.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define I2SEnable NOROM_I2SEnable + #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure + #define I2SChannelConfigure NOROM_I2SChannelConfigure + #define I2SBufferConfig NOROM_I2SBufferConfig + #define I2SPointerUpdate NOROM_I2SPointerUpdate + #define I2SPointerSet NOROM_I2SPointerSet + #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure + #define I2SSampleStampGet NOROM_I2SSampleStampGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an audio control table. Note: Memory for this +//! structure \b must be initialized by user application. See detailed description! +//! +//! \deprecated This structure will be removed in a future release. +//! +//! These fields are used by the I2S and normally it is not necessary for +//! software to directly read or write fields in the table. +//! +//! \note The control table must be defined by the user as a global variable and +//! the global pointer must then be assigned the address of the control table +//! inside a user function (but before calling any I2S-function). +//! +/*! +\verbatim + I2SControlTable g_controlTable; // Define global + g_pControlTable = &g_controlTable; // Assign pointer (inside a function) +\endverbatim +*/ +//! +// +//***************************************************************************** +#ifndef DEPRECATED +typedef struct +{ + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. +} I2SControlTable; +#endif + +//***************************************************************************** +// +// Declare global pointer to the I2S data structure. +// +// The control table must be defined by the user as a global variable and the +// global pointer must then be assigned the address of the control table: +// +// I2SControlTable g_controlTable; +// g_pControlTable = &g_controlTable; +// +//***************************************************************************** +#ifndef DEPRECATED +extern I2SControlTable *g_pControlTable; +#endif + +//***************************************************************************** +// +// Defines for the I2S DMA buffer sizes +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 +#endif + +//***************************************************************************** +// +// Defines for the I2S audio clock configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 +#endif + +//***************************************************************************** +// +// Defines for the audio data line input/output configuration +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 +#endif + +//***************************************************************************** +// +// Defines for activating an audio channel. +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 +#endif + +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 + +//***************************************************************************** +// +// Defines for the audio format configuration +// +//***************************************************************************** +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits + +//***************************************************************************** +// +// Defines for the sample stamp counters +// +//***************************************************************************** +#ifndef DEPRECATED +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#endif +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when + // calculating the sample stamp + +//***************************************************************************** +// +// Defines for the interrupt +// +//***************************************************************************** +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an I2S base address. +//! +//! This function determines if an I2S port base address is valid. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +I2SBaseValid(uint32_t ui32Base) +{ + return(ui32Base == I2S0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note The module should only be enabled after configuration. When the +//! module is disabled, no data or clocks will be generated on the I2S signals. +//! +//! \note Immediately after enabling the module the programmer should update +//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new +//! pointer is written before the DMA transfer completes. Failure to update +//! the pointer in time will result in an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SEnable(uint32_t ui32Base); +#endif + +//***************************************************************************** +// +//! \brief Disables the I2S module for operation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SPointerUpdate(). +//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR. +//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using +//! \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; +} +#endif + +//***************************************************************************** +// +//! \brief Configures the I2S module. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. The size is set using \ref I2S_WORD_LENGTH_8, +//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui32FmtCfg is the bitwise OR of several options: +//! - Sample size: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! - Clock edge sampling: +//! - \ref I2S_POS_EDGE +//! - \ref I2S_NEG_EDGE +//! - Phase: +//! - \ref I2S_DUAL_PHASE_FMT +//! - \ref I2S_SINGLE_PHASE_FMT +//! - Word length: +//! - \ref I2S_WORD_LENGTH_8 +//! - \ref I2S_WORD_LENGTH_16 +//! - \ref I2S_WORD_LENGTH_24 +//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the +//! positive word clock edge and the MSB of the first word in a phase. The bit +//! clock delay is determined by the ratio between the bit clock and the frame +//! clock and the chosen audio format. The bit clock delay \b must be configured +//! depending on the chosen audio format: +//! - 0 : Left Justified Format (LJF). +//! - 1 : I2S and DSP format. +//! - 2-255 : Right Justified format (RJF). +//! +//! \return None +//! +//! \sa \ref I2SChannelConfigure() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, + uint32_t ui32BitClkDelay); +#endif + +//**************************************************************************** +// +//! \brief Setup the audio channel configuration. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The channel configuration is a bitwise OR of the input/output mode of each +//! data line and the active audio channels within a specific audio frame. +//! +//! Setting up the input/output mode use one of: +//! - \ref I2S_LINE_UNUSED +//! - \ref I2S_LINE_INPUT +//! - \ref I2S_LINE_OUTPUT +//! +//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed. +//! For single phased audio format (DSP) up to 8 active channels are allowed +//! on a single data line. For setting up the active channels in a frame use: +//! - Single phased, use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_ACT +//! - \ref I2S_CHAN1_ACT +//! - \ref I2S_CHAN2_ACT +//! - \ref I2S_CHAN3_ACT +//! - \ref I2S_CHAN4_ACT +//! - \ref I2S_CHAN5_ACT +//! - \ref I2S_CHAN6_ACT +//! - \ref I2S_CHAN7_ACT +//! - Dual phased, use one of: +//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT) +//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT) +//! +//! \note The audio format and the clock configuration should be set using +//! \ref I2SAudioFormatConfigure() +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui32Chan0Cfg defines the channel configuration for data line 0. +//! \param ui32Chan1Cfg defines the channel configuration for data line 1. +//! +//! \return None +//! +//! \sa \ref I2SAudioFormatConfigure() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, + uint32_t ui32Chan1Cfg); +#endif + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Configure I2S clock to be either internal or external and either normal +//! or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed +//! combination of clock source and clock polarity: +//! - Clock source: +//! - \ref I2S_EXT_WCLK : External clock. +//! - \ref I2S_INT_WCLK : Internal clock. +//! - Clock polarity: +//! - \ref I2S_NORMAL_WCLK : Normal clock. +//! - \ref I2S_INVERT_WCLK : Inverted clock. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup register WCLK Source. + HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig & + (I2S_AIFWCLKSRC_WCLK_INV_M | + I2S_AIFWCLKSRC_WCLK_SRC_M); +} +#endif + +//**************************************************************************** +// +//! \brief Set the input buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will +//! occur and all outputs will be disabled. +//! +//! \note At startup the next data pointer should be +//! written just before and just after calling the \ref I2SEnable(). +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32InBufBase is the address of the input buffer. +//! \param ui32OutBufBase is the address of the output buffer. +//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0! +//! \param ui16ChanBufSize is the size of the channel buffers. +//! +//! \return None +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, + uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, + uint16_t ui16ChanBufSize); +#endif + +//**************************************************************************** +// +//! \brief Update the buffer pointers. +//! +//! \deprecated This function will be removed in a future release. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! +//! \return None +//! +//! \sa \ref I2SPointerSet() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); +#endif + +//**************************************************************************** +// +//! \brief Set a buffer pointer (input or output) directly. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function allows bypassing of the pointers in the global control table. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur +//! and all outputs will be disabled. Nothing is preventing the pointers from +//! being identical, but this function relies on both pointers (input or +//! output pointers) are pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput determines whether to update input or output pointer. +//! - \c true : Update input pointer. +//! - \c false : Update output pointer +//! \param pNextPointer is a void pointer to user defined buffer. +//! +//! \return None +//! +//! \sa \ref I2SPointerUpdate() +// +//**************************************************************************** +#ifndef DEPRECATED +extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); +#endif + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param pfnHandler is a pointer to the function to be called when the +//! I2S interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Register the interrupt handler. + IntRegister(INT_I2S_IRQ, pfnHandler); + + // Enable the I2S interrupt. + IntEnable(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. +//! +//! \deprecated This function will be removed in a future release. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an I2S interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the I2S port. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +#ifndef DEPRECATED +__STATIC_INLINE void +I2SIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the interrupt. + IntDisable(INT_I2S_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_I2S_IRQ); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the sample stamp generator. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param bInput enables triggering of the sample stamp generator on input. +//! \param bOutput enables triggering of the sample stamp generator on output. +//! +//! \return None +// +//***************************************************************************** +#ifndef DEPRECATED +extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, + bool bOutput); +#endif + +//***************************************************************************** +// +//! \brief Enables individual I2S interrupt sources. +//! +//! This function enables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual I2S interrupt sources. +//! +//! This function disables the indicated I2S interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified I2S. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the I2S port +//! \param bMasked selects between raw and masked interrupt status: +//! - \c false : Raw interrupt status is required. +//! - \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as a vector of: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +I2SIntStatus(uint32_t ui32Base, bool bMasked) +{ + uint32_t ui32Mask; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS); + return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK)); + } + else + { + return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS)); + } +} + +//***************************************************************************** +// +//! \brief Clears I2S interrupt sources. +//! +//! The specified I2S interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the I2S port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref I2S_INT_DMA_IN +//! - \ref I2S_INT_DMA_OUT +//! - \ref I2S_INT_TIMEOUT +//! - \ref I2S_INT_BUS_ERR +//! - \ref I2S_INT_WCLK_ERR +//! - \ref I2S_INT_PTR_ERR +//! - \ref I2S_INT_ALL (covers all the above) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable the Sample Stamp generator. +//! +//! Use this function to enable the sample stamp generators. +//! +//! \note It is the user's responsibility to ensure that the sample stamp +//! generator is properly configured before it is enabled. It is the setting +//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure() +//! that triggers the start point of the audio streams. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Set the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; +} + +//***************************************************************************** +// +//! \brief Disable the Sample Stamp generator. +//! +//! Use this function to disable the sample stamp generators. When the sample +//! stamp generator is disabled, the clock counters are automatically cleared. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Clear the enable bit. + HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; + +} + +//***************************************************************************** +// +//! \brief Get the current value of a sample stamp counter. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32Channel is the sample stamp counter to sample +//! +//! \return Returns the current value of the selected sample stamp channel. +// +//***************************************************************************** +extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); + +//***************************************************************************** +// +//! \brief Starts the I2S. +//! +//! I2S must be configured before it is started. +//! +//! \note Immediately after enabling the module the programmer must update +//! the DMA data pointer registers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA +//! transfer completes. Failure to update the pointer in time will result in +//! an \ref I2S_INT_PTR_ERR. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8FixDMALength is the length of the DMA buffer: this will allow +//! the DMA to read ui8FixDMALength between to pointer refreshes. +//! +//! \return None +//! +//! \sa \ref I2SStop() +// +//***************************************************************************** +__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Enable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; +} + +//***************************************************************************** +// +//! \brief Stops the I2S module for operation. +//! +//! This function will immediately disable the I2S module. To ensure that +//! all buffer operations are completed before shutting down, the correct +//! procedure is: +//! 1. Do not update the data pointers using \ref I2SInPointerSet() and +//! \ref I2SOutPointerSet(). +//! 2. Await that values returned by \ref I2SInPointerNextGet(), +//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() +//! are zero. +//! 3. Disable the I2S using \ref I2SStop() and clear the pointer +//! error using \ref I2SIntClear(). +//! 4. Disable bit clock source (done externally). +//! +//! \param ui32Base is the I2S module base address. +//! +//! \return None +//! +//! \sa \ref I2SStart() +// +//***************************************************************************** +__STATIC_INLINE void I2SStop(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Disable the I2S module. + HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; +} + +//***************************************************************************** +// +//! \brief Configure the serial format of the I2S module. +//! +//! The word length defines the size of the word transmitted on the data +//! lines. For single phased formats \c ui8BitsPerSample is the exact number +//! of bits per word. In dual phased format this is the maximum number of bits +//! per word. +//! +//! \param ui32Base is the I2S module base address. +//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK +//! edge and the MSB of the first audio channel data transferred during +//! the phase. +//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits +//! or 24 bits. Possible values are: +//! - \ref I2S_MEM_LENGTH_16 +//! - \ref I2S_MEM_LENGTH_24 +//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. +//! Possible values are: +//! - \ref I2S_NEG_EDGE +//! - \ref I2S_POS_EDGE +//! \param boolDualPhase must be set to true for dual phase and to false for +//! single phase and user-defined phase. +//! \param ui8BitsPerSample is the number of bits transmitted for each sample. +//! If this number does not match with the memory length selected +//! (16 bits or 24 bits), samples will be truncated or padded. +//! \param ui16transmissionDelay is the number of WCLK periods before the first +//! transmission. +//! +//! \return None +//! +//! \sa \ref I2SFrameConfigure() +// +//***************************************************************************** +__STATIC_INLINE void +I2SFormatConfigure(uint32_t ui32Base, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, + uint16_t ui16transmissionDelay) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8BitsPerSample <= 24); // Max. I2S_AIFFMTCFG_WORD_LEN + ASSERT(ui8BitsPerSample >= 8); // Min. I2S_AIFFMTCFG_WORD_LEN + + // Setup register AIFFMTCFG Source. + HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits ) | + (ui8iSamplingEdge ) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + + // Number of WCLK periods before the first read / write + HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; +} + +//**************************************************************************** +// +//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). +//! +//! This function sets interface's direction and activated channels. +//! +//! \param ui32Base is base address of the I2S module. +//! \param ui8StatusAD0 defines the usage of AD0 +//! 0x00: AD0 is disabled +//! 0x01, AD0 is an input +//! 0x02, AD0 is an output +//! \param ui8ChanAD0 defines the channel mask for AD0. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! \param ui8StatusAD1 defines the usage of AD1 +//! 0x00: AD1 is disabled +//! 0x10, AD1 is an input +//! 0x20, AD1 is an output +//! \param ui8ChanAD1 defines the channel mask for AD1. +//! Use a bitwise OR'ed combination of: +//! - \ref I2S_CHAN0_MASK +//! - \ref I2S_CHAN1_MASK +//! - \ref I2S_CHAN2_MASK +//! - \ref I2S_CHAN3_MASK +//! - \ref I2S_CHAN4_MASK +//! - \ref I2S_CHAN5_MASK +//! - \ref I2S_CHAN6_MASK +//! - \ref I2S_CHAN7_MASK +//! +//! \return None +//! +//! \sa \ref I2SFormatConfigure() +// +//**************************************************************************** +__STATIC_INLINE void +I2SFrameConfigure(uint32_t ui32Base, + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Configure input/output channels. + HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); + + // Configure the valid channel mask. + HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; + HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; +} + +//**************************************************************************** +// +//! \brief Configure the I2S frame clock (also called WCLK or WS). +//! +//! Configure WCLK clock to be either internal (master) or external (slave). +//! Configure WCLK clock either normal or inverted. +//! +//! \note The bit clock configuration is done externally, but the internal/ +//! external setting must match what is chosen internally in the I2S module +//! for the frame clock. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param boolMaster false: the device is a slave (external clock) +//! true: the device is a master (internal clock) +//! \param boolWCLKInvert false: WCLK is not inverted +//! true: WCLK is internally inverted +//! +//! \return None +// +//**************************************************************************** +__STATIC_INLINE void +I2SWclkConfigure(uint32_t ui32Base, + bool boolMaster, + bool boolWCLKInvert) +{ + // if(boolMaster == 0) then ui8ClkSource = 1 + // if(boolMaster == 1) then ui8ClkSource = 2 + uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); + + // Setup register WCLK Source. + HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); +} + +//**************************************************************************** +// +//! \brief Set the input buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SOutPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Set the output buffer pointer. +//! +//! The next pointer should always be written while the DMA is using the +//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR +//! will occur and all inputs and outputs will be disabled. +//! This function relies on pointer is pointing to a valid address. +//! +//! \note It is recommended that the pointer update is done in an interrupt context +//! to ensure that the update is performed before the buffer is full. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui32NextPointer is the adress of the data +//! +//! \return None +//! +//! \sa \ref I2SInPointerSet() +// +//**************************************************************************** +__STATIC_INLINE void +I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); +} + + +//**************************************************************************** +// +//! \brief Get value stored in PTR NEXT OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR NEXT OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerNextGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR IN register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR IN. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SInPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); +} + +//**************************************************************************** +// +//! \brief Get value stored in PTR OUT register +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return the value of PTR OUT. +// +//**************************************************************************** +__STATIC_INLINE uint32_t +I2SOutPointerGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); +} + +//***************************************************************************** +// +//! \brief Configure the IN sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for input streams. + HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Configure the OUT sample stamp generator. +//! +//! Use this function to configure the sample stamp generator. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param ui16TrigValue value used to set the trigger. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Setup the sample stamp trigger for output streams. + HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; +} + +//***************************************************************************** +// +//! \brief Add the specified value to the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! \param i16Value is the offset to add to the counter (this value can be negative) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) +{ + uint16_t ui16MinusValue; + + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + if (i16Value >= 0) + { + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; + } + else + { + ui16MinusValue = (uint16_t)(-i16Value); + HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; + } +} + +//***************************************************************************** +// +//! \brief Reset the WCLK count. +//! +//! \param ui32Base is the base address of the I2S module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +I2SWclkCounterReset(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_I2SEnable + #undef I2SEnable + #define I2SEnable ROM_I2SEnable + #endif + #ifdef ROM_I2SAudioFormatConfigure + #undef I2SAudioFormatConfigure + #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure + #endif + #ifdef ROM_I2SChannelConfigure + #undef I2SChannelConfigure + #define I2SChannelConfigure ROM_I2SChannelConfigure + #endif + #ifdef ROM_I2SBufferConfig + #undef I2SBufferConfig + #define I2SBufferConfig ROM_I2SBufferConfig + #endif + #ifdef ROM_I2SPointerUpdate + #undef I2SPointerUpdate + #define I2SPointerUpdate ROM_I2SPointerUpdate + #endif + #ifdef ROM_I2SPointerSet + #undef I2SPointerSet + #define I2SPointerSet ROM_I2SPointerSet + #endif + #ifdef ROM_I2SSampleStampConfigure + #undef I2SSampleStampConfigure + #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure + #endif + #ifdef ROM_I2SSampleStampGet + #undef I2SSampleStampGet + #define I2SSampleStampGet ROM_I2SSampleStampGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __I2S_H__ + +//**************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//**************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s_doc.h new file mode 100644 index 00000000..892fb780 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/i2s_doc.h @@ -0,0 +1,139 @@ +/****************************************************************************** +* Filename: i2s_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup i2s_api +//! @{ +//! \section sec_i2s Introduction +//! +//! The I2S API provides a set of functions for using the I2S module. +//! This module provides a standardized serial interface to transfer +//! audio samples from and to external audio devices such as a codec, +//! DAC, or ADC. +//! +//! The I2S module has the following features: +//! - Audio clock signals are internally generated by the PRCM module +//! or externally by another device. +//! - One or two data pins, which can be configured independently as +//! input or output +//! - Various data formats according to the settings of the module +//! - Up to two channels per data pin for dual phase formats and up +//! to eight channels per data pin for single phase formats +//! - DMA with double-buffered pointers +//! - Error detection for DMA and audio clock signal integrity +//! - A Samplestamp generator that allows maintaining of constant +//! audio latency +//! +//! The I2S module is configured through the functions \ref I2SFormatConfigure(), +//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). +//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using +//! \ref I2SStop(). Please note that a specific procedure exists in order +//! to disable transfers without losing data (refer to \ref I2SStop()). +//! +//! Data are transmitted using the two double-buffered pointers. +//! For each interface, two registers are set with the address of the data to +//! transfer. These registers are named INPTR and INPTRNEXT for the input +//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, +//! the hardware copies the content of PTRNEXT into PTR and the next transfer +//! begins. +//! The address of the next value to write or to read in memory (i.e. to receive +//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). +//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using +//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and +//! \ref I2SOutPointerGet() functions. +//! +//! Interrupts can help the user to refresh pointers on time. Interrupts can also +//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() +//! activate and deactivate interrupt(s). Interrupt status can be read through +//! \ref I2SIntStatus() and a pending interrupt can be acquitted by +//! \ref I2SIntClear() function. +//! +//! The sample stamps generator can be configured to slightly delay the +//! emission or the reception of the data (based on the number of WCLK +//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), +//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp +//! can be computed using \ref I2SSampleStampGet(). +//! To finish, the sample stamps generator can be enable and disable using +//! the following functions: \ref I2SSampleStampEnable() and +//! \ref I2SSampleStampDisable(). +//! The sample stamps generator must be enabled prior to any transfer. +//! +//! Note: Other functions contained in the PRCM API are required to handle I2S. +//! +//! \section sec_i2s_api API +//! +//! Two APIs are coexisting. +//! It is recommended to only use the new API as the old one is deprecated and +//! will be removed soon. +//! +//! New API: +//! Functions to perform I2S configuration: +//! - \ref I2SStart() +//! - \ref I2SStop() +//! - \ref I2SFormatConfigure() +//! - \ref I2SFrameConfigure() +//! - \ref I2SWclkConfigure() +//! +//! Functions to perform transfers: +//! - \ref I2SInPointerSet() +//! - \ref I2SOutPointerSet() +//! - \ref I2SInPointerGet() +//! - \ref I2SOutPointerGet() +//! - \ref I2SInPointerNextGet() +//! - \ref I2SOutPointerNextGet() +//! +//! Functions to handle interruptions: +//! - \ref I2SIntEnable() +//! - \ref I2SIntDisable() +//! - \ref I2SIntStatus() +//! - \ref I2SIntClear() +//! +//! Functions to handle sample stamps +//! - \ref I2SSampleStampEnable() +//! - \ref I2SSampleStampDisable() +//! - \ref I2SSampleStampInConfigure() +//! - \ref I2SSampleStampOutConfigure() +//! - \ref I2SSampleStampGet() +//! - \ref I2SWclkCounterConfigure() +//! - \ref I2SWclkCounterReset() +//! +//! Old API: +//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), +//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), +//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), +//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), +//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), +//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), +//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), +//! \ref I2SIntUnregister() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.c new file mode 100644 index 00000000..878f568e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.c @@ -0,0 +1,467 @@ +/****************************************************************************** +* Filename: interrupt.c +* +* Description: Driver for the NVIC Interrupt Controller. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "interrupt.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IntRegister + #define IntRegister NOROM_IntRegister + #undef IntUnregister + #define IntUnregister NOROM_IntUnregister + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #undef IntPrioritySet + #define IntPrioritySet NOROM_IntPrioritySet + #undef IntPriorityGet + #define IntPriorityGet NOROM_IntPriorityGet + #undef IntEnable + #define IntEnable NOROM_IntEnable + #undef IntDisable + #define IntDisable NOROM_IntDisable + #undef IntPendSet + #define IntPendSet NOROM_IntPendSet + #undef IntPendGet + #define IntPendGet NOROM_IntPendGet + #undef IntPendClear + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +//***************************************************************************** +// +//! \brief The default interrupt handler. +//! +//! This is the default interrupt handler for all interrupts. It simply loops +//! forever so that the system state is preserved for observation by a +//! debugger. Since interrupts should be disabled before unregistering the +//! corresponding handler, this should never be called. +//! +//! \return None +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // Go into an infinite loop. + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. +//! +//! Interrupt vector table is placed at ".ramVecs" defined in the linker file +//! provided by Texas Instruments. +//! +//! \note See \ti_code{interrupt.c} for compiler specific implementation! +// +//***************************************************************************** +#if defined(DOXYGEN) +// Dummy void pointer used as placeholder to generate Doxygen documentation. +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=256 +static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".ramVecs"; +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(g_pfnRAMVectors, 256) +#pragma DATA_SECTION(g_pfnRAMVectors, ".ramVecs") +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#elif defined (__CC_ARM) +static __attribute__((section(".ramVecs"), aligned(256))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#else +static __attribute__((section(".ramVecs"), aligned(256))) +void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); +#endif + +//***************************************************************************** +// +// Registers a function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) +{ + uint32_t ui32Idx, ui32Value; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Make sure that the RAM vector table is correctly aligned. + ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0); + + // See if the RAM vector table has been initialized. + if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) + { + // Copy the vector table from the beginning of FLASH to the RAM vector + // table. + ui32Value = HWREG(NVIC_VTABLE); + for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) + { + g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + + ui32Value); + } + + // Point NVIC at the RAM vector table. + HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; + } + + // Save the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = pfnHandler; +} + +//***************************************************************************** +// +// Unregisters the function to be called when an interrupt occurs. +// +//***************************************************************************** +void +IntUnregister(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Reset the interrupt handler. + g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler; +} + +//***************************************************************************** +// +// Sets the priority grouping of the interrupt controller. +// +//***************************************************************************** +void +IntPriorityGroupingSet(uint32_t ui32Bits) +{ + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +//***************************************************************************** +// +// Gets the priority grouping of the interrupt controller +// +//***************************************************************************** +uint32_t +IntPriorityGroupingGet(void) +{ + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +//***************************************************************************** +// +// Sets the priority of an interrupt +// +//***************************************************************************** +void +IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +//***************************************************************************** +// +// Gets the priority of an interrupt +// +//***************************************************************************** +int32_t +IntPriorityGet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +//***************************************************************************** +// +// Enables an interrupt +// +//***************************************************************************** +void +IntEnable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Disables an interrupt +// +//***************************************************************************** +void +IntDisable(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Pends an interrupt +// +//***************************************************************************** +void +IntPendSet(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +//***************************************************************************** +// +// Query whether an interrupt is pending +// +//***************************************************************************** +bool +IntPendGet(uint32_t ui32Interrupt) +{ + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +//***************************************************************************** +// +// Unpends an interrupt +// +//***************************************************************************** +void +IntPendClear(uint32_t ui32Interrupt) +{ + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.h new file mode 100644 index 00000000..c2078988 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt.h @@ -0,0 +1,716 @@ +/****************************************************************************** +* Filename: interrupt.h +* +* Description: Defines and prototypes for the NVIC Interrupt Controller +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup interrupt_api +//! @{ +// +//***************************************************************************** + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_nvic.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IntRegister NOROM_IntRegister + #define IntUnregister NOROM_IntUnregister + #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet + #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet + #define IntPrioritySet NOROM_IntPrioritySet + #define IntPriorityGet NOROM_IntPriorityGet + #define IntEnable NOROM_IntEnable + #define IntDisable NOROM_IntDisable + #define IntPendSet NOROM_IntPendSet + #define IntPendGet NOROM_IntPendGet + #define IntPendClear NOROM_IntPendClear +#endif + +//***************************************************************************** +// +// Macro to generate an interrupt priority mask based on the number of bits +// of priority supported by the hardware. For CC26xx the number of priority +// bit is 3 as defined in hw_types.h. The priority mask is +// defined as +// +// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) +// +//***************************************************************************** +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Registers a function as an interrupt handler in the dynamic vector table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function writes a function pointer to the dynamic interrupt vector table +//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding +//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function +//! pointer is fetched from the dynamic vector table, and the System CPU will +//! execute the interrupt handler. +//! +//! \note The first call to this function (directly or indirectly via a peripheral +//! driver interrupt register function) copies the interrupt vector table from +//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function +//! is called. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - System exceptions (vectors 0 to 15): +//! - INT_NMI_FAULT +//! - INT_HARD_FAULT +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts (vectors >15): +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_BATMON_COMB +//! - INT_PKA_IRQ +//! - INT_SSI1_COMB +//! - INT_UART1_COMB +//! - INT_AUX_TIMER2_EV0 +//! \param pfnHandler is a pointer to the function to register as interrupt handler. +//! +//! \return None. +//! +//! \sa \ref IntUnregister(), \ref IntEnable() +// +//***************************************************************************** +extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler in the dynamic vector table. +//! +//! This function removes an interrupt handler from the dynamic vector table and +//! replaces it with the default interrupt handler \ref IntDefaultHandler(). +//! +//! \note Remember to disable the interrupt before removing its interrupt handler +//! from the vector table. +//! +//! \param ui32Interrupt specifies the index in the vector table to modify. +//! - See \ref IntRegister() for list of valid arguments. +//! +//! \return None. +//! +//! \sa \ref IntRegister(), \ref IntDisable() +// +//***************************************************************************** +extern void IntUnregister(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Sets the priority grouping of the interrupt controller. +//! +//! This function specifies the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! Three bits are available for hardware interrupt prioritization thus priority +//! grouping values of three through seven have the same effect. +//! +//! \param ui32Bits specifies the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +//! +//! \return None +//! +//! \sa \ref IntPrioritySet() +// +//***************************************************************************** +extern void IntPriorityGroupingSet(uint32_t ui32Bits); + +//***************************************************************************** +// +//! \brief Gets the priority grouping of the interrupt controller. +//! +//! This function returns the split between preemptable priority levels and +//! subpriority levels in the interrupt priority specification. +//! +//! \return Returns the number of bits of preemptable priority. +//! - 0 : No pre-emption priority, eight bits of subpriority. +//! - 1 : One bit of pre-emption priority, seven bits of subpriority +//! - 2 : Two bits of pre-emption priority, six bits of subpriority +//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority +// +//***************************************************************************** +extern uint32_t IntPriorityGroupingGet(void); + +//***************************************************************************** +// +//! \brief Sets the priority of an interrupt. +//! +//! This function sets the priority of an interrupt, including system exceptions. +//! When multiple interrupts are asserted simultaneously, the ones with the highest +//! priority are processed before the lower priority interrupts. Smaller numbers +//! correspond to higher interrupt priorities thus priority 0 is the highest +//! interrupt priority. +//! +//! \warning This function does not support setting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to change priority for. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SVCALL +//! - INT_DEBUG +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_BATMON_COMB +//! - INT_PKA_IRQ +//! - INT_SSI1_COMB +//! - INT_UART1_COMB +//! - INT_AUX_TIMER2_EV0 +//! \param ui8Priority specifies the priority of the interrupt. +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +//! +//! \return None +//! +//! \sa \ref IntPriorityGroupingSet() +// +//***************************************************************************** +extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority); + +//***************************************************************************** +// +//! \brief Gets the priority of an interrupt. +//! +//! This function gets the priority of an interrupt. +//! +//! \warning This function does not support getting priority of interrupt vectors +//! one through three which are: +//! - 1: Reset handler +//! - 2: NMI handler +//! - 3: Hard fault handler +//! +//! \param ui32Interrupt specifies the index in the vector table to read priority of. +//! - See \ref IntPrioritySet() for list of valid arguments. +//! +//! \return Returns the interrupt priority: +//! - \ref INT_PRI_LEVEL0 : Highest priority. +//! - \ref INT_PRI_LEVEL1 +//! - \ref INT_PRI_LEVEL2 +//! - \ref INT_PRI_LEVEL3 +//! - \ref INT_PRI_LEVEL4 +//! - \ref INT_PRI_LEVEL5 +//! - \ref INT_PRI_LEVEL6 +//! - \ref INT_PRI_LEVEL7 : Lowest priority. +// +//***************************************************************************** +extern int32_t IntPriorityGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables an interrupt or system exception. +//! +//! This function enables the specified interrupt in the interrupt controller. +//! +//! \note If a fault condition occurs while the corresponding system exception +//! is disabled, the fault is treated as a Hard Fault. +//! +//! \param ui32Interrupt specifies the index in the vector table to enable. +//! - System exceptions: +//! - INT_MEMMANAGE_FAULT +//! - INT_BUS_FAULT +//! - INT_USAGE_FAULT +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_BATMON_COMB +//! - INT_PKA_IRQ +//! - INT_SSI1_COMB +//! - INT_UART1_COMB +//! - INT_AUX_TIMER2_EV0 +//! +//! \return None +//! +//! \sa \ref IntDisable() +// +//***************************************************************************** +extern void IntEnable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Disables an interrupt or system exception. +//! +//! This function disables the specified interrupt in the interrupt controller. +//! +//! \param ui32Interrupt specifies the index in the vector table to disable. +//! - See \ref IntEnable() for list of valid arguments. +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntDisable(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Pends an interrupt. +//! +//! This function pends the specified interrupt in the interrupt controller. +//! This causes the interrupt controller to execute the corresponding interrupt +//! handler at the next available time, based on the current interrupt state +//! priorities. +//! +//! This interrupt controller automatically clears the pending interrupt once the +//! interrupt handler is executed. +//! +//! \param ui32Interrupt specifies the index in the vector table to pend. +//! - System exceptions: +//! - INT_NMI_FAULT +//! - INT_PENDSV +//! - INT_SYSTICK +//! - Interrupts: +//! - INT_AON_GPIO_EDGE +//! - INT_I2C_IRQ +//! - INT_RFC_CPE_1 +//! - INT_AON_RTC_COMB +//! - INT_UART0_COMB +//! - INT_AUX_SWEV0 +//! - INT_SSI0_COMB +//! - INT_RFC_CPE_0 +//! - INT_RFC_HW_COMB +//! - INT_RFC_CMD_ACK +//! - INT_I2S_IRQ +//! - INT_AUX_SWEV1 +//! - INT_WDT_IRQ +//! - INT_GPT0A +//! - INT_GPT0B +//! - INT_GPT1A +//! - INT_GPT1B +//! - INT_GPT2A +//! - INT_GPT2B +//! - INT_GPT3A +//! - INT_GPT3B +//! - INT_CRYPTO_RESULT_AVAIL_IRQ +//! - INT_DMA_DONE_COMB +//! - INT_DMA_ERR +//! - INT_FLASH +//! - INT_SWEV0 +//! - INT_AUX_COMB +//! - INT_AON_PROG0 +//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) +//! - INT_AUX_COMPA +//! - INT_AUX_ADC_IRQ +//! - INT_TRNG_IRQ +//! - INT_OSC_COMB +//! - INT_BATMON_COMB +//! - INT_PKA_IRQ +//! - INT_SSI1_COMB +//! - INT_UART1_COMB +//! - INT_AUX_TIMER2_EV0 +//! +//! \return None +//! +//! \sa \ref IntEnable() +// +//***************************************************************************** +extern void IntPendSet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Checks if an interrupt is pending. +//! +//! This function checks the interrupt controller to see if an interrupt is pending. +//! +//! The interrupt must be enabled in order for the corresponding interrupt handler +//! to be executed, so an interrupt can be pending waiting to be enabled or waiting +//! for an interrupt of higher priority to be done executing. +//! +//! \note This function does not support reading pending status for system exceptions +//! (vector table indexes <16). +//! +//! \param ui32Interrupt specifies the index in the vector table to check pending +//! status for. +//! - See \ref IntPendSet() for list of valid arguments (except system exceptions). +//! +//! \return Returns: +//! - \c true : Specified interrupt is pending. +//! - \c false : Specified interrupt is not pending. +// +//***************************************************************************** +extern bool IntPendGet(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Unpends an interrupt. +//! +//! This function unpends the specified interrupt in the interrupt controller. +//! This causes any previously generated interrupts that have not been handled yet +//! (due to higher priority interrupts or the interrupt no having been enabled +//! yet) to be discarded. +//! +//! \note It is not possible to unpend the NMI because it takes effect +//! immediately when being pended. +//! +//! \param ui32Interrupt specifies the index in the vector table to unpend. +//! - See \ref IntPendSet() for list of valid arguments (except NMI). +//! +//! \return None +// +//***************************************************************************** +extern void IntPendClear(uint32_t ui32Interrupt); + +//***************************************************************************** +// +//! \brief Enables the CPU interrupt. +//! +//! Allows the CPU to respond to interrupts. +//! +//! \return Returns: +//! - \c true : Interrupts were disabled and are now enabled. +//! - \c false : Interrupts were already enabled when the function was called. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterEnable(void) +{ + // Enable CPU interrupts. + return(CPUcpsie()); +} + +//***************************************************************************** +// +//! \brief Disables the CPU interrupts with configurable priority. +//! +//! Prevents the CPU from receiving interrupts except NMI and hard fault. This +//! does not affect the set of interrupts enabled in the interrupt controller; +//! it just gates the interrupt from the interrupt controller to the CPU. +//! +//! \return Returns: +//! - \c true : Interrupts were already disabled when the function was called. +//! - \c false : Interrupts were enabled and are now disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +IntMasterDisable(void) +{ + // Disable CPU interrupts. + return(CPUcpsid()); +} + +//***************************************************************************** +// +//! \brief Sets the priority masking level. +//! +//! This function sets the interrupt priority masking level so that all +//! interrupts at the specified or lesser priority level are masked. This +//! can be used to globally disable a set of interrupts with priority below +//! a predetermined threshold. A value of 0 disables priority +//! masking. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! The device supports priority levels 0 through 7. +//! +//! \param ui32PriorityMask is the priority level that will be masked. +//! - 0 : Disable priority masking. +//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. +//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. +//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. +//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. +//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. +//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. +//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +IntPriorityMaskSet(uint32_t ui32PriorityMask) +{ + CPUbasepriSet(ui32PriorityMask); +} + +//***************************************************************************** +// +//! \brief Gets the priority masking level. +//! +//! This function gets the current setting of the interrupt priority masking +//! level. The value returned is the priority level such that all interrupts +//! of that and lesser priority are masked. A value of 0 means that priority +//! masking is disabled. +//! +//! Smaller numbers correspond to higher interrupt priorities. So for example +//! a priority level mask of 4 will allow interrupts of priority level 0-3, +//! and interrupts with a numerical priority of 4 and greater will be blocked. +//! +//! \return Returns the value of the interrupt priority level mask. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IntPriorityMaskGet(void) +{ + return(CPUbasepriGet()); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IntRegister + #undef IntRegister + #define IntRegister ROM_IntRegister + #endif + #ifdef ROM_IntUnregister + #undef IntUnregister + #define IntUnregister ROM_IntUnregister + #endif + #ifdef ROM_IntPriorityGroupingSet + #undef IntPriorityGroupingSet + #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet + #endif + #ifdef ROM_IntPriorityGroupingGet + #undef IntPriorityGroupingGet + #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet + #endif + #ifdef ROM_IntPrioritySet + #undef IntPrioritySet + #define IntPrioritySet ROM_IntPrioritySet + #endif + #ifdef ROM_IntPriorityGet + #undef IntPriorityGet + #define IntPriorityGet ROM_IntPriorityGet + #endif + #ifdef ROM_IntEnable + #undef IntEnable + #define IntEnable ROM_IntEnable + #endif + #ifdef ROM_IntDisable + #undef IntDisable + #define IntDisable ROM_IntDisable + #endif + #ifdef ROM_IntPendSet + #undef IntPendSet + #define IntPendSet ROM_IntPendSet + #endif + #ifdef ROM_IntPendGet + #undef IntPendGet + #define IntPendGet ROM_IntPendGet + #endif + #ifdef ROM_IntPendClear + #undef IntPendClear + #define IntPendClear ROM_IntPendClear + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __INTERRUPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt_doc.h new file mode 100644 index 00000000..fc02063f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/interrupt_doc.h @@ -0,0 +1,159 @@ +/****************************************************************************** +* Filename: interrupt_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup interrupt_api +//! @{ +//! \section sec_interrupt Introduction +//! +//! The interrupt controller API provides a set of functions for dealing with the +//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable +//! and disable interrupts, register interrupt handlers, and set the priority of +//! interrupts. +//! +//! The event sources that trigger the interrupt lines in the NVIC are controlled by +//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines +//! except one which is programmable. For more information about the MCU event fabric, see the +//! [MCU event fabric API](\ref event_api). +//! +//! \section sec_interrupt_api API +//! +//! Interrupts and system exceptions must be individually enabled and disabled through: +//! - \ref IntEnable() +//! - \ref IntDisable() +//! +//! The global CPU interrupt can be enabled and disabled with the following functions: +//! - \ref IntMasterEnable() +//! - \ref IntMasterDisable() +//! +//! This does not affect the individual interrupt enable states. Masking of the CPU +//! interrupt can be used as a simple critical section (only an NMI can interrupt the +//! CPU while the CPU interrupt is disabled), although masking the CPU +//! interrupt can increase the interrupt response time. +//! +//! It is possible to access the NVIC to see if any interrupts are pending and manually +//! clear pending interrupts which have not yet been serviced or set a specific interrupt as +//! pending to be handled based on its priority. Pending interrupts are cleared automatically +//! when the interrupt is accepted and executed. However, the event source which caused the +//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. +//! The functions to read, clear, and set pending interrupts are: +//! - \ref IntPendGet() +//! - \ref IntPendClear() +//! - \ref IntPendSet() +//! +//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts +//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt +//! handlers by higher priority interrupts. +//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority. +//! The priority of each interrupt source can be set and examined using: +//! - \ref IntPrioritySet() +//! - \ref IntPriorityGet() +//! +//! Interrupts can be masked based on their priority such that interrupts with the same or lower +//! priority than the mask are effectively disabled. This can be configured with: +//! - \ref IntPriorityMaskSet() +//! - \ref IntPriorityMaskGet() +//! +//! Subprioritization is also possible. Instead of having three bits of preemptable +//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of +//! preemptable prioritization and M bits of subpriority. In this scheme, two +//! interrupts with the same preemptable prioritization but different subpriorities +//! do not cause a preemption. Instead, tail chaining is used to process +//! the two interrupts back-to-back. +//! If two interrupts with the same priority (and subpriority if so configured) are +//! asserted at the same time, the one with the lower interrupt number is +//! processed first. +//! Subprioritization is handled by: +//! - \ref IntPriorityGroupingSet() +//! - \ref IntPriorityGroupingGet() +//! +//! \section sec_interrupt_table Interrupt Vector Table +//! +//! The interrupt vector table can be configured in one of two ways: +//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed +//! pointer to an interrupt handler (ISR). +//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed +//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different +//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the +//! System CPU responds to the interrupt. +//! +//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable() +//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required +//! within the peripheral). +//! +//! \subsection sec_interrupt_table_static Static Vector Table +//! +//! Static registration of interrupt handlers is accomplished by editing the interrupt handler +//! table in the startup code of the application. Texas Instruments provides startup files for +//! each supported compiler ( \ti_code{startup_.c} ) and these startup files include +//! a default static interrupt vector table. +//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default +//! interrupt handler. This allows the user to declare and define a function (in the user's code) +//! with the same name as an entry in the vector table. At compile time, the linker then replaces +//! the pointer to the default interrupt handler in the vector table with the pointer to the +//! interrupt handler defined by the user. +//! +//! Statically configuring the interrupt table provides the fastest interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel +//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well +//! as the prefetch of the interrupt handler (assuming it is also in Flash). +//! +//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table +//! +//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. +//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to +//! interrupt handlers throughout the application. +//! +//! DriverLib uses these two functions to modify the dynamic vector table: +//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table. +//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table. +//! +//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the +//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from +//! this point forward. If using the dynamic vector table it is highly recommended to +//! initialize it during the setup phase of the application. The NVIC uses the static vector +//! table in Flash until the application initializes the dynamic vector table in SRAM. +//! +//! Runtime configuration of interrupts adds a small latency to the interrupt response time +//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler +//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed +//! sequentially. +//! +//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called +//! \c .ramVecs which is a section defined in the linker file. +//! +//! \warning Runtime configuration of interrupt handlers requires that the interrupt +//! handler table is placed on a 256-byte boundary in SRAM (typically, this is +//! at the beginning of SRAM). Failure to do so results in an incorrect vector +//! address being fetched in response to an interrupt. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.c new file mode 100644 index 00000000..6a2337bd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.c @@ -0,0 +1,680 @@ +/****************************************************************************** +* Filename: ioc.c +* +* Description: Driver for the IOC. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ioc.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef IOCPortConfigureSet + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #undef IOCIOModeSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #undef IOCIOIntSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #undef IOCIOEvtSet + #define IOCIOEvtSet NOROM_IOCIOEvtSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #undef IOCIOHystSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #undef IOCIOInputSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #undef IOCIntEnable + #define IOCIntEnable NOROM_IOCIntEnable + #undef IOCIntDisable + #define IOCIntDisable NOROM_IOCIntDisable + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #undef IOCPinTypeUart + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #undef IOCPinTypeI2c + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #undef IOCPinTypeAux + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Set the configuration of an IO port +// +//***************************************************************************** +void +IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +//***************************************************************************** +// +// Get the configuration of an IO port +// +//***************************************************************************** +uint32_t +IOCPortConfigureGet(uint32_t ui32IOId) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +//***************************************************************************** +// +// Set wake-up on an IO port +// +//***************************************************************************** +void +IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + + +//***************************************************************************** +// +// Set the IO Mode of an IO Port +// +//***************************************************************************** +void +IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) +{ + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +//***************************************************************************** +// +// Setup interrupt detection on an IO Port +// +//***************************************************************************** +void +IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +//***************************************************************************** +// +// Setup event generation on IO edge detection +// +//***************************************************************************** +void +IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT( (ui32Evt & ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | + IOC_IOCFG0_IOEV_AON_PROG1_EN_M | + IOC_IOCFG0_IOEV_AON_PROG0_EN_M | + IOC_IOCFG0_IOEV_RTC_EN_M | + IOC_IOCFG0_IOEV_MCU_WU_EN_M) ) == 0x00000000); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Read current configuration. + ui32Config = HWREG(ui32IOReg); + + // Disable generation of all events. + ui32Config &= ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | + IOC_IOCFG0_IOEV_AON_PROG1_EN_M | + IOC_IOCFG0_IOEV_AON_PROG0_EN_M | + IOC_IOCFG0_IOEV_RTC_EN_M | + IOC_IOCFG0_IOEV_MCU_WU_EN_M); + + // Enable the required events. + HWREG(ui32IOReg) = ui32Config | ui32Evt; +} + +//***************************************************************************** +// +// Set the pull on an IO port +// +//***************************************************************************** +void +IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +//***************************************************************************** +// +// Configure hysteresis on and IO port +// +//***************************************************************************** +void +IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +//***************************************************************************** +// +// Enable/disable IO port as input +// +//***************************************************************************** +void +IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +//***************************************************************************** +// +// Enable/disable the slew control on an IO port +// +//***************************************************************************** +void +IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +//***************************************************************************** +// +// Configure the drive strength and maximum current of an IO port +// +//***************************************************************************** +void +IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +//***************************************************************************** +// +// Setup the Port ID for this IO +// +//***************************************************************************** +void +IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +//***************************************************************************** +// +// Enables individual IO edge detect interrupt +// +//***************************************************************************** +void +IOCIntEnable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Disables individual IO edge interrupt sources +// +//***************************************************************************** +void +IOCIntDisable(uint32_t ui32IOId) +{ + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO input +// +//***************************************************************************** +void +IOCPinTypeGpioInput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +//***************************************************************************** +// +// Setup an IO for standard GPIO output +// +//***************************************************************************** +void +IOCPinTypeGpioOutput(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +//***************************************************************************** +// +// Configure a set of IOs for standard UART peripheral control +// +//***************************************************************************** +void +IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, + uint32_t ui32Cts, uint32_t ui32Rts) +{ + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx < NUM_IO_MAX) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx < NUM_IO_MAX) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts < NUM_IO_MAX) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts < NUM_IO_MAX) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral master control +// +//***************************************************************************** +void +IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx < NUM_IO_MAX) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx < NUM_IO_MAX) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss < NUM_IO_MAX) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk < NUM_IO_MAX) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard SSI peripheral slave control +// +//***************************************************************************** +void +IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk) +{ + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx < NUM_IO_MAX) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx < NUM_IO_MAX) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss < NUM_IO_MAX) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk < NUM_IO_MAX) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +//***************************************************************************** +// +// Configure a set of IOs for standard I2C peripheral control +// +//***************************************************************************** +void +IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) +{ + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data < NUM_IO_MAX) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk < NUM_IO_MAX) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + +//***************************************************************************** +// +// Configure an IO for AUX control +// +//***************************************************************************** +void +IOCPinTypeAux(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT((ui32IOId < NUM_IO_MAX) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.h new file mode 100644 index 00000000..9d3d9876 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc.h @@ -0,0 +1,1221 @@ +/****************************************************************************** +* Filename: ioc.h +* +* Description: Defines and prototypes for the IO Controller. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ioc_api +//! @{ +// +//***************************************************************************** + +#ifndef __IOC_H__ +#define __IOC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" +#include "gpio.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define IOCPortConfigureSet NOROM_IOCPortConfigureSet + #define IOCPortConfigureGet NOROM_IOCPortConfigureGet + #define IOCIOShutdownSet NOROM_IOCIOShutdownSet + #define IOCIOModeSet NOROM_IOCIOModeSet + #define IOCIOIntSet NOROM_IOCIOIntSet + #define IOCIOEvtSet NOROM_IOCIOEvtSet + #define IOCIOPortPullSet NOROM_IOCIOPortPullSet + #define IOCIOHystSet NOROM_IOCIOHystSet + #define IOCIOInputSet NOROM_IOCIOInputSet + #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet + #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet + #define IOCIOPortIdSet NOROM_IOCIOPortIdSet + #define IOCIntEnable NOROM_IOCIntEnable + #define IOCIntDisable NOROM_IOCIntDisable + #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput + #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput + #define IOCPinTypeUart NOROM_IOCPinTypeUart + #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster + #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave + #define IOCPinTypeI2c NOROM_IOCPinTypeI2c + #define IOCPinTypeAux NOROM_IOCPinTypeAux +#endif + +//***************************************************************************** +// +// Number of IOs (max. total of 32 for 26x2, 48 for 26x4) +// +//***************************************************************************** +#define NUM_IO_MAX 32 + +//***************************************************************************** +// +// The following fields are IO Id for the IOC module +// +//***************************************************************************** +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id + +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask + +//***************************************************************************** +// +// Number of IO ports +// +//***************************************************************************** +#define NUM_IO_PORTS 56 + +//***************************************************************************** +// +// IOC Peripheral Port Mapping +// +//***************************************************************************** +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin +#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin +#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin +#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In + +//***************************************************************************** +// +// Defines for enabling/disabling an IO +// +//***************************************************************************** +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 + +//***************************************************************************** +// +// Defines that can be used to set the shutdown mode of an IO +// +//***************************************************************************** +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 + +//***************************************************************************** +// +// Defines that can be used to set the IO Mode of an IO +// +//***************************************************************************** +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_OPEN_DRAIN_NORMAL \ + 0x04000000 // Open Drain, Normal Input/Output +#define IOC_IOMODE_OPEN_DRAIN_INV \ + 0x05000000 // Open Drain, Inverted + // Input/Output +#define IOC_IOMODE_OPEN_SRC_NORMAL \ + 0x06000000 // Open Source, Normal Input/Output +#define IOC_IOMODE_OPEN_SRC_INV \ + 0x07000000 // Open Source, Inverted + // Input/Output + +//***************************************************************************** +// +// Defines that can be used to set the edge detection on an IO +// +//***************************************************************************** +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask + +//***************************************************************************** +// +// Defines that be used to set pull on an IO +// +//***************************************************************************** +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask + +//***************************************************************************** +// +// Defines that can be used to select the drive strength of an IO +// +//***************************************************************************** +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength + +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength + // (2/4/8 mA @ VVDS) +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength + // (2/4/8 mA @ 1.8V) +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength + // (2/4/8 mA @ 2.5V) +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength + // (2/4/8 mA @ 3.3V) + +//***************************************************************************** +// +// Defines that can be used to enable event generation on edge detect +// +//***************************************************************************** +#define IOC_EVT_AON_PROG2_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG2_ENABLE 0x00800000 +#define IOC_EVT_AON_PROG1_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG1_ENABLE 0x00400000 +#define IOC_EVT_AON_PROG0_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG0_ENABLE 0x00200000 +#define IOC_EVT_RTC_DISABLE 0x00000000 +#define IOC_EVT_RTC_ENABLE 0x00000080 +#define IOC_EVT_MCU_WU_DISABLE 0x00000000 +#define IOC_EVT_MCU_WU_ENABLE 0x00000040 + +//***************************************************************************** +// +// Defines for standard IO setup +// +//***************************************************************************** +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set the configuration of an IO port. +//! +//! This function is used to configure the functionality of an IO. +//! +//! The \c ui32IOId parameter specifies which IO to configure. +//! +//! The \c ui32PortId parameter specifies which functional peripheral to hook +//! up to this IO. +//! +//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all +//! the available configuration modes +//! +//! \note All IO Ports are tied to a specific functionality in a sub module +//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are +//! hardcoded to a specific IO. When enabling one or more pins for the AUX +//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO. +//! +//! \param ui32IOId defines the IO to configure and must be one of the following: +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the functional IO port to connect. +//! The available IO ports are: +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_UART1_RX +//! - \ref IOC_PORT_MCU_UART1_TX +//! - \ref IOC_PORT_MCU_UART1_CTS +//! - \ref IOC_PORT_MCU_UART1_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! \param ui32IOConfig is the IO configuration consisting of +//! the bitwise OR of all configuration modes: +//! - Input/output mode: +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! - Wake-up mode (from shutdown): +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! - Edge detection mode: +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! - Interrupt mode on edge detection: +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! - Pull mode: +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! - Input mode: +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! - Hysteresis mode: +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! - Slew rate reduction mode: +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! - Current mode (see \ref IOCIODrvStrengthSet() for more details): +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - Drive strength mode: +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - Assert AON_PROG2 event on edge detection: +//! - \ref IOC_EVT_AON_PROG2_DISABLE +//! - \ref IOC_EVT_AON_PROG2_ENABLE +//! - Assert AON_PROG1 event on edge detection: +//! - \ref IOC_EVT_AON_PROG1_DISABLE +//! - \ref IOC_EVT_AON_PROG1_ENABLE +//! - Assert AON_PROG0 event on edge detection: +//! - \ref IOC_EVT_AON_PROG0_DISABLE +//! - \ref IOC_EVT_AON_PROG0_ENABLE +//! - Assert RTC event on edge detection: +//! - \ref IOC_EVT_RTC_DISABLE +//! - \ref IOC_EVT_RTC_ENABLE +//! - Assert MCU_WU event on edge detection: +//! - \ref IOC_EVT_MCU_WU_DISABLE +//! - \ref IOC_EVT_MCU_WU_ENABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, + uint32_t ui32IOConfig); + +//***************************************************************************** +// +//! \brief Get the configuration of an IO port. +//! +//! This function is used for getting the configuration of an IO. +//! +//! Each IO port has a dedicated register for setting up the IO. This function +//! returns the current configuration for the given IO. +//! +//! \param ui32IOId selects the IO to return the configuration for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return Returns the IO Port configuration. +//! See \ref IOCPortConfigureSet() for configuration options. +// +//***************************************************************************** +extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Set wake-up mode from shutdown on an IO port. +//! +//! This function is used to set the wake-up mode from shutdown of an IO. +//! +//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet(). +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port. +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_WAKE_ON_LOW +//! - \ref IOC_WAKE_ON_HIGH +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); + + +//***************************************************************************** +// +//! \brief Set the IO Mode of an IO Port. +//! +//! This function is used to set the input/output mode of an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOMode sets the port IO Mode. +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_IOMODE_INV +//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL +//! - \ref IOC_IOMODE_OPEN_DRAIN_INV +//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL +//! - \ref IOC_IOMODE_OPEN_SRC_INV +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode); + +//***************************************************************************** +// +//! \brief Setup edge detection and interrupt generation on an IO Port. +//! +//! This function is used to setup the edge detection and interrupt generation on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Int enables/disables interrupt generation on this IO port. +//! - \ref IOC_INT_ENABLE +//! - \ref IOC_INT_DISABLE +//! \param ui32EdgeDet enables/disables edge detection events on this IO port. +//! - \ref IOC_NO_EDGE +//! - \ref IOC_FALLING_EDGE +//! - \ref IOC_RISING_EDGE +//! - \ref IOC_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, + uint32_t ui32EdgeDet); + +//***************************************************************************** +// +//! \brief Setup event generation on IO edge detection. +//! +//! This function is used to setup event generation for specific events +//! when an IO edge detection occurs. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Evt is a bitwise OR of the IO events to generate when an IO edge detection occurs. +//! All other IO event generations are disabled. +//! - \ref IOC_EVT_AON_PROG2_ENABLE : AON_PROG2 event. +//! - \ref IOC_EVT_AON_PROG1_ENABLE : AON_PROG1 event. +//! - \ref IOC_EVT_AON_PROG0_ENABLE : AON_PROG0 event. +//! - \ref IOC_EVT_RTC_ENABLE : RTC event. +//! - \ref IOC_EVT_MCU_WU_ENABLE : MCU_WU event. +//! +// +//***************************************************************************** +extern void IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt); + +//***************************************************************************** +// +//! \brief Set the pull on an IO port. +//! +//! This function is used to configure the pull on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Pull enables/disables pull on this IO port. +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_IOPULL_UP +//! - \ref IOC_IOPULL_DOWN +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull); + +//***************************************************************************** +// +//! \brief Configure hysteresis on and IO port. +//! +//! This function is used to enable/disable hysteresis on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Hysteresis enable/disable input hysteresis on IO. +//! - \ref IOC_HYST_ENABLE +//! - \ref IOC_HYST_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis); + +//***************************************************************************** +// +//! \brief Enable/disable IO port as input. +//! +//! This function is used to enable/disable input on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32Input enable/disable input on IO. +//! - \ref IOC_INPUT_ENABLE +//! - \ref IOC_INPUT_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input); + +//***************************************************************************** +// +//! \brief Configure slew rate on an IO port. +//! +//! This function is used to enable/disable reduced slew rate on an IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32SlewEnable enables/disables reduced slew rate on an output. +//! - \ref IOC_SLEW_ENABLE +//! - \ref IOC_SLEW_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable); + +//***************************************************************************** +// +//! \brief Configure the drive strength source and current mode of an IO port. +//! +//! The drive strength of an IO is configured by a combination of multiple settings +//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling +//! drive strength at different supply levels. When set to AUTO the battery monitor +//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage +//! in order to keep IO current constant. Alternatively, drive strength source can +//! be controlled manually by selecting one of three options each of which is configurable +//! in the AON IOC by \ref AONIOCDriveStrengthSet(). +//! +//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and +//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode. +//! I.e. EC = 2 x HC = 4 x LC. +//! +//! \note Not all IOs support Extended-Current mode. See datasheet for more information +//! on the specific device. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32IOCurrent selects the IO current mode. +//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. +//! \param ui32DrvStrength sets the source for drive strength control of the IO port. +//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. +//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). +//! +//! \return None +// +//***************************************************************************** +extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, + uint32_t ui32DrvStrength); + +//***************************************************************************** +// +//! \brief Setup the Port ID for this IO. +//! +//! The \c ui32PortId specifies which functional peripheral to hook up to this +//! IO. +//! +//! \param ui32IOId defines the IO to configure. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! \param ui32PortId selects the port to map to the IO. +//! - \ref IOC_PORT_GPIO +//! - \ref IOC_PORT_AON_CLK32K +//! - \ref IOC_PORT_AUX_IO +//! - \ref IOC_PORT_MCU_SSI0_RX +//! - \ref IOC_PORT_MCU_SSI0_TX +//! - \ref IOC_PORT_MCU_SSI0_FSS +//! - \ref IOC_PORT_MCU_SSI0_CLK +//! - \ref IOC_PORT_MCU_I2C_MSSDA +//! - \ref IOC_PORT_MCU_I2C_MSSCL +//! - \ref IOC_PORT_MCU_UART0_RX +//! - \ref IOC_PORT_MCU_UART0_TX +//! - \ref IOC_PORT_MCU_UART0_CTS +//! - \ref IOC_PORT_MCU_UART0_RTS +//! - \ref IOC_PORT_MCU_UART1_RX +//! - \ref IOC_PORT_MCU_UART1_TX +//! - \ref IOC_PORT_MCU_UART1_CTS +//! - \ref IOC_PORT_MCU_UART1_RTS +//! - \ref IOC_PORT_MCU_PORT_EVENT0 +//! - \ref IOC_PORT_MCU_PORT_EVENT1 +//! - \ref IOC_PORT_MCU_PORT_EVENT2 +//! - \ref IOC_PORT_MCU_PORT_EVENT3 +//! - \ref IOC_PORT_MCU_PORT_EVENT4 +//! - \ref IOC_PORT_MCU_PORT_EVENT5 +//! - \ref IOC_PORT_MCU_PORT_EVENT6 +//! - \ref IOC_PORT_MCU_PORT_EVENT7 +//! - \ref IOC_PORT_MCU_SWV +//! - \ref IOC_PORT_MCU_SSI1_RX +//! - \ref IOC_PORT_MCU_SSI1_TX +//! - \ref IOC_PORT_MCU_SSI1_FSS +//! - \ref IOC_PORT_MCU_SSI1_CLK +//! - \ref IOC_PORT_MCU_I2S_AD0 +//! - \ref IOC_PORT_MCU_I2S_AD1 +//! - \ref IOC_PORT_MCU_I2S_WCLK +//! - \ref IOC_PORT_MCU_I2S_BCLK +//! - \ref IOC_PORT_MCU_I2S_MCLK +//! - \ref IOC_PORT_RFC_TRC +//! - \ref IOC_PORT_RFC_GPO0 +//! - \ref IOC_PORT_RFC_GPO1 +//! - \ref IOC_PORT_RFC_GPO2 +//! - \ref IOC_PORT_RFC_GPO3 +//! - \ref IOC_PORT_RFC_GPI0 +//! - \ref IOC_PORT_RFC_GPI1 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId); + +//***************************************************************************** +// +//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! IOC interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_AON_GPIO_EDGE, pfnHandler); + + // Enable the IO edge interrupt. + IntEnable(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when an IO edge interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntUnregister(void) +{ + // Disable the interrupts. + IntDisable(INT_AON_GPIO_EDGE); + + // Unregister the interrupt handler. + IntUnregister(INT_AON_GPIO_EDGE); +} + +//***************************************************************************** +// +//! \brief Enables individual IO edge detect interrupt. +//! +//! This function enables the indicated IO edge interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO to enable edge detect interrupt for. +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntEnable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Disables individual IO edge interrupt sources. +//! +//! This function disables the indicated IO edge interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IOId is the IO edge interrupt source to be disabled. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCIntDisable(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Clears the IO edge interrupt source. +//! +//! The specified IO edge interrupt source is cleared, so that it no longer +//! asserts. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IOId is the IO causing the interrupt. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +IOCIntClear(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Clear the requested interrupt source by clearing the event. + GPIO_clearEventDio(ui32IOId); +} + +//***************************************************************************** +// +//! \brief Returns the status of the IO interrupts. +//! +//! \param ui32IOId is the IO to get the status for. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +IOCIntStatus(uint32_t ui32IOId) +{ + // Check the arguments. + ASSERT(ui32IOId < NUM_IO_MAX); + + // Get the event status. + return (GPIO_getEventDio(ui32IOId)); +} + + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO input. +//! +//! Setup an IO for standard GPIO input with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_ENABLE +//! +//! \param ui32IOId is the IO to setup for GPIO input +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioInput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Setup an IO for standard GPIO output. +//! +//! Setup an IO for standard GPIO output with the following configuration: +//! - Port ID: +//! - \ref IOC_PORT_GPIO +//! - Configuration: +//! - \ref IOC_CURRENT_2MA +//! - \ref IOC_STRENGTH_AUTO +//! - \ref IOC_NO_IOPULL +//! - \ref IOC_SLEW_DISABLE +//! - \ref IOC_HYST_DISABLE +//! - \ref IOC_NO_EDGE +//! - \ref IOC_INT_DISABLE +//! - \ref IOC_IOMODE_NORMAL +//! - \ref IOC_NO_WAKE_UP +//! - \ref IOC_INPUT_DISABLE +//! +//! \param ui32IOId is the IO to setup for GPIO output +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeGpioOutput(uint32_t ui32IOId); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard UART peripheral control. +//! +//! The UART pins must be properly configured for the UART peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). Other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). +//! +//! \note If a UART pin is not intended to be used, then the parameter in the +//! function should be \ref IOID_UNUSED. +//! +//! \param ui32Base is the base address of the UART module. +//! \param ui32Rx is the IO Id of the IO to use as UART Receive. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO Id of the IO to use as UART Transmit. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Rts is the IO Id of the IO to use for UART Request to send. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Cts, + uint32_t ui32Rts); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral master control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock output line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard SSI peripheral slave control. +//! +//! \param ui32Base is the base address of the SSI module to connect to the IOs +//! \param ui32Rx is the IO to connect to the SSI MOSI line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Tx is the IO to connect to the SSI MISO line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Fss is the IO to connect to the SSI FSS line. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the IO to connect to the SSI Clock input line. +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, + uint32_t ui32Tx, uint32_t ui32Fss, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure a set of IOs for standard I2C peripheral control. +//! +//! \param ui32Base is the base address of the I2C module to connect to the IOs +//! \param ui32Data is the I2C data line +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! \param ui32Clk is the I2C input clock +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, + uint32_t ui32Clk); + +//***************************************************************************** +// +//! \brief Configure an IO for AUX control. +//! +//! Use this function to enable AUX to control a specific IO. Please note, that +//! when using AUX to control the IO, the input/output control in the IOC is +//! bypassed and completely controlled by AUX, so enabling or disabling input +//! in the IOC has no effect. +//! +//! \note The IOs available for AUX control can vary from device to device. +//! +//! \param ui32IOId is the IO to setup for AUX usage. +//! - \ref IOID_0 +//! - ... +//! - \ref IOID_31 +//! - \ref IOID_UNUSED +//! +//! \return None +// +//***************************************************************************** +extern void IOCPinTypeAux(uint32_t ui32IOId); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_IOCPortConfigureSet + #undef IOCPortConfigureSet + #define IOCPortConfigureSet ROM_IOCPortConfigureSet + #endif + #ifdef ROM_IOCPortConfigureGet + #undef IOCPortConfigureGet + #define IOCPortConfigureGet ROM_IOCPortConfigureGet + #endif + #ifdef ROM_IOCIOShutdownSet + #undef IOCIOShutdownSet + #define IOCIOShutdownSet ROM_IOCIOShutdownSet + #endif + #ifdef ROM_IOCIOModeSet + #undef IOCIOModeSet + #define IOCIOModeSet ROM_IOCIOModeSet + #endif + #ifdef ROM_IOCIOIntSet + #undef IOCIOIntSet + #define IOCIOIntSet ROM_IOCIOIntSet + #endif + #ifdef ROM_IOCIOEvtSet + #undef IOCIOEvtSet + #define IOCIOEvtSet ROM_IOCIOEvtSet + #endif + #ifdef ROM_IOCIOPortPullSet + #undef IOCIOPortPullSet + #define IOCIOPortPullSet ROM_IOCIOPortPullSet + #endif + #ifdef ROM_IOCIOHystSet + #undef IOCIOHystSet + #define IOCIOHystSet ROM_IOCIOHystSet + #endif + #ifdef ROM_IOCIOInputSet + #undef IOCIOInputSet + #define IOCIOInputSet ROM_IOCIOInputSet + #endif + #ifdef ROM_IOCIOSlewCtrlSet + #undef IOCIOSlewCtrlSet + #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet + #endif + #ifdef ROM_IOCIODrvStrengthSet + #undef IOCIODrvStrengthSet + #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet + #endif + #ifdef ROM_IOCIOPortIdSet + #undef IOCIOPortIdSet + #define IOCIOPortIdSet ROM_IOCIOPortIdSet + #endif + #ifdef ROM_IOCIntEnable + #undef IOCIntEnable + #define IOCIntEnable ROM_IOCIntEnable + #endif + #ifdef ROM_IOCIntDisable + #undef IOCIntDisable + #define IOCIntDisable ROM_IOCIntDisable + #endif + #ifdef ROM_IOCPinTypeGpioInput + #undef IOCPinTypeGpioInput + #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput + #endif + #ifdef ROM_IOCPinTypeGpioOutput + #undef IOCPinTypeGpioOutput + #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput + #endif + #ifdef ROM_IOCPinTypeUart + #undef IOCPinTypeUart + #define IOCPinTypeUart ROM_IOCPinTypeUart + #endif + #ifdef ROM_IOCPinTypeSsiMaster + #undef IOCPinTypeSsiMaster + #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster + #endif + #ifdef ROM_IOCPinTypeSsiSlave + #undef IOCPinTypeSsiSlave + #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave + #endif + #ifdef ROM_IOCPinTypeI2c + #undef IOCPinTypeI2c + #define IOCPinTypeI2c ROM_IOCPinTypeI2c + #endif + #ifdef ROM_IOCPinTypeAux + #undef IOCPinTypeAux + #define IOCPinTypeAux ROM_IOCPinTypeAux + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __IOC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc_doc.h new file mode 100644 index 00000000..99799c99 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ioc_doc.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* Filename: ioc_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup ioc_api +//! @{ +//! \section sec_ioc Introduction +//! +//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). +//! The IOC consists of two APIs: +//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. +//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. +//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is +//! routed to a DIO for external use. +//! +//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api). +//! +//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the +//! peripheral module which is selected to control the DIO. +//! +//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the +//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO +//! can be "hardware controlled" if it is controlled by other modules than GPIO. +//! +//! \section sec_ioc_api API +//! +//! The API functions can be grouped like this: +//! +//! Configure all settings at the same time: +//! - \ref IOCPortConfigureSet() +//! - \ref IOCPortConfigureGet() +//! +//! Configure individual settings: +//! - \ref IOCIODrvStrengthSet() +//! - \ref IOCIOHystSet() +//! - \ref IOCIOInputSet() +//! - \ref IOCIOIntSet() +//! - \ref IOCIOModeSet() +//! - \ref IOCIOPortIdSet() +//! - \ref IOCIOPortPullSet() +//! - \ref IOCIOShutdownSet() +//! - \ref IOCIOSlewCtrlSet() +//! +//! Handle edge detection events: +//! - \ref IOCIntEnable() +//! - \ref IOCIntDisable() +//! - \ref IOCIntClear() +//! - \ref IOCIntStatus() +//! - \ref IOCIntRegister() +//! - \ref IOCIntUnregister() +//! +//! Configure IOCs for typical use cases (can also be used as example code): +//! - \ref IOCPinTypeAux() +//! - \ref IOCPinTypeGpioInput() +//! - \ref IOCPinTypeGpioOutput() +//! - \ref IOCPinTypeI2c() +//! - \ref IOCPinTypeSsiMaster() +//! - \ref IOCPinTypeSsiSlave() +//! - \ref IOCPinTypeUart() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.c new file mode 100644 index 00000000..c381a555 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.c @@ -0,0 +1,846 @@ +/****************************************************************************** +* Filename: osc.c +* +* Description: Driver for setting up the system Oscillators +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "aon_batmon.h" +#include "aon_rtc.h" +#include "osc.h" +#include "sys_ctrl.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef OSCClockSourceSet + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #undef OSCClockSourceGet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSCHF_DebugGetCrystalStartupTime + #define OSCHF_DebugGetCrystalStartupTime NOROM_OSCHF_DebugGetCrystalStartupTime + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #define OSC_HPOSCInitializeSingleInsertionFreqOffsParams NOROM_OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate + #undef OSC_LFXOSCInitStaticOffset + #define OSC_LFXOSCInitStaticOffset NOROM_OSC_LFXOSCInitStaticOffset + #undef OSC_LFXOSCRelativeFrequencyOffsetGet + #define OSC_LFXOSCRelativeFrequencyOffsetGet NOROM_OSC_LFXOSCRelativeFrequencyOffsetGet +#endif + +//***************************************************************************** +// +// OSCHF switch time calculator defines and globals +// +//***************************************************************************** + +#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 ) +#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 ) + +typedef struct { + uint32_t previousStartupTimeInUs ; + uint32_t timeXoscOff_CV ; + uint32_t timeXoscOn_CV ; + uint32_t timeXoscStable_CV ; + int32_t tempXoscOff ; +} OscHfGlobals_t; + +static OscHfGlobals_t oscHfGlobals; + +//***************************************************************************** +// +// XOSC_LF coefficients and scale factor for temperature-dependent ppm offset. +// Must be defined in application before calling OSC_LFXOSCInitStaticOffset +// +//***************************************************************************** +extern XoscLf_Params_t _lfXoscParams __attribute__((weak)); + +//***************************************************************************** +// +// Configure the oscillator input to the a source clock. +// +//***************************************************************************** +void +OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) +{ + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +//***************************************************************************** +// +// Get the source clock settings +// +//***************************************************************************** +uint32_t +OSCClockSourceGet(uint32_t ui32SrcClk) +{ + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return ( ui32ClockSource ); +} + +//***************************************************************************** +// +// Returns maximum startup time (in microseconds) of XOSC_HF +// +//***************************************************************************** +uint32_t +OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ) +{ + uint32_t deltaTimeSinceXoscOnInMs ; + int32_t deltaTempSinceXoscOn ; + uint32_t newStartupTimeInUs ; + + // Check CCFG to determine if device is configured for TCXO. + if( ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & CCFG_MODE_CONF_XOSC_FREQ_M ) == CCFG_MODE_CONF_XOSC_FREQ_TCXO ) + { + // Device configured for TCXO. Report fixed startup time located in CCFG with + // coversion from number of 100us to number of us. + newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & CCFG_MODE_CONF_1_TCXO_MAX_START_M ) >> + CCFG_MODE_CONF_1_TCXO_MAX_START_S ) * 100; + } + else + { + deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV ); + deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff; + + if ( deltaTempSinceXoscOn < 0 ) { + deltaTempSinceXoscOn = -deltaTempSinceXoscOn; + } + + if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) || + ( deltaTempSinceXoscOn > 5 ) || + ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) || + ( oscHfGlobals.previousStartupTimeInUs == 0 ) ) + { + newStartupTimeInUs = 2000; + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >> + CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125; + // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125 + } + } else { + newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin + if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) { + newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs; + } + } + + if ( newStartupTimeInUs < 200 ) { + newStartupTimeInUs = 200; + } + if ( newStartupTimeInUs > 4000 ) { + newStartupTimeInUs = 4000; + } + } + return ( newStartupTimeInUs ); +} + + +//***************************************************************************** +// +// Turns on XOSC_HF (but without switching to XOSC_HF) +// +//***************************************************************************** +void +OSCHF_TurnOnXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); +#endif + oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet(); +} + + +//***************************************************************************** +// +// Switch to XOSC_HF if XOSC_HF is ready. +// +//***************************************************************************** +bool +OSCHF_AttemptToSwitchToXosc( void ) +{ + uint32_t startupTimeInUs; + uint32_t prevLimmit25InUs; + +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) +#endif + { + // Already on XOSC - nothing to do + return ( 1 ); + } + if ( OSCHfSourceReady()) { + OSCHfSourceSwitch(); + + // Store startup time, but limit to 25 percent reduction each time. + oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet(); + startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); + prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs; + prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin + oscHfGlobals.previousStartupTimeInUs = startupTimeInUs; + if ( prevLimmit25InUs > startupTimeInUs ) { + oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs; + } + return ( 1 ); + } + return ( 0 ); +} + + +//***************************************************************************** +// +// Switch to RCOSC_HF and turn off XOSC_HF +// +//***************************************************************************** +void +OSCHF_SwitchToRcOscTurnOffXosc( void ) +{ +#if ( defined( ROM_OSCClockSourceSet )) + ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); +#else + OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); +#endif + + // Do the switching if not already running on RCOSC_HF +#if ( defined( ROM_OSCClockSourceGet )) + if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#else + if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) +#endif + { + OSCHfSourceSwitch(); + } + + oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet(); + oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC(); +} + +//***************************************************************************** +// +// Adjust the XOSC HF cap array relative to the factory setting +// +//***************************************************************************** +void +OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) +{ + { + // Read the MODE_CONF register in CCFG + uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + // Clear CAP_MODE and the CAPARRAY_DELATA field + ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M ); + // Insert new delta value + ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ); + // Update the HW register with the new delta value + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); + } +} + +//***************************************************************************** +// +// Initialize the frequency offset curve fitting parameters +// These are calculated based on the FCFG1:HPOSC_MEAS_x parameters. +// +//***************************************************************************** +#define D1OFFSET_25C (-16) +#define D2OFFSET_85C (-23) +#define D3OFFSET_n40C (5) + +#define HPOSC_COEFF_BITS (20) // HPOSC p1,p2,p3 coefficient precision +#define HPOSC_COEFF0_BITS (16) // HPOSC p0 coefficient precision +#define HPOSC_D_BITS (30) // HPOSC internal parameter +#define HPOSC_COEFF0_SHIFT (HPOSC_COEFF_BITS - HPOSC_COEFF0_BITS) // HPOSC internal parameter +#define HPOSC_SHIFT1 (2*HPOSC_COEFF_BITS - HPOSC_D_BITS) // HPOSC internal parameter +#define HPOSC_DC_BIAS (100000) // HPOSC internal parameter + +int32_t _hposcCoeffs[4] = {0}; // HPOSC polynomial coefficients + +typedef struct +{ + int32_t temp[3]; + int32_t dFreq[3]; +} hposc_insertions_t; + +typedef struct +{ + uint8_t pu0b[4]; + uint8_t pu1b[4]; + uint8_t pu2b[4]; + int64_t pu0c[4]; + int64_t pu1c[4]; + int64_t pu2c[4]; +} hposc_param_t; + +static void +multiplyColumns(int64_t *v1, int64_t *v2, int64_t *pBuf, uint8_t shift) +{ + pBuf[0] = (v1[1]*v2[2]) >> shift; + pBuf[1] = (v1[2]*v2[1]) >> shift; + pBuf[2] = (v1[0]*v2[2]) >> shift; + pBuf[3] = (v1[2]*v2[0]) >> shift; + pBuf[4] = (v1[0]*v2[1]) >> shift; + pBuf[5] = (v1[1]*v2[0]) >> shift; +} + +static int64_t +findDenominator(int64_t *col0, int64_t *col1, int64_t *col2) +{ + int64_t tmp, tmpBuf[6]; + + multiplyColumns(col1, col2, tmpBuf, HPOSC_SHIFT1); // Keep HPOSC_D_BITS precision + + tmp = (tmpBuf[0]*col0[0] - tmpBuf[1]*col0[0] - tmpBuf[2]*col0[1] + + tmpBuf[3]*col0[1] + tmpBuf[4]*col0[2] - tmpBuf[5]*col0[2]) >> HPOSC_COEFF_BITS; + + return tmp; +} + +static int64_t +findNumerator(int32_t *pInput, int64_t *pBuf) +{ + int64_t tmp; + + tmp = ((int64_t)pInput[0]*pBuf[0]) - ((int64_t)pInput[0]*pBuf[1]) - ((int64_t)pInput[1]*pBuf[2]) + + ((int64_t)pInput[1]*pBuf[3]) + ((int64_t)pInput[2]*pBuf[4]) - ((int64_t)pInput[2]*pBuf[5]); + + return tmp; +} + +static void +findHposcCoefficients(int32_t *pInput, int64_t *col0, int64_t *col1, int64_t *col2, hposc_param_t *pParam) +{ + int64_t d,c0,c1,c2,cn,tmpBuf[6]; + int32_t inputBuf[3]; + uint8_t i; + + if(col1 == NULL) /* 1 insertion */ + { + inputBuf[0] = pInput[0] - HPOSC_DC_BIAS; + c0 = (((int64_t)inputBuf[0] << HPOSC_D_BITS) / col0[0]); + c1 = 0; + c2 = 0; + } + else /* 3 insertion */ + { + /* Apply DC bias to input data */ + for(i = 0; i < 3; i++) + { + inputBuf[i] = pInput[i] - HPOSC_DC_BIAS; + } + + /* Solve intermediate parameters, d: HPOSC_D_BITS, c: HPOSC_COEFF_BITS*2 bits */ + d = findDenominator(col0, col1, col2); + + multiplyColumns(col1, col2, tmpBuf, 0); + cn = findNumerator(inputBuf, tmpBuf); + c0 = cn / d; + + multiplyColumns(col0, col2, tmpBuf, 0); + cn = -1*findNumerator(inputBuf, tmpBuf); + c1 = cn / d; + + multiplyColumns(col0, col1, tmpBuf, 0); + cn = findNumerator(inputBuf, tmpBuf); + c2 = cn / d; + } + + /* Compute TCF polynomial coefficients */ + for(i = 0; i < 4; i++) + { + cn = (((pParam->pu0c[i]*c0) >> (pParam->pu0b[i] - HPOSC_COEFF_BITS)) + + ((pParam->pu1c[i]*c1) >> (pParam->pu1b[i] - HPOSC_COEFF_BITS)) + + ((pParam->pu2c[i]*c2) >> (pParam->pu2b[i] - HPOSC_COEFF_BITS))) >> HPOSC_SHIFT1; + + if(i<3) + { + _hposcCoeffs[3-i] = cn; + } + else + { + _hposcCoeffs[0] = (cn >> HPOSC_COEFF0_SHIFT) + ((int64_t)HPOSC_DC_BIAS << HPOSC_COEFF0_BITS); // p[0] is combined with the DC bias + } + } +} + +static void +findHposcPc(int64_t *pCoeff, uint8_t *pBits, int32_t *pTemp, uint8_t nTemp, int64_t *pOutput) +{ + uint8_t i; + int32_t t1,t2,t3; + + for(i = 0; i < nTemp; i++) + { + t1 = pTemp[i]; + t2 = t1*t1; + t3 = t2*t1; + + pOutput[i] = (((int64_t)pCoeff[0]*t3)>>(pBits[0]-HPOSC_COEFF_BITS)) + (((int64_t)pCoeff[1]*t2)>>(pBits[1]-HPOSC_COEFF_BITS)) + + (((int64_t)pCoeff[2]*t1)>>(pBits[2]-HPOSC_COEFF_BITS)) + (((int64_t)pCoeff[3] )>>(pBits[3]-HPOSC_COEFF_BITS)); + } +} + +static void +readTempAndFreq(uint32_t regAddr, int32_t *pTemp, int32_t *pdFreq, int32_t deltaFreq) +{ + uint32_t insertionData = HWREG(regAddr); + + /* temp_stored = Temperature - 27, offset by -27C */ + *pTemp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W )); + + /* dFreq_stored = round( (Freq/12e6 - 1) * 2^22 ), 12MHz is the ideal frequency */ + *pdFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S ))) + >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W )); + *pdFreq = *pdFreq + deltaFreq; +} + +//***************************************************************************** +// The HPOSC initialization function +// - Must be called before using HPOSC +// - To be used when three temperature frequency offset measurements are available +//***************************************************************************** +void +OSC_HPOSCInitializeFrequencyOffsetParameters( void ) +{ + /* Initialize HPOSC internal parameter */ + hposc_insertions_t hposcMeas; + int64_t pu0[3],pu1[3],pu2[3] = {0}; + hposc_param_t hposcParm = + { + .pu0b = {42, 32, 27, 20}, + .pu0c = {-284,-184,536,-104798}, + .pu1b = {36, 32, 27, 20}, + .pu1c = {-1155,44130,-319090,-3563}, + .pu2b = {36, 32, 27, 20}, + .pu2c = {-3410,261727,-32194,-116627} + }; + + /* Retrieve insertions from FCFG */ + readTempAndFreq(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, &hposcMeas.temp[0], &hposcMeas.dFreq[0], D1OFFSET_25C); + readTempAndFreq(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, &hposcMeas.temp[1], &hposcMeas.dFreq[1], D2OFFSET_85C); + readTempAndFreq(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, &hposcMeas.temp[2], &hposcMeas.dFreq[2], D3OFFSET_n40C); + + /* Compute HPOSC polynomial coefficients */ + findHposcPc(hposcParm.pu0c, hposcParm.pu0b, &hposcMeas.temp[0], 3, pu0); + findHposcPc(hposcParm.pu1c, hposcParm.pu1b, &hposcMeas.temp[0], 3, pu1); + findHposcPc(hposcParm.pu2c, hposcParm.pu2b, &hposcMeas.temp[0], 3, pu2); + findHposcCoefficients(&hposcMeas.dFreq[0], pu0, pu1, pu2, &hposcParm); +} + +//***************************************************************************** +// Degub function to calculate the HPOSC polynomials for experimental data sets. +//***************************************************************************** +void +OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ) +{ + /* Initialize HPOSC internal parameter */ + hposc_insertions_t hposcMeas; + int64_t pu0[3],pu1[3],pu2[3] = {0}; + hposc_param_t hposcParm = + { + .pu0b = {42, 32, 27, 20}, + .pu0c = {-284,-184,536,-104798}, + .pu1b = {36, 32, 27, 20}, + .pu1c = {-1155,44130,-319090,-3563}, + .pu2b = {36, 32, 27, 20}, + .pu2c = {-3410,261727,-32194,-116627} + }; + + /* Retrieve insertions from FCFG */ + readTempAndFreq((uint32_t)&pDebugData->meas_1, &hposcMeas.temp[0], &hposcMeas.dFreq[0], pDebugData->offsetD1); + readTempAndFreq((uint32_t)&pDebugData->meas_2, &hposcMeas.temp[1], &hposcMeas.dFreq[1], pDebugData->offsetD2); + readTempAndFreq((uint32_t)&pDebugData->meas_3, &hposcMeas.temp[2], &hposcMeas.dFreq[2], pDebugData->offsetD3); + + /* Compute HPOSC polynomial coefficients */ + findHposcPc(hposcParm.pu0c, hposcParm.pu0b, &hposcMeas.temp[0], 3, pu0); + findHposcPc(hposcParm.pu1c, hposcParm.pu1b, &hposcMeas.temp[0], 3, pu1); + findHposcPc(hposcParm.pu2c, hposcParm.pu2b, &hposcMeas.temp[0], 3, pu2); + findHposcCoefficients(&hposcMeas.dFreq[0], pu0, pu1, pu2, &hposcParm); +} + +//***************************************************************************** +// Special HPOSC initialization function +// - Used when a single temperature offset measurement is available +// - To get a better crystal performance (SW TCXO) +//***************************************************************************** +void +OSC_HPOSCInitializeSingleInsertionFreqOffsParams( uint32_t measFieldAddress ) +{ + /* Initialize HPOSC internal parameter */ + hposc_insertions_t hposcMeas; + int64_t pu0; + hposc_param_t hposcParm = + { + /* Coefficients for SW-TCXO */ + .pu0b = {44, 44, 27, 20}, + .pu0c = {8183, -2546, -210, -104866} + }; + + /* Retrieve insertions from FCFG */ + readTempAndFreq( measFieldAddress, &hposcMeas.temp[0], &hposcMeas.dFreq[0], 0); + + /* Compute HPOSC polynomial coefficients */ + findHposcPc(hposcParm.pu0c, hposcParm.pu0b, &hposcMeas.temp[0], 1, &pu0); + findHposcCoefficients(&hposcMeas.dFreq[0], &pu0, NULL, NULL, &hposcParm); +} + +//***************************************************************************** +// XOSC_LF compensation initialization function +// - Should be called once, and before OSC_LFXOSCRelativeFrequencyOffsetGet +// - _lfXoscParams must be defined before calling this function +//***************************************************************************** +void OSC_LFXOSCInitStaticOffset(void) +{ + int16_t xoscLfCorrection; + int8_t xoscLfCorrectionTemperature; + + /* If device is untrimmed, apply default values */ + if (HWREG(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_5) == 0xFFFFFFFF) + { + /* These values correspond to a 0 ppm offset measurement at 25 degC */ + xoscLfCorrection = 0; + xoscLfCorrectionTemperature = 25; + } + else + { + xoscLfCorrection = (int16_t)((HWREG(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_5) & FCFG1_HPOSC_MEAS_5_HPOSC_D5_M) >> + FCFG1_HPOSC_MEAS_5_HPOSC_D5_S); + xoscLfCorrectionTemperature = (int8_t)(( + HWREG(FCFG1_BASE + FCFG1_O_HPOSC_MEAS_5) & FCFG1_HPOSC_MEAS_5_HPOSC_T5_M) >> + FCFG1_HPOSC_MEAS_5_HPOSC_T5_S); + /* Temperature in FCFG is offset by 27 degrees */ + xoscLfCorrectionTemperature += 27; + } + + /* Calculate the difference between expected offset at FCFG1 temperature, vs actual offset at FCFG1 temperature. + * This becomes a static offset whenever a new temperature offset is calculated. + * ppm(T) = a*T^2 + b*T + c - d, where d represents a device specific offset from the ideal polynomial + * d = ppm(T_trim) - ppm_trim, where ppm_trim is the actual ppm offset measured at production, at the temperature T_trim + * ppm_trim is found from FCFG1_HPOSC_MEAS_5_HPOSC_D5 in FCFG, where FCFG1_HPOSC_MEAS_5_HPOSC_D5 = (f/32768 - 1) * 2^22 + */ + _lfXoscParams.coeffD = (_lfXoscParams.coeffA * xoscLfCorrectionTemperature * xoscLfCorrectionTemperature + + _lfXoscParams.coeffB * xoscLfCorrectionTemperature + _lfXoscParams.coeffC) - + (int32_t)((int64_t)xoscLfCorrection * (1000000LL << _lfXoscParams.shift) / 4194304LL); +} + +//***************************************************************************** +// +// Calculate the temperature dependent relative frequency offset of XOSC_LF +// +//***************************************************************************** +int32_t OSC_LFXOSCRelativeFrequencyOffsetGet(int32_t temperature) +{ + /* The offset (ppm) is given by + * ppm(T) = a*T^2 + b*T + c - d + * The coefficients a, b, c and d are taken from the internal structure _lfXoscParams, which + * must be defined and initialised before this function is called. + */ + return ((_lfXoscParams.coeffA * temperature * temperature) + (_lfXoscParams.coeffB * temperature) + + _lfXoscParams.coeffC - _lfXoscParams.coeffD) >> + _lfXoscParams.shift; +} + +//***************************************************************************** +// +// Calculate the temperature dependent relative frequency offset of HPOSC +// +//***************************************************************************** +int32_t +OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) +{ + // Estimate HPOSC frequency offset, using temperature and curve fitting parameters + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P[3]*(t - T0)^3 + P[2]*(t - T0)^2 + P[1]*(t - T0) + P[0], where: P0,P1,P2,P3 are curve fitting parameters + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + + int32_t d,t1,t2,t3; + + t1 = tempDegC - 27; + t2 = t1 * t1; + t3 = t2 * t1; + + d = ((((int64_t)_hposcCoeffs[3]*t3 + (int64_t)_hposcCoeffs[2]*t2 + (int64_t)_hposcCoeffs[1]*t1) >> HPOSC_COEFF0_SHIFT) + + (int64_t)_hposcCoeffs[0]) >> HPOSC_COEFF0_BITS; + + return ( d ); +} + +//***************************************************************************** +// +// Converts the relative frequency offset of HPOSC to the RF Core parameter format. +// +//***************************************************************************** +int16_t +OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) +{ + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +//***************************************************************************** +// +// Compensate the RTC increment based on the relative frequency offset of HPOSC +// +//***************************************************************************** +void +OSC_HPOSCRtcCompensate( int32_t relFreqOffset ) +{ + uint32_t rtcSubSecInc; + uint32_t lfClkFrequency; + uint32_t hfFreq; + int64_t calcFactor; + + // Calculate SCLK_HF frequency, defined as: + // hfFreq = 48000000 * (1 + relFreqOffset/(2^22)) + if( relFreqOffset >= 0 ) + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000; + } + else + { + calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000; + } + hfFreq = 48000000 + calcFactor; + + // Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536 + lfClkFrequency = ( hfFreq + 768 ) / 1536; + + // Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ + rtcSubSecInc = 0x4000000000 / lfClkFrequency; + + /* Update SUBSECINC value */ + SetupSetAonRtcSubSecInc(rtcSubSecInc); +} + +//***************************************************************************** +// +// Get crystal amplitude (assuming crystal is running). +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetCrystalAmplitude( void ) +{ + uint32_t oscCfgRegCopy ; + uint32_t startTime ; + uint32_t deltaTime ; + uint32_t ampValue ; + + // The specified method is as follows: + // 1. Set minimum interval between oscillator amplitude calibrations. + // (Done by setting PER_M=0 and PER_E=1) + // 2. Wait approximately 4 milliseconds in order to measure over a + // moderately large number of calibrations. + // 3. Read out the crystal amplitude value from the peek detector. + // 4. Restore original oscillator amplitude calibrations interval. + // 5. Return crystal amplitude value converted to millivolt. + + oscCfgRegCopy = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ); + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = ( 1 << AON_PMCTL_OSCCFG_PER_E_S ); + + startTime = AONRTCCurrentCompareValueGet(); + do { + deltaTime = AONRTCCurrentCompareValueGet() - startTime; + } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))); + ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >> + DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ; + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = oscCfgRegCopy; + + return ( ampValue * 15 ); +} + +//***************************************************************************** +// +// Get the expected average crystal amplitude. +// +//***************************************************************************** +uint32_t +OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ) +{ + uint32_t ampCompTh1 ; + uint32_t highThreshold ; + uint32_t lowThreshold ; + + ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); + highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ; + lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >> + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ; + + return ((( highThreshold + lowThreshold ) * 15 ) >> 1 ); +} + +//***************************************************************************** +// +// Measure the crystal startup time - in number of LF clock edges +// +//***************************************************************************** +uint32_t OSCHF_DebugGetCrystalStartupTime( void ) +{ + uint32_t lfEdgesFound = 0 ; + + // Start operation in sync with the LF clock + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); + + OSCHF_TurnOnXosc(); + while ( ! OSCHF_AttemptToSwitchToXosc() ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); + lfEdgesFound ++ ; + } + OSCHF_SwitchToRcOscTurnOffXosc(); + + return ( lfEdgesFound ); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.h new file mode 100644 index 00000000..3ebdde6d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/osc.h @@ -0,0 +1,861 @@ +/****************************************************************************** +* Filename: osc.h +* +* Description: Defines and prototypes for the system oscillator control. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup osc_api +//! @{ +// +//***************************************************************************** + +#ifndef __OSC_H__ +#define __OSC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ddi_0_osc.h" +#include "rom.h" +#include "ddi.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define OSCClockSourceSet NOROM_OSCClockSourceSet + #define OSCClockSourceGet NOROM_OSCClockSourceGet + #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime + #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc + #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc + #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetCrystalStartupTime NOROM_OSCHF_DebugGetCrystalStartupTime + #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSCInitializeSingleInsertionFreqOffsParams NOROM_OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate + #define OSC_LFXOSCInitStaticOffset NOROM_OSC_LFXOSCInitStaticOffset + #define OSC_LFXOSCRelativeFrequencyOffsetGet NOROM_OSC_LFXOSCRelativeFrequencyOffsetGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines the polynomial coefficients for calculating +//! the XOSC LF ppm offset as function of temperature. +//! +//! ppm(T) = (a*T^2 + b*T + c - d) >> shift +//! +//! The coefficients a, b, and c are typically defined by the application, +//! while d is calculated by calling \ref OSC_LFXOSCInitStaticOffset. The fixed point +//! coefficients stored in this structure are the rounded result of the true +//! floating point coefficients, multiplied by a factor of 2^shift. +//! This struct is used in \ref OSC_LFXOSCRelativeFrequencyOffsetGet. +//! +//! \note Before calling \ref OSC_LFXOSCInitStaticOffset, the symbol _lfXoscParams +//! must be defined with type XoscLf_Params_t +//! +/*! +\verbatim +// Example of _lfXoscParams definition +XoscLf_Params_t _lfXoscParams = {.coeffA = -167772, .coeffB = 6710886, .coeffC = -62914560, .shift = 22}; +\endverbatim +*/ +//! +// +//***************************************************************************** +typedef struct +{ + int32_t coeffA; + int32_t coeffB; + int32_t coeffC; + int32_t coeffD; + uint8_t shift; +} XoscLf_Params_t; + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 + +//***************************************************************************** +// +// Defines for the High Frequency XTAL Power mode +// +//***************************************************************************** +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_LF 0x00000004 + +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 + +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 + +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set Power Mode for High Frequency XTAL Oscillator. +//! +//! \param ui32Mode is the power mode for the HF XTAL. +//! - \ref LOW_POWER_XOSC +//! - \ref HIGH_POWER_XOSC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +OSCXHfPowerModeSet(uint32_t ui32Mode) +{ + // Check the arguments. + ASSERT((ui32Mode == LOW_POWER_XOSC) || + (ui32Mode == HIGH_POWER_XOSC)); + + // Change the power mode. + DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, + ui32Mode); +} + +//***************************************************************************** +// +//! \brief Enables OSC clock loss event detection. +//! +//! Enables the clock loss event flag to be raised if a clock loss is detected. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventDisable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventEnable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); +} + +//***************************************************************************** +// +//! \brief Disables OSC clock loss event detection. +//! +//! Disabling the OSC clock loss event does also clear the clock loss event flag. +//! +//! \note OSC clock loss event must be disabled before SCLK_LF clock source is +//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the +//! change is confirmed (by calling \ref OSCClockSourceGet()). +//! +//! \return None +//! +//! \sa \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +OSCClockLossEventDisable( void ) +{ + DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); +} + +//***************************************************************************** +// +//! \brief Configure the oscillator input to the a source clock. +//! +//! Use this function to set the oscillator source for one or more of the +//! system source clocks. +//! +//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do +//! the actual switch. Enabling the high frequency XTAL can take several hundred +//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), +//! leaving System CPU free to perform other tasks as the XTAL starts up. +//! +//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the +//! high frequency oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF) +//! can be derived from all 4 oscillators. +//! +//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown +//! until the LF clock is running which can be checked using \ref OSCClockSourceGet(). +//! +//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF) +//! clock source is changed and remain disabled until the change is confirmed. +//! +//! \param ui32SrcClk is the source clocks to configure. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_LF +//! \param ui32Osc is the oscillator that drives the source clock. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) +//! +//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() +//! +//! \return None +// +//***************************************************************************** +extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc); + +//***************************************************************************** +// +//! \brief Get the source clock settings. +//! +//! Use this function to get the oscillator source for one of the system source +//! clocks. +//! +//! \param ui32SrcClk is the source clock to check. +//! - \ref OSC_SRC_CLK_HF +//! - \ref OSC_SRC_CLK_LF +//! +//! \return Returns the type of oscillator that drives the clock source. +//! - \ref OSC_RCOSC_HF +//! - \ref OSC_XOSC_HF +//! - \ref OSC_RCOSC_LF +//! - \ref OSC_XOSC_LF +//! +//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch() +// +//***************************************************************************** +extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk); + +//***************************************************************************** +// +//! \brief Check if the HF clock source is ready to be switched. +//! +//! If a request to switch the HF clock source has been made, this function +//! can be used to check if the clock source is ready to be switched. +//! +//! Once the HF clock source is ready the switch can be performed by calling +//! the \ref OSCHfSourceSwitch() +//! +//! \return Returns status of HF clock source: +//! - \c true : HF clock source is ready. +//! - \c false : HF clock source is \b not ready. +// +//***************************************************************************** +__STATIC_INLINE bool +OSCHfSourceReady(void) +{ + // Return the readiness of the HF clock source + return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? + true : false; +} + +//***************************************************************************** +// +//! \brief Switch the high frequency clock. +//! +//! When switching the HF clock source the clock period might be prolonged +//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that +//! this does not coincide with a read access to the Flash, potentially +//! freezing the device, the HF clock source switch must be executed from ROM. +//! +//! \note This function will not return until the clock source has been +//! switched. It is left to the programmer to ensure, that there is a pending +//! request for a HF clock source switch before this function is called. +//! +//! \return None +//! +//! \sa \ref OSCClockSourceSet() +// +//***************************************************************************** +__STATIC_INLINE void +OSCHfSourceSwitch(void) +{ + // Read target clock (lower half of the 32-bit CTL0 register) + uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M; + + // If target clock source is RCOSC, change clock source for DCDC to RCOSC + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC) + { + // Force DCDC to use RCOSC before switching SCLK_HF to RCOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + } + + // Switch the HF clock source + HapiHFSourceSafeSwitch(); + + // If target clock source is XOSC, change clock source for DCDC to "auto" + if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC) + { + // Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M; + } +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active. +//! +//! \return Returns status of HPOSC functionality: +//! - \c true : HPOSC is enabled. +//! - \c false : HPOSC is not enabled. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabled(void) +{ + bool enabled = false; + + if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && + (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) + { + enabled = true; + } + + return (enabled); +} + +//***************************************************************************** +// +//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF. +//! +//! This function checks if the device supports HPOSC and that HPOSC is selected +//! as HF oscillator for use when the radio is active and also that SCLK_LF is +//! derived from XOSC_HF. +//! +//! \return Returns status of HPOSC and SCLK_LF configuration: +//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF. +//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF. +// +//***************************************************************************** +__STATIC_INLINE bool +OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) +{ + bool enabled = false; + + // Check configuration by reading lower half of the 32-bit CTL0 register + uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) && + ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) ) + { + enabled = true; + } + + return (enabled); +} + +//***************************************************************************** +// +//! \brief Returns maximum startup time (in microseconds) of XOSC_HF. +//! +//! The startup time depends on several factors. This function calculates the +//! maximum startup time based on statistical information. +//! +//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the +//! startup will occur. +//! +//! \return Time margin to use in microseconds. +// +//***************************************************************************** +extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); + +//***************************************************************************** +// +//! \brief Turns on XOSC_HF (but without switching to XOSC_HF). +//! +//! This function simply indicates the need for XOSC_HF to the hardware which +//! initiates the XOSC_HF startup. +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_TurnOnXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to XOSC_HF if XOSC_HF is ready. +//! +//! This is a non-blocking function checking if the XOSC_HF is ready and +//! performs the switching if ready. The function is somewhat blocking in the +//! case where switching is performed. +//! +//! \return Returns status of the XOSC_HF switching: +//! - \c true : Switching to XOSC_HF has occurred. +//! - \c false : Switching has not occurred. +// +//***************************************************************************** +extern bool OSCHF_AttemptToSwitchToXosc( void ); + +//***************************************************************************** +// +//! \brief Switch to RCOSC_HF and turn off XOSC_HF. +//! +//! This operation takes approximately 50 microseconds (can be shorter if +//! RCOSC_HF already was running). +//! +//! \return None +// +//***************************************************************************** +extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); + +//***************************************************************************** +// +//! \brief Get crystal amplitude (assuming crystal is running). +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function uses an on-chip ADC and peak detector for reading the crystal +//! amplitude. The measurement time is set to 4 milliseconds and this function +//! does not return before the measurement is done. +//! +//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt. +//! +//! \return Returns crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Get the expected average crystal amplitude. +//! +//! \note This is a debug function only. +//! It is hence not recommended to call this function in normal operation. +//! +//! This function read the configured high and low thresholds and returns +//! the mean value converted to millivolt. +//! +//! \return Returns expected average crystal amplitude in millivolt. +//! +//! \sa OSCHF_DebugGetCrystalAmplitude() +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); + +//***************************************************************************** +// +//! \brief Measure the crystal startup time. +//! +//! \note This is a debug function that should not be needed in normal operation. +//! +//! This function assumes that the chip is running on RCOSC_HF when called. +//! It then switches to XOSC_HF while measuring number of LF-clock edges +//! before XOSC_HF has started and are ready to be used. +//! After that, the function switches back to RCOSC_HF and returns number of LF-edges found. +//! +//! The length in time between the LF clock edges is approximately 15 microseconds. +//! Or more exactly: LF_clock_edges / ( 32768 * 2 ) seconds. +//! +//! Please note that the startup time, in addition to the crystal itself also can vary depending +//! on the time since the crystal was stopped and the frequency of the RCOSC_HF oscillator. +//! Calling this function intensively will show a shorter startup time than in typical use cases. +//! When running with TI-RTOS there is a background task (optional but default on) adjusting RCOSC_HF +//! to be as equal as possible to the crystal frequency, giving the shortest possible startup time. +//! +//! \return Returns number of LF-clock edges from starting the crystal until it's ready to be used. +// +//***************************************************************************** +extern uint32_t OSCHF_DebugGetCrystalStartupTime( void ); + +//***************************************************************************** +// +//! \brief HPOSC initialization function. Must always be called before using HPOSC. +//! +//! Calculates the fitting curve parameters (polynomials) to be used by the +//! HPOSC temperature compensation. +//! +//! \return None +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams(), OSC_HPOSCInitializeSingleInsertionFreqOffsParams() +// +//***************************************************************************** +extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); + +//***************************************************************************** +// +//! \brief Data structure for experimental HPOSC polynomials calculation. +//! +//! The structure of the meas_1, meas_2 and meas_3 parameter is +//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3. +//! +//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() +// +//***************************************************************************** +typedef struct { + uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp) + uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp) + uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp) + int32_t offsetD1 ; //!< Offset to measurement set 1 + int32_t offsetD2 ; //!< Offset to measurement set 2 + int32_t offsetD3 ; //!< Offset to measurement set 3 + int32_t polyP3 ; //!< The P3 polynomial +} HposcDebugData_t; + +//***************************************************************************** +// +//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets. +//! +//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t +//! +//! \return None +//! +//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() +// +//***************************************************************************** +extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ); + +//***************************************************************************** +// +//! \brief Special HPOSC initialization function for single temperature compensation. +//! +//! Used when a single temperature offset measurement is available. +//! This is espesially designed to get a better crystal performance (SW TCXO) on the SiP module +//! but can also be usful to get better crystal performance over the entire temperature range on a standard design as well. +//! +//! \return None +//! +//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() +// +//***************************************************************************** +extern void OSC_HPOSCInitializeSingleInsertionFreqOffsParams( uint32_t measFieldAddress ); + +//***************************************************************************** +// +//! \brief Calculate the temperature dependent relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! The frequency offset from the nominal value can be predicted based on +//! second order linear interpolation using coefficients measured in chip +//! production and stored as factory configuration parameters. +//! +//! This function calculates the relative frequency offset, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset (the value returned). +//! +//! By knowing the relative frequency offset it is then possible to compensate +//! any timing related values accordingly. +//! +//! \param tempDegC is the chip temperature in degrees Celsius. Use the +//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature. +//! +//! \return Returns the relative frequency offset parameter d. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() +// +//***************************************************************************** +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); + +//***************************************************************************** +// +//! \brief Adjust the XOSC HF cap array relative to the factory setting +//! +//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63. +//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting. +//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c). +//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting. +//! +//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted +//! +//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting. +//! +//! \return None +// +//***************************************************************************** +extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); + +//***************************************************************************** +// +//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format. +//! +//! The HPOSC (High Precision Oscillator) clock is used by the RF Core. +//! To compensate for a frequency offset in the frequency of the clock source, +//! a frequency offset parameter can be provided as part of the radio configuration +//! override setting list to enable compensation of the RF synthesizer frequency, +//! symbol timing, and radio timer to still achieve correct frequencies. +//! +//! The RF Core takes a relative frequency offset parameter defined differently +//! compared to the relative frequency offset parameter returned from function +//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted: +//! 
+//!     F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
+//!
+//! where +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - F_HPOSC is the current HPOSC frequency. +//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned). +//! +//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return Returns the relative frequency offset in RF Core format. +//! +//! \sa OSC_HPOSCRelativeFrequencyOffsetGet() +// +//***************************************************************************** +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); + +//***************************************************************************** +// +//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC +//! +//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. +//! This variation forces the RTC increment to be compensated if SCLK_LF is configured +//! to be derived from the HF clock of HPOSC. +//! This function must only be called if SCLK_LF is configured to be derived from +//! the HF clock of HPOSC. The status of this configuration can be determined +//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function. +//! +//! This function first calculates the HPOSC frequency, defined as: +//! 
+//!     F_HPOSC = F_nom * (1 + d/(2^22))
+//!
+//! where +//! - F_HPOSC is the current HPOSC frequency. +//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. +//! - d is the relative frequency offset given by the input argument relFreqOffset. +//! Then the SCLK_LF frequency is calculated, defined as: +//! 
+//!     F_SCLK_LF = F_HPOSC / 1536
+//!
+//! Then the RTC increment SUBSECINC is calculated, defined as; +//! 
+//!     SUBSECINC = (2^38) / F_SCLK_LF
+//!
+//! Finally the RTC module is updated with the calculated SUBSECINC value. +//! +//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() +//! +//! \return None +//! +// +//***************************************************************************** +extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); + +//***************************************************************************** +// +//! \brief Initialize device specific coefficient for XOSC LF RTC compensation. +//! +//! Calculates the device specific static offset of XOSC LF and stores it as a coefficient in the internal _lfXoscParams +//! polynomial structure. +//! +//! \warning _lfXoscParams must be defined and populated with polynomial coefficients a, b, and c if this function is called. +//! +//! \note This function must be called once, before calling \ref OSC_LFXOSCRelativeFrequencyOffsetGet. +//! +//! \return None +//! +// +//***************************************************************************** +extern void OSC_LFXOSCInitStaticOffset(void); + +//***************************************************************************** +// +//! \brief Calculates the ppm offset of XOSC LF for a given temperature. +//! +//! The offset (measured in ppm) is given by a second order polynomial function of temperature, T: +//! ppm(T) = a*T^2 + b*T + c - d. +//! The coefficients a, b, c, and d are taken from _lfXoscParams.coeffA, _lfoXscParams.coeffB, +//! _lfXoscParams.coeffC and _lfXoscParams.coeffD and scaled down for fixed point arithmetic +//! by a factor of 2^_lfXoscParams.shift. +//! _lfXoscParams must be defined by the application, and must be fully initialized by calling +//! \ref OSC_LFXOSCInitStaticOffset once, before this function is called. +//! +//! \note \ref OSC_LFXOSCInitStaticOffset should be called once, before this function is used. +//! +//! \param temperature is the on-chip temperature in degrees Celcius. +//! +//! \return Returns the offset in XOSC LF from the nominal frequency, in ppm. +//! +// +//***************************************************************************** +extern int32_t OSC_LFXOSCRelativeFrequencyOffsetGet(int32_t temperature); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_OSCClockSourceSet + #undef OSCClockSourceSet + #define OSCClockSourceSet ROM_OSCClockSourceSet + #endif + #ifdef ROM_OSCClockSourceGet + #undef OSCClockSourceGet + #define OSCClockSourceGet ROM_OSCClockSourceGet + #endif + #ifdef ROM_OSCHF_GetStartupTime + #undef OSCHF_GetStartupTime + #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime + #endif + #ifdef ROM_OSCHF_TurnOnXosc + #undef OSCHF_TurnOnXosc + #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc + #endif + #ifdef ROM_OSCHF_AttemptToSwitchToXosc + #undef OSCHF_AttemptToSwitchToXosc + #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc + #endif + #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc + #undef OSCHF_SwitchToRcOscTurnOffXosc + #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc + #endif + #ifdef ROM_OSCHF_DebugGetCrystalAmplitude + #undef OSCHF_DebugGetCrystalAmplitude + #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude + #endif + #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude + #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude + #endif + #ifdef ROM_OSCHF_DebugGetCrystalStartupTime + #undef OSCHF_DebugGetCrystalStartupTime + #define OSCHF_DebugGetCrystalStartupTime ROM_OSCHF_DebugGetCrystalStartupTime + #endif + #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #undef OSC_HPOSCInitializeFrequencyOffsetParameters + #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters + #endif + #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #undef OSC_HPOSC_Debug_InitFreqOffsetParams + #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams + #endif + #ifdef ROM_OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #undef OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #define OSC_HPOSCInitializeSingleInsertionFreqOffsParams ROM_OSC_HPOSCInitializeSingleInsertionFreqOffsParams + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #undef OSC_HPOSCRelativeFrequencyOffsetGet + #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet + #endif + #ifdef ROM_OSC_AdjustXoscHfCapArray + #undef OSC_AdjustXoscHfCapArray + #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray + #endif + #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert + #endif + #ifdef ROM_OSC_HPOSCRtcCompensate + #undef OSC_HPOSCRtcCompensate + #define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate + #endif + #ifdef ROM_OSC_LFXOSCInitStaticOffset + #undef OSC_LFXOSCInitStaticOffset + #define OSC_LFXOSCInitStaticOffset ROM_OSC_LFXOSCInitStaticOffset + #endif + #ifdef ROM_OSC_LFXOSCRelativeFrequencyOffsetGet + #undef OSC_LFXOSCRelativeFrequencyOffsetGet + #define OSC_LFXOSCRelativeFrequencyOffsetGet ROM_OSC_LFXOSCRelativeFrequencyOffsetGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __OSC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.c new file mode 100644 index 00000000..2626f274 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.c @@ -0,0 +1,1774 @@ +/****************************************************************************** +* Filename: pka.c +* +* Description: Driver for the PKA module +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pka.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PKAClearPkaRam + #define PKAClearPkaRam NOROM_PKAClearPkaRam + #undef PKAGetOpsStatus + #define PKAGetOpsStatus NOROM_PKAGetOpsStatus + #undef PKAArrayAllZeros + #define PKAArrayAllZeros NOROM_PKAArrayAllZeros + #undef PKAZeroOutArray + #define PKAZeroOutArray NOROM_PKAZeroOutArray + #undef PKABigNumModStart + #define PKABigNumModStart NOROM_PKABigNumModStart + #undef PKABigNumModGetResult + #define PKABigNumModGetResult NOROM_PKABigNumModGetResult + #undef PKABigNumDivideStart + #define PKABigNumDivideStart NOROM_PKABigNumDivideStart + #undef PKABigNumDivideGetQuotient + #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient + #undef PKABigNumDivideGetRemainder + #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder + #undef PKABigNumCmpStart + #define PKABigNumCmpStart NOROM_PKABigNumCmpStart + #undef PKABigNumCmpGetResult + #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult + #undef PKABigNumInvModStart + #define PKABigNumInvModStart NOROM_PKABigNumInvModStart + #undef PKABigNumInvModGetResult + #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult + #undef PKABigNumExpModStart + #define PKABigNumExpModStart NOROM_PKABigNumExpModStart + #undef PKABigNumExpModGetResult + #define PKABigNumExpModGetResult NOROM_PKABigNumExpModGetResult + #undef PKABigNumMultiplyStart + #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart + #undef PKABigNumMultGetResult + #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult + #undef PKABigNumAddStart + #define PKABigNumAddStart NOROM_PKABigNumAddStart + #undef PKABigNumAddGetResult + #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult + #undef PKABigNumSubStart + #define PKABigNumSubStart NOROM_PKABigNumSubStart + #undef PKABigNumSubGetResult + #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult + #undef PKAEccMultiplyStart + #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart + #undef PKAEccMontgomeryMultiplyStart + #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart + #undef PKAEccMultiplyGetResult + #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult + #undef PKAEccAddStart + #define PKAEccAddStart NOROM_PKAEccAddStart + #undef PKAEccAddGetResult + #define PKAEccAddGetResult NOROM_PKAEccAddGetResult + #undef PKAEccVerifyPublicKeyWeierstrassStart + #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart +#endif + + + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) + +#define IS_WORD_ALIGNED(ptr) (((uintptr_t)(ptr) << 30) == 0U) + + +//***************************************************************************** +// +// Define for the maximum curve size supported by the PKA module in 32 bit +// word. +// \note PKA hardware module can support up to 384 bit curve size due to the +// 2K of PKA RAM. +// +//***************************************************************************** +#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 + +//***************************************************************************** +// +// Define for the maximum length of the big number supported by the PKA module +// in 32 bit word. +// +//***************************************************************************** +#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD + +//***************************************************************************** +// +// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that +// the base address of the parameter should not be written to a NPTR register. +// +//***************************************************************************** +#define PKA_NO_POINTER_REG 0xFF + +//***************************************************************************** +// +// NIST P224 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint224 NISTP224_generator = { + .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, }}, + .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, }}, +}; + +const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, + 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, + 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, + 0x85, 0x0A, 0x05, 0xB4}}; + +const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +//***************************************************************************** +// +// NIST P256 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 NISTP256_generator = { + .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, + 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, + 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, + .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, + 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, + 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, +}; + +const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, + 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, + 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, + 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, + 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +//***************************************************************************** +// +// NIST P384 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 NISTP384_generator = { + .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, + 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, + 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, + 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, + 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, + 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, + .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, + 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, + 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, + 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, + 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, + 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, +}; + +const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, + 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, + 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, + 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, + 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, + 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; + +const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, + 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, + 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + + +//***************************************************************************** +// +// NIST P521 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint521 NISTP521_generator = { + .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, + 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, + 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, + 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, + 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, + 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, + 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, + 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, + 0xc6, 0x00}}, + .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, + 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, + 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, + 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, + 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, + 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, + 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, + 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, + 0x18, 0x01}}, +}; + +const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, + 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, + 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, + 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, + 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, + 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, + 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, + 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, + 0x51, 0x00}}; + +const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, + 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, + 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, + 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + + +//***************************************************************************** +// +// Brainpool P256r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 BrainpoolP256R1_generator = { + .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, + 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, + 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, + 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, + .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, + 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, + 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, + 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, +}; + +const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, + 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, + 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, + 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, + 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, + 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; + +const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, + 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, + 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, + 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; + +const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, + 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, + 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +//***************************************************************************** +// +// Brainpool P384r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 BrainpoolP384R1_generator = { + .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, + 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, + 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, + 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, + 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, + 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, + .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, + 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, + 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, + 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, + 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, + 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, +}; + +const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, + 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, + 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, + 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, + 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, + 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, + 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, + 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, + 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; + +const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, + 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, + 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, + 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, + 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, + 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; + +const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, + 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, + 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, + 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +//***************************************************************************** +// +// Brainpool P512r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint512 BrainpoolP512R1_generator = { + .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, + 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, + 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, + 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, + 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, + 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, + 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, + 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, + .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, + 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, + 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, + 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, + 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, + 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, + 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, + 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, +}; + +const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, + 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, + 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, + 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, + 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, + 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, + 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, + 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, + 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, + 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, + 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, + 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; + +const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, + 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, + 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, + 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, + 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, + 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, + 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, + 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; + +const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, + 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, + 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, + 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, + 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +//***************************************************************************** +// +// Curve25519 constants in little endian format. byte[0] is the least +// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 Curve25519_generator = { + .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, + 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, + 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + + +//***************************************************************************** +// +// Zeroize PKA RAM. Not threadsafe. +// +//***************************************************************************** +void PKAClearPkaRam(void) +{ + // Get initial state + uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); + + // OR in zeroize bit + secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N; + + // Start zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; + + // Wait 256 cycles for PKA RAM to be cleared + CPUdelay(256 / 4); + + // Turn off zeroization + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module, set required registers, and add an offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + uint32_t i; + uint_fast8_t j; + uint32_t tempWord; + uint32_t *paramWordAlias = (uint32_t *)param; + // Take the floor of paramLength in 32-bit words + uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); + + // Only copy data if it is specified. We may wish to simply allocate another buffer and get + // the required offset. + if (param) { + // Load the data in PKA RAM + for (i = 0; i < paramLengthInWords; i++) { + // If param address is word aligned, param could be an address on PKA RAM, + // which must be word aligned. Since PKA RAM only word addressable, i.e, it only + // allows reading and writing a word, when param address is word aligned, + // write the data in param as a word in PKA RAM. When param adddress is not word aligned, + // copy the data as bytes in a temp word buffer and write the temp buffer in PKA RAM. + if (IS_WORD_ALIGNED(paramWordAlias)) { + // Since PKA RAM is only word addressable, load the data as word in PKA RAM + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; + } + else { + // Copy as bytes in temp buffer + tempWord = 0; + for (j = 0; j < sizeof(tempWord); j++) { + tempWord |= (param[(i * sizeof(uint32_t)) + j] << (8 * j)); + } + + // Since PKA RAM is only word addressable, load temp buffer as word in PKA RAM + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = tempWord; + } + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. The extra zeros at the end should not matter, as the large + // number is little-endian and thus has no effect. + // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. + // However, we would not have been able to zero-out the extra few most significant + // bytes of the most significant word. That would have resulted in doing maths operations + // on whatever follows param in RAM. + if (paramLength % sizeof(uint32_t)) { + tempWord = 0; + uint8_t j; + + if (IS_WORD_ALIGNED(paramWordAlias)) { + // Load the entire word line of the param remainder + tempWord = paramWordAlias[i]; + // Zero-out all bytes beyond the end of the param + for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { + ((uint8_t *)&tempWord)[j] = 0; + } + } + else { + // Only copy the param remainder bytes. + // The rest of the bytes are already zero initialized. + for (j = 0; j < paramLength % sizeof(uint32_t); j++) { + tempWord |= param[(i * sizeof(uint32_t))+ j] << (8 * j); + } + } + + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = tempWord; + + // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) + paramLengthInWords++; + } + } + + // Update the A, B, C, or D pointer with the offset address of the PKA RAM location + // where the number will be stored. + switch (ptrRegOffset) { + case PKA_O_APTR: + HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; + break; + case PKA_O_BPTR: + HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; + break; + case PKA_O_CPTR: + HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; + break; + case PKA_O_DPTR: + HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; + break; + } + + // Ensure 8-byte alignment of next parameter. + // Returns the offset for the next parameter. + return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module but return a larger offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + // Ensure 16-byte alignment. + return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); +} + +#if defined(__GNUC__) && !defined(__ti__) +// Disable GCC's string operation overflow warning when writing a +// value to memory given by a uint8_t pointer. +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-overflow=2" +#endif +//***************************************************************************** +// +// Writes the result of a large number arithmetic operation to a provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t mswOffset; + uint32_t lswOffset; + uint32_t lengthInWords; + uint32_t i; + uint_fast8_t j; + uint32_t tempWord; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + mswOffset = HWREG(PKA_BASE + PKA_O_MSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { + if (*resultLength) { + if(resultBuf) { + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); + lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + if (mswOffset >= lswOffset) { + lengthInWords = mswOffset - lswOffset; + } + else { + return PKA_STATUS_RESULT_ADDRESS_INCORRECT; + } + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + + if (resultBuf) { + // If resultBuf address is word aligned, it could be an address on PKA RAM, + // which must be word aligned. Since PKA RAM is only word addressable, i.e, it only + // allows reading and writing a word, when resultBuf address is word aligned, + // read the result in PKA RAM as a word directly. When resultBuf adddress is not word aligned, + // use a temp word buffer to store the result from PKA RAM and write the result as bytes + // in resultBuf from the temp buffer. + for (i = 0; i < lengthInWords; i++) { + if (IS_WORD_ALIGNED(resultWordAlias)) { + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + else { + // Since PKA RAM is only word addressable, + // copy the result as word in a temp buffer from PKA RAM + tempWord = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + + // Copy the result from temp buffer as bytes + for (j = 0; j < sizeof(tempWord); j++) { + resultBuf[i * sizeof(tempWord) + j] = ((uint8_t *)&tempWord)[j]; + } + } + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Retrieve the result of a modulo operation or the remainder of a division. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t regMSWVal; + uint32_t lengthInWords; + uint32_t i; + uint_fast8_t j; + uint32_t tempWord; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { + if (*resultLength) { + if(resultBuf) { + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + if (resultBuf) { + // If resultBuf address is word aligned, it could be an address on PKA RAM, + // which must be word aligned. Since PKA RAM is only word addressable, i.e, it only + // allows reading and writing a word, when resultBuf address is word aligned, + // read the result in PKA RAM as a word directly. When resultBuf adddress is not word aligned, + // use a temp word buffer to store the result from PKA RAM and write the result as bytes + // in resultBuf from the temp buffer. + for (i = 0; i < lengthInWords; i++) { + if (IS_WORD_ALIGNED(resultWordAlias)) { + // Since PKA RAM is only word addressable, copy the result as word from PKA RAM + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + else { + // Since PKA RAM is only word addressable, + // copy the result as word in a temp buffer from PKA RAM + tempWord = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Copy the result from temp buffer as bytes + for (j = 0; j < sizeof(tempWord); j++) { + resultBuf[i * sizeof(tempWord) + j] = ((uint8_t *)&tempWord)[j]; + } + } + } + } + + return PKA_STATUS_SUCCESS; +} +#if defined(__GNUC__) && !defined(__ti__) +// GCC: Stop ignoring -Wstringop-overflow=2 +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// +// Writes the resultant curve point of an ECC operation to the provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + uint32_t i = 0; + uint32_t lengthInWordsCeiling = 0; + uint32_t tempWord = 0; + uint_fast8_t j = 0; + uint32_t *xWordAlias = (uint32_t *)curvePointX; + uint32_t *yWordAlias = (uint32_t *)curvePointY; + + // Check for the arguments. + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is completed. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + if (HWREG(PKA_BASE + PKA_O_SHIFT)) { + return PKA_STATUS_FAILURE; + } + + // Check to make sure that the result vector is not the point at infinity. + if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { + return PKA_STATUS_POINT_AT_INFINITY; + } + + if (curvePointX != NULL) { + // Copy the x coordinate value of the result from vector D into + // the curvePoint. + // If curvePointX address is word aligned, it could be an address on PKA RAM, + // which must be word aligned. Since PKA RAM is only word addressable, i.e, it only + // allows reading and writing a word, when curvePointX address is word aligned, + // read the result in PKA RAM as a word directly. When curvePointX adddress is not word aligned, + // use a temp word buffer to store the result from PKA RAM and write the result as bytes + // in curvePointX from the temp buffer. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + // Check for word aligned address in x coordinate buffer + if (IS_WORD_ALIGNED(curvePointX)) { + // Since PKA RAM is only word addressable, copy x coordinate as a word from PKA RAM + xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + else { + // Copy x Coordinate as bytes + // Since PKA RAM is only word addressable, temporarily load + // the entire word line of the coordinate + tempWord = HWREG(resultPKAMemAddr + sizeof(tempWord) * i); + + // Write the bytes to the X coordinate + for (j = 0; j < sizeof(tempWord); j++) { + curvePointX[i * sizeof(tempWord) + j] = ((uint8_t *)&tempWord)[j]; + } + } + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + // Load the entire word line of the coordinate remainder + tempWord = HWREG(resultPKAMemAddr + sizeof(tempWord) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&tempWord)[j]; + } + + } + } + + lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); + + resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); + + if (curvePointY != NULL) { + // Copy the y coordinate value of the result from vector D into + // the curvePoint. + // If curvePointY address is word aligned, it could be an address on PKA RAM, + // which must be word aligned. Since PKA RAM is only word addressable, i.e, it only + // allows reading and writing a word, when curvePointY address is word aligned, + // read the result in PKA RAM as a word directly. When curvePointY adddress is not word aligned, + // use a temp word buffer to store the result from PKA RAM and write the result as bytes + // in curvePointY from the temp buffer. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + // Check for word aligned address in y coordinate buffer + if (IS_WORD_ALIGNED(curvePointY)) { + // Since PKA RAM is only word addressable, copy y coordinate as a word from PKA RAM + yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + else { + // Copy y Coordinate as bytes + // Since PKA RAM is only word addressable, temporarily load + // the entire word line of the coordinate + tempWord = HWREG(resultPKAMemAddr + sizeof(tempWord) * i); + + // Write the bytes to the Y coordinate + for (j = 0; j < sizeof(tempWord); j++) { + curvePointY[i * sizeof(tempWord) + j] = ((uint8_t *)&tempWord)[j]; + } + } + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + // Load the entire word line of the coordinate remainder + tempWord = HWREG(resultPKAMemAddr + sizeof(tempWord) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&tempWord)[j]; + } + } + } + + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Provides the PKA operation status. +// +//***************************************************************************** +uint32_t PKAGetOpsStatus(void) +{ + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { + return PKA_STATUS_OPERATION_BUSY; + } + else { + return PKA_STATUS_OPERATION_RDY; + } +} + +//***************************************************************************** +// +// Check if an array consists only of zeros. +// +//***************************************************************************** +bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + uint8_t arrayBits = 0; + + // We could speed things up by comparing word-wise rather than byte-wise. + // However, this extra overhead is inconsequential compared to running an + // actual PKA operation. Especially ECC operations. + for (i = 0; i < arrayLength; i++) { + arrayBits |= array[i]; + } + + if (arrayBits) { + return false; + } + else { + return true; + } + +} + +//***************************************************************************** +// +// Fill an array with zeros +// +//***************************************************************************** +void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + // Take the floor of paramLength in 32-bit words + uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); + + // Zero-out the array word-wise until i >= arrayLength + for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { + HWREG(array + i) = 0; + } + + // If i != arrayLength, there are some remaining bytes to zero-out + if (arrayLength % sizeof(uint32_t)) { + // Subtract 4 from i, since i has already overshot the array + for (i -= 4; i < arrayLength; i++) { + HWREGB(array + i * sizeof(uint32_t)); + } + } +} + +//***************************************************************************** +// +// Start the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(dividend); + ASSERT(divisor); + ASSERT(resultQuotientMemAddr); + ASSERT(resultRemainderMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); + + // Copy the remainder result vector address location. + if (resultRemainderMemAddr) { + *resultRemainderMemAddr = PKA_RAM_BASE + offset; + } + + // The remainder cannot ever be larger than the divisor. It should fit inside + // a buffer of that size. + offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); + + // Copy the remainder result vector address location. + if (resultQuotientMemAddr) { + *resultQuotientMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the quotient location in PKA RAM + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the quotient of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); +} + +//***************************************************************************** +// +// Get the remainder of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); +} + + +//***************************************************************************** +// +// Start the comparison of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); + + // Set the PKA Function register for the Compare operation + // and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the comparison operation of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpGetResult(void) +{ + uint32_t status; + + // verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Check the COMPARE register. + switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { + case PKA_COMPARE_A_EQUALS_B: + status = PKA_STATUS_EQUAL; + break; + + case PKA_COMPARE_A_GREATER_THAN_B: + status = PKA_STATUS_A_GREATER_THAN_B; + break; + + case PKA_COMPARE_A_LESS_THAN_B: + status = PKA_STATUS_A_LESS_THAN_B; + break; + + default: + status = PKA_STATUS_FAILURE; + break; + } + + return status; +} + +//***************************************************************************** +// +// Start the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to InvMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number modular exponentiation operation. +// +//***************************************************************************** +uint32_t PKABigNumExpModStart(const uint8_t *base, uint32_t baseLength, const uint8_t *exponent, uint32_t exponentLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(base); + ASSERT(exponent); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(exponent, exponentLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + offset = PKAWritePkaParam(base, baseLength, offset, PKA_O_CPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to ExpMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x04 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumExpModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(multiplicand); + ASSERT(multiplier); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); + + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the PKA function to the multiplication and start it. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the results of the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(minuend); + ASSERT(subtrahend); + ASSERT(resultPKAMemAddr); + + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + + +//***************************************************************************** +// +// Start ECC Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT(prime); + ASSERT(a); + ASSERT(b); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Start ECC Montgomery Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(prime); + ASSERT(a); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to Montgomery ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Get the result of ECC Multiplication +// +//***************************************************************************** +uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Start the ECC Addition. +// +//***************************************************************************** +uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(curvePoint1X); + ASSERT(curvePoint1Y); + ASSERT(curvePoint2X); + ASSERT(curvePoint2Y); + ASSERT(prime); + ASSERT(a); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); + offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); + + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); + + // Copy the result vector location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA Function to ECC-ADD and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the ECC Addition +// +//***************************************************************************** +uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Verify a public key against the supplied elliptic curve equation +// +//***************************************************************************** +uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) +{ + uint32_t pkaResult; + uint32_t resultLength; + uint32_t resultAddress = 0; // Assign a value to avoid compiler warnings. + uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); + uint8_t *scratchBuffer2 = scratchBuffer + 512; + + + // Verify X in range [0, prime - 1] + PKABigNumCmpStart(curvePointX, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_X_LARGER_THAN_PRIME; + } + + // Verify Y in range [0, prime - 1] + PKABigNumCmpStart(curvePointY, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_Y_LARGER_THAN_PRIME; + } + + // Verify point on curve + // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P + // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b + + // tmp = X ^ 2 + PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += a + PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp *= x + PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += b + PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + + // tmp2 = tmp % prime to ensure we have no fraction in the division. + // The number will only shrink from here on out. + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp = y^2 + PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp %= prime + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp ?= tmp2 + PKABigNumCmpStart(scratchBuffer, + scratchBuffer2, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_EQUAL) { + return PKA_STATUS_POINT_NOT_ON_CURVE; + } + else { + return PKA_STATUS_SUCCESS; + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.h new file mode 100644 index 00000000..d415eb3c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka.h @@ -0,0 +1,1526 @@ +/****************************************************************************** +* Filename: pka.h +* +* Description: PKA header file. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup pka_api +//! @{ +// +//***************************************************************************** + +#ifndef __PKA_H__ +#define __PKA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_pka.h" +#include "../inc/hw_pka_ram.h" +#include "interrupt.h" +#include "sys_ctrl.h" +#include "debug.h" +#include + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PKAClearPkaRam NOROM_PKAClearPkaRam + #define PKAGetOpsStatus NOROM_PKAGetOpsStatus + #define PKAArrayAllZeros NOROM_PKAArrayAllZeros + #define PKAZeroOutArray NOROM_PKAZeroOutArray + #define PKABigNumModStart NOROM_PKABigNumModStart + #define PKABigNumModGetResult NOROM_PKABigNumModGetResult + #define PKABigNumDivideStart NOROM_PKABigNumDivideStart + #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient + #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder + #define PKABigNumCmpStart NOROM_PKABigNumCmpStart + #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult + #define PKABigNumInvModStart NOROM_PKABigNumInvModStart + #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult + #define PKABigNumExpModStart NOROM_PKABigNumExpModStart + #define PKABigNumExpModGetResult NOROM_PKABigNumExpModGetResult + #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart + #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult + #define PKABigNumAddStart NOROM_PKABigNumAddStart + #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult + #define PKABigNumSubStart NOROM_PKABigNumSubStart + #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult + #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart + #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart + #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult + #define PKAEccAddStart NOROM_PKAEccAddStart + #define PKAEccAddGetResult NOROM_PKAEccAddGetResult + #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart +#endif + + + + +//***************************************************************************** +// +// Function return values +// +//***************************************************************************** +#define PKA_STATUS_SUCCESS 0 //!< Success +#define PKA_STATUS_FAILURE 1 //!< Failure +#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter +#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow +#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros +#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second. +#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second. +#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second. +#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress. +#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress. +#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available +#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0 +#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0 +#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime +#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime +#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve +#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect +#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity + + +//***************************************************************************** +// +// Length in bytes of NISTP224 parameters. +// +//***************************************************************************** +#define NISTP224_PARAM_SIZE_BYTES 28 + +//***************************************************************************** +// +// Length in bytes of NISTP256 parameters. +// +//***************************************************************************** +#define NISTP256_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Length in bytes of NISTP384 parameters. +// +//***************************************************************************** +#define NISTP384_PARAM_SIZE_BYTES 48 + +//***************************************************************************** +// +// Length in bytes of NISTP521 parameters. +// +//***************************************************************************** +#define NISTP521_PARAM_SIZE_BYTES 66 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP256R1 parameters. +// +//***************************************************************************** +#define BrainpoolP256R1_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP384R1 parameters. +// +//***************************************************************************** +#define BrainpoolP384R1_PARAM_SIZE_BYTES 48 + +//***************************************************************************** +// +// Length in bytes of BrainpoolP512R1 parameters. +// +//***************************************************************************** +#define BrainpoolP512R1_PARAM_SIZE_BYTES 64 + +//***************************************************************************** +// +// Length in bytes of Curve25519 parameters. +// +//***************************************************************************** +#define Curve25519_PARAM_SIZE_BYTES 32 + +//***************************************************************************** +// +// Union for parameters that forces 32-bit alignment on the byte array. +// +//***************************************************************************** +typedef union { + uint8_t byte[28]; + uint32_t word[28 / sizeof(uint32_t)]; +} PKA_EccParam224; + +typedef union { + uint8_t byte[32]; + uint32_t word[32 / sizeof(uint32_t)]; +} PKA_EccParam256; + +typedef union { + uint8_t byte[48]; + uint32_t word[48 / sizeof(uint32_t)]; +} PKA_EccParam384; + +typedef union { + uint8_t byte[64]; + uint32_t word[64 / sizeof(uint32_t)]; +} PKA_EccParam512; + +typedef union { + uint8_t byte[68]; + uint32_t word[68 / sizeof(uint32_t)]; +} PKA_EccParam521; + +//***************************************************************************** +// +// Struct to keep points in that forces adjacency of X and Y coordinates in +// memmory. +// +//***************************************************************************** + + +typedef struct PKA_EccPoint224_ { + PKA_EccParam224 x; + PKA_EccParam224 y; +} PKA_EccPoint224; + +typedef struct PKA_EccPoint256_ { + PKA_EccParam256 x; + PKA_EccParam256 y; +} PKA_EccPoint256; + +typedef struct PKA_EccPoint384_ { + PKA_EccParam384 x; + PKA_EccParam384 y; +} PKA_EccPoint384; + +typedef struct PKA_EccPoint512_ { + PKA_EccParam512 x; + PKA_EccParam512 y; +} PKA_EccPoint512; + +typedef struct PKA_EccPoint521_ { + PKA_EccParam521 x; + PKA_EccParam521 y; +} PKA_EccPoint521; + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccPoint224 NISTP224_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP224 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP224 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP224 curve. +// +//***************************************************************************** +extern const PKA_EccParam224 NISTP224_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 NISTP256_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP256 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP256 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP256 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 NISTP256_order; + + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccPoint384 NISTP384_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP384 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP384 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP384 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 NISTP384_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccPoint521 NISTP521_generator; + +//***************************************************************************** +// +//! \brief Prime of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_prime; + + +//***************************************************************************** +// +//! \brief a constant of the NISTP521 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_a; + + +//***************************************************************************** +// +//! \brief b constant of the NISTP521 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_b; + + +//***************************************************************************** +// +//! \brief Order of the NISTP521 curve. +// +//***************************************************************************** +extern const PKA_EccParam521 NISTP521_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 BrainpoolP256R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP256R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP256R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP256R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 BrainpoolP256R1_order; + + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint384 BrainpoolP384R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP384R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP384R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP384R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam384 BrainpoolP384R1_order; + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccPoint512 BrainpoolP512R1_generator; + +//***************************************************************************** +// +//! \brief Prime of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_prime; + + +//***************************************************************************** +// +//! \brief a constant of the BrainpoolP512R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_a; + + +//***************************************************************************** +// +//! \brief b constant of the BrainpoolP512R1 curve when expressed in short +//! Weierstrass form (y^2 = x^3 + a*x + b). +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_b; + + +//***************************************************************************** +// +//! \brief Order of the BrainpoolP512R1 curve. +// +//***************************************************************************** +extern const PKA_EccParam512 BrainpoolP512R1_order; + + + +//***************************************************************************** +// +//! \brief X coordinate of the generator point of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccPoint256 Curve25519_generator; + +//***************************************************************************** +// +//! \brief Prime of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_prime; + + +//***************************************************************************** +// +//! \brief a constant of the Curve25519 curve when expressed in Montgomery +//! form (By^2 = x^3 + a*x^2 + x). +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_a; + + +//***************************************************************************** +// +//! \brief b constant of the Curve25519 curve when expressed in Montgomery +//! form (By^2 = x^3 + a*x^2 + x). +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_b; + + +//***************************************************************************** +// +//! \brief Order of the Curve25519 curve. +// +//***************************************************************************** +extern const PKA_EccParam256 Curve25519_order; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Zeroizes PKA RAM. +//! +//! This function uses the zeroization function in PRCM to clear the PKA RAM. +// +//***************************************************************************** +extern void PKAClearPkaRam(void); + +//***************************************************************************** +// +//! \brief Gets the PKA operation status. +//! +//! This function gets information on whether any PKA operation is in +//! progress or not. This function allows to check the PKA operation status +//! before starting any new PKA operation. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA operation is in progress. +//! - \ref PKA_STATUS_OPERATION_RDY if the PKA operation is not in progress. +// +//***************************************************************************** +extern uint32_t PKAGetOpsStatus(void); + +//***************************************************************************** +// +//! \brief Checks whether and array only consists of zeros +//! +//! \param [in] array is the array to check. +//! +//! \param [in] arrayLength is the length of the array. +//! +//! \return Returns true if the array contains only zeros and false if one +//! or more bits are set. +// +//***************************************************************************** +extern bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength); + +//***************************************************************************** +// +//! \brief Zeros-out an array +//! +//! \param [in] array is the array to zero-out. +//! +//! \param [in] arrayLength is the length of the array. +// +//***************************************************************************** +extern void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength); + +//***************************************************************************** +// +//! \brief Starts a big number modulus operation. +//! +//! This function starts the modulo operation on the big number \c bigNum +//! using the divisor \c modulus. The PKA RAM location where the result +//! will be available is stored in \c resultPKAMemAddr. +//! +//! \param [in] bigNum is the pointer to the big number on which modulo operation +//! needs to be carried out. +//! +//! \param [in] bigNumLength is the size of the big number \c bigNum in bytes. +//! +//! \param [in] modulus is the pointer to the divisor. +//! +//! \param [in] modulusLength is the size of the divisor \c modulus in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumModGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the big number modulus operation. +//! +//! This function gets the result of the big number modulus operation which was +//! previously started using the function PKABigNumModStart(). +//! The function will zero-out \c resultBuf prior to copying in the result of +//! the modulo operation. +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumModStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumModStart() +// +//***************************************************************************** +extern uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts a big number divide operation. +//! +//! This function starts the dive operation on the big number \c bigNum +//! using the \c divisor. The PKA RAM location where the result +//! will be available is stored in \c resultPKAMemAddr. +//! +//! \param [in] dividend is the pointer to the big number to be divided. +//! +//! \param [in] dividendLength is the size of the big number \c dividend in bytes. +//! +//! \param [in] divisor is the pointer to the divisor. +//! +//! \param [in] divisorLength is the size of the \c divisor in bytes. +//! +//! \param [out] resultQuotientMemAddr is the pointer to the quotient vector location +//! which will be set by this function. +//! +//! \param [out] resultRemainderMemAddr is the pointer to the remainder vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumDivideGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideStart(const uint8_t *dividend, + uint32_t dividendLength, + const uint8_t *divisor, + uint32_t divisorLength, + uint32_t *resultQuotientMemAddr, + uint32_t *resultRemainderMemAddr); + +//***************************************************************************** +// +//! \brief Gets the quotient of the big number divide operation. +//! +//! This function gets the quotient of the big number divide operation which was +//! previously started using the function PKABigNumDivideStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultQuotientMemAddr is the address of the result location which +//! was provided by the start function PKABigNumDivideStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumDivideStart() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr); + +//***************************************************************************** +// +//! \brief Gets the remainder of the big number divide operation. +//! +//! This function gets the remainder of the big number divide operation which was +//! previously started using the function PKABigNumDivideStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to +//! be stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultRemainderMemAddr is the address of the result location which +//! was provided by the start function PKABigNumDivideStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length +//! of the result. +//! +//! \sa PKABigNumDivideStart() +// +//***************************************************************************** +extern uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr); + +//***************************************************************************** +// +//! \brief Starts the comparison of two big numbers. +//! +//! This function starts the comparison of two big numbers pointed by +//! \c bigNum1 and \c bigNum2. +//! +//! \note \c bigNum1 and \c bigNum2 must have same size. +//! +//! \param [in] bigNum1 is the pointer to the first big number. +//! +//! \param [in] bigNum2 is the pointer to the second big number. +//! +//! \param [in] length is the size of the big numbers in bytes. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumCmpGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length); + +//***************************************************************************** +// +//! \brief Gets the result of the comparison operation of two big numbers. +//! +//! This function provides the results of the comparison of two big numbers +//! which was started using the PKABigNumCmpStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_OPERATION_BUSY if the operation is in progress. +//! - \ref PKA_STATUS_SUCCESS if the two big numbers are equal. +//! - \ref PKA_STATUS_A_GREATER_THAN_B if the first number is greater than the second. +//! - \ref PKA_STATUS_A_LESS_THAN_B if the first number is less than the second. +//! +//! \sa PKABigNumCmpStart() +// +//***************************************************************************** +extern uint32_t PKABigNumCmpGetResult(void); + +//***************************************************************************** +// +//! \brief Starts a big number inverse modulo operation. +//! +//! This function starts the inverse modulo operation on \c bigNum +//! using the divisor \c modulus. +//! +//! \param [in] bigNum is the pointer to the buffer containing the big number +//! (dividend). +//! +//! \param [in] bigNumLength is the size of the \c bigNum in bytes. +//! +//! \param [in] modulus is the pointer to the buffer containing the divisor. +//! +//! \param [in] modulusLength is the size of the divisor in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumInvModGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); + + +//***************************************************************************** +// +//! \brief Gets the result of the big number inverse modulo operation. +//! +//! This function gets the result of the big number inverse modulo operation +//! previously started using the function PKABigNumInvModStart(). +//! The function will zero-out \c resultBuf prior to copying in the result of +//! the inverse modulo operation. +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to be +//! stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumInvModStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! than the result. +//! +//! \sa PKABigNumInvModStart() +// +//***************************************************************************** +extern uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts a big number modular exponentiation operation. +//! +//! This function starts the exponentiation operation on \c base with +//! \c exponent and modulo \c modulus. +//! +//! \param [in] base is the pointer to the buffer containing the big number +//! to exponentiate. +//! +//! \param [in] baseLength is the size of the \c base in bytes. +//! +//! \param [in] exponent is the pointer to the buffer containing the big number +//! that exponentiates. +//! +//! \param [in] exponentLength is the size of the \c exponent in bytes. + +//! \param [in] modulus is the pointer to the buffer containing the divisor. +//! +//! \param [in] modulusLength is the size of the divisor in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumExpModGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumExpModStart(const uint8_t *base, uint32_t baseLength, const uint8_t *exponent, uint32_t exponentLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the big number modular exponentiation operation. +//! +//! This function gets the result of the big number modular exponentiation +//! operation previously started using the function PKABigNumExpModStart(). +//! The function will zero-out \c resultBuf prior to copying in the result of +//! the modular exponentiation operation. +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to be +//! stored. +//! +//! \param [in] length is the size of the provided buffer in bytes. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumExpModStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! than the result. +//! +//! \sa PKABigNumExpModStart() +// +//***************************************************************************** +extern uint32_t PKABigNumExpModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts the multiplication of two big numbers. +//! +//! \param [in] multiplicand is the pointer to the buffer containing the big +//! number multiplicand. +//! +//! \param [in] multiplicandLength is the size of the multiplicand in bytes. +//! +//! \param [in] multiplier is the pointer to the buffer containing the big +//! number multiplier. +//! +//! \param [in] multiplierLength is the size of the multiplier in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumMultGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the big number multiplication. +//! +//! This function gets the result of the multiplication of two big numbers +//! operation previously started using the function PKABigNumMultiplyStart(). +//! +//! \param [out] resultBuf is the pointer to buffer where the result needs to be +//! stored. +//! +//! \param [in, out] resultLength is the address of the variable containing the length of the +//! buffer in bytes. After the operation, the actual length of the resultant is stored +//! at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumMultiplyStart(). +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumMultiplyStart() +// +//***************************************************************************** +extern uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts the addition of two big numbers. +//! +//! \param [in] bigNum1 is the pointer to the buffer containing the first +//! big number. +//! +//! \param [in] bigNum1Length is the size of the first big number in bytes. +//! +//! \param [in] bigNum2 is the pointer to the buffer containing the second +//! big number. +//! +//! \param [in] bigNum2Length is the size of the second big number in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumAddGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the addition operation on two big numbers. +//! +//! \param [out] resultBuf is the pointer to buffer where the result +//! needs to be stored. +//! +//! \param [in, out] resultLength is the address of the variable containing +//! the length of the buffer. After the operation the actual length of the +//! resultant is stored at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumAddStart(). +//! +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumAddStart() +// +//***************************************************************************** +extern uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts the subtraction of one big number from another. +//! +//! \param [in] minuend is the pointer to the buffer containing the big number +//! to be subtracted from. +//! +//! \param [in] minuendLength is the size of the minuend in bytes. +//! +//! \param [in] subtrahend is the pointer to the buffer containing the big +//! number to subtract from the \c minuend. +//! +//! \param [in] subtrahendLength is the size of the subtrahend in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKABigNumSubGetResult() +// +//***************************************************************************** +extern uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the subtraction operation on two big numbers. +//! +//! \param [out] resultBuf is the pointer to buffer where the result +//! needs to be stored. +//! +//! \param [in, out] resultLength is the address of the variable containing +//! the length of the buffer. After the operation the actual length of the +//! resultant is stored at this address. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKABigNumAddStart(). +//! +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less +//! then the length of the result. +//! +//! \sa PKABigNumSubStart() +// +//***************************************************************************** +extern uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts ECC multiplication. +//! +//! \param [in] scalar is pointer to the buffer containing the scalar +//! value to be multiplied. +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] curvePointY is the pointer to the buffer containing the +//! Y coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] b is the b constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccMultiplyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccMultiplyStart(const uint8_t *scalar, + const uint8_t *curvePointX, + const uint8_t *curvePointY, + const uint8_t *prime, + const uint8_t *a, + const uint8_t *b, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Starts ECC Montgomery multiplication. +//! +//! \param [in] scalar is pointer to the buffer containing the scalar +//! value to be multiplied. +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to be multiplied. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccMultiplyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, + const uint8_t *curvePointX, + const uint8_t *prime, + const uint8_t *a, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of ECC multiplication +//! +//! This function gets the result of ECC point multiplication operation on the +//! EC point and the scalar value, previously started using the function +//! PKAEccMultiplyStart(). +//! +//! \param [out] curvePointX is the pointer to the structure where the X coordinate +//! of the resultant EC point will be stored. +//! +//! \param [out] curvePointY is the pointer to the structure where the Y coordinate +//! of the resultant EC point will be stored. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKAEccMultiplyStart(). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing +//! the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! +//! \sa PKAEccMultiplyStart() +// +//***************************************************************************** +extern uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); + +//***************************************************************************** +// +//! \brief Starts the ECC addition. +//! +//! \param [in] curvePoint1X is the pointer to the buffer containing the +//! X coordinate of the first elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint1Y is the pointer to the buffer containing the +//! Y coordinate of the first elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint2X is the pointer to the buffer containing the +//! X coordinate of the second elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] curvePoint2Y is the pointer to the buffer containing the +//! Y coordinate of the second elliptic curve point to be added. +//! The point must be on the given curve. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in short Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \param [out] resultPKAMemAddr is the pointer to the result vector location +//! which will be set by this function. +//! +//!\return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing +//! some other operation. +//! +//! \sa PKAEccAddGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, + const uint8_t *curvePoint1Y, + const uint8_t *curvePoint2X, + const uint8_t *curvePoint2Y, + const uint8_t *prime, + const uint8_t *a, + uint32_t length, + uint32_t *resultPKAMemAddr); + +//***************************************************************************** +// +//! \brief Gets the result of the ECC addition +//! +//! This function gets the result of ECC point addition operation on the +//! on the two given EC points, previously started using the function +//! PKAEccAddStart(). +//! +//! \param [out] curvePointX is the pointer to the structure where the X coordinate +//! of the resultant EC point will be stored. +//! +//! \param [out] curvePointY is the pointer to the structure where the Y coordinate +//! of the resultant EC point will be stored. +//! +//! \param [in] resultPKAMemAddr is the address of the result location which +//! was provided by the start function PKAEccAddGetResult(). +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. +//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! +//! \sa PKAEccAddStart() +// +//***************************************************************************** +extern uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); + + +//***************************************************************************** +// +//! \brief Begins the validation of a public key against a Short-Weierstrass curve +//! +//! This function validates a public key against a curve. +//! After performing multiple smaller PKA operations in polling mode, +//! it starts an ECC scalar multiplication. +//! +//! The function verifies that: +//! - X and Y are in the range [1, prime - 1] +//! - The point is not the point at infinity +//! - X and Y satisfy the Short-Weierstrass curve equation Y^2 = X^3 + a*X + b mod P +//! - Multiplying the point by the order of the curve yields the point at infinity +//! +//! \param [in] curvePointX is the pointer to the buffer containing the +//! X coordinate of the elliptic curve point to verify. +//! +//! \param [in] curvePointY is the pointer to the buffer containing the +//! Y coordinate of the elliptic curve point to verify. +//! +//! \param [in] prime is the prime of the curve. +//! +//! \param [in] a is the a constant of the curve when the curve equation is expressed +//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] b is the b constant of the curve when the curve equation is expressed +//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). +//! +//! \param [in] order is the order of the curve. +//! +//! \param [in] length is the length of the curve parameters in bytes. +//! +//! \return Returns a status code. +//! - \ref PKA_STATUS_SUCCESS if the operation is successful. +//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. +//! - \ref PKA_STATUS_FAILURE if the operation is not successful. +//! - \ref PKA_STATUS_X_ZERO if X is zero. +//! - \ref PKA_STATUS_Y_ZERO if Y is zero. +//! - \ref PKA_STATUS_X_LARGER_THAN_PRIME if X is larger than the curve prime +//! - \ref PKA_STATUS_Y_LARGER_THAN_PRIME if Y is larger than the curve prime +//! - \ref PKA_STATUS_POINT_NOT_ON_CURVE if X and Y do not satisfy the curve equation +//! +//! \sa PKAEccVerifyPublicKeyGetResult() +// +//***************************************************************************** +extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, + const uint8_t *curvePointY, + const uint8_t *prime, + const uint8_t *a, + const uint8_t *b, + const uint8_t *order, + uint32_t length); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PKAClearPkaRam + #undef PKAClearPkaRam + #define PKAClearPkaRam ROM_PKAClearPkaRam + #endif + #ifdef ROM_PKAGetOpsStatus + #undef PKAGetOpsStatus + #define PKAGetOpsStatus ROM_PKAGetOpsStatus + #endif + #ifdef ROM_PKAArrayAllZeros + #undef PKAArrayAllZeros + #define PKAArrayAllZeros ROM_PKAArrayAllZeros + #endif + #ifdef ROM_PKAZeroOutArray + #undef PKAZeroOutArray + #define PKAZeroOutArray ROM_PKAZeroOutArray + #endif + #ifdef ROM_PKABigNumModStart + #undef PKABigNumModStart + #define PKABigNumModStart ROM_PKABigNumModStart + #endif + #ifdef ROM_PKABigNumModGetResult + #undef PKABigNumModGetResult + #define PKABigNumModGetResult ROM_PKABigNumModGetResult + #endif + #ifdef ROM_PKABigNumDivideStart + #undef PKABigNumDivideStart + #define PKABigNumDivideStart ROM_PKABigNumDivideStart + #endif + #ifdef ROM_PKABigNumDivideGetQuotient + #undef PKABigNumDivideGetQuotient + #define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient + #endif + #ifdef ROM_PKABigNumDivideGetRemainder + #undef PKABigNumDivideGetRemainder + #define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder + #endif + #ifdef ROM_PKABigNumCmpStart + #undef PKABigNumCmpStart + #define PKABigNumCmpStart ROM_PKABigNumCmpStart + #endif + #ifdef ROM_PKABigNumCmpGetResult + #undef PKABigNumCmpGetResult + #define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult + #endif + #ifdef ROM_PKABigNumInvModStart + #undef PKABigNumInvModStart + #define PKABigNumInvModStart ROM_PKABigNumInvModStart + #endif + #ifdef ROM_PKABigNumInvModGetResult + #undef PKABigNumInvModGetResult + #define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult + #endif + #ifdef ROM_PKABigNumExpModStart + #undef PKABigNumExpModStart + #define PKABigNumExpModStart ROM_PKABigNumExpModStart + #endif + #ifdef ROM_PKABigNumExpModGetResult + #undef PKABigNumExpModGetResult + #define PKABigNumExpModGetResult ROM_PKABigNumExpModGetResult + #endif + #ifdef ROM_PKABigNumMultiplyStart + #undef PKABigNumMultiplyStart + #define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart + #endif + #ifdef ROM_PKABigNumMultGetResult + #undef PKABigNumMultGetResult + #define PKABigNumMultGetResult ROM_PKABigNumMultGetResult + #endif + #ifdef ROM_PKABigNumAddStart + #undef PKABigNumAddStart + #define PKABigNumAddStart ROM_PKABigNumAddStart + #endif + #ifdef ROM_PKABigNumAddGetResult + #undef PKABigNumAddGetResult + #define PKABigNumAddGetResult ROM_PKABigNumAddGetResult + #endif + #ifdef ROM_PKABigNumSubStart + #undef PKABigNumSubStart + #define PKABigNumSubStart ROM_PKABigNumSubStart + #endif + #ifdef ROM_PKABigNumSubGetResult + #undef PKABigNumSubGetResult + #define PKABigNumSubGetResult ROM_PKABigNumSubGetResult + #endif + #ifdef ROM_PKAEccMultiplyStart + #undef PKAEccMultiplyStart + #define PKAEccMultiplyStart ROM_PKAEccMultiplyStart + #endif + #ifdef ROM_PKAEccMontgomeryMultiplyStart + #undef PKAEccMontgomeryMultiplyStart + #define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart + #endif + #ifdef ROM_PKAEccMultiplyGetResult + #undef PKAEccMultiplyGetResult + #define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult + #endif + #ifdef ROM_PKAEccAddStart + #undef PKAEccAddStart + #define PKAEccAddStart ROM_PKAEccAddStart + #endif + #ifdef ROM_PKAEccAddGetResult + #undef PKAEccAddGetResult + #define PKAEccAddGetResult ROM_PKAEccAddGetResult + #endif + #ifdef ROM_PKAEccVerifyPublicKeyWeierstrassStart + #undef PKAEccVerifyPublicKeyWeierstrassStart + #define PKAEccVerifyPublicKeyWeierstrassStart ROM_PKAEccVerifyPublicKeyWeierstrassStart + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PKA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka_doc.h new file mode 100644 index 00000000..4cdd5452 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pka_doc.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* Filename: pka_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup pka_api +//! @{ +//! \section sec_pka Introduction +//! +//! The PKA (Public Key Accelerator) API provides access to the Large Number +//! Engine (LNME). The LNME allows for efficient math operations on numbers +//! larger than those that fit within the ALU of the system CPU. It is significantly faster +//! to perform these operations using the LNME than implementing the same +//! functionality in software using regular word-wise math operations. While the +//! LNME runs in the background, the system CPU may perform other operations +//! or be turned off. +//! +//! The LNME supports both primitive math operations and serialized primitive +//! operations (sequencer operations). +//! - Addition +//! - Multiplication +//! - Comparison +//! - Modulo +//! - Inverse Modulo +//! - ECC Point Addition (including point doubling) +//! - ECC Scalar Multiplication +//! +//! These primitives and sequencer operations can be used to implement various +//! public key encryption schemes. +//! It is possible to implement the following schemes using the operations mentioned above: +//! - RSA encryption and decryption +//! - RSA sign and verify +//! - DHE (Diffie-Hellman Key Exchange) +//! - ECDH (Elliptic Curve Diffie-Hellman Key Exchange) +//! - ECDSA (Elliptic Curve Digital Signature Algorithm) +//! - ECIES (Elliptic Curve Integrated Encryption Scheme) +//! +//! The DriverLib PKA functions copy the relevant parameters into the dedicated +//! PKA RAM. The LNME requires these parameters be present and correctly +//! formatted in the PKA RAM and not system RAM. They are copied word-wise as +//! the PKA RAM does not support byte-wise access. The CPU handles the alignment differences +//! during the memory copy operation. Forcing buffer alignment in system RAM results +//! in a significant speedup of the copy operation compared to unaligned buffers. +//! +//! When the operation completes, the result is copied back into +//! a buffer in system RAM specified by the application. The PKA RAM is then cleared +//! to prevent sensitive keying material from remaining in PKA RAM. +//! +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.c new file mode 100644 index 00000000..ca436ea1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.c @@ -0,0 +1,690 @@ +/****************************************************************************** +* Filename: prcm.c +* +* Description: Driver for the PRCM. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "prcm.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPowerDomainsAllOff + #define PRCMPowerDomainsAllOff NOROM_PRCMPowerDomainsAllOff + #undef PRCMPowerDomainsAllOn + #define PRCMPowerDomainsAllOn NOROM_PRCMPowerDomainsAllOn + #undef PRCMDeepSleep + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGR), // Index 0 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGR), // Index 1 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGR), // Index 2 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGR), // Index 3 + (PRCM_BASE + PRCM_O_SECDMACLKGR), // Index 4 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPIOCLKGR), // Index 5 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKGR) // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGS), // Index 0 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGS), // Index 1 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGS), // Index 2 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGS), // Index 3 + (PRCM_BASE + PRCM_O_SECDMACLKGS), // Index 4 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPIOCLKGS), // Index 5 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKGS) // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGDS), // Index 0 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGDS), // Index 1 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGDS), // Index 2 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGDS), // Index 3 + (PRCM_BASE + PRCM_O_SECDMACLKGDS), // Index 4 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPIOCLKGDS), // Index 5 + (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKGDS) // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +//***************************************************************************** +// +// Configure the infrastructure clock. +// +//***************************************************************************** +void +PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) +{ + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +//***************************************************************************** +// +// Use this function to get the infrastructure clock configuration +// +//***************************************************************************** +uint32_t +PRCMInfClockConfigureGet(uint32_t ui32PowerMode) +{ + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + + +//***************************************************************************** +// +// Configure the audio clock generation +// +//***************************************************************************** +void +PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) +{ + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clock generation with manual setting of clock divider. +// +//***************************************************************************** +void +PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +//***************************************************************************** +// +// Configure the audio clocks for I2S module +// +//***************************************************************************** +void +PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv) +{ + // Check the arguments. + ASSERT(ui8SamplingEdge == PRCM_I2S_WCLK_NEG_EDGE || + ui8SamplingEdge == PRCM_I2S_WCLK_POS_EDGE); + ASSERT(ui8WCLKPhase == PRCM_WCLK_SINGLE_PHASE || + ui8WCLKPhase == PRCM_WCLK_DUAL_PHASE || + ui8WCLKPhase == PRCM_WCLK_USER_DEF); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity and enable it. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | + (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | + (1 << PRCM_I2SCLKCTL_EN_S ); +} + +//***************************************************************************** +// +// Configure the clocks as "internally generated". +// +//***************************************************************************** +void PRCMAudioClockInternalSource(void) +{ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SBCLKSEL) = PRCM_I2SBCLKSEL_SRC; +} + +//***************************************************************************** +// +// Configure the clocks as "externally generated". +// +//***************************************************************************** +void PRCMAudioClockExternalSource(void) +{ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SBCLKSEL) = 0; +} + +//***************************************************************************** +// +// Turn power on in power domains in the MCU domain +// +//***************************************************************************** +void +PRCMPowerDomainOn(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1CPU ) = 1; + } +} + +//***************************************************************************** +// +// Turn off a specific power domain +// +//***************************************************************************** +void +PRCMPowerDomainOff(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. + // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. + ASSERT(!(ui32Domains & 0x00010000)); + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1CPU ) = 0; + } +} + +//***************************************************************************** +// +// Enables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in Run mode +// +//***************************************************************************** +void +PRCMPeripheralRunDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in sleep mode +// +//***************************************************************************** +void +PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Enables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Disables a peripheral in deep-sleep mode +// +//***************************************************************************** +void +PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) +{ + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +//***************************************************************************** +// +// Return PRCM_DOMAIN_POWER_OFF if all power domains are off +// +//***************************************************************************** +uint32_t +PRCMPowerDomainsAllOff(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = false; + ui32StatusRegister0 = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus || + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus || (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus || (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +//***************************************************************************** +// +// Return PRCM_DOMAIN_POWER_ON if all power domains are on +// +//***************************************************************************** +uint32_t +PRCMPowerDomainsAllOn(uint32_t ui32Domains) +{ + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +//***************************************************************************** +// +// Put the processor into deep-sleep mode +// +//***************************************************************************** +void +PRCMDeepSleep(void) +{ + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.h new file mode 100644 index 00000000..c466d373 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/prcm.h @@ -0,0 +1,1259 @@ +/****************************************************************************** +* Filename: prcm.h +* +* Description: Defines and prototypes for the PRCM +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup prcm_api +//! @{ +// +//***************************************************************************** + +#ifndef __PRCM_H__ +#define __PRCM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_memmap_common.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_rtc.h" +#include "interrupt.h" +#include "debug.h" +#include "cpu.h" + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet + #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet + #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride + #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource + #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource + #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn + #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff + #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable + #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable + #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable + #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable + #define PRCMPowerDomainsAllOff NOROM_PRCMPowerDomainsAllOff + #define PRCMPowerDomainsAllOn NOROM_PRCMPowerDomainsAllOn + #define PRCMDeepSleep NOROM_PRCMDeepSleep +#endif + +//***************************************************************************** +// +// Defines for the different System CPU power modes. +// +//***************************************************************************** +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 + +//***************************************************************************** +// +// Defines used for setting the clock division factors +// +//***************************************************************************** +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 + +//***************************************************************************** +// +// Defines used for enabling and disabling domains and memories in the MCU +// domain +// +//***************************************************************************** +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for + // clock/power control. +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for + // clock/power control. +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for + // clock/power control. +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power + // control. +#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ + 0x00020010 // For function PRCMPowerDomainOff() it is an option to + // select that VIMS power domain shall not power up + // during the next wake up from uLDO (VIMS_MODE=0b10). +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power + // control. +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock + // control. +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for + // clock/power control. +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU + // domain. +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be + // powered down. + +//***************************************************************************** +// +// Defines for setting up the audio interface in the I2S module. +// +//***************************************************************************** +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 + +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 + +//***************************************************************************** +// +// Defines used for enabling and disabling peripheral modules in the MCU domain +// bits[11:8] Defines the index into the register offset constant tables: +// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs +// bits[4:0] Defines the bit position within the register pointed on in [11:8] +// +//***************************************************************************** +#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1 +#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module +#define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module +#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a peripheral identifier. +//! +//! This function determines if a peripheral identifier is valid. +//! +//! \param ui32Peripheral is the peripheral identifier. +//! +//! \return Returns status of peripheral identifier: +//! - \b true : Peripheral identifier is valid. +//! - \b false : Peripheral identifier is invalid. +// +//***************************************************************************** +static bool +PRCMPeripheralValid(uint32_t ui32Peripheral) +{ + return((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_UART1) || + (ui32Peripheral == PRCM_PERIPH_PKA) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || + (ui32Peripheral == PRCM_PERIPH_I2S)); +} +#endif + +//***************************************************************************** +// +//! \brief Configure the infrastructure clock. +//! +//! Each System CPU power mode has its own infrastructure clock division factor. This +//! function can be used for setting up the division factor for the +//! infrastructure clock in the available power modes for the System CPU. The +//! infrastructure clock is used for all internal logic in the PRCM, and is +//! always running as long as power is on in the MCU voltage domain. +//! This can be enabled and disabled from the AON Wake Up Controller. +//! +//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2. +//! +//! \param ui32ClkDiv determines the division ratio for the infrastructure +//! clock when the device is in the specified mode. +//! Allowed division factors for all three System CPU power modes are: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! \param ui32PowerMode determines the System CPU operation mode for which to +//! modify the clock division factor. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, + uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Use this function to get the infrastructure clock configuration. +//! +//! \param ui32PowerMode determines which System CPU power mode to return the +//! infrastructure clock division ratio for. +//! The three allowed power modes are: +//! - \ref PRCM_RUN_MODE +//! - \ref PRCM_SLEEP_MODE +//! - \ref PRCM_DEEP_SLEEP_MODE +//! +//! \return Returns the infrastructure clock division factor for the specified +//! power mode. +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_32 +//! +//! \sa \ref PRCMInfClockConfigureSet(). +// +//***************************************************************************** +extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode); + +//***************************************************************************** +// +//! \brief Assert or de-assert a request for the uLDO. +//! +//! Use this function to request to switch to the micro Low Voltage Dropout +//! regulator (uLDO). The uLDO has a much lower capacity for supplying power +//! to the system. It is therefore imperative and solely the programmers +//! responsibility to ensure that a sufficient amount of peripheral modules +//! have been turned of before requesting a switch to the uLDO. +//! +//! \note Asserting this bit has no effect until: +//! 1. FLASH has accepted to be powered down +//! 2. Deepsleep must be asserted +//! +//! \param ui32Enable +//! - 0 : Disable uLDO request +//! - 1 : Enable uLDO request +//! +//! \return None +//! +//! \sa \ref PRCMDeepSleep() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMMcuUldoConfigure(uint32_t ui32Enable) +{ + // Enable or disable the uLDO request signal. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VDCTL) = ui32Enable; +} + +//***************************************************************************** +// +//! \brief Setup the clock division factor for the GP-Timer domain. +//! +//! Use this function to set up the clock division factor on the GP-Timer. +//! +//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when +//! it is slower than PRCM_GPTCLKDIV_RATIO setting. +//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. +//! Note that the register will contain the written content even though the setting is +//! faster than PRCM_GPTCLKDIV_RATIO setting. +//! +//! \note For change to take effect, \ref PRCMLoadSet() needs to be called +//! +//! \param clkDiv is the division factor to set. +//! The argument must be only one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \return None +//! +//! \sa \ref PRCMGPTimerClockDivisionGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +{ + ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + + HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV ) = clkDiv; +} + +//***************************************************************************** +// +//! \brief Get the clock division factor for the GP-Timer domain. +//! +//! Use this function to get the clock division factor set for the GP-Timer. +//! +//! \return Returns one of the following values: +//! - \ref PRCM_CLOCK_DIV_1 +//! - \ref PRCM_CLOCK_DIV_2 +//! - \ref PRCM_CLOCK_DIV_4 +//! - \ref PRCM_CLOCK_DIV_8 +//! - \ref PRCM_CLOCK_DIV_16 +//! - \ref PRCM_CLOCK_DIV_32 +//! - \ref PRCM_CLOCK_DIV_64 +//! - \ref PRCM_CLOCK_DIV_128 +//! - \ref PRCM_CLOCK_DIV_256 +//! +//! \sa \ref PRCMGPTimerClockDivisionSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PRCMGPTimerClockDivisionGet( void ) +{ + return ( HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV )); +} + + +//***************************************************************************** +// +//! \brief Enable the audio clock generation. +//! +//! Use this function to enable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockEnable(void) +{ + // Enable the audio clock generation. + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the audio clock generation. +//! +//! Use this function to disable the audio clock generation. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMAudioClockDisable(void) +{ + // Disable the audio clock generation + HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Configure the audio clock generation. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the sample rate when using internal audio clock +//! generation for the I2S module. +//! +//! \note While other clocks are possible, the stability of the four sample +//! rates defined here are only guaranteed if the clock input to the I2S module +//! is 48MHz. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32SampleRate is the desired audio clock sample rate. +//! The supported sample rate configurations are: +//! - \ref I2S_SAMPLE_RATE_16K +//! - \ref I2S_SAMPLE_RATE_24K +//! - \ref I2S_SAMPLE_RATE_32K +//! - \ref I2S_SAMPLE_RATE_48K +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSetOverride() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, + uint32_t ui32SampleRate); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clock generation with manual setting of clock divider. +//! +//! \deprecated This function will be removed in a future release. +//! +//! Use this function to set the audio clock divider values manually. +//! +//! \note See hardware documentation before setting audio clock dividers manually. +//! +//! \param ui32ClkConfig is the audio clock configuration. +//! The parameter is a bitwise OR'ed value consisting of: +//! - Phase +//! - \ref PRCM_WCLK_SINGLE_PHASE +//! - \ref PRCM_WCLK_DUAL_PHASE +//! - Clock polarity +//! - \ref PRCM_WCLK_NEG_EDGE +//! - \ref PRCM_WCLK_POS_EDGE +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockConfigSet() +// +//***************************************************************************** +#ifndef DEPRECATED +extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, + uint32_t ui32BitDiv, uint32_t ui32WordDiv); +#endif + +//***************************************************************************** +// +//! \brief Configure the audio clocks for I2S module. +//! +//! \note See hardware documentation before setting audio clock dividers. +//! This is user's responsability to provide valid clock dividers. +//! +//! \param ui8SamplingEdge Define the clock polarity: +//! - \ref PRCM_I2S_WCLK_NEG_EDGE +//! - \ref PRCM_I2S_WCLK_POS_EDGE +//! \param ui8WCLKPhase Define I2S phase used +//! - PRCM_I2S_WCLK_SINGLE_PHASE +//! - PRCM_I2S_WCLK_DUAL_PHASE +//! - PRCM_I2S_WCLK_USER_DEF +//! \param ui32MstDiv is the desired master clock divider. +//! \param ui32BitDiv is the desired bit clock divider. +//! \param ui32WordDiv is the desired word clock divider. +//! +//! \return None +//! +//***************************************************************************** +extern void PRCMAudioClockConfigOverride + (uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be internally generated. +//! +//! Use this function to set the audio clocks as internal. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockExternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockInternalSource(void); + +//***************************************************************************** +// +//! \brief Configure the audio clocks to be externally generated. +//! +//! Use this function to set the audio clocks as external. +//! +//! \return None +//! +//! \sa \ref PRCMAudioClockInternalSource() +// +//***************************************************************************** +extern void PRCMAudioClockExternalSource(void); + +//***************************************************************************** +// +//! \brief Use this function to synchronize the load settings. +//! +//! Most of the clock settings in the PRCM module should be updated +//! synchronously. This is ensured by the implementation of a load registers +//! that, when written to, will let the previous written update values for all +//! the relevant registers propagate through to hardware. +//! +//! The functions that require a synchronization of the clock settings are: +//! - \ref PRCMAudioClockConfigSet() +//! - \ref PRCMAudioClockConfigSetOverride() +//! - \ref PRCMAudioClockDisable() +//! - \ref PRCMDomainEnable() +//! - \ref PRCMDomainDisable() +//! - \ref PRCMPeripheralRunEnable() +//! - \ref PRCMPeripheralRunDisable() +//! - \ref PRCMPeripheralSleepEnable() +//! - \ref PRCMPeripheralSleepDisable() +//! - \ref PRCMPeripheralDeepSleepEnable() +//! - \ref PRCMPeripheralDeepSleepDisable() +//! +//! \return None +//! +//! \sa \ref PRCMLoadGet() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMLoadSet(void) +{ + // Enable the update of all load related registers. + HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD; +} + +//***************************************************************************** +// +//! \brief Check if any of the load sensitive register has been updated. +//! +//! \return Returns status of the load sensitive register: +//! - \c true : No registers have changed since the last load. +//! - \c false : Any register has changed. +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMLoadGet(void) +{ + // Return the load status. + return ((HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Enable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to enable. +//! The independent clock domains inside the MCU voltage domain which can be +//! configured are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainEnable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Enable the clock domain(s). + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; + } +} + +//***************************************************************************** +// +//! \brief Disable clock domains in the MCU voltage domain. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note Clocks will only be running if the domain is powered. +//! +//! \param ui32Domains is a bit mask containing the clock domains to disable. +//! The independent clock domains inside the MCU voltage domain are: +//! - \ref PRCM_DOMAIN_RFCORE +//! - \ref PRCM_DOMAIN_VIMS +//! +//! \return None +//! +//! \sa PRCMDomainEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMDomainDisable(uint32_t ui32Domains) +{ + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Disable the power domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = 0x0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = 0x0; + } +} + +//***************************************************************************** +// +//! \brief Turn power on in power domains in the MCU domain. +//! +//! Use this function to turn on power domains inside the MCU voltage domain. +//! +//! Power on and power off request has different implications for the +//! different power domains. +//! - RF Core power domain: +//! - Power On : Domain is on or in the process of turning on. +//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third +//! option for the RF Core is to power down when the it is idle. +//! This can be set using \b PRCMRfPowerDownWhenIdle() +//! - SERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - PERIPHERIAL power domain: +//! - Power on : Domain is powered on. +//! - Power off : Domain is powered off. +//! - VIMS power domain: +//! - Power On : Domain is powered if Bus domain is powered. +//! - Power Off : Domain is only powered when CPU domain is on. +//! - BUS power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on. +//! - CPU power domain: +//! - Power On : Domain is on. +//! - Power Off : Domain is powering down if System CPU is idle. This will also +//! initiate a power down of the SRAM and BUS power domains, unless +//! RF Core is requesting them to be on. +//! +//! \note After a call to this function the status of the power domain should be checked +//! using either \ref PRCMPowerDomainsAllOff() or \ref PRCMPowerDomainsAllOn(). +//! Any write operation to a power domain which is still not operational can +//! result in unexpected behavior. +//! +//! \param ui32Domains determines which power domains to turn on. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOn(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Turn off a specific power domain. +//! +//! Use this function to power down domains inside the MCU voltage domain. +//! +//! \note For specifics regarding on/off configuration please see +//! \ref PRCMPowerDomainOn(). +//! +//! \param ui32Domains determines which domain to request a power down for. +//! The domains that can be turned on/off are: +//! - \b PRCM_DOMAIN_RFCORE : RF Core +//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM +//! - \b PRCM_DOMAIN_SYSBUS +//! - \b PRCM_DOMAIN_CPU +//! +//! \return None +// +//***************************************************************************** +extern void PRCMPowerDomainOff(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Configure RF core to power down when idle. +//! +//! Use this function to configure the RF core to power down when Idle. This +//! is handled automatically in hardware if the RF Core reports that it is +//! idle. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMRfPowerDownWhenIdle(void) +{ + // Configure the RF power domain. + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL0RFC) = 0; +} + +//***************************************************************************** +// +//! \brief Enables a peripheral in Run mode. +//! +//! Peripherals are enabled with this function. At power-up, some peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note The actual enabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken to ensure that the +//! peripheral is not accessed until it is enabled. +//! When enabling Timers always make sure that the division factor for the +//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a +//! continuous rate even if the \b SYSBUSCLK is gated. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in Run mode +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \note The actual disabling of the peripheral may be delayed until some +//! time after this function returns. Care should be taken by the user to +//! ensure that the peripheral is not accessed in this interval as this might +//! cause the system to hang. +//! +//! \param ui32Peripheral is the peripheral to disable. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into sleep mode. Since the clocking configuration of the device does +//! not change, any peripheral can safely continue operating while the +//! processor is in sleep mode, and can therefore wake the processor from sleep +//! mode. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into sleep mode. Disabling peripherals while in sleep mode helps to lower +//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()), +//! the peripheral will automatically resume operation when the processor +//! leaves sleep mode, maintaining its entire state from before sleep mode was +//! entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Enables a peripheral in deep-sleep mode. +//! +//! This function allows a peripheral to continue operating when the processor +//! goes into deep-sleep mode. Since the clocking configuration of the device +//! may change, not all peripherals can safely continue operating while the +//! processor is in sleep mode. This in turn depends on the chosen power mode. +//! It is the responsibility of the caller to make sensible choices. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Disables a peripheral in deep-sleep mode. +//! +//! This function causes a peripheral to stop operating when the processor goes +//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps +//! to lower the current draw of the device, and can keep peripherals that +//! require a particular clock frequency from operating when the clock changes +//! as a result of entering deep-sleep mode. If enabled (via +//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume +//! operation when the processor leaves deep-sleep mode, maintaining its entire +//! state from before deep-sleep mode was entered. +//! +//! \note A call to this function will only setup the shadow registers in the +//! MCU domain for the PRCM module. For the changes to propagate to the system +//! controller in the AON domain a call to this function should always be +//! followed by a call to \ref PRCMLoadSet(). +//! +//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. +//! The parameter must be one of the following: +//! - \ref PRCM_PERIPH_TIMER0 +//! - \ref PRCM_PERIPH_TIMER1 +//! - \ref PRCM_PERIPH_TIMER2 +//! - \ref PRCM_PERIPH_TIMER3 +//! - \ref PRCM_PERIPH_SSI0 +//! - \ref PRCM_PERIPH_SSI1 +//! - \ref PRCM_PERIPH_UART0 +//! - \ref PRCM_PERIPH_UART1 +//! - \ref PRCM_PERIPH_I2C0 +//! - \ref PRCM_PERIPH_CRYPTO +//! - \ref PRCM_PERIPH_TRNG +//! - \ref PRCM_PERIPH_PKA +//! - \ref PRCM_PERIPH_UDMA +//! - \ref PRCM_PERIPH_GPIO +//! - \ref PRCM_PERIPH_I2S +//! +//! \return None +//! +//! \sa \ref PRCMLoadSet() +// +//***************************************************************************** +extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral); + +//***************************************************************************** +// +//! \brief Get the status for a specific power domain. +//! +//! Use this function to retrieve the current power status of one or more +//! power domains. +//! +//! \param ui32Domains determines which domain to get the power status for. +//! The parameter must be an OR'ed combination of one or several of: +//! - \ref PRCM_DOMAIN_RFCORE : RF Core. +//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! +//! \return Returns status of the requested domains: +//! - \ref PRCM_DOMAIN_POWER_OFF : The specified domains are \b all powered down. +//! This status is unconditional and the powered down status is guaranteed. +//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are still powered up. +// +//***************************************************************************** +extern uint32_t PRCMPowerDomainsAllOff(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Get the status for a specific power domain. +//! +//! Use this function to retrieve the current power status of one or more +//! power domains. +//! +//! \param ui32Domains determines which domain to get the power status for. +//! The parameter must be an OR'ed combination of one or several of: +//! - \ref PRCM_DOMAIN_RFCORE : RF Core. +//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 +//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 +//! +//! \return Returns status of the requested domains: +//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up. +//! This status is unconditional and the powered up status is guaranteed. +//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are still powered down. +// +//***************************************************************************** +extern uint32_t PRCMPowerDomainsAllOn(uint32_t ui32Domains); + +//***************************************************************************** +// +//! \brief Return the access status of the RF Core. +//! +//! Use this function to check if the RF Core is on and ready to be accessed. +//! Accessing register or memories that are not powered and clocked will +//! cause a bus fault. +//! +//! \return Returns access status of the RF Core. +//! - \c true : RF Core can be accessed. +//! - \c false : RF Core domain is not ready for access. +// +//***************************************************************************** +__STATIC_INLINE bool +PRCMRfReady(void) +{ + // Return the ready status of the RF Core. + return ((HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT1RFC) & + PRCM_PDSTAT1RFC_ON) ? true : false); +} + + +//***************************************************************************** +// +//! \brief Put the processor into sleep mode. +//! +//! This function places the processor into sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the +//! processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PRCMSleep(void) +{ + // Wait for an interrupt. + CPUwfi(); +} + +//***************************************************************************** +// +//! \brief Put the processor into deep-sleep mode. +//! +//! This function places the processor into deep-sleep mode; it does not return +//! until the processor returns to run mode. The peripherals that are enabled +//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up +//! the processor. +//! +//! \return None +//! +//! \sa \ref PRCMPeripheralDeepSleepEnable() +// +//***************************************************************************** +extern void PRCMDeepSleep(void); + +//***************************************************************************** +// +//! \brief Enable CACHE RAM retention +//! +//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionEnable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; +} + +//***************************************************************************** +// +//! \brief Disable CACHE RAM retention +//! +//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +PRCMCacheRetentionDisable( void ) +{ + HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PRCMInfClockConfigureSet + #undef PRCMInfClockConfigureSet + #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet + #endif + #ifdef ROM_PRCMInfClockConfigureGet + #undef PRCMInfClockConfigureGet + #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet + #endif + #ifdef ROM_PRCMAudioClockConfigSet + #undef PRCMAudioClockConfigSet + #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet + #endif + #ifdef ROM_PRCMAudioClockConfigSetOverride + #undef PRCMAudioClockConfigSetOverride + #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride + #endif + #ifdef ROM_PRCMAudioClockInternalSource + #undef PRCMAudioClockInternalSource + #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource + #endif + #ifdef ROM_PRCMAudioClockExternalSource + #undef PRCMAudioClockExternalSource + #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource + #endif + #ifdef ROM_PRCMPowerDomainOn + #undef PRCMPowerDomainOn + #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn + #endif + #ifdef ROM_PRCMPowerDomainOff + #undef PRCMPowerDomainOff + #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff + #endif + #ifdef ROM_PRCMPeripheralRunEnable + #undef PRCMPeripheralRunEnable + #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable + #endif + #ifdef ROM_PRCMPeripheralRunDisable + #undef PRCMPeripheralRunDisable + #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable + #endif + #ifdef ROM_PRCMPeripheralSleepEnable + #undef PRCMPeripheralSleepEnable + #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable + #endif + #ifdef ROM_PRCMPeripheralSleepDisable + #undef PRCMPeripheralSleepDisable + #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepEnable + #undef PRCMPeripheralDeepSleepEnable + #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable + #endif + #ifdef ROM_PRCMPeripheralDeepSleepDisable + #undef PRCMPeripheralDeepSleepDisable + #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable + #endif + #ifdef ROM_PRCMPowerDomainsAllOff + #undef PRCMPowerDomainsAllOff + #define PRCMPowerDomainsAllOff ROM_PRCMPowerDomainsAllOff + #endif + #ifdef ROM_PRCMPowerDomainsAllOn + #undef PRCMPowerDomainsAllOn + #define PRCMPowerDomainsAllOn ROM_PRCMPowerDomainsAllOn + #endif + #ifdef ROM_PRCMDeepSleep + #undef PRCMDeepSleep + #define PRCMDeepSleep ROM_PRCMDeepSleep + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PRCM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.c new file mode 100644 index 00000000..3146c293 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.c @@ -0,0 +1,78 @@ +/****************************************************************************** +* Filename: pwr_ctrl.c +* +* Description: Power Control driver. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "pwr_ctrl.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + + +//***************************************************************************** +// +// Set (Request) the main power source +// +//***************************************************************************** +void +PowerCtrlSourceSet(uint32_t ui32PowerConfig) +{ + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |= + (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &= + ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.h new file mode 100644 index 00000000..f0244474 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/pwr_ctrl.h @@ -0,0 +1,299 @@ +/****************************************************************************** +* Filename: pwr_ctrl.h +* +* Description: Defines and prototypes for the System Power Control. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup pwrctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __PWR_CTRL_H__ +#define __PWR_CTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_adi_2_refsys.h" +#include "debug.h" +#include "interrupt.h" +#include "osc.h" +#include "cpu.h" +#include "prcm.h" +#include "aon_ioc.h" +#include "adi.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#endif + +//***************************************************************************** +// +// Defines for the system power states +// +//***************************************************************************** +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 + +//***************************************************************************** +// +// Defines for the power configuration in the AON System Control 1.2 V +// +//***************************************************************************** +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 + +//***************************************************************************** +// +// The following are defines for the various reset source for the device. +// +//***************************************************************************** +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set (Request) the main power source. +//! +//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO +//! when in active mode. This is only allowed when the system is in lower power +//! mode where no code is executing and no peripherals are active. +//! Assuming that there is an external capacitor available for the +//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth +//! between the two when in active mode. +//! +//! \note The system will automatically switch to the GLDO / DCDC when waking +//! up from a low power mode. +//! +//! \param ui32PowerConfig is a bitmask indicating the target power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +//! - \ref PWRCTRL_PWRSRC_ULDO +//! +//! \return None +// +//***************************************************************************** +extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig); + +//***************************************************************************** +// +//! \brief Get the main power source. +//! +//! Use this function to retrieve the current active power source. +//! +//! When the System CPU is active it can never be powered by uLDO as this +//! is too weak a power source. +//! +//! \note Using the DCDC power supply requires an external inductor. +//! +//! \return Returns the main power source. +//! - \ref PWRCTRL_PWRSRC_DCDC +//! - \ref PWRCTRL_PWRSRC_GLDO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlSourceGet(void) +{ + uint32_t ui32PowerConfig; + + // Return the current power source + ui32PowerConfig = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL); + if(ui32PowerConfig & AON_PMCTL_PWRCTL_DCDC_ACTIVE) + { + return (PWRCTRL_PWRSRC_DCDC); + } + else + { + return (PWRCTRL_PWRSRC_GLDO); + } +} + +//***************************************************************************** +// +//! \brief OBSOLETE: Get the last known reset source of the system. +//! +//! \deprecated This function will be removed in a future release. +//! Use \ref SysCtrlResetSourceGet() instead. +//! +//! This function returns reset source but does not cover if waking up from shutdown. +//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet() +//! and will be removed in a future release. +//! +//! \return Returns one of the known reset values. +//! The possible reset sources are: +//! - \ref PWRCTRL_RST_POWER_ON +//! - \ref PWRCTRL_RST_PIN +//! - \ref PWRCTRL_RST_VDDS_BOD +//! - \ref PWRCTRL_RST_VDD_BOD +//! - \ref PWRCTRL_RST_VDDR_BOD +//! - \ref PWRCTRL_RST_CLK_LOSS +//! - \ref PWRCTRL_RST_SW_PIN +//! - \ref PWRCTRL_RST_WARM +//! +//! \sa \ref SysCtrlResetSourceGet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +PowerCtrlResetSourceGet(void) +{ + // Get the reset source. + return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & + AON_PMCTL_RESETCTL_RESET_SRC_M ) >> + AON_PMCTL_RESETCTL_RESET_SRC_S ) ; +} + +//***************************************************************************** +// +//! \brief Enables pad sleep in order to latch device outputs before shutdown. +//! +//! See \ref SysCtrlShutdown() for more information about how to enter +//! shutdown and how to wake up from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepDisable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepEnable(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 0; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown. +//! +//! This function must be called by the application after the device wakes up +//! from shutdown. +//! +//! See \ref SysCtrlShutdown() for more information about how to enter +//! shutdown and how to wake up from shutdown. +//! +//! \return None +//! +//! \sa \ref PowerCtrlPadSleepEnable() +// +//***************************************************************************** +__STATIC_INLINE void +PowerCtrlPadSleepDisable(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 1; + HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_PowerCtrlSourceSet + #undef PowerCtrlSourceSet + #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __PWR_CTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_cmd.h new file mode 100644 index 00000000..5438e94d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_cmd.h @@ -0,0 +1,2901 @@ +/****************************************************************************** +* Filename: rf_ble_cmd.h +* +* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __BLE_CMD_H +#define __BLE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ble_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; +typedef struct __RFC_STRUCT rfc_ble5RadioOp_s rfc_ble5RadioOp_t; +typedef struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s rfc_ble5Tx20RadioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s rfc_CMD_BLE5_SLAVE_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s rfc_CMD_BLE5_MASTER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s rfc_CMD_BLE5_ADV_EXT_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s rfc_CMD_BLE5_ADV_AUX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_PER_s rfc_CMD_BLE5_ADV_PER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_PER_s rfc_CMD_BLE5_SCANNER_PER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s rfc_CMD_BLE5_SCANNER_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s rfc_CMD_BLE5_INITIATOR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s rfc_CMD_BLE5_GENERIC_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s rfc_CMD_BLE5_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s rfc_CMD_BLE5_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s rfc_CMD_BLE5_ADV_DIR_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s rfc_CMD_BLE5_ADV_NC_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s rfc_CMD_BLE5_ADV_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s rfc_CMD_BLE5_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t; +typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t; +typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t; +typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t; +typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t; +typedef struct __RFC_STRUCT rfc_ble5SlavePar_s rfc_ble5SlavePar_t; +typedef struct __RFC_STRUCT rfc_ble5MasterPar_s rfc_ble5MasterPar_t; +typedef struct __RFC_STRUCT rfc_ble5AdvExtPar_s rfc_ble5AdvExtPar_t; +typedef struct __RFC_STRUCT rfc_ble5AdvAuxPar_s rfc_ble5AdvAuxPar_t; +typedef struct __RFC_STRUCT rfc_ble5AdvPerPar_s rfc_ble5AdvPerPar_t; +typedef struct __RFC_STRUCT rfc_ble5AuxChRes_s rfc_ble5AuxChRes_t; +typedef struct __RFC_STRUCT rfc_ble5ScannerPar_s rfc_ble5ScannerPar_t; +typedef struct __RFC_STRUCT rfc_ble5ScannerPerPar_s rfc_ble5ScannerPerPar_t; +typedef struct __RFC_STRUCT rfc_ble5InitiatorPar_s rfc_ble5InitiatorPar_t; +typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t; +typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t; +typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t; +typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t; +typedef struct __RFC_STRUCT rfc_ble5ScanInitOutput_s rfc_ble5ScanInitOutput_t; +typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t; +typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t; +typedef struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s rfc_ble5ExtAdvEntry_t; +typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t; +typedef struct __RFC_STRUCT rfc_ble5AdiEntry_s rfc_ble5AdiEntry_t; +typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; +typedef struct __RFC_STRUCT rfc_ble5RxStatus_s rfc_ble5RxStatus_t; + +//! \addtogroup bleRadioOp +//! @{ +struct __RFC_STRUCT rfc_bleRadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5RadioOp +//! @{ +struct __RFC_STRUCT rfc_ble5RadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5Tx20RadioOp +//! @{ +//! Command structure for Bluetooth commands which includes the optional field for 20-dBm PA TX power +struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SLAVE +//! @{ +#define CMD_BLE_SLAVE 0x1801 +//! BLE Slave Command +struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_MASTER +//! @{ +#define CMD_BLE_MASTER 0x1802 +//! BLE Master Command +struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV +//! @{ +#define CMD_BLE_ADV 0x1803 +//! BLE Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_DIR +//! @{ +#define CMD_BLE_ADV_DIR 0x1804 +//! BLE Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_NC +//! @{ +#define CMD_BLE_ADV_NC 0x1805 +//! BLE Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_SCAN +//! @{ +#define CMD_BLE_ADV_SCAN 0x1806 +//! BLE Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_SCANNER +//! @{ +#define CMD_BLE_SCANNER 0x1807 +//! BLE Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_INITIATOR +//! @{ +#define CMD_BLE_INITIATOR 0x1808 +//! BLE Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_GENERIC_RX +//! @{ +#define CMD_BLE_GENERIC_RX 0x1809 +//! BLE Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_TX_TEST +//! @{ +#define CMD_BLE_TX_TEST 0x180A +//! BLE PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE_ADV_PAYLOAD +//! @{ +#define CMD_BLE_ADV_PAYLOAD 0x1001 +//! BLE Update Advertising Payload Command +struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_RADIO_SETUP +//! @{ +#define CMD_BLE5_RADIO_SETUP 0x1820 +//! Bluetooth 5 Radio Setup Command for all PHYs +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x1820 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_SLAVE +//! @{ +#define CMD_BLE5_SLAVE 0x1821 +//! Bluetooth 5 Slave Command +struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s { + uint16_t commandNo; //!< The command ID number 0x1821 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_MASTER +//! @{ +#define CMD_BLE5_MASTER 0x1822 +//! Bluetooth 5 Master Command +struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s { + uint16_t commandNo; //!< The command ID number 0x1822 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_EXT +//! @{ +#define CMD_BLE5_ADV_EXT 0x1823 +//! Bluetooth 5 Extended Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s { + uint16_t commandNo; //!< The command ID number 0x1823 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_AUX +//! @{ +#define CMD_BLE5_ADV_AUX 0x1824 +//! Bluetooth 5 Secondary Channel Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s { + uint16_t commandNo; //!< The command ID number 0x1824 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_PER +//! @{ +#define CMD_BLE5_ADV_PER 0x1825 +//! Bluetooth 5 Periodic Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_PER_s { + uint16_t commandNo; //!< The command ID number 0x1825 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvPerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_SCANNER_PER +//! @{ +#define CMD_BLE5_SCANNER_PER 0x1826 +//! Bluetooth 5 Periodic Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_PER_s { + uint16_t commandNo; //!< The command ID number 0x1826 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5ScannerPerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_SCANNER +//! @{ +#define CMD_BLE5_SCANNER 0x1827 +//! Bluetooth 5 Scanner Command +struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s { + uint16_t commandNo; //!< The command ID number 0x1827 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_INITIATOR +//! @{ +#define CMD_BLE5_INITIATOR 0x1828 +//! Bluetooth 5 Initiator Command +struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s { + uint16_t commandNo; //!< The command ID number 0x1828 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_GENERIC_RX +//! @{ +#define CMD_BLE5_GENERIC_RX 0x1829 +//! Bluetooth 5 Generic Receiver Command +struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s { + uint16_t commandNo; //!< The command ID number 0x1829 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_TX_TEST +//! @{ +#define CMD_BLE5_TX_TEST 0x182A +//! Bluetooth 5 PHY Test Transmitter Command +struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x182A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV +//! @{ +#define CMD_BLE5_ADV 0x182B +//! Bluetooth 5 Connectable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s { + uint16_t commandNo; //!< The command ID number 0x182B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_DIR +//! @{ +#define CMD_BLE5_ADV_DIR 0x182C +//! Bluetooth 5 Connectable Directed Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s { + uint16_t commandNo; //!< The command ID number 0x182C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_NC +//! @{ +#define CMD_BLE5_ADV_NC 0x182D +//! Bluetooth 5 Non-Connectable Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s { + uint16_t commandNo; //!< The command ID number 0x182D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BLE5_ADV_SCAN +//! @{ +#define CMD_BLE5_ADV_SCAN 0x182E +//! Bluetooth 5 Scannable Undirected Advertiser Command +struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x182E + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct { + uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct { + uint8_t mainMode:2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. +} __RFC_STRUCT_ATTR; + +//! @} + +#define CMD_BLE5_RADIO_SETUP_PA CMD_BLE5_RADIO_SETUP + +//! \addtogroup CMD_BLE5_RADIO_SETUP_PA +//! @{ +//! Bluetooth 5 Radio Setup Command for all PHYs with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlavePar +//! @{ +struct __RFC_STRUCT rfc_bleMasterSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleSlavePar +//! @{ +//! Parameter structure for legacy slave (CMD_BLE_SLAVE) + +struct __RFC_STRUCT rfc_bleSlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterPar +//! @{ +//! Parameter structure for legacy master (CMD_BLE_MASTER) + +struct __RFC_STRUCT rfc_bleMasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvPar +//! @{ +//! Parameter structure for legacy advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) + +struct __RFC_STRUCT rfc_bleAdvPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerPar +//! @{ +//! Parameter structure for legacy scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the white list + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU
+ //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorPar +//! @{ +//! Parameter structure for legacy initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxPar +//! @{ +//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestPar +//! @{ +//! Parameter structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestPar_s { + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F, + //!< Section 4.1.4 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct { + uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9:1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS9 encoding of packet
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15:1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS15 encoding of packet
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5SlavePar +//! @{ +//! Parameter structure for Bluetooth 5 slave (CMD_BLE5_SLAVE) + +struct __RFC_STRUCT rfc_ble5SlavePar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5MasterPar +//! @{ +//! Parameter structure for Bluetooth 5 master (CMD_BLE5_MASTER) + +struct __RFC_STRUCT rfc_ble5MasterPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdvExtPar +//! @{ +//! Parameter structure for extended advertiser (CMD_BLE5_ADV_EXT) + +struct __RFC_STRUCT rfc_ble5AdvExtPar_s { + struct { + uint8_t :2; + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + } advConfig; + uint8_t __dummy0; + uint8_t __dummy1; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdvAuxPar +//! @{ +//! Parameter structure for secondary channel advertiser (CMD_BLE5_ADV_AUX) + +struct __RFC_STRUCT rfc_ble5AdvAuxPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t targetAddrType:1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list + //!< 1: Advertiser is directed: pWhiteList points to a single device address + uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + struct { + uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet + uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet + //!< (may be NULL if not applicable) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdvPerPar +//! @{ +//! Parameter structure for periodic advertiser (CMD_BLE5_ADV_PER) + +struct __RFC_STRUCT rfc_ble5AdvPerPar_s { + uint16_t __dummy0; + uint8_t __dummy1; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet + uint32_t accessAddress; //!< Access address used on the periodic advertisement + uint8_t crcInit0; //!< CRC initialization value used on the periodic advertisement -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the periodic advertisement -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the periodic advertisement -- most significant byte +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AuxChRes +//! @{ +struct __RFC_STRUCT rfc_ble5AuxChRes_s { + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ScannerPar +//! @{ +//! Parameter structure for Bluetooth 5 scanner (CMD_BLE5_SCANNER) + +struct __RFC_STRUCT rfc_ble5ScannerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan:1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets
+ //!< 1: Automatically set ignore bit in white list for legacy packets + uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode:1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + struct { + uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering
+ //!< 1: Perform ADI filtering on packets where ADI is present + uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
+ //!< 1: Legacy mode: Automatically update ADI entry for received packets with + //!< AdvDataInfo after first occurrence + uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended + //!< advertiser packets (recommended)
+ //!< 1: Apply duplicate filtering based on device address for extended advertiser + //!< packets with no ADI field + uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
+ //!< 1: Automatically set ignore bit in white list for extended advertising packets + uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing
+ //!< 1: Automatically update ADI entry for received packets so that only the same + //!< ADI is accepted for the rest of the chain and the SID/DID combination is + //!< ignored after the entire chain is received. + uint8_t bExclusiveSid:1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all + //!< valid SIDs are accepted
+ //!< 1: Do not modify adiStatus.state when command starts
+ uint8_t bAcceptSyncInfo:1; //!< \brief 0: Perform normal filtering
+ //!< 1: Accept packets with SyncInfo present in the extended header, or non-connectable + //!< non-scannable adv ext ind with aux ptr, even if they would normally be filtered out + } extFilterConfig; + struct { + uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored + uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; + //!< lastAcceptedSid field is not valid
+ //!< 1: A message with ADI has been received, but no chain is under reception; + //!< ADI filtering to be performed normally
+ //!< 2: A message with SID as given in lastAcceptedSid has been + //!< received, and chained messages are still pending. Messages without this + //!< SID will be ignored
+ //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID + //!< as given in lastAcceptedSid, and chained messages are + //!< pending. Messages with an ADI field will be ignored.
+ //!< 4: A message with no ADI has been received, and chained messages are still + //!< pending. Messages with an ADI field will be ignored.
+ //!< Others: Reserved + } adiStatus; + uint8_t __dummy0; + uint16_t __dummy1; + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list + rfc_ble5AdiEntry_t *pAdiList; //!< Pointer to advDataInfo list + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ScannerPerPar +//! @{ +//! Parameter structure for Bluetooth 5 periodic scanner (CMD_BLE5_SCANNER_PER) + +struct __RFC_STRUCT rfc_ble5ScannerPerPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t :2; + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t :1; + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + } scanConfig; + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + uint32_t accessAddress; //!< Access address used on the periodic advertisement + uint8_t crcInit0; //!< CRC initialization value used on the periodic advertisement -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the periodic advertisement -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the periodic advertisement -- most significant byte + uint8_t __dummy3; + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5InitiatorPar +//! @{ +//! Parameter structure for Bluetooth 5 initiator (CMD_BLE5_INITIATOR) + +struct __RFC_STRUCT rfc_ble5InitiatorPar_s { + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct { + uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset:1; //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
+ //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND + } initConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct { + uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleMasterSlaveOutput +//! @{ +//! Output structure for master and slave (CMD_BLE_MASTER/CMD_BLE_SLAVE/CMD_BLE5_MASTER/CMD_BLE5_SLAVE) + +struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet (signed) + struct { + uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise + uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; //!< Status of received packets + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleAdvOutput +//! @{ +//! Output structure for advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) + +struct __RFC_STRUCT rfc_bleAdvOutput_s { + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored + uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleScannerOutput +//! @{ +//! Output structure for legacy scanner (CMD_BLE_SCANNER) + +struct __RFC_STRUCT rfc_bleScannerOutput_s { + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleInitiatorOutput +//! @{ +//! Output structure for legacy initiator (CMD_BLE_INITIATOR) + +struct __RFC_STRUCT rfc_bleInitiatorOutput_s { + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ) +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ScanInitOutput +//! @{ +//! Output structure for BLE scanner and initiator (CMD_BLE5_SCANNER and CMD_BLE5_INITIATOR) + +struct __RFC_STRUCT rfc_ble5ScanInitOutput_s { + uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets + uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored + uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored + uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleGenericRxOutput +//! @{ +//! Output structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) + +struct __RFC_STRUCT rfc_bleGenericRxOutput_s { + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleTxTestOutput +//! @{ +//! Output structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) + +struct __RFC_STRUCT rfc_bleTxTestOutput_s { + uint16_t nTx; //!< Number of packets transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5ExtAdvEntry +//! @{ +//! Common Extended Packet Entry Format + +struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s { + struct { + uint8_t length:6; //!< Extended header length + uint8_t advMode:2; //!< \brief Advertiser mode as defined in BLE:
+ //!< 0: Non-connectable, non-scannable
+ //!< 1: Connectable, non-scannable
+ //!< 2: Non-connectable, scannable
+ //!< 3: Reserved + } extHdrInfo; + uint8_t extHdrFlags; //!< Extended header flags as defined in BLE + struct { + uint8_t bSkipAdvA:1; //!< \brief 0: AdvA is present in extended payload if configured in + //!< extHdrFlags
+ //!< 1: AdvA is inserted automatically from command structure if configured in + //!< extHdrFlags and is omitted from extended header + uint8_t bSkipTargetA:1; //!< \brief 0: TargetA is present in extended payload if configured in + //!< extHdrFlags. For response messages, the value is replaced + //!< by the received address when sending
+ //!< 1: TargetA is inserted automatically from command structure or received + //!< address if configured in extHdrFlags and is omitted from + //!< extended header. Not supported with CMD_BLE5_ADV_EXT. + uint8_t deviceAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the device address in extended + //!< header buffer -- public (0) or random (1) + uint8_t targetAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the target address in extended + //!< header buffer -- public (0) or random (1) + } extHdrConfig; + uint8_t advDataLen; //!< Size of payload buffer + uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended + //!< header flags, automatic advertiser address, or automatic target address are + //!< present, pointer may be NULL. + uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If advDataLen = 0, + //!< pointer may be NULL. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleWhiteListEntry +//! @{ +//! White list entry structure + +struct __RFC_STRUCT rfc_bleWhiteListEntry_s { + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct { + uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo + //!< field is not present, 0 otherwise. Used to mask out entries that + //!< have already been scanned and reported. + uint8_t :1; + uint8_t bPrivIgn:1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5AdiEntry +//! @{ +//! AdvDataInfo list entry structure + +struct __RFC_STRUCT rfc_ble5AdiEntry_s { + struct { + uint16_t advDataId:12; //!< \brief If bValid = 1: Last Advertising Data ID (DID) for the + //!< Advertising Set ID (SID) corresponding to the entry number in the array + uint16_t mode:2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)
+ //!< 1: Entry is valid (ignore packets with the given SID where DID equals + //!< advDataId)
+ //!< 2: Entry is blocked (always ignore packet with the given SID)
+ //!< 3: Reserved + } advDataInfo; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup bleRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer for legacy commands + +struct __RFC_STRUCT rfc_bleRxStatus_s { + struct { + uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ble5RxStatus +//! @{ +//! Receive status field that may be appended to message in receive buffer for Bluetooth 5 commands + +struct __RFC_STRUCT rfc_ble5RxStatus_s { + struct { + uint16_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint16_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint16_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + uint16_t phyMode:2; //!< \brief The PHY on which the packet was received
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded, S = 8 (125 kbps)
+ //!< 3: Coded, S = 2 (500 kbps) + uint16_t bSyncInfoAutoAccept:1; //!< \brief 1 if the packet was accepted only due to syncInfo field present in the extHdr, + //!< 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_mailbox.h new file mode 100644 index 00000000..7331daf5 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ble_mailbox.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* Filename: rf_ble_mailbox.h +* +* Description: Definitions for BLE interface +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _BLE_MAILBOX_H +#define _BLE_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead +#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 +#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted +///@} +/// \name Operation finished with error +///@{ +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past +///@} +///@} + + +/// Special trigger for BLE slave command +#define BLE_TRIG_REL_SYNC 15 + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_coex.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_coex.h new file mode 100644 index 00000000..396afa17 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_coex.h @@ -0,0 +1,168 @@ +/****************************************************************************** +* Filename: rf_bt5_coex.h +* +* Description: CC13x2/CC26x2 structures for bt5 coexistence support +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __BT5_COEX_H +#define __BT5_COEX_H + +//! \addtogroup rfCoreHal +//! @{ + +//! \addtogroup bt5_coex +//! @{ + +#include +#include "rf_mailbox.h" + +// Error code for GRANT signal not given +#define BLE_ERROR_NO_GRANT 0x1808 + +typedef struct rfCoreHal_bleCoExConfig_s rfCoreHal_bleCoExConfig_t; + + +//! \addtogroup bleCoExConfig +//! @{ +struct rfCoreHal_bleCoExConfig_s { + struct { + uint8_t bCoExEnable:1; //!< \brief 0: CoEx disabled + //!< 1: CoEx enabled + uint8_t bUseREQUEST:1; //!< \brief 0: REQUEST signal inactive + //!< 1: REQUEST signal active + uint8_t bUseGRANT:1; //!< \brief 0: GRANT signal inactive + //!< 1: GRANT signal active + uint8_t bUsePRIORITY:1; //!< \brief 0: PRIORITY signal inactive + //!< 1: PRIORITY signal active + uint8_t bRequestForChain:1; //!< \brief 0: Deassert REQUEST after each RF command + //!< 1: Keep REQUEST asserted for entire command chain + } coExEnable; + uint8_t coExTxRxIndication; //!< \brief 0 = RX indication is 0, TX indication is 0 + //!< 1 = RX indication is 0, TX indication is 1 + //!< 2 = RX indication is 1, TX indication is 0 + //!< 3 = RX indication is 1, RX indication is 1 + uint16_t priorityIndicationTime; //!< Time (in us) that the PRIORITY signal will indicate the priority. + struct { + uint8_t bRequestAsserted:1; //!< \brief READ ONLY. 0 = REQUEST not asserted, 1 = REQUEST is asserted. + //!< Will indicate if REQUEST would have been asserted, except if signal is not used. + uint8_t bIgnoreGrantInRxAsserted:1;//!< \brief READ ONLY. 0 = GRANT is checked in RX, 1 = GRANT is not checked in RX + //!< Will indicate if the current running command is ignoring GRANT in RX + } rfCoreCoExStatus; + struct { + uint8_t bUseOverridePriority:1; //!< \brief Bit to override default priority + //!< 0: Use default priority + //!< 1: use overridePriority priority for entire chain + uint8_t overridePriority:1; //!< \brief Priority to use if priority is overridden + //!< 0: Low priority if bUseOverridePriority = 1 + //!< 1: High priority if bUseOverridePriority = 1 + uint8_t bUseOverrideRequestForRx:1;//!< \brief Bit to override default request for RX + //!< 0: Use default request for RX + //!< 1: use overrideRequestForRx for entire chain + uint8_t overrideRequestForRx:1; //!< \brief REQUEST signal override if bUseOverrideRequestForRx = 1, used for entire chain + //!< 0: Don't request for RX if bUseOverrideRequestForRx = 1 + //!< 1: Request for RX if bUseOverrideRequestForRx = 1 + } overrideConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleMasterSlaveConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleAdvConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleScanConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleInitConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleGenericRxConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdBleTxTestConfig; + uint8_t grantLatencyTime; //!< \brief Reserved for future use. Writes to this variable have no effect. +} ; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_iq_autocopy.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_iq_autocopy.h new file mode 100644 index 00000000..938ccc75 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_bt5_iq_autocopy.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* Filename: rf_bt5_iq_autocopy.h +* +* Description: CC13x2/CC26x2 API for IQ Sample automatic copy in BLE +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __RF_BT5_IQ_AUTOCOPY_H +#define __RF_BT5_IQ_AUTOCOPY_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup rf_bt5_iq_autocopy +//! @{ + +#include +#include "rf_mailbox.h" + +#define IRQN_CTE_SAMPLES_AUTOCOPIED 15 +#define IRQ_CTE_SAMPLES_AUTOCOPIED (1U << IRQN_CTE_SAMPLES_AUTOCOPIED) + +typedef struct __RFC_STRUCT rfc_iqAutoCopyDef_s rfc_iqAutoCopyDef_t; +typedef struct __RFC_STRUCT rfc_statusIqSamplesEntry_s rfc_statusIqSamplesEntry_t; + +//! \addtogroup iqAutoCopyDef +//! @{ +struct __RFC_STRUCT rfc_iqAutoCopyDef_s { + struct { + uint8_t bFlushCrcErr:1; //!< \brief 0: Report samples regardless of CRC result
+ //!< 1: Do not report samples from packets with CRC error + uint8_t bFlushCteInfoErr:1; //!< \brief 0: Report samples from packets with any CTEInfo
+ //!< 1: Do not report samples from packets with invalid CTEInfo + uint8_t bFlushAoa:1; //!< \brief 0: Report samples from AoA packets
+ //!< 1: Do not report samples from AoA packets + uint8_t bFlushAod1us:1; //!< \brief 0: Report samples from AoD packets with 1 us slots
+ //!< 1: Do not report samples from AoD packets with 1 us slots + uint8_t bFlushAod2us:1; //!< \brief 0: Report samples from AoD packets with 2 us slots
+ //!< 1: Do not report samples from AoD packets with 2 us slots + uint8_t bIncludeRfGain:1; //!< \brief 0: Report gain as single-bit value in status field only
+ //!< 1: Also report an explicit gain byte in dB + uint8_t bIncludeRssi:1; //!< \brief 0: Don't report RSSI in status field
+ //!< 1: Report RSSI in status field + } samplesConfig; + uint8_t minReportSize; //!< Minimum value of CTETime for packets to report + uint8_t maxReportSize; //!< Maximum value of CTETime for packets to report + uint8_t cteCopyLimitCount; //!< \brief Number of CTE that should be recieved. + //!< 0x00: Do not copy any CTE, CTE will be flushed + //!< 0x01 - 0xFE: Copy CTE and decrement this counter + //!< 0xFF: Copy CTE and do not decrement this counter + uint32_t* pSamplesQueue; //!< Pointer to queue for copying samples. 0: Do not copy samples + uint8_t numPktCopied; //!< Number of packets copied. Updated by CM0. + uint8_t numPktFlushed; //!< Number of packets not copied due to the settings in samplesConfig. Updated by CM0. + uint8_t numPktBufFull; //!< Number of packets not copied because no buffer was available. Updated by CM0. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup statusIqSamplesEntry +//! @{ +struct __RFC_STRUCT rfc_statusIqSamplesEntry_s { + struct { + uint8_t bCrcErr:1; //!< 1 if the samples came from a packet received with CRC error; 0 otherwise + uint8_t bCopyTrunk:1; //!< 1 if the entry was too short to hold all the samples in RF core RAM; 0 otherwise + uint8_t bSamplTrunk:1; //!< 1 if the entry contains samples of a CTE that was too long for the available RF core RAM; 0 otherwise + uint8_t rfRamInfo:2; //!< \brief 0: Reserved
+ //!< 1: Packet was contained in MCE RAM only
+ //!< 2: Packet was contained in RFE RAM only
+ //!< 3: Packet was contained in both RAMs
+ uint8_t rfPhy:1; //!< \brief PHY of the packet containing the samples
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps + uint8_t rfGainStep:1; //!< \brief RF gain of the received samples
+ //!< 0: High gain
+ //!< 1: Low gain + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_common_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_common_cmd.h new file mode 100644 index 00000000..a501a8e8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_common_cmd.h @@ -0,0 +1,1095 @@ +/****************************************************************************** +* Filename: rf_common_cmd.h +* +* Description: CC13x2/CC26x2 API for common/generic commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __COMMON_CMD_H +#define __COMMON_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup common_cmd +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; +typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; +typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t; +typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s rfc_CMD_RESYNC_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t; +typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t; +typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t; +typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t; +typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t; +typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s rfc_CMD_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t; +typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t; +typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t; +typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t; +typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t; +typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t; +typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t; +typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t; +typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t; +typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t; +typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t; +typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t; +typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t; +typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; +typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t; + +//! \addtogroup command +//! @{ +struct __RFC_STRUCT rfc_command_s { + uint16_t commandNo; //!< The command ID number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup radioOp +//! @{ +//! Common definition for radio operation commands + +struct __RFC_STRUCT rfc_radioOp_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_NOP +//! @{ +#define CMD_NOP 0x0801 +//! No Operation Command +struct __RFC_STRUCT rfc_CMD_NOP_s { + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RADIO_SETUP +//! @{ +#define CMD_RADIO_SETUP 0x0802 +//! Radio Setup Command for Pre-Defined Schemes +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS +//! @{ +#define CMD_FS 0x0803 +//! Frequency Synthesizer Programming Command +struct __RFC_STRUCT rfc_CMD_FS_s { + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct { + uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq:6; //!< \brief 0: Use default reference frequency
+ //!< Others: Use reference frequency 48 MHz/refFreq + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_OFF +//! @{ +#define CMD_FS_OFF 0x0804 +//! Command for Turning off Frequency Synthesizer +struct __RFC_STRUCT rfc_CMD_FS_OFF_s { + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RX_TEST +//! @{ +#define CMD_RX_TEST 0x0807 +//! Receiver Test Command +struct __RFC_STRUCT rfc_CMD_RX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TX_TEST +//! @{ +#define CMD_TX_TEST 0x0808 +//! Transmitter Test Command +struct __RFC_STRUCT rfc_CMD_TX_TEST_s { + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bUseCw:1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode:2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_STOP_RAT +//! @{ +#define CMD_SYNC_STOP_RAT 0x0809 +//! Synchronize and Stop Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SYNC_START_RAT +//! @{ +#define CMD_SYNC_START_RAT 0x080A +//! Synchrously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_RESYNC_RAT +//! @{ +#define CMD_RESYNC_RAT 0x0816 +//! Re-calculate rat0 value while RAT is running +struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0816 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT +//! @{ +#define CMD_COUNT 0x080B +//! Counter Command +struct __RFC_STRUCT rfc_CMD_COUNT_s { + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERUP +//! @{ +#define CMD_FS_POWERUP 0x080C +//! Power up Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FS_POWERDOWN +//! @{ +#define CMD_FS_POWERDOWN 0x080D +//! Power down Frequency Syntheszier Command +struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SCH_IMM +//! @{ +#define CMD_SCH_IMM 0x0810 +//! Run Immidiate Command as Radio Operation Command +struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_COUNT_BRANCH +//! @{ +#define CMD_COUNT_BRANCH 0x0812 +//! Counter Command with Branch of Command Chain +struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PATTERN_CHECK +//! @{ +#define CMD_PATTERN_CHECK 0x0813 +//! Command for Checking a Value in Memory aginst a Pattern +struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t operation:2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value + uint16_t signExtend:5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal:1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to +} __RFC_STRUCT_ATTR; + +//! @} + +#define CMD_RADIO_SETUP_PA CMD_RADIO_SETUP + +//! \addtogroup CMD_RADIO_SETUP_PA +//! @{ +//! Radio Setup Command for Pre-Defined Schemes with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
+ //!< Others: Reserved + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ABORT +//! @{ +#define CMD_ABORT 0x0401 +//! Abort Running Radio Operation Command +struct __RFC_STRUCT rfc_CMD_ABORT_s { + uint16_t commandNo; //!< The command ID number 0x0401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_STOP +//! @{ +#define CMD_STOP 0x0402 +//! Stop Running Radio Operation Command Gracefully +struct __RFC_STRUCT rfc_CMD_STOP_s { + uint16_t commandNo; //!< The command ID number 0x0402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_RSSI +//! @{ +#define CMD_GET_RSSI 0x0403 +//! Read RSSI Command +struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { + uint16_t commandNo; //!< The command ID number 0x0403 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_RADIO_SETUP +//! @{ +#define CMD_UPDATE_RADIO_SETUP 0x0001 +//! Update Radio Settings Command +struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_TRIGGER +//! @{ +#define CMD_TRIGGER 0x0404 +//! Generate Command Trigger +struct __RFC_STRUCT rfc_CMD_TRIGGER_s { + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_GET_FW_INFO +//! @{ +#define CMD_GET_FW_INFO 0x0002 +//! Request Information on the RF Core ROM Firmware +struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_START_RAT +//! @{ +#define CMD_START_RAT 0x0405 +//! Asynchronously Start Radio Timer Command +struct __RFC_STRUCT rfc_CMD_START_RAT_s { + uint16_t commandNo; //!< The command ID number 0x0405 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PING +//! @{ +#define CMD_PING 0x0406 +//! Respond with Command ACK Only +struct __RFC_STRUCT rfc_CMD_PING_s { + uint16_t commandNo; //!< The command ID number 0x0406 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_READ_RFREG +//! @{ +#define CMD_READ_RFREG 0x0601 +//! Read RF Core Hardware Register +struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ADD_DATA_ENTRY +//! @{ +#define CMD_ADD_DATA_ENTRY 0x0005 +//! Add Data Entry to Queue +struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_DATA_ENTRY +//! @{ +#define CMD_REMOVE_DATA_ENTRY 0x0006 +//! Remove First Data Entry from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_FLUSH_QUEUE +//! @{ +#define CMD_FLUSH_QUEUE 0x0007 +//! Flush Data Queue +struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CLEAR_RX +//! @{ +#define CMD_CLEAR_RX 0x0008 +//! Clear all RX Queue Entries +struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_REMOVE_PENDING_ENTRIES +//! @{ +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +//! Remove Pending Entries from Queue +struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CMP +//! @{ +#define CMD_SET_RAT_CMP 0x000A +//! Set Radio Timer Channel in Compare Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_CPT +//! @{ +#define CMD_SET_RAT_CPT 0x0603 +//! Set Radio Timer Channel in Capture Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { + uint16_t commandNo; //!< The command ID number 0x0603 + struct { + uint16_t :3; + uint16_t inputSrc:5; //!< Input source indicator + uint16_t ratCh:4; //!< The radio timer channel number + uint16_t bRepeated:1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode:2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISABLE_RAT_CH +//! @{ +#define CMD_DISABLE_RAT_CH 0x0408 +//! Disable Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_RAT_OUTPUT +//! @{ +#define CMD_SET_RAT_OUTPUT 0x0604 +//! Set Radio Timer Output to a Specified Mode +struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { + uint16_t commandNo; //!< The command ID number 0x0604 + struct { + uint16_t :2; + uint16_t outputSel:3; //!< Output event indicator + uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh:4; //!< The radio timer channel number + } config; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_ARM_RAT_CH +//! @{ +#define CMD_ARM_RAT_CH 0x0409 +//! Arm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_DISARM_RAT_CH +//! @{ +#define CMD_DISARM_RAT_CH 0x040A +//! Disarm Radio Timer Channel +struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX_POWER +//! @{ +#define CMD_SET_TX_POWER 0x0010 +//! Set Transmit Power +struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< New TX power setting +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_TX20_POWER +//! @{ +#define CMD_SET_TX20_POWER 0x0014 +//! Set Transmit Power for 20-dBm PA +struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s { + uint16_t commandNo; //!< The command ID number 0x0014 + uint16_t __dummy0; + uint32_t tx20Power; //!< New TX power setting +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_CHANGE_PA +//! @{ +#define CMD_CHANGE_PA 0x0015 +//! Set TX power with possibility to switch between PAs +struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s { + uint16_t commandNo; //!< The command ID number 0x0015 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the + //!< change, including new TX power +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_HPOSC_FREQ +//! @{ +#define CMD_UPDATE_HPOSC_FREQ 0x0608 +//! Set New Frequency Offset for HPOSC +struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s { + uint16_t commandNo; //!< The command ID number 0x0608 + int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_UPDATE_FS +//! @{ +#define CMD_UPDATE_FS 0x0011 +//! Set New Synthesizer Frequency without Recalibration (Deprecated; use CMD_MODIFY_FS) +struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_MODIFY_FS +//! @{ +#define CMD_MODIFY_FS 0x0013 +//! Set New Synthesizer Frequency without Recalibration +struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s { + uint16_t commandNo; //!< The command ID number 0x0013 + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_BUS_REQUEST +//! @{ +#define CMD_BUS_REQUEST 0x040E +//! Request System Bus to be Availbale +struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_SET_CMD_START_IRQ +//! @{ +#define CMD_SET_CMD_START_IRQ 0x0411 +//! Enable or disable generation of IRQ when a radio operation command starts +struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s { + uint16_t commandNo; //!< The command ID number 0x0411 + uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_data_entry.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_data_entry.h new file mode 100644 index 00000000..5e775082 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_data_entry.h @@ -0,0 +1,217 @@ +/****************************************************************************** +* Filename: rf_data_entry.h +* +* Description: Definition of API for data exchange +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __DATA_ENTRY_H +#define __DATA_ENTRY_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup data_entry +//! @{ + +#include +#include "rf_mailbox.h" + +typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; +typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; +typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t; +typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t; +typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; + +//! \addtogroup dataEntry +//! @{ +struct __RFC_STRUCT rfc_dataEntry_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryGeneral +//! @{ +//! General data entry structure (type = 0) + +struct __RFC_STRUCT rfc_dataEntryGeneral_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryMulti +//! @{ +//! Multi-element data entry structure (type = 1) + +struct __RFC_STRUCT rfc_dataEntryMulti_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPointer +//! @{ +//! Pointer data entry structure (type = 2) + +struct __RFC_STRUCT rfc_dataEntryPointer_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup dataEntryPartial +//! @{ +//! Partial read data entry structure (type = 3) + +struct __RFC_STRUCT rfc_dataEntryPartial_s { + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct { + uint8_t type:2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct { + uint16_t numElements:13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_cmd.h new file mode 100644 index 00000000..a62fa3de --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_cmd.h @@ -0,0 +1,844 @@ +/****************************************************************************** +* Filename: rf_hid_cmd.h +* +* Description: CC13x2/CC26x2 API for HID commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +/*!***************************************************************************** + * @file rf_hid_cmd.h + * @brief RF HID command interface for CC13x2, CC26x2 + * + * + * To use the CMD_HID_TX and CMD_HID_RX commands, make sure that the following + * override list is being used: + * @code + * #define TURNAROUND_TIME 64 // 64 µs turnaround time + * uint32_t pOverridesCommon[] = + * { + * // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). + * (uint32_t)0x00F388D3, + * // Set pilot tone length to 4 us (enable phase error discard as early as possible) + * HW_REG_OVERRIDE(0x6024,0x0020), + * // Bluetooth 5: Default to no CTE. + * HW_REG_OVERRIDE(0x5328,0x0000), + * // Synth: Increase mid code calibration time to 5 us + * (uint32_t)0x00058683, + * // Synth: Increase mid code calibration time to 5 us + * HW32_ARRAY_OVERRIDE(0x4004,1), + * // Synth: Increase mid code calibration time to 5 us + * (uint32_t)0x38183C30, + * // HID: Reduce turnaround times: + * (uint32_t)((TURNAROUND_TIME*4)<<16)|0x0263, // modify tx to rx turnaround time + * (uint32_t)((TURNAROUND_TIME*4)<<16)|0x0283, // modify rx to tx turnaround time + * // Of of override list + * (uint32_t)0xFFFFFFFF + * }; + * @endcode + * + * @anchor rf_hid_overview + * # Overview + * The HID commands are designed to be compatible with CC254x devices, + * using the same protocol as the CC254x. + * The packet are defined as: + * 8 bit preamble, 32 bit sync word, optional 8 bit address, 8 or 9 bit header, + * [0-n] byte payload and 16 bit CRC at 2 Mbps. + * The HID commands uses the same automode functionality as found in the + * CC254x devices, see [CC254x user guide](https://www.ti.com/lit/ug/swru283b/swru283b.pdf). + * + * The CMD_HID_TX utlizes a TX queue to evaluate if the subsequent packet + * should be sent, given that the device is not retranmitting the previous packet. + * On submission of the CMD_HID_TX, the radio will check if there are TX + * entries in the queue. If TX entires are present, the radio will start sending + * the packets as defined by the startTrigger. If no packets are present, the radio + * will enter a wait-state, waiting on CMD_TRIGGER_HID_TX. Once CMD_TRIGGER_HID_TX + * is submitted, the radio will re-evaluate the TX queue, and if packets are present + * , the radio will start sending the TX packets as defined by the startTrigger. + * If no entries in the TX queue has been submitted, or CMD_STOP/CMD_ABORT was + * submitted, the CMD_HID_TX will end and the radio is ready for another command. + * + * + *
+ * @anchor rf_hid_Usage + * # Usage + * + * This documentation provides basic @ref rf_hid_settings_c + * "rf_hid_settings.c", @ref rf_hid_settings_h + * "rf_hid_settings.h" and a set of @ref rf_hid_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor rf_hid_settings + * ## RF HID settings + * @anchor rf_hid_settings_c + * @code + * // Filename: rf_hid_settings.c + * + * // Import the settings header file + * #include "rf_hid_settings.h" + * + * // Import the RF driver definitions + * #include + * + * // Import the needed radio files + * #include + * #include DeviceFamily_constructPath(driverlib/rf_mailbox.h) + * #include DeviceFamily_constructPath(driverlib/rf_hid_cmd.h) + * #include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_multi_protocol.h) + * #include DeviceFamily_constructPath(driverlib/rf_data_entry.h) + * #include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) + * + * + * // TI-RTOS RF Mode Object + * RF_Mode RF_hid = + * { + * .rfMode = RF_MODE_PROPRIETARY, + * .cpePatchFxn = &rf_patch_cpe_multi_protocol, + * .mcePatchFxn = 0, + * .rfePatchFxn = 0 + * }; + * + * // TX and RX queue declarations + * uint8_t txEntry1[BUFFER_LEN]; + * uint8_t txEntry2[BUFFER_LEN]; + * uint8_t rxEntry1[BUFFER_LEN]; + * uint8_t rxEntry2[BUFFER_LEN]; + * + * dataQueue_t txQ = { + * .pCurrEntry = NULL, + * .pLastEntry = NULL, + * }; + * + * dataQueue_t rxQ = { + * .pCurrEntry = NULL, + * .pLastEntry = NULL, + * }; + * + * // Statistics + * rfc_hidRxTxOutput_t rxTxStatistics; + * + * // Override list. 64 us turnaround compatible with fastest setting + * // for CC254x devices + * #define TURNAROUND_TIME 64 // Turnaround time in usec + * uint32_t pOverridesCommon[] = + * { + * // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). + * (uint32_t)0x00F388D3, + * // Set pilot tone length to 4 us (enable phase error discard as early as possible) + * HW_REG_OVERRIDE(0x6024,0x0020), + * // Bluetooth 5: Default to no CTE. + * HW_REG_OVERRIDE(0x5328,0x0000), + * // Synth: Increase mid code calibration time to 5 us + * (uint32_t)0x00058683, + * // Synth: Increase mid code calibration time to 5 us + * HW32_ARRAY_OVERRIDE(0x4004,1), + * // Synth: Increase mid code calibration time to 5 us + * (uint32_t)0x38183C30, + * // HID: Reduce turnaround times: + * (uint32_t)((TURNAROUND_TIME*4)<<16)|0x0263, // modify tx to rx turnaround time + * (uint32_t)((TURNAROUND_TIME*4)<<16)|0x0283, // modify rx to tx turnaround time + * // Of of override list + * (uint32_t)0xFFFFFFFF + * }; + * + * // CMD_RADIO_SETUP + * // Radio setup for HID command + * rfc_CMD_RADIO_SETUP_t RF_cmdRadioSetup = + * { + * .commandNo = CMD_RADIO_SETUP, + * .status = 0x0000, + * .pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx + * .startTime = 0x00000000, + * .startTrigger.triggerType = 0x0, + * .startTrigger.bEnaCmd = 0x0, + * .startTrigger.triggerNo = 0x0, + * .startTrigger.pastTrig = 0x0, + * .condition.rule = 0x1, + * .condition.nSkip = 0x0, + * .mode = 0x2, // HID mode + * .loDivider = 0x00, + * .config.frontEndMode = 0x0, + * .config.biasMode = 0x0, + * .config.analogCfgMode = 0x0, + * .config.bNoFsPowerUp = 0x0, + * .txPower = 0x7217, + * .pRegOverride = pOverridesCommon, + * }; + * + * // CMD_FS + * // Frequency Synthesizer Programming Command + * rfc_CMD_FS_t RF_cmdFs = + * { + * .commandNo = 0x0803, + * .status = 0x0000, + * .pNextOp = 0, + * .startTime = 0x00000000, + * .startTrigger.triggerType = 0x0, + * .startTrigger.bEnaCmd = 0x0, + * .startTrigger.triggerNo = 0x0, + * .startTrigger.pastTrig = 0x1, + * .condition.rule = 0x1, + * .condition.nSkip = 0x0, + * .frequency = 2440, + * .fractFreq = 0x0000, + * .synthConf.bTxMode = 0x0, + * .synthConf.refFreq = 0x0, + * .__dummy0 = 0x00, + * .__dummy1 = 0x00, + * .__dummy2 = 0x00, + * .__dummy3 = 0x0000 + * }; + * + * // CMD_HID_TX + * // HID TX command + * rfc_CMD_HID_TX_t RF_cmdTxHID = + * { + * .commandNo = CMD_HID_TX, + * .status = 0x0000, + * .pNextOp = 0x00000000, + * .startTime = 0x00000000, + * .startTrigger.triggerType = 0x0, + * .startTrigger.bEnaCmd = 0x0, + * .startTrigger.triggerNo = 0x0, + * .startTrigger.pastTrig = 0x0, + * .condition.rule = COND_NEVER, + * .condition.nSkip = 0x0, + * .pktConf.bFsOff = 0x0, // Keep synth on + * .pktConf.bAutoRetransmit = 0x1, // Listen for ack and retransmit + * .pktConf.bVarLen = 0x1, // Variable length mode + * .pktConf.hdrMode = 0x0, // 9 bit mode + * .pktConf.bIncludeAddr = 0x1, // Include address after sync word + * .pktConf.hdrConf = 0x0, // Automatically generate header + * .pktConf.bFixedTxLen = 0x0, // Calculate length when sending packet + * .rxConf.bAutoFlushIgnored = 0x0, // Do not flush ignored packets + * .rxConf.bAutoFlushCrcErr = 0x1, // Flush packets with CRC error + * .rxConf.bIncludeAddr = 0x0, // Do not include address in queue + * .rxConf.bIncludeHdr = 0x1, // Include header in queue + * .rxConf.bIncludeCrc = 0x0, // Do not include CRC in queue + * .rxConf.bAppendStatus = 0x0, // Do not append status byte in queue + * .rxConf.bAppendTimestamp = 0x0, // Do not append time stamp of received packet in queue + * .syncWord = 0x29417671, + * .address = 0xEF, + * .seqNo = 0x00, + * .maxAckLen = 0x1E, // Maximum length of ack + * .pktLen = 32, // Packet is 32 bytes + * .maxRetrans = 3, // Maximum three retransmissions + * .noAckMode.noAckVal = 0, // Set automatic NO_ACK value to inverse of bAutoRetransmit + * .noAckMode.bAlwaysAutoRetransmit = 1, // Never disable auto retransmit + * .retransDelay = 0x1E, // Number of RAT ticks from start of transmission of a packet to retransmission + * .pPkt = 0, + * .pRxQueue = 0, + * .pOutput = 0, + * }; + * + * // CMD_HID_RX + * // HID RX command + * rfc_CMD_HID_RX_t RF_cmdRxHID = + * { + * .commandNo = CMD_HID_RX, + * .status = 0x0000, + * .pNextOp = 0x00000000, + * .startTime = 0x00000000, + * .startTrigger.triggerType = 0x0, + * .startTrigger.bEnaCmd = 0x0, + * .startTrigger.triggerNo = 0x0, + * .startTrigger.pastTrig = 0x0, + * .condition.rule = COND_NEVER, + * .condition.nSkip = 0x0, + * .pktConf.bFsOff = 0x0, // Keep synth on + * .pktConf.bRepeatOk = 1, // If packet was received OK, then end + * .pktConf.bRepeatNok = 1, // If packer was NOK, then go back to sync search + * .pktConf.hdrMode = 0x0, // 9 bit mode + * .pktConf.bIncludeAddr = 0x1, // Include address after sync word + * .pktConf.hdrConf = 0x0, // Automatically generate header + * .rxConf.bAutoFlushIgnored = 0x0, // Do not flush ignored packets + * .rxConf.bAutoFlushCrcErr = 0x0, // Do not flush packets with CRC error + * .rxConf.bIncludeAddr = 0x0, // Do not include address in queue + * .rxConf.bIncludeHdr = 0x0, // Do not include header in queue + * .rxConf.bIncludeCrc = 0x0, // Do not include CRC in queue + * .rxConf.bAppendRssi = 0x0, // Do not append RSSI in queue + * .rxConf.bAppendStatus = 0x0, // Do not append status byte in queue + * .rxConf.bAppendTimestamp = 0x0, // Do not append time stamp of received packet in queue + * .syncWord0 = 0x29417671, + * .syncWord1 = 0x0, + * .numAddr = 1, // Number of address entries in pAddrEntry + * .__dummy0 = 0, + * .__dummy1 = 0, + * .endTrigger.triggerType = 1, // Trig never + * .endTrigger.bEnaCmd = 0, + * .endTrigger.triggerNo = 0, + * .endTrigger.pastTrig = 0, + * .endTime = 0, + * .pAddrEntry = 0, //pointer to array of address entries + * .pRxQueue = 0, + * .pOutput = 0, + * }; + * + * // Struct used for the address entry + * rfc_hidAddrEntry_t addrEntry = + * { + * .addrConfig.ena0 = 1, // Enable entry for sync word 0 + * .addrConfig.ena1 = 0, // Disable entry for sync word 0 + * .addrConfig.autoAckMode = 2, // Always enable auto-acknowledgement for the entry + * .addrConfig.bVarLen = 1, // Use variable length in receiver when receiving packets + * .addrConfig.bFixedTxLen = 0, // Use actual length in header when sending ACK + * .maxPktLen = 100, + * .address = 0xEF, // Address of packet + * .pTxQueue = 0, // Pointer to transmit queue for acknowledgements in use for the address + * .crcVal = 0, + * }; + * @endcode + * + * @anchor rf_hid_settings_h + * @code + * // Filename: rf_hid_settings.h + * + * #include + * #include DeviceFamily_constructPath(driverlib/rf_mailbox.h) + * #include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) + * #include DeviceFamily_constructPath(driverlib/rf_hid_cmd.h) + * #include DeviceFamily_constructPath(driverlib/rf_data_entry.h) + * #include + * + * extern RF_Mode RF_hid; + * + * #define BUFFER_LEN 20 // Set the appropriate length here + * + * // RF Core API commands + * extern rfc_CMD_RADIO_SETUP_t RF_cmdRadioSetup; + * extern rfc_CMD_FS_t RF_cmdFs; + * extern rfc_CMD_HID_TX_t RF_cmdTxHID; + * extern rfc_CMD_HID_RX_t RF_cmdRxHID; + * extern rfc_hidAddrEntry_t addrEntry; + * + * // RF HID queue and statistics + * extern dataQueue_t txQ; + * extern dataQueue_t rxQ; + * extern uint8_t txEntry1[BUFFER_LEN]; + * extern uint8_t rxEntry1[BUFFER_LEN]; + * extern uint8_t txEntry2[BUFFER_LEN]; + * extern uint8_t rxEntry2[BUFFER_LEN]; + * extern rfc_hidRxTxOutput_t rxTxStatistics; + * + * @endcode + * + *
+ * @anchor rf_hid_Examples + * # Examples + * The following code example opens the RF driver, setup the radio for CMD_HID_TX, + * initiates the TX/RX queues so that the packet is being transmitted as fast + * as possible once the CMD_HID_TX is submitted. + * + * ### Using the RF CMD_HID_TX without trigger # + * The example below does not use the CMD_HID_TRIGGER_TX, since the + * queues are committed to the command before the RF_cmdTxHID is submitted. + * The radio will evaluate the TX queue as containing data and proceed to start the + * transmission. + * The radio will continue to send packets and receive ACK's as long as there are + * enough space in the queues to allow reception of ACK's, TX queue is filled and + * retramission count is below the threshold, and no other error has occured. + * The command will terminate if the RX queue ran out of free entries, + * or the maximum number of retransmissions (RF_cmdTxHID.maxRetrans) was done, + * or the CMD_STOP/CMD_ABORT command was submitted, + * or any error occured. + * If the TX queue runs out of valid entires, the radio will enter the same wait state + * as if command is submitted without committed TX queues. + * @code + * // Initialize the radio + * RF_Params rfParams; + * RF_Params_init(&rfParams); + * + * // Open the radio and submit setup command + * RF_Handle rfHandle = RF_open(pObj, &RF_hid, (RF_RadioSetup *)&RF_cmdRadioSetup, NULL); + * RF_runCmd(rfHandle, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, 0); + * // Initialize the queues + * rfc_dataEntryGeneral_t *txEntry = (rfc_dataEntryGeneral_t *)txEntry1; + * txEntry->pNextEntry = txEntry2; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * + * txEntry = (rfc_dataEntryGeneral_t *)txEntry2; + * txEntry->pNextEntry = txEntry1; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * txQ.pCurrEntry = txEntry1; + * txQ.pLastEntry = NULL; + * + * rfc_dataEntryGeneral_t *rxEntry = (rfc_dataEntryGeneral_t*)rxEntry1; + * rxEntry->pNextEntry = rxEntry2; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * + * rxEntry = (rfc_dataEntryGeneral_t*)rxEntry2; + * rxEntry->pNextEntry = rxEntry1; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * rxQ.pCurrEntry = rxEntry1; + * rxQ.pLastEntry = NULL; + * + * // Commit the queues and statistics to the TX command + * RF_cmdTxHID.pPkt = (uint8_t*)&txQ; + * RF_cmdTxHID.pRxQueue = &rxQ; + * RF_cmdTxHID.pOutput = &rxTxStatistics; + * + * // Submit the command and handle the queue fill/empty in the hidTxCb callback + * RF_runCmd(rfHandle, + * (RF_Op*)&RF_cmdTxHID, + * RF_PriorityNormal, + * &hidTxCb, + * RF_EventTxDone | RF_EventTxEntryDone | RF_EventRxEntryDone | RF_EventLastCmdDone); + * @endcode + * + * + * ### Using the RF CMD_HID_TX with trigger # + * The example below is using the CMD_HID_TRIGGER_TX to trigger the transmission of + * the TX packet and ACK reception. + * The setup for the command is the same as for the example without the trigger, with + * the only difference being that the queues are commited to the command after it has + * been submitted. + * This is a way to enable faster TX start up, compared to regular command submission. + * + * The example below is using the same data as the above. + * The transmission is then triggered 500 usec after CMD_HID_TX command submission. + * The delta between RF_runCmd(..., RF_cmdTxHID, ...) and TX start without trigger + * is greater than delta between RF_runDirectCmd(rfHandle, CMD_TRIGGER_HID_TX) and + * TX start, but will consume more power. + * + * @code + * // Initialize the radio + * RF_Params rfParams; + * RF_Params_init(&rfParams); + * + * // Open the radio and submit setup command + * RF_Handle rfHandle = RF_open(pObj, &RF_hid, (RF_RadioSetup *)&RF_cmdRadioSetup, NULL); + * RF_runCmd(rfHandle, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, 0); + * // Initialize the queues + * rfc_dataEntryGeneral_t *txEntry = (rfc_dataEntryGeneral_t *)txEntry1; + * txEntry->pNextEntry = txEntry2; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * + * txEntry = (rfc_dataEntryGeneral_t *)txEntry2; + * txEntry->pNextEntry = txEntry1; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * txQ.pCurrEntry = txEntry1; + * txQ.pLastEntry = NULL; + * + * rfc_dataEntryGeneral_t *rxEntry = (rfc_dataEntryGeneral_t*)rxEntry1; + * rxEntry->pNextEntry = rxEntry2; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * + * rxEntry = (rfc_dataEntryGeneral_t*)rxEntry2; + * rxEntry->pNextEntry = rxEntry1; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * rxQ.pCurrEntry = rxEntry1; + * rxQ.pLastEntry = NULL; + * + * RF_cmdTxHID.pRxQueue = &rxQ; + * RF_cmdTxHID.pOutput = &rxTxStatistics; + * + * // Submit the command and handle the queue fill/empty in the hidTxCb callback + * RF_CmdHandle ch = RF_postCmd(rfHandle, + * (RF_Op*)&RF_cmdTxHID, + * RF_PriorityNormal, + * &hidTxCb, + * RF_EventTxDone | RF_EventTxEntryDone | RF_EventRxEntryDone | RF_EventLastCmdDone); + * // Wait 500 usec + * usleep(500); + * + * // Commit the queues and statistics to the TX command + * RF_cmdTxHID.pPkt = (uint8_t*)&txQ; + * + * // Submit the trigger + * RF_runDirectCmd(rfHandle, CMD_TRIGGER_HID_TX); + * + * // Pend on the command end. + * RF_pendCmd(rfHandle, ch, RF_EventCmdDone); + * + * @endcode + * + * + * + * ### Using the RF CMD_HID_RX command # + * The CMD_HID_RX is not using the trigger as done with the CMD_HID_TX, instead + * the reception is handled by the startTrigger. + * + * The TX queues are used for sending the ACK's, and the TX queue to use is decided + * by the address entry, meaning that it's possible to have different TX queues for + * different received addresses, allowing for different ACK's for different addresses. + * + * If pktConf.bIncludeAddr is zero, meaning that no address is sent, the address entry + * used will be the first entry that matches the received sync word with the sync word + * ID in the address entry. + * + * The command will terminate if the RX queue is full, CMD_STOP/CMD_ABORT is being sent + * or if any error occured. + * + * An example of the CMD_HID_RX is shown below. + * @code + * // Initialize the radio + * RF_Params rfParams; + * RF_Params_init(&rfParams); + * + * // Open the radio and submit setup command + * RF_Handle rfHandle = RF_open(pObj, &RF_hid, (RF_RadioSetup *)&RF_cmdRadioSetup, NULL); + * RF_runCmd(rfHandle, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, 0); + * // Initialize the queues + * rfc_dataEntryGeneral_t *txEntry = (rfc_dataEntryGeneral_t *)txEntry1; + * txEntry->pNextEntry = txEntry2; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * + * txEntry = (rfc_dataEntryGeneral_t *)txEntry2; + * txEntry->pNextEntry = txEntry1; + * txEntry->status = DATA_ENTRY_PENDING; + * txEntry->config.type = DATA_ENTRY_TYPE_GEN; + * txEntry->config.irqIntv = 0; + * txEntry->config.lenSz = 0; + * txEntry->config.type = 0; + * txEntry->length = 10; // Set the appropriate length here + * + * rfc_dataEntryGeneral_t *rxEntry = (rfc_dataEntryGeneral_t*)rxEntry1; + * rxEntry->pNextEntry = rxEntry2; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * + * rxEntry = (rfc_dataEntryGeneral_t*)rxEntry2; + * rxEntry->pNextEntry = rxEntry1; + * rxEntry->status = DATA_ENTRY_PENDING; + * rxEntry->config.type = DATA_ENTRY_TYPE_GEN; + * rxEntry->config.lenSz = 1; + * rxEntry->length = BUFFER_LEN-8; + * rxQ.pCurrEntry = rxEntry1; + * rxQ.pLastEntry = NULL; + * + * // Attach the TX queue to the address entry. Used for ACK's + * addrEntry.pTxQueue = &txQ; + * RF_cmdRxHID.pAddrEntry = &addrEntry; + * RF_cmdRxHID.pRxQueue = &rxQ; + * RF_cmdRxHID.pOutput = &rxTxStatistics; + * + * // Submit the command and handle the queue fill/empty in the hidRxCb callback + * RF_runCmd(rfHandle, + * (RF_Op*)&RF_cmdRxHID, + * RF_PriorityNormal, + * &hidRxCb, + * RF_EventTxDone | RF_EventTxEntryDone | RF_EventRxEntryDone | RF_EventLastCmdDone); + * @endcode + * + * + *
+ * + * ============================================================================ + */ +#ifndef __HID_CMD_H +#define __HID_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup hid_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_HID_TX_s rfc_CMD_HID_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_HID_RX_s rfc_CMD_HID_RX_t; +typedef struct __RFC_STRUCT rfc_hidAddrEntry_s rfc_hidAddrEntry_t; +typedef struct __RFC_STRUCT rfc_hidRxTxOutput_s rfc_hidRxTxOutput_t; +typedef struct __RFC_STRUCT rfc_hidRxStatus_s rfc_hidRxStatus_t; + +//! \addtogroup CMD_HID_TX +//! @{ +#define CMD_HID_TX 0x5801 +//! HID Transmit Command with Auto Retransmission +struct __RFC_STRUCT rfc_CMD_HID_TX_s { + uint16_t commandNo; //!< The command ID number 0x5801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bAutoRetransmit:1; //!< \brief 0: Do not listen for ACK
+ //!< 1: Listen for ACK and retransmit if missing + uint8_t bVarLen:1; //!< \brief 0: Fixed length mode
+ //!< 1: Variable length mode + uint8_t hdrMode:1; //!< \brief 0: 9-bit header
+ //!< 1: 10-bit header + uint8_t bIncludeAddr:1; //!< \brief 0: Do not include address byte after sync word
+ //!< 1: Include address byte after sync word + uint8_t hdrConf:2; //!< \brief 0: Automatically generate header (no header byte in buffer\)
+ //!< 1: Insert NO_ACK field from TX buffer
+ //!< 2: Insert SEQ field from TX buffer
+ //!< 3: Insert SEQ and NO_ACK field from TX buffer + uint8_t bFixedTxLen:1; //!< \brief 0: Use actual length in header when sending packet
+ //!< 1: Use fixed word in length field of header when sending packet + //!< (only for peer without variable length packets) + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets (RX) or empty ACKs (TX) from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeAddr:1; //!< If 1, the received address byte is included in the Rx queue + uint8_t bIncludeHdr:1; //!< If 1, the received header is included in the Rx queue + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; //!< Receive entry configuration + uint32_t syncWord; //!< Sync word to send + uint8_t address; //!< Address byte + uint8_t seqNo; //!< Sequence number to use for next packet + uint8_t maxAckLen; //!< Maximum length of ACKs + uint8_t pktLen; //!< Length of transmitted packet + uint8_t maxRetrans; //!< Maximum number of retransmissions + struct { + uint8_t noAckVal:2; //!< \brief 0: Set automatic NO_ACK value to inverse of bAutoRetransmit
+ //!< 1: Set automatic NO_ACK value to bAutoRetransmit
+ //!< 2: Set automatic NO_ACK value to 0
+ //!< 3: Set automatic NO_ACK value to 1 + uint8_t bAlwaysAutoRetransmit:1; //!< \brief 0: Disable auto retransmit if transmitted NO_ACK was 1
+ //!< 1: Never disable auto retransmit + } noAckMode; + uint16_t retransDelay; //!< Number of RAT ticks from start of transmission of a packet to retransmission + uint8_t* pPkt; //!< Pointer to transmit queue for packets + dataQueue_t* pRxQueue; //!< Pointer to receive queue for ACKs + rfc_hidRxTxOutput_t *pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_HID_RX +//! @{ +#define CMD_HID_RX 0x5802 +//! HID Recieve Command with Auto Ack +struct __RFC_STRUCT rfc_CMD_HID_RX_s { + uint16_t commandNo; //!< The command ID number 0x5802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t hdrMode:1; //!< \brief 0: 9-bit header
+ //!< 1: 10-bit header + uint8_t bIncludeAddr:1; //!< \brief 0: Include address byte after sync word
+ //!< 1: Do not include address byte after sync word + uint8_t hdrConf:2; //!< \brief 0: Automatically generate header (no header byte in buffer) + //!< 1: Insert NO_ACK field from TX buffer + //!< 2: Insert SEQ field from TX buffer + //!< 3: Insert SEQ and NO_ACK field from TX buffer + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets (RX) or empty ACKs (TX) from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeAddr:1; //!< If 1, the received address byte is included in the Rx queue + uint8_t bIncludeHdr:1; //!< If 1, the received header is included in the Rx queue + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; //!< Receive entry configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint8_t numAddr; //!< Number of address entries + uint8_t __dummy0; + uint8_t __dummy1; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + rfc_hidAddrEntry_t *pAddrEntry; //!< Pointer to array of address entries + dataQueue_t* pRxQueue; //!< Pointer to receive queue + rfc_hidRxTxOutput_t *pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hidAddrEntry +//! @{ +//! Address entry structure for CMD_HID_RX + +struct __RFC_STRUCT rfc_hidAddrEntry_s { + struct { + uint8_t ena0:1; //!< \brief 0: Disable entry for syncWord0
+ //!< 1: Enable entry for syncWord0 + uint8_t ena1:1; //!< \brief 0: Disable entry for syncWord1
+ //!< 1: Enable entry for syncWord1 + uint8_t autoAckMode:2; //!< \brief 0: Always disable auto-acknowledgement for the entry
+ //!< 1: Always enable auto-acknowledgement for the entry
+ //!< 2: Enable auto-acknowledgement for the entry only if received NO_ACK bit is 0
+ //!< 3: Enable auto-acknowledgement for the entry only if received NO_ACK bit is 1 + uint8_t bVarLen:1; //!< \brief 0: Use fixed length given by maxPktLen in receiver when receiving packets
+ //!< 1: Use variable length in receiver when receiving packets + uint8_t bFixedTxLen:1; //!< \brief 0: Use actual length in header when sending ACK + //!< 1: Use fixed word in length field of header when sending ACK and no payload + //!< (only for peer without variable length ACKs) + } addrConfig; + uint8_t maxPktLen; //!< Packet length for fixed length, maximum packet length for variable length + uint8_t address; //!< Address byte of packet + struct { + uint8_t bValid:1; //!< \brief 0: The status is not valid. Any packet is viewed as new.
+ //!< 1: The status is valid. Only packets with a sequence number and CRC different + //!< from the previous one are accepted. + uint8_t seq:2; //!< Sequence number of last successfully received packet + uint8_t ackSeq:2; //!< Sequence number of the next or current ACK to be transmitted + uint8_t bAckPayloadSent:1; //!< \brief 0: The last received packet was not acknowledged with payload.
+ //!< 1: The last received packet was acknowledged with payload. + } seqStat; + dataQueue_t* pTxQueue; //!< Pointer to transmit queue for acknowledgements in use for the address + uint16_t crcVal; //!< CRC value (last two bytes if more than 2 CRC bytes) of last successfully received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hidRxTxOutput +//! @{ +//! Output structure for CMD_HID_RX and CMD_HID_TX + +struct __RFC_STRUCT rfc_hidRxTxOutput_s { + uint8_t nTx; //!< Number of packets or acknowledgements transmitted + uint8_t nRxOk; //!< Number of packets that have been received with CRC OK + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets ignored as retransmissions or empty ACKs + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + uint8_t nRxAborted; //!< Number of packets not received due to device address mismatch, invalid length, or abort command + uint8_t __dummy0; + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hidRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_hidRxStatus_s { + struct { + uint8_t addrInd:5; //!< Index of address found + uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_mailbox.h new file mode 100644 index 00000000..f6e290d4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hid_mailbox.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* Filename: rf_hid_mailbox.h +* +* Description: Definitions for HID interface +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _HID_MAILBOX_H +#define _HID_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define HID_DONE_OK 0x5400 ///< Operation ended normally +#define HID_DONE_RXTIMEOUT 0x5401 ///< Operation stopped after end trigger while waiting for sync +#define HID_DONE_NOSYNC 0x5402 ///< Timeout of subsequent Rx +#define HID_DONE_RXERR 0x5403 ///< Operation ended after CRC error +#define HID_DONE_ENDED 0x5404 ///< Operation stopped after end trigger during reception +#define HID_DONE_STOPPED 0x5405 ///< Operation stopped after stop command +#define HID_DONE_ABORT 0x5406 ///< Operation aborted by abort command +///@} +/// \name Operation finished with error +///@{ +#define HID_ERROR_PAR 0x5800 ///< Illegal parameter +#define HID_ERROR_RXBUF 0x5801 ///< No available Rx buffer at the start of a packet +#define HID_ERROR_NO_SETUP 0x5802 ///< Radio was not set up in a compatible mode +#define HID_ERROR_NO_FS 0x5803 ///< Synth was not programmed when running Rx or Tx +#define HID_ERROR_RXOVF 0x5804 ///< Rx overflow observed during operation +#define HID_ERROR_TXUNF 0x5805 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_cmd.h new file mode 100644 index 00000000..59def954 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_cmd.h @@ -0,0 +1,208 @@ +/****************************************************************************** +* Filename: rf_hs_cmd.h +* +* Description: CC13x2/CC26x2 API for high-speed mode commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HS_CMD_H +#define __HS_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup hs_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; +typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t; +typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; + +//! \addtogroup CMD_HS_TX +//! @{ +#define CMD_HS_TX 0x3841 +//! High-Speed Transmit Command +struct __RFC_STRUCT rfc_CMD_HS_TX_s { + uint16_t commandNo; //!< The command ID number 0x3841 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first half-word + uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
+ //!< 1: Check if Tx queue is empty when packet has been transmitted + } pktConf; + uint8_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to Tx queue +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_HS_RX +//! @{ +#define CMD_HS_RX 0x3842 +//! High-Speed Receive Command +struct __RFC_STRUCT rfc_CMD_HS_RX_s { + uint16_t commandNo; //!< The command ID number 0x3842 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC
+ //!< 1: Receive and check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t addressMode:2; //!< \brief 0: No address check
+ //!< 1: Accept address0 and address1
+ //!< 2: Accept address0, address1, and 0x0000
+ //!< 3: Accept address0, address1, 0x0000, and 0xFFFF + } pktConf; + struct { + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it + uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; + uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length + uint16_t address0; //!< Address + uint16_t address1; //!< Address (set equal to address0 to accept only one address) + uint8_t __dummy0; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxOutput +//! @{ +//! Output structure for CMD_HS_RX + +struct __RFC_STRUCT rfc_hsRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with CRC OK + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup hsRxStatus +//! @{ +//! Receive status word that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_hsRxStatus_s { + struct { + uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed) + uint16_t bCrcErr:1; //!< \brief 0: Packet received OK
+ //!< 1: Packet received with CRC error + uint16_t addressInd:2; //!< \brief 0: Received address0 (or no address check)
+ //!< 1: Received address1
+ //!< 2: Received address 0x0000
+ //!< 3: Received address 0xFFFF + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_mailbox.h new file mode 100644 index 00000000..eb8fecf9 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_hs_mailbox.h @@ -0,0 +1,63 @@ +/****************************************************************************** +* Filename: rf_hs_mailbox.h +* +* Description: Definitions for high-speed mode radio interface +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _HS_MAILBOX_H +#define _HS_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define HS_DONE_OK 0x3440 ///< Operation ended normally +#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync +#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error +#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation +#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception +#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command +#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command +///@} +/// \name Operation finished with error +///@{ +#define HS_ERROR_PAR 0x3840 ///< Illegal parameter +#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet +#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode +#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx +#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation +#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_cmd.h new file mode 100644 index 00000000..2d1cc8d7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_cmd.h @@ -0,0 +1,626 @@ +/****************************************************************************** +* Filename: rf_ieee_cmd.h +* +* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __IEEE_CMD_H +#define __IEEE_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup ieee_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t; +typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t; +typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t; +typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t; +typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; + +//! \addtogroup CMD_IEEE_RX +//! @{ +#define CMD_IEEE_RX 0x2801 +//! IEEE 802.15.4 Receive Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { + uint16_t commandNo; //!< The command ID number 0x2801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue + uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue + uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; + dataQueue_t* pRxQ; //!< Pointer to receive queue + rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results) + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } frameFiltOpt; //!< Frame filtering options + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } frameTypes; //!< Frame types to receive in frame filtering + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + uint8_t numExtEntries; //!< Number of extended address entries + uint8_t numShortEntries; //!< Number of short address entries + uint32_t* pExtEntryList; //!< Pointer to list of extended address entries + uint32_t* pShortEntryList; //!< Pointer to list of short address entries + uint64_t localExtAddr; //!< The extended address of the local device + uint16_t localShortAddr; //!< The short address of the local device + uint16_t localPanID; //!< The PAN ID of the local device + uint16_t __dummy1; + uint8_t __dummy2; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ED_SCAN +//! @{ +#define CMD_IEEE_ED_SCAN 0x2802 +//! IEEE 802.15.4 Energy Detect Scan Command +struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { + uint16_t commandNo; //!< The command ID number 0x2802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_TX +//! @{ +#define CMD_IEEE_TX 0x2C01 +//! IEEE 802.15.4 Transmit Command +struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { + uint16_t commandNo; //!< The command ID number 0x2C01 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically
+ //!< 1: Insert PHY header from the buffer + uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC
+ //!< 1: Insert FCS (CRC) from the buffer + uint8_t :1; + uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long + //!< non-standard packets for test purposes + } txOpt; + uint8_t payloadLen; //!< Number of bytes in the payload + uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen + ratmr_t timeStamp; //!< Time stamp of transmitted frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CSMA +//! @{ +#define CMD_IEEE_CSMA 0x2C02 +//! IEEE 802.15.4 CSMA-CA Command +struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { + uint16_t commandNo; //!< The command ID number 0x2C02 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t randomState; //!< The state of the pseudo-random generator + uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE + uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs + struct { + uint8_t initCW:5; //!< The initialization value for the CW parameter + uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA
+ //!< 1: slotted CSMA + uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, + //!< or after finishing it (including auto ACK) otherwise
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs + } csmaConfig; + uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown + int8_t lastRssi; //!< RSSI measured at the last CCA operation + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation + ratmr_t lastTimeStamp; //!< Time of the last CCA operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< CSMA-CA operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_RX_ACK +//! @{ +#define CMD_IEEE_RX_ACK 0x2C03 +//! IEEE 802.15.4 Receive Acknowledgement Command +struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { + uint16_t commandNo; //!< The command ID number 0x2C03 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t seqNo; //!< Sequence number to expect + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up + //!< acknowledgement reception +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_BG +//! @{ +#define CMD_IEEE_ABORT_BG 0x2C04 +//! IEEE 802.15.4 Abort Background Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { + uint16_t commandNo; //!< The command ID number 0x2C04 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_CCA +//! @{ +#define CMD_IEEE_MOD_CCA 0x2001 +//! IEEE 802.15.4 Modify CCA Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { + uint16_t commandNo; //!< The command ID number 0x2001 + struct { + uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } newCcaOpt; //!< New value of ccaOpt for the running background level operation + int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_FILT +//! @{ +#define CMD_IEEE_MOD_FILT 0x2002 +//! IEEE 802.15.4 Modify Frame Filtering Parameter Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { + uint16_t commandNo; //!< The command ID number 0x2002 + struct { + uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation + struct { + uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } newFrameTypes; //!< New value of frameTypes for the running background level operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_MOD_SRC_MATCH +//! @{ +#define CMD_IEEE_MOD_SRC_MATCH 0x2003 +//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command +struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { + uint16_t commandNo; //!< The command ID number 0x2003 + struct { + uint8_t bEnable:1; //!< \brief 0: Disable entry
+ //!< 1: Enable entry + uint8_t srcPend:1; //!< New value of the pending bit for the entry + uint8_t entryType:1; //!< \brief 0: Short address
+ //!< 1: Extended address + } options; + uint8_t entryNo; //!< Index of entry to enable or disable +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_ABORT_FG +//! @{ +#define CMD_IEEE_ABORT_FG 0x2401 +//! IEEE 802.15.4 Abort Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { + uint16_t commandNo; //!< The command ID number 0x2401 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_STOP_FG +//! @{ +#define CMD_IEEE_STOP_FG 0x2402 +//! IEEE 802.15.4 Gracefully Stop Foreground Level Command +struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { + uint16_t commandNo; //!< The command ID number 0x2402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_IEEE_CCA_REQ +//! @{ +#define CMD_IEEE_CCA_REQ 0x2403 +//! IEEE 802.15.4 CCA and RSSI Information Request Command +struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { + uint16_t commandNo; //!< The command ID number 0x2403 + int8_t currentRssi; //!< The RSSI currently observed on the channel + int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started + struct { + uint8_t ccaState:2; //!< \brief Value of the current CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy + } ccaInfo; +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxOutput +//! @{ +//! Output structure for CMD_IEEE_RX + +struct __RFC_STRUCT rfc_ieeeRxOutput_s { + uint8_t nTxAck; //!< Total number of transmitted ACK frames + uint8_t nRxBeacon; //!< Number of received beacon frames + uint8_t nRxData; //!< Number of received data frames + uint8_t nRxAck; //!< Number of received acknowledgement frames + uint8_t nRxMacCmd; //!< Number of received MAC command frames + uint8_t nRxReserved; //!< Number of received frames with reserved frame type + uint8_t nRxNok; //!< Number of received frames with CRC error + uint8_t nRxIgnored; //!< Number of frames received that are to be ignored + uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full + int8_t lastRssi; //!< RSSI of last received frame + int8_t maxRssi; //!< Highest RSSI observed in the operation + uint8_t __dummy0; + ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup shortAddrEntry +//! @{ +//! Structure for short address entries + +struct __RFC_STRUCT rfc_shortAddrEntry_s { + uint16_t shortAddr; //!< Short address + uint16_t panId; //!< PAN ID +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeRxCorrCrc +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { + struct { + uint8_t corr:6; //!< The correlation value + uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise + uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_coex.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_coex.h new file mode 100644 index 00000000..dc8f7b1f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_coex.h @@ -0,0 +1,207 @@ +/****************************************************************************** +* Filename: rf_ieee_coex.h +* +* Description: CC13x2/CC26x2 API for Co-Existance (CoEx) support in IEEE +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __RF_IEEE_COEX_H +#define __RF_IEEE_COEX_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup rf_ieee_coex +//! @{ + +#include +#include "rf_mailbox.h" + +// Error code for GRANT signal not given +#define IEEE_ERROR_NO_GRANT 0x2806 + +typedef struct __RFC_STRUCT rfc_ieeeCoexGlobalEnable_s rfc_ieeeCoexGlobalEnable_t; +typedef struct __RFC_STRUCT rfc_ieeeCoExConfig_s rfc_ieeeCoExConfig_t; + +//! \addtogroup ieeeCoexGlobalEnable +//! @{ +struct __RFC_STRUCT rfc_ieeeCoexGlobalEnable_s { + uint32_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint32_t __dummy3; + uint32_t __dummy4; + uint32_t __dummy5; + uint32_t __dummy6; + uint32_t __dummy7; + uint32_t __dummy8; + uint32_t __dummy9; + uint32_t __dummy10; + uint32_t __dummy11; + uint32_t __dummy12; + uint32_t __dummy13; + uint32_t __dummy14; + uint32_t __dummy15; + uint32_t __dummy16; + uint32_t __dummy17; + uint32_t __dummy18; + uint32_t __dummy19; + uint32_t __dummy20; + uint32_t __dummy21; + uint32_t __dummy22; + uint32_t __dummy23; + uint32_t __dummy24; + uint32_t __dummy25; + uint32_t __dummy26; + uint32_t __dummy27; + uint32_t __dummy28; + uint32_t __dummy29; + uint32_t __dummy30; + uint32_t __dummy31; + uint32_t __dummy32; + uint32_t __dummy33; + uint32_t __dummy34; + uint16_t __dummy35; + uint8_t __dummy36; + uint8_t coExGlobalEnable; //!< 0 = CoEx features disabled. All other values = CoEx enabled. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup ieeeCoExConfig +//! @{ +struct __RFC_STRUCT rfc_ieeeCoExConfig_s { + struct { + uint8_t bCoExEnable:1; //!< \brief 0: CoEx disabled + //!< 1: CoEx enabled + uint8_t bUseREQUEST:1; //!< \brief 0: REQUEST signal inactive + //!< 1: REQUEST signal active + uint8_t bUseGRANT:1; //!< \brief 0: GRANT signal inactive + //!< 1: GRANT signal active + uint8_t bUsePRIORITY:1; //!< \brief 0: PRIORITY signal inactive + //!< 1: PRIORITY signal active + uint8_t bRequestForChain:1; //!< \brief 0: Deassert REQUEST after each RF command + //!< 1: Keep REQUEST asserted for entire command chain + } coExEnable; + uint8_t coExTxRxIndication; //!< \brief 0 = RX indication is 0, TX indication is 0 + //!< 1 = RX indication is 0, TX indication is 1 + //!< 2 = RX indication is 1, TX indication is 0 + //!< 3 = RX indication is 1, RX indication is 1 + uint16_t priorityIndicationTime; //!< Time (in us) that the PRIORITY signal will indicate the priority. + struct { + uint8_t bRequestAsserted:1; //!< \brief READ ONLY. 0 = REQUEST not asserted, 1 = REQUEST is asserted. + //!< Will indicate if REQUEST would have been asserted, except if signal is not used. + uint8_t bIgnoreGrantInRxAsserted:1;//!< \brief READ ONLY. 0 = GRANT is checked in RX, 1 = GRANT is not checked in RX + //!< Will indicate if the current running command is ignoring GRANT in RX + } rfCoreCoExStatus; + struct { + uint8_t bUseOverridePriority:1; //!< \brief Bit to override default priority + //!< 0: Use default priority + //!< 1: use overridePriority priority for entire chain + uint8_t overridePriority:1; //!< \brief Priority to use if priority is overridden + //!< 0: Low priority if bUseOverridePriority = 1 + //!< 1: High priority if bUseOverridePriority = 1 + uint8_t bUseOverrideRequestForRx:1;//!< \brief Bit to override default request for RX + //!< 0: Use default request for RX + //!< 1: use overrideRequestForRx for entire chain + uint8_t overrideRequestForRx:1; //!< \brief REQUEST signal override if bUseOverrideRequestForRx = 1, used for entire chain + //!< 0: Don't request for RX if bUseOverrideRequestForRx = 1 + //!< 1: Request for RX if bUseOverrideRequestForRx = 1 + } overrideConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdIeeeRxConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdIeeeRxAckConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdIeeeCcaConfig; + struct { + uint8_t defaultPriority:1; //!< \brief 0: Default low priority + //!< 1: Default high priority + uint8_t bAssertRequestForRx:1; //!< \brief Default "request for RX" behaviour + //!< 0: Assert REQUEST for TX operations only + //!< 1: Assert REQUEST for both RX and TX operations + uint8_t bIgnoreGrantInRx:1; //!< \brief 0: Check GRANT in RX and TX + //!< 1: Ignore GRANT in RX, check GRANT in TX. Independent of asserting REQUEST for RX. + uint8_t bKeepRequestIfNoGrant:1; //!< \brief 0: Deassert REQUEST if GRANT was not given + //!< 1: Keep REQUEST asserted if no GRANT was given + } cmdIeeeTxConfig; + uint8_t grantLatencyTime; //!< \brief Grant Response Time to Request Signal. + //!< Request signal will be asserted Radio activity start time - grantLatencyTime + //!< 20 us <= grantLatencyTime <= 80 us +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_mailbox.h new file mode 100644 index 00000000..a34b7db7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_ieee_mailbox.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* Filename: rf_ieee_mailbox.h +* +* Description: Definitions for IEEE 802.15.4 interface +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _IEEE_MAILBOX_H +#define _IEEE_MAILBOX_H + +#include "rf_mailbox.h" + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IEEE_SUSPENDED 0x2001 ///< Operation suspended +///@} +/// \name Operation finished normally +///@{ +#define IEEE_DONE_OK 0x2400 ///< Operation ended normally +#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure +#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command +#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared +#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set +#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout +#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level + ///< operation ended +#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command +///@} +/// \name Operation finished with error +///@{ +#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter +#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode +#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured +#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time +#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation +#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation +///@} +///@} + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_mailbox.h new file mode 100644 index 00000000..057fca68 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_mailbox.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: rf_mailbox.h +* +* Description: Definitions for interface between system and radio CPU +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _MAILBOX_H +#define _MAILBOX_H + +#include +#include + + +/// \name RF mode values +/// Defines used to indicate mode of operation to radio core. +///@{ +#define RF_MODE_AUTO 0x00 +#define RF_MODE_BLE 0x00 +#define RF_MODE_IEEE_15_4 0x00 +#define RF_MODE_PROPRIETARY_2_4 0x00 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x00 +///@} + + +/// Type definition for RAT +typedef uint32_t ratmr_t; + + + +/// Type definition for a data queue +typedef struct { + uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue +} dataQueue_t; + + + +/// \name CPE interrupt definitions +/// Interrupt masks for the CPE interrupt in RDBELL. +///@{ +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state +#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state +#define IRQN_PA_CHANGED 14 ///< PA is changed +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished + +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed + +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) + +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) + +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) + +#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) +#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) +#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) + +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +///@} + + + +/// \name CMDSTA values +/// Values returned in result byte of CMDSTA +///@{ +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed + +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the + ///< command is not a direct command +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context + ///< where it is not supported +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled + ///< while another operation was already running in the RF core +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed + ///< on submission. +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was + ///< not supported by the queue in its current state +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry + ///< was busy +///@} + + + +/// \name Macros for sending direct commands +///@{ +/// Direct command with no parameter +#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) + +/// Direct command with 1-byte parameter +#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) + +/// Direct command with 2-byte parameter +#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) + +///@} + + + +/// \name Definitions for trigger types +///@{ +#define TRIG_NOW 0 ///< Triggers immediately +#define TRIG_NEVER 1 ///< Never trigs +#define TRIG_ABSTIME 2 ///< Trigs at an absolute time +#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted +#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started +#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started +#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started +#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended +#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1" +#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2" +#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer +#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if + ///< trigger happened in the past +///@} + + +/// \name Definitions for conditional execution +///@{ +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned + ///< False +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned + ///< False +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of + ///< commands if it returned False +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next + ///< command if it returned False +///@} + + + +/// \name Radio operation status +///@{ +/// \name Operation not finished +///@{ +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +///@} +/// \name Operation finished normally +///@{ +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +///@} +/// \name Operation finished with error +///@{ +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio + ///< operation command +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +///@} +///@} + + +/// \name Data entry types +///@{ +#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry +#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type +#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type +#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type +///@ + + +/// \name Data entry statuses +///@{ +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +///@} + + +/// \name Macros for RF register override +///@{ +/// Macro for ADI half-size value-mask combination +#define ADI_VAL_MASK(addr, mask, value) \ +(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ + ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) +/// 32-bit write of 16-bit value +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +/// ADI register, full-size write +#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, full-size write +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ +(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) +/// ADI register, half-size read-modify-write +#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ +(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) +/// 2 ADI registers, half-size read-modify-write +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ +(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + +/// 16-bit SW register as defined in radio_par_def.txt +#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) +/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). +#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ +(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) +/// 8-bit SW register as defined in radio_par_def.txt +#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ +(((uint32_t)(val) & 0xFF) << 16)) +/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. +#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ +((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) + +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ +((uint32_t)(length) << 16) | (1U << 30)) +#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) +#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ +((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) +#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ +((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \ + (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\ + ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ + ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ + (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) +#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) +#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) +#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) +#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ + (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) +#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ + ((centerFreq) << 20)) +#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ + ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ + (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ + (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ + (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ + (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ + (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ + (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ + (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ + 0x09) << 4)) // Use illegal value for illegal address range +/// End of string for override register +#define END_OVERRIDE 0xFFFFFFFF + + +/// ADI address-value pair +#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) +#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) + +/// Low half-word +#define LOWORD(value) ((value) & 0xFFFF) +/// High half-word +#define HIWORD(value) ((value) >> 16) +///@} + + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_cmd.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_cmd.h new file mode 100644 index 00000000..1e83d8b1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_cmd.h @@ -0,0 +1,1185 @@ +/****************************************************************************** +* Filename: rf_prop_cmd.h +* +* Description: CC13x2/CC26x2 API for Proprietary mode commands +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __PROP_CMD_H +#define __PROP_CMD_H + +#ifndef __RFC_STRUCT +#define __RFC_STRUCT +#endif + +#ifndef __RFC_STRUCT_ATTR +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) +#else +#define __RFC_STRUCT_ATTR +#endif +#endif + +//! \addtogroup rfc +//! @{ + +//! \addtogroup prop_cmd +//! @{ + +#include +#include "rf_mailbox.h" +#include "rf_common_cmd.h" + +typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_CS_s rfc_CMD_PROP_CS_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s rfc_CMD_PROP_RX_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s rfc_CMD_PROP_RX_ADV_SNIFF_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s rfc_CMD_PROP_RADIO_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t; +typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t; +typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t; +typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; + +//! \addtogroup carrierSense +//! @{ +struct __RFC_STRUCT rfc_carrierSense_s { + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX +//! @{ +#define CMD_PROP_TX 0x3801 +//! Proprietary Mode Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_s { + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX +//! @{ +#define CMD_PROP_RX 0x3802 +//! Proprietary Mode Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_s { + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_TX_ADV +//! @{ +#define CMD_PROP_TX_ADV 0x3803 +//! Proprietary Mode Advanced Transmit Command +struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t :2; + uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct { + uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV +//! @{ +#define CMD_PROP_RX_ADV 0x3804 +//! Proprietary Mode Advanced Receive Command +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_CS +//! @{ +#define CMD_PROP_CS 0x3805 +//! Carrier Sense Command +struct __RFC_STRUCT rfc_CMD_PROP_CS_s { + uint16_t commandNo; //!< The command ID number 0x3805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOffIdle:1; //!< \brief 0: Keep synth running if command ends with channel Idle
+ //!< 1: Turn off synth if command ends with channel Idle + uint8_t bFsOffBusy:1; //!< \brief 0: Keep synth running if command ends with channel Busy
+ //!< 1: Turn off synth if command ends with channel Busy + } csFsConf; + uint8_t __dummy0; + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_SETUP +//! @{ +#define CMD_PROP_RADIO_SETUP 0x3806 +//! Proprietary Mode Radio Setup Command for 2.4 GHz +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP +//! @{ +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +//! Proprietary Mode Radio Setup Command for All Frequency Bands +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { + uint16_t commandNo; //!< The command ID number 0x3807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_SNIFF +//! @{ +#define CMD_PROP_RX_SNIFF 0x3808 +//! Proprietary Mode Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen:1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress:1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RX_ADV_SNIFF +//! @{ +#define CMD_PROP_RX_ADV_SNIFF 0x3809 +//! Proprietary Mode Advanced Receive Command with Sniff Mode +struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { + uint16_t commandNo; //!< The command ID number 0x3809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct { + uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t :1; + uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct { + uint16_t numHdrBits:6; //!< Number of bits in header (0--32) + uint16_t lenPos:5; //!< Position of length field in header (0--31) + uint16_t numLenBits:5; //!< Number of bits in length field (0--16) + } hdrConf; + struct { + uint16_t addrType:1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr:5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct { + uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion + uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct { + uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation +} __RFC_STRUCT_ATTR; + +//! @} + +#define CMD_PROP_RADIO_SETUP_PA CMD_PROP_RADIO_SETUP + +//! \addtogroup CMD_PROP_RADIO_SETUP_PA +//! @{ +//! Proprietary Mode Radio Setup Command for 2.4 GHz with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +#define CMD_PROP_RADIO_DIV_SETUP_PA CMD_PROP_RADIO_DIV_SETUP + +//! \addtogroup CMD_PROP_RADIO_DIV_SETUP_PA +//! @{ +//! Proprietary Mode Radio Setup Command for All Frequency Bands with PA Switching Fields +struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s { + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct { + uint8_t triggerType:4; //!< The type of trigger + uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct { + uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct { + uint16_t modType:3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz:2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct { + uint32_t preScale:8; //!< Prescaler value + uint32_t rateWord:21; //!< Rate word + uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct { + uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct { + uint16_t nSwBits:6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode:4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t :1; + uint16_t whitenMode:3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct { + uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode:1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + uint16_t :1; + uint16_t bSynthNarrowBand:1; //!< \brief 0: Normal synth mode
+ //!< 1: Narrow-band synth mode + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 + uint8_t __dummy0; + uint16_t __dummy1; + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_SET_LEN +//! @{ +#define CMD_PROP_SET_LEN 0x3401 +//! Set Packet Length Command +struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup CMD_PROP_RESTART_RX +//! @{ +#define CMD_PROP_RESTART_RX 0x3402 +//! Restart Packet Command +struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { + uint16_t commandNo; //!< The command ID number 0x3402 +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxOutput +//! @{ +//! Output structure for RX operations + +struct __RFC_STRUCT rfc_propRxOutput_s { + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet +} __RFC_STRUCT_ATTR; + +//! @} + +//! \addtogroup propRxStatus +//! @{ +//! Receive status byte that may be appended to message in receive buffer + +struct __RFC_STRUCT rfc_propRxStatus_s { + struct { + uint8_t addressInd:5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; +} __RFC_STRUCT_ATTR; + +//! @} + +//! @} +//! @} +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_mailbox.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_mailbox.h new file mode 100644 index 00000000..9e811f3a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rf_prop_mailbox.h @@ -0,0 +1,69 @@ +/****************************************************************************** +* Filename: rf_prop_mailbox.h +* +* Description: Definitions for proprietary mode radio interface +* +* Copyright (c) 2015 - 2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _PROP_MAILBOX_H +#define _PROP_MAILBOX_H + +/// \name Radio operation status +///@{ +/// \name Operation finished normally +///@{ +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 + +///@} +/// \name Operation finished with error +///@{ +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +///@} +///@} + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.c new file mode 100644 index 00000000..47476850 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.c @@ -0,0 +1,295 @@ +/****************************************************************************** +* Filename: rfc.c +* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) +* Revision: 52334 +* +* Description: Driver for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "rfc.h" +#include "rf_mailbox.h" +#include + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + + +//***************************************************************************** +// +// Get and clear CPE interrupt flags which match the provided bitmask +// +//***************************************************************************** +uint32_t +RFCCpeIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask; + + // Clear the interrupt flags + RFCCpeIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Send a radio operation to the doorbell and wait for an acknowledgement +// +//***************************************************************************** +uint32_t +RFCDoorbellSendTo(uint32_t pOp) +{ + // Wait until the doorbell becomes available + while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0); + RFCAckIntClear(); + + // Submit the command to the CM0 through the doorbell + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp; + + // Wait until the CM0 starts to parse the command + while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + RFCAckIntClear(); + + // Return with the content of status register + return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA)); +} + + +//***************************************************************************** +// +// Turn off the RF synthesizer. The radio will no longer respond to commands! +// +//***************************************************************************** +void +RFCSynthPowerDown(void) +{ + // Definition of reserved words + const uint32_t RFC_RESERVED0 = 0x40046054; + const uint32_t RFC_RESERVED1 = 0x40046060; + const uint32_t RFC_RESERVED2 = 0x40046058; + const uint32_t RFC_RESERVED3 = 0x40044100; + + // Disable CPE clock, enable FSCA clock. + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) + & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M | RFC_PWR_PWMCLKEN_RFE_M; + + HWREG(RFC_RESERVED0) = 3; + HWREG(RFC_RESERVED1) = 0x1030; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x50; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x650; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED1) = 0x10C0; + HWREG(RFC_RESERVED2) = 1; + HWREG(RFC_RESERVED3) = 1; +} + + +//***************************************************************************** +// +// Reset previously patched CPE RAM to a state where it can be patched again +// +//***************************************************************************** +void +RFCCpePatchReset(void) +{ + // Function is not complete +} + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +uint8_t +RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth) +{ + // Search from start of the override list, to look for first override entry that matches search pattern + uint8_t override_index; + for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++) + { + // Compare the value to the given pattern + if((pOverride[override_index] & mask) == pattern) + { + // Return with the index of override in case of match + return override_index; + } + } + + // Return with an invalid index + return 0xFF; +} + +//***************************************************************************** +// +// Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +uint32_t +RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode) +{ + uint16_t fsOnly; + uint16_t txSetting; + + switch (loDivider) + { + case 0: fsOnly = 0x0502; + break; + case 2: + fsOnly = 0x0102; + break; + case 4: + case 6: + case 12: + fsOnly = 0xF101; + break; + case 5: + case 10: + case 15: + case 30: + fsOnly = 0x1101; + break; + default: + // Error, should not occur! + fsOnly = 0; + break; + } + + if (frontEndMode == 255) + { + // Special value meaning 20 dBm PA + txSetting = (fsOnly | 0x00C0) & ~0x0400; + } + else if (frontEndMode == 0) + { + // Differential + txSetting = fsOnly | 0x0030; + } + else if (frontEndMode & 1) + { + // Single ended on RFP + txSetting = fsOnly | 0x0010; + } + else + { + // Single ended on RFN + txSetting = fsOnly | 0x0020; + } + + return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS); +} + +//***************************************************************************** +// +// Update the override list based on values stored in FCFG1 +// +//***************************************************************************** +uint8_t +RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) +{ + // Function is left blank for compatibility reasons. + return 0; +} + + +//***************************************************************************** +// +// Get and clear HW interrupt flags +// +//***************************************************************************** +uint32_t +RFCHwIntGetAndClear(uint32_t ui32Mask) +{ + // Read the CPE interrupt flags which match the provided bitmask + uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask; + + // Clear the interupt flags + RFCHwIntClear(ui32Ifg); + + // Return with the interrupt flags + return (ui32Ifg); +} + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #undef RFCSynthPowerDown + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #undef RFCCpePatchReset + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #undef RFCOverrideSearch + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #undef RFCOverrideUpdate + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + +// See rfc.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.h new file mode 100644 index 00000000..747c0013 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rfc.h @@ -0,0 +1,492 @@ +/****************************************************************************** +* Filename: rfc.h +* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) +* Revision: 52338 +* +* Description: Defines and prototypes for the RF Core. +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup rfc_api +//! @{ +// +//***************************************************************************** + +#ifndef __RFC_H__ +#define __RFC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_rfc_pwr.h) +#include DeviceFamily_constructPath(inc/hw_rfc_dbell.h) +#include DeviceFamily_constructPath(inc/hw_fcfg1.h) +#include DeviceFamily_constructPath(inc/hw_adi_3_refsys.h) +#include DeviceFamily_constructPath(inc/hw_adi.h) +#include DeviceFamily_constructPath(inc/hw_prcm.h) +#include "rf_common_cmd.h" +#include "rf_prop_cmd.h" +#include "rf_ble_cmd.h" + +// Definition of RFTRIM container +typedef struct { + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; +} rfTrim_t; + +// Definition of maximum search depth used by the RFCOverrideUpdate function +#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_IEEE_CMD_BG_ADDRESS 0x21000160 +#define RFC_IEEE_CMD_BG_IEEE_RX_O_CAP_TIME 24 +#define RFC_PA_TYPE_ADDRESS 0x21000385 +#define RFC_PA_TYPE_MASK 0x04 +#define RFC_PA_GAIN_ADDRESS 0x21000398 +#define RFC_PA_GAIN_MASK 0x003FFFFF +#define RFC_FE_MODE_ESCAPE_VALUE 0xFF +#define RFC_FE_OVERRIDE_ADDRESS 0x0703 +#define RFC_FE_OVERRIDE_MASK 0x0000FFFF + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear + #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo + #define RFCSynthPowerDown NOROM_RFCSynthPowerDown + #define RFCCpePatchReset NOROM_RFCCpePatchReset + #define RFCOverrideSearch NOROM_RFCOverrideSearch + #define RFCOverrideUpdate NOROM_RFCOverrideUpdate + #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear + #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#endif + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockEnable(void) +{ + // Enable basic clocks to get the CPE run + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM + | RFC_PWR_PWMCLKEN_CPE + | RFC_PWR_PWMCLKEN_RFC; +} + + +//***************************************************************************** +// +//! \brief Disable the RF core clocks. +//! +//! As soon as the RF core is started it will handle clock control +//! autonomously. No check should be performed to check the clocks. Instead +//! the radio can be ping'ed through the command interface. +//! +//! When disabling clocks it is the programmers responsibility that the +//! RF core clocks are safely gated. I.e. the RF core should be safely +//! 'parked'. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +RFCClockDisable(void) +{ + // Disable all clocks + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; +} + + +//***************************************************************************** +// +//! Clear HW interrupt flags +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Clear CPE interrupt flags. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntClear(uint32_t ui32Mask) +{ + // Clear the masked pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelect(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Enable CPEx interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntEnable(uint32_t ui32Mask) +{ + // Enable CPE interrupts from RF Core. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE0. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE0 IRQ. + RFCCpe0IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Select, clear, and enable interrupt sources to CPE1. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) +{ + // Multiplex RF Core interrupts to CPE1 IRQ. + RFCCpe1IntSelect(ui32Mask); + + // Clear the masked interrupts. + RFCCpeIntClear(ui32Mask); + + // Enable the masked interrupts. + RFCCpeIntEnable(ui32Mask); +} + + +//***************************************************************************** +// +//! Enable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntEnable(uint32_t ui32Mask) +{ + // Enable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; +} + + +//***************************************************************************** +// +//! Disable CPE interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCCpeIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Disable HW interrupt sources. +// +//***************************************************************************** +__STATIC_INLINE void +RFCHwIntDisable(uint32_t ui32Mask) +{ + // Disable the masked interrupts + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; +} + + +//***************************************************************************** +// +//! Get and clear CPE interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Clear ACK interrupt flag. +// +//***************************************************************************** +__STATIC_INLINE void +RFCAckIntClear(void) +{ + // Clear any pending interrupts. + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; +} + + +//***************************************************************************** +// +//! Send a radio operation to the doorbell and wait for an acknowledgment. +// +//***************************************************************************** +extern uint32_t RFCDoorbellSendTo(uint32_t pOp); + + +//***************************************************************************** +// +//! This function implements a fast way to turn off the synthesizer. +// +//***************************************************************************** +extern void RFCSynthPowerDown(void); + + +//***************************************************************************** +// +//! Reset previously patched CPE RAM to a state where it can be patched again. +// +//***************************************************************************** +extern void RFCCpePatchReset(void); + + +//***************************************************************************** +// +// Function to search an override list for the provided pattern within the search depth. +// +//***************************************************************************** +extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); + + +//***************************************************************************** +// +//! Function to update override list +// +//***************************************************************************** +extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams); + + +//***************************************************************************** +// +//! Get and clear HW interrupt flags. +// +//***************************************************************************** +extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); + + +//***************************************************************************** +// +//! Get the type of currently selected PA. +// +//***************************************************************************** +__STATIC_INLINE bool +RFCGetPaType(void) +{ + return (bool)(HWREGB(RFC_PA_TYPE_ADDRESS) & RFC_PA_TYPE_MASK); +} + +//***************************************************************************** +// +//! Get the gain of currently selected PA. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +RFCGetPaGain(void) +{ + return (HWREG(RFC_PA_GAIN_ADDRESS) & RFC_PA_GAIN_MASK); +} + +//***************************************************************************** +// +//! Get the power domain status of the radio core +// +//***************************************************************************** +__STATIC_INLINE uint32_t +RFCGetPowerDomainStatus(void) +{ + return (HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) | + HWREG(PRCM_BASE + PRCM_O_PDSTAT0RFC)); +} + +//***************************************************************************************** +// +//! Get the capture time from RFC_RAM of the current received packet in an IEEE RX command +//! Warning: Reading from RFC_RAM requires the RF Core to be powered. +// +//***************************************************************************************** +__STATIC_INLINE uint32_t +RFCGetIeeeRxCaptureTime(void) +{ + return (HWREG(RFC_IEEE_CMD_BG_ADDRESS + RFC_IEEE_CMD_BG_IEEE_RX_O_CAP_TIME)); +} + +//***************************************************************************** +// +//! Function to calculate the proper override run-time for the High Gain PA. +// +//***************************************************************************** +extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include DeviceFamily_constructPath(driverlib/rom.h) + #ifdef ROM_RFCCpeIntGetAndClear + #undef RFCCpeIntGetAndClear + #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear + #endif + #ifdef ROM_RFCDoorbellSendTo + #undef RFCDoorbellSendTo + #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo + #endif + #ifdef ROM_RFCSynthPowerDown + #undef RFCSynthPowerDown + #define RFCSynthPowerDown ROM_RFCSynthPowerDown + #endif + #ifdef ROM_RFCCpePatchReset + #undef RFCCpePatchReset + #define RFCCpePatchReset ROM_RFCCpePatchReset + #endif + #ifdef ROM_RFCOverrideSearch + #undef RFCOverrideSearch + #define RFCOverrideSearch ROM_RFCOverrideSearch + #endif + #ifdef ROM_RFCOverrideUpdate + #undef RFCOverrideUpdate + #define RFCOverrideUpdate ROM_RFCOverrideUpdate + #endif + #ifdef ROM_RFCHwIntGetAndClear + #undef RFCHwIntGetAndClear + #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear + #endif + #ifdef ROM_RFCAnaDivTxOverride + #undef RFCAnaDivTxOverride + #define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __RFC_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom.h new file mode 100644 index 00000000..d934bed2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom.h @@ -0,0 +1,1041 @@ +/****************************************************************************** +* Filename: rom.h +* +* Description: Prototypes for the ROM utility functions. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ROM_H__ +#define __ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "../inc/hw_types.h" + +#ifndef __HAPI_H__ +#define __HAPI_H__ + +// Start address of the ROM hard API access table (located after the ROM FW rev field) +#define ROM_HAPI_TABLE_ADDR 0x10000048 + +// ROM Hard-API function interface types +typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\ + uint32_t /* ui32ByteCount */,\ + uint32_t /* ui32RepeatCount */); + +typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); + +typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); + +typedef uint32_t (* FPTR_RESERVED2_T) ( void ); + +typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\ + uint32_t ,\ + uint32_t ); + +typedef void (* FPTR_RESETDEV_T) ( void ); + +typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\ + uint16_t /* ui16WordCount */,\ + uint16_t /* ui16RepeatCount */); + +typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\ + uint32_t /* ui32DataCount */); + +typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); + +typedef void (* FPTR_RESERVED4_T) ( uint32_t ); + +typedef void (* FPTR_RESERVED5_T) ( uint32_t ); + +typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); + +typedef void (* FPTR_DACVREF_T) ( uint8_t /* ut8Signal */); + +extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, + uint32_t ui32Address, + uint32_t ui32Count); + +extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); + +// ROM Hard-API access table type +typedef struct +{ + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_DACVREF_T SelectDACVref; +} HARD_API_T; + +// Pointer to the ROM HAPI table +#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) + +#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) +#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) +#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) +#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) +#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) +#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch() +#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a) +#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a) +#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a) +#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) + +// Defines for input parameter to the HapiSelectCompAInput function. +#define COMPA_IN_NC 0x00 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectCompARef function. +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 +// Defines used in CC13x0/CC26x0 devices +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 + +// Defines for input parameter to the HapiSelectADCCompBInput function. +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 +// Defines used in CC13x0/CC26x0 devices +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 +// Defines used in CC13x2/CC26x2 devices +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 + +// Defines for input parameter to the HapiSelectDACVref function. +// The define values can not be changed! +#define DAC_REF_NC 0x00 +#define DAC_REF_DCOUPL 0x01 +#define DAC_REF_VSS 0x02 +#define DAC_REF_VDDS 0x03 + +#endif // __HAPI_H__ + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) + + +#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) +#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) +#define ROM_API_OSC_TABLE ((uint32_t*) (ROM_API_TABLE[24])) +#define ROM_API_AUX_ADC_TABLE ((uint32_t*) (ROM_API_TABLE[25])) +#define ROM_API_SYS_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[26])) +#define ROM_API_AON_BATMON_TABLE ((uint32_t*) (ROM_API_TABLE[27])) +#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28])) +#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29])) +#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30])) +#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31])) +#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32])) +#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33])) + +// AON_EVENT FUNCTIONS +#define ROM_AONEventMcuWakeUpSet \ + ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[0]) + +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) + +#define ROM_AONEventMcuSet \ + ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ + ROM_API_AON_EVENT_TABLE[4]) + +#define ROM_AONEventMcuGet \ + ((uint32_t (*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) + + +// AON_RTC FUNCTIONS +#define ROM_AONRTCCurrent64BitValueGet \ + ((uint64_t (*)(void)) \ + ROM_API_AON_RTC_TABLE[12]) + + +// AUX_TDC FUNCTIONS +#define ROM_AUXTDCConfigSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ + ROM_API_AUX_TDC_TABLE[0]) + +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) + + +// DDI FUNCTIONS +#define ROM_DDI16BitWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ + ROM_API_DDI_TABLE[0]) + +#define ROM_DDI16BitfieldWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ + ROM_API_DDI_TABLE[1]) + +#define ROM_DDI16BitRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ + ROM_API_DDI_TABLE[2]) + +#define ROM_DDI16BitfieldRead \ + ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ + ROM_API_DDI_TABLE[3]) + +#define ROM_DDI32RegWrite \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ + ROM_API_DDI_TABLE[4]) + + +// FLASH FUNCTIONS +#define ROM_FlashPowerModeSet \ + ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ + ROM_API_FLASH_TABLE[0]) + +#define ROM_FlashProtectionSet \ + ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ + ROM_API_FLASH_TABLE[2]) + +#define ROM_FlashProtectionGet \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) + +#define ROM_FlashProtectionSave \ + ((uint32_t (*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) + +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) + +#define ROM_FlashDisableSectorsForWrite \ + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) + + +// I2C FUNCTIONS +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ + ROM_API_I2C_TABLE[0]) + +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) + + +// INTERRUPT FUNCTIONS +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits)) \ + ROM_API_INTERRUPT_TABLE[0]) + +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) + +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ + ROM_API_INTERRUPT_TABLE[2]) + +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) + +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[4]) + +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[5]) + +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[6]) + +#define ROM_IntPendGet \ + ((bool (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[7]) + +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[8]) + + +// IOC FUNCTIONS +#define ROM_IOCPortConfigureSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ + ROM_API_IOC_TABLE[0]) + +#define ROM_IOCPortConfigureGet \ + ((uint32_t (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) + +#define ROM_IOCIOShutdownSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ + ROM_API_IOC_TABLE[2]) + +#define ROM_IOCIOModeSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ + ROM_API_IOC_TABLE[4]) + +#define ROM_IOCIOIntSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ + ROM_API_IOC_TABLE[5]) + +#define ROM_IOCIOPortPullSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ + ROM_API_IOC_TABLE[6]) + +#define ROM_IOCIOHystSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ + ROM_API_IOC_TABLE[7]) + +#define ROM_IOCIOInputSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ + ROM_API_IOC_TABLE[8]) + +#define ROM_IOCIOSlewCtrlSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ + ROM_API_IOC_TABLE[9]) + +#define ROM_IOCIODrvStrengthSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ + ROM_API_IOC_TABLE[10]) + +#define ROM_IOCIOPortIdSet \ + ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ + ROM_API_IOC_TABLE[11]) + +#define ROM_IOCIntEnable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[12]) + +#define ROM_IOCIntDisable \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[13]) + +#define ROM_IOCPinTypeGpioInput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[14]) + +#define ROM_IOCPinTypeGpioOutput \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[15]) + +#define ROM_IOCPinTypeUart \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ + ROM_API_IOC_TABLE[16]) + +#define ROM_IOCPinTypeSsiMaster \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[17]) + +#define ROM_IOCPinTypeSsiSlave \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[18]) + +#define ROM_IOCPinTypeI2c \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ + ROM_API_IOC_TABLE[19]) + +#define ROM_IOCPinTypeAux \ + ((void (*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[21]) + + +// PRCM FUNCTIONS +#define ROM_PRCMInfClockConfigureSet \ + ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[0]) + +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t (*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) + +#define ROM_PRCMAudioClockConfigSet \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ + ROM_API_PRCM_TABLE[4]) + +#define ROM_PRCMPowerDomainOn \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[5]) + +#define ROM_PRCMPowerDomainOff \ + ((void (*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[6]) + +#define ROM_PRCMPeripheralRunEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[7]) + +#define ROM_PRCMPeripheralRunDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[8]) + +#define ROM_PRCMPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[9]) + +#define ROM_PRCMPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[10]) + +#define ROM_PRCMPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) + +#define ROM_PRCMPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) + +#define ROM_PRCMDeepSleep \ + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) + +#define ROM_PRCMAudioClockConfigSetOverride \ + ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ + ROM_API_PRCM_TABLE[17]) + + +// SMPH FUNCTIONS +#define ROM_SMPHAcquire \ + ((void (*)(uint32_t ui32Semaphore)) \ + ROM_API_SMPH_TABLE[0]) + + +// SSI FUNCTIONS +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ + ROM_API_SSI_TABLE[0]) + +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[1]) + +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) + +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[3]) + +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ + ROM_API_SSI_TABLE[4]) + + +// TIMER FUNCTIONS +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ + ROM_API_TIMER_TABLE[0]) + +#define ROM_TimerLevelControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ + ROM_API_TIMER_TABLE[1]) + +#define ROM_TimerStallControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ + ROM_API_TIMER_TABLE[3]) + +#define ROM_TimerWaitOnTriggerControl \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ + ROM_API_TIMER_TABLE[4]) + +#define ROM_TimerIntervalLoadMode \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ + ROM_API_TIMER_TABLE[5]) + +#define ROM_TimerMatchUpdateMode \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ + ROM_API_TIMER_TABLE[6]) + + +// TRNG FUNCTIONS +#define ROM_TRNGConfigure \ + ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ + ROM_API_TRNG_TABLE[0]) + +#define ROM_TRNGNumberGet \ + ((uint32_t (*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) + + +// UART FUNCTIONS +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) + +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ + ROM_API_UART_TABLE[1]) + +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ + ROM_API_UART_TABLE[2]) + +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[3]) + +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) + +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) + +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[6]) + +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ + ROM_API_UART_TABLE[7]) + + +// UDMA FUNCTIONS +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[0]) + +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ + ROM_API_UDMA_TABLE[1]) + +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) + +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ + ROM_API_UDMA_TABLE[3]) + +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ + ROM_API_UDMA_TABLE[4]) + +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) + +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) + +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) + + +// VIMS FUNCTIONS +#define ROM_VIMSConfigure \ + ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ + ROM_API_VIMS_TABLE[0]) + +#define ROM_VIMSModeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ + ROM_API_VIMS_TABLE[1]) + +#define ROM_VIMSModeGet \ + ((uint32_t (*)(uint32_t ui32Base)) \ + ROM_API_VIMS_TABLE[2]) + +#define ROM_VIMSModeSafeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ + ROM_API_VIMS_TABLE[3]) + + +// OSC FUNCTIONS +#define ROM_OSCClockSourceGet \ + ((uint32_t (*)(uint32_t ui32SrcClk)) \ + ROM_API_OSC_TABLE[0]) + +#define ROM_OSCClockSourceSet \ + ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ + ROM_API_OSC_TABLE[1]) + +#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ + ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ + ROM_API_OSC_TABLE[3]) + + +// AUX_ADC FUNCTIONS +#define ROM_AUXADCAdjustValueForGainAndOffset \ + ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[0]) + +#define ROM_AUXADCDisable \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[1]) + +#define ROM_AUXADCDisableInputScaling \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[2]) + +#define ROM_AUXADCEnableAsync \ + ((void (*)(uint32_t refSource, uint32_t trigger)) \ + ROM_API_AUX_ADC_TABLE[3]) + +#define ROM_AUXADCEnableSyncNoBugWorkaround \ + ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ + ROM_API_AUX_ADC_TABLE[4]) + +#define ROM_AUXADCFlushFifo \ + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[5]) + +#define ROM_AUXADCGetAdjustmentGain \ + ((int32_t (*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[6]) + +#define ROM_AUXADCGetAdjustmentOffset \ + ((int32_t (*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[7]) + +#define ROM_AUXADCMicrovoltsToValue \ + ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ + ROM_API_AUX_ADC_TABLE[8]) + +#define ROM_AUXADCPopFifo \ + ((uint32_t (*)(void)) \ + ROM_API_AUX_ADC_TABLE[9]) + +#define ROM_AUXADCReadFifo \ + ((uint32_t (*)(void)) \ + ROM_API_AUX_ADC_TABLE[10]) + +#define ROM_AUXADCUnadjustValueForGainAndOffset \ + ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[11]) + +#define ROM_AUXADCValueToMicrovolts \ + ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ + ROM_API_AUX_ADC_TABLE[12]) + + +// SYS_CTRL FUNCTIONS +#define ROM_SysCtrlResetSourceGet \ + ((uint32_t (*)(void)) \ + ROM_API_SYS_CTRL_TABLE[0]) + +#define ROM_SysCtrl_DCDC_VoltageConditionalControl \ + ((void (*)(void)) \ + ROM_API_SYS_CTRL_TABLE[1]) + + +// AON_BATMON FUNCTIONS +#define ROM_AONBatMonTemperatureGetDegC \ + ((int32_t (*)(void)) \ + ROM_API_AON_BATMON_TABLE[0]) + + +// SETUP_ROM FUNCTIONS +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[0]) + +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ + ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[1]) + +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[2]) + +#define ROM_SetupGetTrimForAdcShModeEn \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[3]) + +#define ROM_SetupGetTrimForAdcShVbufEn \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[4]) + +#define ROM_SetupGetTrimForAmpcompCtrl \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[5]) + +#define ROM_SetupGetTrimForAmpcompTh1 \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[6]) + +#define ROM_SetupGetTrimForAmpcompTh2 \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[7]) + +#define ROM_SetupGetTrimForAnabypassValue1 \ + ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[8]) + +#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[9]) + +#define ROM_SetupGetTrimForRadcExtCfg \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[10]) + +#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[11]) + +#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[12]) + +#define ROM_SetupGetTrimForXoscHfCtl \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[13]) + +#define ROM_SetupGetTrimForXoscHfFastStart \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[14]) + +#define ROM_SetupGetTrimForXoscHfIbiastherm \ + ((uint32_t (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[15]) + +#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ + ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[16]) + +#define ROM_SetupSetAonRtcSubSecInc \ + ((void (*)(uint32_t subSecInc)) \ + ROM_API_SETUP_ROM_TABLE[17]) + +#define ROM_SetupSetCacheModeAccordingToCcfgSetting \ + ((void (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[18]) + +#define ROM_SetupStepVddrTrimTo \ + ((void (*)(uint32_t toCode)) \ + ROM_API_SETUP_ROM_TABLE[19]) + + +// I2S FUNCTIONS +#define ROM_I2SPointerSet \ + ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ + ROM_API_I2S_TABLE[0]) + +#define ROM_I2SSampleStampGet \ + ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ + ROM_API_I2S_TABLE[1]) + + +// PWR_CTRL FUNCTIONS +#define ROM_PowerCtrlSourceSet \ + ((void (*)(uint32_t ui32PowerConfig)) \ + ROM_API_PWR_CTRL_TABLE[0]) + + +// AES FUNCTIONS +#define ROM_AESConfigureCCMCtrl \ + ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ + ROM_API_AES_TABLE[0]) + +#define ROM_AESReadFromKeyStore \ + ((uint32_t (*)(uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[1]) + +#define ROM_AESReadTag \ + ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[2]) + +#define ROM_AESSetInitializationVector \ + ((void (*)(const uint32_t *initializationVector)) \ + ROM_API_AES_TABLE[3]) + +#define ROM_AESStartDMAOperation \ + ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_AES_TABLE[4]) + +#define ROM_AESVerifyTag \ + ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[5]) + +#define ROM_AESWaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_AES_TABLE[6]) + +#define ROM_AESWriteCCMInitializationVector \ + ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ + ROM_API_AES_TABLE[7]) + + +// PKA FUNCTIONS +#define ROM_PKABigNumAddGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[0]) + +#define ROM_PKABigNumCmpGetResult \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[1]) + +#define ROM_PKABigNumInvModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[2]) + +#define ROM_PKABigNumModGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[3]) + +#define ROM_PKABigNumMultGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[4]) + +#define ROM_PKAEccAddGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[5]) + +#define ROM_PKAEccAddStart \ + ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[6]) + +#define ROM_PKAEccMultiplyGetResult \ + ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[7]) + +#define ROM_PKAEccMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[8]) + +#define ROM_PKAGetOpsStatus \ + ((uint32_t (*)(void)) \ + ROM_API_PKA_TABLE[9]) + +#define ROM_PKABigNumAddStart \ + ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[10]) + +#define ROM_PKABigNumCmpStart \ + ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ + ROM_API_PKA_TABLE[11]) + +#define ROM_PKABigNumInvModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[12]) + +#define ROM_PKABigNumModStart \ + ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[13]) + +#define ROM_PKABigNumMultiplyStart \ + ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[14]) + +#define ROM_PKABigNumSubGetResult \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[15]) + +#define ROM_PKABigNumSubStart \ + ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[16]) + +#define ROM_PKAArrayAllZeros \ + ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[17]) + +#define ROM_PKABigNumDivideGetQuotient \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ + ROM_API_PKA_TABLE[18]) + +#define ROM_PKABigNumDivideGetRemainder \ + ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[19]) + +#define ROM_PKABigNumDivideStart \ + ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[20]) + +#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ + ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ + ROM_API_PKA_TABLE[21]) + +#define ROM_PKAZeroOutArray \ + ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ + ROM_API_PKA_TABLE[22]) + +#define ROM_PKAEccMontgomeryMultiplyStart \ + ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[23]) + + +// SHA2 FUNCTIONS +#define ROM_SHA2ComputeFinalHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[0]) + +#define ROM_SHA2ComputeHash \ + ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[1]) + +#define ROM_SHA2ComputeInitialHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ + ROM_API_SHA2_TABLE[2]) + +#define ROM_SHA2ComputeIntermediateHash \ + ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ + ROM_API_SHA2_TABLE[3]) + +#define ROM_SHA2StartDMAOperation \ + ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ + ROM_API_SHA2_TABLE[4]) + +#define ROM_SHA2WaitForIRQFlags \ + ((uint32_t (*)(uint32_t irqFlags)) \ + ROM_API_SHA2_TABLE[5]) + + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __ROM_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.c new file mode 100644 index 00000000..8086eaa2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.c @@ -0,0 +1,186 @@ +/******************************************************************************* +* Filename: rom_crypto.c +* +* Description: This is the implementation for the API to the ECC functions +* built into ROM on the CC13x2/CC26x2. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#include +#include "rom_crypto.h" + + +////////////////////////////////////* ECC *//////////////////////////////////// + +#if defined(__GNUC__) && !defined(__ti__) +// Disable string operation overflow warning when writing a +// value to memory given by a uint8_t pointer. +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-overflow=2" +#endif +//***************************************************************************** +// ECC_initialize +//***************************************************************************** +void +ECC_initialize(uint32_t *pWorkzone) +{ + // Initialize curve parameters + //data_p = ECC_NISTP256_prime; + *((const uint32_t **)0x20000138) = ECC_NISTP256_prime; + + //data_r = ECC_NISTP256_order; + *((const uint32_t **)0x2000013c) = ECC_NISTP256_order; + + //data_a = ECC_NISTP256_a; + *((const uint32_t **)0x20000140) = ECC_NISTP256_a; + + //data_b = ECC_NISTP256_b; + *((const uint32_t **)0x20000144) = ECC_NISTP256_b; + + //data_Gx = ECC_NISTP256_generatorX; + *((const uint32_t **)0x2000012c) = ECC_NISTP256_generatorX; + + //data_Gy = ECC_NISTP256_generatorY; + *((const uint32_t **)0x20000130) = ECC_NISTP256_generatorY; + + // Initialize window size + //win = (uint8_t) ECC_WINDOW_SIZE; + *((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20000134) = (uint32_t *) pWorkzone; +} +#if defined(__GNUC__) && !defined(__ti__) +// GCC: Stop ignoring -Wstringop-overflow=2 +#pragma GCC diagnostic pop +#endif + +//***************************************************************************** +// ECC_init +//***************************************************************************** +void +ECC_init(uint32_t *workzone, + uint8_t windowSize, + const uint32_t *prime, + const uint32_t *order, + const uint32_t *a, + const uint32_t *b, + const uint32_t *generatorX, + const uint32_t *generatorY) +{ + // Initialize curve parameters + //data_p = (uint32_t *)PARAM_P; + *((const uint32_t **)0x20000138) = prime; + + //data_r = (uint32_t *)PARAM_R; + *((const uint32_t **)0x2000013c) = order; + + //data_a = (uint32_t *)PARAM_A; + *((const uint32_t **)0x20000140) = a; + + //data_b = (uint32_t *)PARAM_B; + *((const uint32_t **)0x20000144) = b; + + //data_Gx = (uint32_t *)PARAM_GX; + *((const uint32_t **)0x2000012c) = generatorX; + + //data_Gy = (uint32_t *)PARAM_GY; + *((const uint32_t **)0x20000130) = generatorY; + + // Initialize window size + //win = (uint8_t) windowSize; + *((uint8_t *)0x20000148) = windowSize; + + // Initialize work zone + //workzone = (uint32_t *) pWorkzone; + *((uint32_t **)0x20000134) = workzone; +} + +typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); +ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d); + +typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381); + +typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805); + +typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); +ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485); + +//***************************************************************************** +// ECC_generateKey +//***************************************************************************** +uint8_t +ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y) +{ + return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, + (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); + +} + +//***************************************************************************** +// ECC_ECDSA_sign +//***************************************************************************** +uint8_t +ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDSA_verify +//***************************************************************************** +uint8_t +ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2) +{ + return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, + (uint32_t*)sign1, (uint32_t*)sign2); +} + +//***************************************************************************** +// ECC_ECDH_computeSharedSecret +//***************************************************************************** +uint8_t +ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, + uint32_t *publicKey_y, uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y) +{ + return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, + (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, + (uint32_t*)sharedSecret_y); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.h new file mode 100644 index 00000000..013e7fbd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/rom_crypto.h @@ -0,0 +1,274 @@ +/****************************************************************************** +* Filename: rom_crypto.h +* +* Description: This header file is the API to the crypto functions +* built into ROM on the CC13xx/CC26xx. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup rom_crypto_api +//! @{ +// +//***************************************************************************** + +#ifndef ROM_CRYPTO_H +#define ROM_CRYPTO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +////////////////////////////////////* ECC *///////////////////////////////////// + +/* Curve Parameters in ROM */ + +/* Curve parameters for the NISTP256 curve. These curve parameters are stored + * in ROM and can be accessed via the pointers below. + * Each curve parameter starts with the 32-bit word 0x08 followed by the actual + * parameter encoded in 32 bytes as a little-endian integer. + */ +#define ECC_NISTP256_prime ((const uint32_t *) 0x100257d4) +#define ECC_NISTP256_order ((const uint32_t *) 0x100257f8) +#define ECC_NISTP256_a ((const uint32_t *) 0x1002581c) +#define ECC_NISTP256_b ((const uint32_t *) 0x10025840) +#define ECC_NISTP256_generatorX ((const uint32_t *) 0x10025864) +#define ECC_NISTP256_generatorY ((const uint32_t *) 0x10025888) + +/* Length in bytes of NISTP256 curve parameters excluding the prepended length + * word. + */ +#define ECC_NISTP256_PARAM_LENGTH_BYTES 32 + +/* Length in words of NISTP256 curve parameters excluding the prepended length + * word. + */ +#define ECC_NISTP256_PARAM_LENGTH_WORDS (ECC_NISTP256_PARAM_LENGTH_BYTES / sizeof(uint32_t)) + +/* Number of bytes for the length word prepended before all parameters passed + * into the ECC functions. + */ +#define ECC_LENGTH_OFFSET_BYTES 4 + +/* Window size, valid values are 2,3,4,5. + * Higher the value, faster the computation at the expense of memory usage. + * + * Recommended workzone size (in 4-byte words) + * Window size: 3, Workzone size: 275 + * + */ +#define ECC_WINDOW_SIZE 3 + +/* + * ECC Supported Curves, define one: + * ECC_PRIME_NIST256_CURVE + */ +#define ECC_PRIME_NIST256_CURVE + +/* + * ECC Return Status Flags. + */ +// Scalar multiplication status +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 + +// ECDSA and ECDH status +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 + +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK + +//***************************************************************************** +/*! + * \brief Initialize elliptic curve parameters to default values and specify workzone. + * + * This function initializes the elliptic curve parameters to default values. + * The default elliptic curve used is NIST-P256. + * + * The workzone defaults to an expected window size of 3. + * + * This function can be called again to point the ECC workzone at + * a different memory buffer. + * + * \param pWorkzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * + * \return None + */ +//***************************************************************************** +extern void ECC_initialize(uint32_t *pWorkzone); + +//***************************************************************************** +/*! + * \brief Initialize elliptic curve parameters to specified values and specify workzone. + * + * This function may be used to explicitly specify the curve parameters used + * by the ECC in ROM implementation. + * + * All curve parameters must be prepended with a length word specifying the + * length of the parameter in 32-bit words excluding the length word itself. + * For NIST-P256, the length word is 8. + * + * @param workzone Pointer to memory allocated for computations, input. + * See description at beginning of ECC section for + * memory requirements. + * @param windowSize Window size of \c workzone. Default value is 3. + * @param prime Curve prime + * @param order Curve order + * @param a Curve a value + * @param b Curve b value + * @param generatorX X coordinate of generator point + * @param generatorY Y coordinate of generator point + */ +extern void ECC_init(uint32_t *workzone, + uint8_t windowSize, + const uint32_t *prime, + const uint32_t *order, + const uint32_t *a, + const uint32_t *b, + const uint32_t *generatorX, + const uint32_t *generatorY); + +//***************************************************************************** + /*! + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, + uint32_t *publicKey_x, uint32_t *publicKey_y); + +//***************************************************************************** +/*! + * \brief Sign data. + * + * \param secretKey Pointer to the secret key, input. + * \param text Pointer to the message, input. + * \param randString Pointer to random string, input. + * \param sign1 Pointer to signature part 1, output. + * \param sign2 Pointer to signature part 2, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, + uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Verify signature. + * + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param text Pointer to message data, input. + * \param sign1 Pointer to signature part 1, input. + * \param sign2 Pointer to signature part 2, input. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, + uint32_t *text, uint32_t *sign1, uint32_t *sign2); + +//***************************************************************************** +/*! + * \brief Compute the shared secret. + * + * \param privateKey Pointer to private key, input. + * \param publicKey_x Pointer to public key X-coordinate, input. + * \param publicKey_y Pointer to public key Y-coordinate, input. + * \param sharedSecret_x Pointer to shared secret X-coordinate, output. + * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. + * + * \return Status + */ +//***************************************************************************** +extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, + uint32_t *publicKey_x, + uint32_t *publicKey_y, + uint32_t *sharedSecret_x, + uint32_t *sharedSecret_y); + +#ifdef __cplusplus +} +#endif + +#endif /* ROM_CRYPTO_H */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.c new file mode 100644 index 00000000..f7263edf --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.c @@ -0,0 +1,383 @@ +/****************************************************************************** +* Filename: setup.c +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +// Temporarily adding these defines as they are missing in hw_adi_4_aux.h +#define ADI_4_AUX_O_LPMBIAS 0x0000000E +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_vims.h" +// Driverlib headers +#include "aon_rtc.h" +#include "interrupt.h" +#include "aux_sysif.h" +#include "chipinfo.h" +#include "osc.h" +#include "setup.h" +#include "setup_rom.h" +#include "ccfgread.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupTrimDevice + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + + + +//***************************************************************************** +// +// Defined CPU delay macro with microseconds as input +// Quick check shows: (To be further investigated) +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles +// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles +// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles +// +//***************************************************************************** +#define CPU_DELAY_MICRO_SECONDS( x ) \ + CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 ) + + +//***************************************************************************** +// +// Constants for SubSecInc values at different SCLK_LF frequencies +// +//***************************************************************************** +#define SUBSECINC_31250_HZ 0x8637BD +#define SUBSECINC_32768_HZ 0x800000 + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** +static void TrimAfterColdReset( void ); +static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision ); +static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ); + +//***************************************************************************** +// +// Perform the necessary trim of the device which is not done in boot code +// +// This function should only execute coming from ROM boot. The current +// implementation does not take soft reset into account. However, it does no +// damage to execute it again. It only consumes time. +// +//***************************************************************************** +void +SetupTrimDevice(void) +{ + uint32_t ui32Fcfg1Revision; + uint32_t ui32AonSysResetctl; + + // Get layout revision of the factory configuration area + // (Handle undefined revision as revision = 0) + ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION); + if ( ui32Fcfg1Revision == 0xFFFFFFFF ) { + ui32Fcfg1Revision = 0; + } + + // This driverlib version and setup file is for the CC13x2x7, CC26x2x7 chips. + // Halt if violated + ThisLibraryIsFor_CC13x2x7_CC26x2x7_HaltIfViolated(); + + // Enable standby in flash bank + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; + + // Select correct CACHE mode and set correct CACHE configuration +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupSetCacheModeAccordingToCcfgSetting(); +#else + NOROM_SetupSetCacheModeAccordingToCcfgSetting(); +#endif + + // 1. Check for powerdown + // 2. Check for shutdown + // 3. Assume cold reset if none of the above. + // + // It is always assumed that the application will freeze the latches in + // AON_IOC when going to powerdown in order to retain the values on the IOs. + // + // NB. If this bit is not cleared before proceeding to powerdown, the IOs + // will all default to the reset configuration when restarting. + if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + // Check for shutdown + // + // When device is going to shutdown the hardware will automatically clear + // the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module. + // It is left for the application to assert this bit when waking back up, + // but not before the desired IO configuration has been re-established. + else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN ))) + { + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + } + else + { + // Consider adding a check for soft reset to allow debugging to skip + // this section!!! + // + // NB. This should be calling a ROM implementation of required trim and + // compensation + // e.g. TrimAfterColdReset() --> + // TrimAfterColdResetWakeupFromShutDown() --> + // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() + TrimAfterColdReset(); + TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); + TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); + + } + + // Set VIMS power domain control. + // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered + HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; + + // Configure optimal wait time for flash FSM in cases where flash pump + // wakes up from sleep + HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & + ~FLASH_FPAC1_PSLEEPTDIS_M) | + (0x139<> + AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) + { + ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & + ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M )); + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M; + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl; + } + + // Reset the RTC + AONRTCReset(); + // Configure the combined event + IntPendClear(INT_AON_RTC_COMB); + AONRTCCombinedEventConfig(AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2); + // Start the RTC + AONRTCEnable(); + + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_XOSC_LF) + { + /* Set SubSecInc to 31.250 kHz since we start up on RCOSC_HF_DLF. The + * rom startup code leaves this at the default 32.768 kHz but that is + * only accurate once we actually switch to XOSC_LF. Once the + * oscillator combined interrupt triggers after we switch to the target + * clock, we will configure SubSecInc back to 32.768 kHz. + * + * There is no need to update SubSecInc dynamically for other LF clock + * sources. + * - RCOSC_LF starts on RCOSC_HF-derived but switches fast enough that + * we do not accumulate any real-time clock drift before switching. + * - External LF is correctly set and requires no switching. + * - XOSC_HF-derived does not change LF clock frequencies. + */ + SetupSetAonRtcSubSecInc(SUBSECINC_31250_HZ); + } + + // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() + // (There should typically be no wait time here, but need to be sure) + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + } + +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from POWER_DOWN (also called when +//! coming from SHUTDOWN and PIN_RESET). +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) +{ + // Currently no specific trim for Powerdown +} + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from SHUTDOWN (also called when +//! coming from PIN_RESET). +//! +//! \param ui32Fcfg1Revision +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) +{ + uint32_t ccfg_ModeConfReg ; + + // Check in CCFG for alternative DCDC setting + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { + // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) + // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) + // Using a single 4-bit masked write since layout is equal for both source and destination + HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | + ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); + } + + // Force DCDC to use RCOSC before starting up XOSC. + // Clock loss detector does not use XOSC until SCLK_HF actually switches + // and thus DCDC is not protected from clock loss on XOSC in that time frame. + // The force must be released when the switch to XOSC has happened. This is done + // in OSCHfSourceSwitch(). + HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); + // Dummy read to ensure that the write has propagated + HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); + + // read the MODE_CONF register in CCFG + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + // First part of trim done after cold reset and wakeup from shutdown: + // -Adjust the VDDR_TRIM_SLEEP value. + // -Configure DCDC. + SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); + + // Addition to the CC1352 boost mode for HWREV >= 2.0 + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + // OR in VDDR_BOOST_COMP_BOOST and maintain the other register fields. + // On CC13X2, CC26X2, CC13X1 and CC26X1 devices, there are no other + // fields in this register. But on CC26X4 and CC13X4 devices, there is + // an additional trim field that must not be overwritten. + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) |= ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ; + } + + // Second part of trim done after cold reset and wakeup from shutdown: + // -Configure XOSC. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); +#endif + + { + uint32_t trimReg ; + uint32_t ui32TrimValue ; + + //--- Propagate the LPM_BIAS trim --- + trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF ); + ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >> + FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ; + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) & + ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ; + // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration + if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) { + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } else { + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; + } + // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration + { + uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S ); + HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3 + (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8] + ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0] + } + } + + // Third part of trim done after cold reset and wakeup from shutdown: + // -Configure HPOSC. + // -Setup the LF clock. +#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) + SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#else + NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); +#endif + + // Set AUX into power down active mode + AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA ); + + // Disable EFUSE clock + HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; +} + + +//***************************************************************************** +// +//! \brief Trims to be applied when coming from PIN_RESET. +//! +//! \return None +// +//***************************************************************************** +static void +TrimAfterColdReset( void ) +{ + // Currently no specific trim for Cold Reset +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.h new file mode 100644 index 00000000..73d1688a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup.h @@ -0,0 +1,139 @@ +/****************************************************************************** +* Filename: setup.h +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_H__ +#define __SETUP_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupTrimDevice NOROM_SetupTrimDevice +#endif + +//***************************************************************************** +// +//! \brief Performs the necessary trim of the device which is not done in ROM boot code. +//! +//! This function should only execute coming from ROM boot. +//! +//! The following is handled by this function: +//! - Checks if the driverlib variant used by the application is supported by the +//! device. Execution is halted in case of unsupported driverlib variant. +//! - Configures VIMS cache mode based on setting in CCFG. +//! - Configures functionalities like DCDC and XOSC dependent on startup modes like +//! cold reset, wakeup from shutdown and wakeup from from powerdown. +//! - Configures VIMS power domain control. +//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. +//! +//! \note The current implementation does not take soft reset into account. However, +//! it does no damage to execute it again. It only consumes time. +//! +//! \note This function is called by the compiler specific device startup codes +//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. +//! +//! \return None +// +//***************************************************************************** +extern void SetupTrimDevice( void ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupTrimDevice + #undef SetupTrimDevice + #define SetupTrimDevice ROM_SetupTrimDevice + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_doc.h new file mode 100644 index 00000000..4c741e3c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_doc.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: setup_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_api +//! @{ +//! +//! This module contains functions for device setup which is not done in boot code. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.c new file mode 100644 index 00000000..a656a271 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.c @@ -0,0 +1,942 @@ +/****************************************************************************** +* Filename: setup_rom.c +* +* Description: Setup file for CC13xx/CC26xx devices. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +// Driverlib headers +#include "ddi.h" +#include "ioc.h" +#include "osc.h" +#include "sys_ctrl.h" +#include "setup_rom.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #undef SetupStepVddrTrimTo + #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo +#endif + +//***************************************************************************** +// +// Function declarations +// +//***************************************************************************** + + +//***************************************************************************** +// +// SetupStepVddrTrimTo +// +//***************************************************************************** +void +SetupStepVddrTrimTo( uint32_t toCode ) +{ + uint32_t pmctlResetctl_reg ; + int32_t targetTrim ; + int32_t currentTrim ; + + targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( targetTrim != currentTrim ) { + pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate + } + + while ( targetTrim != currentTrim ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( targetTrim > currentTrim ) currentTrim++; + else currentTrim--; + + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( + ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | + ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } + } +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg1 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) +{ + // Check for CC1352 boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg2 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); +} + +//***************************************************************************** +// +// SetupAfterColdResetWakeupFromShutDownCfg3 +// +//***************************************************************************** +void +SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) +{ + uint32_t fcfg1OscConf; + uint32_t ui32Trim; + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +//***************************************************************************** +// +// SetupGetTrimForAnabypassValue1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) +{ + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfRtuneCtuneTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfIbiastherm +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfIbiastherm( void ) +{ + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh2 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh2( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompTh1 +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompTh1( void ) +{ + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForAmpcompCtrl +// +//***************************************************************************** +uint32_t +SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +//***************************************************************************** +// +// SetupGetTrimForDblrLoopFilterResetVoltage +// +//***************************************************************************** +uint32_t +SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) +{ + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShModeEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForAdcShVbufEn +// +//***************************************************************************** +uint32_t +SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfCtl +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscHfFastStart +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscHfFastStart( void ) +{ + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRadcExtCfg +// +//***************************************************************************** +uint32_t +SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) +{ + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForRcOscLfIBiasTrim +// +//***************************************************************************** +uint32_t +SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +//***************************************************************************** +// +// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +// +//***************************************************************************** +uint32_t +SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) +{ + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +//***************************************************************************** +// +// SetupSetCacheModeAccordingToCcfgSetting +// +//***************************************************************************** +void +SetupSetCacheModeAccordingToCcfgSetting( void ) +{ + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +} + +//***************************************************************************** +// +// SetupSetAonRtcSubSecInc +// +//***************************************************************************** +void +SetupSetAonRtcSubSecInc( uint32_t subSecInc ) +{ + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1 + // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0; + +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.h new file mode 100644 index 00000000..3725161d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom.h @@ -0,0 +1,468 @@ +/****************************************************************************** +* Filename: setup_rom.h +* +* Description: Prototypes and defines for the setup API. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup setup_rom_api +//! @{ +// +//***************************************************************************** + +#ifndef __SETUP_ROM_H__ +#define __SETUP_ROM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +// Hardware headers +#include "../inc/hw_types.h" +// Driverlib headers +// - None needed + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc + #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo +#endif + +//***************************************************************************** +// +//! \brief First part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following based on settings in CCFG (Customer Configuration area: +//! - Boost mode for CC13xx devices +//! - Minimal VDDR voltage threshold used during sleep mode +//! - DCDC functionality: +//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode +//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode +//! +//! In addition the battery monitor low limit for internal regulator mode is set +//! to a hard coded value. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Second part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures and trims functionalites required for use of XOSC_HF. +//! The configurations and trimmings are based on settings in FCFG1 (Factory +//! Configuration area) and partly on \c ccfg_ModeConfReg. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Third part of configuration required after cold reset and when waking up from shutdown. +//! +//! Configures the following: +//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a +//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory +//! Configuration area). +//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. +//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. +//! - SCLK_LF based on \c ccfg_ModeConfReg. +//! - Output voltage of ADC fixed reference based on FCFG1 setting. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return None +// +//***************************************************************************** +extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh1( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAmpcompTh2( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. +//! +//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); + +//***************************************************************************** +// +//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value from FCFG1. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the +//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfFastStart( void ); + +//***************************************************************************** +// +//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in +//! the ANABYPASS_VALUE2 register in OSC_DIG. +//! +//! \return Returns the trim value. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); + +//***************************************************************************** +// +//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet +//! spanning bits [5:0] in the returned value. +//! +//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register +//! +//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. +// +//***************************************************************************** +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); + +//***************************************************************************** +// +//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) +//! +//! \param ui32VddrTrimVal +//! +//! \return Returns Sign extended VDDR_TRIM setting. +// +//***************************************************************************** +__STATIC_INLINE int32_t +SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +{ + // The VDDR trim value is 5 bits representing the range from -10 to +21 + // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) + int32_t i32SignedVddrVal = ui32VddrTrimVal; + if ( i32SignedVddrVal > 0x15 ) { + i32SignedVddrVal -= 0x20; + } + return ( i32SignedVddrVal ); +} + +//***************************************************************************** +// +//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetCacheModeAccordingToCcfgSetting( void ); + +//***************************************************************************** +// +//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value +//! +//! \param subSecInc +//! +//! \return None +// +//***************************************************************************** +extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); + + +//***************************************************************************** +// +//! \brief Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and +//! setting VDDS_BOD to max) +//! +//! \param toCode specifies the target VDDR trim value. +//! The input parameter \c toCode can be either the signed extended +//! trim value or holding the trim code bits only. +//! +//! \return None +// +//***************************************************************************** +extern void SetupStepVddrTrimTo( uint32_t toCode ); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #undef SetupAfterColdResetWakeupFromShutDownCfg1 + #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #undef SetupAfterColdResetWakeupFromShutDownCfg2 + #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 + #endif + #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #undef SetupAfterColdResetWakeupFromShutDownCfg3 + #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 + #endif + #ifdef ROM_SetupGetTrimForAdcShModeEn + #undef SetupGetTrimForAdcShModeEn + #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn + #endif + #ifdef ROM_SetupGetTrimForAdcShVbufEn + #undef SetupGetTrimForAdcShVbufEn + #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn + #endif + #ifdef ROM_SetupGetTrimForAmpcompCtrl + #undef SetupGetTrimForAmpcompCtrl + #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh1 + #undef SetupGetTrimForAmpcompTh1 + #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 + #endif + #ifdef ROM_SetupGetTrimForAmpcompTh2 + #undef SetupGetTrimForAmpcompTh2 + #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 + #endif + #ifdef ROM_SetupGetTrimForAnabypassValue1 + #undef SetupGetTrimForAnabypassValue1 + #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 + #endif + #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #undef SetupGetTrimForDblrLoopFilterResetVoltage + #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage + #endif + #ifdef ROM_SetupGetTrimForRadcExtCfg + #undef SetupGetTrimForRadcExtCfg + #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg + #endif + #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim + #undef SetupGetTrimForRcOscLfIBiasTrim + #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim + #endif + #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #undef SetupGetTrimForRcOscLfRtuneCtuneTrim + #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim + #endif + #ifdef ROM_SetupGetTrimForXoscHfCtl + #undef SetupGetTrimForXoscHfCtl + #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl + #endif + #ifdef ROM_SetupGetTrimForXoscHfFastStart + #undef SetupGetTrimForXoscHfFastStart + #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart + #endif + #ifdef ROM_SetupGetTrimForXoscHfIbiastherm + #undef SetupGetTrimForXoscHfIbiastherm + #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm + #endif + #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio + #endif + #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting + #undef SetupSetCacheModeAccordingToCcfgSetting + #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting + #endif + #ifdef ROM_SetupSetAonRtcSubSecInc + #undef SetupSetAonRtcSubSecInc + #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc + #endif + #ifdef ROM_SetupStepVddrTrimTo + #undef SetupStepVddrTrimTo + #define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SETUP_ROM_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom_doc.h new file mode 100644 index 00000000..cd8c1e1d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/setup_rom_doc.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* Filename: setup_rom_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup setup_rom_api +//! @{ +//! +//! This module contains functions from the Setup API which are likely to be in ROM. +//! +//! \note Do not use functions from this module directly! This module is only to be used by +//! SetupTrimDevice(). +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.c new file mode 100644 index 00000000..78c42420 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.c @@ -0,0 +1,269 @@ +/****************************************************************************** +* Filename: sha2.c +* +* Description: Driver for the SHA-2 functions of the crypto module +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "sha2.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SHA2StartDMAOperation + #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation + #undef SHA2WaitForIRQFlags + #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags + #undef SHA2ComputeInitialHash + #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash + #undef SHA2ComputeIntermediateHash + #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash + #undef SHA2ComputeFinalHash + #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash + #undef SHA2ComputeHash + #define SHA2ComputeHash NOROM_SHA2ComputeHash +#endif + + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); + + +//***************************************************************************** +// +// Start a SHA-2 DMA operation. +// +//***************************************************************************** +void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) +{ + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + if (channel0Addr) { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +//***************************************************************************** +// +// Poll the IRQ status register and return. +// +//***************************************************************************** +uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) +{ + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + return irqTrigger; +} + +//***************************************************************************** +// +// Start a new SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) +{ + ASSERT(message); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); +} + +//***************************************************************************** +// +// Start an intermediate SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) +{ + ASSERT(message); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); +} + +//***************************************************************************** +// +// Start an intermediate SHA-2 hash operation and finalize it. +// +//***************************************************************************** +uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) +{ + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); +} + +//***************************************************************************** +// +// Start and finalize a new SHA-2 hash operation. +// +//***************************************************************************** +uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) +{ + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); +} + +//***************************************************************************** +// +// Start any SHA-2 hash operation. +// +//***************************************************************************** +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) +{ + uint8_t digestLength = 0; + uint32_t dmaAlgorithmSelect = 0; + + SHA2ClearDigestAvailableFlag(); + + switch (hashAlgorithm) { + case SHA2_MODE_SELECT_SHA224: + digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA256: + digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA384: + digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + case SHA2_MODE_SELECT_SHA512: + digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + default: + return SHA2_INVALID_ALGORITHM; + } + + if (initialHash && finalHash) { + // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot + // handle running with a transfer length of 0. This workaround depends on the hash engine adding the + // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. + // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization + // and determines how many padding-bytes are added. + // Altering totalMsgLength would alter the final hash digest. + // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded + // through the DMA is irrelevant. It is overwritten internally in the hash engine. + messageLength = messageLength ? messageLength : 1; + } + + // Setting the incorrect number of bits here leads to the calculation of the correct result + // but a failure to read them out. + // The tag bit is set to read out the digest via DMA rather than through the slave interface. + SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); + + // Only load the intermediate digest if requested. + if (intermediateDigest && !initialHash) { + SHA2SetDigest(intermediateDigest, digestLength); + } + + // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section + // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. + if (finalHash) { + // This specific length must be specified in bits not bytes. + SHA2SetMessageLength(totalMsgLength * 8); + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; + + } + + // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does + // hash operations in-place. + SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); + + return SHA2_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.h new file mode 100644 index 00000000..e67e5447 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2.h @@ -0,0 +1,800 @@ +/****************************************************************************** +* Filename: sha2.h +* +* Description: SHA-2 header file. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup sha2_api +//! @{ +// +//***************************************************************************** + +#ifndef __SHA2_H__ +#define __SHA2_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_crypto.h" +#include "../inc/hw_ccfg.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation + #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags + #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash + #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash + #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash + #define SHA2ComputeHash NOROM_SHA2ComputeHash +#endif + +//***************************************************************************** +// +// Values that can be passed to SHA2IntEnable, SHA2IntDisable, and SHA2IntClear +// as the intFlags parameter, and returned from SHA2IntStatus. +// Only SHA2_DMA_IN_DONE and SHA2_RESULT_RDY are routed to the NVIC. Check each +// function to see if it supports other interrupt status flags. +// +//***************************************************************************** +#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M) +#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M) +#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M) + + +//***************************************************************************** +// +// General constants +// +//***************************************************************************** + +// SHA-2 module return codes +#define SHA2_SUCCESS 0 +#define SHA2_INVALID_ALGORITHM 1 +#define SHA2_DMA_BUSY 3 +#define SHA2_DMA_ERROR 4 +#define SHA2_DIGEST_NOT_READY 5 +#define SHA2_OLD_DIGEST_NOT_READ 6 + +// SHA-2 output digest lengths in bytes. +#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8) +#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8) +#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8) +#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8) + +//Selectable SHA-2 modes. They determine the algorithm used and if initial +//values will be set to the default constants or not +#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M) +#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M) +#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M) +#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M) +#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M) + +// SHA-2 block lengths. When hashing block-wise, they define the size of each +// block provided to the new and intermediate hash functions. +#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8) +#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8) + +// DMA status codes +#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M) +#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M) +#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M) + +// Crypto module DMA operation types +#define SHA2_ALGSEL_SHA256 0x04 +#define SHA2_ALGSEL_SHA512 0x08 +#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M) + + + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Start a crypto DMA operation +//! +//! Enable the crypto DMA channels, configure the channel addresses, +//! and set the length of the data transfer. +//! Setting the length of the data transfer automatically starts the +//! transfer. It is also used by the hardware module as a signal to +//! begin the encryption, decryption, or MAC operation. +//! +//! \param [in] channel0Addr +//! A pointer to the address channel 0 shall use. +//! +//! \param [in] channel0Length +//! Length of the data in bytes to be read from or written to at +//! \c channel0Addr. Set to 0 to not set up this channel. +//! +//! \param [out] channel1Addr +//! A pointer to the address channel 1 shall use. +//! +//! \param [in] channel1Length +//! Length of the data in bytes to be read from or written to at +//! \c channel1Addr. Set to 0 to not set up this channel. +//! +//! \return None +// +//***************************************************************************** +extern void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); + +//***************************************************************************** +// +//! \brief Poll the interrupt status register and clear when done. +//! +//! This function polls until one of the bits in the \c irqFlags is +//! asserted. Only \ref SHA2_DMA_IN_DONE and \ref SHA2_RESULT_RDY can actually +//! trigger the interrupt line. That means that one of those should +//! always be included in \c irqFlags and will always be returned together +//! with any error codes. +//! +//! \param [in] irqFlags +//! IRQ flags to poll and mask that the status register will be +//! masked with. Consists of any bitwise OR of the flags +//! below that includes at least one of +//! \ref SHA2_DMA_IN_DONE or \ref SHA2_RESULT_RDY : +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +//! +//! \return Returns the IRQ status register masked with \c irqFlags. May be any +//! bitwise OR of the following masks: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +// +//***************************************************************************** +extern uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags); + +//***************************************************************************** +// +//! \brief Start a new SHA-2 hash operation. +//! +//! This function begins a new piecewise hash operation. +//! +//! Call this function when starting a new hash operation and the +//! entire message is not yet available. +//! +//! Call SHA2ComputeIntermediateHash() or SHA2ComputeFinalHash() +//! after this call. +//! +//! If the device shall go into standby in between calls to this +//! function and either SHA2ComputeIntermediateHash() or +//! SHA2ComputeFinalHash(), the intermediate digest must be saved in +//! system RAM. +//! +//! \param [in] message +//! Byte array containing the start of the message to hash. +//! Must be exactly as long as the block length of the selected +//! algorithm. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be stored in the internal +//! registers of the SHA module. +//! - Not NULL Specifies the location the intermediate digest will +//! be written to. +//! +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied into the +//! registers through the AHB slave interface in +//! SHA2ComputeIntermediateHash() and SHA2ComputeFinalHash(). +//! This can only be done word-by-word. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \param [in] initialMessageLength The length in bytes of the first +//! section of the message to process. Must be a multiple of the +//! block size. +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeIntermediateHash() +//! \sa SHA2ComputeFinalHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength); + +//***************************************************************************** +// +//! \brief Resume a SHA-2 hash operation but do not finalize it. +//! +//! This function resumes a previous hash operation. +//! +//! Call this function when continuing a hash operation and the +//! message is not yet complete. +//! +//! Call this function again or SHA2ComputeFinalHash() +//! after this call. +//! +//! If the device shall go into standby in between calls to this +//! function and SHA2ComputeFinalHash(), the intermediate +//! digest must be saved in system RAM. +//! +//! \param [in] message +//! Byte array containing the start of the current block of the +//! message to hash. +//! Must be exactly as long as the block length of the selected +//! algorithm. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [in, out] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be sourced from the internal +//! registers of the SHA module and stored there after the +//! operation completes. +//! - Not NULL Specifies the location the intermediate digest will +//! be read from and written to. +//! +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied from and +//! to the registers through the AHB slave interface. +//! This can only be done word-by-word. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \param [in] intermediateMessageLength The length in bytes of this +//! section of the message to process. Must be a multiple of the +//! block size. +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeInitialHash() +//! \sa SHA2ComputeFinalHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength); + +//***************************************************************************** +// +//! \brief Resume a SHA-2 hash operation and finalize it. +//! +//! This function resumes a previous hash session. +//! +//! Call this function when continuing a hash operation and the +//! message is complete. +//! +//! \param [in] message +//! Byte array containing the final block of the message to hash. +//! Any length <= the block size is acceptable. +//! The DMA finalize the message as necessary. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] resultDigest +//! Byte array that the final digest will be written to. Must be of +//! a length equal to the digest length of the selected hash algorithm. +//! +//! \param [in] intermediateDigest +//! Pointer to intermediate digest. +//! - NULL The intermediate digest will be sourced from the internal +//! registers of the SHA module. +//! - Not NULL Specifies the location the intermediate digest will +//! be read from. +//! Must be of a length equal to the digest length of the selected +//! hash algorithm. +//! Must be 32-bit aligned. \c intermediateDigest is copied from and +//! to the registers through the AHB slave interface. +//! This can only be done word-by-word. +//! +//! \param [in] totalMsgLength +//! The length in bytes of the entire \c message including the sections +//! passed to previous calls to SHA2ComputeInitialHash() and +//! SHA2ComputeIntermediateHash(). +//! +//! \param [in] messageLength The length in bytes of the last +//! section of the message to process. Does not need to be +//! a multiple of the block size. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +//! \sa SHA2ComputeInitialHash() +//! \sa SHA2ComputeIntermediateHash() +// +//***************************************************************************** +extern uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm); + +//***************************************************************************** +// +//! \brief Start a SHA-2 hash operation and return the finalized digest. +//! +//! This function starts a hash operation and returns the finalized +//! digest. +//! +//! Use this function if the entire message is available when starting +//! the hash. +//! +//! \param [in] message +//! Byte array containing the message that will be hashed. +//! Any length <= the block size is acceptable. +//! The DMA will finalize the message as necessary. +//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES +//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES +//! +//! \param [out] resultDigest +//! Byte array that the final digest will be written to. Must be of a +//! length equal to the digest length of the selected hash algorithm. +//! +//! \param [in] totalMsgLength +//! The length in bytes of the entire \c message. +//! +//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: +//! - \ref SHA2_MODE_SELECT_SHA224 +//! - \ref SHA2_MODE_SELECT_SHA256 +//! - \ref SHA2_MODE_SELECT_SHA384 +//! - \ref SHA2_MODE_SELECT_SHA512 +//! +//! \return Returns a SHA-2 return code. +//! - \ref SHA2_SUCCESS +//! - \ref SHA2_INVALID_ALGORITHM +//! +// +//***************************************************************************** +extern uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm); + +//***************************************************************************** +// +//! \brief Configure the crypto DMA for a particular operation. +//! +//! \param algorithm +//! Configures the crypto DMA for a particular operation. +//! It also powers on the respective part of the system. +//! \ref SHA2_ALGSEL_TAG may be combined with another flag. All other +//! flags are mutually exclusive. +//! - 0 : Reset the module and turn off all sub-modules. +//! - \ref SHA2_ALGSEL_SHA256 Configure for a SHA224 or SHA256 operation. +//! - \ref SHA2_ALGSEL_SHA512 Configure for a SHA384 or SHA512 operation. +//! - \ref SHA2_ALGSEL_TAG Read out hash via DMA rather than the slave interface +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2SelectAlgorithm(uint32_t algorithm) +{ + ASSERT((algorithm == SHA2_ALGSEL_SHA256) || + (algorithm == SHA2_ALGSEL_SHA512) || + (algorithm == SHA2_ALGSEL_SHA256 | SHA2_ALGSEL_TAG) || + (algorithm == SHA2_ALGSEL_SHA512 | SHA2_ALGSEL_TAG)); + + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; +} + + + +//***************************************************************************** +// +//! \brief Specify the total length of the message. +//! +//! Despite specifying it here, the crypto DMA must still be +//! set up with the correct data length. +//! +//! Call this function only when setting up the final hash operation to +//! enable finalization. +//! +//! \param length Total message length in bits. +//! +//! \return None +//! +//! \sa SHA2StartDMAOperation() +// +//***************************************************************************** +__STATIC_INLINE void SHA2SetMessageLength(uint32_t length) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = length; + // CRYPTO_O_HASHINLENH is automatically set to 0. No need for the extra write. +} + +//***************************************************************************** +// +//! \brief Load an intermediate digest. +//! +//! \param [in] digestLength +//! Length of the digest in bytes. Must be one of: +//! - \ref SHA2_SHA224_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA256_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA384_DIGEST_LENGTH_BYTES +//! - \ref SHA2_SHA512_DIGEST_LENGTH_BYTES +//! +//! \param [in] digest +//! Pointer to an intermediate digest. Must be 32-bit aligned. +//! +// +//***************************************************************************** +__STATIC_INLINE void SHA2SetDigest(uint32_t *digest, uint8_t digestLength) +{ + // Check the arguments. + ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); + ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); + + // Write digest + uint32_t i = 0; + for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { + HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i]; + } + +} + +//***************************************************************************** +// +//! \brief Read the intermediate or final digest. +//! +//! \param [in] digestLength Length of the digest in bytes. Must be one of: +//! - ref SHA2_SHA224_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA256_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA384_DIGEST_LENGTH_BYTES +//! - ref SHA2_SHA512_DIGEST_LENGTH_BYTES +//! +//! \param [out] digest +//! Pointer to an intermediate digest. Must be 32-bit aligned. +//! +//! \return Returns a status code. +//! - \ref SHA2_OLD_DIGEST_NOT_READ +//! - \ref SHA2_SUCCESS +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2GetDigest(uint32_t *digest, uint8_t digestLength) +{ + // Check the arguments. + ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); + ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || + (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); + + if (HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) & CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M) { + return SHA2_OLD_DIGEST_NOT_READ; + } + else { + // Read digest + uint32_t i = 0; + for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { + digest[i] = HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))); + } + return SHA2_SUCCESS; + } +} + +//***************************************************************************** +// +//! \brief Confirm digest was read. +// +//***************************************************************************** +__STATIC_INLINE void SHA2ClearDigestAvailableFlag(void) +{ + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL); +} + +//***************************************************************************** +// +//! \brief Enable individual crypto interrupt sources. +//! +//! This function enables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntEnable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Using level interrupt. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + + // Enable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; +} + +//***************************************************************************** +// +//! \brief Disable individual crypto interrupt sources. +//! +//! This function disables the indicated crypto interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntDisable(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Disable the specified interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; +} + +//***************************************************************************** +// +//! \brief Get the current masked interrupt status. +//! +//! This function returns the masked interrupt status of the crypto module. +//! +//! \return Returns the status of the masked lines when enabled: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2IntStatusMasked(void) +{ + uint32_t mask; + + // Return the masked interrupt status + mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); + return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Get the current raw interrupt status. +//! +//! This function returns the raw interrupt status of the crypto module. +//! It returns both the status of the lines routed to the NVIC as well as the +//! error flags. +//! +//! \return Returns the raw interrupt status: +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! - \ref SHA2_DMA_BUS_ERR +// +//***************************************************************************** +__STATIC_INLINE uint32_t SHA2IntStatusRaw(void) +{ + // Return either the raw interrupt status + return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); +} + +//***************************************************************************** +// +//! \brief Clear crypto interrupt sources. +//! +//! The specified crypto interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in the module until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref SHA2_DMA_IN_DONE +//! - \ref SHA2_RESULT_RDY +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntClear(uint32_t intFlags) +{ + // Check the arguments. + ASSERT((intFlags & SHA2_DMA_IN_DONE) || + (intFlags & SHA2_RESULT_RDY)); + + // Clear the requested interrupt sources, + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; +} + +//***************************************************************************** +// +//! \brief Register an interrupt handler for a crypto interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific crypto interrupts must be enabled via \ref SHA2IntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param handlerFxn is a pointer to the function to be called when the +//! crypto interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntRegister(void (*handlerFxn)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); + + // Enable the crypto interrupt. + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregister an interrupt handler for a crypto interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler called when a crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void SHA2IntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SHA2StartDMAOperation + #undef SHA2StartDMAOperation + #define SHA2StartDMAOperation ROM_SHA2StartDMAOperation + #endif + #ifdef ROM_SHA2WaitForIRQFlags + #undef SHA2WaitForIRQFlags + #define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags + #endif + #ifdef ROM_SHA2ComputeInitialHash + #undef SHA2ComputeInitialHash + #define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash + #endif + #ifdef ROM_SHA2ComputeIntermediateHash + #undef SHA2ComputeIntermediateHash + #define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash + #endif + #ifdef ROM_SHA2ComputeFinalHash + #undef SHA2ComputeFinalHash + #define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash + #endif + #ifdef ROM_SHA2ComputeHash + #undef SHA2ComputeHash + #define SHA2ComputeHash ROM_SHA2ComputeHash + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SHA2_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2_doc.h new file mode 100644 index 00000000..cc36d80a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sha2_doc.h @@ -0,0 +1,60 @@ +/****************************************************************************** +* Filename: sha2_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup sha2_api +//! @{ +//! \section sec_sha2 Introduction +//! +//! The SHA-2 (Secure Hash Algorithm) API provides access to the SHA-2 +//! functionality of the crypto core. The AES accelerator and keystore are +//! also contained within the crypto core. Hence, only one of SHA-2 and AES +//! may be used at the same time. +//! This module offers hardware acceleration for the SHA-2 family of hash +//! algorithms. The following output digest sizes are supported: +//! - 224 bits +//! - 256 bits +//! - 384 bits +//! - 512 bits +//! +//! Messages are hashed in one go or in multiple steps. Stepwise hashing +//! consists of an initial hash, multiple intermediate hashes, and a +//! finalization hash. +//! +//! The crypto core does not have retention and all configuration settings +//! are lost when going into standby or shutdown. If you wish to continue +//! a hash operation after going into standby or shutdown, you must load +//! the intermediate hash into system RAM before entering standby or shutdown +//! and load the intermediate hash back into the crypto module after resuming +//! operation. +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.c new file mode 100644 index 00000000..ab7b7fbf --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* Filename: smph.c +* +* Description: Driver for the MCU Semaphore. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "smph.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SMPHAcquire + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// Acquire a semaphore +// +//***************************************************************************** +void +SMPHAcquire(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.h new file mode 100644 index 00000000..95bf65fd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph.h @@ -0,0 +1,310 @@ +/****************************************************************************** +* Filename: smph.h +* +* Description: Defines and prototypes for the MCU Semaphore. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup mcusemaphore_api +//! @{ +// +//***************************************************************************** + +#ifndef __SMPH_H__ +#define __SMPH_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_memmap.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SMPHAcquire NOROM_SMPHAcquire +#endif + +//***************************************************************************** +// +// General constants and defines +// +//***************************************************************************** +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed + +//***************************************************************************** +// +// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease +// as the ui32Semaphore parameter. +// +//***************************************************************************** +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Acquire a semaphore. +//! +//! This function acquires the given semaphore, blocking the call until +//! the semaphore is available. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +extern void SMPHAcquire(uint32_t ui32Semaphore); + +//***************************************************************************** +// +//! \brief Try to Acquire a semaphore. +//! +//! This function tries to acquire the given semaphore, if the semaphore +//! could not be claimed the function returns false. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return Returns if a semaphore was acquired +//! - \c true : Semaphore acquired. +//! - \c false : Semaphore \b not acquired. +// +//***************************************************************************** +__STATIC_INLINE bool +SMPHTryAcquire(uint32_t ui32Semaphore) +{ + uint32_t ui32SemaReg; + + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Semaphore register reads 1 if lock was acquired + // (i.e. SMPH_FREE). + ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); + + return (ui32SemaReg == SMPH_FREE); +} + +//***************************************************************************** +// +//! \brief Release a semaphore. +//! +//! This function releases the given semaphore. +//! +//! \note It is up to the application to provide the convention for clearing +//! semaphore. +//! +//! \param ui32Semaphore is the semaphore number. +//! - \ref SMPH_0 +//! - \ref SMPH_1 +//! - ... +//! - \ref SMPH_31 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SMPHRelease(uint32_t ui32Semaphore) +{ + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // No check before release, it is up to the application to provide the + // conventions for who and when a semaphore can be released. + HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SMPHAcquire + #undef SMPHAcquire + #define SMPHAcquire ROM_SMPHAcquire + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SMPH_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph_doc.h new file mode 100644 index 00000000..5e3c37db --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/smph_doc.h @@ -0,0 +1,55 @@ +/****************************************************************************** +* Filename: smph_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup mcusemaphore_api +//! @{ +//! \section sec_mcusemaphore Introduction +//! +//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. +//! One and only one semaphore can be handled during a transaction. +//! +//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). +//! How the semaphores are used and respected is decided by software. +//! +//! \section sec_mcusemaphore_api API +//! +//! The API functions can be grouped like this: +//! +//! Semaphore acquire: +//! - \ref SMPHAcquire() +//! - \ref SMPHTryAcquire() +//! +//! Semaphore release: +//! - \ref SMPHRelease() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.c new file mode 100644 index 00000000..3f08165b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.c @@ -0,0 +1,251 @@ +/****************************************************************************** +* Filename: ssi.c +* +* Description: Driver for Synchronous Serial Interface +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "ssi.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #undef SSIDataPut + #define SSIDataPut NOROM_SSIDataPut + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #undef SSIDataGet + #define SSIDataGet NOROM_SSIDataGet + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #undef SSIIntRegister + #define SSIIntRegister NOROM_SSIIntRegister + #undef SSIIntUnregister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Configures the synchronous serial port +// +//***************************************************************************** +void +SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth) +{ + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +int32_t +SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Puts a data element into the SSI transmit FIFO +// +//***************************************************************************** +void +SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +void +SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +//***************************************************************************** +// +// Gets a data element from the SSI receive FIFO +// +//***************************************************************************** +int32_t +SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the synchronous serial port interrupt. + IntEnable(ui32Int); +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the synchronous serial port +// +//***************************************************************************** +void +SSIIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine the interrupt number based on the SSI port. + ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; + + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.h new file mode 100644 index 00000000..bc2782ce --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/ssi.h @@ -0,0 +1,698 @@ +/****************************************************************************** +* Filename: ssi.h +* +* Description: Defines and macros for the SSI. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup ssi_api +//! @{ +// +//***************************************************************************** + +#ifndef __SSI_H__ +#define __SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_ssi.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk + #define SSIDataPut NOROM_SSIDataPut + #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking + #define SSIDataGet NOROM_SSIDataGet + #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking + #define SSIIntRegister NOROM_SSIIntRegister + #define SSIIntUnregister NOROM_SSIIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that are returned from SSIStatus +// +//***************************************************************************** +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks an SSI base address. +//! +//! This function determines if an SSI module base address is valid. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +SSIBaseValid(uint32_t ui32Base) +{ + return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the synchronous serial port. +//! +//! This function configures the synchronous serial port. It sets +//! the SSI protocol, mode of operation, bit rate, and data width. +//! +//! The \c ui32Protocol parameter defines the data frame format. The Motorola +//! frame formats imply the following polarity and phase configurations: +//! +//! 
+//! Polarity Phase       Mode
+//!   0       0   SSI_FRF_MOTO_MODE_0
+//!   0       1   SSI_FRF_MOTO_MODE_1
+//!   1       0   SSI_FRF_MOTO_MODE_2
+//!   1       1   SSI_FRF_MOTO_MODE_3
+//!
+//! +//! The \c ui32Mode parameter defines the operating mode of the SSI module. +//! The SSI module can operate as a master or slave; if a slave, the SSI can be +//! configured to disable output on its serial output line. +//! +//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit +//! rate must satisfy the following clock ratio criteria: +//! - Master mode : FSSI >= 2 * bit rate +//! - Slave mode : FSSI >= 12 * bit rate +//! +//! where FSSI is the frequency of the clock supplied to the SSI module. +//! +//! The \c ui32DataWidth parameter defines the width of the data transfers, and +//! can be a value between 4 and 16, inclusive. +//! +//! \note The peripheral clock is not necessarily the same as the processor clock. +//! The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. +//! \param ui32Protocol specifies the data transfer protocol. +//! The parameter can be one of the following values: +//! - \ref SSI_FRF_MOTO_MODE_0 +//! - \ref SSI_FRF_MOTO_MODE_1 +//! - \ref SSI_FRF_MOTO_MODE_2 +//! - \ref SSI_FRF_MOTO_MODE_3 +//! - \ref SSI_FRF_TI +//! - \ref SSI_FRF_NMW. +//! \param ui32Mode specifies the mode of operation. +//! The parameter can be one of the following values: +//! - \ref SSI_MODE_MASTER +//! - \ref SSI_MODE_SLAVE +//! - \ref SSI_MODE_SLAVE_OD +//! \param ui32BitRate specifies the clock rate. +//! \param ui32DataWidth specifies number of bits transferred per frame. +//! Must be a value between 4 and 16, both included. +//! +//! \return None +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, uint32_t ui32DataWidth); + +//***************************************************************************** +// +//! \brief Enables the synchronous serial port. +//! +//! This function enables operation of the synchronous serial port. The +//! synchronous serial port must be configured before it is enabled. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; +} + +//***************************************************************************** +// +//! \brief Disables the synchronous serial port. +//! +//! This function disables operation of the synchronous serial port. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Read-modify-write the enable bit. + HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); +} + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the +//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). +//! For example, if the interface is configured for 8-bit data width, the upper +//! 24 bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Puts a data element into the SSI transmit FIFO. +//! +//! This function places the supplied data into the transmit FIFO of the +//! specified SSI module. If there is no space in the FIFO, then this function +//! returns a zero. +//! +//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, +//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For +//! example, if the interface is configured for 8-bit data width, the upper 24 +//! bits of \c ui32Data are discarded. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32Data is the data to be transmitted over the SSI interface. +//! +//! \return Returns the number of elements written to the SSI transmit FIFO. +// +//***************************************************************************** +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified +//! SSI module and places that data into the location specified by the +//! \c pui32Data parameter. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to +//! \c pui32Data contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return None +// +//***************************************************************************** +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Gets a data element from the SSI receive FIFO. +//! +//! This function gets received data from the receive FIFO of the specified SSI +//! module and places that data into the location specified by the \c ui32Data +//! parameter. If there is no data in the FIFO, then this function returns a +//! zero. +//! +//! \note Only the lower N bits of the value written to \c pui32Data contain +//! valid data, where N is the data width as configured by +//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for +//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data +//! contain valid data. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pui32Data is a pointer to a storage location for data that was +//! received over the SSI interface. +//! +//! \return Returns the number of elements read from the SSI receive FIFO. +// +//***************************************************************************** +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); + +//***************************************************************************** +// +//! \brief Determines whether the SSI transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, then the transmit FIFO +//! is empty and all bits of the last transmitted word have left the hardware +//! shift register. +//! +//! \param ui32Base is the base address of the SSI port. +//! +//! \return Returns status of the SSI transmit buffer. +//! - \c true : SSI is transmitting. +//! - \c false : SSI transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +SSIBusy(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Determine if the SSI is busy. + return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); +} + +//***************************************************************************** +// +//! \brief Get the status of the SSI data buffers. +//! +//! This function is used to poll the status of the internal FIFOs in the SSI +//! module. The status of both TX and RX FIFO is returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return Returns the current status of the internal SSI data buffers. +//! The status is a bitwise OR'ed combination of: +//! - \ref SSI_RX_FULL : Receive FIFO full. +//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. +//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. +//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return the status + return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, +//! it is the interrupt handler's responsibility to clear the interrupt source +//! via \ref SSIIntClear(). +//! +//! \param ui32Base specifies the SSI module base address. +//! \param pfnHandler is a pointer to the function to be called when the +//! synchronous serial port interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SSI +//! interrupt occurs. This will also mask off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \param ui32Base specifies the SSI module base address. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void SSIIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual SSI interrupt sources. +//! +//! Enables the indicated SSI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual SSI interrupt sources. +//! +//! Disables the indicated SSI interrupt sources. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Clears SSI interrupt sources. +//! +//! The specified SSI interrupt sources are cleared so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupts from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base specifies the SSI module base address. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter can consist of either or both of: +//! - \ref SSI_RXTO : Timeout interrupt. +//! - \ref SSI_RXOR : Overrun interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the SSI module. Either the +//! raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base specifies the SSI module base address. +//! \param bMasked selects either raw or masked interrupt. +//! \c false : Raw interrupt status is required. +//! \c true : Masked interrupt status is required. +//! +//! \return Returns the current interrupt status as an OR'ed combination of: +//! - \ref SSI_TXFF +//! - \ref SSI_RXFF +//! - \ref SSI_RXTO +//! - \ref SSI_RXOR +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SSIIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + SSI_O_MIS)); + } + else + { + return(HWREG(ui32Base + SSI_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Enable SSI DMA operation. +//! +//! The specified SSI DMA features are enabled. The SSI can be +//! configured to use DMA for transmit and/or receive data transfers. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the SSI. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Enable DMA for receive. +//! - \ref SSI_DMA_TX : Enable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Set the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable SSI DMA operation. +//! +//! This function is used to disable SSI DMA features that were enabled +//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. +//! +//! \param ui32Base is the base address of the SSI port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - \ref SSI_DMA_RX : Disable DMA for receive. +//! - \ref SSI_DMA_TX : Disable DMA for transmit. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Clear the requested bits in the SSI DMA control register. + HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SSIConfigSetExpClk + #undef SSIConfigSetExpClk + #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk + #endif + #ifdef ROM_SSIDataPut + #undef SSIDataPut + #define SSIDataPut ROM_SSIDataPut + #endif + #ifdef ROM_SSIDataPutNonBlocking + #undef SSIDataPutNonBlocking + #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking + #endif + #ifdef ROM_SSIDataGet + #undef SSIDataGet + #define SSIDataGet ROM_SSIDataGet + #endif + #ifdef ROM_SSIDataGetNonBlocking + #undef SSIDataGetNonBlocking + #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking + #endif + #ifdef ROM_SSIIntRegister + #undef SSIIntRegister + #define SSIIntRegister ROM_SSIIntRegister + #endif + #ifdef ROM_SSIIntUnregister + #undef SSIIntUnregister + #define SSIIntUnregister ROM_SSIIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SSI_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_chacha.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_chacha.c new file mode 100644 index 00000000..94ea80fd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_chacha.c @@ -0,0 +1,119 @@ +/****************************************************************************** +* Filename: sw_chacha.c +******************************************************************************/ +/* +chacha-ref.c version 20080118 +D. J. Bernstein +Public domain. +*/ + +#define ECRYPT_LITTLE_ENDIAN + +#include "sw_ecrypt-sync.h" + +#define ROTATE(v,c) (ROTL32(v,c)) +#define XOR(v,w) ((v) ^ (w)) +#define PLUS(v,w) (U32V((v) + (w))) +#define PLUSONE(v) (PLUS((v),1)) + +#define QUARTERROUND(a,b,c,d) \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ + x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ + x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); + +static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) +{ + u32 x[16]; + int i; + + for (i = 0;i < 16;++i) x[i] = input[i]; + for (i = 8;i > 0;i -= 2) { + QUARTERROUND( 0, 4, 8,12) + QUARTERROUND( 1, 5, 9,13) + QUARTERROUND( 2, 6,10,14) + QUARTERROUND( 3, 7,11,15) + QUARTERROUND( 0, 5,10,15) + QUARTERROUND( 1, 6,11,12) + QUARTERROUND( 2, 7, 8,13) + QUARTERROUND( 3, 4, 9,14) + } + for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); + for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); +} + +void ECRYPT_init(void) +{ + return; +} + +static const char sigma[16] = "expand 32-byte k"; +static const char tau[16] = "expand 16-byte k"; + +void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) +{ + const char *constants; + + x->input[4] = U8TO32_LITTLE(k + 0); + x->input[5] = U8TO32_LITTLE(k + 4); + x->input[6] = U8TO32_LITTLE(k + 8); + x->input[7] = U8TO32_LITTLE(k + 12); + if (kbits == 256) { /* recommended */ + k += 16; + constants = sigma; + } else { /* kbits == 128 */ + constants = tau; + } + x->input[8] = U8TO32_LITTLE(k + 0); + x->input[9] = U8TO32_LITTLE(k + 4); + x->input[10] = U8TO32_LITTLE(k + 8); + x->input[11] = U8TO32_LITTLE(k + 12); + x->input[0] = U8TO32_LITTLE(constants + 0); + x->input[1] = U8TO32_LITTLE(constants + 4); + x->input[2] = U8TO32_LITTLE(constants + 8); + x->input[3] = U8TO32_LITTLE(constants + 12); +} + +void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) +{ + x->input[12] = 0; + x->input[13] = 0; + x->input[14] = U8TO32_LITTLE(iv + 0); + x->input[15] = U8TO32_LITTLE(iv + 4); +} + +void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) +{ + u8 output[64]; + int i; + + if (!bytes) return; + for (;;) { + salsa20_wordtobyte(output,x->input); + x->input[12] = PLUSONE(x->input[12]); + if (!x->input[12]) { + x->input[13] = PLUSONE(x->input[13]); + /* stopping at 2^70 bytes per nonce is user's responsibility */ + } + if (bytes <= 64) { + for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; + return; + } + for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; + bytes -= 64; + c += 64; + m += 64; + } +} + +void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) +{ + ECRYPT_encrypt_bytes(x,c,m,bytes); +} + +void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) +{ + u32 i; + for (i = 0;i < bytes;++i) stream[i] = 0; + ECRYPT_encrypt_bytes(x,stream,stream,bytes); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-config.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-config.h new file mode 100644 index 00000000..3ac6862f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-config.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* Filename: sw_ecrypt-config.h +******************************************************************************/ +/* ecrypt-config.h */ + +/* *** Normally, it should not be necessary to edit this file. *** */ + +#ifndef ECRYPT_CONFIG +#define ECRYPT_CONFIG + +/* ------------------------------------------------------------------------- */ + +/* Guess the endianness of the target architecture. */ + +/* + * The LITTLE endian machines: + */ +#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN + +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN + +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined (_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit + * integers. + * + * Note: to enable 64-bit types on 32-bit compilers, it might be + * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc + * -std=c99). + */ + +#include + +/* --- check char --- */ + +#if (UCHAR_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) + +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif + +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check short --- */ + +#if (USHRT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) + +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif + +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check int --- */ + +#if (UINT_MAX / 0xFU > 0xFU) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) + +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif + +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long --- */ + +#if (ULONG_MAX / 0xFUL > 0xFUL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) + +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif + +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif + +#endif +#endif +#endif +#endif + +/* --- check long long --- */ + +#ifdef ULLONG_MAX + +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) + +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif + +#endif + +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif + +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif + +#endif +#endif +#endif +#endif + +#endif + +/* --- check __int64 --- */ + +#ifdef _UI64_MAX + +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-machine.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-machine.h new file mode 100644 index 00000000..c02e6939 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-machine.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* Filename: sw_ecrypt-machine.h +******************************************************************************/ +/* ecrypt-machine.h */ + +/* + * This file is included by 'ecrypt-portable.h'. It allows to override + * the default macros for specific platforms. Please carefully check + * the machine code generated by your compiler (with optimisations + * turned on) before deciding to edit this file. + */ + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) + +#define ECRYPT_MACHINE_ROT + +#if (defined(WIN32) && defined(_MSC_VER)) + +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 + +#include + +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) + +#endif + +#endif + +/* ------------------------------------------------------------------------- */ + +#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) + +#define ECRYPT_MACHINE_SWAP + +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ + +#endif + +/* ------------------------------------------------------------------------- */ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-portable.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-portable.h new file mode 100644 index 00000000..f98cfde8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-portable.h @@ -0,0 +1,306 @@ +/****************************************************************************** +* Filename: sw_ecrypt-portable.h +******************************************************************************/ +/* ecrypt-portable.h */ + +/* + * WARNING: the conversions defined below are implemented as macros, + * and should be used carefully. They should NOT be used with + * parameters which perform some action. E.g., the following two lines + * are not equivalent: + * + * 1) ++x; y = ROTL32(x, n); + * 2) y = ROTL32(++x, n); + */ + +/* + * *** Please do not edit this file. *** + * + * The default macros can be overridden for specific architectures by + * editing 'ecrypt-machine.h'. + */ + +#ifndef ECRYPT_PORTABLE +#define ECRYPT_PORTABLE + +#include "sw_ecrypt-config.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following types are defined (if available): + * + * u8: unsigned integer type, at least 8 bits + * u16: unsigned integer type, at least 16 bits + * u32: unsigned integer type, at least 32 bits + * u64: unsigned integer type, at least 64 bits + * + * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 + * + * The selection of minimum-width integer types is taken care of by + * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit + * compilers, it might be necessary to switch from ISO C90 mode to ISO + * C99 mode (e.g., gcc -std=c99). + */ + +#ifdef I8T +typedef signed I8T s8; +typedef unsigned I8T u8; +#endif + +#ifdef I16T +typedef signed I16T s16; +typedef unsigned I16T u16; +#endif + +#ifdef I32T +typedef signed I32T s32; +typedef unsigned I32T u32; +#endif + +#ifdef I64T +typedef signed I64T s64; +typedef unsigned I64T u64; +#endif + +/* + * The following macros are used to obtain exact-width results. + */ + +#define U8V(v) ((u8)(v) & U8C(0xFF)) +#define U16V(v) ((u16)(v) & U16C(0xFFFF)) +#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) +#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return words with their bits rotated over n + * positions to the left/right. + */ + +#define ECRYPT_DEFAULT_ROT + +#define ROTL8(v, n) \ + (U8V((v) << (n)) | ((v) >> (8 - (n)))) + +#define ROTL16(v, n) \ + (U16V((v) << (n)) | ((v) >> (16 - (n)))) + +#define ROTL32(v, n) \ + (U32V((v) << (n)) | ((v) >> (32 - (n)))) + +#define ROTL64(v, n) \ + (U64V((v) << (n)) | ((v) >> (64 - (n)))) + +#define ROTR8(v, n) ROTL8(v, 8 - (n)) +#define ROTR16(v, n) ROTL16(v, 16 - (n)) +#define ROTR32(v, n) ROTL32(v, 32 - (n)) +#define ROTR64(v, n) ROTL64(v, 64 - (n)) + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +/* + * The following macros return a word with bytes in reverse order. + */ + +#define ECRYPT_DEFAULT_SWAP + +#define SWAP16(v) \ + ROTL16(v, 8) + +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ + (ROTL32(v, 24) & U32C(0xFF00FF00))) + +#ifdef ECRYPT_NATIVE64 +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ + (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ + (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ + (ROTL64(v, 56) & U64C(0xFF000000FF000000))) +#else +#define SWAP64(v) \ + (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) +#endif + +#include "sw_ecrypt-machine.h" + +#define ECRYPT_DEFAULT_WTOW + +#ifdef ECRYPT_LITTLE_ENDIAN +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) + +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) +#endif + +#ifdef ECRYPT_BIG_ENDIAN +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) + +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) +#endif + +#include "sw_ecrypt-machine.h" + +/* + * The following macros load words from an array of bytes with + * different types of endianness, and vice versa. + */ + +#define ECRYPT_DEFAULT_BTOW + +#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) + +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) + +#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) + +#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) + +#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) + +#else + +#define U8TO16_LITTLE(p) \ + (((u16)((p)[0]) ) | \ + ((u16)((p)[1]) << 8)) + +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0]) ) | \ + ((u32)((p)[1]) << 8) | \ + ((u32)((p)[2]) << 16) | \ + ((u32)((p)[3]) << 24)) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0]) ) | \ + ((u64)((p)[1]) << 8) | \ + ((u64)((p)[2]) << 16) | \ + ((u64)((p)[3]) << 24) | \ + ((u64)((p)[4]) << 32) | \ + ((u64)((p)[5]) << 40) | \ + ((u64)((p)[6]) << 48) | \ + ((u64)((p)[7]) << 56)) +#else +#define U8TO64_LITTLE(p) \ + ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) +#endif + +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]) )) + +#define U8TO32_BIG(p) \ + (((u32)((p)[0]) << 24) | \ + ((u32)((p)[1]) << 16) | \ + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]) )) + +#ifdef ECRYPT_NATIVE64 +#define U8TO64_BIG(p) \ + (((u64)((p)[0]) << 56) | \ + ((u64)((p)[1]) << 48) | \ + ((u64)((p)[2]) << 40) | \ + ((u64)((p)[3]) << 32) | \ + ((u64)((p)[4]) << 24) | \ + ((u64)((p)[5]) << 16) | \ + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]) )) +#else +#define U8TO64_BIG(p) \ + (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) +#endif + +#define U16TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_LITTLE(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + (p)[2] = U8V((v) >> 16); \ + (p)[3] = U8V((v) >> 24); \ + (p)[4] = U8V((v) >> 32); \ + (p)[5] = U8V((v) >> 40); \ + (p)[6] = U8V((v) >> 48); \ + (p)[7] = U8V((v) >> 56); \ + } while (0) +#else +#define U64TO8_LITTLE(p, v) \ + do { \ + U32TO8_LITTLE((p), U32V((v) )); \ + U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ + } while (0) +#endif + +#define U16TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) ); \ + (p)[1] = U8V((v) >> 8); \ + } while (0) + +#define U32TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 24); \ + (p)[1] = U8V((v) >> 16); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v) ); \ + } while (0) + +#ifdef ECRYPT_NATIVE64 +#define U64TO8_BIG(p, v) \ + do { \ + (p)[0] = U8V((v) >> 56); \ + (p)[1] = U8V((v) >> 48); \ + (p)[2] = U8V((v) >> 40); \ + (p)[3] = U8V((v) >> 32); \ + (p)[4] = U8V((v) >> 24); \ + (p)[5] = U8V((v) >> 16); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v) ); \ + } while (0) +#else +#define U64TO8_BIG(p, v) \ + do { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v) )); \ + } while (0) +#endif + +#endif + +#include "sw_ecrypt-machine.h" + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-sync.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-sync.h new file mode 100644 index 00000000..4bcb082c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_ecrypt-sync.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: sw_ecrypt-sync.h +******************************************************************************/ +/* ecrypt-sync.h */ + +/* + * Header file for synchronous stream ciphers without authentication + * mechanism. + * + * *** Please only edit parts marked with "[edit]". *** + */ + +#ifndef ECRYPT_SYNC +#define ECRYPT_SYNC + +#include "sw_ecrypt-portable.h" + +/* ------------------------------------------------------------------------- */ + +/* Cipher parameters */ + +/* + * The name of your cipher. + */ +#define ECRYPT_NAME "ChaCha8" +#define ECRYPT_PROFILE "_____" + +/* + * Specify which key and IV sizes are supported by your cipher. A user + * should be able to enumerate the supported sizes by running the + * following code: + * + * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) + * { + * keysize = ECRYPT_KEYSIZE(i); + * + * ... + * } + * + * All sizes are in bits. + */ + +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ + +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ + +/* ------------------------------------------------------------------------- */ + +/* Data structures */ + +/* + * ECRYPT_ctx is the structure containing the representation of the + * internal state of your cipher. + */ + +typedef struct +{ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ +} ECRYPT_ctx; + +/* ------------------------------------------------------------------------- */ + +/* Mandatory functions */ + +/* + * Key and message independent initialization. This function will be + * called once when the program starts (e.g., to build expanded S-box + * tables). + */ +void ECRYPT_init(void); + +/* + * Key setup. It is the user's responsibility to select the values of + * keysize and ivsize from the set of supported values specified + * above. + */ +void ECRYPT_keysetup( + ECRYPT_ctx* ctx, + const u8* key, + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ + +/* + * IV setup. After having called ECRYPT_keysetup(), the user is + * allowed to call ECRYPT_ivsetup() different times in order to + * encrypt/decrypt different messages with the same key but different + * IV's. + */ +void ECRYPT_ivsetup( + ECRYPT_ctx* ctx, + const u8* iv); + +/* + * Encryption/decryption of arbitrary length messages. + * + * For efficiency reasons, the API provides two types of + * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function + * (declared here) encrypts byte strings of arbitrary length, while + * the ECRYPT_encrypt_blocks() function (defined later) only accepts + * lengths which are multiples of ECRYPT_BLOCKLENGTH. + * + * The user is allowed to make multiple calls to + * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, + * but he is NOT allowed to make additional encryption calls once he + * has called ECRYPT_encrypt_bytes() (unless he starts a new message + * of course). For example, this sequence of calls is acceptable: + * + * ECRYPT_keysetup(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_blocks(); + * + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_bytes(); + * + * The following sequence is not: + * + * ECRYPT_keysetup(); + * ECRYPT_ivsetup(); + * ECRYPT_encrypt_blocks(); + * ECRYPT_encrypt_bytes(); + * ECRYPT_encrypt_blocks(); + */ + +void ECRYPT_encrypt_bytes( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 msglen); /* Message length in bytes. */ + +void ECRYPT_decrypt_bytes( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 msglen); /* Message length in bytes. */ + +/* ------------------------------------------------------------------------- */ + +/* Optional features */ + +/* + * For testing purposes it can sometimes be useful to have a function + * which immediately generates keystream without having to provide it + * with a zero plaintext. If your cipher cannot provide this function + * (e.g., because it is not strictly a synchronous cipher), please + * reset the ECRYPT_GENERATES_KEYSTREAM flag. + */ + +#define ECRYPT_GENERATES_KEYSTREAM +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_bytes( + ECRYPT_ctx* ctx, + u8* keystream, + u32 length); /* Length of keystream in bytes. */ + +#endif + +/* ------------------------------------------------------------------------- */ + +/* Optional optimizations */ + +/* + * By default, the functions in this section are implemented using + * calls to functions declared above. However, you might want to + * implement them differently for performance reasons. + */ + +/* + * All-in-one encryption/decryption of (short) packets. + * + * The default definitions of these functions can be found in + * "ecrypt-sync.c". If you want to implement them differently, please + * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. + */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ + +void ECRYPT_encrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* plaintext, + u8* ciphertext, + u32 msglen); + +void ECRYPT_decrypt_packet( + ECRYPT_ctx* ctx, + const u8* iv, + const u8* ciphertext, + u8* plaintext, + u32 msglen); + +/* + * Encryption/decryption of blocks. + * + * By default, these functions are defined as macros. If you want to + * provide a different implementation, please undef the + * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions + * declared below. + */ + +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ + +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS + +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ + (blocks) * ECRYPT_BLOCKLENGTH) + +#endif + +#else + +void ECRYPT_encrypt_blocks( + ECRYPT_ctx* ctx, + const u8* plaintext, + u8* ciphertext, + u32 blocks); /* Message length in blocks. */ + +void ECRYPT_decrypt_blocks( + ECRYPT_ctx* ctx, + const u8* ciphertext, + u8* plaintext, + u32 blocks); /* Message length in blocks. */ + +#ifdef ECRYPT_GENERATES_KEYSTREAM + +void ECRYPT_keystream_blocks( + ECRYPT_ctx* ctx, + const u8* keystream, + u32 blocks); /* Keystream length in blocks. */ + +#endif + +#endif + +/* + * If your cipher can be implemented in different ways, you can use + * the ECRYPT_VARIANT parameter to allow the user to choose between + * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please + * only use this possibility if you really think it could make a + * significant difference and keep the number of variants + * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than + * 10). Note also that all variants should have exactly the same + * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). + */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ + +#ifndef ECRYPT_VARIANT +#define ECRYPT_VARIANT 1 +#endif + +#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) +#error this variant does not exist +#endif + +/* ------------------------------------------------------------------------- */ + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna-32.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna-32.h new file mode 100644 index 00000000..4ef50b8a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna-32.h @@ -0,0 +1,221 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna-32.h +******************************************************************************/ +/* + poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition +*/ + +#if defined(_MSC_VER) + #define POLY1305_NOINLINE __declspec(noinline) +#elif defined(__GNUC__) + #define POLY1305_NOINLINE __attribute__((noinline)) +#else + #define POLY1305_NOINLINE +#endif + +#define poly1305_block_size 16 + +/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ +typedef struct { + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; +} poly1305_state_internal_t; + +/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ +static unsigned long +U8TO32(const unsigned char *p) { + return + (((unsigned long)(p[0] & 0xff) ) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); +} + +/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ +static void +U32TO8(unsigned char *p, unsigned long v) { + p[0] = (v ) & 0xff; + p[1] = (v >> 8) & 0xff; + p[2] = (v >> 16) & 0xff; + p[3] = (v >> 24) & 0xff; +} + +void +poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + + /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ + st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; + st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; + + /* h = 0 */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + + /* save pad for later */ + st->pad[0] = U8TO32(&key[16]); + st->pad[1] = U8TO32(&key[20]); + st->pad[2] = U8TO32(&key[24]); + st->pad[3] = U8TO32(&key[28]); + + st->leftover = 0; + st->final = 0; +} + +static void +poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { + const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ + unsigned long r0,r1,r2,r3,r4; + unsigned long s1,s2,s3,s4; + unsigned long h0,h1,h2,h3,h4; + unsigned long long d0,d1,d2,d3,d4; + unsigned long c; + + r0 = st->r[0]; + r1 = st->r[1]; + r2 = st->r[2]; + r3 = st->r[3]; + r4 = st->r[4]; + + s1 = r1 * 5; + s2 = r2 * 5; + s3 = r3 * 5; + s4 = r4 * 5; + + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + while (bytes >= poly1305_block_size) { + /* h += m[i] */ + h0 += (U8TO32(m+ 0) ) & 0x3ffffff; + h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; + h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; + h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; + h4 += (U8TO32(m+12) >> 8) | hibit; + + /* h *= r */ + d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); + d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); + d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); + d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); + d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); + + /* (partial) h %= p */ + c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; + d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; + d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; + d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; + d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; + h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; + h1 += c; + + m += poly1305_block_size; + bytes -= poly1305_block_size; + } + + st->h[0] = h0; + st->h[1] = h1; + st->h[2] = h2; + st->h[3] = h3; + st->h[4] = h4; +} + +POLY1305_NOINLINE void +poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + unsigned long h0,h1,h2,h3,h4,c; + unsigned long g0,g1,g2,g3,g4; + unsigned long long f; + unsigned long mask; + + /* process the remaining block */ + if (st->leftover) { + size_t i = st->leftover; + st->buffer[i++] = 1; + for (; i < poly1305_block_size; i++) + st->buffer[i] = 0; + st->final = 1; + poly1305_blocks(st, st->buffer, poly1305_block_size); + } + + /* fully carry h */ + h0 = st->h[0]; + h1 = st->h[1]; + h2 = st->h[2]; + h3 = st->h[3]; + h4 = st->h[4]; + + c = h1 >> 26; h1 = h1 & 0x3ffffff; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; + h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; + h1 += c; + + /* compute h + -p */ + g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; + g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; + g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; + g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; + g4 = h4 + c - (1UL << 26); + + /* select h if h < p, or h + -p if h >= p */ + mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; + g0 &= mask; + g1 &= mask; + g2 &= mask; + g3 &= mask; + g4 &= mask; + mask = ~mask; + h0 = (h0 & mask) | g0; + h1 = (h1 & mask) | g1; + h2 = (h2 & mask) | g2; + h3 = (h3 & mask) | g3; + h4 = (h4 & mask) | g4; + + /* h = h % (2^128) */ + h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + + /* mac = (h + pad) % (2^128) */ + f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; + f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; + f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; + f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; + + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); + U32TO8(mac + 12, h3); + + /* zero out the state */ + st->h[0] = 0; + st->h[1] = 0; + st->h[2] = 0; + st->h[3] = 0; + st->h[4] = 0; + st->r[0] = 0; + st->r[1] = 0; + st->r[2] = 0; + st->r[3] = 0; + st->r[4] = 0; + st->pad[0] = 0; + st->pad[1] = 0; + st->pad[2] = 0; + st->pad[3] = 0; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.c new file mode 100644 index 00000000..26843629 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.c @@ -0,0 +1,184 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.c +******************************************************************************/ + +#include "sw_poly1305-donna.h" + +#include "sw_poly1305-donna-32.h" + +void +poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { + poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; + size_t i; + + /* handle leftover */ + if (st->leftover) { + size_t want = (poly1305_block_size - st->leftover); + if (want > bytes) + want = bytes; + for (i = 0; i < want; i++) + st->buffer[st->leftover + i] = m[i]; + bytes -= want; + m += want; + st->leftover += want; + if (st->leftover < poly1305_block_size) + return; + poly1305_blocks(st, st->buffer, poly1305_block_size); + st->leftover = 0; + } + + /* process full blocks */ + if (bytes >= poly1305_block_size) { + size_t want = (bytes & ~(poly1305_block_size - 1)); + poly1305_blocks(st, m, want); + m += want; + bytes -= want; + } + + /* store leftover */ + if (bytes) { + for (i = 0; i < bytes; i++) + st->buffer[st->leftover + i] = m[i]; + st->leftover += bytes; + } +} + +void +poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { + poly1305_context ctx; + poly1305_init(&ctx, key); + poly1305_update(&ctx, m, bytes); + poly1305_finish(&ctx, mac); +} + +int +poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { + size_t i; + unsigned int dif = 0; + for (i = 0; i < 16; i++) + dif |= (mac1[i] ^ mac2[i]); + dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); + return (dif & 1); +} + + +/* test a few basic operations */ +int +poly1305_power_on_self_test(void) { + /* example from nacl */ + static const unsigned char nacl_key[32] = { + 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, + 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, + 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, + 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 + }; + + static const unsigned char nacl_msg[131] = { + 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, + 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, + 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, + 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, + 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, + 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, + 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, + 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, + 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, + 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, + 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, + 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, + 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, + 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, + 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, + 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, + 0xe3,0x55,0xa5 + }; + + static const unsigned char nacl_mac[16] = { + 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, + 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 + }; + + /* generates a final value of (2^130 - 2) == 3 */ + static const unsigned char wrap_key[32] = { + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + static const unsigned char wrap_msg[16] = { + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char wrap_mac[16] = { + 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + }; + + /* + mac of the macs of messages of length 0 to 256, where the key and messages + have all their values set to the length + */ + static const unsigned char total_key[32] = { + 0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff + }; + + static const unsigned char total_mac[16] = { + 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, + 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 + }; + + poly1305_context ctx; + poly1305_context total_ctx; + unsigned char all_key[32]; + unsigned char all_msg[256]; + unsigned char mac[16]; + size_t i, j; + int result = 1; + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_init(&ctx, nacl_key); + poly1305_update(&ctx, nacl_msg + 0, 32); + poly1305_update(&ctx, nacl_msg + 32, 64); + poly1305_update(&ctx, nacl_msg + 96, 16); + poly1305_update(&ctx, nacl_msg + 112, 8); + poly1305_update(&ctx, nacl_msg + 120, 4); + poly1305_update(&ctx, nacl_msg + 124, 2); + poly1305_update(&ctx, nacl_msg + 126, 1); + poly1305_update(&ctx, nacl_msg + 127, 1); + poly1305_update(&ctx, nacl_msg + 128, 1); + poly1305_update(&ctx, nacl_msg + 129, 1); + poly1305_update(&ctx, nacl_msg + 130, 1); + poly1305_finish(&ctx, mac); + result &= poly1305_verify(nacl_mac, mac); + + for (i = 0; i < sizeof(mac); i++) + mac[i] = 0; + poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); + result &= poly1305_verify(wrap_mac, mac); + + poly1305_init(&total_ctx, total_key); + for (i = 0; i < 256; i++) { + /* set key and message to 'i,i,i..' */ + for (j = 0; j < sizeof(all_key); j++) + all_key[j] = i; + for (j = 0; j < i; j++) + all_msg[j] = i; + poly1305_auth(mac, all_msg, i, all_key); + poly1305_update(&total_ctx, mac, 16); + } + poly1305_finish(&total_ctx, mac); + result &= poly1305_verify(total_mac, mac); + + return result; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.h new file mode 100644 index 00000000..621fcfbb --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sw_poly1305-donna.h @@ -0,0 +1,23 @@ +/****************************************************************************** +* Filename: sw_poly1305-donna.h +******************************************************************************/ + +#ifndef POLY1305_DONNA_H +#define POLY1305_DONNA_H + +#include + +typedef struct { + size_t aligner; + unsigned char opaque[136]; +} poly1305_context; + +void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); +void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); +void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); +void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); + +int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); +int poly1305_power_on_self_test(void); + +#endif /* POLY1305_DONNA_H */ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.c new file mode 100644 index 00000000..44d8c6b4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.c @@ -0,0 +1,361 @@ +/****************************************************************************** +* Filename: sys_ctrl.c +* +* Description: Driver for the System Control. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +// Hardware headers +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ioc.h" +// Driverlib headers +#include "aon_batmon.h" +#include "flash.h" +#include "gpio.h" +#include "setup_rom.h" +#include "sys_ctrl.h" + + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef SysCtrlIdle + #define SysCtrlIdle NOROM_SysCtrlIdle + #undef SysCtrlShutdownWithAbort + #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort + #undef SysCtrlShutdown + #define SysCtrlShutdown NOROM_SysCtrlShutdown + #undef SysCtrlStandby + #define SysCtrlStandby NOROM_SysCtrlStandby + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + + +//***************************************************************************** +// +// Force the system in to idle mode +// +//***************************************************************************** +void SysCtrlIdle(uint32_t vimsPdMode) +{ + // Configure the VIMS mode + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS) = vimsPdMode; + + // Always keep cache retention ON in IDLE + PRCMCacheRetentionEnable(); + + // Turn off the CPU power domain, will take effect when PRCMDeepSleep() executes + PRCMPowerDomainOff(PRCM_DOMAIN_CPU); + + // Ensure any possible outstanding AON writes complete + SysCtrlAonSync(); + + // Invoke deep sleep to go to IDLE + PRCMDeepSleep(); +} + +//***************************************************************************** +// +// Try to enter shutdown but abort if wakeup event happened before shutdown +// +//***************************************************************************** +void SysCtrlShutdownWithAbort(void) +{ + uint32_t wakeupDetected = 0; + uint32_t ioIndex = 0; + + uint32_t ioCount = (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & + FCFG1_IOCONF_GPIO_CNT_M ) >> FCFG1_IOCONF_GPIO_CNT_S ) ; + + // Wakeup events are detected when pads are in sleep mode + PowerCtrlPadSleepEnable(); + + // Make sure all potential events have propagated before checking event flags + SysCtrlAonUpdate(); + SysCtrlAonUpdate(); + + // For all IO CFG registers check if wakeup detect is enabled + for(ioIndex = 0; ioIndex < ioCount; ioIndex++) + { + // Read MSB from WU_CFG bit field + if( HWREG(IOC_BASE + IOC_O_IOCFG0 + (ioIndex * 4) ) & (1 << (IOC_IOCFG0_WU_CFG_S + IOC_IOCFG0_WU_CFG_W - 1)) ) + { + if (GPIO_getEventDio(ioIndex)) + { + wakeupDetected = 1; + break; + } + } + } + + // If no edge detect flags for wakeup enabled IOs are set then shut down the device + if( wakeupDetected == 0 ) + { + SysCtrlShutdown(); + } + else + { + PowerCtrlPadSleepDisable(); + } +} + +//***************************************************************************** +// +// Force the system into shutdown mode +// +//***************************************************************************** +void SysCtrlShutdown(void) +{ + // Request shutdown mode + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SHUTDOWN) = AON_PMCTL_SHUTDOWN_EN; + + // Make sure System CPU does not continue beyond this point. + // Shutdown happens when all shutdown conditions are met. + while(1); +} + +//***************************************************************************** +// +// Force the system in to standby mode +// +//***************************************************************************** +void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode) +{ + uint32_t modeVIMS; + + // In external regulator mode: + // Set static recharge timing to approximately 500 milliseconds + // Else: + // Handle compensation for improving RCOSC_LF stability at low temperatures + // as configured in CCFG + SysCtrlSetRechargeBeforePowerDown(XOSC_IN_HIGH_POWER_MODE); + + // Freeze the IOs on the boundary between MCU and AON + AONIOCFreezeEnable(); + + // Ensure any possible outstanding AON writes complete before turning off the power domains + SysCtrlAonSync(); + + // Request power off of domains in the MCU voltage domain + PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU); + + // Ensure that no clocks are forced on in any modes for Crypto, DMA and I2S + HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_DMA_AM_CLK_EN); + HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN; + + // Gate running deep sleep clocks for Crypto, DMA and I2S + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_I2S); + + // Load the new clock settings + PRCMLoadSet(); + + // Configure the VIMS power domain mode + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; + + // Request uLDO during standby + PRCMMcuUldoConfigure(1); + + // In external regulator mode: + // - Setting the AON_PMCTL_O_RECHARGECFG register is already handled above. + // (in function SysCtrlSetRechargeBeforePowerDown() ) + // Else: + // - Set the AON_PMCTL_O_RECHARGECFG register as described below. + if ((HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE)==0) + { + // In internal regulator mode the recharge functionality is set up with + // adaptive recharge mode and fixed parameter values + if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE) + { + // Enable the Recharge Comparator + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR; + } + else + { + // Set requested recharge mode + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = rechargeMode; + } + } + + // Ensure all writes have taken effect + SysCtrlAonSync(); + + // Ensure UDMA, Crypto and I2C clocks are turned off + while (!PRCMLoadGet()) {;} + + // Ensure power domains have been turned off. + // CPU power domain will power down when PRCMDeepSleep() executes. + while (PRCMPowerDomainsAllOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF) {;} + + // Turn off cache retention if requested + if (retainCache == false) { + + // Get the current VIMS mode + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + // If in a cache mode, turn VIMS off + if (modeVIMS == VIMS_MODE_ENABLED) { + VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF); + } + + // Disable retention of cache RAM + PRCMCacheRetentionDisable(); + } + + // Invoke deep sleep to go to STANDBY + PRCMDeepSleep(); +} + +//***************************************************************************** +// +// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) +// +//***************************************************************************** +void +SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) +{ + + // If external regulator mode we shall: + // - Set static recharge timing in AON_PMCTL_RECHARGECFG (MODE_STATIC) + // - Set recharge period to approximately 500 mS (perM=31, perE=5 => 0xFD) + if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG ) = ( AON_PMCTL_RECHARGECFG_MODE_STATIC | 0x000000FD ); + return; + } + +} + + +//***************************************************************************** +// +// SysCtrlAdjustRechargeAfterPowerDown() +// +//***************************************************************************** +void +SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) +{ + // Nothing to be done but keeping this function for platform compatibility. +} + + +//***************************************************************************** +// +// SysCtrl_DCDC_VoltageConditionalControl() +// +//***************************************************************************** +void +SysCtrl_DCDC_VoltageConditionalControl( void ) +{ + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } + } + } +} + + +//***************************************************************************** +// +// SysCtrlResetSourceGet() +// +//***************************************************************************** +uint32_t +SysCtrlResetSourceGet( void ) +{ + uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); + + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); + } + } else { + return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.h new file mode 100644 index 00000000..182f1676 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/sys_ctrl.h @@ -0,0 +1,576 @@ +/****************************************************************************** +* Filename: sys_ctrl.h +* +* Description: Defines and prototypes for the System Controller. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup sysctrl_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSCTRL_H__ +#define __SYSCTRL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_fcfg1.h" +#include "interrupt.h" +#include "debug.h" +#include "pwr_ctrl.h" +#include "osc.h" +#include "prcm.h" +#include "adi.h" +#include "ddi.h" +#include "cpu.h" +#include "vims.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define SysCtrlIdle NOROM_SysCtrlIdle + #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort + #define SysCtrlShutdown NOROM_SysCtrlShutdown + #define SysCtrlStandby NOROM_SysCtrlStandby + #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown + #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#endif + +//***************************************************************************** +// +// Defines for the settings of the main XOSC +// +//***************************************************************************** +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 + +//***************************************************************************** +// +// Defines for the different power modes of the System CPU +// +//***************************************************************************** +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 + +//***************************************************************************** +// +// Defines for SysCtrlSetRechargeBeforePowerDown +// +//***************************************************************************** +#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC + +//***************************************************************************** +// +// Defines for the vimsPdMode parameter of SysCtrlIdle and SysCtrlStandby +// +//***************************************************************************** +#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered +#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered +#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup. + +//***************************************************************************** +// +// Defines for the rechargeMode parameter of SysCtrlStandby +// +//***************************************************************************** +#define SYSCTRL_PREFERRED_RECHARGE_MODE \ + 0xFFFFFFFF // Preferred recharge mode + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Force the system into idle mode. +//! +//! This function forces the system into IDLE mode by configuring the requested +//! VIMS mode, enabling cache retention and powering off the CPU power domain. +//! +//! \param vimsPdMode selects the requested VIMS power domain mode +//! The parameter must be one of the following: +//! - \ref VIMS_ON_CPU_ON_MODE +//! - \ref VIMS_ON_BUS_ON_MODE +//! - \ref VIMS_NO_PWR_UP_MODE +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlIdle(uint32_t vimsPdMode); + +//***************************************************************************** +// +//! \brief Try to enter shutdown but abort if wakeup event happened before shutdown. +//! +//! This function puts the device in shutdown state if no wakeup events are +//! detected before shutdown. +//! +//! Compared to the basic \ref SysCtrlShutdown() function this function makes sure +//! that wakeup events that happen before actual shutdown are also detected. This +//! function either enters shutdown with a guaranteed wakeup detection or returns +//! to the caller function due to a pre-shutdown wakeup event. +//! +//! See \ref SysCtrlShutdown() for basic information about how to configure the device before +//! shutdown and how to wakeup from shutdown. +//! +//! This function uses IO edge detection in addition to the mandatory wakeup configuration. +//! Additional requirements to the application for this function are: +//! - \b Before : +//! - When the application configures an IO for wakeup (see \ref IOCIOShutdownSet()) +//! the application must also configure the same IO for edge detection +//! (see \ref IOCIOIntSet()). +//! - Edge detection must use the same polarity as the wakeup configuration. +//! - Application must enable peripheral power domain (see \ref PRCMPowerDomainOn()) +//! and enable GPIO module in the peripheral power domain (see \ref PRCMPeripheralRunEnable()). +//! - \b After : +//! - An edge, with same polarity as a wakeup event, was detected on a wakeup +//! enabled IO before shutdown, and the shutdown was aborted. The application must +//! clear the event generated by the edge detect (see \ref GPIO_clearEventDio()) and +//! decide what happens next. +//! +//! Useful functions related to shutdown: +//! - \ref IOCIOShutdownSet() : Enables wakeup from shutdown. +//! - \ref IOCIOIntSet() : Enables IO edge detection. +//! - \ref PRCMPowerDomainOn() : Enables peripheral power domain. +//! - \ref PRCMPeripheralRunEnable() : Enables GPIO module. +//! - \ref SysCtrlResetSourceGet() : Detects wakeup from shutdown. +//! - \ref PowerCtrlPadSleepDisable() : Unlatches outputs (disables pad sleep) after +//! wakeup from shutdown. +//! - \ref GPIO_clearEventDio() : Clears edge detects. +//! +//! It is recommended to disable interrupts before calling this function because: +//! - Pads are in sleep mode while this function runs. +//! - An interrupt routine might be terminated if it is triggered after the decision +//! to enter shutdown. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlShutdownWithAbort(void); + +//***************************************************************************** +// +//! \brief Enable shutdown of the device. +//! +//! This function puts the device in shutdown state. The device automatically +//! latches all outputs (pads in sleep) before it turns off all internal power +//! supplies. +//! +//! JTAG must be disconnected and JTAG power domain must be off before device can +//! enter shutdown. This function waits until the device satisfies all shutdown +//! conditions before it enters shutdown. +//! +//! \note The application must unlatch the outputs when the device wakes up from shutdown. +//! It is recommended that any outputs that need to be restored after a wakeup from +//! shutdown are restored before outputs are unlatched in order to avoid glitches. +//! +//! See \ref PowerCtrlPadSleepDisable() for information about how to unlatch outputs +//! (disable pad sleep) after wakeup from shutdown. +//! +//! \note Wakeup events are only detected after the device enters shutdown. +//! +//! See \ref IOCIOShutdownSet() for information about how to enable wakeup from shutdown. +//! +//! See \ref SysCtrlResetSourceGet() for information about how to detect wakeup +//! from shutdown. +//! +//! It is recommended to disable interrupts before calling this function. Shutdown +//! happens immediately when the device satisfies all shutdown conditions thus +//! interrupt routines triggered after this function is called might be +//! aborted. +//! +//! \return This function does \b not return. +// +//***************************************************************************** +extern void SysCtrlShutdown(void); + + +//***************************************************************************** +// +//! \brief Force the system into standby mode. +//! +//! This function forces all power domains (RFCORE, SERIAL, PERIPHERAL) off. +//! The VIMS and CPU power domains are turned off by the HW when the +//! \ref PRCMDeepSleep() function is called. +//! The IOs are latched (frozen) before the power domains are turned off to +//! avoid glitches. +//! The VIMS retention (cache) and VIMS module are turned off if requested. +//! The deep-sleep clock for the crypto and DMA modules are turned off, +//! as they must be off in order to enter standby. +//! This function assumes that the LF clock has already been switched to +//! and that the LF clock qualifiers must have been disabled/bypassed. +//! +//! In internal regulator mode the adaptive recharge functionality is enabled +//! with fixed parameter values. +//! In external regulator mode the recharge functionality is disabled. +//! +//! \note This function is optimized to execute with TI-RTOS. There might be +//! application specific prerequisites you would want to do before entering +//! standby which deviate from this specific implementation. +//! +//! \param retainCache selects if VIMS cache shall be retained or not. +//! - false : VIMS cache is not retained +//! - true : VIMS cache is retained +//! \param vimsPdMode selects the VIMS power domain mode. +//! The parameter must be one of the following: +//! - \ref VIMS_ON_CPU_ON_MODE +//! - \ref VIMS_NO_PWR_UP_MODE +//! \param rechargeMode specifies the requested recharge mode. +//! The parameter must be one of the following: +//! - \ref SYSCTRL_PREFERRED_RECHARGE_MODE : Preferred recharge mode specified by TI +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode); + +//***************************************************************************** +// +//! \brief Get the CPU core clock frequency. +//! +//! Use this function to get the current clock frequency for the CPU. +//! +//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined +//! by the combined division factor of the SYSBUS and the CPU clock divider. +//! +//! \return Returns the current CPU core clock frequency. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysCtrlClockGet( void ) +{ + // Return fixed clock speed + return( GET_MCU_CLOCK ); +} + +//***************************************************************************** +// +//! \brief Sync all accesses to the AON register interface. +//! +//! When this function returns, all writes to the AON register interface are +//! guaranteed to have propagated to hardware. The function will return +//! immediately if no AON writes are pending; otherwise, it will wait for the next +//! AON clock before returning. +//! +//! \return None +//! +//! \sa \ref SysCtrlAonUpdate() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonSync(void) +{ + // Sync the AON interface + HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Update all interfaces to AON. +//! +//! When this function returns, at least 1 clock cycle has progressed on the +//! AON domain, so that any outstanding updates to and from the AON interface +//! is guaranteed to be in sync. +//! +//! \note This function should primarily be used after wakeup from sleep modes, +//! as it will guarantee that all shadow registers on the AON interface are updated +//! before reading any AON registers from the MCU domain. If a write has been +//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). +//! +//! \return None +//! +//! \sa \ref SysCtrlAonSync() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlAonUpdate(void) +{ + // Force a clock cycle on the AON interface to guarantee all registers are + // in sync. + HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC) = 1; + HWREG(AON_RTC_BASE + NONSECURE_OFFSET + AON_RTC_O_SYNC); +} + +//***************************************************************************** +// +//! \brief Set Recharge values before entering Power Down. +//! +//! This function shall be called just before entering Power Down. +//! This function typically does nothing (default setting), but +//! if temperature compensated recharge level are enabled (by setting +//! CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0) +//! it adds temperature compensation to the recharge level. +//! +//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). +//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. +//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); + +//***************************************************************************** +// +//! \brief Adjust Recharge calculations to be used next. +//! +//! Nothing to be done but keeping this function for platform compatibility. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); + +//***************************************************************************** +// +//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. +//! +//! This function controls the DCDC only if both the following CCFG settings are \c true: +//! - DCDC is configured to be used. +//! - Alternative DCDC settings are defined and enabled. +//! +//! The DCDC is configured in accordance to the CCFG settings when turned on. +//! +//! This function should be called periodically. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtrl_DCDC_VoltageConditionalControl( void ); + +//***************************************************************************** +// \name Return values from calling SysCtrlResetSourceGet() +//@{ +//***************************************************************************** +#define RSTSRC_PWR_ON (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_PIN_RESET (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDS_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_VDDR_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_CLK_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_SYSRESET (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WARMRESET (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 ) +#define RSTSRC_WAKEUP_FROM_TCK_NOISE ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 ) +//@} + +//***************************************************************************** +// +//! \brief Returns the reset source (including "wakeup from shutdown"). +//! +//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is +//! responsible for unlatching the outputs (disable pad sleep). +//! See \ref PowerCtrlPadSleepDisable() for more information. +//! +//! \return Returns the reset source. +//! - \ref RSTSRC_PWR_ON +//! - \ref RSTSRC_PIN_RESET +//! - \ref RSTSRC_VDDS_LOSS +//! - \ref RSTSRC_VDDR_LOSS +//! - \ref RSTSRC_CLK_LOSS +//! - \ref RSTSRC_SYSRESET +//! - \ref RSTSRC_WARMRESET +//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN +//! - \ref RSTSRC_WAKEUP_FROM_TCK_NOISE +// +//***************************************************************************** +extern uint32_t SysCtrlResetSourceGet( void ); + +//***************************************************************************** +// +//! \brief Perform a full system reset. +//! +//! \return The chip will reset and hence never return from this call. +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlSystemReset( void ) +{ + // Disable CPU interrupts + CPUcpsid(); + // Write reset register + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; + // Finally, wait until the above write propagates + while ( 1 ) { + // Do nothing, just wait for the reset (and never return from here) + } +} + +//***************************************************************************** +// +//! \brief Enables reset if OSC clock loss event is asserted. +//! +//! Clock loss circuit in analog domain must be enabled as well in order to +//! actually enable for a clock loss reset to occur +//! \ref OSCClockLossEventEnable(). +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetEnable(void) +{ + // Set clock loss enable bit in AON_SYSCTRL + HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables reset due to OSC clock loss event. +//! +//! \note This function shall typically not be called because the clock loss +//! reset functionality is controlled by the boot code (a factory configuration +//! defines whether it is set or not). +//! +//! \return None +//! +//! \sa \ref SysCtrlClockLossResetEnable() +// +//***************************************************************************** +__STATIC_INLINE void +SysCtrlClockLossResetDisable(void) +{ + // Clear clock loss enable bit in AON_SYSCTRL + HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_SysCtrlIdle + #undef SysCtrlIdle + #define SysCtrlIdle ROM_SysCtrlIdle + #endif + #ifdef ROM_SysCtrlShutdownWithAbort + #undef SysCtrlShutdownWithAbort + #define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort + #endif + #ifdef ROM_SysCtrlShutdown + #undef SysCtrlShutdown + #define SysCtrlShutdown ROM_SysCtrlShutdown + #endif + #ifdef ROM_SysCtrlStandby + #undef SysCtrlStandby + #define SysCtrlStandby ROM_SysCtrlStandby + #endif + #ifdef ROM_SysCtrlSetRechargeBeforePowerDown + #undef SysCtrlSetRechargeBeforePowerDown + #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown + #endif + #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown + #undef SysCtrlAdjustRechargeAfterPowerDown + #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown + #endif + #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl + #undef SysCtrl_DCDC_VoltageConditionalControl + #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl + #endif + #ifdef ROM_SysCtrlResetSourceGet + #undef SysCtrlResetSourceGet + #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTRL_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.c new file mode 100644 index 00000000..cfa81d5f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: systick.c +* +* Description: Driver for the SysTick timer +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "systick.h" + +// See systick.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.h new file mode 100644 index 00000000..90d38e5b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick.h @@ -0,0 +1,286 @@ +/****************************************************************************** +* Filename: systick.h +* +* Description: Prototypes for the SysTick driver. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_cpu_group +//! @{ +//! \addtogroup systick_api +//! @{ +// +//***************************************************************************** + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// API Functions and Prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the SysTick counter. +//! +//! This will start the SysTick counter. If an interrupt handler has been +//! registered, it will be called when the SysTick counter rolls over. +//! +//! \note Calling this function will cause the SysTick counter to (re)commence +//! counting from its current value. The counter is not automatically reloaded +//! with the period as specified in a previous call to \ref SysTickPeriodSet(). +//! If an immediate reload is required, the NVIC_ST_CURRENT register must be +//! written to force this. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the supplied period on the next +//! clock. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickEnable(void) +{ + // Enable SysTick. + HWREG(NVIC_ST_CTRL) |= (NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! \brief Disables the SysTick counter. +//! +//! This will stop the SysTick counter. If an interrupt handler has been +//! registered, it will no longer be called until SysTick is restarted. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickDisable(void) +{ + // Disable SysTick. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! SysTick interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler, returning an error if an error occurs. + IntRegister(INT_SYSTICK, pfnHandler); + + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. +//! +//! This function will clear the handler to be called when a SysTick interrupt +//! occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntUnregister(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + + // Unregister the interrupt handler. + IntUnregister(INT_SYSTICK); +} + +//***************************************************************************** +// +//! \brief Enables the SysTick interrupt. +//! +//! This function will enable the SysTick interrupt, allowing it to be +//! reflected to the processor. +//! +//! \note The SysTick interrupt handler does not need to clear the SysTick +//! interrupt source as this is done automatically when the interrupt handler +//! is called. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntEnable(void) +{ + // Enable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; +} + +//***************************************************************************** +// +//! \brief Disables the SysTick interrupt. +//! +//! This function will disable the SysTick interrupt, preventing it from being +//! reflected to the processor. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickIntDisable(void) +{ + // Disable the SysTick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); +} + +//***************************************************************************** +// +//! \brief Sets the period of the SysTick counter. +//! +//! This function sets the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \note Calling this function does not cause the SysTick counter to reload + +//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT +//! register must be written. Any write to this register clears the SysTick +//! counter to 0 and will cause a reload with the \c ui32Period supplied here +//! on the next clock after the SysTick is enabled. +//! +//! \param ui32Period is the number of clock ticks in each period of the +//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +SysTickPeriodSet(uint32_t ui32Period) +{ + // Check the arguments. + ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); + + // Set the period of the SysTick counter. + HWREG(NVIC_ST_RELOAD) = ui32Period - 1; +} + +//***************************************************************************** +// +//! \brief Gets the period of the SysTick counter. +//! +//! This function returns the rate at which the SysTick counter wraps; this +//! equals to the number of processor clocks between interrupts. +//! +//! \return Returns the period of the SysTick counter. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickPeriodGet(void) +{ + // Return the period of the SysTick counter. + return(HWREG(NVIC_ST_RELOAD) + 1); +} + +//***************************************************************************** +// +//! \brief Gets the current value of the SysTick counter. +//! +//! This function returns the current value of the SysTick counter; this will +//! be a value between the (period - 1) and zero, both included. +//! +//! \return Returns the current value of the SysTick counter +// +//***************************************************************************** +__STATIC_INLINE uint32_t +SysTickValueGet(void) +{ + // Return the current value of the SysTick counter. + return(HWREG(NVIC_ST_CURRENT)); +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +//***************************************************************************** +// +//! Close the Doxygen group +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick_doc.h new file mode 100644 index 00000000..412de6c6 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/systick_doc.h @@ -0,0 +1,66 @@ +/****************************************************************************** +* Filename: systick_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup systick_api +//! @{ +//! \section sec_systick Introduction +//! +//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, +//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. +//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on +//! the next clock edge, then decrements on subsequent clocks. +//! +//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the +//! SysTick counter stops. +//! +//! When the processor is halted for debugging, the counter does not decrement. +//! +//! \section sec_systick_api API +//! +//! The API functions can be grouped like this: +//! +//! Configuration and status: +//! - \ref SysTickPeriodSet() +//! - \ref SysTickPeriodGet() +//! - \ref SysTickValueGet() +//! +//! Enable and disable: +//! - \ref SysTickEnable() +//! - \ref SysTickDisable() +//! +//! Interrupt configuration: +//! - \ref SysTickIntRegister() +//! - \ref SysTickIntUnregister() +//! - \ref SysTickIntEnable() +//! - \ref SysTickIntDisable() +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.c new file mode 100644 index 00000000..2a80988e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.c @@ -0,0 +1,390 @@ +/****************************************************************************** +* Filename: timer.c +* +* Description: Driver for the General Purpose Timer +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "timer.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TimerConfigure + #define TimerConfigure NOROM_TimerConfigure + #undef TimerLevelControl + #define TimerLevelControl NOROM_TimerLevelControl + #undef TimerStallControl + #define TimerStallControl NOROM_TimerStallControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #undef TimerIntRegister + #define TimerIntRegister NOROM_TimerIntRegister + #undef TimerIntUnregister + #define TimerIntUnregister NOROM_TimerIntUnregister + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +//! \brief Gets the timer interrupt number. +//! +//! Given a timer base address, this function returns the corresponding +//! interrupt number. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. +// +//***************************************************************************** +static uint32_t +TimerIntNumberGet(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // Loop through the table that maps timer base addresses to interrupt + // numbers. + switch(ui32Base) + { + case GPT0_BASE : + ui32Int = INT_GPT0A; + break; + case GPT1_BASE : + ui32Int = INT_GPT1A; + break; + case GPT2_BASE : + ui32Int = INT_GPT2A; + break; + case GPT3_BASE : + ui32Int = INT_GPT3A; + break; + default : + ui32Int = 0x0; + } + + // Return the interrupt number or (-1) if not base address is not matched. + return (ui32Int); +} + +//***************************************************************************** +// +// Configures the timer(s) +// +//***************************************************************************** +void +TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +//***************************************************************************** +// +// Controls the output level +// +//***************************************************************************** +void +TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the stall handling +// +//***************************************************************************** +void +TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +//***************************************************************************** +// +// Controls the wait on trigger handling +// +//***************************************************************************** +void +TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +//***************************************************************************** +// +// Registers an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Register an interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Register the interrupt handler. + IntRegister(ui32Int, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int); + } + + // Register an interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Register the interrupt handler. + IntRegister(ui32Int + 1, pfnHandler); + + // Enable the interrupt. + IntEnable(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for the timer interrupt +// +//***************************************************************************** +void +TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) +{ + uint32_t ui32Int; + + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Get the interrupt number for this timer module. + ui32Int = TimerIntNumberGet(ui32Base); + + // Unregister the interrupt handler for timer A if requested. + if(ui32Timer & TIMER_A) + { + // Disable the interrupt. + IntDisable(ui32Int); + + // Unregister the interrupt handler. + IntUnregister(ui32Int); + } + + // Unregister the interrupt handler for timer B if requested. + if(ui32Timer & TIMER_B) + { + // Disable the interrupt. + IntDisable(ui32Int + 1); + + // Unregister the interrupt handler. + IntUnregister(ui32Int + 1); + } +} + +//***************************************************************************** +// +// Sets the Match Register Update mode +// +//***************************************************************************** +void +TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +//***************************************************************************** +// +// Sets the Interval Load mode +// +//***************************************************************************** +void +TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.h new file mode 100644 index 00000000..78fd456b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer.h @@ -0,0 +1,1174 @@ +/****************************************************************************** +* Filename: timer.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//**************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup timer_api +//! @{ +// +//**************************************************************************** + +#ifndef __GPT_H__ +#define __GPT_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_ints.h" +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_gpt.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TimerConfigure NOROM_TimerConfigure + #define TimerLevelControl NOROM_TimerLevelControl + #define TimerStallControl NOROM_TimerStallControl + #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl + #define TimerIntRegister NOROM_TimerIntRegister + #define TimerIntUnregister NOROM_TimerIntUnregister + #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode + #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both + +//***************************************************************************** +// +// Values that can be passed to GPTSynchronize as the ui32Timers parameter +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B + +//***************************************************************************** +// +// Values that can be passed to TimerMatchUpdateMode +// +//***************************************************************************** +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout + +//***************************************************************************** +// +// Values that can be passed to TimerIntervalLoad +// +//***************************************************************************** +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a timer base address. +//! +//! This function determines if a timer module base address is valid. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +TimerBaseValid(uint32_t ui32Base) +{ + return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || + (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the timer(s). +//! +//! This function enables operation of the timer module. The timer must be +//! configured before it is enabled. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to enable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Enable the timer(s) module. + HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); +} + +//***************************************************************************** +// +//! \brief Disables the timer(s). +//! +//! This function disables operation of the timer module. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to disable. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Disable the timer module. + HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & + (GPT_CTL_TAEN | GPT_CTL_TBEN)); +} + +//***************************************************************************** +// +//! \brief Configures the timer(s). +//! +//! This function configures the operating mode of the timer(s). The timer +//! module is disabled before being configured and is left in the disabled +//! state. +//! +//! The timers are comprised of two 16-bit timers that can +//! operate independently or be concatenated to form a 32-bit timer. +//! +//! \note If the timers are used independently the length of timer can be +//! extended to 24 bit by use of an 8 bit prescale register set using +//! \ref TimerPrescaleSet(). +//! +//! When configuring for full-width timer \c ui32Config is set +//! as one of the following values: +//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. +//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. +//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up +//! instead of down. +//! +//! When configuring for a pair of half-width timers, each timer is separately +//! configured. The timers are configured by setting \c ui32Config to +//! the bitwise OR of one of each of the following three: +//! - Use half-width timers: +//! - \ref TIMER_CFG_SPLIT_PAIR +//! - Timer A: +//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer +//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer +//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture +//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts +//! up instead of down. +//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture +//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up +//! instead of down. +//! - \ref TIMER_CFG_A_PWM : Half-width PWM output +//! - Timer B: +//! - Same as Timer A but using TIMER_CFG_B_* instead. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Config is the configuration for the timer. +//! +//! \return None +// +//***************************************************************************** +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Controls the output level. +//! +//! This function configures the PWM output level for the specified timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bInvert specifies the output level. +//! - \c true : Timer's output is active low. +//! - \c false : Timer's output is active high. +//! +//! \return None +// +//***************************************************************************** +extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); + +//***************************************************************************** +// +//! \brief Controls the event type. +//! +//! This function configures the signal edge(s) that triggers the timer when +//! in capture mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Event specifies the type of event; must be one of: +//! - \ref TIMER_EVENT_POS_EDGE +//! - \ref TIMER_EVENT_NEG_EDGE +//! - \ref TIMER_EVENT_BOTH_EDGES +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the event type. + ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; + HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | + (ui32Event & ui32Timer)); +} + +//***************************************************************************** +// +//! \brief Controls the stall handling. +//! +//! This function controls the stall response for the specified timer. If the +//! \e bStall parameter is \b true, then the timer stops counting if the +//! processor enters debug mode; otherwise the timer keeps running while in +//! debug mode. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bStall specifies the response to a stall signal. +//! - \c true : Timer stops counting if the processor enters debug mode. +//! - \c false : Timer keeps running if the processor enters debug mode. +//! +//! \return None +// +//***************************************************************************** +extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); + +//***************************************************************************** +// +//! \brief Controls the wait on trigger handling. +//! +//! This function controls whether or not a timer waits for a trigger input to +//! start counting. When enabled, the previous timer in the trigger chain must +//! count to its timeout in order for this timer to start counting. Refer to +//! the part's data sheet for a description of the trigger chain. +//! +//! \note This function should not be used for Timer 0A or Wide Timer 0A. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param bWait specifies if the timer should wait for a trigger input. +//! - \c true : Wait for trigger. +//! - \c false : Do not wait for trigger. +//! +//! \return None +// +//***************************************************************************** +extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); + +//***************************************************************************** +// +//! \brief Set the timer prescale value. +//! +//! This function configures the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale value which must be between 0 and 255 +//! (both included). +//! - 0 : Timer division ratio = 1 (disable prescaling). +//! - 1 : Timer division ratio = 2. +//! - ... +//! - 255 : Timer division ratio = 256. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescaler if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPR) = ui32Value; + } + + // Set the timer B prescaler if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale value. +//! +//! This function gets the value of the timer clock prescaler. The +//! prescaler is only operational when in half-width mode and is used to extend +//! the range of the half-width timer modes. +//! +//! When in one-shot or periodic down count modes, \b ui32Value defines the +//! prescaler for the timer counter. When acting as a true prescaler, the +//! prescaler counts down to 0 before the value in timer registers are incremented. +//! +//! In all other individual/split modes, \b ui32Value is a linear extension of +//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes +//! of the 16/32-bit timer. +//! +//! \note Because the prescaler counts down to 0 the timer division ratio equals +//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescaler. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Return the appropriate prescale value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : + HWREG(ui32Base + GPT_O_TBPR)); +} + +//***************************************************************************** +// +//! \brief Set the timer prescale match value. +//! +//! This function configures the value of the input clock prescaler match +//! value. When in a half-width mode that uses the counter match and the +//! prescaler, the prescale match effectively extends the range of the match. +//! The prescaler provides the least significant bits when counting down in +//! periodic and one-shot modes; in all other modes, the prescaler provides the +//! most significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the timer prescale match value which must be between 0 +//! and 255 (both included). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + ASSERT(ui32Value < 256); + + // Set the timer A prescale match if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; + } + + // Set the timer B prescale match if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Get the timer prescale match value. +//! +//! This function gets the value of the input clock prescaler match value. +//! When in a half-width mode that uses the counter match and prescaler, the +//! prescale match effectively extends the range of the match. The prescaler +//! provides the least significant bits when counting down in periodic and +//! one-shot modes; in all other modes, the prescaler provides the most +//! significant bits. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the value of the timer prescale match. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate prescale match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : + HWREG(ui32Base + GPT_O_TBPMR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer load value. +//! +//! This function configures the timer load value; if the timer is running then +//! the value is immediately loaded into the timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the load value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A load value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAILR) = ui32Value; + } + + // Set the timer B load value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBILR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer load value. +//! +//! This function gets the currently programmed interval load value for the +//! specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the load value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate load value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : + HWREG(ui32Base + GPT_O_TBILR)); +} + +//***************************************************************************** +// +//! \brief Gets the current timer value. +//! +//! This function reads the current value of the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! +//! \return Returns the current value of the timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate timer value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : + HWREG(ui32Base + GPT_O_TBR)); +} + +//***************************************************************************** +// +//! \brief Sets the timer match value. +//! +//! This function configures the match value for a timer. This value is used +//! in capture count mode to determine when to interrupt the processor and in +//! PWM mode to determine the duty cycle of the output signal. Match interrupts +//! can also be generated in periodic and one-shot modes when the value of the +//! counter matches this register. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to adjust; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Value is the match value. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the timer A match value if requested. + if(ui32Timer & TIMER_A) + { + HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; + } + + // Set the timer B match value if requested. + if(ui32Timer & TIMER_B) + { + HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; + } +} + +//***************************************************************************** +// +//! \brief Gets the timer match value. +//! +//! This function gets the match value for the specified timer. +//! +//! \note This function can be used for both full- and half-width modes of +//! 16/32-bit timers. +//! +//! \note Only \ref TIMER_A should be used when the timer is configured for +//! full-width operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return Returns the match value for the timer +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); + + // Return the appropriate match value. + return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : + HWREG(ui32Base + GPT_O_TBMATCHR)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref TimerIntClear(). +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param pfnHandler is a pointer to the function to be called when the timer +//! interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. +//! +//! This function unregisters the handler to be called when a timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler is no longer called. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s); must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); + +//***************************************************************************** +// +//! \brief Enables individual timer interrupt sources. +//! +//! This function enables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual timer interrupt sources. +//! +//! This function disables the indicated timer interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the timer module. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the timer module. +//! \param bMasked selects either raw or masked interrupt status: +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return The current interrupt status, enumerated as a bit field of values: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TimerIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : + HWREG(ui32Base + GPT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears timer interrupt sources. +//! +//! The specified timer interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter must be the bitwise OR of any combination of +//! the following: +//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. +//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. +//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. +//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. +//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. +//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the requested interrupt sources. + HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Synchronizes the counters in a set of timers. +//! +//! This function synchronizes the counters in a specified set of timers. +//! When a timer is running in half-width mode, each half can be included or +//! excluded in the synchronization event. When a timer is running in +//! full-width mode, only the A timer can be synchronized (specifying the B +//! timer has no effect). +//! +//! \param ui32Base is the base address of the timer module. This parameter must +//! be the base address of Timer0 (in other words, \b GPT0_BASE). +//! \param ui32Timers is the set of timers to synchronize. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TIMER_0A_SYNC +//! - \ref TIMER_0B_SYNC +//! - \ref TIMER_1A_SYNC +//! - \ref TIMER_1B_SYNC +//! - \ref TIMER_2A_SYNC +//! - \ref TIMER_2B_SYNC +//! - \ref TIMER_3A_SYNC +//! - \ref TIMER_3B_SYNC +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) +{ + // Check the arguments. + ASSERT(ui32Base == GPT0_BASE); + + // Synchronize the specified timers. + HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; +} + +//***************************************************************************** +// +//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineEnable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Set the bit + HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; +} + +//***************************************************************************** +// +//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. +//! +//! \param ui32Base is the base address of the timer module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TimerCcpCombineDisable(uint32_t ui32Base) +{ + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + + // Clear the bit + HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); +} + +//***************************************************************************** +// +//! \brief Sets the Match Register Update mode. +//! +//! This function controls when the Match Register value and Prescale Register value +//! are applied after writing these registers while a timer is enabled. +//! +//! \note If the timer is disabled when setting the update mode the Match Register +//! and Prescale Register values are applied immediately when enabling the timer. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock +//! cycle after writing any of these registers. +//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout +//! after writing any of these registers. +//! +//! \return None +// +//***************************************************************************** +extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Sets the Interval Load mode. +//! +//! This function controls when the Timer Register and Prescale Snap-shot (if used) +//! are updated. +//! +//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written +//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is +//! written depending on the mode of operation. +//! +//! \param ui32Base is the base address of the timer module. +//! \param ui32Timer specifies the timer(s) to configure; must be one of: +//! - \ref TIMER_A +//! - \ref TIMER_B +//! - \ref TIMER_BOTH +//! \param ui32Mode sets the mode: +//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock +//! cycle after writing Interval Load Register or Prescale Register, respectively. +//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout +//! after writing Interval Load Register or Prescale Register, respectively. +//! +//! \return None +// +//***************************************************************************** +extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TimerConfigure + #undef TimerConfigure + #define TimerConfigure ROM_TimerConfigure + #endif + #ifdef ROM_TimerLevelControl + #undef TimerLevelControl + #define TimerLevelControl ROM_TimerLevelControl + #endif + #ifdef ROM_TimerStallControl + #undef TimerStallControl + #define TimerStallControl ROM_TimerStallControl + #endif + #ifdef ROM_TimerWaitOnTriggerControl + #undef TimerWaitOnTriggerControl + #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl + #endif + #ifdef ROM_TimerIntRegister + #undef TimerIntRegister + #define TimerIntRegister ROM_TimerIntRegister + #endif + #ifdef ROM_TimerIntUnregister + #undef TimerIntUnregister + #define TimerIntUnregister ROM_TimerIntUnregister + #endif + #ifdef ROM_TimerMatchUpdateMode + #undef TimerMatchUpdateMode + #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode + #endif + #ifdef ROM_TimerIntervalLoadMode + #undef TimerIntervalLoadMode + #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __GPT_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer_doc.h new file mode 100644 index 00000000..63af787f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/timer_doc.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* Filename: timer_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup timer_api +//! @{ +//! \section sec_timer Introduction +//! +//! The timer API provides a set of functions for using the general-purpose timer module. +//! +//! The timer module contains four timer blocks with the following functional options: +//! - Operating modes: +//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. +//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. +//! - Two capture compare PWM pins (CCP) for each 32-bit timer. +//! - 24-bit input-edge count or 24-bit time-capture modes. +//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. +//! - Count up or down. +//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. +//! - Timer synchronization allows selected timers to start counting on the same clock cycle. +//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. +//! - Ability to determine the elapsed time between the assertion of the timer interrupt and +//! entry into the interrupt service routine. +//! +//! Each timer block provides two half-width timers/counters that can be configured +//! to operate independently as timers or event counters or to operate as a combined +//! full-width timer. +//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. +//! For the purposes of this API, the two +//! half-width timers provided by a timer block are referred to as TimerA and +//! TimerB, and the full-width timer is referred to as TimerA. +//! +//! When in half-width mode, the timer can also be configured for event capture or +//! as a pulse width modulation (PWM) generator. When configured for event +//! capture, the timer acts as a counter. It can be configured to count either the +//! time between events or the events themselves. The type of event +//! being counted can be configured as a positive edge, a negative edge, or both +//! edges. When a timer is configured as a PWM generator, the input signal used to +//! capture events becomes an output signal, and the timer drives an +//! edge-aligned pulse onto that signal. +//! +//! Control is also provided over interrupt sources and events. Interrupts can be +//! generated to indicate that an event has been captured, or that a certain number +//! of events have been captured. Interrupts can also be generated when the timer +//! has counted down to 0 or when the timer matches a certain value. +//! +//! Timer configuration is handled by \ref TimerConfigure(), which performs the high +//! level setup of the timer module; that is, it is used to set up full- or +//! half-width modes, and to select between PWM, capture, and timer operations. +//! +//! \section sec_timer_api API +//! +//! The API functions can be grouped like this: +//! +//! Functions to perform timer control: +//! - \ref TimerConfigure() +//! - \ref TimerEnable() +//! - \ref TimerDisable() +//! - \ref TimerLevelControl() +//! - \ref TimerWaitOnTriggerControl() +//! - \ref TimerEventControl() +//! - \ref TimerStallControl() +//! - \ref TimerIntervalLoadMode() +//! - \ref TimerMatchUpdateMode() +//! - \ref TimerCcpCombineDisable() +//! - \ref TimerCcpCombineEnable() +//! +//! Functions to manage timer content: +//! - \ref TimerLoadSet() +//! - \ref TimerLoadGet() +//! - \ref TimerPrescaleSet() +//! - \ref TimerPrescaleGet() +//! - \ref TimerMatchSet() +//! - \ref TimerMatchGet() +//! - \ref TimerPrescaleMatchSet() +//! - \ref TimerPrescaleMatchGet() +//! - \ref TimerValueGet() +//! - \ref TimerSynchronize() +//! +//! Functions to manage the interrupt handler for the timer interrupt: +//! - \ref TimerIntRegister() +//! - \ref TimerIntUnregister() +//! +//! The individual interrupt sources within the timer module are managed with: +//! - \ref TimerIntEnable() +//! - \ref TimerIntDisable() +//! - \ref TimerIntStatus() +//! - \ref TimerIntClear() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.c new file mode 100644 index 00000000..28a3bce7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* Filename: trng.c +* +* Description: Driver for the TRNG module +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "trng.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef TRNGConfigure + #define TRNGConfigure NOROM_TRNGConfigure + #undef TRNGNumberGet + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// Configure the true random number generator +// +//***************************************************************************** +void +TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample) +{ + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +//***************************************************************************** +// +// Get a random number from the generator +// +//***************************************************************************** +uint32_t +TRNGNumberGet(uint32_t ui32Word) +{ + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.h new file mode 100644 index 00000000..b5c6ade6 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/trng.h @@ -0,0 +1,449 @@ +/****************************************************************************** +* Filename: trng.h +* +* Description: Defines and prototypes for the true random number gen. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup trng_api +//! @{ +// +//***************************************************************************** + +#ifndef __TRNG_H__ +#define __TRNG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "debug.h" +#include "interrupt.h" +#include "cpu.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define TRNGConfigure NOROM_TRNGConfigure + #define TRNGNumberGet NOROM_TRNGNumberGet +#endif + +//***************************************************************************** +// +// +// +//***************************************************************************** +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // + +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 + +//***************************************************************************** +// +// API Function and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Configure the true random number generator. +//! +//! Use this function to set the minimum and maximum number of samples required +//! in each generation of a new random number. +//! +//! \param ui32MinSamplesPerCycle is the minimum number of samples per each +//! generated random number. Constraints: +//! - Value must be bigger than or equal to 2^6 and less than 2^14. +//! - The 6 LSBs of the argument are truncated. +//! - If the value is zero, the number of samples is fixed to the value determined +//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random +//! numbers the value 0 should be used. +//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each +//! generated random number. Constraints: +//! - Value must be between 2^8 and 2^24 (both included). +//! - The 8 LSBs of the argument are truncated. +//! - Value 0 and 2^24 both give the highest possible value. +//! \param ui32ClocksPerSample is the number of clock cycles for each time +//! a new sample is generated from the FROs. +//! - 0 : Every sample. +//! - 1 : Every second sample. +//! - ... +//! - 15 : Every 16. sample. +//! +//! \return None +// +//***************************************************************************** +extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, + uint32_t ui32MaxSamplesPerCycle, + uint32_t ui32ClocksPerSample); + +//***************************************************************************** +// +//! \brief Enable the TRNG. +//! +//! Enable the TRNG to start preparing a random number. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGEnable(void) +{ + // Enable the TRNG. + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disable the TRNG module. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGDisable(void) +{ + // Enable the TRNG + HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Get a random number from the generator. +//! +//! Use this function to get either the high or low part of the 64 bit +//! generated number. +//! +//! \note Data from this register is only valid if the TRNG has produced a +//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this +//! function a new random number will be generated. +//! +//! \param ui32Word determines if whether to return the high or low 32 bits. +//! - \ref TRNG_HI_WORD +//! - \ref TRNG_LOW_WORD +//! +//! \return Return either the high or low part of the 64 bit generated random +//! number. +// +//***************************************************************************** +extern uint32_t TRNGNumberGet(uint32_t ui32Word); + +//***************************************************************************** +// +//! \brief Get the status of the TRNG. +//! +//! Use this function to retrieve the status of the TRNG. +//! +//! \return Returns the current status of the TRNG module. +//! The returned status is a bitwise OR'ed combination of: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! - \ref TRNG_NEED_CLOCK +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGStatusGet(void) +{ + // Return the status. + return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); +} + +//***************************************************************************** +// +//! \brief Reset the TRNG. +//! +//! Use this function to reset the TRNG module. Reset will be low for +//! approximately 5 clock cycles. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGReset(void) +{ + // Reset the TRNG. + HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; +} + +//***************************************************************************** +// +//! \brief Enables individual TRNG interrupt sources. +//! +//! This function enables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntEnable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Enable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual TRNG interrupt sources. +//! +//! This function disables the indicated TRNG interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntDisable(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Disable the specified interrupts. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status of the TRNG module. +//! +//! This function returns the interrupt status for the specified TRNG. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param bMasked selects either raw or masked interrupt status. +//! - \c true : Masked interrupt. +//! - \c false : Raw interrupt. +//! +//! \return Returns the current interrupt status, enumerated as: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +TRNGIntStatus(bool bMasked) +{ + uint32_t ui32Mask; + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); + return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); + } + else + { + return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); + } +} + +//***************************************************************************** +// +//! \brief Clears TRNG interrupt sources. +//! +//! The specified TRNG interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! The parameter is the bitwise OR of any of the following: +//! - \ref TRNG_NUMBER_READY +//! - \ref TRNG_FRO_SHUTDOWN +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntClear(uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || + (ui32IntFlags & TRNG_FRO_SHUTDOWN)); + + // Clear the requested interrupt sources. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt +//! handler's responsibility to clear the interrupt source. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! TRNG interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_TRNG_IRQ, pfnHandler); + + // Enable the TRNG interrupt. + IntEnable(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a Crypto interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +TRNGIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_TRNG_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_TRNG_IRQ); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_TRNGConfigure + #undef TRNGConfigure + #define TRNGConfigure ROM_TRNGConfigure + #endif + #ifdef ROM_TRNGNumberGet + #undef TRNGNumberGet + #define TRNGNumberGet ROM_TRNGNumberGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __TRNG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.c new file mode 100644 index 00000000..b857868d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.c @@ -0,0 +1,308 @@ +/****************************************************************************** +* Filename: uart.c +* +* Description: Driver for the UART. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "uart.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #undef UARTDisable + #define UARTDisable NOROM_UARTDisable + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #undef UARTCharGet + #define UARTCharGet NOROM_UARTCharGet + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #undef UARTCharPut + #define UARTCharPut NOROM_UARTCharPut + #undef UARTIntRegister + #define UARTIntRegister NOROM_UARTIntRegister + #undef UARTIntUnregister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Gets the FIFO level at which interrupts are generated +// +//***************************************************************************** +void +UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel) +{ + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +//***************************************************************************** +// +// Sets the configuration of a UART +// +//***************************************************************************** +void +UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config) +{ + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +//***************************************************************************** +// +// Gets the current configuration of a UART +// +//***************************************************************************** +void +UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config) +{ + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +// Disables transmitting and receiving +// +//***************************************************************************** +void +UARTDisable(uint32_t ui32Base) +{ + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +// Receives a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGetNonBlocking(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +//***************************************************************************** +// +// Waits for a character from the specified port +// +//***************************************************************************** +int32_t +UARTCharGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +//***************************************************************************** +// +// Sends a character to the specified port +// +//***************************************************************************** +bool +UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +//***************************************************************************** +// +// Waits to send a character from the specified port +// +//***************************************************************************** +void +UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +//***************************************************************************** +// +// Registers an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Register and enable the interrupt handler. + // (Doing the '& 0xFFFF' to catch both buffered and unbuffered offsets) + if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) + { + IntRegister(INT_UART0_COMB, pfnHandler); + IntEnable(INT_UART0_COMB); + } + else + { + IntRegister(INT_UART1_COMB, pfnHandler); + IntEnable(INT_UART1_COMB); + } +} + +//***************************************************************************** +// +// Unregisters an interrupt handler for a UART interrupt +// +//***************************************************************************** +void +UARTIntUnregister(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable and unregister the interrupt. + // (Doing the '& 0xFFFF' to catch both buffered and unbuffered offsets) + if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) + { + IntDisable(INT_UART0_COMB); + IntUnregister(INT_UART0_COMB); + } + else + { + IntDisable(INT_UART1_COMB); + IntUnregister(INT_UART1_COMB); + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.h new file mode 100644 index 00000000..e3c333f5 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart.h @@ -0,0 +1,1095 @@ +/****************************************************************************** +* Filename: uart.h +* +* Description: Defines and prototypes for the UART. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** + +#ifndef __UART_H__ +#define __UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_uart.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_ints.h" +#include "interrupt.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet + #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk + #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk + #define UARTDisable NOROM_UARTDisable + #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking + #define UARTCharGet NOROM_UARTCharGet + #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking + #define UARTCharPut NOROM_UARTCharPut + #define UARTIntRegister NOROM_UARTIntRegister + #define UARTIntUnregister NOROM_UARTIntUnregister +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_EOT ( UART_IMSC_EOTIM ) // End Of Transmission Interrupt Mask +#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask +#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask +#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask +#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask +#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask +#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask +#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask +#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values returned from the UARTBusy(). +// +//***************************************************************************** +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a UART base address. +//! +//! This function determines if a UART port base address is valid. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +UARTBaseValid(uint32_t ui32Base) +{ + return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || + ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); +} +#endif // #ifdef DRIVERLIB_DEBUG + +//***************************************************************************** +// +//! \brief Sets the type of parity. +//! +//! This function sets the type of parity to use for transmitting and expect +//! when receiving. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32Parity specifies the type of parity to use. The last two allow +//! direct control of the parity bit; it is always either one or zero based on +//! the mode. +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || + (ui32Parity == UART_CONFIG_PAR_EVEN) || + (ui32Parity == UART_CONFIG_PAR_ODD) || + (ui32Parity == UART_CONFIG_PAR_ONE) || + (ui32Parity == UART_CONFIG_PAR_ZERO)); + + // Set the parity mode. + HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & + ~(UART_LCRH_SPS | UART_LCRH_EPS | + UART_LCRH_PEN)) | ui32Parity); +} + +//***************************************************************************** +// +//! \brief Gets the type of parity currently being used. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the current parity settings, specified as one of: +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTParityModeGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current parity setting + return(HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); +} + +//***************************************************************************** +// +//! \brief Sets the FIFO level at which interrupts are generated. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || + (ui32TxLevel == UART_FIFO_TX2_8) || + (ui32TxLevel == UART_FIFO_TX4_8) || + (ui32TxLevel == UART_FIFO_TX6_8) || + (ui32TxLevel == UART_FIFO_TX7_8)); + ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || + (ui32RxLevel == UART_FIFO_RX2_8) || + (ui32RxLevel == UART_FIFO_RX4_8) || + (ui32RxLevel == UART_FIFO_RX6_8) || + (ui32RxLevel == UART_FIFO_RX7_8)); + + // Set the FIFO interrupt levels. + HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; +} + +//***************************************************************************** +// +//! \brief Gets the FIFO level at which interrupts are generated. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \param ui32Base is the base address of the UART port. +//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_TX1_8 +//! - \ref UART_FIFO_TX2_8 +//! - \ref UART_FIFO_TX4_8 +//! - \ref UART_FIFO_TX6_8 +//! - \ref UART_FIFO_TX7_8 +//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of: +//! - \ref UART_FIFO_RX1_8 +//! - \ref UART_FIFO_RX2_8 +//! - \ref UART_FIFO_RX4_8 +//! - \ref UART_FIFO_RX6_8 +//! - \ref UART_FIFO_RX7_8 +//! +//! \return None +// +//***************************************************************************** +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); + +//***************************************************************************** +// +//! \brief Sets the configuration of a UART. +//! +//! This function configures the UART for operation in the specified data +//! format. +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param ui32Baud is the desired baud rate. +//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) +//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) +//! \param ui32Config is the data format for the port. +//! The parameter is the bitwise OR of three values: +//! - Number of data bits +//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. +//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. +//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. +//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. +//! - Number of stop bits +//! - \ref UART_CONFIG_STOP_ONE : One stop bit. +//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. +//! - Parity +//! - \ref UART_CONFIG_PAR_NONE +//! - \ref UART_CONFIG_PAR_EVEN +//! - \ref UART_CONFIG_PAR_ODD +//! - \ref UART_CONFIG_PAR_ONE +//! - \ref UART_CONFIG_PAR_ZERO +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); + +//***************************************************************************** +// +//! \brief Gets the current configuration of a UART. +//! +//! The baud rate and data format for the UART is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an "official" baud rate. The data format returned in +//! \c pui32Config is enumerated the same as the \c ui32Config parameter of +//! \ref UARTConfigSetExpClk(). +//! +//! \note The peripheral clock is not necessarily the same as the processor +//! clock. The frequency of the peripheral clock is set by the system control. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32UARTClk is the rate of the clock supplied to the UART module. +//! \param pui32Baud is a pointer to storage for the baud rate. +//! \param pui32Config is a pointer to storage for the data format. +//! +//! \return None +// +//***************************************************************************** +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); + +//***************************************************************************** +// +//! \brief Enables transmitting and receiving. +//! +//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit +//! and receive FIFOs. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; + + // Enable RX, TX, and the UART. + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +//***************************************************************************** +// +//! \brief Disables transmitting and receiving. +//! +//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of +//! transmission of the current character, and flushes the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +extern void UARTDisable(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables the transmit and receive FIFOs. +//! +//! This functions enables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFOEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the FIFO. + HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; +} + +//***************************************************************************** +// +//! \brief Disables the transmit and receive FIFOs. +//! +//! This functions disables the transmit and receive FIFOs in the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTFIFODisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); +} + +//***************************************************************************** +// +//! \brief Determines if there are any characters in the receive FIFO. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the receive FIFO. +//! - \c true : There is data in the receive FIFO. +//! - \c false : There is no data in the receive FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTCharsAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of characters. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); +} + +//***************************************************************************** +// +//! \brief Determines if there is any space in the transmit FIFO. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit FIFO. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of the transmit FIFO. +//! - \c true : There is space available in the transmit FIFO. +//! - \c false : There is no space available in the transmit FIFO. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTSpaceAvail(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the availability of space. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); +} + +//***************************************************************************** +// +//! \brief Receives a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. +//! +//! \note The \ref UARTCharsAvail() function should be called before +//! attempting to call this function. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. A \c -1 is returned if there are no characters present in the +//! receive FIFO. +//! +//! \sa \ref UARTCharsAvail() +// +//***************************************************************************** +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Waits for a character from the specified port. +//! +//! This function gets a character from the receive FIFO for the specified +//! port. If there are no characters available, this function waits until a +//! character is received before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns the character read from the specified port, cast as an +//! \c int32_t. +// +//***************************************************************************** +extern int32_t UARTCharGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Sends a character to the specified port. +//! +//! This function writes the character \c ui8Data to the transmit FIFO for the +//! specified port. This function does not block, so if there is no space +//! available, then a \c false is returned, and the application must retry the +//! function later. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return Returns status of the character transmit. +//! - \c true : The character was successfully placed in the transmit FIFO. +//! - \c false : There was no space available in the transmit FIFO. Try again later. +// +//***************************************************************************** +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Waits to send a character from the specified port. +//! +//! This function sends the character \c ui8Data to the transmit FIFO for the +//! specified port. If there is no space available in the transmit FIFO, this +//! function waits until there is space available before returning. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui8Data is the character to be transmitted. +//! +//! \return None +// +//***************************************************************************** +extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); + +//***************************************************************************** +// +//! \brief Determines whether the UART transmitter is busy or not. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware. If \c false is returned, the transmit FIFO is +//! empty and all bits of the last transmitted character, including all stop +//! bits, have left the hardware shift register. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns status of UART transmitter. +//! - \c true : UART is transmitting. +//! - \c false : All transmissions are complete. +// +//***************************************************************************** +__STATIC_INLINE bool +UARTBusy(uint32_t ui32Base) +{ + // Check the argument. + ASSERT(UARTBaseValid(ui32Base)); + + // Determine if the UART is busy. + return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? + UART_BUSY : UART_IDLE); +} + +//***************************************************************************** +// +//! \brief Causes a BREAK to be sent. +//! +//! \note For proper transmission of a break +//! command, the break must be asserted for at least two complete frames. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bBreakState controls the output level. +//! - \c true : Asserts a break condition on the UART. +//! - \c false : Removes the break condition. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTBreakCtl(uint32_t ui32Base, bool bBreakState) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the break condition as requested. + HWREG(ui32Base + UART_O_LCRH) = + (bBreakState ? + (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : + (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source. +//! +//! \param ui32Base is the base address of the UART module. +//! \param pfnHandler is a pointer to the function to be called when the +//! UART interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. It +//! clears the handler to be called when a UART interrupt occurs. This +//! function also masks off the interrupt in the interrupt controller so that +//! the interrupt handler no longer is called. +//! +//! \param ui32Base is the base address of the UART module. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +extern void UARTIntUnregister(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! This function enables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Enable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! This function disables the indicated UART interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Disable the specified interrupts. + HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); +} + +//***************************************************************************** +// +//! \brief Gets the current interrupt status. +//! +//! This function returns the interrupt status for the specified UART. Either +//! the raw interrupt status or the status of interrupts that are allowed to +//! reflect to the processor can be returned. +//! +//! \param ui32Base is the base address of the UART port. +//! \param bMasked selects either raw or masked interrupt. +//! - \c true : Masked interrupt status is required. +//! - \c false : Raw interrupt status is required. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of: +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTIntStatus(uint32_t ui32Base, bool bMasked) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return either the interrupt status or the raw interrupt status as + // requested. + if(bMasked) + { + return(HWREG(ui32Base + UART_O_MIS)); + } + else + { + return(HWREG(ui32Base + UART_O_RIS)); + } +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The specified UART interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. +//! - \ref UART_INT_EOT : End Of Transmission interrupt. +//! - \ref UART_INT_OE : Overrun Error interrupt. +//! - \ref UART_INT_BE : Break Error interrupt. +//! - \ref UART_INT_PE : Parity Error interrupt. +//! - \ref UART_INT_FE : Framing Error interrupt. +//! - \ref UART_INT_RT : Receive Timeout interrupt. +//! - \ref UART_INT_TX : Transmit interrupt. +//! - \ref UART_INT_RX : Receive interrupt. +//! - \ref UART_INT_CTS : CTS interrupt. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) +{ + // Check the arguments + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested interrupt sources + HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; +} + +//***************************************************************************** +// +//! \brief Enable UART DMA operation. +//! +//! The specified UART DMA features are enabled. The UART can be +//! configured to use DMA for transmit or receive, and to disable +//! receive if an error occurs. +//! +//! \note The uDMA controller must also be set up before DMA can be used +//! with the UART. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to enable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Set the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Disable UART DMA operation. +//! +//! This function is used to disable UART DMA features that were enabled +//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. +//! +//! \param ui32Base is the base address of the UART port. +//! \param ui32DMAFlags is a bit mask of the DMA features to disable. +//! The parameter is the bitwise OR of any of the following values: +//! - UART_DMA_RX : Enable DMA for receive. +//! - UART_DMA_TX : Enable DMA for transmit. +//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Clear the requested bits in the UART DMA control register. + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; +} + +//***************************************************************************** +// +//! \brief Gets current receiver errors. +//! +//! This function returns the current state of each of the 4 receiver error +//! sources. The returned errors are equivalent to the four error bits +//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() +//! with the exception that the overrun error is set immediately the overrun +//! occurs rather than when a character is next read. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return Returns a bitwise OR combination of the receiver error flags: +//! - \ref UART_RXERROR_FRAMING +//! - \ref UART_RXERROR_PARITY +//! - \ref UART_RXERROR_BREAK +//! - \ref UART_RXERROR_OVERRUN +// +//***************************************************************************** +__STATIC_INLINE uint32_t +UARTRxErrorGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Return the current value of the receive status register. + return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); +} + +//***************************************************************************** +// +//! \brief Clears all reported receiver errors. +//! +//! This function is used to clear all receiver error conditions reported via +//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or +//! break interrupts, this function must be called after clearing the interrupt +//! to ensure that later errors of the same type trigger another interrupt. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTRxErrorClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Any write to the Error Clear Register will clear all bits which are + // currently set. + HWREG(ui32Base + UART_O_ECR) = 0; +} + +//***************************************************************************** +// +//! \brief Enables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlEnable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + +//***************************************************************************** +// +//! \brief Disables hardware flow control for both CTS and RTS +//! +//! Hardware flow control is disabled by default. +//! +//! \param ui32Base is the base address of the UART port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +UARTHwFlowControlDisable( uint32_t ui32Base ) +{ + // Check the arguments. + ASSERT( UARTBaseValid( ui32Base )); + + HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); +} + + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_UARTFIFOLevelGet + #undef UARTFIFOLevelGet + #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet + #endif + #ifdef ROM_UARTConfigSetExpClk + #undef UARTConfigSetExpClk + #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk + #endif + #ifdef ROM_UARTConfigGetExpClk + #undef UARTConfigGetExpClk + #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk + #endif + #ifdef ROM_UARTDisable + #undef UARTDisable + #define UARTDisable ROM_UARTDisable + #endif + #ifdef ROM_UARTCharGetNonBlocking + #undef UARTCharGetNonBlocking + #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking + #endif + #ifdef ROM_UARTCharGet + #undef UARTCharGet + #define UARTCharGet ROM_UARTCharGet + #endif + #ifdef ROM_UARTCharPutNonBlocking + #undef UARTCharPutNonBlocking + #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking + #endif + #ifdef ROM_UARTCharPut + #undef UARTCharPut + #define UARTCharPut ROM_UARTCharPut + #endif + #ifdef ROM_UARTIntRegister + #undef UARTIntRegister + #define UARTIntRegister ROM_UARTIntRegister + #endif + #ifdef ROM_UARTIntUnregister + #undef UARTIntUnregister + #define UARTIntUnregister ROM_UARTIntUnregister + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart_doc.h new file mode 100644 index 00000000..510b044e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/uart_doc.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* Filename: uart_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +/*! +\addtogroup uart_api +@{ + +\section sec_uart_printf Use printf() + +DriverLib only supports writing a single character at a time to the UART buffer but it is +possible to utilize the library function \c printf by overriding a few of the functions used by +\c printf with a device specific definition. However, the implementation of \c printf is +compiler specific and requires different functions to be overridden depending on the compiler. + +Using \c printf can increase code size significantly but some compilers provide a highly optimized +and configurable implementation suitable for embedded systems which makes the code size increase +acceptable for most applications. See the compiler's documentation for details about how to +configure the \c printf library function. + +It is required that the application configures and enables the UART module before using \c printf +function. + +\subsection sec_uart_printf_ccs Code Composer Studio + +In Code Composer Studio the functions \c fputc and \c fputs must be overridden. + +\code{.c} +#include +#include + +#define PRINTF_UART UART0_BASE + +// Override 'fputc' function in order to use printf() to output to UART +int fputc(int _c, register FILE *_fp) +{ + UARTCharPut(PRINTF_UART, (uint8_t)_c); + return _c; +} + +// Override 'fputs' function in order to use printf() to output to UART +int fputs(const char *_ptr, register FILE *_fp) +{ + unsigned int i, len; + + len = strlen(_ptr); + + for(i=0 ; i +#include + +#define PRINTF_UART UART0_BASE + +// Override 'putchar' function in order to use printf() to output to UART. +int putchar(int data) +{ + UARTCharPut(PRINTF_UART, (uint8_t)data); + return data; +} +\endcode + +@} +*/ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.c new file mode 100644 index 00000000..95c1ea2d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.c @@ -0,0 +1,446 @@ +/****************************************************************************** +* Filename: udma.c +* +* Description: Driver for the uDMA controller +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "udma.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +// Enables attributes of a uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Disables attributes of an uDMA channel +// +//***************************************************************************** +void +uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32Attr) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +//***************************************************************************** +// +// Gets the enabled attributes of a uDMA channel +// +//***************************************************************************** +uint32_t +uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +//***************************************************************************** +// +// Sets the control parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Control) +{ + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +//***************************************************************************** +// +// Sets the transfer parameters for a uDMA channel control structure +// +//***************************************************************************** +void +uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, + uint32_t ui32TransferSize) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +//***************************************************************************** +// +// Configures a uDMA channel for scatter-gather mode +// +//***************************************************************************** +void +uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, void *pvTaskList, + uint32_t ui32IsPeriphSG) +{ + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +//***************************************************************************** +// +// Gets the current transfer size for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +//***************************************************************************** +// +// Gets the transfer mode for a uDMA channel control structure +// +//***************************************************************************** +uint32_t +uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) +{ + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.h new file mode 100644 index 00000000..63b627d5 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/udma.h @@ -0,0 +1,1240 @@ +/****************************************************************************** +* Filename: udma.h +* +* Description: Defines and prototypes for the uDMA controller. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup udma_api +//! @{ +// +//***************************************************************************** + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_udma.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable + #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable + #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet + #define uDMAChannelControlSet NOROM_uDMAChannelControlSet + #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet + #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet + #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet + #define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#endif + +//***************************************************************************** +// +//! \brief A structure that defines an entry in the channel control table. +//! +//! These fields are used by the uDMA controller and normally it is not necessary for +//! software to directly read or write fields in the table. +// +//***************************************************************************** +typedef struct +{ + volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} +tDMAControlTable; + +//***************************************************************************** +// +//! \brief A helper macro for building scatter-gather task table entries. +//! +//! This macro is intended to be used to help populate a table of uDMA tasks +//! for a scatter-gather transfer. This macro will calculate the values for +//! the fields of a task structure entry based on the input parameters. +//! +//! There are specific requirements for the values of each parameter. No +//! checking is done so it is up to the caller to ensure that correct values +//! are used for the parameters. +//! +//! This macro is intended to be used to initialize individual entries of +//! a structure of tDMAControlTable type, like this: +//! +/*! +\verbatim + tDMAControlTable MyTaskList[] = + { + uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, + UDMA_SRC_INC_8, MySourceBuf, + UDMA_DST_INC_8, MyDestBuf, + UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), + uDMATaskStructEntry(Task2Count, ... ), + } +\endverbatim +*/ +//! \param ui32TransferCount is the count of items to transfer for this task. +//! It must be in the range 1-1024. +//! \param ui32ItemSize is the bit size of the items to transfer for this task. +//! It must be one of: +//! - \ref UDMA_SIZE_8 +//! - \ref UDMA_SIZE_16 +//! - \ref UDMA_SIZE_32 +//! \param ui32SrcIncrement is the bit size increment for source data. +//! It must be one of: +//! - \ref UDMA_SRC_INC_8 +//! - \ref UDMA_SRC_INC_16 +//! - \ref UDMA_SRC_INC_32 +//! - \ref UDMA_SRC_INC_NONE +//! \param pvSrcAddr is the starting address of the data to transfer. +//! \param ui32DstIncrement is the bit size increment for destination data. +//! It must be one of: +//! - \ref UDMA_DST_INC_8 +//! - \ref UDMA_DST_INC_16 +//! - \ref UDMA_DST_INC_32 +//! - \ref UDMA_DST_INC_NONE +//! \param pvDstAddr is the starting address of the destination data. +//! \param ui32ArbSize is the arbitration size to use for the transfer task. +//! This is used to select the arbitration size in powers of 2, from 1 to 1024. +//! It must be one of: +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - ... +//! - \ref UDMA_ARB_1024 +//! \param ui32Mode is the transfer mode for this task. +//! Note that normally all tasks will be one of the scatter-gather modes while the +//! last task is a task list will be AUTO or BASIC. +//! It must be one of: +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +//! +//! \return None (this is not a function) +// +//***************************************************************************** +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ + ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ + ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ + ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ + ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ + (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ + } + +//***************************************************************************** +// +// The hardware configured number of uDMA channels. +// +//***************************************************************************** +#define UDMA_NUM_CHANNELS 21 + +//***************************************************************************** +// +// The level of priority for the uDMA channels +// +//***************************************************************************** +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 + +//***************************************************************************** +// +// Flags that can be passed to uDMAChannelAttributeEnable(), +// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). +// +//***************************************************************************** +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F + +//***************************************************************************** +// +// DMA control modes that can be passed to uDMAChannelModeSet() and returned +// uDMAChannelModeGet(). +// +//***************************************************************************** +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ + 0x00000004 +#define UDMA_MODE_PER_SCATTER_GATHER \ + 0x00000006 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 + +//***************************************************************************** +// +// Channel configuration values that can be passed to uDMAControlSet(). +// +//***************************************************************************** +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 + +//***************************************************************************** +// +// Channel numbers to be passed to API functions that require a channel number +// ID. +// +//***************************************************************************** +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 TX Data +#define UDMA_CHAN_UART1_RX 5 // UART1 RX Data +#define UDMA_CHAN_UART1_TX 6 // UART1 TX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 // Timer1 A event +#define UDMA_CHAN_TIMER1_B 12 // Timer1 B event +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 // SSI1 RX Data +#define UDMA_CHAN_SSI1_TX 17 // SSI1 TX Data +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 + +//***************************************************************************** +// +// Flags to be OR'd with the channel ID to indicate if the primary or alternate +// control structure should be used. +// +//***************************************************************************** +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \internal +//! +//! \brief Checks a uDMA base address. +//! +//! This function determines if a uDMA module base address is valid. +//! +//! \param ui32Base specifies the uDMA module base address. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +uDMABaseValid(uint32_t ui32Base) +{ + return(ui32Base == UDMA0_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Enables the uDMA controller for use. +//! +//! This function enables the uDMA controller. The uDMA controller must be +//! enabled before it can be configured and used. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAEnable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Set the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; +} + +//***************************************************************************** +// +//! \brief Disables the uDMA controller for use. +//! +//! This function disables the uDMA controller. Once disabled, the uDMA +//! controller will not operate until re-enabled with \ref uDMAEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMADisable(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the master enable bit in the config register. + HWREG(ui32Base + UDMA_O_CFG) = 0; +} + +//***************************************************************************** +// +//! \brief Gets the uDMA error status. +//! +//! This function returns the uDMA error status. It should be called from +//! within the uDMA error interrupt handler to determine if a uDMA error +//! occurred. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns non-zero if a uDMA error is pending. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAErrorStatusGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA error status. + return(HWREG(ui32Base + UDMA_O_ERROR)); +} + +//***************************************************************************** +// +//! \brief Clears the uDMA error interrupt. +//! +//! This function clears a pending uDMA error interrupt. It should be called +//! from within the uDMA error interrupt handler to clear the interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAErrorStatusClear(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the uDMA error interrupt. + HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; +} + +//***************************************************************************** +// +//! \brief Enables a uDMA channel for operation. +//! +//! This function enables a specific uDMA channel for use. This function must +//! be used to enable a channel before it can be used to perform a uDMA +//! transfer. +//! +//! When a uDMA transfer is completed, the channel will be automatically +//! disabled by the uDMA controller. Therefore, this function should be called +//! prior to starting up any new transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to enable. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable set register. + HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Disables a uDMA channel for operation. +//! +//! This function disables a specific uDMA channel. Once disabled, a channel +//! will not respond to uDMA transfer requests until re-enabled via +//! \ref uDMAChannelEnable(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to disable. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the enable clear register. + HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Checks if a uDMA channel is enabled for operation. +//! +//! This function checks to see if a specific uDMA channel is enabled. This +//! can be used to check the status of a transfer, since the channel will +//! be automatically disabled at the end of a transfer. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number to check. +//! +//! \return Returns status of uDMA channel. +//! - \c true : Channel is enabled. +//! - \c false : Disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // AND the specified channel bit with the enable register, and return the + // result. + return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the base address for the channel control table. +//! +//! This function sets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. The table must be aligned on a 1024 byte boundary. The base +//! address must be set before any of the channel functions can be used. +//! Setting the base address of the primary control table will automatically +//! set the address for the alternate control table as the next memory +//! location after the primary control table. +//! +//! The size of the channel control table depends on the number of uDMA +//! channels, and which transfer modes are used. Refer to the introductory +//! text and the microcontroller datasheet for more information about the +//! channel control table. +//! +//! \note This register cannot be read when the controller is in the reset +//! state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param pControlTable is a pointer to the 1024 byte aligned base address +//! of the uDMA channel control table. The address must be an absolute address +//! in system memory space. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(((uint32_t)pControlTable & ~0x3FF) == + (uint32_t)pControlTable); + ASSERT((uint32_t)pControlTable >= SRAM_BASE); + + // Program the base address into the register. + HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table. +//! +//! This function gets the base address of the channel control table. This +//! table resides in system memory and holds control information for each uDMA +//! channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + + ASSERT(uDMABaseValid(ui32Base)); + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_CTRL)); +} + +//***************************************************************************** +// +//! \brief Gets the base address for the channel control table alternate structures. +//! +//! This function gets the base address of the second half of the channel +//! control table that holds the alternate control structures for each channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Returns a pointer to the base address of the second half of the +//! channel control table. +// +//***************************************************************************** +__STATIC_INLINE void * +uDMAControlAlternateBaseGet(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read the current value of the control base register, and return it to + // the caller. + return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); +} + +//***************************************************************************** +// +//! \brief Requests a uDMA channel to start a transfer. +//! +//! This function allows software to request a uDMA channel to begin a +//! transfer. This could be used for performing a memory to memory transfer, +//! or if for some reason a transfer needs to be initiated by software instead +//! of the peripheral associated with that channel. +//! +//! \note If the channel is a software channel and interrupts are used, then +//! the completion will be signaled on the uDMA dedicated interrupt. If a +//! peripheral channel is used, then the completion will be signaled on the +//! peripheral's interrupt. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel number on which to request a uDMA +//! transfer. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the bit for this channel in the software uDMA request register. + HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Enables attributes of a uDMA channel. +//! +//! This function is used to enable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeEnable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Disables attributes of an uDMA channel. +//! +//! This function is used to disable attributes of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! \param ui32Attr is a combination of attributes for the channel. +//! The parameter is the bitwise OR of any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelAttributeDisable(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32Attr); + +//***************************************************************************** +// +//! \brief Gets the enabled attributes of a uDMA channel. +//! +//! This function returns a combination of flags representing the attributes of +//! the uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the channel to configure. +//! +//! \return Returns the bitwise OR of the attributes of the uDMA channel, which +//! can be any of the following: +//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. +//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure +//! for this channel (it is very unlikely that this flag should be used). +//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. +//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the +//! peripheral for this channel. +// +//***************************************************************************** +extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, + uint32_t ui32ChannelNum); + +//***************************************************************************** +// +//! \brief Sets the control parameters for a uDMA channel control structure. +//! +//! This function is used to set control parameters for a uDMA transfer. These +//! are typically parameters that are not changed often. +//! +//! \note The address increment cannot be smaller than the data size. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Control is the bitwise OR of five values: +//! - Data size +//! - \ref UDMA_SIZE_8 : 8 bits. +//! - \ref UDMA_SIZE_16 : 16 bits. +//! - \ref UDMA_SIZE_32 : 32 bits. +//! - Source address increment +//! - \ref UDMA_SRC_INC_8 : 8 bits. +//! - \ref UDMA_SRC_INC_16 : 16 bits. +//! - \ref UDMA_SRC_INC_32 : 32 bits. +//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. +//! - Destination address increment +//! - \ref UDMA_DST_INC_8 : 8 bits. +//! - \ref UDMA_DST_INC_16 : 16 bits. +//! - \ref UDMA_DST_INC_32 : 32 bits. +//! - \ref UDMA_DST_INC_NONE : Non-incrementing. +//! - Arbitration size. Determines how many items are transferred before +//! the uDMA controller re-arbitrates for the bus. In power of 2. +//! - \ref UDMA_ARB_1 +//! - \ref UDMA_ARB_2 +//! - \ref UDMA_ARB_4 +//! - \ref UDMA_ARB_8 +//! - ... +//! - \ref UDMA_ARB_1024 +//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. +//! - \ref UDMA_NEXT_USEBURST +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelControlSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Control); + +//***************************************************************************** +// +//! \brief Sets the transfer parameters for a uDMA channel control structure. +//! +//! This function is used to set the parameters for a uDMA transfer. These are +//! typically parameters that are changed often. The function +//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior +//! to calling this function. +//! +//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first +//! location of the data to be transferred. These addresses should be aligned +//! according to the item size. The compiler will take care of this if the +//! pointers are pointing to storage of the appropriate data type. +//! +//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different +//! depending on whether the primary or alternate control structure is +//! selected. This function will look for the \ref UDMA_PRI_SELECT and +//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the +//! scatter/gather mode as appropriate for the primary or alternate control +//! structure. +//! +//! The channel must also be enabled using \ref uDMAChannelEnable() after calling +//! this function. The transfer will not begin until the channel has been set +//! up and enabled. Note that the channel is automatically disabled after the +//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called +//! again after setting up the next transfer. +//! +//! \note Great care must be taken to not modify a channel control structure +//! that is in use or else the results will be unpredictable, including the +//! possibility of undesired data transfers to or from memory or peripherals. +//! For BASIC and AUTO modes, it is safe to make changes when the channel is +//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For +//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the +//! primary or alternate control structure only when the other is being used. +//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a +//! channel control structure is inactive and safe to modify. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT : Use primary data structure. +//! - \ref UDMA_ALT_SELECT : Use alternate data structure. +//! \param ui32Mode is the type of uDMA transfer. +//! The parameter should be one of the following values: +//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode +//! to this value at the end of a transfer. +//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. +//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once +//! started even if request is removed. +//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the +//! primary and alternate control structures for the channel. This allows +//! use of ping-pong buffering for uDMA transfers. +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. +//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. +//! \param pvSrcAddr is the source address for the transfer. +//! \param pvDstAddr is the destination address for the transfer. +//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). +//! +//! \return None +// +//***************************************************************************** +extern void uDMAChannelTransferSet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex, + uint32_t ui32Mode, void *pvSrcAddr, + void *pvDstAddr, uint32_t ui32TransferSize); + +//***************************************************************************** +// +//! \brief Configures a uDMA channel for scatter-gather mode. +//! +//! This function is used to configure a channel for scatter-gather mode. +//! The caller must have already set up a task list, and pass a pointer to +//! the start of the task list as the \c pvTaskList parameter. +//! +//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the +//! size of the task list. +//! +//! The flag \c bIsPeriphSG should be used to indicate +//! if the scatter-gather should be configured for a peripheral or memory +//! scatter-gather operation. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is the uDMA channel number. +//! \param ui32TaskCount is the number of scatter-gather tasks to execute. +//! \param pvTaskList is a pointer to the beginning of the scatter-gather +//! task list. +//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral +//! scatter-gather transfer (else it will be memory scatter-gather transfer) +//! +//! \return None +//! +//! \sa \ref uDMATaskStructEntry() +// +//***************************************************************************** +extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, + uint32_t ui32ChannelNum, + uint32_t ui32TaskCount, + void *pvTaskList, + uint32_t ui32IsPeriphSG); + +//***************************************************************************** +// +//! \brief Gets the current transfer size for a uDMA channel control structure. +//! +//! This function is used to get the uDMA transfer size for a channel. The +//! transfer size is the number of items to transfer, where the size of an item +//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, +//! then the number of remaining items will be returned. If the transfer is +//! complete, then 0 will be returned. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the number of items remaining to transfer. +// +//***************************************************************************** +extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Gets the transfer mode for a uDMA channel control structure. +//! +//! This function is used to get the transfer mode for the uDMA channel. It +//! can be used to query the status of a transfer on a channel. When the +//! transfer is complete the mode will be \ref UDMA_MODE_STOP. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: +//! - \ref UDMA_PRI_SELECT +//! - \ref UDMA_ALT_SELECT +//! +//! \return Returns the transfer mode of the specified channel and control +//! structure, which will be one of the following values: +//! - \ref UDMA_MODE_STOP +//! - \ref UDMA_MODE_BASIC +//! - \ref UDMA_MODE_AUTO +//! - \ref UDMA_MODE_PINGPONG +//! - \ref UDMA_MODE_MEM_SCATTER_GATHER +//! - \ref UDMA_MODE_PER_SCATTER_GATHER +// +//***************************************************************************** +extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, + uint32_t ui32ChannelStructIndex); + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! \note The interrupt handler for uDMA is for transfer completion when the +//! software channel is used, and for error interrupts. The interrupts for each +//! peripheral channel are handled through the individual peripheral interrupt +//! handlers. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! \param pfnHandler is a pointer to the function to be called when the +//! interrupt is activated. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, + void (*pfnHandler)(void)) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(pfnHandler); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Register the interrupt handler. + IntRegister(ui32IntChannel, pfnHandler); + + // Enable the memory management fault. + IntEnable(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. +//! +//! This function will disable and clear the handler to be called for the +//! specified uDMA interrupt. +//! +//! \param ui32Base is the base address of the uDMA module. +//! \param ui32IntChannel specifies which uDMA interrupt to unregister. +//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts +//! from the uDMA software channel. +//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error +//! interrupts. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); + + // Disable the interrupt. + IntDisable(ui32IntChannel); + + // Unregister the interrupt handler. + IntUnregister(ui32IntChannel); +} + +//***************************************************************************** +// +//! \brief Clears uDMA interrupt done status. +//! +//! Clears bits in the uDMA interrupt status register according to which bits +//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit +//! is set in \c ui32ChanMask, then that corresponding channel's interrupt +//! status will be cleared (if it was set). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Clear the requested bits in the uDMA interrupt status register. + HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; +} + +//***************************************************************************** +// +//! \brief Get the uDMA interrupt status. +//! +//! This function returns the interrupt status for the specified UDMA. This +//! function does not differentiate between software or hardware activated +//! interrupts. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAIntStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Return the uDMA interrupt status register. + return (HWREG(ui32Base + UDMA_O_REQDONE)); +} + +//***************************************************************************** +// +//! \brief Enable interrupt on software event driven uDMA transfers. +//! +//! \note The main purpose of this function is to prevent propagation of uDMA +//! status signals to a peripheral, if a peripheral and a software event is +//! sharing the uDMA channel. If it is desired to initiate a transfer by +//! writing to a register inside the uDMA (this means a software driven +//! channel), then the uDMA status signals propagation need to be blocked to +//! the hardware peripherals. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to enable software +//! interrupts for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Enable the channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; +} + +//***************************************************************************** +// +//! \brief Disable interrupt on software event driven uDMA transfers. +//! +//! This register disables the blocking of the uDMA status signals propagation +//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32IntChannel identifies which uDMA interrupt to disable software +//! interrupts for. +//! +//! \return None +//! +//! \sa \ref uDMAIntSwEventEnable() +// +//***************************************************************************** +__STATIC_INLINE void +uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); + + // Disable the SW channel. + HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; +} + +//***************************************************************************** +// +//! \brief Return the status of the uDMA module. +//! +//! \note This status register cannot be read when the controller is in the reset state. +//! +//! \param ui32Base is the base address of the uDMA port. +//! +//! \return Current status of the uDMA module. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +uDMAGetStatus(uint32_t ui32Base) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + + // Read and return the status register. + return HWREG(ui32Base + UDMA_O_STATUS); +} + +//***************************************************************************** +// +//! \brief Set the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To reset a channel +//! priority to the default value use \ref uDMAChannelPriorityClear(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum is uDMA channel to set the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Set the channel priority to high. + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +//! \brief Get the priority of a uDMA channel. +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to get the priority for. +//! +//! \return Returns one of: +//! - \ref UDMA_PRIORITY_HIGH +//! - \ref UDMA_PRIORITY_LOW +// +//***************************************************************************** +__STATIC_INLINE bool +uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Return the channel priority. + return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? + UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); +} + +//***************************************************************************** +// +//! \brief Clear the priority of a uDMA channel. +//! +//! \note Writing 0 to a bit has no effect on the priority. To set a channel +//! priority to high use \ref uDMAChannelPrioritySet(). +//! +//! \param ui32Base is the base address of the uDMA port. +//! \param ui32ChannelNum The uDMA channel to clear the priority for. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) +{ + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Clear the channel priority. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_uDMAChannelAttributeEnable + #undef uDMAChannelAttributeEnable + #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable + #endif + #ifdef ROM_uDMAChannelAttributeDisable + #undef uDMAChannelAttributeDisable + #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable + #endif + #ifdef ROM_uDMAChannelAttributeGet + #undef uDMAChannelAttributeGet + #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet + #endif + #ifdef ROM_uDMAChannelControlSet + #undef uDMAChannelControlSet + #define uDMAChannelControlSet ROM_uDMAChannelControlSet + #endif + #ifdef ROM_uDMAChannelTransferSet + #undef uDMAChannelTransferSet + #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet + #endif + #ifdef ROM_uDMAChannelScatterGatherSet + #undef uDMAChannelScatterGatherSet + #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet + #endif + #ifdef ROM_uDMAChannelSizeGet + #undef uDMAChannelSizeGet + #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet + #endif + #ifdef ROM_uDMAChannelModeGet + #undef uDMAChannelModeGet + #define uDMAChannelModeGet ROM_uDMAChannelModeGet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UDMA_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.c new file mode 100644 index 00000000..7a358cc7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.c @@ -0,0 +1,174 @@ +/****************************************************************************** +* Filename: vims.c +* +* Description: Driver for the VIMS. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "vims.h" + +//***************************************************************************** +// +// Handle support for DriverLib in ROM: +// This section will undo prototype renaming made in the header file +// +//***************************************************************************** +#if !defined(DOXYGEN) + #undef VIMSConfigure + #define VIMSConfigure NOROM_VIMSConfigure + #undef VIMSModeSet + #define VIMSModeSet NOROM_VIMSModeSet + #undef VIMSModeGet + #define VIMSModeGet NOROM_VIMSModeGet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Configures the VIMS. +// +//***************************************************************************** +void +VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Set the operational mode of the VIMS +// +//***************************************************************************** +void +VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +//***************************************************************************** +// +// Get the current operational mode of the VIMS. +// +//***************************************************************************** +uint32_t +VIMSModeGet(uint32_t ui32Base) +{ + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +//***************************************************************************** +// +// Safe setting of new VIMS mode +// - Function might be blocking +// - Can be called for any mode change (also if actually not changing mode) +// +//***************************************************************************** +void +VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) +{ + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.h new file mode 100644 index 00000000..251684ac --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/vims.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* Filename: vims.h +* +* Description: Defines and prototypes for the VIMS. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup system_control_group +//! @{ +//! \addtogroup vims_api +//! @{ +// +//***************************************************************************** + +#ifndef __VIMS_H__ +#define __VIMS_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_vims.h" +#include "debug.h" + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// This section renames all functions that are not "static inline", so that +// calling these functions will default to implementation in flash. At the end +// of this file a second renaming will change the defaults to implementation in +// ROM for available functions. +// +// To force use of the implementation in flash, e.g. for debugging: +// - Globally: Define DRIVERLIB_NOROM at project level +// - Per function: Use prefix "NOROM_" when calling the function +// +//***************************************************************************** +#if !defined(DOXYGEN) + #define VIMSConfigure NOROM_VIMSConfigure + #define VIMSModeSet NOROM_VIMSModeSet + #define VIMSModeGet NOROM_VIMSModeGet + #define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#endif + +//***************************************************************************** +// +// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, +// and returned from VIMSModeGet(). +// +//***************************************************************************** +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE + // can not be changed at moment. +#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +#ifdef DRIVERLIB_DEBUG +//***************************************************************************** +// +//! \brief Checks a VIMS base address. +//! +//! This function determines if the VIMS base address is valid. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns \c true if the base address is valid and \c false +//! otherwise. +// +//***************************************************************************** +static bool +VIMSBaseValid(uint32_t ui32Base) +{ + return(ui32Base == VIMS_BASE); +} +#endif + +//***************************************************************************** +// +//! \brief Configures the VIMS. +//! +//! This function sets general control settings of the VIMS system. +//! +//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param bRoundRobin specifies the arbitration method. +//! - \c true : Round Robin arbitration between the two available read/write interfaces +//! (i.e. Icode/Dcode and Sysbus) is to be used. +//! - \c false : Strict arbitration will be used, where Icode/Dcode +//! is preferred over the Sysbus. +//! \param bPrefetch specifies if prefetching is to be used. +//! - \c true : Cache is to prefetch tag data for the following address. +//! - \c false : No prefetch. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, + bool bPrefetch); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS. +//! +//! This function sets the operational mode of the VIMS. +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational. +//! Reads and writes to flash will be uncached. +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in \ref VIMSModeSafeSet() +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. Once \ref VIMSModeSet() is used to set the VIMS in +//! \ref VIMS_MODE_CHANGING mode, the user should check using +//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when +//! the mode has changed the cache has been completely invalidated. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32Mode is the operational mode. +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \return None +//! +//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() +// +//***************************************************************************** +extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); + +//***************************************************************************** +// +//! \brief Get the current operational mode of the VIMS. +//! +//! This function returns the operational mode of the VIMS. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return Returns one of: +//! - \ref VIMS_MODE_CHANGING +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! +//! \sa \ref VIMSModeSet() +// +//***************************************************************************** +extern uint32_t VIMSModeGet(uint32_t ui32Base); + +//***************************************************************************** +// +//! \brief Set the operational mode of the VIMS in a safe sequence. +//! +//! This function sets the operational mode of the VIMS in a safe sequence +//! +//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. +//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will not be operational (read/write to flash will be uncached). +//! After a short delay (approx. 1029 clock cycles) the VIMS will +//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). +//! +//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is +//! accessible: +//! The GP RAM will be accessible. +//! The Cache will not be operational. +//! Reads from flash will be uncached. +//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). +//! +//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. +//! The GP RAM will not be operational (read/write will result in bus fault). +//! The Cache will be operational for SYSCODE space. +//! Reads from flash in USERCODE space will be uncached. +//! +//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. +//! +//! \note The VIMS must be invalidated when switching mode. +//! This is done by setting VIMS_MODE_OFF before setting any new mode. +//! This is automatically handled in this function. +//! +//! \note It is highly recommended that the VIMS is put in disabled mode before +//! \b writing to flash, since the cache will not be updated nor invalidated +//! by flash writes. The line buffers should also be disabled when updating the +//! flash. +//! +//! \note Access from System Bus is never cached. Only access through ICODE +//! DCODE bus from the System CPU is cached. +//! +//! \param ui32Base is the base address of the VIMS. +//! \param ui32NewMode is the new operational mode: +//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) +//! - \ref VIMS_MODE_ENABLED (CACHE mode) +//! - \ref VIMS_MODE_OFF +//! \param blocking shall be set to TRUE if further code execution shall be +//! blocked (delayed) until mode change is completed. +//! +//! \return None +//! +//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() +// +//***************************************************************************** +extern void VIMSModeSafeSet( uint32_t ui32Base , + uint32_t ui32NewMode , + bool blocking ); + +//***************************************************************************** +// +//! \brief Disable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufDisable(uint32_t ui32Base) +{ + // Disable line buffers + HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M; +} + +//***************************************************************************** +// +//! \brief Enable VIMS linebuffers. +//! +//! Linebuffers should only be disabled when attempting to update the flash, to +//! ensure that the content of the buffers is not stale. As soon as flash is +//! updated the linebuffers should be reenabled. Failing to enable +//! will have a performance impact. +//! +//! \param ui32Base is the base address of the VIMS. +//! +//! \return None. +// +//***************************************************************************** +__STATIC_INLINE void +VIMSLineBufEnable(uint32_t ui32Base) +{ + // Enable linebuffers + HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | + VIMS_CTL_SYSBUS_LB_DIS_M); +} + +//***************************************************************************** +// +// Support for DriverLib in ROM: +// Redirect to implementation in ROM when available. +// +//***************************************************************************** +#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) + #include "../driverlib/rom.h" + #ifdef ROM_VIMSConfigure + #undef VIMSConfigure + #define VIMSConfigure ROM_VIMSConfigure + #endif + #ifdef ROM_VIMSModeSet + #undef VIMSModeSet + #define VIMSModeSet ROM_VIMSModeSet + #endif + #ifdef ROM_VIMSModeGet + #undef VIMSModeGet + #define VIMSModeGet ROM_VIMSModeGet + #endif + #ifdef ROM_VIMSModeSafeSet + #undef VIMSModeSafeSet + #define VIMSModeSafeSet ROM_VIMSModeSafeSet + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __VIMS_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.c new file mode 100644 index 00000000..e0612b52 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.c @@ -0,0 +1,39 @@ +/****************************************************************************** +* Filename: watchdog.c +* +* Description: Driver for the Watchdog Timer. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include "watchdog.h" + +// See watchdog.h for implementation diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.h new file mode 100644 index 00000000..1c237827 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog.h @@ -0,0 +1,518 @@ +/****************************************************************************** +* Filename: watchdog.h +* +* Description: Defines and prototypes for the Watchdog Timer. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup peripheral_group +//! @{ +//! \addtogroup wdt_api +//! @{ +// +//***************************************************************************** + +#ifndef __WATCHDOG_H__ +#define __WATCHDOG_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_wdt.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired + +//***************************************************************************** +// +// The type of interrupt that can be generated by the watchdog. +// +//***************************************************************************** +#define WATCHDOG_INT_TYPE_INT WDT_CTL_INTTYPE_MASKABLE +#define WATCHDOG_INT_TYPE_NMI WDT_CTL_INTTYPE_NONMASKABLE + +//***************************************************************************** +// +// API Functions and prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Determines if the watchdog timer is enabled. +//! +//! This function checks to see if the watchdog timer is enabled. +//! +//! \return Returns status of Watchdog Timer: +//! - \c true : Watchdog timer is enabled. +//! - \c false : Watchdog timer is disabled. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogRunning(void) +{ + // See if the watchdog timer module is enabled, and return. + return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer counter and interrupt. +//! +//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogEnable(void) +{ + // Enable the watchdog timer module. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer reset. +//! +//! This function enables the capability of the watchdog timer to issue a reset +//! to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetEnable(void) +{ + // Enable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer reset. +//! +//! This function disables the capability of the watchdog timer to issue a +//! reset to the processor after a second timeout condition. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogResetDisable(void) +{ + // Disable the watchdog reset. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer lock mechanism. +//! +//! This function locks out write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogLock(void) +{ + // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK + // register causes the lock to go into effect. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; +} + +//***************************************************************************** +// +//! \brief Disables the watchdog timer lock mechanism. +//! +//! This function enables write access to the watchdog timer configuration +//! registers. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogUnlock(void) +{ + // Unlock watchdog register writes. + HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; +} + +//***************************************************************************** +// +//! \brief Gets the state of the watchdog timer lock mechanism. +//! +//! This function returns the lock state of the watchdog timer registers. +//! +//! \return Returns state of lock mechanism. +//! - \c true : Watchdog timer registers are locked. +//! - \c false : Registers are not locked. +// +//***************************************************************************** +__STATIC_INLINE bool +WatchdogLockState(void) +{ + // Get the lock state. + return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? + true : false); +} + +//***************************************************************************** +// +//! \brief Sets the watchdog timer reload value. +//! +//! This function configures the value to load into the watchdog timer when the +//! count reaches zero for the first time; if the watchdog timer is running +//! when this function is called, then the value is immediately loaded into the +//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an +//! interrupt is immediately generated. +//! +//! \note This function has no effect if the watchdog timer has been locked. +//! +//! \param ui32LoadVal is the load value for the watchdog timer. +//! +//! \return None +//! +//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogReloadSet(uint32_t ui32LoadVal) +{ + // Set the load register. + HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; +} + +//***************************************************************************** +// +//! \brief Gets the watchdog timer reload value. +//! +//! This function gets the value that is loaded into the watchdog timer when +//! the count reaches zero for the first time. +//! +//! \return None +//! +//! \sa \ref WatchdogReloadSet() +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogReloadGet(void) +{ + // Get the load register. + return(HWREG(WDT_BASE + WDT_O_LOAD)); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer value. +//! +//! This function reads the current value of the watchdog timer. +//! +//! \return Returns the current value of the watchdog timer. +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogValueGet(void) +{ + // Get the current watchdog timer register value. + return(HWREG(WDT_BASE + WDT_O_VALUE)); +} + +//***************************************************************************** +// +//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! +//! +//! This function registers a function as the interrupt handler for a specific +//! interrupt and enables the corresponding interrupt in the interrupt controller. +//! +//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the +//! interrupt handler's responsibility to clear the interrupt source via +//! \ref WatchdogIntClear(). +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \param pfnHandler is a pointer to the function to be called when the +//! watchdog timer interrupt occurs. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntRegister(void (*pfnHandler)(void)) +{ + // Register the interrupt handler. + IntRegister(INT_WDT_IRQ, pfnHandler); + + // Enable the watchdog timer interrupt. + IntEnable(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. +//! +//! This function does the actual unregistering of the interrupt handler. This +//! function clears the handler to be called when a watchdog timer interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! +//! \note This function registers the standard watchdog interrupt handler. To +//! register the NMI watchdog handler, use \ref IntRegister() to register the +//! handler for the \b INT_NMI_FAULT interrupt. +//! +//! \return None +//! +//! \sa \ref IntRegister() for important information about registering interrupt +//! handlers. +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntUnregister(void) +{ + // Disable the interrupt. + IntDisable(INT_WDT_IRQ); + + // Unregister the interrupt handler. + IntUnregister(INT_WDT_IRQ); +} + +//***************************************************************************** +// +//! \brief Enables the watchdog timer. +//! +//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). +//! +//! \return None +//! +//! \sa \ref WatchdogEnable() +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntEnable(void) +{ + // Enable the Watchdog interrupt. + WatchdogEnable(); +} + +//***************************************************************************** +// +//! \brief Gets the current watchdog timer interrupt status. +//! +//! This function returns the interrupt status for the watchdog timer module. +//! +//! \return Returns the interrupt status. +//! - 1 : Watchdog time-out has occurred. +//! - 0 : Watchdog time-out has not occurred. +//! +//! \sa \ref WatchdogIntClear(); +// +//***************************************************************************** +__STATIC_INLINE uint32_t +WatchdogIntStatus(void) +{ + // Return either the interrupt status or the raw interrupt status as + // requested. + return(HWREG(WDT_BASE + WDT_O_RIS)); +} + +//***************************************************************************** +// +//! \brief Clears the watchdog timer interrupt. +//! +//! The watchdog timer interrupt source is cleared, so that it no longer +//! asserts. +//! +//! \note Due to write buffers and synchronizers in the system it may take several +//! clock cycles from a register write clearing an event in a module and until the +//! event is actually cleared in the NVIC of the system CPU. It is recommended to +//! clear the event source early in the interrupt service routine (ISR) to allow +//! the event clear to propagate to the NVIC before returning from the ISR. +//! At the same time, an early event clear allows new events of the same type to be +//! pended instead of ignored if the event is cleared later in the ISR. +//! It is the responsibility of the programmer to make sure that enough time has passed +//! before returning from the ISR to avoid false re-triggering of the cleared event. +//! A simple, although not necessarily optimal, way of clearing an event before +//! returning from the ISR is: +//! -# Write to clear event (interrupt source). (buffered write) +//! -# Dummy read from the event source module. (making sure the write has propagated) +//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntClear(void) +{ + // Clear the interrupt source. + HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; +} + +//***************************************************************************** +// +//! \brief Sets the type of interrupt generated by the watchdog. +//! +//! This function sets the type of interrupt that is generated if the watchdog +//! timer expires. +//! +//! When configured to generate an NMI, the watchdog interrupt must still be +//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the +//! NMI handler with \ref WatchdogIntClear(). +//! +//! \param ui32Type is the type of interrupt to generate. +//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). +//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogIntTypeSet(uint32_t ui32Type) +{ + // Check the arguments. + ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || + (ui32Type == WATCHDOG_INT_TYPE_NMI)); + + // Set the interrupt type. + HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; +} + +//***************************************************************************** +// +//! \brief Enables stalling of the watchdog timer during debug events. +//! +//! This function allows the watchdog timer to stop counting when the processor +//! is stopped by the debugger. By doing so, the watchdog is prevented from +//! expiring and resetting the system (if reset is enabled). The watchdog instead expires +//! after the appropriate number of processor cycles have been executed while +//! debugging (or at the appropriate time after the processor has been +//! restarted). +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallEnable(void) +{ + // Enable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; +} + +//***************************************************************************** +// +//! \brief Disables stalling of the watchdog timer during debug events. +//! +//! This function disables the debug mode stall of the watchdog timer. By +//! doing so, the watchdog timer continues to count regardless of the processor +//! debug state. +//! +//! \return None +// +//***************************************************************************** +__STATIC_INLINE void +WatchdogStallDisable(void) +{ + // Disable timer stalling. + HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; +} + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __WATCHDOG_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog_doc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog_doc.h new file mode 100644 index 00000000..d035f2d8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/watchdog_doc.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* Filename: watchdog_doc.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//! \addtogroup wdt_api +//! @{ +//! \section sec_wdt Introduction +//! +//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to +//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt +//! on the first time-out and a system reset on the following time-out if the application fails to +//! restart the WDT. +//! +//! WDT has the following features: +//! - 32-bit down counter with a configurable load register. +//! - Configurable interrupt generation logic with interrupt masking and optional NMI function. +//! - Optional reset generation. +//! - Register protection from runaway software (lock). +//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. +//! +//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at +//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled. +//! +//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out: +//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load +//! value, and resumes counting down from that value. +//! - If the WDT counts down to zero again before the application clears the interrupt, and the +//! reset signal has been enabled, the WDT asserts its reset signal to the system. +//! +//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device. +//! +//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet(). +//! However, it is not possible to detect which of the warm reset sources that caused the reset. +//! +//! Typical use case: +//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on +//! first time-out. +//! - The application must implement an interrupt handler for the selected interrupt type. If +//! application uses the \e static vector table (see startup_.c) the interrupt +//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler() +//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table, +//! see \ref sec_interrupt_table. +//! - Use \ref WatchdogResetEnable() to enable reset on second time-out. +//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter. +//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value. +//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration. +//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out. +//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts +//! the selected type of interrupt, reloads the counter, and starts counting down again. +//! - The interrupt handler triggered by the first time-out can be used to log debug information +//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT +//! times out the second time. +//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus +//! reloads the WDT counter. This means that the WDT interrupt handler never returns. +//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt +//! is still asserted then WDT triggers a reset (if enabled). +//! +//! \section sec_wdt_api API +//! +//! The API functions can be grouped like this: +//! +//! Watchdog configuration: +//! - \ref WatchdogIntTypeSet() +//! - \ref WatchdogResetEnable() +//! - \ref WatchdogResetDisable() +//! - \ref WatchdogReloadSet() +//! - \ref WatchdogEnable() +//! +//! Status: +//! - \ref WatchdogRunning() +//! - \ref WatchdogValueGet() +//! - \ref WatchdogReloadGet() +//! - \ref WatchdogIntStatus() +//! +//! Interrupt configuration: +//! - \ref WatchdogIntEnable() +//! - \ref WatchdogIntClear() +//! - \ref WatchdogIntRegister() +//! - \ref WatchdogIntUnregister() +//! +//! Register protection: +//! - \ref WatchdogLock() +//! - \ref WatchdogLockState() +//! - \ref WatchdogUnlock() +//! +//! Stall configuration for debugging: +//! - \ref WatchdogStallDisable() +//! - \ref WatchdogStallEnable() +//! +//! @} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/asmdefs.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/asmdefs.h new file mode 100644 index 00000000..3e3b8bc2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/asmdefs.h @@ -0,0 +1,149 @@ +/****************************************************************************** +* Filename: asmdefs.h +* +* Description: Macros to allow assembly code be portable among tool chains. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef __IAR_SYSTEMS_ICC__ + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // __IAR_SYSTEMS_ICC__ + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(__GNUC__) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // __GNUC__ + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#if defined(__CC_ARM) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // __CC_ARM + + +#endif // __ASMDEF_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi.h new file mode 100644 index 00000000..ab6b18b0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi.h @@ -0,0 +1,1180 @@ +/****************************************************************************** +* Filename: hw_adi.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_H__ +#define __HW_ADI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the ADI master and +// accessing ADI slave registers via the ADI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a ADI Slave. +// +// The macros that that provide ADI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example ADI_O_SLAVECONF is a macro for a +// register offset and ADI_SLAVECONF_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; +// +// The "instruction offset" macros are used to pass an instruction to +// the ADI Master when accessing ADI slave registers. These macros are +// only used when accessing ADI Slave Registers. (Remember ADI +// Master Registers are accessed normally). +// +// The instructions supported when accessing an ADI Slave Register follow: +// - Direct Access to an ADI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a ADI Slave register. +// - Clear the specified bits in a ADI Slave register. +// - Mask write of 4 bits to the a ADI Slave register. +// - Mask write of 8 bits to the a ADI Slave register. +// - Mask write of 16 bits to the a ADI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are +// supported natively. If accessing wider bitfields, the read/write operation +// will be spread out over a number of transactions. This is hidden for the +// user, but can potentially be very timeconsuming. Especially of running +// on a slow clock. +// +// The generic format of using these macros for a read follows: +// // Read low 8-bits in ADI_SLAVE_OFF +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) +// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); +// +// Notes: In the above example: +// - ADI_MASTER_BASE is the base address of the ADI Master defined +// in the hw_memmap.h header file. +// - ADI_SLAVE_OFF is the ADI Slave offset defined in the +// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys +// module). +// - ADI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to an ADI Slave register +// ADI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; +// +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; +// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; +// +// // Write each byte at ADI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the ADI master instruction offsets. +// +//***************************************************************************** +#define ADI_O_DIR 0x00000000 // Offset for the direct access + // instruction +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 15:8 are + // mask. Bits 7:0 are data. Requires + // 'short' write. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. + // Data bit[n] is written if mask + // bit[n] is set ('1'). Bits 31:16 + // are mask. Bits 15:0 are data. + // Requires 'long' write. + +//***************************************************************************** +// +// The following are defines for the ADI register offsets. +// +//***************************************************************************** +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 + +//***************************************************************************** +// +// The following are defines pseudo-magic numbers that should go away. +// New code should not use these registers and old code should be ported +// to not use these. +// +//***************************************************************************** +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte + // offsets 0 to 3 +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte + // offsets 4 to 7 +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte + // offsets 8 to 11 +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte + // offsets 12 to 15 +#define ADI_O_SET03 0x00000010 // Set register for ADI byte + // offsets 0 to 3 +#define ADI_O_SET47 0x00000014 // Set register for ADI byte + // offsets 4 to 7 +#define ADI_O_SET811 0x00000018 // Set register for ADI byte + // offsets 8 to 11 +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte + // offsets 12 to 15 +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte + // offsets 0 to 3 +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte + // offsets 4 to 7 +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte + // offsets 8 to 11 +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte + // offsets 12 to 15 +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration + // register +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI + // Registers at byte offsets 14 and + // 15 +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI + // Registers at byte offsets 0 and + // 1 +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI + // Registers at byte offsets 2 and + // 3 +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI + // Registers at byte offsets 4 and + // 5 +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI + // Registers at byte offsets 6 and + // 7 +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI + // Registers at byte offsets 8 and + // 9 +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI + // Registers at byte offsets 10 and + // 11 +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI + // Registers at byte offsets 12 and + // 13 +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI + // Registers at byte offsets 14 and + // 15 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR03 register. +// +//***************************************************************************** +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR47 register. +// +//***************************************************************************** +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR811 register. +// +//***************************************************************************** +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register + // 11 +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register + // 10 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_DIR1215 register. +// +//***************************************************************************** +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register + // 15 +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register + // 14 +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register + // 13 +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register + // 12 +#define ADI_DIR1215_B0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET03 register. +// +//***************************************************************************** +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 3. Read returns 0. +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 2. Read returns 0. +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 1. Read returns 0. +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 0. Read returns 0. +#define ADI_SET03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET47 register. +// +//***************************************************************************** +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 7. Read returns 0. +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 6. Read returns 0. +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 5. Read returns 0. +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 4. Read returns 0. +#define ADI_SET47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET811 register. +// +//***************************************************************************** +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 11. Read returns 0. +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 10. Read returns 0. +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 9. Read returns 0. +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 8. Read returns 0. +#define ADI_SET811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_SET1215 register. +// +//***************************************************************************** +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the + // corresponding bit in ADI + // register 15. Read returns 0. +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the + // corresponding bit in ADI + // register 14. Read returns 0. +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the + // corresponding bit in ADI + // register 13. Read returns 0. +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the + // corresponding bit in ADI + // register 12. Read returns 0. +#define ADI_SET1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR03 register. +// +//***************************************************************************** +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 3 +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 2 +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 1 +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 0 +#define ADI_CLR03_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR47 register. +// +//***************************************************************************** +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 7 +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 6 +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 5 +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 4 +#define ADI_CLR47_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR811 register. +// +//***************************************************************************** +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 11 +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 10 +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 9 +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 8 +#define ADI_CLR811_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_CLR1215 register. +// +//***************************************************************************** +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the + // corresponding bit in ADI + // register 15 +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the + // corresponding bit in ADI + // register 14 +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the + // corresponding bit in ADI + // register 13 +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the + // corresponding bit in ADI + // register 12 +#define ADI_CLR1215_S0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVESTAT register. +// +//***************************************************************************** +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ + // signal. Writing 0 to this bit + // forces a sync with slave, + // ensuring that req will be 0. It + // is recommended to write 0 to + // this register before power down + // of the master. +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK + // signal +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_SLAVECONF register. +// +//***************************************************************************** +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer + // accessible when this bit is set. + // (unless sticky_bit_overwrite is + // asserted on top module) +#define ADI_SLAVECONF_CONFLOCK_M \ + 0x00000080 +#define ADI_SLAVECONF_CONFLOCK_S 7 +#define ADI_SLAVECONF_WAITFORACK \ + 0x00000004 // A transaction on the ADI + // interface does not end until ack + // has been received from the slave + // when this bit is set. + +#define ADI_SLAVECONF_WAITFORACK_M \ + 0x00000004 +#define ADI_SLAVECONF_WAITFORACK_S 2 +#define ADI_SLAVECONF_ADICLKSPEED_M \ + 0x00000003 // Sets the period of an ADI + // transactions. All transactions + // takes an even number of clock + // cycles,- ADI clock rising edge + // occurs in the middle of the + // period. Data and ctrl to slave + // is set up in beginning of cycle, + // and data from slave is read in + // after the transaction 00: An ADI + // transaction takes 2 master clock + // cyclkes 01: An ADI transaction + // takes 4 master clock cycles 10: + // And ADI Transaction takes 8 + // master clock cycles 11: An ADI + // transaction takes 16 master + // clock cycles + +#define ADI_SLAVECONF_ADICLKSPEED_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B01 register. +// +//***************************************************************************** +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 1 +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 1, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 1 +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 1, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 0 +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 0, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 0 +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 0, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B01_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B23 register. +// +//***************************************************************************** +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 3 +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 3, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 3 +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 3, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 2 +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 2, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 2 +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 2, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B23_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B45 register. +// +//***************************************************************************** +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 5 +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 5, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 5 +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 5, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 4 +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 4, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 4 +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 4, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B45_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B67 register. +// +//***************************************************************************** +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 7 +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 7, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 7 +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 7, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 6 +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 6, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 6 +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 6, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B67_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK4B89 register. +// +//***************************************************************************** +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 9 +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 9, - only bits selected + // by mask M1H will be affected by + // access +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 9 +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 9, - only bits selected + // by mask M1L will be affected by + // access +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 8 +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 8, - only bits selected + // by mask M0H will be affected by + // access +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 8 +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 8, - only bits selected + // by mask M0L will be affected by + // access +#define ADI_MASK4B89_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1011 register. +// +//***************************************************************************** +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 11 +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 11, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 11 +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 11, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 10 +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 10, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 10 +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 10, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1011_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1213 register. +// +//***************************************************************************** +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 13 +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 13, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 13 +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 13, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 12 +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 12, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 12 +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 12, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1213_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK4B1415 register. +// +//***************************************************************************** +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI + // register 15 +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI + // register 15, - only bits + // selected by mask M1H will be + // affected by access +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI + // register 15 +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI + // register 15, - only bits + // selected by mask M1L will be + // affected by access +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI + // register 14 +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI + // register 14, - only bits + // selected by mask M0H will be + // affected by access +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI + // register 14 +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI + // register 14, - only bits + // selected by mask M0L will be + // affected by access +#define ADI_MASK4B1415_D0L_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B01 register. +// +//***************************************************************************** +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B01_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B23 register. +// +//***************************************************************************** +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B23_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B45 register. +// +//***************************************************************************** +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B45_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B67 register. +// +//***************************************************************************** +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B67_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the ADI_O_MASK8B89 register. +// +//***************************************************************************** +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only + // bits selected by mask M1 will be + // affected by access +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only + // bits selected by mask M0 will be + // affected by access +#define ADI_MASK8B89_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1011 register. +// +//***************************************************************************** +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1011_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1213 register. +// +//***************************************************************************** +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1213_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK8B1415 register. +// +//***************************************************************************** +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - + // only bits selected by mask M1 + // will be affected by access +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - + // only bits selected by mask M0 + // will be affected by access +#define ADI_MASK8B1415_D0_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B01 register. +// +//***************************************************************************** +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at + // offsets 0 and 1, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B01_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B23 register. +// +//***************************************************************************** +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at + // offsets 2 and 3, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B23_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B45 register. +// +//***************************************************************************** +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at + // offsets 4 and 5, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B45_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B67 register. +// +//***************************************************************************** +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at + // offsets 6 and 7, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B67_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B89 register. +// +//***************************************************************************** +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at + // offsets 8 and 9, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B89_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1011 register. +// +//***************************************************************************** +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at + // offsets 10 and 11, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1011_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1213 register. +// +//***************************************************************************** +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at + // offsets 12 and 13, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1213_D_S 0 +//***************************************************************************** +// +// The following are defines for the bit fields in the +// ADI_O_MASK16B1415 register. +// +//***************************************************************************** +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at + // offsets 14 and 15, - only bits + // selected by mask M will be + // affected by access +#define ADI_MASK16B1415_D_S 0 + +#endif // __HW_ADI_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_2_refsys.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_2_refsys.h new file mode 100644 index 00000000..1e2bd85f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_2_refsys.h @@ -0,0 +1,362 @@ +/****************************************************************************** +* Filename: hw_adi_2_refsys_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_2_REFSYS_H__ +#define __HW_ADI_2_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_2_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 + +// Internal +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B + +// Internal +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [4:0] TRIM_IREF +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL0 +// +//***************************************************************************** +// Field: [7:4] VTRIM_UDIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 + +// Field: [3:0] VTRIM_BOD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL1 +// +//***************************************************************************** +// Field: [7:4] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 + +// Field: [3:0] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL2 +// +//***************************************************************************** +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL3 +// +//***************************************************************************** +// Field: [7:6] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 + +// Field: [5:3] ITRIM_DIGLDO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BIAS_120P Internal. Only to be used through TI provided API. +// BIAS_100P Internal. Only to be used through TI provided API. +// BIAS_80P Internal. Only to be used through TI provided API. +// BIAS_60P Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 + +// Field: [2:0] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL4 +// +//***************************************************************************** +// Field: [6:5] UDIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 + +// Field: [4:2] DIG_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 + +// Field: [1] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 + +// Field: [0] UDIG_LDO_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_SOCLDOCTL5 +// +//***************************************************************************** +// Field: [3] IMON_ITEST_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 + +// Field: [2:0] TESTSEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDD_AON Internal. Only to be used through TI provided API. +// VREF_AMP Internal. Only to be used through TI provided API. +// ITEST Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL0 +// +//***************************************************************************** +// Field: [7] FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 + +// Field: [6:5] BIAS_RECHARGE_DLY +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// MIN_DLY_X8 Internal. Only to be used through TI provided API. +// MIN_DLY_X4 Internal. Only to be used through TI provided API. +// MIN_DLY_X2 Internal. Only to be used through TI provided API. +// MIN_DLY_X1 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 + +// Field: [4:3] TUNE_CAP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SHIFT_M108 Internal. Only to be used through TI provided API. +// SHIFT_M70 Internal. Only to be used through TI provided API. +// SHIFT_M35 Internal. Only to be used through TI provided API. +// SHIFT_0 Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 + +// Field: [2:1] SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 + +// Field: [0] DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// HPOSC_2520MHZ Internal. Only to be used through TI provided API. +// HPOSC_840MHZ Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL1 +// +//***************************************************************************** +// Field: [5] BIAS_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 + +// Field: [4] PWRDET_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 + +// Field: [3:0] BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 + +//***************************************************************************** +// +// Register: ADI_2_REFSYS_O_HPOSCCTL2 +// +//***************************************************************************** +// Field: [7] BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 + +// Field: [6] TESTMUX_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 + +// Field: [5:4] ATEST_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 + +// Field: [3:0] CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 + + +#endif // __ADI_2_REFSYS__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_3_refsys.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_3_refsys.h new file mode 100644 index 00000000..7ddb4c28 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_3_refsys.h @@ -0,0 +1,685 @@ +/****************************************************************************** +* Filename: hw_adi_3_refsys_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_3_REFSYS_H__ +#define __HW_ADI_3_REFSYS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_3_REFSYS component +// +//***************************************************************************** +// Internal +#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 + +// Internal +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 + +// DCDC Control 0 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 + +// DCDC Control 1 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 + +// DCDC Control 2 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A + +// Internal +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B + +// RECHARGE_CONTROL_1 +#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C + +// Recharge Comparator Control Byte 0 +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D + +// Recharge Comparator Control Byte 1 +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_ATESTCTL1 +// +//***************************************************************************** +// Field: [4:3] ATEST0_CTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ICELL_A0 Internal. Only to be used through TI provided API. +// IREF_A0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000 + +// Field: [2:0] ATEST1_CTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VREFM_A1 Internal. Only to be used through TI provided API. +// VPP_DIV5_A1 Internal. Only to be used through TI provided API. +// VREAD_DIV2_A1 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL0 +// +//***************************************************************************** +// Field: [7:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BMCOMPOUT Internal. Only to be used through TI provided API. +// VTEMP Internal. Only to be used through TI provided API. +// VREF0P8V Internal. Only to be used through TI provided API. +// VBGUNBUFF Internal. Only to be used through TI provided API. +// VBG Internal. Only to be used through TI provided API. +// IREF4U Internal. Only to be used through TI provided API. +// IVREF4U Internal. Only to be used through TI provided API. +// IPTAT2U Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL1 +// +//***************************************************************************** +// Field: [7:3] TRIM_VDDS_BOD +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// POS_27 Internal. Only to be used through TI provided API. +// POS_26 Internal. Only to be used through TI provided API. +// POS_25 Internal. Only to be used through TI provided API. +// POS_24 Internal. Only to be used through TI provided API. +// POS_31 Internal. Only to be used through TI provided API. +// POS_30 Internal. Only to be used through TI provided API. +// POS_29 Internal. Only to be used through TI provided API. +// POS_28 Internal. Only to be used through TI provided API. +// POS_19 Internal. Only to be used through TI provided API. +// POS_18 Internal. Only to be used through TI provided API. +// POS_17 Internal. Only to be used through TI provided API. +// POS_16 Internal. Only to be used through TI provided API. +// POS_23 Internal. Only to be used through TI provided API. +// POS_22 Internal. Only to be used through TI provided API. +// POS_21 Internal. Only to be used through TI provided API. +// POS_20 Internal. Only to be used through TI provided API. +// POS_11 Internal. Only to be used through TI provided API. +// POS_10 Internal. Only to be used through TI provided API. +// POS_9 Internal. Only to be used through TI provided API. +// POS_8 Internal. Only to be used through TI provided API. +// POS_15 Internal. Only to be used through TI provided API. +// POS_14 Internal. Only to be used through TI provided API. +// POS_13 Internal. Only to be used through TI provided API. +// POS_12 Internal. Only to be used through TI provided API. +// POS_3 Internal. Only to be used through TI provided API. +// POS_2 Internal. Only to be used through TI provided API. +// POS_1 Internal. Only to be used through TI provided API. +// POS_0 Internal. Only to be used through TI provided API. +// POS_7 Internal. Only to be used through TI provided API. +// POS_6 Internal. Only to be used through TI provided API. +// POS_5 Internal. Only to be used through TI provided API. +// POS_4 Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 + +// Field: [2] BATMON_COMP_TEST_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 + +// Field: [1:0] TESTCTL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// IPTAT1U Internal. Only to be used through TI provided API. +// BMCOMPIN Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL2 +// +//***************************************************************************** +// Field: [7:4] TRIM_VREF +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 + +// Field: [3] BOD_EXTERNAL_REG_MODE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3 + +// Field: [1:0] TRIM_TSENSE +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_REFSYSCTL3 +// +//***************************************************************************** +// Field: [7] BOD_BG_TRIM_EN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 + +// Field: [6] VTEMP_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 + +// Field: [5:0] TRIM_VBG +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL0 +// +//***************************************************************************** +// Field: [7:5] GLDO_ISRC +// +// Set charge and re-charge current level. +// 2's complement encoding. +// +// 0x0: Default 11mA. +// 0x3: Max 15mA. +// 0x4: Max 5mA +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 + +// Field: [4:0] VDDR_TRIM +// +// Set the VDDR voltage. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x05: Typical voltage after trim voltage 1.71V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL1 +// +//***************************************************************************** +// Field: [7:6] IPTAT_TRIM +// +// Trim GLDO bias current. +// Proprietary encoding. +// +// 0x0: Default +// 0x1: Increase GLDO bias by 1.3x. +// 0x2: Increase GLDO bias by 1.6x. +// 0x3: Decrease GLDO bias by 0.7x. +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 + +// Field: [5] VDDR_OK_HYST +// +// Increase the hysteresis for when VDDR is considered ok. +// +// 0: Hysteresis = 60mV +// 1: Hysteresis = 70mV +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 + +// Field: [4:0] VDDR_TRIM_SLEEP +// +// Set the min VDDR voltage threshold during sleep mode. +// Proprietary encoding. +// +// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. +// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. +// Step size = 16mV +// +// 0x00: Default, about 1.63V. +// 0x19: Typical voltage after trim voltage 1.52V. +// 0x15: Max voltage 1.96V. +// 0x16: Min voltage 1.47V. +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL2 +// +//***************************************************************************** +// Field: [6] TURNON_EA_SW +// +// Turn on erroramp switch +// +// 0: Erroramp Off (Default) +// 1: Erroramp On. Turns on GLDO error amp switch. +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 + +// Field: [5] TEST_VDDR +// +// Connect VDDR to ATEST bus +// +// 0: Not connected. +// 1: Connected +// +// Set TESTSEL = 0x0 first before setting this bit. +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 + +// Field: [4] BIAS_DIS +// +// Disable dummy bias current. +// +// 0: Dummy bias current on (Default) +// 1: Dummy bias current off +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 + +// Field: [3:0] TESTSEL +// +// Select signal for test bus, one hot. +// ENUMs: +// VDDROK VDDR_OK connected to test bus. +// IB1U 1uA bias current connected to test bus. +// PASSGATE Pass transistor gate voltage connected to test +// bus. +// ERRAMP_OUT Error amp output voltage connected to test bus. +// NC No signal connected to test bus. +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL3 +// +//***************************************************************************** +// Field: [1:0] VDDR_BOOST_COMP +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// BOOST_P1 Internal. Only to be used through TI provided API. +// BOOST Internal. Only to be used through TI provided API. +// BOOST_N1 Internal. Only to be used through TI provided API. +// DEFAULT Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL4 +// +//***************************************************************************** +// Field: [7:6] DEADTIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 + +// Field: [5:3] LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 + +// Field: [2:0] HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_DCDCCTL5 +// +//***************************************************************************** +// Field: [5] TESTN +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 + +// Field: [4] TESTP +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 + +// Field: [3] DITHER_EN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// EN Internal. Only to be used through TI provided API. +// DIS Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 + +// Field: [2:0] IPEAK +// +// Internal. Only to be used through TI provided API. +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_AUX_DEBUG +// +//***************************************************************************** +// Field: [6] LPM_BIAS_BACKUP_EN +// +// Activate the backup circuit in case the main circuit does not work +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6 + +// Field: [5] DAC_DBG_OFFSET_COMP +// +// Offset compensation signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5 + +// Field: [4] DAC_DBG_HOLD +// +// S-H Cap hold signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4 + +// Field: [3] DAC_DBG_PRECHARGE +// +// PRE-CHARGE signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3 + +// Field: [2] DAC_DBG_CAP_SAMPLE +// +// Cap-array sample signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2 + +// Field: [1] DAC_DBG_SAMPLE +// +// S-H Cap sample signal (Debug Mode) +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1 + +// Field: [0] DAC_DBG_EN +// +// Enable Debug Mode +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 +// +//***************************************************************************** +// Field: [4] COMP_CLK_DISABLE +// +// Enable/Disable the 32 kHz clock (SCLK_LF) to the recharge comparator +// ENUMs: +// DIS Disable the clock +// EN Enable the clock +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000 + +// Field: [3:0] TRIM_RECHARGE_COMP_REFLEVEL +// +// Trim ref level of recharge. +// +// 0xF: 90% of VDDR level. +// 0x0: 100% of VDDR level. +// +// Step size = 0.67% of VDDR level. +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_W \ + 4 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M \ + 0x0000000F +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S \ + 0 + +//***************************************************************************** +// +// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 +// +//***************************************************************************** +// Field: [7] RECHARGE_BLOCK_VTRIG_EN +// +// Enable/Disable ATEST input to VDDR input of recharge comparator. Used for +// trimming the recharge voltage reference level +// ENUMs: +// EN Enable. VDDR input is connected to ATEST network +// DIS Disable. VDDR input is connected to VDDR itself +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \ + 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \ + 7 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \ + 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \ + 0x00000000 + +// Field: [6] RECHARGE_BLOCK_ATEST_EN +// +// Enable/Disable test inputs/outputs to recharge comparator block +// ENUMs: +// EN Enable +// DIS Disable +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \ + 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \ + 6 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \ + 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \ + 0x00000000 + +// Field: [5] FORCE_SAMPLE_VDDR +// +// Force Sample of VDDR on cap divider +// ENUMs: +// EN Enable +// DIS Disable +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000 + +// Field: [4:0] TRIM_RECHARGE_COMP_OFFSET +// +// Trim offset of Recharge comparator. +// +// 0x00: Maximum degeneration on input side (VDDR side). +// 0x1F: Maximum degeneration on reference side from cap divider. +// 0x10: Nominal code. +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \ + 5 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \ + 0x0000001F +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \ + 0 + + +#endif // __ADI_3_REFSYS__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_4_aux.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_4_aux.h new file mode 100644 index 00000000..131535be --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_adi_4_aux.h @@ -0,0 +1,513 @@ +/****************************************************************************** +* Filename: hw_adi_4_aux_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_ADI_4_AUX_H__ +#define __HW_ADI_4_AUX_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// ADI_4_AUX component +// +//***************************************************************************** +// Internal +#define ADI_4_AUX_O_MUX0 0x00000000 + +// Internal +#define ADI_4_AUX_O_MUX1 0x00000001 + +// Internal +#define ADI_4_AUX_O_MUX2 0x00000002 + +// Internal +#define ADI_4_AUX_O_MUX3 0x00000003 + +// Current Source +#define ADI_4_AUX_O_ISRC 0x00000004 + +// Comparator +#define ADI_4_AUX_O_COMP 0x00000005 + +// Internal +#define ADI_4_AUX_O_MUX4 0x00000007 + +// ADC Control 0 +#define ADI_4_AUX_O_ADC0 0x00000008 + +// ADC Control 1 +#define ADI_4_AUX_O_ADC1 0x00000009 + +// ADC Reference 0 +#define ADI_4_AUX_O_ADCREF0 0x0000000A + +// ADC Reference 1 +#define ADI_4_AUX_O_ADCREF1 0x0000000B + +// Internal +#define ADI_4_AUX_O_LPMBIAS 0x0000000E + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX0 +// +//***************************************************************************** +// Field: [6] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDR_1P8V Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000 + +// Field: [3:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// ADCVREFP Internal. Only to be used through TI provided API. +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX1 +// +//***************************************************************************** +// Field: [7:0] COMPA_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX2 +// +//***************************************************************************** +// Field: [7:3] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// VSS Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// ATEST1 Internal. Only to be used through TI provided API. +// ATEST0 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 + +// Field: [2:0] DAC_VREF_SEL +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// VDDS Internal. Only to be used through TI provided API. +// ADCREF Internal. Only to be used through TI provided API. +// DCOUPL Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX3 +// +//***************************************************************************** +// Field: [7:0] ADCCOMPB_IN +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ISRC +// +//***************************************************************************** +// Field: [7:2] TRIM +// +// Adjust current from current source. +// +// Output currents may be combined to get desired total current. +// ENUMs: +// 11P75U 11.75 uA +// 4P5U 4.5 uA +// 2P0U 2.0 uA +// 1P0U 1.0 uA +// 0P5U 0.5 uA +// 0P25U 0.25 uA +// NC No current connected +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 + +// Field: [0] EN +// +// Current source enable +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_COMP +// +//***************************************************************************** +// Field: [7] COMPA_REF_RES_EN +// +// Enables 400kohm resistance from COMPA reference node to ground. Used with +// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 + +// Field: [6] COMPA_REF_CURR_EN +// +// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires +// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for +// cap-sense. +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 + +// Field: [5:3] LPM_BIAS_WIDTH_TRIM +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 + +// Field: [2] COMPB_EN +// +// COMPB enable +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 + +// Field: [0] COMPA_EN +// +// COMPA enable +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_MUX4 +// +//***************************************************************************** +// Field: [7:0] COMPA_REF +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// AUXIO19 Internal. Only to be used through TI provided API. +// AUXIO20 Internal. Only to be used through TI provided API. +// AUXIO21 Internal. Only to be used through TI provided API. +// AUXIO22 Internal. Only to be used through TI provided API. +// AUXIO23 Internal. Only to be used through TI provided API. +// AUXIO24 Internal. Only to be used through TI provided API. +// AUXIO25 Internal. Only to be used through TI provided API. +// AUXIO26 Internal. Only to be used through TI provided API. +// NC Internal. Only to be used through TI provided API. +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC0 +// +//***************************************************************************** +// Field: [7] SMPL_MODE +// +// ADC Sampling mode: +// +// 0: Synchronous mode +// 1: Asynchronous mode +// +// The ADC does a sample-and-hold before conversion. In synchronous mode the +// sampling starts when the ADC clock detects a rising edge on the trigger +// signal. Jitter/uncertainty will be inferred in the detection if the trigger +// signal originates from a domain that is asynchronous to the ADC clock. +// SMPL_CYCLE_EXP determines the the duration of sampling. +// Conversion starts immediately after sampling ends. +// +// In asynchronous mode the sampling is continuous when enabled. Sampling ends +// and conversion starts immediately with the rising edge of the trigger +// signal. Sampling restarts when the conversion has finished. +// Asynchronous mode is useful when it is important to avoid jitter in the +// sampling instant of an externally driven signal +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 + +// Field: [6:3] SMPL_CYCLE_EXP +// +// Controls the sampling duration before conversion when the ADC is operated in +// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous +// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. +// ENUMs: +// 10P9_MS 65536x 6 MHz clock periods = 10.9ms +// 5P46_MS 32768x 6 MHz clock periods = 5.46ms +// 2P73_MS 16384x 6 MHz clock periods = 2.73ms +// 1P37_MS 8192x 6 MHz clock periods = 1.37ms +// 682_US 4096x 6 MHz clock periods = 682us +// 341_US 2048x 6 MHz clock periods = 341us +// 170_US 1024x 6 MHz clock periods = 170us +// 85P3_US 512x 6 MHz clock periods = 85.3us +// 42P6_US 256x 6 MHz clock periods = 42.6us +// 21P3_US 128x 6 MHz clock periods = 21.3us +// 10P6_US 64x 6 MHz clock periods = 10.6us +// 5P3_US 32x 6 MHz clock periods = 5.3us +// 2P7_US 16x 6 MHz clock periods = 2.7us +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 + +// Field: [1] RESET_N +// +// Reset ADC digital subchip, active low. ADC must be reset every time it is +// reconfigured. +// +// 0: Reset +// 1: Normal operation +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 + +// Field: [0] EN +// +// ADC Enable +// +// 0: Disable +// 1: Enable +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADC1 +// +//***************************************************************************** +// Field: [0] SCALE_DIS +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF0 +// +//***************************************************************************** +// Field: [6] REF_ON_IDLE +// +// Enable ADCREF in IDLE state. +// +// 0: Disabled in IDLE state +// 1: Enabled in IDLE state +// +// Keep ADCREF enabled when ADC0.SMPL_MODE = 0. +// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than +// 0x6 (21.3us sampling time). +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 + +// Field: [5] IOMUX +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 + +// Field: [4] EXT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 + +// Field: [3] SRC +// +// ADC reference source: +// +// 0: Fixed reference = 4.3V +// 1: Relative reference = VDDS +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 + +// Field: [0] EN +// +// ADC reference module enable: +// +// 0: ADC reference module powered down +// 1: ADC reference module enabled +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_ADCREF1 +// +//***************************************************************************** +// Field: [5:0] VTRIM +// +// Trim output voltage of ADC fixed reference (64 steps, 2's complement). +// Applies only for ADCREF0.SRC = 0. +// +// Examples: +// 0x00 - nominal voltage 1.43V +// 0x01 - nominal + 0.4% 1.435V +// 0x3F - nominal - 0.4% 1.425V +// 0x1F - maximum voltage 1.6V +// 0x20 - minimum voltage 1.3V +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 + +//***************************************************************************** +// +// Register: ADI_4_AUX_O_LPMBIAS +// +//***************************************************************************** +// Field: [5:0] LPM_TRIM_IOUT +// +// Internal. Only to be used through TI provided API. +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 + + +#endif // __ADI_4_AUX__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_batmon.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_batmon.h new file mode 100644 index 00000000..c4ef916c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_batmon.h @@ -0,0 +1,662 @@ +/****************************************************************************** +* Filename: hw_aon_batmon_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_BATMON_H__ +#define __HW_AON_BATMON_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_BATMON component +// +//***************************************************************************** +// Internal +#define AON_BATMON_O_CTL 0x00000000 + +// Internal +#define AON_BATMON_O_MEASCFG 0x00000004 + +// Internal +#define AON_BATMON_O_TEMPP0 0x0000000C + +// Internal +#define AON_BATMON_O_TEMPP1 0x00000010 + +// Internal +#define AON_BATMON_O_TEMPP2 0x00000014 + +// Internal +#define AON_BATMON_O_BATMONP0 0x00000018 + +// Internal +#define AON_BATMON_O_BATMONP1 0x0000001C + +// Internal +#define AON_BATMON_O_IOSTRP0 0x00000020 + +// Internal +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 + +// Last Measured Battery Voltage +#define AON_BATMON_O_BAT 0x00000028 + +// Battery Update +#define AON_BATMON_O_BATUPD 0x0000002C + +// Temperature +#define AON_BATMON_O_TEMP 0x00000030 + +// Temperature Update +#define AON_BATMON_O_TEMPUPD 0x00000034 + +// Event Mask +#define AON_BATMON_O_EVENTMASK 0x00000048 + +// Event +#define AON_BATMON_O_EVENT 0x0000004C + +// Battery Upper Limit +#define AON_BATMON_O_BATTUL 0x00000050 + +// Battery Lower Limit +#define AON_BATMON_O_BATTLL 0x00000054 + +// Temperature Upper Limit +#define AON_BATMON_O_TEMPUL 0x00000058 + +// Temperature Lower Limit +#define AON_BATMON_O_TEMPLL 0x0000005C + +//***************************************************************************** +// +// Register: AON_BATMON_O_CTL +// +//***************************************************************************** +// Field: [1] CALC_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 + +// Field: [0] MEAS_EN +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_MEASCFG +// +//***************************************************************************** +// Field: [1:0] PER +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 32CYC Internal. Only to be used through TI provided API. +// 16CYC Internal. Only to be used through TI provided API. +// 8CYC Internal. Only to be used through TI provided API. +// CONT Internal. Only to be used through TI provided API. +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP0 +// +//***************************************************************************** +// Field: [7:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPP2 +// +//***************************************************************************** +// Field: [4:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP0 +// +//***************************************************************************** +// Field: [6:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP0_CFG_W 7 +#define AON_BATMON_BATMONP0_CFG_M 0x0000007F +#define AON_BATMON_BATMONP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATMONP1 +// +//***************************************************************************** +// Field: [5:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_IOSTRP0 +// +//***************************************************************************** +// Field: [5:4] CFG2 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 + +// Field: [3:0] CFG1 +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_FLASHPUMPP0 +// +//***************************************************************************** +// Field: [9] DIS_NOISE_FILTER +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9 + +// Field: [8] FALLB +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 + +// Field: [7:6] HIGHLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 + +// Field: [5] LOWLIM +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 + +// Field: [4] OVR +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 + +// Field: [3:0] CFG +// +// Internal. Only to be used through TI provided API. +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New battery voltage is present. +// +// Write 1 to clear the status. +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMP +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature value. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUPD +// +//***************************************************************************** +// Field: [0] STAT +// +// +// 0: No update since last clear +// 1: New temperature is present. +// +// Write 1 to clear the status. +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_EVENTMASK +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE_MASK +// +// 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON +// 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5 + +// Field: [4] BATT_UPDATE_MASK +// +// 1: EVENT.BATT_UPDATE contributes to combined event from BATMON +// 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4 + +// Field: [3] TEMP_BELOW_LL_MASK +// +// 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3 + +// Field: [2] TEMP_OVER_UL_MASK +// +// 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON +// 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2 + +// Field: [1] BATT_BELOW_LL_MASK +// +// 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON +// 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1 + +// Field: [0] BATT_OVER_UL_MASK +// +// 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON +// 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_EVENT +// +//***************************************************************************** +// Field: [5] TEMP_UPDATE +// +// Alias to TEMPUPD.STAT +#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5 +#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_S 5 + +// Field: [4] BATT_UPDATE +// +// Alias to BATUPD.STAT +#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4 +#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_S 4 + +// Field: [3] TEMP_BELOW_LL +// +// Read: +// 1: Temperature level is below the lower limit set by TEMPLL. +// 0: Temperature level is not below the lower limit set by TEMPLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3 + +// Field: [2] TEMP_OVER_UL +// +// Read: +// 1: Temperature level is above the upper limit set by TEMPUL. +// 0: Temperature level is not above the upper limit set by TEMPUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2 +#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2 + +// Field: [1] BATT_BELOW_LL +// +// Read: +// 1: Battery level is below the lower limit set by BATTLL. +// 0: Battery level is not below the lower limit set by BATTLL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1 +#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1 + +// Field: [0] BATT_OVER_UL +// +// Read: +// 1: Battery level is above the upper limit set by BATTUL. +// 0: Battery level is not above the upper limit set by BATTUL. +// Write: +// 1: Clears the flag +// 0: No change in the flag +#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0 +#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATTUL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BATTUL_INT_W 3 +#define AON_BATMON_BATTUL_INT_M 0x00000700 +#define AON_BATMON_BATTUL_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BATTUL_FRAC_W 8 +#define AON_BATMON_BATTUL_FRAC_M 0x000000FF +#define AON_BATMON_BATTUL_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_BATTLL +// +//***************************************************************************** +// Field: [10:8] INT +// +// Integer part: +// +// 0x0: 0V + fractional part +// ... +// 0x3: 3V + fractional part +// 0x4: 4V + fractional part +#define AON_BATMON_BATTLL_INT_W 3 +#define AON_BATMON_BATTLL_INT_M 0x00000700 +#define AON_BATMON_BATTLL_INT_S 8 + +// Field: [7:0] FRAC +// +// Fractional part, standard binary fractional encoding. +// +// 0x00: .0V +// ... +// 0x20: 1/8 = .125V +// 0x40: 1/4 = .25V +// 0x80: 1/2 = .5V +// ... +// 0xA0: 1/2 + 1/8 = .625V +// ... +// 0xFF: Max +#define AON_BATMON_BATTLL_FRAC_W 8 +#define AON_BATMON_BATTLL_FRAC_M 0x000000FF +#define AON_BATMON_BATTLL_FRAC_S 0 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPUL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature upper limit. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMPUL_INT_W 9 +#define AON_BATMON_TEMPUL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPUL_INT_S 8 + +// Field: [7:6] FRAC +// +// Fractional part of temperature upper limit. +// Total value = INTEGER + FRACTIONAL +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0C +// 01: 0.25C +// 10: 0.5C +// 11: 0.75C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define AON_BATMON_TEMPUL_FRAC_W 2 +#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPUL_FRAC_S 6 + +//***************************************************************************** +// +// Register: AON_BATMON_O_TEMPLL +// +//***************************************************************************** +// Field: [16:8] INT +// +// Integer part (signed) of temperature lower limit. +// Total value = INTEGER + FRACTIONAL +// 2's complement encoding +// +// 0x100: Min value +// 0x1D8: -40C +// 0x1FF: -1C +// 0x00: 0C +// 0x1B: 27C +// 0x55: 85C +// 0xFF: Max value +#define AON_BATMON_TEMPLL_INT_W 9 +#define AON_BATMON_TEMPLL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPLL_INT_S 8 + +// Field: [7:6] FRAC +// +// Fractional part of temperature lower limit. +// Total value = INTEGER + FRACTIONAL +// The encoding is an extension of the 2's complement encoding. +// +// 00: 0.0C +// 01: 0.25C +// 10: 0.5C +// 11: 0.75C +// +// For example: +// 000000001,00 = ( 1+0,00) = 1,00 +// 000000000,11 = ( 0+0,75) = 0,75 +// 000000000,10 = ( 0+0,50) = 0,50 +// 000000000,01 = ( 0+0,25) = 0,25 +// 000000000,00 = ( 0+0,00) = 0,00 +// 111111111,11 = (-1+0,75) = -0,25 +// 111111111,10 = (-1+0,50) = -0,50 +// 111111111,01 = (-1+0,25) = -0,75 +// 111111111,00 = (-1+0,00) = -1,00 +// 111111110,11 = (-2+0,75) = -1,25 +#define AON_BATMON_TEMPLL_FRAC_W 2 +#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPLL_FRAC_S 6 + + +#endif // __AON_BATMON__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_event.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_event.h new file mode 100644 index 00000000..9dc633d0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_event.h @@ -0,0 +1,1135 @@ +/****************************************************************************** +* Filename: hw_aon_event_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_EVENT_H__ +#define __HW_AON_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_EVENT component +// +//***************************************************************************** +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL 0x00000000 + +// Wake-up Selector For MCU +#define AON_EVENT_O_MCUWUSEL1 0x00000004 + +// Event Selector For MCU Event Fabric +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 + +// RTC Capture Event Selector For AON_RTC +#define AON_EVENT_O_RTCSEL 0x0000000C + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL +// +//***************************************************************************** +// Field: [29:24] WU3_EV +// +// MCU Wakeup Source #3 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000 + +// Field: [21:16] WU2_EV +// +// MCU Wakeup Source #2 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000 + +// Field: [13:8] WU1_EV +// +// MCU Wakeup Source #1 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000 + +// Field: [5:0] WU0_EV +// +// MCU Wakeup Source #0 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_MCUWUSEL1 +// +//***************************************************************************** +// Field: [29:24] WU7_EV +// +// MCU Wakeup Source #7 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24 +#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000 + +// Field: [21:16] WU6_EV +// +// MCU Wakeup Source #6 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16 +#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000 + +// Field: [13:8] WU5_EV +// +// MCU Wakeup Source #5 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8 +#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000 + +// Field: [5:0] WU4_EV +// +// MCU Wakeup Source #4 +// +// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up +// the MCU domain from Power Off or Power Down. +// Note: +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_MCU_WU in +// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] +#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0 +#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_EVTOMCUSEL +// +//***************************************************************************** +// Field: [21:16] AON_PROG2_EV +// +// Event selector for AON_PROG2 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. +// ENUMs: +// NONE No event, always low +// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal +// directly from AUX Comparator B (inverted) as +// opposed to AUX_COMPB which is synchronized in +// AUX +// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal +// directly from the AUX Comparator B as opposed +// to AUX_COMPB which is synchronized in AUX +// BATMON_VOLT BATMON voltage update event +// BATMON_TEMP BATMON temperature update event +// AUX_TIMER1_EV AUX Timer 1 Event +// AUX_TIMER0_EV AUX Timer 0 Event +// AUX_TDC_DONE TDC completed or timed out +// AUX_ADC_DONE ADC conversion completed +// AUX_COMPB Comparator B triggered +// AUX_COMPA Comparator A triggered +// AUX_SWEV2 AUX Software triggered event #2. Triggered by +// AUX_EVCTL:SWEVSET.SWEV2 +// AUX_SWEV1 AUX Software triggered event #1. Triggered by +// AUX_EVCTL:SWEVSET.SWEV1 +// AUX_SWEV0 AUX Software triggered event #0. Triggered by +// AUX_EVCTL:SWEVSET.SWEV0 +// JTAG JTAG generated event +// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line +// toggles value every 32 kHz clock period) +// RTC_COMB_DLY RTC combined delayed event +// RTC_CH2_DLY RTC channel 2 - delayed event +// RTC_CH1_DLY RTC channel 1 - delayed event +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_AON_PROG2 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG2 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000 + +// Field: [13:8] AON_PROG1_EV +// +// Event selector for AON_PROG1 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY RTC channel 0 - delayed event +// RTC_CH2 RTC channel 2 event +// RTC_CH1 RTC channel 1 event +// RTC_CH0 RTC channel 0 event +// PAD Edge detect on any PAD +// BATMON_COMBINED Combined event from BATMON +// BATMON_TEMP_LL BATMON event: Temperature level below lower limit +// BATMON_TEMP_UL BATMON event: Temperature level above upper limit +// BATMON_BATT_LL BATMON event: Battery level below lower limit +// BATMON_BATT_UL BATMON event: Battery level above upper limit +// AUX_TIMER2_EV3 Event 3 from AUX TImer2 +// AUX_TIMER2_EV2 Event 2 from AUX TImer2 +// AUX_TIMER2_EV1 Event 1 from AUX TImer2 +// AUX_TIMER2_EV0 Event 0 from AUX TImer2 +// IOEV_AON_PROG1 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG1 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000 + +// Field: [5:0] AON_PROG0_EV +// +// Event selector for AON_PROG0 event. +// +// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY +// RTC_CH2 +// RTC_CH1 +// RTC_CH0 +// PAD +// BATMON_COMBINED +// BATMON_TEMP_LL +// BATMON_TEMP_UL +// BATMON_BATT_LL +// BATMON_BATT_UL +// AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 +// IOEV_AON_PROG0 Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_AON_PROG0 in +// [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN] +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000 + +//***************************************************************************** +// +// Register: AON_EVENT_O_RTCSEL +// +//***************************************************************************** +// Field: [5:0] RTC_CH1_CAPT_EV +// +// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer +// to AON_RTC:CH1CAPT +// ENUMs: +// NONE +// AUX_COMPB_ASYNC_N +// AUX_COMPB_ASYNC +// BATMON_VOLT +// BATMON_TEMP +// AUX_TIMER1_EV +// AUX_TIMER0_EV +// AUX_TDC_DONE +// AUX_ADC_DONE +// AUX_COMPB +// AUX_COMPA +// AUX_SWEV2 +// AUX_SWEV1 +// AUX_SWEV0 +// JTAG +// RTC_UPD +// RTC_COMB_DLY +// RTC_CH2_DLY +// RTC_CH1_DLY +// RTC_CH0_DLY +// RTC_CH2 +// RTC_CH1 +// RTC_CH0 +// PAD +// BATMON_COMBINED +// BATMON_TEMP_LL +// BATMON_TEMP_UL +// BATMON_BATT_LL +// BATMON_BATT_UL +// AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 +// IOEV_RTC Edge detect IO event from the DIO(s) which have +// enabled contribution to IOEV_RTC in +// [MCU_IOC:IOCFGx.IOEV_RTC_EN] +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000 + + +#endif // __AON_EVENT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_ioc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_ioc.h new file mode 100644 index 00000000..781ae858 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_ioc.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* Filename: hw_aon_ioc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_IOC_H__ +#define __HW_AON_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_IOC component +// +//***************************************************************************** +// Internal +#define AON_IOC_O_IOSTRMIN 0x00000000 + +// Internal +#define AON_IOC_O_IOSTRMED 0x00000004 + +// Internal +#define AON_IOC_O_IOSTRMAX 0x00000008 + +// IO Latch Control +#define AON_IOC_O_IOCLATCH 0x0000000C + +// SCLK_LF External Output Control +#define AON_IOC_O_CLK32KCTL 0x00000010 + +// TCK IO Pin Control +#define AON_IOC_O_TCKCTL 0x00000014 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMIN +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMED +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOSTRMAX +// +//***************************************************************************** +// Field: [2:0] GRAY_CODE +// +// Internal. Only to be used through TI provided API. +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_IOCLATCH +// +//***************************************************************************** +// Field: [0] EN +// +// Controls latches between MCU IOC and AON_IOC. +// +// The latches are transparent by default. +// +// They must be closed prior to power off the domain(s) controlling the IOs in +// order to preserve IO values on external pins. +// ENUMs: +// TRANSP Latches are transparent, meaning the value of the +// IO is directly controlled by the GPIO or +// peripheral value +// STATIC Latches are static, meaning the current value on +// the IO pin is frozen by latches and kept even +// if GPIO module or a peripheral module is turned +// off +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 + +//***************************************************************************** +// +// Register: AON_IOC_O_CLK32KCTL +// +//***************************************************************************** +// Field: [0] OE_N +// +// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for +// example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. +// 1: Output enable not active +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 + +//***************************************************************************** +// +// Register: AON_IOC_O_TCKCTL +// +//***************************************************************************** +// Field: [0] EN +// +// 0: Input driver for TCK disabled. +// 1: Input driver for TCK enabled. +#define AON_IOC_TCKCTL_EN 0x00000001 +#define AON_IOC_TCKCTL_EN_BITN 0 +#define AON_IOC_TCKCTL_EN_M 0x00000001 +#define AON_IOC_TCKCTL_EN_S 0 + + +#endif // __AON_IOC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_pmctl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_pmctl.h new file mode 100644 index 00000000..aa3f9325 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_pmctl.h @@ -0,0 +1,623 @@ +/****************************************************************************** +* Filename: hw_aon_pmctl_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_PMCTL_H__ +#define __HW_AON_PMCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_PMCTL component +// +//***************************************************************************** +// AUX SCE Clock Management +#define AON_PMCTL_O_AUXSCECLK 0x00000004 + +// RAM Configuration +#define AON_PMCTL_O_RAMCFG 0x00000008 + +// Power Management Control +#define AON_PMCTL_O_PWRCTL 0x00000010 + +// AON Power and Reset Status +#define AON_PMCTL_O_PWRSTAT 0x00000014 + +// Shutdown Control +#define AON_PMCTL_O_SHUTDOWN 0x00000018 + +// Recharge Controller Configuration +#define AON_PMCTL_O_RECHARGECFG 0x0000001C + +// Recharge Controller Status +#define AON_PMCTL_O_RECHARGESTAT 0x00000020 + +// Oscillator Configuration +#define AON_PMCTL_O_OSCCFG 0x00000024 + +// Reset Management +#define AON_PMCTL_O_RESETCTL 0x00000028 + +// Sleep Control +#define AON_PMCTL_O_SLEEPCTL 0x0000002C + +// JTAG Configuration +#define AON_PMCTL_O_JTAGCFG 0x00000034 + +// JTAG USERCODE +#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C + +//***************************************************************************** +// +// Register: AON_PMCTL_O_AUXSCECLK +// +//***************************************************************************** +// Field: [8] PD_SRC +// +// Selects the clock source for the AUX domain when AUX is in powerdown mode. +// Note: Switching the clock source is guaranteed to be glitch-free +// ENUMs: +// SCLK_LF LF clock (SCLK_LF ) +// NO_CLOCK No clock +#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 + +// Field: [0] SRC +// +// Selects the clock source for the AUX domain when AUX is in active mode. +// Note: Switching the clock source is guaranteed to be glitch-free +// ENUMs: +// SCLK_MF MF Clock (SCLK_MF) +// SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) +#define AON_PMCTL_AUXSCECLK_SRC 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_BITN 0 +#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_S 0 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RAMCFG +// +//***************************************************************************** +// Field: [17] AUX_SRAM_PWR_OFF +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 + +// Field: [16] AUX_SRAM_RET_EN +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 + +// Field: [3:0] BUS_SRAM_RET_EN +// +// MCU SRAM is partitioned into 5 banks . This register controls which of the +// banks that has retention during MCU Bus domain power off +// ENUMs: +// RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 +// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 +// ,SRAM:BANK2 and SRAM:BANK3 +// RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and +// SRAM:BANK2 +// RET_NONE Retention is disabled +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_PWRCTL +// +//***************************************************************************** +// Field: [2] DCDC_ACTIVE +// +// Select to use DCDC regulator for VDDR in active mode +// +// 0: Use GLDO for regulation of VDDR in active mode. +// 1: Use DCDC for regulation of VDDR in active mode. +// +// DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active +// mode +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 + +// Field: [1] EXT_REG_MODE +// +// Status of source for VDDRsupply: +// +// 0: DCDC or GLDO are generating VDDR +// 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR +#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 + +// Field: [0] DCDC_EN +// +// Select to use DCDC regulator during recharge of VDDR +// +// 0: Use GLDO for recharge of VDDR +// 1: Use DCDC for recharge of VDDR +// +// Note: This bitfield should be set to the same as DCDC_ACTIVE +#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_PWRSTAT +// +//***************************************************************************** +// Field: [2] JTAG_PD_ON +// +// Indicates JTAG power state: +// +// 0: JTAG is powered off +// 1: JTAG is powered on +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 + +// Field: [1] AUX_BUS_RESET_DONE +// +// Indicates Reset Done from AUX Bus: +// +// 0: AUX Bus is being reset +// 1: AUX Bus reset is released +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 + +// Field: [0] AUX_RESET_DONE +// +// Indicates Reset Done from AUX: +// +// 0: AUX is being reset +// 1: AUX reset is released +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_SHUTDOWN +// +//***************************************************************************** +// Field: [0] EN +// +// Shutdown control. +// +// 0: Do not write 0 to this bit. +// 1: Immediately start the process to enter shutdown mode +#define AON_PMCTL_SHUTDOWN_EN 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_BITN 0 +#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RECHARGECFG +// +//***************************************************************************** +// Field: [31:30] MODE +// +// Selects recharge algorithm for VDDR when the system is running on the uLDO +// ENUMs: +// COMPARATOR External recharge comparator. +// Note that the clock to +// the recharge comparator must be enabled, +// +// [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], +// before selecting this recharge algorithm. +// ADAPTIVE Adaptive timer +// STATIC Static timer +// OFF Recharge disabled +#define AON_PMCTL_RECHARGECFG_MODE_W 2 +#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_S 30 +#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 +#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 +#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 + +// Field: [23:20] C2 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_C2_W 4 +#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 +#define AON_PMCTL_RECHARGECFG_C2_S 20 + +// Field: [19:16] C1 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_C1_W 4 +#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 +#define AON_PMCTL_RECHARGECFG_C1_S 16 + +// Field: [15:11] MAX_PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 + +// Field: [10:8] MAX_PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 + +// Field: [7:3] PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_PMCTL_RECHARGECFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RECHARGECFG_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 +#define AON_PMCTL_RECHARGECFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RECHARGESTAT +// +//***************************************************************************** +// Field: [19:16] VDDR_SMPLS +// +// The last 4 VDDR samples. +// +// For each bit: +// 0: VDDR was below VDDR_OK threshold when recharge started +// 1: VDDR was above VDDR_OK threshold when recharge started +// +// The register is updated prior to every recharge period with a shift left, +// and bit 0 is updated with the last VDDR sample. +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 + +// Field: [15:0] MAX_USED_PER +// +// Shows the maximum number of 32kHz periods that have separated two recharge +// cycles and VDDR still was above VDDR_OK threshold when the latter recharge +// started. This register can be used as an indication of the leakage current +// during standby. +// +// This bitfield is cleared to 0 when writing this register. +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_OSCCFG +// +//***************************************************************************** +// Field: [7:3] PER_M +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_OSCCFG_PER_M_W 5 +#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 +#define AON_PMCTL_OSCCFG_PER_M_S 3 + +// Field: [2:0] PER_E +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_OSCCFG_PER_E_W 3 +#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 +#define AON_PMCTL_OSCCFG_PER_E_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_RESETCTL +// +//***************************************************************************** +// Field: [31] SYSRESET +// +// Cold reset register. Writing 1 to this bitfield will reset the entire chip +// and cause boot code to run again. +// +// 0: No effect +// 1: Generate system reset. Appears as SYSRESET in RESET_SRC +#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_S 31 + +// Field: [25] BOOT_DET_1_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 + +// Field: [24] BOOT_DET_0_CLR +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 + +// Field: [17] BOOT_DET_1_SET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 + +// Field: [16] BOOT_DET_0_SET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 + +// Field: [15] WU_FROM_SD +// +// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from +// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin +// being forced low) +// +// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup +// sources. +// +// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC +// 1: A wakeup has occurred from SHUTDOWN +// +// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. +#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 + +// Field: [14] GPIO_WU_FROM_SD +// +// A wakeup from SHUTDOWN on an IO event has occurred +// +// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup +// sources. +// +// 0: The wakeup did not occur from SHUTDOWN on an IO event +// 1: A wakeup from SHUTDOWN occurred from an IO event +// +// The case where WU_FROM_SD is asserted but this bitfield is not asserted will +// only occur in a debug session. The boot code will not proceed with wakeup +// from SHUTDOWN procedure until this bitfield is asserted as well. +// +// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 + +// Field: [13] BOOT_DET_1 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 + +// Field: [12] BOOT_DET_0 +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 + +// Field: [8] VDDS_LOSS_EN +// +// Controls reset generation in case VDDS is lost +// +// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDS generates system reset +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 + +// Field: [7] VDDR_LOSS_EN +// +// Controls reset generation in case VDDR is lost +// +// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 +// 1: Brown out detect of VDDR generates system reset +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 + +// Field: [6] VDD_LOSS_EN +// +// Controls reset generation in case VDD is lost +// +// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 +// 1: Brown out detect of VDD generates system reset +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 + +// Field: [5] CLK_LOSS_EN +// +// Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when +// clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] +// +// 0: Clock loss is ignored +// 1: Clock loss generates system reset +// +// Note: Clock loss reset generation must be disabled when changing clock +// source for SCLK_LF. Failure to do so may result in a spurious system +// reset. Clock loss reset generation is controlled by +// [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 + +// Field: [4] MCU_WARM_RESET +// +// Internal. Only to be used through TI provided API. +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 + +// Field: [3:1] RESET_SRC +// +// Shows the root cause of the last system reset. More than the reported reset +// source can have been active during the last system reset but only the root +// cause is reported. +// +// The capture feature is not rearmed until all off the possible reset sources +// have been released and the result has been copied to AON_PMCTL. During the +// copy and rearm process it is one 2MHz period in which and eventual new +// system reset will be reported as Power on reset regardless of the root +// cause. +// ENUMs: +// WARMRESET Software reset via PRCM warm reset request +// SYSRESET Software reset via SYSRESET or hardware power +// management timeout detection. +// +// Note: The hardware power +// management timeout circuit is always enabled. +// CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect +// VDDR_LOSS Brown out detect on VDDR +// VDDS_LOSS Brown out detect on VDDS +// PIN_RESET Reset pin +// PWR_ON Power on reset +#define AON_PMCTL_RESETCTL_RESET_SRC_W 3 +#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_S 1 +#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_SLEEPCTL +// +//***************************************************************************** +// Field: [0] IO_PAD_SLEEP_DIS +// +// Controls the I/O pad sleep mode. The boot code will set this bitfield +// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is +// set). +// +// 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations +// are latched. Inputs are transparent if pad is configured as input before +// IO_PAD_SLEEP_DIS is set to 1 +// 1: I/O pad sleep mode is disabled +// +// Application software must reconfigure the state for all IO's before setting +// this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_JTAGCFG +// +//***************************************************************************** +// Field: [8] JTAG_PD_FORCE_ON +// +// Controls JTAG Power domain power state: +// +// 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be +// powered off unless a debugger is attached) +// 1: JTAG Power Domain is forced on, independent of debug subsystem. +// +// Note: The reset value causes JTAG Power domain to be powered on by default. +// Software must clear this bit to turn off the JTAG Power domain +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 + +//***************************************************************************** +// +// Register: AON_PMCTL_O_JTAGUSERCODE +// +//***************************************************************************** +// Field: [31:0] USER_CODE +// +// 32-bit JTAG USERCODE register feeding main JTAG TAP +// Note: This field can be locked by LOCKCFG.LOCK +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 + + +#endif // __AON_PMCTL__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_rtc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_rtc.h new file mode 100644 index 00000000..ae7b53fd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aon_rtc.h @@ -0,0 +1,546 @@ +/****************************************************************************** +* Filename: hw_aon_rtc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AON_RTC_H__ +#define __HW_AON_RTC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AON_RTC component +// +//***************************************************************************** +// Control +#define AON_RTC_O_CTL 0x00000000 + +// Event Flags, RTC Status +#define AON_RTC_O_EVFLAGS 0x00000004 + +// Second Counter Value, Integer Part +#define AON_RTC_O_SEC 0x00000008 + +// Second Counter Value, Fractional Part +#define AON_RTC_O_SUBSEC 0x0000000C + +// Subseconds Increment +#define AON_RTC_O_SUBSECINC 0x00000010 + +// Channel Configuration +#define AON_RTC_O_CHCTL 0x00000014 + +// Channel 0 Compare Value +#define AON_RTC_O_CH0CMP 0x00000018 + +// Channel 1 Compare Value +#define AON_RTC_O_CH1CMP 0x0000001C + +// Channel 2 Compare Value +#define AON_RTC_O_CH2CMP 0x00000020 + +// Channel 2 Compare Value Auto-increment +#define AON_RTC_O_CH2CMPINC 0x00000024 + +// Channel 1 Capture Value +#define AON_RTC_O_CH1CAPT 0x00000028 + +// AON Synchronization +#define AON_RTC_O_SYNC 0x0000002C + +// Current Counter Value +#define AON_RTC_O_TIME 0x00000030 + +// Synchronization to SCLK_LF +#define AON_RTC_O_SYNCLF 0x00000034 + +//***************************************************************************** +// +// Register: AON_RTC_O_CTL +// +//***************************************************************************** +// Field: [18:16] COMB_EV_MASK +// +// Eventmask selecting which delayed events that form the combined event. +// ENUMs: +// CH2 Use Channel 2 delayed event in combined event +// CH1 Use Channel 1 delayed event in combined event +// CH0 Use Channel 0 delayed event in combined event +// NONE No event is selected for combined event. +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 + +// Field: [11:8] EV_DELAY +// +// Number of SCLK_LF clock cycles waited before generating delayed events. +// (Common setting for all RTC cannels) the delayed event is delayed +// ENUMs: +// D144 Delay by 144 clock cycles +// D128 Delay by 128 clock cycles +// D112 Delay by 112 clock cycles +// D96 Delay by 96 clock cycles +// D80 Delay by 80 clock cycles +// D64 Delay by 64 clock cycles +// D48 Delay by 48 clock cycles +// D32 Delay by 32 clock cycles +// D16 Delay by 16 clock cycles +// D8 Delay by 8 clock cycles +// D4 Delay by 4 clock cycles +// D2 Delay by 2 clock cycles +// D1 Delay by 1 clock cycles +// D0 No delay on delayed event +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 + +// Field: [7] RESET +// +// RTC Counter reset. +// +// Writing 1 to this bit will reset the RTC counter. +// +// This bit is cleared when reset takes effect +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 + +// Field: [2] RTC_4KHZ_EN +// +// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 +// which is used by AUX timer. +// +// 0: RTC_4KHZ signal is forced to 0 +// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 + +// Field: [1] RTC_UPD_EN +// +// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is +// SCLK_LF divided by 2 +// +// 0: RTC_UPD signal is forced to 0 +// 1: RTC_UPD signal is toggling @16 kHz +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 + +// Field: [0] EN +// +// Enable RTC counter +// +// 0: Halted (frozen) +// 1: Running +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_EVFLAGS +// +//***************************************************************************** +// Field: [16] CH2 +// +// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or +// passes the CH2CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH2CMP provided that the channel is enabled and the new value matches any +// time between next RTC value and 1 second in the past +// +// Writing 1 clears this flag. +// +// AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it +// using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 + +// Field: [8] CH1 +// +// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: +// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP +// value. +// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH1CMP provided that the channel is enabled, in compare mode and the new +// value matches any time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 + +// Field: [0] CH0 +// +// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or +// passes the CH0CMP value. +// +// An event will be scheduled to occur as soon as possible when writing to +// CH0CMP provided that the channels is enabled and the new value matches any +// time between next RTC value and 1 second in the past. +// +// Writing 1 clears this flag. +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in seconds. +// +// When reading this register the content of SUBSEC.VALUE is simultaneously +// latched. A consistent reading of the combined Real Time Clock can be +// obtained by first reading this register, then reading SUBSEC register. +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSEC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// Unsigned integer representing Real Time Clock in fractions of a second +// (VALUE/2^32 seconds) at the time when SEC register was read. +// +// Examples : +// - 0x0000_0000 = 0.0 sec +// - 0x4000_0000 = 0.25 sec +// - 0x8000_0000 = 0.5 sec +// - 0xC000_0000 = 0.75 sec +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SUBSECINC +// +//***************************************************************************** +// Field: [23:0] VALUEINC +// +// This value compensates for a SCLK_LF clock which has an offset from 32768 +// Hz. +// +// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF +// clock frequency in Hertz +// +// This value is added to SUBSEC.VALUE on every cycle, and carry of this is +// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with +// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a +// hidden 6-bit register that generates a carry into the above mentioned +// addition on overflow. +// The default value corresponds to incrementing by precisely 1/32768 of a +// second. +// +// NOTE: This register is read only. Modification of the register value must be +// done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and +// AUX_SYSIF:RTCSUBSECINCCTL +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CHCTL +// +//***************************************************************************** +// Field: [18] CH2_CONT_EN +// +// Set to enable continuous operation of Channel 2 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 + +// Field: [16] CH2_EN +// +// RTC Channel 2 Enable +// +// 0: Disable RTC Channel 2 +// 1: Enable RTC Channel 2 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 + +// Field: [9] CH1_CAPT_EN +// +// Set Channel 1 mode +// +// 0: Compare mode (default) +// 1: Capture mode +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 + +// Field: [8] CH1_EN +// +// RTC Channel 1 Enable +// +// 0: Disable RTC Channel 1 +// 1: Enable RTC Channel 1 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 + +// Field: [0] CH0_EN +// +// RTC Channel 0 Enable +// +// 0: Disable RTC Channel 0 +// 1: Enable RTC Channel 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH0CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 0 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 1 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMP +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// RTC Channel 2 compare value. +// +// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of +// the compare value. +// +// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE +// (31:16) values of the Real Time Clock register. A Cannel 0 event is +// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or +// exciting the compare value. +// +// Writing to this register can trigger an immediate*) event in case the new +// compare value matches a Real Time Clock value from 1 second in the past up +// till current Real Time Clock value. +// +// Example: +// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 +// +// *) It can take up to one SCLK_LF clock cycles before event occurs due to +// synchronization. +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH2CMPINC +// +//***************************************************************************** +// Field: [31:0] VALUE +// +// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every +// channel 2 compare event. +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_CH1CAPT +// +//***************************************************************************** +// Field: [31:16] SEC +// +// Value of SEC.VALUE bits 15:0 at capture time. +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 + +// Field: [15:0] SUBSEC +// +// Value of SUBSEC.VALUE bits 31:16 at capture time. +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNC +// +//***************************************************************************** +// Field: [0] WBUSY +// +// This register will always return 0,- however it will not return the value +// until there are no outstanding write requests between MCU and AON +// +// Note: Writing to this register prior to reading will force a wait until next +// SCLK_MF edge. This is recommended for syncing read registers from AON when +// waking up from sleep +// Failure to do so may result in reading AON values from prior to going to +// sleep +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_TIME +// +//***************************************************************************** +// Field: [31:16] SEC_L +// +// Returns the lower halfword of SEC register. +#define AON_RTC_TIME_SEC_L_W 16 +#define AON_RTC_TIME_SEC_L_M 0xFFFF0000 +#define AON_RTC_TIME_SEC_L_S 16 + +// Field: [15:0] SUBSEC_H +// +// Returns the upper halfword of SUBSEC register. +#define AON_RTC_TIME_SUBSEC_H_W 16 +#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF +#define AON_RTC_TIME_SUBSEC_H_S 0 + +//***************************************************************************** +// +// Register: AON_RTC_O_SYNCLF +// +//***************************************************************************** +// Field: [0] PHASE +// +// This bit will always return the SCLK_LF phase. The return will delayed until +// a positive or negative edge of SCLK_LF is seen. +// 0: Falling edge of SCLK_LF +// 1: Rising edge of SCLK_LF +#define AON_RTC_SYNCLF_PHASE 0x00000001 +#define AON_RTC_SYNCLF_PHASE_BITN 0 +#define AON_RTC_SYNCLF_PHASE_M 0x00000001 +#define AON_RTC_SYNCLF_PHASE_S 0 + + +#endif // __AON_RTC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_aiodio.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_aiodio.h new file mode 100644 index 00000000..7f2a5a6f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_aiodio.h @@ -0,0 +1,1030 @@ +/****************************************************************************** +* Filename: hw_aux_aiodio_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_AIODIO_H__ +#define __HW_AUX_AIODIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_AIODIO component +// +//***************************************************************************** +// Input Output Mode +#define AUX_AIODIO_O_IOMODE 0x00000000 + +// General Purpose Input Output Digital Input Enable +#define AUX_AIODIO_O_GPIODIE 0x00000004 + +// Input Output Peripheral Output Enable +#define AUX_AIODIO_O_IOPOE 0x00000008 + +// General Purpose Input Output Data Out +#define AUX_AIODIO_O_GPIODOUT 0x0000000C + +// General Purpose Input Output Data In +#define AUX_AIODIO_O_GPIODIN 0x00000010 + +// General Purpose Input Output Data Out Set +#define AUX_AIODIO_O_GPIODOUTSET 0x00000014 + +// General Purpose Input Output Data Out Clear +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 + +// General Purpose Input Output Data Out Toggle +#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C + +// Input Output 0 Peripheral Select +#define AUX_AIODIO_O_IO0PSEL 0x00000020 + +// Input Output 1 Peripheral Select +#define AUX_AIODIO_O_IO1PSEL 0x00000024 + +// Input Output 2 Peripheral Select +#define AUX_AIODIO_O_IO2PSEL 0x00000028 + +// Input Output 3 Peripheral Select +#define AUX_AIODIO_O_IO3PSEL 0x0000002C + +// Input Output 4 Peripheral Select +#define AUX_AIODIO_O_IO4PSEL 0x00000030 + +// Input Output 5 Peripheral Select +#define AUX_AIODIO_O_IO5PSEL 0x00000034 + +// Input Output 6 Peripheral Select +#define AUX_AIODIO_O_IO6PSEL 0x00000038 + +// Input Output 7 Peripheral Select +#define AUX_AIODIO_O_IO7PSEL 0x0000003C + +// Input Output Mode Low +#define AUX_AIODIO_O_IOMODEL 0x00000040 + +// Input Output Mode High +#define AUX_AIODIO_O_IOMODEH 0x00000044 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODE +// +//***************************************************************************** +// Field: [15:14] IO7 +// +// Selects mode for AUXIO[8i+7]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 7 is 0: +// - If GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is driven high. +// +// When IOPOE bit 7 is 1: +// - If signal selected by +// IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 7 is 0: +// - If GPIODOUT bit 7 is 0: +// AUXIO[8i+7] is driven low. +// - If GPIODOUT bit 7 is 1: +// AUXIO[8i+7] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 7 is 1: +// - If signal selected by +// IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. +// - If signal selected by +// IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 7 is 0: +// AUXIO[8i+7] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 7 is 1: +// AUXIO[8i+7] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 7 is 0: +// GPIODOUT bit 7 drives AUXIO[8i+7]. +// +// When IOPOE bit 7 is 1: +// The signal selected by IO7PSEL.SRC drives +// AUXIO[8i+7]. +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 + +// Field: [13:12] IO6 +// +// Selects mode for AUXIO[8i+6]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 6 is 0: +// - If GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is driven high. +// +// When IOPOE bit 6 is 1: +// - If signal selected by +// IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 6 is 0: +// - If GPIODOUT bit 6 is 0: +// AUXIO[8i+6] is driven low. +// - If GPIODOUT bit 6 is 1: +// AUXIO[8i+6] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 6 is 1: +// - If signal selected by +// IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. +// - If signal selected by +// IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 6 is 0: +// AUXIO[8i+6] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 6 is 1: +// AUXIO[8i+6] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 6 is 0: +// GPIODOUT bit 6 drives AUXIO[8i+6]. +// +// When IOPOE bit 6 is 1: +// The signal selected by IO6PSEL.SRC drives +// AUXIO[8i+6]. +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 + +// Field: [11:10] IO5 +// +// Selects mode for AUXIO[8i+5]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 5 is 0: +// - If GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is driven high. +// +// When IOPOE bit 5 is 1: +// - If signal selected by +// IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 5 is 0: +// - If GPIODOUT bit 5 is 0: +// AUXIO[8i+5] is driven low. +// - If GPIODOUT bit 5 is 1: +// AUXIO[8i+5] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 5 is 1: +// - If signal selected by +// IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. +// - If signal selected by +// IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 5 is 0: +// AUXIO[8i+5] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 5 is 1: +// AUXIO[8i+5] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 5 is 0: +// GPIODOUT bit 5 drives AUXIO[8i+5]. +// +// When IOPOE bit 5 is 1: +// The signal selected by IO5PSEL.SRC drives +// AUXIO[8i+5]. +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 + +// Field: [9:8] IO4 +// +// Selects mode for AUXIO[8i+4]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 4 is 0: +// - If GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is driven high. +// +// When IOPOE bit 4 is 1: +// - If signal selected by +// IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 4 is 0: +// - If GPIODOUT bit 4 is 0: +// AUXIO[8i+4] is driven low. +// - If GPIODOUT bit 4 is 1: +// AUXIO[8i+4] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 4 is 1: +// - If signal selected by +// IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. +// - If signal selected by +// IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 4 is 0: +// AUXIO[8i+4] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 4 is 1: +// AUXIO[8i+4] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 4 is 0: +// GPIODOUT bit 4 drives AUXIO[8i+4]. +// +// When IOPOE bit 4 is 1: +// The signal selected by IO4PSEL.SRC drives +// AUXIO[8i+4]. +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 + +// Field: [7:6] IO3 +// +// Selects mode for AUXIO[8i+3]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 3 is 0: +// - If GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is driven high. +// +// When IOPOE bit 3 is 1: +// - If signal selected by +// IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 3 is 0: +// - If GPIODOUT bit 3 is 0: +// AUXIO[8i+3] is driven low. +// - If GPIODOUT bit 3 is 1: +// AUXIO[8i+3] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 3 is 1: +// - If signal selected by +// IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. +// - If signal selected by +// IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 3 is 0: +// AUXIO[8i+3] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 3 is 1: +// AUXIO[8i+3] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 3 is 0: +// GPIODOUT bit 3 drives AUXIO[8i+3]. +// +// When IOPOE bit 3 is 1: +// The signal selected by IO3PSEL.SRC drives +// AUXIO[8i+3]. +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 + +// Field: [5:4] IO2 +// +// Select mode for AUXIO[8i+2]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 2 is 0: +// - If GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is driven high. +// +// When IOPOE bit 2 is 1: +// - If signal selected by +// IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 2 is 0: +// - If GPIODOUT bit 2 is 0: +// AUXIO[8i+2] is driven low. +// - If GPIODOUT bit 2 is 1: +// AUXIO[8i+2] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 2 is 1: +// - If signal selected by +// IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. +// - If signal selected by +// IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 2 is 0: +// AUXIO[8i+2] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 2 is 1: +// AUXIO[8i+2] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 2 is 0: +// GPIODOUT bit 2 drives AUXIO[8i+2]. +// +// When IOPOE bit 2 is 1: +// The signal selected by IO2PSEL.SRC drives +// AUXIO[8i+2]. +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 + +// Field: [3:2] IO1 +// +// Select mode for AUXIO[8i+1]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 1 is 0: +// - If GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is driven high. +// +// When IOPOE bit 1 is 1: +// - If signal selected by +// IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 1 is 0: +// - If GPIODOUT bit 1 is 0: +// AUXIO[8i+1] is driven low. +// - If GPIODOUT bit 1 is 1: +// AUXIO[8i+1] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 1 is 1: +// - If signal selected by +// IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. +// - If signal selected by +// IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 1 is 0: +// AUXIO[8i+1] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 1 is 1: +// AUXIO[8i+1] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 1 is 0: +// GPIODOUT bit 1 drives AUXIO[8i+1]. +// +// When IOPOE bit 1 is 1: +// The signal selected by IO1PSEL.SRC drives +// AUXIO[8i+1]. +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 + +// Field: [1:0] IO0 +// +// Select mode for AUXIO[8i+0]. +// ENUMs: +// OPEN_SOURCE Open-Source Mode: +// +// When IOPOE bit 0 is 0: +// - If GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// - If GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is driven high. +// +// When IOPOE bit 0 is 1: +// - If signal selected by +// IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// - If signal selected by +// IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. +// OPEN_DRAIN Open-Drain Mode: +// +// When IOPOE bit 0 is 0: +// - If GPIODOUT bit 0 is 0: +// AUXIO[8i+0] is driven low. +// - If GPIODOUT bit 0 is 1: +// AUXIO[8i+0] is tri-stated or pulled. This +// depends on IOC:IOCFGn.PULL_CTL. +// +// When IOPOE bit 0 is 1: +// - If signal selected by +// IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. +// - If signal selected by +// IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or +// pulled. This depends on IOC:IOCFGn.PULL_CTL. +// IN Input Mode: +// +// When GPIODIE bit 0 is 0: +// AUXIO[8i+0] is enabled for analog signal +// transfer. +// +// When GPIODIE bit 0 is 1: +// AUXIO[8i+0] is enabled for digital input. +// OUT Output Mode: +// +// When IOPOE bit 0 is 0: +// GPIODOUT bit 0 drives AUXIO[8i+0]. +// +// When IOPOE bit 0 is 1: +// The signal selected by IO0PSEL.SRC drives +// AUXIO[8i+0]. +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to enable digital input buffer for +// AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to disable digital input buffer +// for AUXIO[8i+n]. +// +// You must enable the digital input buffer for AUXIO[8i+n] to read the pin +// value in GPIODIN. +// You must disable the digital input buffer for analog input or pins that +// float to avoid current leakage. +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOPOE +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be +// driven from source given in [IOnPSEL.*]. +// Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be +// driven from bit n in GPIODOUT. +#define AUX_AIODIO_IOPOE_IO7_0_W 8 +#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF +#define AUX_AIODIO_IOPOE_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUT +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. +// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. +// +// You must clear bit n in IOPOE to connect bit n in this bit vector to +// AUXIO[8i+n]. +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODIN +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit +// n is set. Otherwise, bit n is read as 0. +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTSET +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTCLR +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_GPIODOUTTGL +// +//***************************************************************************** +// Field: [7:0] IO7_0 +// +// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. +// +// Read value is 0. +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO0PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO0PSEL_SRC_W 3 +#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_S 0 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO1PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO1PSEL_SRC_W 3 +#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_S 0 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO2PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO2PSEL_SRC_W 3 +#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_S 0 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO3PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO3PSEL_SRC_W 3 +#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_S 0 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO4PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO4PSEL_SRC_W 3 +#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_S 0 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO5PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO5PSEL_SRC_W 3 +#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_S 0 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO6PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO6PSEL_SRC_W 3 +#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_S 0 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IO7PSEL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is +// set. +// ENUMs: +// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. +// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. +// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. +// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. +// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version +// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. +// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. +// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. +// AUX_EV_OBS Peripheral output mux selects event selected by +// AUX_EVCTL:EVOBSCFG +#define AUX_AIODIO_IO7PSEL_SRC_W 3 +#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_S 0 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODEL +// +//***************************************************************************** +// Field: [7:6] IO3 +// +// See IOMODE.IO3. +#define AUX_AIODIO_IOMODEL_IO3_W 2 +#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODEL_IO3_S 6 + +// Field: [5:4] IO2 +// +// See IOMODE.IO2. +#define AUX_AIODIO_IOMODEL_IO2_W 2 +#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODEL_IO2_S 4 + +// Field: [3:2] IO1 +// +// See IOMODE.IO1. +#define AUX_AIODIO_IOMODEL_IO1_W 2 +#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODEL_IO1_S 2 + +// Field: [1:0] IO0 +// +// See IOMODE.IO0. +#define AUX_AIODIO_IOMODEL_IO0_W 2 +#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODEL_IO0_S 0 + +//***************************************************************************** +// +// Register: AUX_AIODIO_O_IOMODEH +// +//***************************************************************************** +// Field: [7:6] IO7 +// +// See IOMODE.IO7. +#define AUX_AIODIO_IOMODEH_IO7_W 2 +#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 +#define AUX_AIODIO_IOMODEH_IO7_S 6 + +// Field: [5:4] IO6 +// +// See IOMODE.IO6. +#define AUX_AIODIO_IOMODEH_IO6_W 2 +#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 +#define AUX_AIODIO_IOMODEH_IO6_S 4 + +// Field: [3:2] IO5 +// +// See IOMODE.IO5. +#define AUX_AIODIO_IOMODEH_IO5_W 2 +#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C +#define AUX_AIODIO_IOMODEH_IO5_S 2 + +// Field: [1:0] IO4 +// +// See IOMODE.IO4. +#define AUX_AIODIO_IOMODEH_IO4_W 2 +#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 +#define AUX_AIODIO_IOMODEH_IO4_S 0 + + +#endif // __AUX_AIODIO__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_anaif.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_anaif.h new file mode 100644 index 00000000..1605e589 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_anaif.h @@ -0,0 +1,632 @@ +/****************************************************************************** +* Filename: hw_aux_anaif_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_ANAIF_H__ +#define __HW_AUX_ANAIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_ANAIF component +// +//***************************************************************************** +// ADC Control +#define AUX_ANAIF_O_ADCCTL 0x00000010 + +// ADC FIFO Status +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 + +// ADC FIFO +#define AUX_ANAIF_O_ADCFIFO 0x00000018 + +// ADC Trigger +#define AUX_ANAIF_O_ADCTRIG 0x0000001C + +// Current Source Control +#define AUX_ANAIF_O_ISRCCTL 0x00000020 + +// DAC Control +#define AUX_ANAIF_O_DACCTL 0x00000030 + +// Low Power Mode Bias Control +#define AUX_ANAIF_O_LPMBIASCTL 0x00000034 + +// DAC Sample Control +#define AUX_ANAIF_O_DACSMPLCTL 0x00000038 + +// DAC Sample Configuration 0 +#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C + +// DAC Sample Configuration 1 +#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 + +// DAC Value +#define AUX_ANAIF_O_DACVALUE 0x00000044 + +// DAC Status +#define AUX_ANAIF_O_DACSTAT 0x00000048 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCCTL +// +//***************************************************************************** +// Field: [14] START_POL +// +// Select active polarity for START_SRC event. +// ENUMs: +// FALL Set ADC trigger on falling edge of event source. +// RISE Set ADC trigger on rising edge of event source. +#define AUX_ANAIF_ADCCTL_START_POL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 14 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_S 14 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 + +// Field: [13:8] START_SRC +// +// Select ADC trigger event source from the asynchronous AUX event bus. +// +// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through +// ADCTRIG.START. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_ANAIF_ADCCTL_START_SRC_W 6 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 +#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 +#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 +#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 +#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 + +// Field: [1:0] CMD +// +// ADC interface command. +// +// Non-enumerated values are not supported. The written value is returned when +// read. +// ENUMs: +// FLUSH Flush ADC FIFO. +// +// You must set CMD to EN or +// DIS after flush. +// +// System CPU must wait two +// clock cycles before it sets CMD to EN or DIS. +// EN Enable ADC interface. +// DIS Disable ADC interface. +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFOSTAT +// +//***************************************************************************** +// Field: [4] OVERFLOW +// +// FIFO overflow flag. +// +// 0: FIFO has not overflowed. +// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO write pointer is static. It is not +// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 + +// Field: [3] UNDERFLOW +// +// FIFO underflow flag. +// +// 0: FIFO has not underflowed. +// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. +// +// When the flag is set, the ADC FIFO read pointer is static. Read returns the +// previous sample that was read. Flush FIFO to clear the flag. +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 + +// Field: [2] FULL +// +// FIFO full flag. +// +// 0: FIFO is not full, there is less than 4 samples in the FIFO. +// 1: FIFO is full, there are 4 samples in the FIFO. +// +// When the flag is set, it is not possible to add more samples to the ADC +// FIFO. An attempt to add samples sets the OVERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 + +// Field: [1] ALMOST_FULL +// +// FIFO almost full flag. +// +// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL +// flag is also asserted in the latter case. +// 1: There are 3 samples in the FIFO, there is room for one more sample. +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 + +// Field: [0] EMPTY +// +// FIFO empty flag. +// +// 0: FIFO contains one or more samples. +// 1: FIFO is empty. +// +// When the flag is set, read returns the previous sample that was read and +// sets the UNDERFLOW flag. +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCFIFO +// +//***************************************************************************** +// Field: [11:0] DATA +// +// FIFO data. +// +// Read: +// Get oldest ADC sample from FIFO. +// +// Write: +// Write dummy sample to FIFO. This is useful for code development when you do +// not have real ADC samples. +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ADCTRIG +// +//***************************************************************************** +// Field: [0] START +// +// Manual ADC trigger. +// +// Write any value to START to trigger ADC. +// +// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to +// avoid conflict with event-driven ADC trigger. +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_ISRCCTL +// +//***************************************************************************** +// Field: [0] RESET_N +// +// ISRC reset control. +// +// 0: ISRC drives 0 uA. +// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACCTL +// +//***************************************************************************** +// Field: [5] DAC_EN +// +// DAC module enable. +// +// 0: Disable DAC. +// 1: Enable DAC. +// +// The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ +// equals PDA. +// +// The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA +// in Standby TI-RTOS power mode. The System CPU must set +// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active +// and Idle TI-RTOS power modes. +#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 +#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_S 5 + +// Field: [4] DAC_BUFFER_EN +// +// DAC buffer enable. +// +// DAC buffer reduces the time required to produce the programmed voltage at +// the expense of increased current consumption. +// +// 0: Disable DAC buffer. +// 1: Enable DAC buffer. +// +// Enable buffer when DAC_VOUT_SEL equals COMPA_IN. +// +// Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 + +// Field: [3] DAC_PRECHARGE_EN +// +// DAC precharge enable. +// +// Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and +// VDDS is higher than 2.65 V. +// +// DAC output voltage range: +// +// 0: 0 V to 1.28 V. +// 1: 1.28 V to 2.56 V. +// +// Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. +// +// Enable precharge 1 us before you enable the DAC and the buffer. +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 + +// Field: [2:0] DAC_VOUT_SEL +// +// DAC output connection. +// +// An analog node must only have one driver. Other drivers for the following +// analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. +// ENUMs: +// COMPA_IN Connect to COMPA_IN analog node. +// +// Required setting to drive +// external load selected in +// ADI_4_AUX:MUX1.COMPA_IN. +// COMPA_REF Connect to COMPA_REF analog node. +// +// It is not possible to +// drive external loads connected to COMPA_REF I/O +// mux with this setting. +// COMPB_REF Connect to COMPB_REF analog node. +// +// Required setting to use +// Comparator B. +// NC Connect to nothing +// +// It is recommended to use +// NC as intermediate step when you change +// DAC_VOUT_SEL. +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_LPMBIASCTL +// +//***************************************************************************** +// Field: [0] EN +// +// Module enable. +// +// 0: Disable low power mode bias module. +// 1: Enable low power mode bias module. +// +// Set EN to 1 15 us before you enable the DAC or Comparator A. +#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 +#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCTL +// +//***************************************************************************** +// Field: [0] EN +// +// DAC sample clock enable. +// +// 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 +// when the current sample clock period completes. +// 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample +// clock. +#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 +#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCFG0 +// +//***************************************************************************** +// Field: [5:0] CLKDIV +// +// Clock division. +// +// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the +// sample clock base frequency. +// +// 0: Divide by 1. +// 1: Divide by 2. +// ... +// 63: Divide by 64. +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSMPLCFG1 +// +//***************************************************************************** +// Field: [14] H_PER +// +// High time. +// +// The sample clock period is high for this many base periods. +// +// 0: 2 periods +// 1: 4 periods +#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 + +// Field: [13:12] L_PER +// +// Low time. +// +// The sample clock period is low for this many base periods. +// +// 0: 1 period +// 1: 2 periods +// 2: 3 periods +// 3: 4 periods +#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 + +// Field: [11:8] SETUP_CNT +// +// Setup count. +// +// Number of active sample clock periods during the setup phase. +// +// 0: 1 sample clock period +// 1: 2 sample clock periods +// ... +// 15 : 16 sample clock periods +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 + +// Field: [7:0] HOLD_INTERVAL +// +// Hold interval. +// +// Number of inactive sample clock periods between each active sample clock +// period during hold phase. The sample clock is low when inactive. +// +// The range is 0 to 255. +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACVALUE +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// DAC value. +// +// Digital data word for the DAC. +// +// Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable +// the DAC. +#define AUX_ANAIF_DACVALUE_VALUE_W 8 +#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF +#define AUX_ANAIF_DACVALUE_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_ANAIF_O_DACSTAT +// +//***************************************************************************** +// Field: [1] SETUP_ACTIVE +// +// DAC setup phase status. +// +// 0: Sample clock is disabled or setup phase is complete. +// 1: Setup phase in progress. +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 + +// Field: [0] HOLD_ACTIVE +// +// DAC hold phase status. +// +// 0: Sample clock is disabled or DAC is not in hold phase. +// 1: Hold phase in progress. +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 + + +#endif // __AUX_ANAIF__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_evctl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_evctl.h new file mode 100644 index 00000000..d37a872b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_evctl.h @@ -0,0 +1,2355 @@ +/****************************************************************************** +* Filename: hw_aux_evctl_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_EVCTL_H__ +#define __HW_AUX_EVCTL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_EVCTL component +// +//***************************************************************************** +// Event Status 0 +#define AUX_EVCTL_O_EVSTAT0 0x00000000 + +// Event Status 1 +#define AUX_EVCTL_O_EVSTAT1 0x00000004 + +// Event Status 2 +#define AUX_EVCTL_O_EVSTAT2 0x00000008 + +// Event Status 3 +#define AUX_EVCTL_O_EVSTAT3 0x0000000C + +// Sensor Controller Engine Wait Event Configuration 0 +#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010 + +// Sensor Controller Engine Wait Event Configuration 1 +#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014 + +// Direct Memory Access Control +#define AUX_EVCTL_O_DMACTL 0x00000018 + +// Software Event Set +#define AUX_EVCTL_O_SWEVSET 0x00000020 + +// Events To AON Flags +#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024 + +// Events To AON Polarity +#define AUX_EVCTL_O_EVTOAONPOL 0x00000028 + +// Events To AON Clear +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C + +// Events to MCU Flags +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030 + +// Event To MCU Polarity +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034 + +// Events To MCU Flags Clear +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 + +// Combined Event To MCU Mask +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C + +// Event Observation Configuration +#define AUX_EVCTL_O_EVOBSCFG 0x00000040 + +// Programmable Delay +#define AUX_EVCTL_O_PROGDLY 0x00000044 + +// Manual +#define AUX_EVCTL_O_MANUAL 0x00000048 + +// Event Status 0 Low +#define AUX_EVCTL_O_EVSTAT0L 0x0000004C + +// Event Status 0 High +#define AUX_EVCTL_O_EVSTAT0H 0x00000050 + +// Event Status 1 Low +#define AUX_EVCTL_O_EVSTAT1L 0x00000054 + +// Event Status 1 High +#define AUX_EVCTL_O_EVSTAT1H 0x00000058 + +// Event Status 2 Low +#define AUX_EVCTL_O_EVSTAT2L 0x0000005C + +// Event Status 2 High +#define AUX_EVCTL_O_EVSTAT2H 0x00000060 + +// Event Status 3 Low +#define AUX_EVCTL_O_EVSTAT3L 0x00000064 + +// Event Status 3 High +#define AUX_EVCTL_O_EVSTAT3H 0x00000068 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0 +// +//***************************************************************************** +// Field: [15] AUXIO15 +// +// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15 + +// Field: [14] AUXIO14 +// +// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14 + +// Field: [13] AUXIO13 +// +// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13 + +// Field: [12] AUXIO12 +// +// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12 +#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12 + +// Field: [11] AUXIO11 +// +// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11 +#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11 + +// Field: [10] AUXIO10 +// +// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10 +#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10 + +// Field: [9] AUXIO9 +// +// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9 +#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9 + +// Field: [8] AUXIO8 +// +// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8 +#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8 + +// Field: [7] AUXIO7 +// +// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7 +#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7 + +// Field: [6] AUXIO6 +// +// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6 +#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6 + +// Field: [5] AUXIO5 +// +// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5 +#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5 + +// Field: [4] AUXIO4 +// +// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4 +#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4 + +// Field: [3] AUXIO3 +// +// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3 +#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3 + +// Field: [2] AUXIO2 +// +// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2 + +// Field: [1] AUXIO1 +// +// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1 + +// Field: [0] AUXIO0 +// +// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1 +// +//***************************************************************************** +// Field: [15] AUXIO31 +// +// AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15 +#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15 + +// Field: [14] AUXIO30 +// +// AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14 +#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14 + +// Field: [13] AUXIO29 +// +// AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13 +#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13 + +// Field: [12] AUXIO28 +// +// AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12 + +// Field: [11] AUXIO27 +// +// AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11 + +// Field: [10] AUXIO26 +// +// AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10 + +// Field: [9] AUXIO25 +// +// AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9 + +// Field: [8] AUXIO24 +// +// AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8 + +// Field: [7] AUXIO23 +// +// AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. +#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7 + +// Field: [6] AUXIO22 +// +// AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. +#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6 + +// Field: [5] AUXIO21 +// +// AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. +#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5 + +// Field: [4] AUXIO20 +// +// AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. +#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4 + +// Field: [3] AUXIO19 +// +// AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. +#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3 + +// Field: [2] AUXIO18 +// +// AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. +#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2 + +// Field: [1] AUXIO17 +// +// AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. +#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1 + +// Field: [0] AUXIO16 +// +// AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. +#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2 +// +//***************************************************************************** +// Field: [15] AUX_COMPB +// +// Comparator B output. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15 + +// Field: [14] AUX_COMPA +// +// Comparator A output. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14 + +// Field: [13] MCU_OBSMUX1 +// +// Observation input 1 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL1. +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13 + +// Field: [12] MCU_OBSMUX0 +// +// Observation input 0 from IOC. +// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by +// IOC:OBSAUXOUTPUT.SEL_MISC. +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12 + +// Field: [11] MCU_EV +// +// Event from EVENT configured by EVENT:AUXSEL0. +#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11 +#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11 + +// Field: [10] ACLK_REF +// +// TDC reference clock. +// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by +// AUX_SYSIF:TDCREFCLKCTL.REQ. +#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10 + +// Field: [9] VDDR_RECHARGE +// +// Event is high during VDDR recharge. +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9 + +// Field: [8] MCU_ACTIVE +// +// Event is high while system(MCU, AUX, or JTAG domains) is active or +// transitions to active (GLDO or DCDC power supply state). Event is not high +// during VDDR recharge. +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8 + +// Field: [7] PWR_DWN +// +// Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO +// power supply). +#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7 + +// Field: [6] SCLK_LF +// +// SCLK_LF clock +#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6 + +// Field: [5] AON_BATMON_TEMP_UPD +// +// Event is high for two SCLK_MF clock periods when there is an update of +// AON_BATMON:TEMP. +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5 + +// Field: [4] AON_BATMON_BAT_UPD +// +// Event is high for two SCLK_MF clock periods when there is an update of +// AON_BATMON:BAT. +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4 + +// Field: [3] AON_RTC_4KHZ +// +// AON_RTC:SUBSEC.VALUE bit 19. +// AON_RTC:CTL.RTC_4KHZ_EN enables this event. +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3 + +// Field: [2] AON_RTC_CH2_DLY +// +// AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2 + +// Field: [1] AON_RTC_CH2 +// +// AON_RTC:EVFLAGS.CH2. +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1 + +// Field: [0] MANUAL_EV +// +// Programmable event. See MANUAL for description. +#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3 +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_CLKSWITCH_RDY +// +// AUX_SYSIF:TIMER2CLKSWITCH.RDY +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15 + +// Field: [14] AUX_DAC_HOLD_ACTIVE +// +// AUX_ANAIF:DACSTAT.HOLD_ACTIVE +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14 + +// Field: [13] AUX_SMPH_AUTOTAKE_DONE +// +// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13 + +// Field: [12] AUX_ADC_FIFO_NOT_EMPTY +// +// AUX_ANAIF:ADCFIFOSTAT.EMPTY negated +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12 + +// Field: [11] AUX_ADC_FIFO_ALMOST_FULL +// +// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// The logical function for this event is configurable. +// +// When DMACTL.EN = 1 : +// Event = UDMA0 Channel 7 done event OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// When DMACTL.EN = 0 : +// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR +// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW +// +// Bit 7 in UDMA0:DONEMASK must be 0. +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10 + +// Field: [9] AUX_ADC_DONE +// +// AUX_ANAIF ADC conversion done event. +// Event is synchronized at AUX bus rate. +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9 + +// Field: [8] AUX_ISRC_RESET_N +// +// AUX_ANAIF:ISRCCTL.RESET_N +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8 + +// Field: [7] AUX_TDC_DONE +// +// AUX_TDC:STAT.DONE +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7 + +// Field: [6] AUX_TIMER0_EV +// +// AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER2_PULSE +// +// AUX_TIMER2 pulse event. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4 + +// Field: [3] AUX_TIMER2_EV3 +// +// AUX_TIMER2 event output 3. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3 + +// Field: [2] AUX_TIMER2_EV2 +// +// AUX_TIMER2 event output 2. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2 + +// Field: [1] AUX_TIMER2_EV1 +// +// AUX_TIMER2 event output 1. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1 + +// Field: [0] AUX_TIMER2_EV0 +// +// AUX_TIMER2 event output 0. +// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the +// synchronization rate for this event. +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVCFG0 +// +//***************************************************************************** +// Field: [6] COMB_EV_EN +// +// Event combination control: +// +// 0: Disable event combination. +// 1: Enable event combination. +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6 + +// Field: [5:0] EV0_SEL +// +// Select the event source from the synchronous event bus to be used in event +// equation. +// ENUMs: +// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SCEWEVCFG1 +// +//***************************************************************************** +// Field: [7] EV0_POL +// +// Polarity of SCEWEVCFG0.EV0_SEL event. +// +// When SCEWEVCFG0.COMB_EV_EN is 0: +// +// 0: Non-inverted. +// 1: Non-inverted. +// +// When SCEWEVCFG0.COMB_EV_EN is 1. +// +// 0: Non-inverted. +// 1: Inverted. +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7 + +// Field: [6] EV1_POL +// +// Polarity of EV1_SEL event. +// +// When SCEWEVCFG0.COMB_EV_EN is 0: +// +// 0: Non-inverted. +// 1: Non-inverted. +// +// When SCEWEVCFG0.COMB_EV_EN is 1. +// +// 0: Non-inverted. +// 1: Inverted. +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6 + +// Field: [5:0] EV1_SEL +// +// Select the event source from the synchronous event bus to be used in event +// equation. +// ENUMs: +// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_DMACTL +// +//***************************************************************************** +// Field: [2] REQ_MODE +// +// UDMA0 Request mode +// ENUMs: +// SINGLE Single requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +// BURST Burst requests are generated on UDMA0 channel 7 +// when the condition configured in SEL is met. +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 + +// Field: [1] EN +// +// uDMA ADC interface enable. +// +// 0: Disable UDMA0 interface to ADC. +// 1: Enable UDMA0 interface to ADC. +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 + +// Field: [0] SEL +// +// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO +// data. +// ENUMs: +// AUX_ADC_FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC +// FIFO is almost full (3/4 full). +// AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there +// are samples in the ADC FIFO. +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_SWEVSET +// +//***************************************************************************** +// Field: [2] SWEV2 +// +// Software event flag 2. +// +// 0: No effect. +// 1: Set software event flag 2. +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Software event flag 1. +// +// 0: No effect. +// 1: Set software event flag 1. +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Software event flag 0. +// +// 0: No effect. +// 1: Set software event flag 0. +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGS +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV +// occurs on EVSTAT3.AUX_TIMER1_EV. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8 + +// Field: [7] AUX_TIMER0_EV +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV +// occurs on EVSTAT3.AUX_TIMER0_EV. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7 + +// Field: [6] AUX_TDC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs +// on EVSTAT3.AUX_TDC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6 + +// Field: [5] AUX_ADC_DONE +// +// This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs +// on EVSTAT3.AUX_ADC_DONE. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on +// EVSTAT2.AUX_COMPB. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on +// EVSTAT2.AUX_COMPA. +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV2. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV1. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// This event flag is set when software writes a 1 to SWEVSET.SWEV0. +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONPOL +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// Select the level of EVSTAT3.AUX_TIMER1_EV that sets +// EVTOAONFLAGS.AUX_TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000 + +// Field: [7] AUX_TIMER0_EV +// +// Select the level of EVSTAT3.AUX_TIMER0_EV that sets +// EVTOAONFLAGS.AUX_TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000 + +// Field: [6] AUX_TDC_DONE +// +// Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000 + +// Field: [5] AUX_ADC_DONE +// +// Select the level of EVSTAT3.AUX_ADC_DONE that sets +// EVTOAONFLAGS.AUX_ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000 + +// Field: [4] AUX_COMPB +// +// Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000 + +// Field: [3] AUX_COMPA +// +// Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR +// +//***************************************************************************** +// Field: [8] AUX_TIMER1_EV +// +// Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8 + +// Field: [7] AUX_TIMER0_EV +// +// Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7 + +// Field: [6] AUX_TDC_DONE +// +// Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6 + +// Field: [5] AUX_ADC_DONE +// +// Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5 + +// Field: [4] AUX_COMPB +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 + +// Field: [3] AUX_COMPA +// +// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 + +// Field: [2] SWEV2 +// +// Write 1 to clear EVTOAONFLAGS.SWEV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 + +// Field: [1] SWEV1 +// +// Write 1 to clear EVTOAONFLAGS.SWEV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 + +// Field: [0] SWEV0 +// +// Write 1 to clear EVTOAONFLAGS.SWEV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGS +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE +// occurs on EVSTAT3.AUX_TIMER2_PULSE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 +// occurs on EVSTAT3.AUX_TIMER2_EV3. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 +// occurs on EVSTAT3.AUX_TIMER2_EV2. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 +// occurs on EVSTAT3.AUX_TIMER2_EV1. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 +// occurs on EVSTAT3.AUX_TIMER2_EV0. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs +// on EVSTAT3.AUX_ADC_IRQ. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs +// on EVSTAT2.MCU_OBSMUX0. +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// This event flag is set when level selected by +// EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on +// EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs +// on EVSTAT3.AUX_ADC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// This event flag is set when level selected by +// EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV +// occurs on EVSTAT3.AUX_TIMER1_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV +// occurs on EVSTAT3.AUX_TIMER0_EV. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs +// on EVSTAT3.AUX_TDC_DONE. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on +// EVSTAT2.AUX_COMPB. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on +// EVSTAT2.AUX_COMPA. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on +// reduction-OR of the AUX_SYSIF:WUFLAGS register. +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUPOL +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000 + +// Field: [14] AUX_TIMER2_EV3 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000 + +// Field: [13] AUX_TIMER2_EV2 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000 + +// Field: [12] AUX_TIMER2_EV1 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000 + +// Field: [11] AUX_TIMER2_EV0 +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000 + +// Field: [10] AUX_ADC_IRQ +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000 + +// Field: [9] MCU_OBSMUX0 +// +// Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// Select the event source level that sets +// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 + +// Field: [7] AUX_ADC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 + +// Field: [5] AUX_TIMER1_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000 + +// Field: [4] AUX_TIMER0_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000 + +// Field: [3] AUX_TDC_DONE +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000 + +// Field: [2] AUX_COMPB +// +// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000 + +// Field: [1] AUX_COMPA +// +// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA. +// ENUMs: +// FALL Falling edge +// RISE Rising edge +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000 + +// Field: [0] AUX_WU_EV +// +// Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV. +// ENUMs: +// LOW Low level +// HIGH High level +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. +// +// Read value is 0. +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_COMBEVTOMCUMASK +// +//***************************************************************************** +// Field: [15] AUX_TIMER2_PULSE +// +// EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15 + +// Field: [14] AUX_TIMER2_EV3 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14 + +// Field: [13] AUX_TIMER2_EV2 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13 + +// Field: [12] AUX_TIMER2_EV1 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12 + +// Field: [11] AUX_TIMER2_EV0 +// +// EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11 + +// Field: [10] AUX_ADC_IRQ +// +// EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10 + +// Field: [9] MCU_OBSMUX0 +// +// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9 + +// Field: [8] AUX_ADC_FIFO_ALMOST_FULL +// +// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8 + +// Field: [7] AUX_ADC_DONE +// +// EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7 + +// Field: [6] AUX_SMPH_AUTOTAKE_DONE +// +// EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6 + +// Field: [5] AUX_TIMER1_EV +// +// EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5 + +// Field: [4] AUX_TIMER0_EV +// +// EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4 + +// Field: [3] AUX_TDC_DONE +// +// EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3 + +// Field: [2] AUX_COMPB +// +// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. +// +// 0: Exclude +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 + +// Field: [1] AUX_COMPA +// +// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 + +// Field: [0] AUX_WU_EV +// +// EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event. +// +// 0: Exclude. +// 1: Include. +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVOBSCFG +// +//***************************************************************************** +// Field: [5:0] EVOBS_SEL +// +// Select which event from the asynchronous event bus that represents +// AUX_EV_OBS in AUX_AIODIOn. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB EVSTAT2.AUX_COMPB +// AUX_COMPA EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 +// MCU_EV EVSTAT2.MCU_EV +// ACLK_REF EVSTAT2.ACLK_REF +// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE EVSTAT2.MCU_ACTIVE +// PWR_DWN EVSTAT2.PWR_DWN +// SCLK_LF EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 +// MANUAL_EV EVSTAT2.MANUAL_EV +// AUXIO31 EVSTAT1.AUXIO31 +// AUXIO30 EVSTAT1.AUXIO30 +// AUXIO29 EVSTAT1.AUXIO29 +// AUXIO28 EVSTAT1.AUXIO28 +// AUXIO27 EVSTAT1.AUXIO27 +// AUXIO26 EVSTAT1.AUXIO26 +// AUXIO25 EVSTAT1.AUXIO25 +// AUXIO24 EVSTAT1.AUXIO24 +// AUXIO23 EVSTAT1.AUXIO23 +// AUXIO22 EVSTAT1.AUXIO22 +// AUXIO21 EVSTAT1.AUXIO21 +// AUXIO20 EVSTAT1.AUXIO20 +// AUXIO19 EVSTAT1.AUXIO19 +// AUXIO18 EVSTAT1.AUXIO18 +// AUXIO17 EVSTAT1.AUXIO17 +// AUXIO16 EVSTAT1.AUXIO16 +// AUXIO15 EVSTAT0.AUXIO15 +// AUXIO14 EVSTAT0.AUXIO14 +// AUXIO13 EVSTAT0.AUXIO13 +// AUXIO12 EVSTAT0.AUXIO12 +// AUXIO11 EVSTAT0.AUXIO11 +// AUXIO10 EVSTAT0.AUXIO10 +// AUXIO9 EVSTAT0.AUXIO9 +// AUXIO8 EVSTAT0.AUXIO8 +// AUXIO7 EVSTAT0.AUXIO7 +// AUXIO6 EVSTAT0.AUXIO6 +// AUXIO5 EVSTAT0.AUXIO5 +// AUXIO4 EVSTAT0.AUXIO4 +// AUXIO3 EVSTAT0.AUXIO3 +// AUXIO2 EVSTAT0.AUXIO2 +// AUXIO1 EVSTAT0.AUXIO1 +// AUXIO0 EVSTAT0.AUXIO0 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_PROGDLY +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// VALUE decrements to 0 at a rate of 1 MHz. +// +// The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low. +// +// Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when +// AUX_SYSIF:OPMODEACK.ACK equals A or LP. +// +// Decrementation of VALUE halts when either is true: +// - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. +// - AUX_SYSIF:TIMERHALT.PROGDLY is set. +#define AUX_EVCTL_PROGDLY_VALUE_W 16 +#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF +#define AUX_EVCTL_PROGDLY_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_MANUAL +// +//***************************************************************************** +// Field: [0] EV +// +// This bit field sets the value of EVSTAT2.MANUAL_EV. +#define AUX_EVCTL_MANUAL_EV 0x00000001 +#define AUX_EVCTL_MANUAL_EV_BITN 0 +#define AUX_EVCTL_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_MANUAL_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT0 event 7 down to 0. +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT0H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT0 event 15 down to 8. +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT1 event 7 down to 0. +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT1H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT1 event 15 down to 8. +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT2 event 7 down to 0. +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT2H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT2 event 15 down to 8. +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3L +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT3 event 7 down to 0. +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0 + +//***************************************************************************** +// +// Register: AUX_EVCTL_O_EVSTAT3H +// +//***************************************************************************** +// Field: [7:0] ALIAS_EV +// +// Alias of EVSTAT3 event 15 down to 8. +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0 + + +#endif // __AUX_EVCTL__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_mac.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_mac.h new file mode 100644 index 00000000..85213be6 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_mac.h @@ -0,0 +1,748 @@ +/****************************************************************************** +* Filename: hw_aux_mac_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_MAC_H__ +#define __HW_AUX_MAC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_MAC component +// +//***************************************************************************** +// Signed Operand 0 +#define AUX_MAC_O_OP0S 0x00000000 + +// Unsigned Operand 0 +#define AUX_MAC_O_OP0U 0x00000004 + +// Signed Operand 1 and Multiply +#define AUX_MAC_O_OP1SMUL 0x00000008 + +// Unsigned Operand 1 and Multiply +#define AUX_MAC_O_OP1UMUL 0x0000000C + +// Signed Operand 1 and Multiply-Accumulate +#define AUX_MAC_O_OP1SMAC 0x00000010 + +// Unsigned Operand 1 and Multiply-Accumulate +#define AUX_MAC_O_OP1UMAC 0x00000014 + +// Signed Operand 1 and 16-bit Addition +#define AUX_MAC_O_OP1SADD16 0x00000018 + +// Unsigned Operand 1 and 16-bit Addition +#define AUX_MAC_O_OP1UADD16 0x0000001C + +// Signed Operand 1 and 32-bit Addition +#define AUX_MAC_O_OP1SADD32 0x00000020 + +// Unsigned Operand 1 and 32-bit Addition +#define AUX_MAC_O_OP1UADD32 0x00000024 + +// Count Leading Zero +#define AUX_MAC_O_CLZ 0x00000028 + +// Count Leading Sign +#define AUX_MAC_O_CLS 0x0000002C + +// Accumulator Shift +#define AUX_MAC_O_ACCSHIFT 0x00000030 + +// Accumulator Reset +#define AUX_MAC_O_ACCRESET 0x00000034 + +// Accumulator Bits 15:0 +#define AUX_MAC_O_ACC15_0 0x00000038 + +// Accumulator Bits 16:1 +#define AUX_MAC_O_ACC16_1 0x0000003C + +// Accumulator Bits 17:2 +#define AUX_MAC_O_ACC17_2 0x00000040 + +// Accumulator Bits 18:3 +#define AUX_MAC_O_ACC18_3 0x00000044 + +// Accumulator Bits 19:4 +#define AUX_MAC_O_ACC19_4 0x00000048 + +// Accumulator Bits 20:5 +#define AUX_MAC_O_ACC20_5 0x0000004C + +// Accumulator Bits 21:6 +#define AUX_MAC_O_ACC21_6 0x00000050 + +// Accumulator Bits 22:7 +#define AUX_MAC_O_ACC22_7 0x00000054 + +// Accumulator Bits 23:8 +#define AUX_MAC_O_ACC23_8 0x00000058 + +// Accumulator Bits 24:9 +#define AUX_MAC_O_ACC24_9 0x0000005C + +// Accumulator Bits 25:10 +#define AUX_MAC_O_ACC25_10 0x00000060 + +// Accumulator Bits 26:11 +#define AUX_MAC_O_ACC26_11 0x00000064 + +// Accumulator Bits 27:12 +#define AUX_MAC_O_ACC27_12 0x00000068 + +// Accumulator Bits 28:13 +#define AUX_MAC_O_ACC28_13 0x0000006C + +// Accumulator Bits 29:14 +#define AUX_MAC_O_ACC29_14 0x00000070 + +// Accumulator Bits 30:15 +#define AUX_MAC_O_ACC30_15 0x00000074 + +// Accumulator Bits 31:16 +#define AUX_MAC_O_ACC31_16 0x00000078 + +// Accumulator Bits 32:17 +#define AUX_MAC_O_ACC32_17 0x0000007C + +// Accumulator Bits 33:18 +#define AUX_MAC_O_ACC33_18 0x00000080 + +// Accumulator Bits 34:19 +#define AUX_MAC_O_ACC34_19 0x00000084 + +// Accumulator Bits 35:20 +#define AUX_MAC_O_ACC35_20 0x00000088 + +// Accumulator Bits 36:21 +#define AUX_MAC_O_ACC36_21 0x0000008C + +// Accumulator Bits 37:22 +#define AUX_MAC_O_ACC37_22 0x00000090 + +// Accumulator Bits 38:23 +#define AUX_MAC_O_ACC38_23 0x00000094 + +// Accumulator Bits 39:24 +#define AUX_MAC_O_ACC39_24 0x00000098 + +// Accumulator Bits 39:32 +#define AUX_MAC_O_ACC39_32 0x0000009C + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP0S +// +//***************************************************************************** +// Field: [15:0] OP0_VALUE +// +// Signed operand 0. +// +// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. +#define AUX_MAC_OP0S_OP0_VALUE_W 16 +#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0S_OP0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP0U +// +//***************************************************************************** +// Field: [15:0] OP0_VALUE +// +// Unsigned operand 0. +// +// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. +#define AUX_MAC_OP0U_OP0_VALUE_W 16 +#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0U_OP0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SMUL +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and multiplication trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * +// OP0S.OP0_VALUE. +// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * +// OP0U.OP0_VALUE. +#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UMUL +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and multiplication trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * +// OP0S.OP0_VALUE. +// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * +// OP0U.OP0_VALUE. +#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SMAC +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and multiply-accumulation trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0S.OP0_VALUE ). +// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0U.OP0_VALUE ). +#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UMAC +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and multiply-accumulation trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0S.OP0_VALUE ). +// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * +// OP0U.OP0_VALUE ). +#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SADD16 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Signed operand 1 and 16-bit addition trigger. +// +// Write OP1_VALUE to set signed operand 1 and trigger the following operation: +// +// ACC = ACC + OP1_VALUE. +#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UADD16 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Unsigned operand 1 and 16-bit addition trigger. +// +// Write OP1_VALUE to set unsigned operand 1 and trigger the following +// operation: +// +// ACC = ACC + OP1_VALUE. +#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1SADD32 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Upper half of signed 32-bit operand and addition trigger. +// +// Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the +// following operation: +// +// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). +// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). +#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_OP1UADD32 +// +//***************************************************************************** +// Field: [15:0] OP1_VALUE +// +// Upper half of unsigned 32-bit operand and addition trigger. +// +// Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the +// following operation: +// +// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). +// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + +// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). +#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_CLZ +// +//***************************************************************************** +// Field: [5:0] VALUE +// +// Number of leading zero bits in the accumulator: +// +// 0x00: 0 leading zeros. +// 0x01: 1 leading zero. +// ... +// 0x28: 40 leading zeros (accumulator value is 0). +#define AUX_MAC_CLZ_VALUE_W 6 +#define AUX_MAC_CLZ_VALUE_M 0x0000003F +#define AUX_MAC_CLZ_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_CLS +// +//***************************************************************************** +// Field: [5:0] VALUE +// +// Number of leading sign bits in the accumulator. +// +// When MSB of accumulator is 0, VALUE is number of leading zeros, MSB +// included. +// When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. +// +// VALUE range is 1 thru 40. +#define AUX_MAC_CLS_VALUE_W 6 +#define AUX_MAC_CLS_VALUE_M 0x0000003F +#define AUX_MAC_CLS_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACCSHIFT +// +//***************************************************************************** +// Field: [2] LSL1 +// +// Logic shift left by 1 bit. +// +// Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. +#define AUX_MAC_ACCSHIFT_LSL1 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_BITN 2 +#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_S 2 + +// Field: [1] LSR1 +// +// Logic shift right by 1 bit. +// +// Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. +#define AUX_MAC_ACCSHIFT_LSR1 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_BITN 1 +#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_S 1 + +// Field: [0] ASR1 +// +// Arithmetic shift right by 1 bit. +// +// Write 1 to shift the accumulator one bit to the right, previous sign bit +// inserted at bit 39. +#define AUX_MAC_ACCSHIFT_ASR1 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_BITN 0 +#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACCRESET +// +//***************************************************************************** +// Field: [15:0] TRG +// +// Write any value to this register to trigger a reset of all bits in the +// accumulator. +#define AUX_MAC_ACCRESET_TRG_W 16 +#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF +#define AUX_MAC_ACCRESET_TRG_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC15_0 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 15:0. +// +// Write VALUE to initialize bits 15:0 of accumulator. +#define AUX_MAC_ACC15_0_VALUE_W 16 +#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC15_0_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC16_1 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 16:1. +#define AUX_MAC_ACC16_1_VALUE_W 16 +#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC16_1_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC17_2 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 17:2. +#define AUX_MAC_ACC17_2_VALUE_W 16 +#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC17_2_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC18_3 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 18:3. +#define AUX_MAC_ACC18_3_VALUE_W 16 +#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC18_3_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC19_4 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 19:4. +#define AUX_MAC_ACC19_4_VALUE_W 16 +#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC19_4_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC20_5 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 20:5. +#define AUX_MAC_ACC20_5_VALUE_W 16 +#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC20_5_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC21_6 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 21:6. +#define AUX_MAC_ACC21_6_VALUE_W 16 +#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC21_6_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC22_7 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 22:7. +#define AUX_MAC_ACC22_7_VALUE_W 16 +#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC22_7_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC23_8 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 23:8. +#define AUX_MAC_ACC23_8_VALUE_W 16 +#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC23_8_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC24_9 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 24:9. +#define AUX_MAC_ACC24_9_VALUE_W 16 +#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC24_9_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC25_10 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 25:10. +#define AUX_MAC_ACC25_10_VALUE_W 16 +#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC25_10_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC26_11 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 26:11. +#define AUX_MAC_ACC26_11_VALUE_W 16 +#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC26_11_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC27_12 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 27:12. +#define AUX_MAC_ACC27_12_VALUE_W 16 +#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC27_12_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC28_13 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 28:13. +#define AUX_MAC_ACC28_13_VALUE_W 16 +#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC28_13_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC29_14 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 29:14. +#define AUX_MAC_ACC29_14_VALUE_W 16 +#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC29_14_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC30_15 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 30:15. +#define AUX_MAC_ACC30_15_VALUE_W 16 +#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC30_15_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC31_16 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 31:16. +// +// Write VALUE to initialize bits 31:16 of accumulator. +#define AUX_MAC_ACC31_16_VALUE_W 16 +#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC31_16_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC32_17 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 32:17. +#define AUX_MAC_ACC32_17_VALUE_W 16 +#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC32_17_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC33_18 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 33:18. +#define AUX_MAC_ACC33_18_VALUE_W 16 +#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC33_18_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC34_19 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 34:19. +#define AUX_MAC_ACC34_19_VALUE_W 16 +#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC34_19_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC35_20 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 35:20. +#define AUX_MAC_ACC35_20_VALUE_W 16 +#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC35_20_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC36_21 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 36:21. +#define AUX_MAC_ACC36_21_VALUE_W 16 +#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC36_21_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC37_22 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 37:22. +#define AUX_MAC_ACC37_22_VALUE_W 16 +#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC37_22_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC38_23 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 38:23. +#define AUX_MAC_ACC38_23_VALUE_W 16 +#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC38_23_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC39_24 +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Value of the accumulator, bits 39:24. +#define AUX_MAC_ACC39_24_VALUE_W 16 +#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC39_24_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_MAC_O_ACC39_32 +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// Value of the accumulator, bits 39:32. +// +// Write VALUE to initialize bits 39:32 of accumulator. +#define AUX_MAC_ACC39_32_VALUE_W 8 +#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF +#define AUX_MAC_ACC39_32_VALUE_S 0 + + +#endif // __AUX_MAC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_ram.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_ram.h new file mode 100644 index 00000000..08c75200 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_ram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_aux_ram_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_RAM_H__ +#define __HW_AUX_RAM_H__ + + +#define AUX_RAM_O_BANK0 0x00000000 +#define AUX_RAM_BANK0_BYTE_SIZE 4096 + +#define AUX_RAM_TOT_BYTE_SIZE 4096 + + + +#endif // __HW_AUX_RAM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sce.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sce.h new file mode 100644 index 00000000..87fcff07 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sce.h @@ -0,0 +1,398 @@ +/****************************************************************************** +* Filename: hw_aux_sce_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SCE_H__ +#define __HW_AUX_SCE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SCE component +// +//***************************************************************************** +// Internal +#define AUX_SCE_O_CTL 0x00000000 + +// Internal +#define AUX_SCE_O_FETCHSTAT 0x00000004 + +// Internal +#define AUX_SCE_O_CPUSTAT 0x00000008 + +// Internal +#define AUX_SCE_O_WUSTAT 0x0000000C + +// Internal +#define AUX_SCE_O_REG1_0 0x00000010 + +// Internal +#define AUX_SCE_O_REG3_2 0x00000014 + +// Internal +#define AUX_SCE_O_REG5_4 0x00000018 + +// Internal +#define AUX_SCE_O_REG7_6 0x0000001C + +// Internal +#define AUX_SCE_O_LOOPADDR 0x00000020 + +// Internal +#define AUX_SCE_O_LOOPCNT 0x00000024 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CTL +// +//***************************************************************************** +// Field: [31:24] FORCE_EV_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 + +// Field: [23:16] FORCE_EV_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 + +// Field: [15:8] RESET_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESET_VECTOR_W 8 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 + +// Field: [6] DBG_FREEZE_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 + +// Field: [5] FORCE_WU_LOW +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 + +// Field: [4] FORCE_WU_HIGH +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 + +// Field: [3] RESTART +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 + +// Field: [2] SINGLE_STEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 + +// Field: [1] SUSPEND +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 + +// Field: [0] CLK_EN +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_FETCHSTAT +// +//***************************************************************************** +// Field: [31:16] OPCODE +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 + +// Field: [15:0] PC +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_CPUSTAT +// +//***************************************************************************** +// Field: [11] BUS_ERROR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 + +// Field: [10] SLEEP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 + +// Field: [9] WEV +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 + +// Field: [8] HALTED +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_HALTED 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_BITN 8 +#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_S 8 + +// Field: [3] V_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 + +// Field: [2] C_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 + +// Field: [1] N_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 + +// Field: [0] Z_FLAG +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_WUSTAT +// +//***************************************************************************** +// Field: [18:16] EXC_VECTOR +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 + +// Field: [8] WU_SIGNAL +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 + +// Field: [7:0] EV_SIGNALS +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// SCEWEV_PROG Internal. Only to be used through TI provided API. +// AUX_ADC_FIFO_NOT_EMPTY Internal. Only to be used through TI provided API. +// AUX_TIMER1_EV_OR_IDLE Internal. Only to be used through TI provided API. +// AUX_TIMER0_EV_OR_IDLE Internal. Only to be used through TI provided API. +// AUX_TDC_DONE Internal. Only to be used through TI provided API. +// AUX_COMPB Internal. Only to be used through TI provided API. +// AUX_COMPA Internal. Only to be used through TI provided API. +// AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API. +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 +#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG1_0 +// +//***************************************************************************** +// Field: [31:16] REG1 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 + +// Field: [15:0] REG0 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG3_2 +// +//***************************************************************************** +// Field: [31:16] REG3 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 + +// Field: [15:0] REG2 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG5_4 +// +//***************************************************************************** +// Field: [31:16] REG5 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 + +// Field: [15:0] REG4 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_REG7_6 +// +//***************************************************************************** +// Field: [31:16] REG7 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 + +// Field: [15:0] REG6 +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPADDR +// +//***************************************************************************** +// Field: [31:16] STOP +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 + +// Field: [15:0] START +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 + +//***************************************************************************** +// +// Register: AUX_SCE_O_LOOPCNT +// +//***************************************************************************** +// Field: [7:0] ITER_LEFT +// +// Internal. Only to be used through TI provided API. +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 + + +#endif // __AUX_SCE__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_smph.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_smph.h new file mode 100644 index 00000000..c0942202 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_smph.h @@ -0,0 +1,282 @@ +/****************************************************************************** +* Filename: hw_aux_smph_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SMPH_H__ +#define __HW_AUX_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SMPH component +// +//***************************************************************************** +// Semaphore 0 +#define AUX_SMPH_O_SMPH0 0x00000000 + +// Semaphore 1 +#define AUX_SMPH_O_SMPH1 0x00000004 + +// Semaphore 2 +#define AUX_SMPH_O_SMPH2 0x00000008 + +// Semaphore 3 +#define AUX_SMPH_O_SMPH3 0x0000000C + +// Semaphore 4 +#define AUX_SMPH_O_SMPH4 0x00000010 + +// Semaphore 5 +#define AUX_SMPH_O_SMPH5 0x00000014 + +// Semaphore 6 +#define AUX_SMPH_O_SMPH6 0x00000018 + +// Semaphore 7 +#define AUX_SMPH_O_SMPH7 0x0000001C + +// Auto Take +#define AUX_SMPH_O_AUTOTAKE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Request or release of semaphore. +// +// Request by read: +// +// 0: Semaphore not available. +// 1: Semaphore granted. +// +// Release by write: +// +// 0: Do not use. +// 1: Release semaphore. +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SMPH_O_AUTOTAKE +// +//***************************************************************************** +// Field: [2:0] SMPH_ID +// +// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until +// it is granted. +// +// When semaphore SMPH_ID is granted, event +// AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE becomes 1. +// +// The event becomes 0 when software releases the semaphore or writes a new +// value to SMPH_ID. +// +// To avoid corrupted semaphores: +// - Usage of this functionality must be restricted to one CPU core. +// - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1 +// before it writes a new value to SMPH_ID. +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 + + +#endif // __AUX_SMPH__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_spim.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_spim.h new file mode 100644 index 00000000..e5fb4a20 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_spim.h @@ -0,0 +1,239 @@ +/****************************************************************************** +* Filename: hw_aux_spim_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SPIM_H__ +#define __HW_AUX_SPIM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SPIM component +// +//***************************************************************************** +// SPI Master Configuration +#define AUX_SPIM_O_SPIMCFG 0x00000000 + +// MISO Configuration +#define AUX_SPIM_O_MISOCFG 0x00000004 + +// MOSI Control +#define AUX_SPIM_O_MOSICTL 0x00000008 + +// Transmit 8 Bit +#define AUX_SPIM_O_TX8 0x0000000C + +// Transmit 16 Bit +#define AUX_SPIM_O_TX16 0x00000010 + +// Receive 8 Bit +#define AUX_SPIM_O_RX8 0x00000014 + +// Receive 16 Bit +#define AUX_SPIM_O_RX16 0x00000018 + +// SCLK Idle +#define AUX_SPIM_O_SCLKIDLE 0x0000001C + +// Data Idle +#define AUX_SPIM_O_DATAIDLE 0x00000020 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_SPIMCFG +// +//***************************************************************************** +// Field: [7:2] DIV +// +// SCLK divider. +// +// Peripheral clock frequency division gives the SCLK clock frequency. The +// division factor equals (2 * (DIV+1)): +// +// 0x00: Divide by 2. +// 0x01: Divide by 4. +// 0x02: Divide by 6. +// ... +// 0x3F: Divide by 128. +#define AUX_SPIM_SPIMCFG_DIV_W 6 +#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC +#define AUX_SPIM_SPIMCFG_DIV_S 2 + +// Field: [1] PHA +// +// Phase of the MOSI and MISO data signals. +// +// 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) +// edges of SCLK. +// 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) +// edges of SCLK. +#define AUX_SPIM_SPIMCFG_PHA 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_BITN 1 +#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_S 1 + +// Field: [0] POL +// +// Polarity of the SCLK signal. +// +// 0: SCLK is low when idle, first clock edge rises. +// 1: SCLK is high when idle, first clock edge falls. +#define AUX_SPIM_SPIMCFG_POL 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_BITN 0 +#define AUX_SPIM_SPIMCFG_POL_M 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_MISOCFG +// +//***************************************************************************** +// Field: [4:0] AUXIO +// +// AUXIO to MISO mux. +// +// Select the AUXIO pin that connects to MISO. +#define AUX_SPIM_MISOCFG_AUXIO_W 5 +#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F +#define AUX_SPIM_MISOCFG_AUXIO_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_MOSICTL +// +//***************************************************************************** +// Field: [0] VALUE +// +// MOSI level control. +// +// 0: Set MOSI low. +// 1: Set MOSI high. +#define AUX_SPIM_MOSICTL_VALUE 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_BITN 0 +#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_TX8 +// +//***************************************************************************** +// Field: [7:0] DATA +// +// 8 bit data transfer. +// +// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays +// at the value of LSB. +#define AUX_SPIM_TX8_DATA_W 8 +#define AUX_SPIM_TX8_DATA_M 0x000000FF +#define AUX_SPIM_TX8_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_TX16 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// 16 bit data transfer. +// +// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays +// at the value of LSB. +#define AUX_SPIM_TX16_DATA_W 16 +#define AUX_SPIM_TX16_DATA_M 0x0000FFFF +#define AUX_SPIM_TX16_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_RX8 +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Latest 8 bits received on MISO. +#define AUX_SPIM_RX8_DATA_W 8 +#define AUX_SPIM_RX8_DATA_M 0x000000FF +#define AUX_SPIM_RX8_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_RX16 +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Latest 16 bits received on MISO. +#define AUX_SPIM_RX16_DATA_W 16 +#define AUX_SPIM_RX16_DATA_M 0x0000FFFF +#define AUX_SPIM_RX16_DATA_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_SCLKIDLE +// +//***************************************************************************** +// Field: [0] STAT +// +// Wait for SCLK idle. +// +// Read operation stalls until SCLK is idle with no remaining clock edges. Read +// then returns 1. +// +// AUX_SCE can use this to control CS deassertion. +#define AUX_SPIM_SCLKIDLE_STAT 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_BITN 0 +#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SPIM_O_DATAIDLE +// +//***************************************************************************** +// Field: [0] STAT +// +// Wait for data idle. +// +// Read operation stalls until the SCLK period associated with LSB transmission +// completes. Read then returns 1. +// +// AUX_SCE can use this to control CS deassertion. +#define AUX_SPIM_DATAIDLE_STAT 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_BITN 0 +#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_S 0 + + +#endif // __AUX_SPIM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sysif.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sysif.h new file mode 100644 index 00000000..72b6ad43 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_sysif.h @@ -0,0 +1,2088 @@ +/****************************************************************************** +* Filename: hw_aux_sysif_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_SYSIF_H__ +#define __HW_AUX_SYSIF_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_SYSIF component +// +//***************************************************************************** +// Operational Mode Request +#define AUX_SYSIF_O_OPMODEREQ 0x00000000 + +// Operational Mode Acknowledgement +#define AUX_SYSIF_O_OPMODEACK 0x00000004 + +// Programmable Wakeup 0 Configuration +#define AUX_SYSIF_O_PROGWU0CFG 0x00000008 + +// Programmable Wakeup 1 Configuration +#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C + +// Programmable Wakeup 2 Configuration +#define AUX_SYSIF_O_PROGWU2CFG 0x00000010 + +// Programmable Wakeup 3 Configuration +#define AUX_SYSIF_O_PROGWU3CFG 0x00000014 + +// Software Wakeup Triggers +#define AUX_SYSIF_O_SWWUTRIG 0x00000018 + +// Wakeup Flags +#define AUX_SYSIF_O_WUFLAGS 0x0000001C + +// Wakeup Flags Clear +#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020 + +// Wakeup Gate +#define AUX_SYSIF_O_WUGATE 0x00000024 + +// Vector Configuration 0 +#define AUX_SYSIF_O_VECCFG0 0x00000028 + +// Vector Configuration 1 +#define AUX_SYSIF_O_VECCFG1 0x0000002C + +// Vector Configuration 2 +#define AUX_SYSIF_O_VECCFG2 0x00000030 + +// Vector Configuration 3 +#define AUX_SYSIF_O_VECCFG3 0x00000034 + +// Vector Configuration 4 +#define AUX_SYSIF_O_VECCFG4 0x00000038 + +// Vector Configuration 5 +#define AUX_SYSIF_O_VECCFG5 0x0000003C + +// Vector Configuration 6 +#define AUX_SYSIF_O_VECCFG6 0x00000040 + +// Vector Configuration 7 +#define AUX_SYSIF_O_VECCFG7 0x00000044 + +// Event Synchronization Rate +#define AUX_SYSIF_O_EVSYNCRATE 0x00000048 + +// Peripheral Operational Rate +#define AUX_SYSIF_O_PEROPRATE 0x0000004C + +// ADC Clock Control +#define AUX_SYSIF_O_ADCCLKCTL 0x00000050 + +// TDC Counter Clock Control +#define AUX_SYSIF_O_TDCCLKCTL 0x00000054 + +// TDC Reference Clock Control +#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058 + +// AUX_TIMER2 Clock Control +#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C + +// AUX_TIMER2 Clock Status +#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060 + +// AUX_TIMER2 Clock Switch +#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064 + +// AUX_TIMER2 Debug Control +#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068 + +// Clock Shift Detection +#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070 + +// VDDR Recharge Trigger +#define AUX_SYSIF_O_RECHARGETRIG 0x00000074 + +// VDDR Recharge Detection +#define AUX_SYSIF_O_RECHARGEDET 0x00000078 + +// Real Time Counter Sub Second Increment 0 +#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C + +// Real Time Counter Sub Second Increment 1 +#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080 + +// Real Time Counter Sub Second Increment Control +#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084 + +// Real Time Counter Second +#define AUX_SYSIF_O_RTCSEC 0x00000088 + +// Real Time Counter Sub-Second +#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C + +// AON_RTC Event Clear +#define AUX_SYSIF_O_RTCEVCLR 0x00000090 + +// AON_BATMON Battery Voltage Value +#define AUX_SYSIF_O_BATMONBAT 0x00000094 + +// AON_BATMON Temperature Value +#define AUX_SYSIF_O_BATMONTEMP 0x0000009C + +// Timer Halt +#define AUX_SYSIF_O_TIMERHALT 0x000000A0 + +// AUX_TIMER2 Bridge +#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0 + +// Software Power Profiler +#define AUX_SYSIF_O_SWPWRPROF 0x000000B4 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_OPMODEREQ +// +//***************************************************************************** +// Field: [1:0] REQ +// +// AUX operational mode request. +// ENUMs: +// PDLP Powerdown operational mode with wakeup to lowpower +// mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - +// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock +// frequency (SCE_RATE). +// - An active wakeup flag +// overrides the operational mode externally to +// lowpower (LP) as long as the flag is set. +// PDA Powerdown operational mode with wakeup to active +// mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - +// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock +// frequency (SCE_RATE). +// - An active wakeup flag +// overrides the operational mode externally to +// active (A) as long as the flag is set. +// LP Lowpower operational mode, characterized by: +// - Powerdown system power +// supply state (uLDO) request. +// - SCE clock frequency +// (SCE_RATE) equals SCLK_MF. +// - An active wakeup flag +// does not change operational mode. +// A Active operational mode, characterized by: +// - Active system power +// supply state (GLDO or DCDC) request. +// - AON_PMCTL:AUXSCECLK.SRC +// sets the SCE clock frequency (SCE_RATE). +// - An active wakeup flag +// does not change operational mode. +#define AUX_SYSIF_OPMODEREQ_REQ_W 2 +#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_S 0 +#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002 +#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001 +#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_OPMODEACK +// +//***************************************************************************** +// Field: [1:0] ACK +// +// AUX operational mode acknowledgement. +// ENUMs: +// PDLP Powerdown operational mode with wakeup to lowpower +// mode is acknowledged. +// PDA Powerdown operational mode with wakeup to active +// mode is acknowledged. +// LP Lowpower operational mode is acknowledged. +// A Active operational mode is acknowledged. +#define AUX_SYSIF_OPMODEACK_ACK_W 2 +#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_S 0 +#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002 +#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001 +#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU0CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU0. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_S 7 +#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU1CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU1. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_S 7 +#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU2CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU2. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_S 7 +#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PROGWU3CFG +// +//***************************************************************************** +// Field: [7] POL +// +// Polarity of WU_SRC. +// +// The procedure used to clear the wakeup flag decides level or edge +// sensitivity, see WUFLAGSCLR.PROG_WU3. +// ENUMs: +// LOW The wakeup flag is set when WU_SRC is low or goes +// low. +// HIGH The wakeup flag is set when WU_SRC is high or goes +// high. +#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_S 7 +#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000 + +// Field: [6] EN +// +// Programmable wakeup flag enable. +// +// 0: Disable wakeup flag. +// 1: Enable wakeup flag. +#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_S 6 + +// Field: [5:0] WU_SRC +// +// Wakeup source from the asynchronous AUX event bus. +// +// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_SWWUTRIG +// +//***************************************************************************** +// Field: [3] SW_WU3 +// +// Software wakeup 3 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3 + +// Field: [2] SW_WU2 +// +// Software wakeup 2 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2 + +// Field: [1] SW_WU1 +// +// Software wakeup 1 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1 + +// Field: [0] SW_WU0 +// +// Software wakeup 0 trigger. +// +// 0: No effect. +// 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. +#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUFLAGS +// +//***************************************************************************** +// Field: [7] SW_WU3 +// +// Software wakeup 3 flag. +// +// 0: Software wakeup 3 not triggered. +// 1: Software wakeup 3 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7 + +// Field: [6] SW_WU2 +// +// Software wakeup 2 flag. +// +// 0: Software wakeup 2 not triggered. +// 1: Software wakeup 2 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6 + +// Field: [5] SW_WU1 +// +// Software wakeup 1 flag. +// +// 0: Software wakeup 1 not triggered. +// 1: Software wakeup 1 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5 + +// Field: [4] SW_WU0 +// +// Software wakeup 0 flag. +// +// 0: Software wakeup 0 not triggered. +// 1: Software wakeup 0 triggered. +#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4 + +// Field: [3] PROG_WU3 +// +// Programmable wakeup 3. +// +// 0: Programmable wakeup 3 not triggered. +// 1: Programmable wakeup 3 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3 + +// Field: [2] PROG_WU2 +// +// Programmable wakeup 2. +// +// 0: Programmable wakeup 2 not triggered. +// 1: Programmable wakeup 2 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2 + +// Field: [1] PROG_WU1 +// +// Programmable wakeup 1. +// +// 0: Programmable wakeup 1 not triggered. +// 1: Programmable wakeup 1 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1 + +// Field: [0] PROG_WU0 +// +// Programmable wakeup 0. +// +// 0: Programmable wakeup 0 not triggered. +// 1: Programmable wakeup 0 triggered. +#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUFLAGSCLR +// +//***************************************************************************** +// Field: [7] SW_WU3 +// +// Clear software wakeup flag 3. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7 + +// Field: [6] SW_WU2 +// +// Clear software wakeup flag 2. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6 + +// Field: [5] SW_WU1 +// +// Clear software wakeup flag 1. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5 + +// Field: [4] SW_WU0 +// +// Clear software wakeup flag 0. +// +// 0: No effect. +// 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4 + +// Field: [3] PROG_WU3 +// +// Programmable wakeup flag 3. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when +// PROGWU3CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when +// PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3 + +// Field: [2] PROG_WU2 +// +// Programmable wakeup flag 2. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when +// PROGWU2CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when +// PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2 + +// Field: [1] PROG_WU1 +// +// Programmable wakeup flag 1. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when +// PROGWU1CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when +// PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1 + +// Field: [0] PROG_WU0 +// +// Programmable wakeup flag 0. +// +// 0: No effect. +// 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. +// +// The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when +// PROGWU0CFG.EN is 1. +// The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when +// PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_WUGATE +// +//***************************************************************************** +// Field: [0] EN +// +// Wakeup output enable. +// +// 0: Disable AUX wakeup output. +// 1: Enable AUX wakeup output. +#define AUX_SYSIF_WUGATE_EN 0x00000001 +#define AUX_SYSIF_WUGATE_EN_BITN 0 +#define AUX_SYSIF_WUGATE_EN_M 0x00000001 +#define AUX_SYSIF_WUGATE_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG0 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 0. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG0_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG0_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG1 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 1. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG1_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG1_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG2 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 2. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG2_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG2_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG3 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 3. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG3_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG3_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG4 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 4. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG4_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG4_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG5 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 5. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG5_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG5_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG6 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 6. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG6_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG6_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_VECCFG7 +// +//***************************************************************************** +// Field: [3:0] VEC_EV +// +// Select trigger event for vector 7. +// +// Non-enumerated values are treated as NONE. +// ENUMs: +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// SW_WU3 WUFLAGS.SW_WU3 +// SW_WU2 WUFLAGS.SW_WU2 +// SW_WU1 WUFLAGS.SW_WU1 +// SW_WU0 WUFLAGS.SW_WU0 +// PROG_WU3 WUFLAGS.PROG_WU3 +// PROG_WU2 WUFLAGS.PROG_WU2 +// PROG_WU1 WUFLAGS.PROG_WU1 +// PROG_WU0 WUFLAGS.PROG_WU0 +// NONE Vector is disabled. +#define AUX_SYSIF_VECCFG7_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG7_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_EVSYNCRATE +// +//***************************************************************************** +// Field: [2] AUX_COMPA_SYNC_RATE +// +// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000 + +// Field: [1] AUX_COMPB_SYNC_RATE +// +// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000 + +// Field: [0] AUX_TIMER2_SYNC_RATE +// +// Select synchronization rate for: +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_PEROPRATE +// +//***************************************************************************** +// Field: [3] ANAIF_DAC_OP_RATE +// +// Select operational rate for AUX_ANAIF DAC sample clock state machine. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000 + +// Field: [2] TIMER01_OP_RATE +// +// Select operational rate for AUX_TIMER01. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000 + +// Field: [1] SPIM_OP_RATE +// +// Select operational rate for AUX_SPIM. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000 + +// Field: [0] MAC_OP_RATE +// +// Select operational rate for AUX_MAC. +// ENUMs: +// BUS_RATE AUX bus rate +// SCE_RATE SCE rate +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_ADCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// Clock acknowledgement. +// +// 0: ADC clock is disabled. +// 1: ADC clock is enabled. +#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// ADC clock request. +// +// 0: Disable ADC clock. +// 1: Enable ADC clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TDCCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// TDC counter clock acknowledgement. +// +// 0: TDC counter clock is disabled. +// 1: TDC counter clock is enabled. +#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// TDC counter clock request. +// +// 0: Disable TDC counter clock. +// 1: Enable TDC counter clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TDCREFCLKCTL +// +//***************************************************************************** +// Field: [1] ACK +// +// TDC reference clock acknowledgement. +// +// 0: TDC reference clock is disabled. +// 1: TDC reference clock is enabled. +#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1 + +// Field: [0] REQ +// +// TDC reference clock request. +// +// 0: Disable TDC reference clock. +// 1: Enable TDC reference clock. +// +// Only modify REQ when equal to ACK. +#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKCTL +// +//***************************************************************************** +// Field: [2:0] SRC +// +// Select clock source for AUX_TIMER2. +// +// Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or +// TIMER2CLKSWITCH.RDY is 1. +// +// It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0. +// +// A non-enumerated value is ignored. +// ENUMs: +// SCLK_HFDIV2 SCLK_HF / 2 +// SCLK_MF SCLK_MF +// SCLK_LF SCLK_LF +// NONE no clock +#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKSTAT +// +//***************************************************************************** +// Field: [2:0] STAT +// +// AUX_TIMER2 clock source status. +// ENUMs: +// SCLK_HFDIV2 SCLK_HF / 2 +// SCLK_MF SCLK_MF +// SCLK_LF SCLK_LF +// NONE No clock +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2CLKSWITCH +// +//***************************************************************************** +// Field: [0] RDY +// +// Status of clock switcher. +// +// 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. +// 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. +// +// RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2DBGCTL +// +//***************************************************************************** +// Field: [0] DBG_FREEZE_EN +// +// Debug freeze enable. +// +// 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. +// 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_CLKSHIFTDET +// +//***************************************************************************** +// Field: [0] STAT +// +// Clock shift detection. +// +// Write: +// +// 0: Restart clock shift detection. +// 1: Do not use. +// +// Read: +// +// 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. +// 1: MCU domain entered or exited active state since you wrote 0 to STAT. +#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0 +#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RECHARGETRIG +// +//***************************************************************************** +// Field: [0] TRIG +// +// Recharge trigger. +// +// 0: No effect. +// 1: Request VDDR recharge. +// +// Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. +// +// Follow this sequence when OPMODEREQ.REQ is LP: +// - Set TRIG. +// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. +// - Clear TRIG. +// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. +// +// Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: +// - Set TRIG. +// - Clear TRIG. +#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0 +#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RECHARGEDET +// +//***************************************************************************** +// Field: [1] STAT +// +// VDDR recharge detector status. +// +// 0: No recharge of VDDR has occurred since EN was set. +// 1: Recharge of VDDR has occurred since EN was set. +#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1 +#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_S 1 + +// Field: [0] EN +// +// VDDR recharge detector enable. +// +// 0: Disable recharge detection. STAT becomes zero. +// 1: Enable recharge detection. +#define AUX_SYSIF_RECHARGEDET_EN 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_BITN 0 +#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINC0 +// +//***************************************************************************** +// Field: [15:0] INC15_0 +// +// New value for bits 15:0 in AON_RTC:SUBSECINC. +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINC1 +// +//***************************************************************************** +// Field: [7:0] INC23_16 +// +// New value for bits 23:16 in AON_RTC:SUBSECINC. +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSECINCCTL +// +//***************************************************************************** +// Field: [1] UPD_ACK +// +// Update acknowledgement. +// +// 0: AON_RTC has not acknowledged UPD_REQ. +// 1: AON_RTC has acknowledged UPD_REQ. +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1 + +// Field: [0] UPD_REQ +// +// Request AON_RTC to update AON_RTC:SUBSECINC. +// +// 0: Clear request to update. +// 1: Set request to update. +// +// Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is +// 1. +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSEC +// +//***************************************************************************** +// Field: [15:0] SEC +// +// Bits 15:0 in AON_RTC:SEC.VALUE. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of SEC. +// - Then read SEC until two consecutive reads are equal. +#define AUX_SYSIF_RTCSEC_SEC_W 16 +#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSEC_SEC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCSUBSEC +// +//***************************************************************************** +// Field: [15:0] SUBSEC +// +// Bits 31:16 in AON_RTC:SUBSEC.VALUE. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads SUBSEC. +// - Then read SUBSEC until two consecutive reads are equal. +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16 +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_RTCEVCLR +// +//***************************************************************************** +// Field: [0] RTC_CH2_EV_CLR +// +// Clear events from AON_RTC channel 2. +// +// 0: No effect. +// 1: Clear events from AON_RTC channel 2. +// +// Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and +// AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_BATMONBAT +// +//***************************************************************************** +// Field: [10:8] INT +// +// See AON_BATMON:BAT.INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of INT. +// - Then read INT until two consecutive reads are equal. +#define AUX_SYSIF_BATMONBAT_INT_W 3 +#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700 +#define AUX_SYSIF_BATMONBAT_INT_S 8 + +// Field: [7:0] FRAC +// +// See AON_BATMON:BAT.FRAC. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of FRAC. +// - Then read FRAC until two consecutive reads are equal. +#define AUX_SYSIF_BATMONBAT_FRAC_W 8 +#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF +#define AUX_SYSIF_BATMONBAT_FRAC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_BATMONTEMP +// +//***************************************************************************** +// Field: [15:11] SIGN +// +// Sign extension of INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of SIGN. +// - Then read SIGN until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_SIGN_W 5 +#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800 +#define AUX_SYSIF_BATMONTEMP_SIGN_S 11 + +// Field: [10:2] INT +// +// See AON_BATMON:TEMP.INT. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of INT. +// - Then read INT until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_INT_W 9 +#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC +#define AUX_SYSIF_BATMONTEMP_INT_S 2 + +// Field: [1:0] FRAC +// +// See AON_BATMON:TEMP.FRAC. +// +// Follow this procedure to get the correct value: +// - Do two dummy reads of FRAC. +// - Then read FRAC until two consecutive reads are equal. +#define AUX_SYSIF_BATMONTEMP_FRAC_W 2 +#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003 +#define AUX_SYSIF_BATMONTEMP_FRAC_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMERHALT +// +//***************************************************************************** +// Field: [3] PROGDLY +// +// Halt programmable delay. +// +// 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. +// 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. +#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3 +#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3 + +// Field: [2] AUX_TIMER2 +// +// Halt AUX_TIMER2. +// +// 0: AUX_TIMER2 operates as normal. +// 1: Halt AUX_TIMER2 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2 + +// Field: [1] AUX_TIMER1 +// +// Halt AUX_TIMER01 Timer 1. +// +// 0: AUX_TIMER01 Timer 1 operates as normal. +// 1: Halt AUX_TIMER01 Timer 1 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1 + +// Field: [0] AUX_TIMER0 +// +// Halt AUX_TIMER01 Timer 0. +// +// 0: AUX_TIMER01 Timer 0 operates as normal. +// 1: Halt AUX_TIMER01 Timer 0 operation. +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_TIMER2BRIDGE +// +//***************************************************************************** +// Field: [0] BUSY +// +// Status of bus transactions to AUX_TIMER2. +// +// 0: No unfinished bus transactions. +// 1: A bus transaction is ongoing. +#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0 + +//***************************************************************************** +// +// Register: AUX_SYSIF_O_SWPWRPROF +// +//***************************************************************************** +// Field: [2:0] STAT +// +// Software status bits that can be read by the power profiler. +#define AUX_SYSIF_SWPWRPROF_STAT_W 3 +#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007 +#define AUX_SYSIF_SWPWRPROF_STAT_S 0 + + +#endif // __AUX_SYSIF__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_tdc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_tdc.h new file mode 100644 index 00000000..60a8acae --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_tdc.h @@ -0,0 +1,879 @@ +/****************************************************************************** +* Filename: hw_aux_tdc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TDC_H__ +#define __HW_AUX_TDC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TDC component +// +//***************************************************************************** +// Control +#define AUX_TDC_O_CTL 0x00000000 + +// Status +#define AUX_TDC_O_STAT 0x00000004 + +// Result +#define AUX_TDC_O_RESULT 0x00000008 + +// Saturation Configuration +#define AUX_TDC_O_SATCFG 0x0000000C + +// Trigger Source +#define AUX_TDC_O_TRIGSRC 0x00000010 + +// Trigger Counter +#define AUX_TDC_O_TRIGCNT 0x00000014 + +// Trigger Counter Load +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 + +// Trigger Counter Configuration +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C + +// Prescaler Control +#define AUX_TDC_O_PRECTL 0x00000020 + +// Prescaler Counter +#define AUX_TDC_O_PRECNTR 0x00000024 + +//***************************************************************************** +// +// Register: AUX_TDC_O_CTL +// +//***************************************************************************** +// Field: [1:0] CMD +// +// TDC commands. +// ENUMs: +// ABORT Force TDC state machine back to IDLE state. +// +// Never write this command +// while AUX_TDC:STAT.STATE equals CLR_CNT or +// WAIT_CLR_CNT_DONE. +// RUN Asynchronous counter start. +// +// The counter starts to +// count when the start event is high. To achieve +// precise edge-to-edge measurements you must +// ensure that the start event is low for at least +// 420 ns after you write this command. +// RUN_SYNC_START Synchronous counter start. +// +// The counter looks for the +// opposite edge of the selected start event +// before it starts to count when the selected +// edge occurs. This guarantees an edge-triggered +// start and is recommended for frequency +// measurements. +// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. +// +// This is not needed as +// prerequisite for a measurement. Reliable clear +// is only guaranteed from IDLE state. +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_STAT +// +//***************************************************************************** +// Field: [7] SAT +// +// TDC measurement saturation flag. +// +// 0: Conversion has not saturated. +// 1: Conversion stopped due to saturation. +// +// This field is cleared when a new measurement is started or when CLR_RESULT +// is written to CTL.CMD. +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 + +// Field: [6] DONE +// +// TDC measurement complete flag. +// +// 0: TDC measurement has not yet completed. +// 1: TDC measurement has completed. +// +// This field clears when a new TDC measurement starts or when you write +// CLR_RESULT to CTL.CMD. +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 + +// Field: [5:0] STATE +// +// TDC state machine status. +// ENUMs: +// FORCE_STOP Current state is TDC_FORCESTOP. +// You wrote ABORT to +// CTL.CMD to abort the TDC measurement. +// START_FALL Current state is TDC_WAIT_STARTFALL. +// The fast-counter circuit +// waits for a falling edge on the start event. +// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. +// The state machine waits +// for fast-counter circuit to finish reset. +// POR Current state is TDC_STATE_POR. +// This is the reset state. +// GET_RESULT Current state is TDC_STATE_GETRESULTS. +// The state machine copies +// the counter value from the fast-counter +// circuit. +// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. +// The fast-counter circuit +// looks for the stop condition. It will ignore a +// number of stop events configured in +// TRIGCNTLOAD.CNT. +// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. +// The state machine waits +// for the fast-counter circuit to stop. +// CLR_CNT Current state is TDC_STATE_CLRCNT. The +// fast-counter circuit is reset. +// IDLE Current state is TDC_STATE_IDLE. +// This is the default state +// after reset and abortion. State will change +// when you write CTL.CMD to either RUN_SYNC_START +// or RUN. +// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +// WAIT_START Current state is TDC_STATE_WAIT_START. +// The fast-counter circuit +// looks for the start condition. The state +// machine waits for the fast-counter to +// increment. +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_RESULT +// +//***************************************************************************** +// Field: [24:0] VALUE +// +// TDC conversion result. +// +// The result of the TDC conversion is given in number of clock edges of the +// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and +// falling edges are counted. +// +// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it +// takes a non-zero time to stop the measurement. Hence, the maximum value of +// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT +// to R24. +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_SATCFG +// +//***************************************************************************** +// Field: [3:0] LIMIT +// +// Saturation limit. +// +// The flag STAT.SAT is set when the TDC counter saturates. +// +// Values not enumerated are not supported +// ENUMs: +// R24 Result bit 24: TDC conversion saturates and stops +// when RESULT.VALUE[24] is set. +// R23 Result bit 23: TDC conversion saturates and stops +// when RESULT.VALUE[23] is set. +// R22 Result bit 22: TDC conversion saturates and stops +// when RESULT.VALUE[22] is set. +// R21 Result bit 21: TDC conversion saturates and stops +// when RESULT.VALUE[21] is set. +// R20 Result bit 20: TDC conversion saturates and stops +// when RESULT.VALUE[20] is set. +// R19 Result bit 19: TDC conversion saturates and stops +// when RESULT.VALUE[19] is set. +// R18 Result bit 18: TDC conversion saturates and stops +// when RESULT.VALUE[18] is set. +// R17 Result bit 17: TDC conversion saturates and stops +// when RESULT.VALUE[17] is set. +// R16 Result bit 16: TDC conversion saturates and stops +// when RESULT.VALUE[16] is set. +// R15 Result bit 15: TDC conversion saturates and stops +// when RESULT.VALUE[15] is set. +// R14 Result bit 14: TDC conversion saturates and stops +// when RESULT.VALUE[14] is set. +// R13 Result bit 13: TDC conversion saturates and stops +// when RESULT.VALUE[13] is set. +// R12 Result bit 12: TDC conversion saturates and stops +// when RESULT.VALUE[12] is set. +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGSRC +// +//***************************************************************************** +// Field: [14] STOP_POL +// +// Polarity of stop source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion stops when low level is detected. +// HIGH TDC conversion stops when high level is detected. +#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 14 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 + +// Field: [13:8] STOP_SRC +// +// Select stop source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// NO_EVENT No event. +// AUX_TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 6 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000 + +// Field: [6] START_POL +// +// Polarity of start source. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// LOW TDC conversion starts when low level is detected. +// HIGH TDC conversion starts when high level is detected. +#define AUX_TDC_TRIGSRC_START_POL 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_BITN 6 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_S 6 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 + +// Field: [5:0] START_SRC +// +// Select start source from the asynchronous AUX event bus. +// +// Change only while STAT.STATE is IDLE. +// ENUMs: +// NO_EVENT No event. +// AUX_TDC_PRE Select TDC Prescaler event which is generated by +// configuration of PRECTL. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_TRIGSRC_START_SRC_W 6 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E +#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNT +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// Read CNT to get the remaining number of stop events to ignore during a TDC +// measurement. +// +// Write CNT to update the remaining number of stop events to ignore during a +// TDC measurement. The TDC measurement ignores updates of CNT if there are no +// more stop events left to ignore. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the +// start of the measurement. +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTLOAD +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. +// +// To measure frequency of an event source: +// - Set start event equal to stop event. +// - Set CNT to number of periods to measure. Both 0 and 1 values measures a +// single event source period. +// +// To measure pulse width of an event source: +// - Set start event source equal to stop event source. +// - Select different polarity for start and stop event. +// - Set CNT to 0. +// +// To measure time from the start event to the Nth stop event when N > 1: +// - Select different start and stop event source. +// - Set CNT to (N-1). +// +// See the Technical Reference Manual for event timing requirements. +// +// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start +// of the measurement. +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_TRIGCNTCFG +// +//***************************************************************************** +// Field: [0] EN +// +// Enable stop-counter. +// +// 0: Disable stop-counter. +// 1: Enable stop-counter. +// +// Change only while STAT.STATE is IDLE. +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECTL +// +//***************************************************************************** +// Field: [7] RESET_N +// +// Prescaler reset. +// +// 0: Reset prescaler. +// 1: Release reset of prescaler. +// +// AUX_TDC_PRE event becomes 0 when you reset the prescaler. +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 + +// Field: [6] RATIO +// +// Prescaler ratio. +// +// This controls how often the AUX_TDC_PRE event is generated by the prescaler. +// ENUMs: +// DIV64 Prescaler divides input by 64. +// +// AUX_TDC_PRE event has a +// rising edge for every 64 rising edges of the +// input. AUX_TDC_PRE event toggles on every 32nd +// rising edge of the input. +// DIV16 Prescaler divides input by 16. +// +// AUX_TDC_PRE event has a +// rising edge for every 16 rising edges of the +// input. AUX_TDC_PRE event toggles on every 8th +// rising edge of the input. +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 + +// Field: [5:0] SRC +// +// Prescaler event source. +// +// Select an event from the asynchronous AUX event bus to connect to the +// prescaler input. +// +// Configure only while RESET_N is 0. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TDC_PRECTL_SRC_W 6 +#define AUX_TDC_PRECTL_SRC_M 0x0000003F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F +#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E +#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001 +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TDC_O_PRECNTR +// +//***************************************************************************** +// Field: [15:0] CNT +// +// Prescaler counter value. +// +// Write a value to CNT to capture the value of the 16-bit prescaler counter +// into CNT. Read CNT to get the captured value. +// +// The read value gets 1 LSB uncertainty if the event source level rises when +// you release the reset. +// The read value gets 1 LSB uncertainty if the event source level rises when +// you capture the prescaler counter. +// +// Please note the following: +// - The prescaler counter is reset to 2 by PRECTL.RESET_N. +// - The captured value is 2 when the number of rising edges on prescaler input +// is less than 3. Otherwise, captured value equals number of event pulses - 1. +#define AUX_TDC_PRECNTR_CNT_W 16 +#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNTR_CNT_S 0 + + +#endif // __AUX_TDC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer01.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer01.h new file mode 100644 index 00000000..2547f699 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer01.h @@ -0,0 +1,611 @@ +/****************************************************************************** +* Filename: hw_aux_timer01_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER01_H__ +#define __HW_AUX_TIMER01_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER01 component +// +//***************************************************************************** +// Timer 0 Configuration +#define AUX_TIMER01_O_T0CFG 0x00000000 + +// Timer 0 Control +#define AUX_TIMER01_O_T0CTL 0x00000004 + +// Timer 0 Target +#define AUX_TIMER01_O_T0TARGET 0x00000008 + +// Timer 0 Counter +#define AUX_TIMER01_O_T0CNTR 0x0000000C + +// Timer 1 Configuration +#define AUX_TIMER01_O_T1CFG 0x00000010 + +// Timer 1 Control +#define AUX_TIMER01_O_T1CTL 0x00000014 + +// Timer 1 Target +#define AUX_TIMER01_O_T1TARGET 0x00000018 + +// Timer 1 Counter +#define AUX_TIMER01_O_T1CNTR 0x0000001C + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CFG +// +//***************************************************************************** +// Field: [14] TICK_SRC_POL +// +// Tick source polarity for Timer 0. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [13:8] TICK_SRC +// +// Select Timer 0 tick source from the synchronous event bus. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// NO_EVENT No event. +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER01_T0CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER01_T0CFG_PRE_W 4 +#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T0CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 0 mode. +// +// Configure source for Timer 0 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use clock as source for prescaler. Note that +// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the +// clock frequency. +#define AUX_TIMER01_T0CFG_MODE 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_BITN 1 +#define AUX_TIMER01_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_S 1 +#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 0 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 0 restarts when the +// counter value becomes equal to or greater than +// ( T0TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 0 stops and +// T0CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T0TARGET.VALUE. +#define AUX_TIMER01_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_S 0 +#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 0 enable. +// +// 0: Disable Timer 0. +// 1: Enable Timer 0. +// +// The counter restarts from 0 when you enable Timer 0. +#define AUX_TIMER01_T0CTL_EN 0x00000001 +#define AUX_TIMER01_T0CTL_EN_BITN 0 +#define AUX_TIMER01_T0CTL_EN_M 0x00000001 +#define AUX_TIMER01_T0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 target value. +// +// Manual Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter +// value is equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 +// peripheral clock period. +// +// Continuous Reload Mode: +// - Timer 0 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter +// value is 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 0 counter value remains 0. +// AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you +// enable the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER01_T0TARGET_VALUE_W 16 +#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T0CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 0 counter value. +#define AUX_TIMER01_T0CNTR_VALUE_W 16 +#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0CNTR_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CFG +// +//***************************************************************************** +// Field: [14] TICK_SRC_POL +// +// Tick source polarity for Timer 1. +// ENUMs: +// FALL Count on falling edges of TICK_SRC. +// RISE Count on rising edges of TICK_SRC. +#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 + +// Field: [13:8] TICK_SRC +// +// Select Timer 1 tick source from the synchronous event bus. +// ENUMs: +// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY +// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// NO_EVENT No event. +// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER01_T1CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 + +// Field: [7:4] PRE +// +// Prescaler division ratio is 2^PRE: +// +// 0x0: Divide by 1. +// 0x1: Divide by 2. +// 0x2: Divide by 4. +// ... +// 0xF: Divide by 32,768. +#define AUX_TIMER01_T1CFG_PRE_W 4 +#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T1CFG_PRE_S 4 + +// Field: [1] MODE +// +// Timer 1 mode. +// +// Configure source for Timer 1 prescaler. +// ENUMs: +// TICK Use event set by TICK_SRC as source for prescaler. +// CLK Use clock as source for prescaler. Note that +// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the +// clock frequency. +#define AUX_TIMER01_T1CFG_MODE 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_BITN 1 +#define AUX_TIMER01_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_S 1 +#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 + +// Field: [0] RELOAD +// +// Timer 1 reload mode. +// ENUMs: +// CONT Continuous mode. +// +// Timer 1 restarts when the +// counter value becomes equal to or greater than +// ( T1TARGET.VALUE - 1). +// MAN Manual mode. +// +// Timer 1 stops and +// T1CTL.EN becomes 0 when the counter value +// becomes equal to or greater than +// T1TARGET.VALUE. +#define AUX_TIMER01_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_S 0 +#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CTL +// +//***************************************************************************** +// Field: [0] EN +// +// Timer 1 enable. +// +// 0: Disable Timer 1. +// 1: Enable Timer 1. +// +// The counter restarts from 0 when you enable Timer 1. +#define AUX_TIMER01_T1CTL_EN 0x00000001 +#define AUX_TIMER01_T1CTL_EN_BITN 0 +#define AUX_TIMER01_T1CTL_EN_M 0x00000001 +#define AUX_TIMER01_T1CTL_EN_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 1 target value. +// +// Manual Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than VALUE. +// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter +// value is equal to or greater than VALUE. +// +// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 +// peripheral clock period. +// +// Continuous Reload Mode: +// - Timer 1 increments until the counter value becomes equal to or greater +// than ( VALUE - 1), then restarts from 0. +// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter +// value is 0, except for when you enable the timer. +// +// Note: When VALUE is less than 2, Timer 1 counter value remains 0. +// AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you +// enable the timer. +// +// +// It is allowed to update the VALUE while the timer runs. +#define AUX_TIMER01_T1TARGET_VALUE_W 16 +#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER01_O_T1CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Timer 1 counter value. +#define AUX_TIMER01_T1CNTR_VALUE_W 16 +#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1CNTR_VALUE_S 0 + + +#endif // __AUX_TIMER01__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer2.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer2.h new file mode 100644 index 00000000..e12d6cba --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_aux_timer2.h @@ -0,0 +1,2491 @@ +/****************************************************************************** +* Filename: hw_aux_timer2_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_AUX_TIMER2_H__ +#define __HW_AUX_TIMER2_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// AUX_TIMER2 component +// +//***************************************************************************** +// Timer Control +#define AUX_TIMER2_O_CTL 0x00000000 + +// Target +#define AUX_TIMER2_O_TARGET 0x00000004 + +// Shadow Target +#define AUX_TIMER2_O_SHDWTARGET 0x00000008 + +// Counter +#define AUX_TIMER2_O_CNTR 0x0000000C + +// Clock Prescaler Configuration +#define AUX_TIMER2_O_PRECFG 0x00000010 + +// Event Control +#define AUX_TIMER2_O_EVCTL 0x00000014 + +// Pulse Trigger +#define AUX_TIMER2_O_PULSETRIG 0x00000018 + +// Channel 0 Event Configuration +#define AUX_TIMER2_O_CH0EVCFG 0x00000080 + +// Channel 0 Capture Configuration +#define AUX_TIMER2_O_CH0CCFG 0x00000084 + +// Channel 0 Pipeline Capture Compare +#define AUX_TIMER2_O_CH0PCC 0x00000088 + +// Channel 0 Capture Compare +#define AUX_TIMER2_O_CH0CC 0x0000008C + +// Channel 1 Event Configuration +#define AUX_TIMER2_O_CH1EVCFG 0x00000090 + +// Channel 1 Capture Configuration +#define AUX_TIMER2_O_CH1CCFG 0x00000094 + +// Channel 1 Pipeline Capture Compare +#define AUX_TIMER2_O_CH1PCC 0x00000098 + +// Channel 1 Capture Compare +#define AUX_TIMER2_O_CH1CC 0x0000009C + +// Channel 2 Event Configuration +#define AUX_TIMER2_O_CH2EVCFG 0x000000A0 + +// Channel 2 Capture Configuration +#define AUX_TIMER2_O_CH2CCFG 0x000000A4 + +// Channel 2 Pipeline Capture Compare +#define AUX_TIMER2_O_CH2PCC 0x000000A8 + +// Channel 2 Capture Compare +#define AUX_TIMER2_O_CH2CC 0x000000AC + +// Channel 3 Event Configuration +#define AUX_TIMER2_O_CH3EVCFG 0x000000B0 + +// Channel 3 Capture Configuration +#define AUX_TIMER2_O_CH3CCFG 0x000000B4 + +// Channel 3 Pipeline Capture Compare +#define AUX_TIMER2_O_CH3PCC 0x000000B8 + +// Channel 3 Capture Compare +#define AUX_TIMER2_O_CH3CC 0x000000BC + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CTL +// +//***************************************************************************** +// Field: [6] CH3_RESET +// +// Channel 3 reset. +// +// 0: No effect. +// 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH3_RESET 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_BITN 6 +#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_S 6 + +// Field: [5] CH2_RESET +// +// Channel 2 reset. +// +// 0: No effect. +// 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH2_RESET 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_BITN 5 +#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_S 5 + +// Field: [4] CH1_RESET +// +// Channel 1 reset. +// +// 0: No effect. +// 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH1_RESET 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_BITN 4 +#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_S 4 + +// Field: [3] CH0_RESET +// +// Channel 0 reset. +// +// 0: No effect. +// 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. +// +// Read returns 0. +#define AUX_TIMER2_CTL_CH0_RESET 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_BITN 3 +#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_S 3 + +// Field: [2] TARGET_EN +// +// Select counter target value. +// +// You must select TARGET to use shadow target functionality. +// ENUMs: +// TARGET TARGET.VALUE +// CNTR_MAX 65535 +#define AUX_TIMER2_CTL_TARGET_EN 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_BITN 2 +#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_S 2 +#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 + +// Field: [1:0] MODE +// +// Timer mode control. +// +// The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or +// UPDWN_PER. +// +// When you write MODE all internally queued updates to [CHnCC.*] and TARGET +// clear. +// ENUMs: +// UPDWN_PER Count up and down periodically. The timer counts +// from 0 to target value and back to 0, +// repeatedly. +// +// Period = (target value * +// 2) * timer clock period +// UP_PER Count up periodically. The timer increments from 0 +// to target value, repeatedly. +// +// Period = (target value + +// 1) * timer clock period +// UP_ONCE Count up once. The timer increments from 0 to +// target value, then stops and sets MODE to DIS. +// DIS Disable timer. Updates to counter, channels, and +// events stop. +#define AUX_TIMER2_CTL_MODE_W 2 +#define AUX_TIMER2_CTL_MODE_M 0x00000003 +#define AUX_TIMER2_CTL_MODE_S 0 +#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 +#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 +#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 +#define AUX_TIMER2_CTL_MODE_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_TARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// 16 bit user defined counter target value, which is used when selected by +// CTL.TARGET_EN. +#define AUX_TIMER2_TARGET_VALUE_W 16 +#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_TARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_SHDWTARGET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Target value for next counter period. +// +// The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy +// does not happen when you restart the timer. +// +// This is useful to avoid period jitter in PWM applications with time-varying +// period, sometimes referenced as phase corrected PWM. +#define AUX_TIMER2_SHDWTARGET_VALUE_W 16 +#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_SHDWTARGET_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CNTR +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// 16 bit current counter value. +#define AUX_TIMER2_CNTR_VALUE_W 16 +#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CNTR_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_PRECFG +// +//***************************************************************************** +// Field: [7:0] CLKDIV +// +// Clock division. +// +// CLKDIV determines the timer clock frequency for counter, synchronization, +// and timer event updates. The timer clock frequency is the clock selected by +// AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the +// timer clock period. +// +// 0x00: Divide by 1. +// 0x01: Divide by 2. +// ... +// 0xFF: Divide by 256. +#define AUX_TIMER2_PRECFG_CLKDIV_W 8 +#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF +#define AUX_TIMER2_PRECFG_CLKDIV_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_EVCTL +// +//***************************************************************************** +// Field: [7] EV3_SET +// +// Set event 3. +// +// Write 1 to set event 3. +#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 +#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_S 7 + +// Field: [6] EV3_CLR +// +// Clear event 3. +// +// Write 1 to clear event 3. +#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 +#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_S 6 + +// Field: [5] EV2_SET +// +// Set event 2. +// +// Write 1 to set event 2. +#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 +#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_S 5 + +// Field: [4] EV2_CLR +// +// Clear event 2. +// +// Write 1 to clear event 2. +#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 +#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_S 4 + +// Field: [3] EV1_SET +// +// Set event 1. +// +// Write 1 to set event 1. +#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 +#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_S 3 + +// Field: [2] EV1_CLR +// +// Clear event 1. +// +// Write 1 to clear event 1. +#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 +#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_S 2 + +// Field: [1] EV0_SET +// +// Set event 0. +// +// Write 1 to set event 0. +#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 +#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_S 1 + +// Field: [0] EV0_CLR +// +// Clear event 0. +// +// Write 1 to clear event 0. +#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 +#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_PULSETRIG +// +//***************************************************************************** +// Field: [0] TRIG +// +// Pulse trigger. +// +// Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse +// width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. +#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 +#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 0 does not control event 3. +// 1: Channel 0 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 0 does not control event 2. +// 1: Channel 0 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 0 does not control event 1. +// 1: Channel 0 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 0 does not control event 0. +// 1: Channel 0 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH0CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH0CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH0CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH0CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH0CC.VALUE / TARGET.VALUE ). +// +// When CH0CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH0CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH0CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH0CCFG.CAPT_SRC relative to the signal edge +// given by CH0CCFG.EDGE. +// +// Set enabled events when +// CH0CC.VALUE contains signal period and +// CH0PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH0CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH0CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH0CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH0CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH0CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH0EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH0EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH0EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH0EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_S 0 +#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH0CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. +#define AUX_TIMER2_CH0PCC_VALUE_W 16 +#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH0CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH0EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH0CC_VALUE_W 16 +#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 1 does not control event 3. +// 1: Channel 1 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 1 does not control event 2. +// 1: Channel 1 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 1 does not control event 1. +// 1: Channel 1 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 1 does not control event 0. +// 1: Channel 1 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH1CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH1CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH1CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH1CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH1CC.VALUE / TARGET.VALUE ). +// +// When CH1CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH1CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH1CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH1CCFG.CAPT_SRC relative to the signal edge +// given by CH1CCFG.EDGE. +// +// Set enabled events when +// CH1CC.VALUE contains signal period and +// CH1PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH1CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH1CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH1CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH1CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH1CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH1EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH1EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH1EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH1EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_S 0 +#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH1CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. +#define AUX_TIMER2_CH1PCC_VALUE_W 16 +#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH1CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH1EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH1CC_VALUE_W 16 +#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 2 does not control event 3. +// 1: Channel 2 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 2 does not control event 2. +// 1: Channel 2 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 2 does not control event 1. +// 1: Channel 2 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 2 does not control event 0. +// 1: Channel 2 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH2CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH2CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH2CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH2CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH2CC.VALUE / TARGET.VALUE ). +// +// When CH2CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH2CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH2CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH2CCFG.CAPT_SRC relative to the signal edge +// given by CH2CCFG.EDGE. +// +// Set enabled events when +// CH2CC.VALUE contains signal period and +// CH2PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH2CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH2CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH2CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH2CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set to SET_ON_CAPT +// with no event enable. +// - Configure CH2CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH2EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH2EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function is: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH2EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH2EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_S 0 +#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH2CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. +#define AUX_TIMER2_CH2PCC_VALUE_W 16 +#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH2CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH2EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH2CC_VALUE_W 16 +#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2CC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3EVCFG +// +//***************************************************************************** +// Field: [7] EV3_GEN +// +// Event 3 enable. +// +// 0: Channel 3 does not control event 3. +// 1: Channel 3 controls event 3. +// +// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 + +// Field: [6] EV2_GEN +// +// Event 2 enable. +// +// 0: Channel 3 does not control event 2. +// 1: Channel 3 controls event 2. +// +// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 + +// Field: [5] EV1_GEN +// +// Event 1 enable. +// +// 0: Channel 3 does not control event 1. +// 1: Channel 3 controls event 1. +// +// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 + +// Field: [4] EV0_GEN +// +// Event 0 enable. +// +// 0: Channel 3 does not control event 0. +// 1: Channel 3 controls event 0. +// +// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. +#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 + +// Field: [3:0] CCACT +// +// Capture-Compare action. +// +// Capture-Compare action defines 15 different channel functions that utilize +// capture, compare, and zero events. +// ENUMs: +// PULSE_ON_CMP Pulse on compare repeatedly. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP Toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// SET_ON_CMP Set on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// CLR_ON_CMP Clear on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UP_PER +// for edge-aligned PWM generation. Duty cycle is +// given by: +// +// When CH3CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = +// CH3CC.VALUE / ( TARGET.VALUE + 1 ). +// +// When CH3CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 1. +// +// Enabled events are +// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// +// Set CTL.MODE to UPDWN_PER +// for center-aligned PWM generation. Duty cycle +// is given by: +// +// When CH3CC.VALUE <= +// TARGET.VALUE: +// Duty cycle = 1 - ( +// CH3CC.VALUE / TARGET.VALUE ). +// +// When CH3CC.VALUE > +// TARGET.VALUE: +// Duty cycle = 0. +// +// Enabled events are set +// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT Set on capture repeatedly. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH3CC.VALUE. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Select this function +// with no event enable. +// - Configure CH3CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// enable events. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. +// +// Continuously capture +// period and pulse width of the signal selected +// by CH3CCFG.CAPT_SRC relative to the signal edge +// given by CH3CCFG.EDGE. +// +// Set enabled events when +// CH3CC.VALUE contains signal period and +// CH3PCC.VALUE contains signal pulse width. +// +// Notes: +// - Make sure that you +// configure CH3CCFG.CAPT_SRC and CCACT when +// CTL.MODE equals DIS, then set CTL.MODE to +// UP_ONCE or UP_PER. +// - The counter restarts in +// the selected timer mode when CH3CC.VALUE +// contains the signal period. +// - If more than one +// channel uses this function, the channels will +// perform this function one at a time. The +// channel with lowest number has priority and +// performs the function first. Next measurement +// starts when current measurement completes +// successfully or times out. A timeout occurs +// when counter equals target. +// - If you want to observe +// a timeout event configure another channel to +// SET_ON_CAPT. +// +// Signal property +// requirements: +// - Signal Period >= 2 * ( +// 1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal Period <= 65535 +// * (1 + PRECFG.CLKDIV ) * timer clock period. +// - Signal low and high +// phase >= (1 + PRECFG.CLKDIV ) * timer clock +// period. +// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. +// +// Channel function +// sequence: +// - Pulse enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// The event is high for +// two timer clock periods. +// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. +// +// Channel function +// sequence: +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_CMP_DIS Set on compare, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// CLR_ON_CMP_DIS Clear on compare, and then disable channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Set enabled events when +// CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are +// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = +// 0. +// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable +// channel. +// +// Channel function +// sequence: +// - Clear enabled events +// when CNTR.VALUE = 0. +// - Toggle enabled events +// when CH3CC.VALUE = CNTR.VALUE. +// - Disable channel. +// +// Enabled events are set +// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. +// SET_ON_CAPT_DIS Set on capture, and then disable channel. +// +// Channel function +// sequence: +// - Set enabled events on +// capture event and copy CNTR.VALUE to +// CH3CC.VALUE. +// - Disable channel. +// +// Primary use scenario is +// to select this function before you start the +// timer. +// Follow these steps if you +// need to select this function while CTL.MODE is +// different from DIS: +// - Set CCACT to +// SET_ON_CAPT with no event enable. +// - Configure CH3CCFG +// (optional). +// - Wait for three timer +// clock periods as defined in PRECFG before you +// set CCACT to SET_ON_CAPT_DIS. Event enable is +// optional. +// +// These steps prevent +// capture events caused by expired signal values +// in edge-detection circuit. +// DIS Disable channel. +#define AUX_TIMER2_CH3EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3CCFG +// +//***************************************************************************** +// Field: [6:1] CAPT_SRC +// +// Select capture signal source from the asynchronous AUX event bus. +// +// The selected signal enters the edge-detection circuit. False capture events +// can occur when: +// - the edge-detection circuit contains expired signal samples and the circuit +// is enabled without flush as described in CH3EVCFG +// - this register is reconfigured while CTL.MODE is different from DIS. +// +// You can avoid false capture events. When wanted channel function: +// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. +// - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. +// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in +// CH3EVCFG.CCACT. +// +// If you write a non-enumerated value the behavior is identical to NO_EVENT. +// The written value is returned when read. +// ENUMs: +// NO_EVENT No event. +// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE +// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY +// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ +// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE +// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N +// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE +// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV +// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV +// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 +// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB +// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA +// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 +// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 +// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV +// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF +// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE +// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE +// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN +// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF +// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD +// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD +// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ +// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY +// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 +// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV +// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 +// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 +// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 +// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 +// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 +// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 +// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 +// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 +// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 +// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 +// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 +// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 +// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 +// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 +// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 +// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 +// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 +// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 +// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 +// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 +// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 +// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 +// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 +// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 +// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 +// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 +// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 +// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 +// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 +// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 +// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 +// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 + +// Field: [0] EDGE +// +// Edge configuration. +// +// Channel captures counter value at selected edge on signal source selected by +// CAPT_SRC. See CH3EVCFG.CCACT. +// ENUMs: +// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. +// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. +#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_S 0 +#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3PCC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Pipeline Capture Compare value. +// +// 16-bit user defined pipeline compare value or channel-updated capture value. +// +// Compare mode: +// An update of VALUE will be transferred to CH3CC.VALUE when the next +// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for +// PWM generation and prevents jitter on the edges of the generated signal. +// +// Capture mode: +// When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the +// width of the low or high phase of the selected signal. This is specified by +// CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. +#define AUX_TIMER2_CH3PCC_VALUE_W 16 +#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3PCC_VALUE_S 0 + +//***************************************************************************** +// +// Register: AUX_TIMER2_O_CH3CC +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Capture Compare value. +// +// 16-bit user defined compare value or channel-updated capture value. +// +// Compare mode: +// VALUE is compared against CNTR.VALUE and an event is generated as specified +// by CH3EVCFG.CCACT when these are equal. +// +// Capture mode: +// The current counter value is stored in VALUE when a capture event occurs. +// CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture +// value. +#define AUX_TIMER2_CH3CC_VALUE_W 16 +#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3CC_VALUE_S 0 + + +#endif // __AUX_TIMER2__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg.h new file mode 100644 index 00000000..59d9895f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg.h @@ -0,0 +1,1934 @@ +/****************************************************************************** +* Filename: hw_ccfg_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_H__ +#define __HW_CCFG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CCFG component +// +//***************************************************************************** +// Extern LF clock configuration +#define CCFG_O_EXT_LF_CLK 0x00001FA8 + +// Mode Configuration 1 +#define CCFG_O_MODE_CONF_1 0x00001FAC + +// CCFG Size and Disable Flags +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 + +// Mode Configuration 0 +#define CCFG_O_MODE_CONF 0x00001FB4 + +// Voltage Load 0 +#define CCFG_O_VOLT_LOAD_0 0x00001FB8 + +// Voltage Load 1 +#define CCFG_O_VOLT_LOAD_1 0x00001FBC + +// Real Time Clock Offset +#define CCFG_O_RTC_OFFSET 0x00001FC0 + +// Frequency Offset +#define CCFG_O_FREQ_OFFSET 0x00001FC4 + +// IEEE MAC Address 0 +#define CCFG_O_IEEE_MAC_0 0x00001FC8 + +// IEEE MAC Address 1 +#define CCFG_O_IEEE_MAC_1 0x00001FCC + +// IEEE BLE Address 0 +#define CCFG_O_IEEE_BLE_0 0x00001FD0 + +// IEEE BLE Address 1 +#define CCFG_O_IEEE_BLE_1 0x00001FD4 + +// Bootloader Configuration +#define CCFG_O_BL_CONFIG 0x00001FD8 + +// Erase Configuration +#define CCFG_O_ERASE_CONF 0x00001FDC + +// TI Options +#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 + +// Test Access Points Enable 0 +#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 + +// Test Access Points Enable 1 +#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 + +// Image Valid +#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC + +// Protect Sectors 0-31 +#define CCFG_O_CCFG_PROT_31_0 0x00001FF0 + +// Protect Sectors 32-63 +#define CCFG_O_CCFG_PROT_63_32 0x00001FF4 + +// Protect Sectors 64-95 +#define CCFG_O_CCFG_PROT_95_64 0x00001FF8 + +// Protect Sectors 96-127 +#define CCFG_O_CCFG_PROT_127_96 0x00001FFC + +//***************************************************************************** +// +// Register: CCFG_O_EXT_LF_CLK +// +//***************************************************************************** +// Field: [31:24] DIO +// +// Unsigned integer, selecting the DIO to supply external 32 kHz clock as +// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO +// will be marked as reserved by the pin driver (TI-RTOS environment) and hence +// not selectable for other usage. +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 + +// Field: [23:0] RTC_INCREMENT +// +// Unsigned integer, defining the input frequency of the external clock and is +// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: +// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: +// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF_1 +// +//***************************************************************************** +// Field: [31] TCXO_TYPE +// +// Selects the TCXO type. +// +// 0: CMOS type. Internal common-mode bias will not be enabled. +// 1: Clipped-sine type. Internal common-mode bias will be enabled when TCXO is +// used. +// +// Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. +#define CCFG_MODE_CONF_1_TCXO_TYPE 0x80000000 +#define CCFG_MODE_CONF_1_TCXO_TYPE_BITN 31 +#define CCFG_MODE_CONF_1_TCXO_TYPE_M 0x80000000 +#define CCFG_MODE_CONF_1_TCXO_TYPE_S 31 + +// Field: [30:24] TCXO_MAX_START +// +// Maximum TCXO startup time in units of 100us. +// Bit field value is only valid if MODE_CONF.XOSC_FREQ=0. +#define CCFG_MODE_CONF_1_TCXO_MAX_START_W 7 +#define CCFG_MODE_CONF_1_TCXO_MAX_START_M 0x7F000000 +#define CCFG_MODE_CONF_1_TCXO_MAX_START_S 24 + +// Field: [23:20] ALT_DCDC_VMIN +// +// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is +// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// Voltage = (28 + ALT_DCDC_VMIN) / 16. +// 0: 1.75V +// 1: 1.8125V +// ... +// 14: 2.625V +// 15: 2.6875V +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 + +// Field: [19] ALT_DCDC_DITHER_EN +// +// Enable DC/DC dithering if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). +// 0: Dither disable +// 1: Dither enable +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 + +// Field: [18:16] ALT_DCDC_IPEAK +// +// Inductor peak current if alternate DC/DC setting is enabled +// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external +// inductor! +// +// 0: 46mA (min) +// ... +// 4: 70mA +// ... +// 7: 87mA (max) +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 + +// Field: [15:12] DELTA_IBIAS_INIT +// +// Signed delta value for IBIAS_INIT. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 + +// Field: [11:8] DELTA_IBIAS_OFFSET +// +// Signed delta value for IBIAS_OFFSET. Delta value only applies if +// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 + +// Field: [7:0] XOSC_MAX_START +// +// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. +// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_SIZE_AND_DIS_FLAGS +// +//***************************************************************************** +// Field: [31:16] SIZE_OF_CCFG +// +// Total size of CCFG in bytes. +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 + +// Field: [15:4] DISABLE_FLAGS +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 + +// Field: [3] DIS_TCXO +// +// Deprecated. Must be set to 1. +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 + +// Field: [2] DIS_GPRAM +// +// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). +// 0: GPRAM is enabled and hence CACHE disabled. +// 1: GPRAM is disabled and instead CACHE is enabled (default). +// Notes: +// - Disabling CACHE will reduce CPU execution speed (up to 60%). +// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if +// enabled. +// See: +// VIMS:CTL.MODE +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 + +// Field: [1] DIS_ALT_DCDC_SETTING +// +// Disable alternate DC/DC settings. +// 0: Enable alternate DC/DC settings. +// 1: Disable alternate DC/DC settings. +// See: +// MODE_CONF_1.ALT_DCDC_VMIN +// MODE_CONF_1.ALT_DCDC_DITHER_EN +// MODE_CONF_1.ALT_DCDC_IPEAK +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 + +// Field: [0] DIS_XOSC_OVR +// +// Disable XOSC override functionality. +// 0: Enable XOSC override functionality. +// 1: Disable XOSC override functionality. +// See: +// MODE_CONF_1.DELTA_IBIAS_INIT +// MODE_CONF_1.DELTA_IBIAS_OFFSET +// MODE_CONF_1.XOSC_MAX_START +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_MODE_CONF +// +//***************************************************************************** +// Field: [31:28] VDDR_TRIM_SLEEP_DELTA +// +// Signed delta value to apply to the +// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. +// 0x8 (-8) : Delta = -7 +// ... +// 0xF (-1) : Delta = 0 +// 0x0 (0) : Delta = +1 +// ... +// 0x7 (7) : Delta = +8 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 + +// Field: [27] DCDC_RECHARGE +// +// DC/DC during recharge in powerdown. +// 0: Use the DC/DC during recharge in powerdown. +// 1: Do not use the DC/DC during recharge in powerdown (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 + +// Field: [26] DCDC_ACTIVE +// +// DC/DC in active mode. +// 0: Use the DC/DC during active mode. +// 1: Do not use the DC/DC during active mode (default). +// +// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must +// be called regularly to apply this field (handled automatically if using TI +// RTOS!). +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 + +// Field: [25] VDDR_EXT_LOAD +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 + +// Field: [24] VDDS_BOD_LEVEL +// +// VDDS BOD level. +// 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum +// PA output power on CC13xx). +// 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 + +// Field: [23:22] SCLK_LF_OPTION +// +// Select source for SCLK_LF. +// ENUMs: +// RCOSC_LF Low frequency RCOSC (default) +// XOSC_LF 32.768kHz low frequency XOSC +// EXTERNAL_LF External low frequency clock on DIO defined by +// EXT_LF_CLK.DIO. The RTC tick speed +// AON_RTC:SUBSECINC is updated to +// EXT_LF_CLK.RTC_INCREMENT (done in the +// SetupTrimDevice() driverlib boot function). +// External clock must always be running when the +// chip is in standby for VDDR recharge timing. +// XOSC_HF_DLF 31.25kHz clock derived from 48MHz XOSC or HPOSC. +// The RTC tick speed AON_RTC:SUBSECINC is updated +// to 0x8637BD, corresponding to a 31.25kHz clock +// (done in the SetupTrimDevice() driverlib boot +// function). The device must be blocked from +// entering Standby mode when using this clock +// source. +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 + +// Field: [21] VDDR_TRIM_SLEEP_TC +// +// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated +// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time +// standby mode is entered. This improves low-temperature RCOSC_LF frequency +// stability in standby mode. +// +// When temperature compensation is performed, the delta is calculates this +// way: +// Delta = max (delta, min(8, floor(62-temp)/8)) +// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current +// temperature in degrees C. +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 + +// Field: [20] RTC_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 + +// Field: [19:18] XOSC_FREQ +// +// Selects which high frequency oscillator is used (required for radio usage). +// ENUMs: +// 24M 24 MHz XOSC_HF. Not supported. +// 48M 48 MHz XOSC_HF +// HPOSC Internal high precision oscillator. +// TCXO External 48 Mhz TCXO. +// Refer to +// MODE_CONF_1.TCXO_MAX_START and +// MODE_CONF_1.TCXO_TYPE bit fields for additional +// configuration of TCXO. +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 +#define CCFG_MODE_CONF_XOSC_FREQ_TCXO 0x00000000 + +// Field: [17] XOSC_CAP_MOD +// +// Enable modification (delta) to XOSC cap-array. Value specified in +// XOSC_CAPARRAY_DELTA. +// 0: Apply cap-array delta +// 1: Do not apply cap-array delta (default) +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 + +// Field: [16] HF_COMP +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 + +// Field: [15:8] XOSC_CAPARRAY_DELTA +// +// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. +// Enabled by XOSC_CAP_MOD. +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 + +// Field: [7:0] VDDR_CAP +// +// Unsigned 8-bit integer, representing the minimum decoupling capacitance +// (worst case) on VDDR, in units of 100nF. This should take into account +// capacitor tolerance and voltage dependent capacitance variation. This bit +// affects the recharge period calculation when going into powerdown or +// standby. +// +// NOTE! If using the following functions this field must be configured (used +// by TI RTOS): +// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_0 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP45 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 + +// Field: [23:16] VDDR_EXT_TP25 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 + +// Field: [15:8] VDDR_EXT_TP5 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 + +// Field: [7:0] VDDR_EXT_TM15 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_VOLT_LOAD_1 +// +//***************************************************************************** +// Field: [31:24] VDDR_EXT_TP125 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 + +// Field: [23:16] VDDR_EXT_TP105 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 + +// Field: [15:8] VDDR_EXT_TP85 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 + +// Field: [7:0] VDDR_EXT_TP65 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_RTC_OFFSET +// +//***************************************************************************** +// Field: [31:16] RTC_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 + +// Field: [15:8] RTC_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 + +// Field: [7:0] RTC_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HF_COMP_P0 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 + +// Field: [15:8] HF_COMP_P1 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 + +// Field: [7:0] HF_COMP_P2 +// +// Reserved for future use. Software should not rely on the value of a +// reserved. Writing any other value than the reset/default value may result in +// undefined behavior. +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_MAC_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE MAC address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[31:0] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IEEE_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Bits[63:32] of the 64-bits custom IEEE BLE address. +// If different from 0xFFFFFFFF then the value of this field is applied; +// otherwise use value from FCFG. +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_BL_CONFIG +// +//***************************************************************************** +// Field: [31:24] BOOTLOADER_ENABLE +// +// Bootloader enable. Boot loader can be accessed if +// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and +// conditions for boot loader backdoor are met). +// 0xC5: Boot loader is enabled. +// Any other value: Boot loader is disabled. +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 + +// Field: [16] BL_LEVEL +// +// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot +// loader backdoor is enabled by the BL_ENABLE field. +// 0: Active low. +// 1: Active high. +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 + +// Field: [15:8] BL_PIN_NUMBER +// +// DIO number that is level checked if the boot loader backdoor is enabled by +// the BL_ENABLE field. +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 + +// Field: [7:0] BL_ENABLE +// +// Enables the boot loader backdoor. +// 0xC5: Boot loader backdoor is enabled. +// Any other value: Boot loader backdoor is disabled. +// +// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader +// backdoor is enabled. +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_ERASE_CONF +// +//***************************************************************************** +// Field: [8] CHIP_ERASE_DIS_N +// +// Chip erase. +// This bit controls if a chip erase requested through the JTAG WUC TAP will be +// ignored in a following boot caused by a reset of the MCU VD. +// A successful chip erase operation will force the content of the flash main +// bank back to the state as it was when delivered by TI. +// 0: Disable. Any chip erase request detected during boot will be ignored. +// 1: Enable. Any chip erase request detected during boot will be performed by +// the boot FW. +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 + +// Field: [0] BANK_ERASE_DIS_N +// +// Bank erase. +// This bit controls if the ROM serial boot loader will accept a received Bank +// Erase command (COMMAND_BANK_ERASE). +// A successful Bank Erase operation will erase all main bank sectors not +// protected by write protect configuration bits in CCFG. +// 0: Disable the boot loader bank erase function. +// 1: Enable the boot loader bank erase function. +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TI_OPTIONS +// +//***************************************************************************** +// Field: [7:0] TI_FA_ENABLE +// +// TI Failure Analysis. +// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) +// option with the unlock code. +// All other values: Disable the functionality of unlocking the TI FA option +// with the unlock code. +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_0 +// +//***************************************************************************** +// Field: [23:16] CPU_DAP_ENABLE +// +// Enable CPU DAP. +// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM +// boot FW. +// Any other value: Main CPU DAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 + +// Field: [15:8] PWRPROF_TAP_ENABLE +// +// Enable PWRPROF TAP. +// 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PWRPROF TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 + +// Field: [7:0] TEST_TAP_ENABLE +// +// Enable Test TAP. +// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: TEST TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_TAP_DAP_1 +// +//***************************************************************************** +// Field: [23:16] PBIST2_TAP_ENABLE +// +// Enable PBIST2 TAP. +// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST2 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 + +// Field: [15:8] PBIST1_TAP_ENABLE +// +// Enable PBIST1 TAP. +// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot +// FW if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: PBIST1 TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 + +// Field: [7:0] AON_TAP_ENABLE +// +// Enable AON TAP +// 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW +// if enabled by corresponding configuration value in FCFG1 defined by TI. +// Any other value: AON TAP access will remain disabled out of +// power-up/system-reset. +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_IMAGE_VALID_CONF +// +//***************************************************************************** +// Field: [31:0] IMAGE_VALID +// +// This field must have the address value of the start of the flash vector +// table in order to enable the boot FW in ROM to transfer control to a flash +// image. +// Any illegal vector table start address value will force the boot FW in ROM +// to transfer control to the serial boot loader in ROM. +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_31_0 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_31 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 + +// Field: [30] WRT_PROT_SEC_30 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 + +// Field: [29] WRT_PROT_SEC_29 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 + +// Field: [28] WRT_PROT_SEC_28 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 + +// Field: [27] WRT_PROT_SEC_27 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 + +// Field: [26] WRT_PROT_SEC_26 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 + +// Field: [25] WRT_PROT_SEC_25 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 + +// Field: [24] WRT_PROT_SEC_24 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 + +// Field: [23] WRT_PROT_SEC_23 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 + +// Field: [22] WRT_PROT_SEC_22 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 + +// Field: [21] WRT_PROT_SEC_21 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 + +// Field: [20] WRT_PROT_SEC_20 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 + +// Field: [19] WRT_PROT_SEC_19 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 + +// Field: [18] WRT_PROT_SEC_18 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 + +// Field: [17] WRT_PROT_SEC_17 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 + +// Field: [16] WRT_PROT_SEC_16 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 + +// Field: [15] WRT_PROT_SEC_15 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 + +// Field: [14] WRT_PROT_SEC_14 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 + +// Field: [13] WRT_PROT_SEC_13 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 + +// Field: [12] WRT_PROT_SEC_12 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 + +// Field: [11] WRT_PROT_SEC_11 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 + +// Field: [10] WRT_PROT_SEC_10 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 + +// Field: [9] WRT_PROT_SEC_9 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 + +// Field: [8] WRT_PROT_SEC_8 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 + +// Field: [7] WRT_PROT_SEC_7 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 + +// Field: [6] WRT_PROT_SEC_6 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 + +// Field: [5] WRT_PROT_SEC_5 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 + +// Field: [4] WRT_PROT_SEC_4 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 + +// Field: [3] WRT_PROT_SEC_3 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 + +// Field: [2] WRT_PROT_SEC_2 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 + +// Field: [1] WRT_PROT_SEC_1 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 + +// Field: [0] WRT_PROT_SEC_0 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_63_32 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_63 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 + +// Field: [30] WRT_PROT_SEC_62 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 + +// Field: [29] WRT_PROT_SEC_61 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 + +// Field: [28] WRT_PROT_SEC_60 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 + +// Field: [27] WRT_PROT_SEC_59 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 + +// Field: [26] WRT_PROT_SEC_58 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 + +// Field: [25] WRT_PROT_SEC_57 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 + +// Field: [24] WRT_PROT_SEC_56 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 + +// Field: [23] WRT_PROT_SEC_55 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 + +// Field: [22] WRT_PROT_SEC_54 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 + +// Field: [21] WRT_PROT_SEC_53 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 + +// Field: [20] WRT_PROT_SEC_52 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 + +// Field: [19] WRT_PROT_SEC_51 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 + +// Field: [18] WRT_PROT_SEC_50 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 + +// Field: [17] WRT_PROT_SEC_49 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 + +// Field: [16] WRT_PROT_SEC_48 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 + +// Field: [15] WRT_PROT_SEC_47 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 + +// Field: [14] WRT_PROT_SEC_46 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 + +// Field: [13] WRT_PROT_SEC_45 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 + +// Field: [12] WRT_PROT_SEC_44 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 + +// Field: [11] WRT_PROT_SEC_43 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 + +// Field: [10] WRT_PROT_SEC_42 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 + +// Field: [9] WRT_PROT_SEC_41 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 + +// Field: [8] WRT_PROT_SEC_40 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 + +// Field: [7] WRT_PROT_SEC_39 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 + +// Field: [6] WRT_PROT_SEC_38 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 + +// Field: [5] WRT_PROT_SEC_37 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 + +// Field: [4] WRT_PROT_SEC_36 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 + +// Field: [3] WRT_PROT_SEC_35 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 + +// Field: [2] WRT_PROT_SEC_34 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 + +// Field: [1] WRT_PROT_SEC_33 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 + +// Field: [0] WRT_PROT_SEC_32 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_95_64 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_95 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 + +// Field: [30] WRT_PROT_SEC_94 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 + +// Field: [29] WRT_PROT_SEC_93 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 + +// Field: [28] WRT_PROT_SEC_92 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 + +// Field: [27] WRT_PROT_SEC_91 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 + +// Field: [26] WRT_PROT_SEC_90 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 + +// Field: [25] WRT_PROT_SEC_89 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 + +// Field: [24] WRT_PROT_SEC_88 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 + +// Field: [23] WRT_PROT_SEC_87 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 + +// Field: [22] WRT_PROT_SEC_86 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 + +// Field: [21] WRT_PROT_SEC_85 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 + +// Field: [20] WRT_PROT_SEC_84 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 + +// Field: [19] WRT_PROT_SEC_83 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 + +// Field: [18] WRT_PROT_SEC_82 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 + +// Field: [17] WRT_PROT_SEC_81 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 + +// Field: [16] WRT_PROT_SEC_80 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 + +// Field: [15] WRT_PROT_SEC_79 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 + +// Field: [14] WRT_PROT_SEC_78 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 + +// Field: [13] WRT_PROT_SEC_77 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 + +// Field: [12] WRT_PROT_SEC_76 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 + +// Field: [11] WRT_PROT_SEC_75 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 + +// Field: [10] WRT_PROT_SEC_74 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 + +// Field: [9] WRT_PROT_SEC_73 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 + +// Field: [8] WRT_PROT_SEC_72 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 + +// Field: [7] WRT_PROT_SEC_71 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 + +// Field: [6] WRT_PROT_SEC_70 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 + +// Field: [5] WRT_PROT_SEC_69 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 + +// Field: [4] WRT_PROT_SEC_68 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 + +// Field: [3] WRT_PROT_SEC_67 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 + +// Field: [2] WRT_PROT_SEC_66 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 + +// Field: [1] WRT_PROT_SEC_65 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 + +// Field: [0] WRT_PROT_SEC_64 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 + +//***************************************************************************** +// +// Register: CCFG_O_CCFG_PROT_127_96 +// +//***************************************************************************** +// Field: [31] WRT_PROT_SEC_127 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 + +// Field: [30] WRT_PROT_SEC_126 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 + +// Field: [29] WRT_PROT_SEC_125 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 + +// Field: [28] WRT_PROT_SEC_124 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 + +// Field: [27] WRT_PROT_SEC_123 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 + +// Field: [26] WRT_PROT_SEC_122 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 + +// Field: [25] WRT_PROT_SEC_121 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 + +// Field: [24] WRT_PROT_SEC_120 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 + +// Field: [23] WRT_PROT_SEC_119 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 + +// Field: [22] WRT_PROT_SEC_118 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 + +// Field: [21] WRT_PROT_SEC_117 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 + +// Field: [20] WRT_PROT_SEC_116 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 + +// Field: [19] WRT_PROT_SEC_115 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 + +// Field: [18] WRT_PROT_SEC_114 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 + +// Field: [17] WRT_PROT_SEC_113 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 + +// Field: [16] WRT_PROT_SEC_112 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 + +// Field: [15] WRT_PROT_SEC_111 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 + +// Field: [14] WRT_PROT_SEC_110 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 + +// Field: [13] WRT_PROT_SEC_109 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 + +// Field: [12] WRT_PROT_SEC_108 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 + +// Field: [11] WRT_PROT_SEC_107 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 + +// Field: [10] WRT_PROT_SEC_106 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 + +// Field: [9] WRT_PROT_SEC_105 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 + +// Field: [8] WRT_PROT_SEC_104 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 + +// Field: [7] WRT_PROT_SEC_103 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 + +// Field: [6] WRT_PROT_SEC_102 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 + +// Field: [5] WRT_PROT_SEC_101 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 + +// Field: [4] WRT_PROT_SEC_100 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 + +// Field: [3] WRT_PROT_SEC_99 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 + +// Field: [2] WRT_PROT_SEC_98 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 + +// Field: [1] WRT_PROT_SEC_97 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 + +// Field: [0] WRT_PROT_SEC_96 +// +// 0: Sector protected +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 + + +#endif // __CCFG__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg_simple_struct.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg_simple_struct.h new file mode 100644 index 00000000..471bc99d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ccfg_simple_struct.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* Filename: hw_ccfg_simple_struct_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ +#define __HW_CCFG_SIMPLE_STRUCT_H__ + +//***************************************************************************** +// +// Customer configuration (ccfg) typedef. +// The implementation of this struct is required by device ROM boot code +// and must be placed at the end of flash. Do not modify this struct! +// +//***************************************************************************** +typedef struct +{ // Mapped to address + uint32_t CCFG_EXT_LF_CLK ; // 0x50004FA8 + uint32_t CCFG_MODE_CONF_1 ; // 0x50004FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50004FB0 + uint32_t CCFG_MODE_CONF ; // 0x50004FB4 + uint32_t CCFG_VOLT_LOAD_0 ; // 0x50004FB8 + uint32_t CCFG_VOLT_LOAD_1 ; // 0x50004FBC + uint32_t CCFG_RTC_OFFSET ; // 0x50004FC0 + uint32_t CCFG_FREQ_OFFSET ; // 0x50004FC4 + uint32_t CCFG_IEEE_MAC_0 ; // 0x50004FC8 + uint32_t CCFG_IEEE_MAC_1 ; // 0x50004FCC + uint32_t CCFG_IEEE_BLE_0 ; // 0x50004FD0 + uint32_t CCFG_IEEE_BLE_1 ; // 0x50004FD4 + uint32_t CCFG_BL_CONFIG ; // 0x50004FD8 + uint32_t CCFG_ERASE_CONF ; // 0x50004FDC + uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50004FE0 + uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50004FE4 + uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50004FE8 + uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50004FEC + uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50004FF0 + uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50004FF4 + uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50004FF8 + uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50004FFC +} ccfg_t; + +//***************************************************************************** +// +// Define the extern ccfg structure (__ccfg) +// +//***************************************************************************** +extern const ccfg_t __ccfg; + + +#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_chip_def.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_chip_def.h new file mode 100644 index 00000000..847994bf --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_chip_def.h @@ -0,0 +1,232 @@ +/****************************************************************************** +* Filename: hw_chip_def.h +* +* Description: Defines for device properties. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +//! \addtogroup config_api +//! @{ +// +//***************************************************************************** + +#ifndef __HW_CHIP_DEF_H__ +#define __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Define CC_CHIP_ID code used in the following macros defined at the bottom: +// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV +// +//***************************************************************************** +/* CC2620F128 */ +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) + #define CC_CHIP_ID 0x26200720 +#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) + #define CC_CHIP_ID 0x26200520 +#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) + #define CC_CHIP_ID 0x26200420 +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) + #define CC_CHIP_ID 0x26200020 +#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) + #define CC_CHIP_ID 0x26200722 +#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) + #define CC_CHIP_ID 0x26200522 +#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) + #define CC_CHIP_ID 0x26200422 +#elif defined(CC2620F128_R22) || defined(CC2620F128) + #define CC_CHIP_ID 0x26200022 +/* CC2630F128 */ +#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) + #define CC_CHIP_ID 0x26300720 +#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) + #define CC_CHIP_ID 0x26300520 +#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) + #define CC_CHIP_ID 0x26300420 +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) + #define CC_CHIP_ID 0x26300020 +#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) + #define CC_CHIP_ID 0x26300722 +#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) + #define CC_CHIP_ID 0x26300522 +#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) + #define CC_CHIP_ID 0x26300422 +#elif defined(CC2630F128_R22) || defined(CC2630F128) + #define CC_CHIP_ID 0x26300022 +/* CC2640F128 */ +#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) + #define CC_CHIP_ID 0x26400720 +#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) + #define CC_CHIP_ID 0x26400520 +#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) + #define CC_CHIP_ID 0x26400420 +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) + #define CC_CHIP_ID 0x26400020 +#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) + #define CC_CHIP_ID 0x26400722 +#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) + #define CC_CHIP_ID 0x26400522 +#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) + #define CC_CHIP_ID 0x26400422 +#elif defined(CC2640F128_R22) || defined(CC2640F128) + #define CC_CHIP_ID 0x26400022 +/* CC2650F128 */ +#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) + #define CC_CHIP_ID 0x26500720 +#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) + #define CC_CHIP_ID 0x26500520 +#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) + #define CC_CHIP_ID 0x26500420 +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) + #define CC_CHIP_ID 0x26500020 +#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) + #define CC_CHIP_ID 0x26500722 +#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) + #define CC_CHIP_ID 0x26500522 +#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) + #define CC_CHIP_ID 0x26500422 +#elif defined(CC2650F128_R22) || defined(CC2650F128) + #define CC_CHIP_ID 0x26500022 +/* CC2650L128 (OTP) */ +#elif defined(CC2650L128) + #define CC_CHIP_ID 0x26501710 +/* CC1310F128 */ +#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) + #define CC_CHIP_ID 0x13100720 +#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) + #define CC_CHIP_ID 0x13100520 +#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) + #define CC_CHIP_ID 0x13100420 +#elif defined(CC1310F128_R20) || defined(CC1310F128) + #define CC_CHIP_ID 0x13100020 +/* CC1350F128 */ +#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) + #define CC_CHIP_ID 0x13500720 +#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) + #define CC_CHIP_ID 0x13500520 +#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) + #define CC_CHIP_ID 0x13500420 +#elif defined(CC1350F128_R20) || defined(CC1350F128) + #define CC_CHIP_ID 0x13500020 +/* CC2640R2F */ +#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) + #define CC_CHIP_ID 0x26401710 +#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) + #define CC_CHIP_ID 0x26401510 +#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) + #define CC_CHIP_ID 0x26401410 +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) + #define CC_CHIP_ID 0x26401010 +/* CC2652R1F */ +#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) + #define CC_CHIP_ID 0x26523710 +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) + #define CC_CHIP_ID 0x26523010 +/* CC2644R1F */ +#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) + #define CC_CHIP_ID 0x26443710 +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) + #define CC_CHIP_ID 0x26443010 +/* CC2642R1F */ +#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) + #define CC_CHIP_ID 0x26423710 +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) + #define CC_CHIP_ID 0x26423010 +/* CC1354R1F */ +#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) + #define CC_CHIP_ID 0x13543710 +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) + #define CC_CHIP_ID 0x13543010 +/* CC1352R1F */ +#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) + #define CC_CHIP_ID 0x13523710 +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) + #define CC_CHIP_ID 0x13523010 +/* CC1312R1F */ +#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) + #define CC_CHIP_ID 0x13123710 +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) + #define CC_CHIP_ID 0x13123010 +#endif + +#define CC_GET_CHIP_FAMILY 0x26 +#define CC_GET_CHIP_OPTION 0x5 +#define CC_GET_CHIP_HWREV 0x10 + +#ifdef CC_CHIP_ID + /* Define chip package only if specified */ + #if (CC_CHIP_ID & 0x00000F00) != 0 + #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) + #endif + + /* Define chip device */ + #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) + + /* The chip family, option and package shall match the DriverLib release */ + #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) + #error "Specified chip option does not match DriverLib release" + #endif + #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) + #error "Specified chip hardware revision does not match DriverLib release" + #endif +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __HW_CHIP_DEF_H__ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_dwt.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_dwt.h new file mode 100644 index 00000000..322dfa48 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_dwt.h @@ -0,0 +1,856 @@ +/****************************************************************************** +* Filename: hw_cpu_dwt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + + +#endif // __CPU_DWT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_fpb.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_fpb.h new file mode 100644 index 00000000..73466f9c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_fpb.h @@ -0,0 +1,443 @@ +/****************************************************************************** +* Filename: hw_cpu_fpb_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_FPB_H__ +#define __HW_CPU_FPB_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_FPB component +// +//***************************************************************************** +// Control +#define CPU_FPB_O_CTRL 0x00000000 + +// Remap +#define CPU_FPB_O_REMAP 0x00000004 + +// Comparator 0 +#define CPU_FPB_O_COMP0 0x00000008 + +// Comparator 1 +#define CPU_FPB_O_COMP1 0x0000000C + +// Comparator 2 +#define CPU_FPB_O_COMP2 0x00000010 + +// Comparator 3 +#define CPU_FPB_O_COMP3 0x00000014 + +// Comparator 4 +#define CPU_FPB_O_COMP4 0x00000018 + +// Comparator 5 +#define CPU_FPB_O_COMP5 0x0000001C + +// Comparator 6 +#define CPU_FPB_O_COMP6 0x00000020 + +// Comparator 7 +#define CPU_FPB_O_COMP7 0x00000024 + +//***************************************************************************** +// +// Register: CPU_FPB_O_CTRL +// +//***************************************************************************** +// Field: [13:12] NUM_CODE2 +// +// Number of full banks of code comparators, sixteen comparators per bank. +// Where less than sixteen code comparators are provided, the bank count is +// zero, and the number present indicated by NUM_CODE1. This read only field +// contains 3'b000 to indicate 0 banks for Cortex-M processor. +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 + +// Field: [11:8] NUM_LIT +// +// Number of literal slots field. +// +// 0x0: No literal slots +// 0x2: Two literal slots +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 + +// Field: [7:4] NUM_CODE1 +// +// Number of code slots field. +// +// 0x0: No code slots +// 0x2: Two code slots +// 0x6: Six code slots +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 + +// Field: [1] KEY +// +// Key field. In order to write to this register, this bit-field must be +// written to '1'. This bit always reads 0. +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 + +// Field: [0] ENABLE +// +// Flash patch unit enable bit +// +// 0x0: Flash patch unit disabled +// 0x1: Flash patch unit enabled +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_REMAP +// +//***************************************************************************** +// Field: [28:5] REMAP +// +// Remap base address field. +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP0 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 0 disabled +// 0x1: Compare and remap for comparator 0 enabled +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP1 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 1 disabled +// 0x1: Compare and remap for comparator 1 enabled +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP2 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 2 disabled +// 0x1: Compare and remap for comparator 2 enabled +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP3 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 3 disabled +// 0x1: Compare and remap for comparator 3 enabled +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP4 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 4 disabled +// 0x1: Compare and remap for comparator 4 enabled +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP5 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Address +// remapping only takes place for the 0x0 setting. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 5 disabled +// 0x1: Compare and remap for comparator 5 enabled +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP6 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 6 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 6 disabled +// 0x1: Compare and remap for comparator 6 enabled +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_FPB_O_COMP7 +// +//***************************************************************************** +// Field: [31:30] REPLACE +// +// This selects what happens when the COMP address is matched. Comparator 7 is +// a literal comparator and the only supported setting is 0x0. Other settings +// will be ignored. +// +// 0x0: Remap to remap address. See REMAP.REMAP +// 0x1: Set BKPT on lower halfword, upper is unaffected +// 0x2: Set BKPT on upper halfword, lower is unaffected +// 0x3: Set BKPT on both lower and upper halfwords. +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 + +// Field: [28:2] COMP +// +// Comparison address. +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 + +// Field: [0] ENABLE +// +// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to +// enable comparisons. +// +// 0x0: Compare and remap for comparator 7 disabled +// 0x1: Compare and remap for comparator 7 enabled +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 + + +#endif // __CPU_FPB__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_itm.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_itm.h new file mode 100644 index 00000000..6fe1ab93 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_itm.h @@ -0,0 +1,1122 @@ +/****************************************************************************** +* Filename: hw_cpu_itm_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + + +#endif // __CPU_ITM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_rom_table.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_rom_table.h new file mode 100644 index 00000000..dc3a4e68 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_rom_table.h @@ -0,0 +1,220 @@ +/****************************************************************************** +* Filename: hw_cpu_rom_table_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_ROM_TABLE_H__ +#define __HW_CPU_ROM_TABLE_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ROM_TABLE component +// +//***************************************************************************** +// System Control Space Component +#define CPU_ROM_TABLE_O_SCS 0x00000000 + +// Data Watchpoint and Trace Component +#define CPU_ROM_TABLE_O_DWT 0x00000004 + +// Flash Patch and Breakpoint Component +#define CPU_ROM_TABLE_O_FPB 0x00000008 + +// Instrumentation Trace Component +#define CPU_ROM_TABLE_O_ITM 0x0000000C + +// Trace Port Interface Component +#define CPU_ROM_TABLE_O_TPIU 0x00000010 + +// Enhanced Trace Component +#define CPU_ROM_TABLE_O_ETM 0x00000014 + +// End Marker +#define CPU_ROM_TABLE_O_END 0x00000018 + +// System Memory Map Access for DAP +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SCS +// +//***************************************************************************** +// Field: [31:0] SCS +// +// Points to the SCS at 0xE000E000. +// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_DWT +// +//***************************************************************************** +// Field: [31:1] DWT +// +// Points to the Data Watchpoint and Trace block at 0xE0001000. +// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 + +// Field: [0] DWT_PRESENT +// +// 0: DWT is not present +// 1: DWT is present. +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_FPB +// +//***************************************************************************** +// Field: [31:1] FPB +// +// Points to the Flash Patch and Breakpoint block at 0xE0002000. +// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 + +// Field: [0] FPB_PRESENT +// +// 0: FPB is not present +// 1: FPB is present. +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ITM +// +//***************************************************************************** +// Field: [31:1] ITM +// +// Points to the Instrumentation Trace block at 0xE0000000. +// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 + +// Field: [0] ITM_PRESENT +// +// 0: ITM is not present +// 1: ITM is present. +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_TPIU +// +//***************************************************************************** +// Field: [31:1] TPIU +// +// Points to the TPIU. TPIU is at 0xE0040000. +// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 + +// Field: [0] TPIU_PRESENT +// +// 0: TPIU is not present +// 1: TPIU is present. +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_ETM +// +//***************************************************************************** +// Field: [31:1] ETM +// +// Points to the ETM. ETM is at 0xE0041000. +// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 + +// Field: [0] ETM_PRESENT +// +// 0: ETM is not present +// 1: ETM is present. +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_END +// +//***************************************************************************** +// Field: [31:0] END +// +// End of the ROM table +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 + +//***************************************************************************** +// +// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS +// +//***************************************************************************** +// Field: [0] SYSTEM_ACCESS +// +// 1: The system memory map is accessible using the DAP +// 0: Only debug resources are accessible using the DAP +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 + + +#endif // __CPU_ROM_TABLE__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_scs.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_scs.h new file mode 100644 index 00000000..f686c2f7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_scs.h @@ -0,0 +1,4789 @@ +/****************************************************************************** +* Filename: hw_cpu_scs_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR9 0x00000424 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// MPU Type +#define CPU_SCS_O_MPU_TYPE 0x00000D90 + +// MPU Control +#define CPU_SCS_O_MPU_CTRL 0x00000D94 + +// MPU Region Number +#define CPU_SCS_O_MPU_RNR 0x00000D98 + +// MPU Region Base Address +#define CPU_SCS_O_MPU_RBAR 0x00000D9C + +// MPU Region Attribute and Size +#define CPU_SCS_O_MPU_RASR 0x00000DA0 + +// MPU Alias 1 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 + +// MPU Alias 1 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 + +// MPU Alias 2 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC + +// MPU Alias 2 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 + +// MPU Alias 3 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 + +// MPU Alias 3 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +// Floating Point Context Control +#define CPU_SCS_O_FPCCR 0x00000F34 + +// Floating-Point Context Address +#define CPU_SCS_O_FPCAR 0x00000F38 + +// Floating Point Default Status Control +#define CPU_SCS_O_FPDSCR 0x00000F3C + +// Media and FP Feature 0 +#define CPU_SCS_O_MVFR0 0x00000F40 + +// Media and FP Feature 1 +#define CPU_SCS_O_MVFR1 0x00000F44 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [9] DISOOFP +// +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define CPU_SCS_ACTLR_DISOOFP 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_BITN 9 +#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_S 9 + +// Field: [8] DISFPCA +// +// Disable automatic update of CONTROL.FPCA +#define CPU_SCS_ACTLR_DISFPCA 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_BITN 8 +#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_S 8 + +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [5] SETENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 +#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 + +// Field: [4] SETENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 +#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 + +// Field: [3] SETENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 +#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 + +// Field: [2] SETENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 +#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 + +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [5] CLRENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 +#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 + +// Field: [4] CLRENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 +#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 + +// Field: [3] CLRENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 +#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 + +// Field: [2] CLRENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 +#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 + +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [5] SETPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 + +// Field: [4] SETPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 + +// Field: [3] SETPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 + +// Field: [2] SETPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 + +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [5] CLRPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 + +// Field: [4] CLRPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 + +// Field: [3] CLRPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 + +// Field: [2] CLRPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 + +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [5] ACTIVE37 +// +// Reading 0 from this bit implies that interrupt line 37 is not active. +// Reading 1 from this bit implies that the interrupt line 37 is active (See +// EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 + +// Field: [4] ACTIVE36 +// +// Reading 0 from this bit implies that interrupt line 36 is not active. +// Reading 1 from this bit implies that the interrupt line 36 is active (See +// EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 + +// Field: [3] ACTIVE35 +// +// Reading 0 from this bit implies that interrupt line 35 is not active. +// Reading 1 from this bit implies that the interrupt line 35 is active (See +// EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 + +// Field: [2] ACTIVE34 +// +// Reading 0 from this bit implies that interrupt line 34 is not active. +// Reading 1 from this bit implies that the interrupt line 34 is active (See +// EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 + +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [31:24] PRI_35 +// +// Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 +#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 + +// Field: [23:16] PRI_34 +// +// Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 + +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR9 +// +//***************************************************************************** +// Field: [15:8] PRI_37 +// +// Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 + +// Field: [7:0] PRI_36 +// +// Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF +#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_TYPE +// +//***************************************************************************** +// Field: [23:16] IREGION +// +// The processor core uses only a unified MPU, this field always reads 0x0. +#define CPU_SCS_MPU_TYPE_IREGION_W 8 +#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 +#define CPU_SCS_MPU_TYPE_IREGION_S 16 + +// Field: [15:8] DREGION +// +// Number of supported MPU regions field. This field reads 0x08 indicating +// eight MPU regions. +#define CPU_SCS_MPU_TYPE_DREGION_W 8 +#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 +#define CPU_SCS_MPU_TYPE_DREGION_S 8 + +// Field: [0] SEPARATE +// +// The processor core uses only a unified MPU, thus this field is always 0. +#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 +#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_CTRL +// +//***************************************************************************** +// Field: [2] PRIVDEFENA +// +// This bit enables the default memory map for privileged access, as a +// background region, when the MPU is enabled. The background region acts as if +// it was region number 1 before any settable regions. Any region that is set +// up overlays this default map, and overrides it. If this bit is not set, the +// default memory map is disabled, and memory not covered by a region faults. +// This applies to memory type, Execute Never (XN), cache and shareable rules. +// However, this only applies to privileged mode (fetch and data access). User +// mode code faults unless a region has been set up for its code and data. When +// the MPU is disabled, the default map acts on both privileged and user mode +// code. XN and SO rules always apply to the system partition whether this +// enable is set or not. If the MPU is disabled, this bit is ignored. +#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 + +// Field: [1] HFNMIENA +// +// This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated +// handlers. If this bit and ENABLE are set, the MPU is enabled when in these +// handlers. If this bit is not set, the MPU is disabled when in these +// handlers, regardless of the value of ENABLE bit. If this bit is set and +// ENABLE is not set, behavior is unpredictable. +#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 +#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 + +// Field: [0] ENABLE +// +// Enable MPU +// +// 0: MPU disabled +// 1: MPU enabled +#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 +#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RNR +// +//***************************************************************************** +// Field: [7:0] REGION +// +// Region select field. +// This field selects the region to operate on when using the MPU_RASR and +// MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID +// and MPU_RBAR.REGION fields are written, which overwrites this. +#define CPU_SCS_MPU_RNR_REGION_W 8 +#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF +#define CPU_SCS_MPU_RNR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR +// +//***************************************************************************** +// Field: [31:5] ADDR +// +// Region base address field. +// The position of the LSB depends on the region size, so that the base address +// is aligned according to an even multiple of size. The power of 2 size +// specified by the SZENABLE field of the MPU Region Attribute and Size +// Register defines how many bits of base address are used. +#define CPU_SCS_MPU_RBAR_ADDR_W 27 +#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 +#define CPU_SCS_MPU_RBAR_ADDR_S 5 + +// Field: [4] VALID +// +// MPU region number valid: +// 0: MPU_RNR remains unchanged and is interpreted. +// 1: MPU_RNR is overwritten by REGION. +#define CPU_SCS_MPU_RBAR_VALID 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_BITN 4 +#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_S 4 + +// Field: [3:0] REGION +// +// MPU region override field +#define CPU_SCS_MPU_RBAR_REGION_W 4 +#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F +#define CPU_SCS_MPU_RBAR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR +// +//***************************************************************************** +// Field: [28] XN +// +// Instruction access disable: +// 0: Enable instruction fetches +// 1: Disable instruction fetches +#define CPU_SCS_MPU_RASR_XN 0x10000000 +#define CPU_SCS_MPU_RASR_XN_BITN 28 +#define CPU_SCS_MPU_RASR_XN_M 0x10000000 +#define CPU_SCS_MPU_RASR_XN_S 28 + +// Field: [26:24] AP +// +// Data access permission: +// 0x0: Priviliged permissions: No access. User permissions: No access. +// 0x1: Priviliged permissions: Read-write. User permissions: No access. +// 0x2: Priviliged permissions: Read-write. User permissions: Read-only. +// 0x3: Priviliged permissions: Read-write. User permissions: Read-write. +// 0x4: Reserved +// 0x5: Priviliged permissions: Read-only. User permissions: No access. +// 0x6: Priviliged permissions: Read-only. User permissions: Read-only. +// 0x7: Priviliged permissions: Read-only. User permissions: Read-only. +#define CPU_SCS_MPU_RASR_AP_W 3 +#define CPU_SCS_MPU_RASR_AP_M 0x07000000 +#define CPU_SCS_MPU_RASR_AP_S 24 + +// Field: [21:19] TEX +// +// Type extension +#define CPU_SCS_MPU_RASR_TEX_W 3 +#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 +#define CPU_SCS_MPU_RASR_TEX_S 19 + +// Field: [18] S +// +// Shareable bit: +// 0: Not shareable +// 1: Shareable +#define CPU_SCS_MPU_RASR_S 0x00040000 +#define CPU_SCS_MPU_RASR_S_BITN 18 +#define CPU_SCS_MPU_RASR_S_M 0x00040000 +#define CPU_SCS_MPU_RASR_S_S 18 + +// Field: [17] C +// +// Cacheable bit: +// 0: Not cacheable +// 1: Cacheable +#define CPU_SCS_MPU_RASR_C 0x00020000 +#define CPU_SCS_MPU_RASR_C_BITN 17 +#define CPU_SCS_MPU_RASR_C_M 0x00020000 +#define CPU_SCS_MPU_RASR_C_S 17 + +// Field: [16] B +// +// Bufferable bit: +// 0: Not bufferable +// 1: Bufferable +#define CPU_SCS_MPU_RASR_B 0x00010000 +#define CPU_SCS_MPU_RASR_B_BITN 16 +#define CPU_SCS_MPU_RASR_B_M 0x00010000 +#define CPU_SCS_MPU_RASR_B_S 16 + +// Field: [15:8] SRD +// +// Sub-Region Disable field: +// Setting a bit in this field disables the corresponding sub-region. Regions +// are split into eight equal-sized sub-regions. Sub-regions are not supported +// for region sizes of 128 bytes and less. +#define CPU_SCS_MPU_RASR_SRD_W 8 +#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 +#define CPU_SCS_MPU_RASR_SRD_S 8 + +// Field: [5:1] SIZE +// +// MPU Protection Region Size Field: +// 0x04: 32B +// 0x05: 64B +// 0x06: 128B +// 0x07: 256B +// 0x08: 512B +// 0x09: 1KB +// 0x0A: 2KB +// 0x0B: 4KB +// 0x0C: 8KB +// 0x0D: 16KB +// 0x0E: 32KB +// 0x0F: 64KB +// 0x10: 128KB +// 0x11: 256KB +// 0x12: 512KB +// 0x13: 1MB +// 0x14: 2MB +// 0x15: 4MB +// 0x16: 8MB +// 0x17: 16MB +// 0x18: 32MB +// 0x19: 64MB +// 0x1A: 128MB +// 0x1B: 256MB +// 0x1C: 512MB +// 0x1D: 1GB +// 0x1E: 2GB +// 0x1F: 4GB +#define CPU_SCS_MPU_RASR_SIZE_W 5 +#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E +#define CPU_SCS_MPU_RASR_SIZE_S 1 + +// Field: [0] ENABLE +// +// Region enable bit: +// 0: Disable region +// 1: Enable region +#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 +#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A1 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A1 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A2 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A2 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A3 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A3 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCCR +// +//***************************************************************************** +// Field: [31] ASPEN +// +// Automatic State Preservation enable. +// When this bit is set is will cause bit [2] of the Special CONTROL register +// to be set (FPCA) on execution of a floating point instruction which results +// in the floating point state automatically being preserved on exception +// entry. +#define CPU_SCS_FPCCR_ASPEN 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_BITN 31 +#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_S 31 + +// Field: [30] LSPEN +// +// Lazy State Preservation enable. +// Lazy state preservation is when the processor performs a context save, space +// on the stack is reserved for the floating point state but it is not stacked +// until the new context performs a floating point operation. +// 0: Disable automatic lazy state preservation for floating-point context. +// 1: Enable automatic lazy state preservation for floating-point context. +#define CPU_SCS_FPCCR_LSPEN 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_BITN 30 +#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_S 30 + +// Field: [8] MONRDY +// +// Indicates whether the the software executing when the processor allocated +// the FP stack frame was able to set the DebugMonitor exception to pending. +// 0: DebugMonitor is disabled or priority did not permit setting +// DEMCR.MON_PEND when the floating-point stack frame was allocated. +// 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when +// the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MONRDY 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_BITN 8 +#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_S 8 + +// Field: [6] BFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the BusFault exception to pending. +// 0: BusFault is disabled or priority did not permit setting the BusFault +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: BusFault is enabled and priority permitted setting the BusFault handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_BFRDY 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_BITN 6 +#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_S 6 + +// Field: [5] MMRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the MemManage exception to pending. +// 0: MemManage is disabled or priority did not permit setting the MemManage +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: MemManage is enabled and priority permitted setting the MemManage handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MMRDY 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_BITN 5 +#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_S 5 + +// Field: [4] HFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the HardFault exception to pending. +// 0: Priority did not permit setting the HardFault handler to the pending +// state when the floating-point stack frame was allocated. +// 1: Priority permitted setting the HardFault handler to the pending state +// when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_HFRDY 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_BITN 4 +#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_S 4 + +// Field: [3] THREAD +// +// Indicates the processor mode was Thread when it allocated the FP stack +// frame. +// 0: Mode was not Thread Mode when the floating-point stack frame was +// allocated. +// 1: Mode was Thread Mode when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_THREAD 0x00000008 +#define CPU_SCS_FPCCR_THREAD_BITN 3 +#define CPU_SCS_FPCCR_THREAD_M 0x00000008 +#define CPU_SCS_FPCCR_THREAD_S 3 + +// Field: [1] USER +// +// Indicates the privilege level of the software executing was User +// (Unpriviledged) when the processor allocated the FP stack frame: +// 0: Privilege level was not user when the floating-point stack frame was +// allocated. +// 1: Privilege level was user when the floating-point stack frame was +// allocated. +#define CPU_SCS_FPCCR_USER 0x00000002 +#define CPU_SCS_FPCCR_USER_BITN 1 +#define CPU_SCS_FPCCR_USER_M 0x00000002 +#define CPU_SCS_FPCCR_USER_S 1 + +// Field: [0] LSPACT +// +// Indicates whether Lazy preservation of the FP state is active: +// 0: Lazy state preservation is not active. +// 1: Lazy state preservation is active. floating-point stack frame has been +// allocated but saving state to it has been deferred. +#define CPU_SCS_FPCCR_LSPACT 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_BITN 0 +#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCAR +// +//***************************************************************************** +// Field: [31:2] ADDRESS +// +// Holds the (double-word-aligned) location of the unpopulated floating-point +// register space allocated on an exception stack frame. +#define CPU_SCS_FPCAR_ADDRESS_W 30 +#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC +#define CPU_SCS_FPCAR_ADDRESS_S 2 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPDSCR +// +//***************************************************************************** +// Field: [26] AHP +// +// Default value for Alternative Half Precision bit. (If this bit is set to 1 +// then Alternative half-precision format is selected). +#define CPU_SCS_FPDSCR_AHP 0x04000000 +#define CPU_SCS_FPDSCR_AHP_BITN 26 +#define CPU_SCS_FPDSCR_AHP_M 0x04000000 +#define CPU_SCS_FPDSCR_AHP_S 26 + +// Field: [25] DN +// +// Default value for Default NaN mode bit. (If this bit is set to 1 then any +// operation involving one or more NaNs returns the Default NaN). +#define CPU_SCS_FPDSCR_DN 0x02000000 +#define CPU_SCS_FPDSCR_DN_BITN 25 +#define CPU_SCS_FPDSCR_DN_M 0x02000000 +#define CPU_SCS_FPDSCR_DN_S 25 + +// Field: [24] FZ +// +// Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then +// Flush-to-zero mode is enabled). +#define CPU_SCS_FPDSCR_FZ 0x01000000 +#define CPU_SCS_FPDSCR_FZ_BITN 24 +#define CPU_SCS_FPDSCR_FZ_M 0x01000000 +#define CPU_SCS_FPDSCR_FZ_S 24 + +// Field: [23:22] RMODE +// +// Default value for Rounding Mode control field. (The encoding for this field +// is: +// 0b00 Round to Nearest (RN) mode +// 0b01 Round towards Plus Infinity (RP) mode +// 0b10 Round towards Minus Infinity (RM) mode +// 0b11 Round towards Zero (RZ) mode. +// The specified rounding mode is used by almost all floating-point +// instructions). +#define CPU_SCS_FPDSCR_RMODE_W 2 +#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 +#define CPU_SCS_FPDSCR_RMODE_S 22 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR0 +// +//***************************************************************************** +// Field: [31:28] FP_ROUNDING_MODES +// +// Indicates the rounding modes supported by the FP floating-point hardware. +// The value of this field is: 0b0001 - all rounding modes supported. +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 + +// Field: [27:24] SHORT_VECTORS +// +// Indicates the hardware support for FP short vectors. The value of this field +// is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 +#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 +#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 + +// Field: [23:20] SQUARE_ROOT +// +// Indicates the hardware support for FP square root operations. The value of +// this field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 +#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 +#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 + +// Field: [19:16] DIVIDE +// +// Indicates the hardware support for FP divide operations. The value of this +// field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_DIVIDE_W 4 +#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 +#define CPU_SCS_MVFR0_DIVIDE_S 16 + +// Field: [15:12] FP_EXCEPTION_TRAPPING +// +// Indicates whether the FP hardware implementation supports exception +// trapping. The value of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 + +// Field: [11:8] DOUBLE_PRECISION +// +// Indicates the hardware support for FP double-precision operations. The value +// of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 + +// Field: [7:4] SINGLE_PRECISION +// +// Indicates the hardware support for FP single-precision operations. The value +// of this field is: 0b0010 - supported. +#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 + +// Field: [3:0] A_SIMD +// +// Indicates the size of the FP register bank. The value of this field is: +// 0b0001 - supported, 16 x 64-bit registers. +#define CPU_SCS_MVFR0_A_SIMD_W 4 +#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F +#define CPU_SCS_MVFR0_A_SIMD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR1 +// +//***************************************************************************** +// Field: [31:28] FP_FUSED_MAC +// +// Indicates whether the FP supports fused multiply accumulate operations. The +// value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 + +// Field: [27:24] FP_HPFP +// +// Indicates whether the FP supports half-precision floating-point conversion +// operations. The value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_HPFP_W 4 +#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 +#define CPU_SCS_MVFR1_FP_HPFP_S 24 + +// Field: [7:4] D_NAN_MODE +// +// Indicates whether the FP hardware implementation supports only the Default +// NaN mode. The value of this field is: 0b0001 - hardware supports propagation +// of NaN values. +#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 +#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 +#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 + +// Field: [3:0] FTZ_MODE +// +// Indicates whether the FP hardware implementation supports only the +// Flush-to-Zero mode of operation. The value of this field is: 0b0001 - +// hardware supports full denormalized number arithmetic. +#define CPU_SCS_MVFR1_FTZ_MODE_W 4 +#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F +#define CPU_SCS_MVFR1_FTZ_MODE_S 0 + + +#endif // __CPU_SCS__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tiprop.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tiprop.h new file mode 100644 index 00000000..a9f2e965 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tiprop.h @@ -0,0 +1,68 @@ +/****************************************************************************** +* Filename: hw_cpu_tiprop_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TIPROP_H__ +#define __HW_CPU_TIPROP_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TIPROP component +// +//***************************************************************************** +// Internal +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 + +//***************************************************************************** +// +// Register: CPU_TIPROP_O_TRACECLKMUX +// +//***************************************************************************** +// Field: [0] TRACECLK_N_SWV +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// TRACECLK Internal. Only to be used through TI provided API. +// SWV Internal. Only to be used through TI provided API. +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 + + +#endif // __CPU_TIPROP__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tpiu.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tpiu.h new file mode 100644 index 00000000..16b46cd1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_cpu_tpiu.h @@ -0,0 +1,347 @@ +/****************************************************************************** +* Filename: hw_cpu_tpiu_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// Field: [31:0] DEVID +// +// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no +// ETM present. +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 + + +#endif // __CPU_TPIU__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_crypto.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_crypto.h new file mode 100644 index 00000000..699b1d0e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_crypto.h @@ -0,0 +1,3966 @@ +/****************************************************************************** +* Filename: hw_crypto_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_CRYPTO_H__ +#define __HW_CRYPTO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CRYPTO component +// +//***************************************************************************** +// Channel 0 Control +#define CRYPTO_O_DMACH0CTL 0x00000000 + +// Channel 0 External Address +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 + +// Channel 0 DMA Length +#define CRYPTO_O_DMACH0LEN 0x0000000C + +// DMAC Status +#define CRYPTO_O_DMASTAT 0x00000018 + +// DMAC Software Reset +#define CRYPTO_O_DMASWRESET 0x0000001C + +// Channel 1 Control +#define CRYPTO_O_DMACH1CTL 0x00000020 + +// Channel 1 External Address +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 + +// Channel 1 DMA Length +#define CRYPTO_O_DMACH1LEN 0x0000002C + +// DMAC Master Run-time Parameters +#define CRYPTO_O_DMABUSCFG 0x00000078 + +// DMAC Port Error Raw Status +#define CRYPTO_O_DMAPORTERR 0x0000007C + +// DMAC Version +#define CRYPTO_O_DMAHWVER 0x000000FC + +// Key Store Write Area +#define CRYPTO_O_KEYWRITEAREA 0x00000400 + +// Key Store Written Area +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 + +// Key Store Size +#define CRYPTO_O_KEYSIZE 0x00000408 + +// Key Store Read Area +#define CRYPTO_O_KEYREADAREA 0x0000040C + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY20 0x00000500 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY21 0x00000504 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY22 0x00000508 + +// AES_KEY2_0 / AES_GHASH_H_IN_0 +#define CRYPTO_O_AESKEY23 0x0000050C + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY30 0x00000510 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY31 0x00000514 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY32 0x00000518 + +// AES_KEY3_0 / AES_KEY2_4 +#define CRYPTO_O_AESKEY33 0x0000051C + +// AES initialization vector registers +#define CRYPTO_O_AESIV0 0x00000540 + +// AES initialization vector registers +#define CRYPTO_O_AESIV1 0x00000544 + +// AES initialization vector registers +#define CRYPTO_O_AESIV2 0x00000548 + +// AES initialization vector registers +#define CRYPTO_O_AESIV3 0x0000054C + +// AES Control +#define CRYPTO_O_AESCTL 0x00000550 + +// AES Crypto Length 0 (LSW) +#define CRYPTO_O_AESDATALEN0 0x00000554 + +// AES Crypto Length 1 (MSW) +#define CRYPTO_O_AESDATALEN1 0x00000558 + +// AES Authentication Length +#define CRYPTO_O_AESAUTHLEN 0x0000055C + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT0 0x00000560 + +// AES Data Input_Output 0 +#define CRYPTO_O_AESDATAIN0 0x00000560 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT1 0x00000564 + +// AES Data Input_Output 0 +#define CRYPTO_O_AESDATAIN1 0x00000564 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT2 0x00000568 + +// AES Data Input_Output 2 +#define CRYPTO_O_AESDATAIN2 0x00000568 + +// Data Input/Output +#define CRYPTO_O_AESDATAOUT3 0x0000056C + +// AES Data Input_Output 3 +#define CRYPTO_O_AESDATAIN3 0x0000056C + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT0 0x00000570 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT1 0x00000574 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT2 0x00000578 + +// AES Tag Out 0 +#define CRYPTO_O_AESTAGOUT3 0x0000057C + +// HASH Data Input 1 +#define CRYPTO_O_HASHDATAIN1 0x00000604 + +// HASH Data Input 2 +#define CRYPTO_O_HASHDATAIN2 0x00000608 + +// HASH Data Input 3 +#define CRYPTO_O_HASHDATAIN3 0x0000060C + +// HASH Data Input 4 +#define CRYPTO_O_HASHDATAIN4 0x00000610 + +// HASH Data Input 5 +#define CRYPTO_O_HASHDATAIN5 0x00000614 + +// HASH Data Input 6 +#define CRYPTO_O_HASHDATAIN6 0x00000618 + +// HASH Data Input 7 +#define CRYPTO_O_HASHDATAIN7 0x0000061C + +// HASH Data Input 8 +#define CRYPTO_O_HASHDATAIN8 0x00000620 + +// HASH Data Input 9 +#define CRYPTO_O_HASHDATAIN9 0x00000624 + +// HASH Data Input 10 +#define CRYPTO_O_HASHDATAIN10 0x00000628 + +// HASH Data Input 11 +#define CRYPTO_O_HASHDATAIN11 0x0000062C + +// HASH Data Input 12 +#define CRYPTO_O_HASHDATAIN12 0x00000630 + +// HASH Data Input 13 +#define CRYPTO_O_HASHDATAIN13 0x00000634 + +// HASH Data Input 14 +#define CRYPTO_O_HASHDATAIN14 0x00000638 + +// HASH Data Input 15 +#define CRYPTO_O_HASHDATAIN15 0x0000063C + +// HASH Data Input 16 +#define CRYPTO_O_HASHDATAIN16 0x00000640 + +// HASH Data Input 17 +#define CRYPTO_O_HASHDATAIN17 0x00000644 + +// HASH Data Input 18 +#define CRYPTO_O_HASHDATAIN18 0x00000648 + +// HASH Data Input 19 +#define CRYPTO_O_HASHDATAIN19 0x0000064C + +// HASH Data Input 20 +#define CRYPTO_O_HASHDATAIN20 0x00000650 + +// HASH Data Input 21 +#define CRYPTO_O_HASHDATAIN21 0x00000654 + +// HASH Data Input 22 +#define CRYPTO_O_HASHDATAIN22 0x00000658 + +// HASH Data Input 23 +#define CRYPTO_O_HASHDATAIN23 0x0000065C + +// HASH Data Input 24 +#define CRYPTO_O_HASHDATAIN24 0x00000660 + +// HASH Data Input 25 +#define CRYPTO_O_HASHDATAIN25 0x00000664 + +// HASH Data Input 26 +#define CRYPTO_O_HASHDATAIN26 0x00000668 + +// HASH Data Input 27 +#define CRYPTO_O_HASHDATAIN27 0x0000066C + +// HASH Data Input 28 +#define CRYPTO_O_HASHDATAIN28 0x00000670 + +// HASH Data Input 29 +#define CRYPTO_O_HASHDATAIN29 0x00000674 + +// HASH Data Input 30 +#define CRYPTO_O_HASHDATAIN30 0x00000678 + +// HASH Data Input 31 +#define CRYPTO_O_HASHDATAIN31 0x0000067C + +// HASH Input_Output Buffer Control +#define CRYPTO_O_HASHIOBUFCTRL 0x00000680 + +// HASH Mode +#define CRYPTO_O_HASHMODE 0x00000684 + +// HASH Input Length LSB +#define CRYPTO_O_HASHINLENL 0x00000688 + +// HASH Input Length MSB +#define CRYPTO_O_HASHINLENH 0x0000068C + +// HASH Digest A +#define CRYPTO_O_HASHDIGESTA 0x000006C0 + +// HASH Digest B +#define CRYPTO_O_HASHDIGESTB 0x000006C4 + +// HASH Digest C +#define CRYPTO_O_HASHDIGESTC 0x000006C8 + +// HASH Digest D +#define CRYPTO_O_HASHDIGESTD 0x000006CC + +// HASH Digest E +#define CRYPTO_O_HASHDIGESTE 0x000006D0 + +// HASH Digest F +#define CRYPTO_O_HASHDIGESTF 0x000006D4 + +// HASH Digest G +#define CRYPTO_O_HASHDIGESTG 0x000006D8 + +// HASH Digest H +#define CRYPTO_O_HASHDIGESTH 0x000006DC + +// HASH Digest I +#define CRYPTO_O_HASHDIGESTI 0x000006E0 + +// HASH Digest J +#define CRYPTO_O_HASHDIGESTJ 0x000006E4 + +// HASH Digest K +#define CRYPTO_O_HASHDIGESTK 0x000006E8 + +// HASH Digest L +#define CRYPTO_O_HASHDIGESTL 0x000006EC + +// HASH Digest M +#define CRYPTO_O_HASHDIGESTM 0x000006F0 + +// HASH Digest N +#define CRYPTO_O_HASHDIGESTN 0x000006F4 + +// HASH Digest 0 +#define CRYPTO_O_HASHDIGESTO 0x000006F8 + +// HASH Digest P +#define CRYPTO_O_HASHDIGESTP 0x000006FC + +// Algorithm Select +#define CRYPTO_O_ALGSEL 0x00000700 + +// DMA Protection Control +#define CRYPTO_O_DMAPROTCTL 0x00000704 + +// Software Reset +#define CRYPTO_O_SWRESET 0x00000740 + +// Control Interrupt Configuration +#define CRYPTO_O_IRQTYPE 0x00000780 + +// Control Interrupt Enable +#define CRYPTO_O_IRQEN 0x00000784 + +// Control Interrupt Clear +#define CRYPTO_O_IRQCLR 0x00000788 + +// Control Interrupt Set +#define CRYPTO_O_IRQSET 0x0000078C + +// Control Interrupt Status +#define CRYPTO_O_IRQSTAT 0x00000790 + +// Hardware Version +#define CRYPTO_O_HWVER 0x000007FC + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority +// 0: Low +// 1: High +// If both channels have the same priority, access of the channels to the +// external port is arbitrated using the round robin scheme. If one channel has +// a high priority and another one low, the channel with the high priority is +// served first, in case of simultaneous access requests. +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 + +// Field: [0] EN +// +// Channel enable +// 0: Disabled +// 1: Enable +// Note: Disabling an active channel interrupts the DMA operation. The ongoing +// block transfer completes, but no new transfers are requested. +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value +// When read during operation, it holds the last updated external address after +// being sent to the master interface. Note: The crypto DMA copies out upto 3 +// bytes until it hits a word boundary, thus the address need not be word +// aligned. +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH0LEN +// +//***************************************************************************** +// Field: [15:0] DMALEN +// +// Channel DMA length in bytes +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Setting this register to a nonzero value starts the transfer if the +// channel is enabled. Therefore, this register must be written last when +// setting up a DMA channel. +#define CRYPTO_DMACH0LEN_DMALEN_W 16 +#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_DMALEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASTAT +// +//***************************************************************************** +// Field: [17] PORT_ERR +// +// Reflects possible transfer errors on the AHB port. +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 + +// Field: [1] CH1_ACT +// +// A value of 1 indicates that channel 1 is active (DMA transfer on-going). +#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_S 1 + +// Field: [0] CH0_ACT +// +// A value of 1 indicates that channel 0 is active (DMA transfer on-going). +#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMASWRESET +// +//***************************************************************************** +// Field: [0] SWRES +// +// Software reset enable +// 0 : Disabled +// 1 : Enabled (self-cleared to 0) +// Completion of the software reset must be checked through the DMASTAT +#define CRYPTO_DMASWRESET_SWRES 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_BITN 0 +#define CRYPTO_DMASWRESET_SWRES_M 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1CTL +// +//***************************************************************************** +// Field: [1] PRIO +// +// Channel priority +// 0: Low +// 1: High +// If both channels have the same priority, access of the channels to the +// external port is arbitrated using the round robin scheme. If one channel has +// a high priority and another one low, the channel with the high priority is +// served first, in case of simultaneous access requests. +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 + +// Field: [0] EN +// +// Channel enable +// 0: Disabled +// 1: Enable +// Note: Disabling an active channel interrupts the DMA operation. The ongoing +// block transfer completes, but no new transfers are requested. +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1EXTADDR +// +//***************************************************************************** +// Field: [31:0] ADDR +// +// Channel external address value. +// When read during operation, it holds the last updated external address after +// being sent to the master interface. Note: The crypto DMA copies out upto 3 +// bytes until it hits a word boundary, thus the address need not be word +// aligned. +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMACH1LEN +// +//***************************************************************************** +// Field: [15:0] DMALEN +// +// Channel DMA length in bytes. +// During configuration, this register contains the DMA transfer length in +// bytes. During operation, it contains the last updated value of the DMA +// transfer length after being sent to the master interface. +// Note: Setting this register to a nonzero value starts the transfer if the +// channel is enabled. Therefore, this register must be written last when +// setting up a DMA channel. +#define CRYPTO_DMACH1LEN_DMALEN_W 16 +#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_DMALEN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMABUSCFG +// +//***************************************************************************** +// Field: [15:12] AHB_MST1_BURST_SIZE +// +// Maximum burst size that can be performed on the AHB bus +// ENUMs: +// 64_BYTE 64 bytes +// 32_BYTE 32 bytes +// 16_BYTE 16 bytes +// 8_BYTE 8 bytes +// 4_BYTE 4 bytes +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 + +// Field: [11] AHB_MST1_IDLE_EN +// +// Idle insertion between consecutive burst transfers on AHB +// ENUMs: +// IDLE Idle transfer insertion enabled +// NO_IDLE Do not insert idle transfers. +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 + +// Field: [10] AHB_MST1_INCR_EN +// +// Burst length type of AHB transfer +// ENUMs: +// SPECIFIED Fixed length bursts or single transfers +// UNSPECIFIED Unspecified length burst transfers +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 + +// Field: [9] AHB_MST1_LOCK_EN +// +// Locked transform on AHB +// ENUMs: +// LOCKED Transfers are locked +// NOT_LOCKED Transfers are not locked +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 + +// Field: [8] AHB_MST1_BIGEND +// +// Endianess for the AHB master +// ENUMs: +// BIG_ENDIAN Big Endian +// LITTLE_ENDIAN Little Endian +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPORTERR +// +//***************************************************************************** +// Field: [12] PORT1_AHB_ERROR +// +// A value of 1 indicates that the EIP-101 has detected an AHB bus error +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 + +// Field: [9] PORT1_CHANNEL +// +// Indicates which channel has serviced last (channel 0 or channel 1) by AHB +// master port. +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAHWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VERSION +// +// Major version number +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 + +// Field: [23:20] HW_MINOR_VERSION +// +// Minor version number +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 + +// Field: [19:16] HW_PATCH_LEVEL +// +// Patch level +// Starts at 0 at first delivery of this version +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 + +// Field: [15:8] EIP_NUMBER_COMPL +// +// Bit-by-bit complement of the EIP_NUMBER field bits. +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 + +// Field: [7:0] EIP_NUMBER +// +// Binary encoding of the EIP-number of this DMA controller (209) +#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF +#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITEAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA7 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA7 is not selected to be written. +// 1: RAM_AREA7 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 + +// Field: [6] RAM_AREA6 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA6 is not selected to be written. +// 1: RAM_AREA6 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 + +// Field: [5] RAM_AREA5 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA5 is not selected to be written. +// 1: RAM_AREA5 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 + +// Field: [4] RAM_AREA4 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA4 is not selected to be written. +// 1: RAM_AREA4 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 + +// Field: [3] RAM_AREA3 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA3 is not selected to be written. +// 1: RAM_AREA3 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 + +// Field: [2] RAM_AREA2 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA2 is not selected to be written. +// 1: RAM_AREA2 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 + +// Field: [1] RAM_AREA1 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA1 is not selected to be written. +// 1: RAM_AREA1 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 + +// Field: [0] RAM_AREA0 +// +// Each RAM_AREAx represents an area of 128 bits. +// Select the key store RAM area(s) where the key(s) needs to be written +// 0: RAM_AREA0 is not selected to be written. +// 1: RAM_AREA0 is selected to be written. +// Writing to multiple RAM locations is possible only when the selected RAM +// areas are sequential. +// Keys that require more than one RAM locations (key size is 192 or 256 bits), +// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, +// or RAM_AREA6. +// ENUMs: +// SEL This RAM area is selected to be written +// NOT_SEL This RAM area is not selected to be written +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYWRITTENAREA +// +//***************************************************************************** +// Field: [7] RAM_AREA_WRITTEN7 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 + +// Field: [6] RAM_AREA_WRITTEN6 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 + +// Field: [5] RAM_AREA_WRITTEN5 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 + +// Field: [4] RAM_AREA_WRITTEN4 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 + +// Field: [3] RAM_AREA_WRITTEN3 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 + +// Field: [2] RAM_AREA_WRITTEN2 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 + +// Field: [1] RAM_AREA_WRITTEN1 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +// ENUMs: +// WRITTEN This RAM area is written with valid key +// information +// NOT_WRITTEN This RAM area is not written with valid key +// information +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 + +// Field: [0] RAM_AREA_WRITTEN0 +// +// On read this bit returns the key area written status. +// +// This bit can be reset by writing a 1. +// +// Note: This register will be reset on a soft reset initiated by writing to +// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key +// store memory. +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYSIZE +// +//***************************************************************************** +// Field: [1:0] SIZE +// +// Key size: +// 00: Reserved +// When writing this to this register, the KEY_STORE_WRITTEN_AREA register is +// reset. +// ENUMs: +// 256_BIT 256 bits +// 192_BIT 192 bits +// 128_BIT 128 bits +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 + +//***************************************************************************** +// +// Register: CRYPTO_O_KEYREADAREA +// +//***************************************************************************** +// Field: [31] BUSY +// +// Key store operation busy status flag (read only): +// 0: Operation is complete. +// 1: Operation is not completed and the key store is busy. +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 + +// Field: [3:0] RAM_AREA +// +// Selects the area of the key store RAM from where the key needs to be read +// that will be writen to the AES engine +// RAM_AREA: +// +// RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid +// read areas for 192 and 256 bits key sizes. +// Only RAM areas that contain valid written keys can be selected. +// ENUMs: +// NO_RAM No RAM +// RAM_AREA7 RAM Area 7 +// RAM_AREA6 RAM Area 6 +// RAM_AREA5 RAM Area 5 +// RAM_AREA4 RAM Area 4 +// RAM_AREA3 RAM Area 3 +// RAM_AREA2 RAM Area 2 +// RAM_AREA1 RAM Area 1 +// RAM_AREA0 RAM Area 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY20 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY20_AES_KEY2_W 32 +#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY21 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY21_AES_KEY2_W 32 +#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY22 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY22_AES_KEY2_W 32 +#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY23 +// +//***************************************************************************** +// Field: [31:0] AES_KEY2 +// +// AES_KEY2/AES_GHASH_H[31:0] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY23_AES_KEY2_W 32 +#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_AES_KEY2_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY30 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY30_AES_KEY3_W 32 +#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY31 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY31_AES_KEY3_W 32 +#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY32 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY32_AES_KEY3_W 32 +#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESKEY33 +// +//***************************************************************************** +// Field: [31:0] AES_KEY3 +// +// AES_KEY3[31:0]/AES_KEY2[159:128] +// +// For GCM: +// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these +// registers. Only used for modes that use the GHASH function (GCM). +// -[255:128] - This register is used to store intermediate values and is +// initialized with 0s when loading a new key. +// +// For CCM: +// -[255:0] - This register is used to store intermediate values. +// +// For CBC-MAC: +// -[255:0] - ZEROES - This register must remain 0. +#define CRYPTO_AESKEY33_AES_KEY3_W 32 +#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_AES_KEY3_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV0 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV0_AES_IV_W 32 +#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV1 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV1_AES_IV_W 32 +#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV2 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV2_AES_IV_W 32 +#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESIV3 +// +//***************************************************************************** +// Field: [31:0] AES_IV +// +// AES_IV[31:0] +// +// Initialization vector +// Used for regular non-ECB modes (CBC/CTR): +// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers +// must be written with a new 128-bit IV. After an operation, these registers +// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode +// is selected, this value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine +// +// For GCM: +// -[127:0] - AES_IV - For GCM operations, these registers must be written with +// a new 128-bit IV. +// After an operation, these registers contain the updated 128-bit result IV, +// generated by the EIP-120t. Note that bits [127:96] of the IV represent the +// initial counter value (which is 1 for GCM) and must therefore be initialized +// to 0x01000000. This value is incremented with 0x1: After first use - When a +// new data block is submitted to the engine. +// +// For CCM: +// -[127:0] - A0: For CCM this field must be written with value A0, this value +// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and +// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL +// register. This 'L' indicates the width of the Nonce and counter. The loaded +// counter must be initialized to 0. The total width of A0 is 128-bit. +// +// For CBC-MAC: +// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the +// start of each operation. After an operation, these registers contain the +// 128-bit TAG output, generated by the EIP-120t. +#define CRYPTO_AESIV3_AES_IV_W 32 +#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_AES_IV_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESCTL +// +//***************************************************************************** +// Field: [31] CONTEXT_READY +// +// If 1, this read-only status bit indicates that the context data registers +// can be overwritten and the host is permitted to write the next context. +#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_S 31 + +// Field: [30] SAVED_CONTEXT_RDY +// +// If 1, this status bit indicates that an AES authentication TAG and/or IV +// block(s) is/are available for the host to retrieve. This bit is only +// asserted if the save_context bit is set to 1. The bit is mutual exclusive +// with the context_ready bit. +// Writing one clears the bit to 0, indicating the AES core can start its next +// operation. This bit is also cleared when the 4th word of the output TAG +// and/or IV is read. +// Note: All other mode bit writes are ignored when this mode bit is written +// with 1. +// Note: This bit is controlled automatically by the EIP-120t for TAG read DMA +// operations. +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 + +// Field: [29] SAVE_CONTEXT +// +// This bit indicates that an authentication TAG or result IV needs to be +// stored as a result context. +// Typically this bit must be set for authentication modes returning a TAG +// (CBC-MAC, GCM and CCM), or for basic encryption modes that require future +// continuation with the current result IV. +// If this bit is set, the engine retains its full context until the TAG and/or +// IV registers are read. +// The TAG or IV must be read before the AES engine can start a new operation. +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 + +// Field: [24:22] CCM_M +// +// Defines M, which indicates the length of the authentication field for CCM +// operations; the authentication field length equals two times (the value of +// CCM-M plus one). +// Note: The EIP-120t always returns a 128-bit authentication field, of which +// the M least significant bytes are valid. All values are supported. +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 + +// Field: [21:19] CCM_L +// +// Defines L, which indicates the width of the length field for CCM operations; +// the length field in bytes equals the value of CMM-L plus one. All values are +// supported. +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 + +// Field: [18] CCM +// +// If set to 1, AES-CCM is selected +// AES-CCM is a combined mode, using AES for authentication and encryption. +// Note: Selecting AES-CCM mode requires writing of the AAD length register +// after all other registers. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR; selecting other AES modes than CTR mode is invalid. +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 + +// Field: [17:16] GCM +// +// Set these bits to 11 to select AES-GCM mode. +// AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the +// power of 128) for authentication and AES-CTR mode for encryption. +// Note: The CTR mode bit in this register must also be set to 1 to enable +// AES-CTR +// Bit combination description: +// 00 = No GCM mode +// 01 = Reserved, do not select +// 10 = Reserved, do not select +// 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) +// Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), +// other GCM modes are not allowed. +#define CRYPTO_AESCTL_GCM_W 2 +#define CRYPTO_AESCTL_GCM_M 0x00030000 +#define CRYPTO_AESCTL_GCM_S 16 + +// Field: [15] CBC_MAC +// +// Set to 1 to select AES-CBC MAC mode. +// The direction bit must be set to 1 for this mode. +// Selecting this mode requires writing the length register after all other +// registers. +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 + +// Field: [8:7] CTR_WIDTH +// +// Specifies the counter width for AES-CTR mode +// 00 = 32-bit counter +// 01 = 64-bit counter +// 10 = 96-bit counter +// 11 = 128-bit counter +// ENUMs: +// 128_BIT 128 bits +// 96_BIT 96 bits +// 64_BIT 64 bits +// 32_BIT 32 bits +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 + +// Field: [6] CTR +// +// If set to 1, AES counter mode (CTR) is selected. +// Note: This bit must also be set for GCM and CCM, when encryption/decryption +// is required. +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 + +// Field: [5] CBC +// +// If set to 1, cipher-block-chaining (CBC) mode is selected. +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 + +// Field: [4:3] KEY_SIZE +// +// This read-only field specifies the key size. +// The key size is automatically configured when a new key is loaded through +// the key store module. +// 00 = N/A - Reserved +// 01 = 128-bit +// 10 = 192-bit +// 11 = 256-bit +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 + +// Field: [2] DIR +// +// If set to 1 an encrypt operation is performed. +// If set to 0 a decrypt operation is performed. +// This bit must be written with a 1 when CBC-MAC is selected. +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 + +// Field: [1] INPUT_READY +// +// If 1, this status bit indicates that the 16-byte AES input buffer is empty. +// The host is permitted to write the next block of data. +// Writing 0 clears the bit to 0 and indicates that the AES core can use the +// provided input data block. +// Writing 1 to this bit is ignored. +// Note: For DMA operations, this bit is automatically controlled by the +// EIP-120t. +// After reset, this bit is 0. After writing a context, this bit becomes 1. +#define CRYPTO_AESCTL_INPUT_READY 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_BITN 1 +#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_S 1 + +// Field: [0] OUTPUT_READY +// +// If 1, this status bit indicates that an AES output block is available to be +// retrieved by the host. +// Writing 0 clears the bit to 0 and indicates that output data is read by the +// host. The AES core can provide a next output data block. +// Writing 1 to this bit is ignored. +// Note: For DMA operations, this bit is automatically controlled by the +// EIP-120t. +#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN0 +// +//***************************************************************************** +// Field: [31:0] C_LENGTH +// +// C_LENGTH[31:0] +// Bits [60:0] of the crypto length registers (LSW and MSW) store the +// cryptographic data length in bytes for all modes. Once processing with this +// context is started, this length decrements to 0. Data lengths up to (261: 1) +// bytes are allowed. +// For GCM, any value up to 236 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - +// 2, resulting in a maximum number of bytes of 236 - 32. +// A write to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN register +// All modes must have a length greater than 0. For the combined modes, it is +// allowed to have one of the lengths equal to 0. +// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program +// zero to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the EIP-120t. For block cipher modes, the +// data length must be programmed in multiples of the block cipher size, 16 +// bytes. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESDATALEN0_C_LENGTH_W 32 +#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_C_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATALEN1 +// +//***************************************************************************** +// Field: [28:0] C_LENGTH +// +// C_LENGTH[60:32] +// Bits [60:0] of the crypto length registers (LSW and MSW) store the +// cryptographic data length in bytes for all modes. Once processing with this +// context is started, this length decrements to 0. Data lengths up to (261: 1) +// bytes are allowed. +// For GCM, any value up to 236 - 32 bytes can be used. This is because a +// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - +// 2, resulting in a maximum number of bytes of 236 - 32. +// A write to this register triggers the engine to start using this context. +// This is valid for all modes except GCM and CCM. +// Note: For the combined modes (GCM and CCM), this length does not include the +// authentication only data; the authentication length is specified in the +// AESAUTHLEN register +// All modes must have a length greater than 0. For the combined modes, it is +// allowed to have one of the lengths equal to 0. +// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program +// zero to the length field; in that case the length is assumed infinite. +// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned +// data streams are not supported by the EIP-120t. For block cipher modes, the +// data length must be programmed in multiples of the block cipher size, 16 +// bytes. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESDATALEN1_C_LENGTH_W 29 +#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_C_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESAUTHLEN +// +//***************************************************************************** +// Field: [31:0] AUTH_LENGTH +// +// Bits [31:0] of the authentication length register store the authentication +// data length in bytes for combined modes only (GCM or CCM). +// Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any +// value up to (2^32 - 1) bytes can be used. Once processing with this context +// is started, this length decrements to 0. +// A write to this register triggers the engine to start using this context for +// GCM and CCM. +// For a host read operation, these registers return all-0s. +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT0 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN0 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[31:0] / AES output data[31:0] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT1 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN1 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[31:0] / AES output data[63:32] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT2 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN2 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[95:64] / AES output data[95:64] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAOUT3 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Data register 0 for output block data from the Crypto peripheral. +// These bits = AES Output Data[31:0] of {127:0] +// +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES engine via DMA. +// +// For a Host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range will read one word (4 bytes) of data out the 4-word deep +// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one +// full block) should be read before the core will move the next block to the +// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY +// must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESDATAIN3 +// +//***************************************************************************** +// Field: [31:0] AES_DATA_IN_OUT +// +// AES input data[127:96] / AES output data[127:96] +// Data registers for input/output block data to/from the EIP-120t. +// For normal operations, this register is not used, since data input and +// output is transferred from and to the AES core via DMA. For a host write +// operation, these registers must be written with the 128-bit input block for +// the next AES operation. Writing at a word-aligned offset within this address +// range stores the word (4 bytes) of data into the corresponding position of +// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is +// used for the next AES operation. If the last data block is not completely +// filled with valid data (see notes below), it is allowed to write only the +// words with valid data. Next AES operation is triggered by writing to the +// input_ready flag of the AES_CTRL register. +// For a host read operation, these registers contain the 128-bit output block +// from the latest AES operation. Reading from a word-aligned offset within +// this address range reads one word (4 bytes) of data out the 4-word deep (16 +// bytes = 128-bits AES block) data output buffer. The words (4 words, one full +// block) should be read before the core will move the next block to the data +// output buffer. To empty the data output buffer, the output_ready flag of the +// AES_CTRL register must be written. +// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid +// (message) bytes/words can be written with any data. +// Note: AES typically operates on 128 bits block multiple input data. The CTR, +// GCM and CCM modes form an exception. The last block of a CTR-mode message +// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the +// last block of both AAD and message data may contain less than 128 bits +// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks +// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR +// mode, the remaining data in an unaligned data block is ignored. +// Note: The AAD / authentication only data is not copied to the output buffer +// but only used for authentication. +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT0 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT0_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT1 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT1_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT2 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT2_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_AESTAGOUT3 +// +//***************************************************************************** +// Field: [31:0] AES_TAG +// +// AES_TAG[31:0] +// Bits [31:0] of this register stores the authentication value for the +// combined and authentication only modes. +// For a host read operation, these registers contain the last 128-bit TAG +// output of the EIP-120t; the TAG is available until the next context is +// written. +// This register will only contain valid data if the TAG is available and when +// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for +// operations/modes that do not return a TAG, reads from this register return +// data from the IV register. +#define CRYPTO_AESTAGOUT3_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_AES_TAG_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN1 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[63:32] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN2 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[95:64] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN3 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[127:96] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when the rfd_in bit of +// the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is +// busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN4 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[159:128] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN5 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[191:160] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN6 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[223:192] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN7 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[255:224] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN8 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[287:256] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN9 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[319:288] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN10 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[351:320] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN11 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[383:352] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN12 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[415:384] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN13 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[447:416] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN14 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[479:448] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN15 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[511:480] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN16 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[543:512] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN17 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[575:544] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN18 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[607:576] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN19 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[639:608] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN20 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[671:640] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN21 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[703:672] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN22 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[735:704] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN23 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[767:736] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN24 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[799:768] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN25 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[831:800] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN26 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[863:832] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN27 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[895:864] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN28 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[923:896] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN29 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[959:924] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN30 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[991:960] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDATAIN31 +// +//***************************************************************************** +// Field: [31:0] HASH_DATA_IN +// +// HASH_DATA_IN[1023:992] +// These registers must be written with the 512-bit input data. The data lines +// are connected directly to the data input of the hash module and hence into +// the engine's internal data buffer. Writing to each of the registers triggers +// a corresponding 32-bit write enable to the internal buffer. +// Note: The host may only write the input data buffer when +// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine +// is busy with processing. During processing, it is not allowed to write new +// input data. +// For message lengths larger than 64 bytes, multiple blocks of data are +// written to this input buffer using a handshake through flags of the +// HASHIOBUFCTRL register. All blocks except the last are required to be 512 +// bits in size. If the last block is not 512 bits long, only the least +// significant bits of data must be written, but they must be padded with 0s to +// the next 32-bit boundary. +// Host read operations from these register addresses return 0s. +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHIOBUFCTRL +// +//***************************************************************************** +// Field: [7] PAD_DMA_MESSAGE +// +// Note: This bit must only be used when data is supplied through the DMA. It +// should not be used when data is supplied through the slave interface. +// This bit indicates whether the hash engine has to pad the message, received +// through the DMA and finalize the hash. +// When set to 1, the hash engine pads the last block using the programmed +// length. After padding, the final hash result is calculated. +// When set to 0, the hash engine treats the last written block as block-size +// aligned and calculates the intermediate digest. +// This bit is automatically cleared when the last DMA data block is arrived in +// the hash engine. +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 + +// Field: [6] GET_DIGEST +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates whether the hash engine should provide the hash digest. +// When provided simultaneously with data_in_av, the hash digest is provided +// after processing the data that is currently in the HASHDATAINn register. +// When provided without data_in_av, the current internal digest buffer value +// is copied to the HASHDIGESTn registers. +// The host must write a 1 to this bit to make the intermediate hash digest +// available. +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (that is, reads 0) when the hash engine +// has processed the contents of the HASHDATAINn register. In the period +// between this bit is set by the host and the actual HASHDATAINn processing, +// this bit reads 1. +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 + +// Field: [5] PAD_MESSAGE +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates that the HASHDATAINn registers hold the last data of the +// message and hash padding must be applied. +// The host must write this bit to 1 in order to indicate to the hash engine +// that the HASHDATAINn register currently holds the last data of the message. +// When pad_message is set to 1, the hash engine will add padding bits to the +// data currently in the HASHDATAINn register. +// When the last message block is smaller than 512 bits, the pad_message bit +// must be set to 1 together with the data_in_av bit. +// When the last message block is equal to 512 bits, pad_message may be set +// together with data_in_av. In this case the pad_message bit may also be set +// after the last data block has been written to the hash engine (so when the +// rfd_in bit has become 1 again after writing the last data block). +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (i.e. reads 0) by the hash engine. This +// bit reads 1 between the time it was set by the host and the hash engine +// interpreted its value. +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 + +// Field: [2] RFD_IN +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit can be ignored when data is received through +// the DMA. +// Read-only status of the input buffer of the hash engine. +// When 1, the input buffer of the hash engine can accept new data; the +// HASHDATAINn registers can safely be populated with new data. +// When 0, the input buffer of the hash engine is processing the data that is +// currently in HASHDATAINn; writing new data to these registers is not +// allowed. +#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 + +// Field: [1] DATA_IN_AV +// +// Note: The bit description below is only applicable when data is sent through +// the slave interface. This bit must be set to 0 when data is received through +// the DMA. +// This bit indicates that the HASHDATAINn registers contain new input data for +// processing. +// The host must write a 1 to this bit to start processing the data in +// HASHDATAINn; the hash engine will process the new data as soon as it is +// ready for it (rfd_in bit is 1). +// Writing 0 to this bit has no effect. +// This bit is automatically cleared (i.e. reads as 0) when the hash engine +// starts processing the HASHDATAINn contents. This bit reads 1 between the +// time it was set by the host and the hash engine actually starts processing +// the input data block. +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 + +// Field: [0] OUTPUT_FULL +// +// Indicates that the output buffer registers (HASHDIGESTn) are available for +// reading by the host. +// When this bit reads 0, the output buffer registers are released; the hash +// engine is allowed to write new data to it. In this case, the registers +// should not be read by the host. +// When this bit reads 1, the hash engine has stored the result of the latest +// hash operation in the output buffer registers. As long as this bit reads 1, +// the host may read output buffer registers and the hash engine is prevented +// from writing new data to the output buffer. +// After retrieving the hash result data from the output buffer, the host must +// write a 1 to this bit to clear it. This makes the digest output buffer +// available for the hash engine to store new hash results. +// Writing 0 to this bit has no effect. +// Note: If this bit is asserted (1) no new operation should be started before +// the digest is retrieved from the hash engine and this bit is cleared (0). +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHMODE +// +//***************************************************************************** +// Field: [6] SHA384_MODE +// +// The host must write this bit with 1 prior to processing a SHA 384 session. +#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 +#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_S 6 + +// Field: [5] SHA512_MODE +// +// The host must write this bit with 1 prior to processing a SHA 512 session. +#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 +#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_S 5 + +// Field: [4] SHA224_MODE +// +// The host must write this bit with 1 prior to processing a SHA 224 session. +#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 +#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_S 4 + +// Field: [3] SHA256_MODE +// +// The host must write this bit with 1 prior to processing a SHA 256 session. +#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 +#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_S 3 + +// Field: [0] NEW_HASH +// +// When set to 1, it indicates that the hash engine must start processing a new +// hash session. The [HASHDIGESTn.* ] registers will automatically be loaded +// with the initial hash algorithm constants of the selected hash algorithm. +// When this bit is 0 while the hash processing is started, the initial hash +// algorithm constants are not loaded in the HASHDIGESTn registers. The hash +// engine will start processing with the digest that is currently in its +// internal HASHDIGESTn registers. +// This bit is automatically cleared when hash processing is started. +#define CRYPTO_HASHMODE_NEW_HASH 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_BITN 0 +#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHINLENL +// +//***************************************************************************** +// Field: [31:0] LENGTH_IN +// +// LENGTH_IN[31:0] +// Message length registers. The content of these registers is used by the hash +// engine during the message padding phase of the hash session. The data lines +// of this registers are directly connected to the interface of the hash +// engine. +// For a write operation by the host, these registers should be written with +// the message length in bits. +// +// Final hash operations: +// The total input data length must be programmed for new hash operations that +// require finalization (padding). The input data must be provided through the +// slave or DMA interface. +// +// Continued hash operations (finalized): +// For continued hash operations that require finalization, the total message +// length must be programmed, including the length of previously hashed data +// that corresponds to the written input digest. +// +// Non-final hash operations: +// For hash operations that do not require finalization (input data length is +// multiple of 512-bits which is SHA-256 data block size), the length field +// does not need to be programmed since not used by the operation. +// +// If the message length in bits is below (2^32-1), then only this register +// needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s +// in this case. +// The host may write the length register at any time during the hash session +// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written +// before the last data of the active hash session is written into the hash +// engine. +// host read operations from these register locations will return 0s. +// Note: When getting data from DMA, this register must be programmed before +// DMA is programmed to start. +#define CRYPTO_HASHINLENL_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENL_LENGTH_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHINLENH +// +//***************************************************************************** +// Field: [31:0] LENGTH_IN +// +// LENGTH_IN[63:32] +// Message length registers. The content of these registers is used by the hash +// engine during the message padding phase of the hash session. The data lines +// of this registers are directly connected to the interface of the hash +// engine. +// For a write operation by the host, these registers should be written with +// the message length in bits. +// +// Final hash operations: +// The total input data length must be programmed for new hash operations that +// require finalization (padding). The input data must be provided through the +// slave or DMA interface. +// +// Continued hash operations (finalized): +// For continued hash operations that require finalization, the total message +// length must be programmed, including the length of previously hashed data +// that corresponds to the written input digest. +// +// Non-final hash operations: +// For hash operations that do not require finalization (input data length is +// multiple of 512-bits which is SHA-256 data block size), the length field +// does not need to be programmed since not used by the operation. +// +// If the message length in bits is below (2^32-1), then only HASHINLENL needs +// to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in +// this case. +// The host may write the length register at any time during the hash session +// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written +// before the last data of the active hash session is written into the hash +// engine. +// host read operations from these register locations will return 0s. +// Note: When getting data from DMA, this register must be programmed before +// DMA is programmed to start. +#define CRYPTO_HASHINLENH_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENH_LENGTH_IN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTA +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[31:0] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTB +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[63:32] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTC +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[95:64] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTD +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[127:96] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTE +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[159:128] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTF +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[191:160] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTG +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[223:192] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTH +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[255:224] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTI +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[287:256] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTJ +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[319:288] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTK +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[351:320] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTL +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[383:352] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTM +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[415:384] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTN +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[447:416] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTO +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[479:448] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HASHDIGESTP +// +//***************************************************************************** +// Field: [31:0] HASH_DIGEST +// +// HASH_DIGEST[511:480] +// Hash digest registers +// Write operation: +// +// Continued hash: +// These registers should be written with the context data, before the start of +// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash +// session). +// +// New hash: +// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the +// internal digest registers are automatically set to the SHA-256 algorithm +// constant and these register should not be written. +// +// Reading from these registers provides the intermediate hash result +// (non-final hash operation) or the final hash result (final hash operation) +// after data processing. +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_ALGSEL +// +//***************************************************************************** +// Field: [32] HASH_SHA_512 +// +// If set to one, selects the hash engine in 512B mode as destination for the +// DMA +// The maximum transfer size to DMA engine is set to 64 bytes for reading and +// 32 bytes for writing (the latter is only applicable if the hash result is +// written out through the DMA). +#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 +#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_S 32 + +// Field: [31] TAG +// +// If this bit is cleared to 0, the DMA operation involves only data. +// If this bit is set, the DMA operation includes a TAG (Authentication Result +// / Digest). +// For SHA-256 operation, a DMA must be set up for both input data and TAG. For +// any other selected module, setting this bit only allows a DMA that reads the +// TAG. No data allowed to be transferred to or from the selected module via +// the DMA. +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 + +// Field: [2] HASH_SHA_256 +// +// If set to one, selects the hash engine in 256B mode as destination for the +// DMA +// The maximum transfer size to DMA engine is set to 64 bytes for reading and +// 32 bytes for writing (the latter is only applicable if the hash result is +// written out through the DMA). +#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 +#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_S 2 + +// Field: [1] AES +// +// If set to one, selects the AES engine as source/destination for the DMA +// The read and write maximum transfer size to the DMA engine is set to 16 +// bytes. +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 + +// Field: [0] KEY_STORE +// +// If set to one, selects the Key Store as destination for the DMA +// The maximum transfer size to DMA engine is set to 32 bytes (however +// transfers of 16, 24 and 32 bytes are allowed) +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_DMAPROTCTL +// +//***************************************************************************** +// Field: [0] PROT_EN +// +// Select AHB transfer protection control for DMA transfers using the key store +// area as destination. +// 0 : transfers use 'USER' type access. +// 1 : transfers use 'PRIVILEGED' type access. +#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_SWRESET +// +//***************************************************************************** +// Field: [0] SW_RESET +// +// If this bit is set to 1, the following modules are reset: +// - Master control internal state is reset. That includes interrupt, error +// status register, and result available interrupt generation FSM. +// - Key store module state is reset. That includes clearing the written area +// flags; therefore, the keys must be reloaded to the key store module. +// Writing 0 has no effect. +// The bit is self cleared after executing the reset. +#define CRYPTO_SWRESET_SW_RESET 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_BITN 0 +#define CRYPTO_SWRESET_SW_RESET_M 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQTYPE +// +//***************************************************************************** +// Field: [0] LEVEL +// +// If this bit is 0, the interrupt output is a pulse. +// If this bit is set to 1, the interrupt is a level interrupt that must be +// cleared by writing the interrupt clear register. +// This bit is applicable for both interrupt output signals. +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQEN +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt +// output is disabled and remains 0. +// If this bit is set to 1, the DMA input done interrupt output is enabled. +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If this bit is set to 0, the result available (irq_result_av) interrupt +// output is disabled and remains 0. +// If this bit is set to 1, the result available interrupt output is enabled. +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQCLR +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// If 1 is written to this bit, the DMA bus error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// If 1 is written to this bit, the key store write error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// If 1 is written to this bit, the key store read error status is cleared. +// Writing 0 has no effect. +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt +// output is cleared. +// Writing 0 has no effect. +// Note that clearing an interrupt makes sense only if the interrupt output is +// programmed as level (refer to IRQTYPE). +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, the result available (irq_result_av) interrupt +// output is cleared. +// Writing 0 has no effect. +// Note that clearing an interrupt makes sense only if the interrupt output is +// programmed as level (refer to IRQTYPE). +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSET +// +//***************************************************************************** +// Field: [1] DMA_IN_DONE +// +// If 1 is written to this bit, the DMA data in done (irq_dma_in_done) +// interrupt output is set to one. +// Writing 0 has no effect. +// If the interrupt configuration register is programmed to pulse, clearing the +// DMA data in done (irq_dma_in_done) interrupt is not needed. If it is +// programmed to level, clearing the interrupt output should be done by writing +// the interrupt clear register (IRQCLR.DMA_IN_DONE). +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// If 1 is written to this bit, the result available (irq_result_av) interrupt +// output is set to one. +// Writing 0 has no effect. +// If the interrupt configuration register is programmed to pulse, clearing the +// result available (irq_result_av) interrupt is not needed. If it is +// programmed to level, clearing the interrupt output should be done by writing +// the interrupt clear register (IRQCLR.RESULT_AVAIL). +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_IRQSTAT +// +//***************************************************************************** +// Field: [31] DMA_BUS_ERR +// +// This bit is set when a DMA bus error is detected during a DMA operation. The +// value of this register is held until it is cleared through the +// IRQCLR.DMA_BUS_ERR +// Note: This error is asserted if an error is detected on the AHB master +// interface during a DMA operation. +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 + +// Field: [30] KEY_ST_WR_ERR +// +// This bit is set when a write error is detected during the DMA write +// operation to the key store memory. The value of this register is held until +// it is cleared through the IRQCLR.KEY_ST_WR_ERR register. +// Note: This error is asserted if a DMA operation does not cover a full key +// area or more areas are written than expected. +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 + +// Field: [29] KEY_ST_RD_ERR +// +// This bit is set when a read error is detected during the read of a key from +// the key store, while copying it to the AES core. The value of this register +// is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. +// Note: This error is asserted if a key location is selected in the key store +// that is not available. +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 + +// Field: [1] DMA_IN_DONE +// +// This read only bit returns the actual DMA data in done (irq_data_in_done) +// interrupt status of the DMA data in done interrupt output pin +// (irq_data_in_done). +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 + +// Field: [0] RESULT_AVAIL +// +// This read only bit returns the actual result available (irq_result_av) +// interrupt status of the result available interrupt output pin +// (irq_result_av). +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 + +//***************************************************************************** +// +// Register: CRYPTO_O_HWVER +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// Major version number +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// Minor version number +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// Patch level +// Starts at 0 at first delivery of this version +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 + +// Field: [15:8] VER_NUM_COMPL +// +// These bits simply contain the complement of bits [7:0] (0x87), used by a +// driver to ascertain that the EIP-120t register is indeed read. +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 + +// Field: [7:0] VER_NUM +// +// These bits encode the EIP number for the EIP-120t, this field contains the +// value 120 (decimal) or 0x78. +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 + + +#endif // __CRYPTO__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi.h new file mode 100644 index 00000000..d894dd64 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi.h @@ -0,0 +1,195 @@ +/****************************************************************************** +* Filename: hw_ddi.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_H__ +#define __HW_DDI_H__ + +//***************************************************************************** +// +// This file contains macros for controlling the DDI master and +// accessing DDI Slave registers via the DDI Master. +// There are 3 categories of macros in this file: +// - macros that provide an offset to a register +// located within the DDI Master itself. +// - macros that define bits or bitfields +// within the DDI Master Registers. +// - macros that provide an "instruction offset" +// that are used when accessing a DDI Slave. +// +// The macros that that provide DDI Master register offsets and +// define bits and bitfields for those registers are the typical +// macros that appear in most hw_.h header files. In +// the following example DDI_O_CFG is a macro for a +// register offset and DDI_CFG_WAITFORACK is a macro for +// a bit in that register. This example code will set the WAITFORACK +// bit in register DDI_O_CFG of the DDI Master. (Note: this +// access the Master not the Slave). +// +// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; +// +// +// The "instruction offset" macros are used to pass an instruction to +// the DDI Master when accessing DDI slave registers. These macros are +// only used when accessing DDI Slave Registers. (Remember DDI +// Master Registers are accessed normally). +// +// The instructions supported when accessing a DDI Slave Regsiter follow: +// - Direct Access to a DDI Slave register. I.e. read or +// write the register. +// - Set the specified bits in a DDI Slave register. +// - Clear the specified bits in a DDI Slave register. +// - Mask write of 4 bits to the a DDI Slave register. +// - Mask write of 8 bits to the a DDI Slave register. +// - Mask write of 16 bits to the a DDI Slave register. +// +// Note: only the "Direct Access" offset should be used when reading +// a DDI Slave register. Only 8- and 16-bit reads are supported. +// +// The generic format of using this marcos for a read follows: +// // read low 16-bits in DDI_SLAVE_OFF +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); +// +// // read high 16-bits in DDI_SLAVE_OFF +// // add 2 for data[31:16] +// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); + +// // read data[31:24] byte in DDI_SLAVE_OFF +// // add 3 for data[31:24] +// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); +// +// Notes: In the above example: +// - DDI_MASTER_BASE is the base address of the DDI Master defined +// in the hw_memmap.h header file. +// - DDI_SLAVE_OFF is the DDI Slave offset defined in the +// hw_.h header file (e.g. hw_osc_top.h for the oscsc +// oscillator modules. +// - DDI_O_DIR is the "instruction offset" macro defined in this +// file that specifies the Direct Access instruction. +// +// Writes can use any of the "instruction macros". +// The following examples do a "direct write" to DDI Slave register +// DDI_SLAVE_OFF using different size operands: +// +// // ---------- DIRECT WRITES ---------- +// // Write 32-bits aligned +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; + +// // Write 16-bits aligned to high 16-bits then low 16-bits +// // Add 2 to get to high 16-bits. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; +// +// // Write each byte at DDI_SLAVE_OFF, one at a time. +// // Add 1,2,or 3 to get to bytes 1,2, or 3. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; +// +// // ---------- SET/CLR ---------- +// The set and clear functions behave similarly to eachother. Each +// can be performed on an 8-, 16-, or 32-bit operand. +// Examples follow: +// // Set all odd bits in a 32-bit words +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; +// +// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; +// +// // Set even bits in byte 2 (data[23:16]) using 8-bit operand +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; +// +// // ---------- MASKED WRITES ---------- +// The mask writes are a bit different. They operate on nibbles, +// bytes, and 16-bit elements. Two operands are required; a 'mask' +// and 'data'; The operands are concatenated and written to the master. +// e.g. the mask and data are combined as follows for a 16 bit masked +// write: +// (mask << 16) | data; +// Examples follow: +// +// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register +// // a long write is needed (32-bits). +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; + +// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register +// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! +// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; +// +// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). +// // a short write is needed (16-bits). +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; +// +// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). +// // add 2 to get to byte 1. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; +// +// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). +// // add 6 to get to byte 3. +// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; +// +// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). +// // Byte write is needed. +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; +// +// // Do an 4 bit masked write of 4 to data[7:4]). +// // Add 1 for next nibble +// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the DDI master instruction offsets. +// +//***************************************************************************** +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 7:4 are mask. Bits 3:0 are data. + // Requires 'byte' write. +#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 15:8 are mask. Bits 7:0 are data. + // Requires 'short' write. +#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. + // Data bit[n] is written if mask bit[n] is set ('1'). + // Bits 31:16 are mask. Bits 15:0 are data. + // Requires 'long' write. + + + +#endif // __HW_DDI_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi_0_osc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi_0_osc.h new file mode 100644 index 00000000..d23e8a4f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ddi_0_osc.h @@ -0,0 +1,1158 @@ +/****************************************************************************** +* Filename: hw_ddi_0_osc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_DDI_0_OSC_H__ +#define __HW_DDI_0_OSC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// DDI_0_OSC component +// +//***************************************************************************** +// Control 0 +#define DDI_0_OSC_O_CTL0 0x00000000 + +// Control 1 +#define DDI_0_OSC_O_CTL1 0x00000004 + +// RADC External Configuration +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 + +// Amplitude Compensation Control +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C + +// Amplitude Compensation Threshold 1 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 + +// Amplitude Compensation Threshold 2 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 + +// Analog Bypass Values 1 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 + +// Internal +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C + +// Analog Test Control +#define DDI_0_OSC_O_ATESTCTL 0x00000020 + +// ADC Doubler Nanoamp Control +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 + +// XOSCHF Control +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 + +// Low Frequency Oscillator Control +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C + +// RCOSCHF Control +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 + +// RCOSC_MF Control +#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 + +// Status 0 +#define DDI_0_OSC_O_STAT0 0x0000003C + +// Status 1 +#define DDI_0_OSC_O_STAT1 0x00000040 + +// Status 2 +#define DDI_0_OSC_O_STAT2 0x00000044 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL0 +// +//***************************************************************************** +// Field: [31] XTAL_IS_24M +// +// Set based on the accurate high frequency XTAL. +// ENUMs: +// 24M Internal. Only to be used through TI provided API. +// 48M Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 + +// Field: [29] BYPASS_XOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 + +// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 + +// Field: [27:26] DOUBLER_START_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 + +// Field: [25] DOUBLER_RESET_DURATION +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 + +// Field: [24] CLK_DCDC_SRC_SEL +// +// Select DCDC clock source. +// +// 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC +// 1: CLK_DCDC is always 48 MHz clock from RCOSC +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 + +// Field: [14] HPOSC_MODE_EN +// +// 0: HPOSC mode is not enabled. The 48 MHz crystal is required for radio +// operation. +// 1: Enables HPOSC mode. The internal HPOSC can be used as HF system clock and +// for radio operation. +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 + +// Field: [12] RCOSC_LF_TRIMMED +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 + +// Field: [11] XOSC_HF_POWER_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 + +// Field: [10] XOSC_LF_DIG_BYPASS +// +// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf +// clock. +// +// 0: Use 32kHz XOSC as xosc_lf clock source +// 1: Use digital input (from AON) as xosc_lf clock source. +// +// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf +// as the sclk_lf source. The muxing performed by this bit is not glitch free. +// The following procedure must be followed when changing this field to avoid +// glitches on sclk_lf. +// +// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock +// source. +// 2) Set or clear this bit to bypass or not bypass the xosc_lf. +// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. +// +// It is recommended that either the rcosc_hf or xosc_hf (whichever is +// currently active) be selected as the source in step 1 above. This provides a +// faster clock change. +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 + +// Field: [9] CLK_LOSS_EN +// +// Enable clock loss detection and hence the indicators to the system +// controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. +// +// 0: Disable +// 1: Enable +// +// Clock loss detection must be disabled when changing the sclk_lf source. +// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf +// source has completed. +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 + +// Field: [8:7] ACLK_TDC_SRC_SEL +// +// Source select for aclk_tdc. +// +// 00: RCOSC_HF (48MHz) +// 01: RCOSC_HF (24MHz) +// 10: XOSC_HF (24MHz) +// 11: Not used +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 + +// Field: [6:4] ACLK_REF_SRC_SEL +// +// Source select for aclk_ref +// +// 000: RCOSC_HF derived (31.25kHz) +// 001: XOSC_HF derived (31.25kHz) +// 010: RCOSC_LF (32kHz) +// 011: XOSC_LF (32.768kHz) +// 100: RCOSC_MF (2MHz) +// 101-111: Not used +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 + +// Field: [3:2] SCLK_LF_SRC_SEL +// +// Source select for sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN +// = 1) +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 + +// Field: [0] SCLK_HF_SRC_SEL +// +// Source select for sclk_hf. +// ENUMs: +// XOSC High frequency XOSC or HPOSC clk (use HPOSC when +// HPOSC_MODE_EN = 1 +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_CTL1 +// +//***************************************************************************** +// Field: [22:18] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 + +// Field: [17] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 + +// Field: [1:0] XOSC_HF_FAST_START +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RADCEXTCFG +// +//***************************************************************************** +// Field: [31:22] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 + +// Field: [21:16] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 + +// Field: [15:12] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 + +// Field: [11:6] RADC_DAC_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 + +// Field: [5] RADC_MODE_IS_SAR +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPCTL +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 + +// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 250KHZ Internal. Only to be used through TI provided API. +// 500KHZ Internal. Only to be used through TI provided API. +// 1MHZ Internal. Only to be used through TI provided API. +// 2MHZ Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 + +// Field: [27] AMPCOMP_SW_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 + +// Field: [26] AMPCOMP_SW_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_AMPCOMPTH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTH +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL1 +// +//***************************************************************************** +// Field: [19:16] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 + +// Field: [15:0] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ANABYPASSVAL2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ATESTCTL +// +//***************************************************************************** +// Field: [31] SCLK_LF_AUX_EN +// +// Enable 32 kHz clock to AUX_COMPB. +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 + +// Field: [15:14] TEST_RCOSCMF +// +// Test mode control for RCOSC_MF +// +// 0x0: test modes disabled +// 0x1: boosted bias current into self biased inverter +// 0x2: clock qualification disabled +// 0x3: boosted bias current into self biased inverter + clock qualification +// disabled +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 + +// Field: [13:12] ATEST_RCOSCMF +// +// ATEST control for RCOSC_MF +// +// 0x0: ATEST disabled +// 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* +// enabled to send out 2MHz clock. +// 0x2: ATEST disabled +// 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* +// enabled to send out 2MHz clock. +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL +// +//***************************************************************************** +// Field: [24] NANOAMP_BIAS_ENABLE +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 + +// Field: [23] SPARE23 +// +// Software should not rely on the value of a reserved. Writing any other value +// than the reset value may result in undefined behavior +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 + +// Field: [5] ADC_SH_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 + +// Field: [4] ADC_SH_VBUF_EN +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 + +// Field: [1:0] ADC_IREF_CTRL +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_XOSCHFCTL +// +//***************************************************************************** +// Field: [13] TCXO_MODE_XOSC_HF_EN +// +// If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, +// turning on the XOSC_HF bias current allowing a DC bias point to be provided +// to the clipped-sine wave clock signal on external input. +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 + +// Field: [12] TCXO_MODE +// +// If this register is 1 when BYPASS is 1, this will enable clock +// qualification on the TCXO clock on external input. This register has no +// effect when BYPASS is 0. +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 + +// Field: [9:8] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 + +// Field: [6] BYPASS +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 + +// Field: [4:2] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 + +// Field: [1:0] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_LFOSCCTL +// +//***************************************************************************** +// Field: [23:22] XOSCLF_REGULATOR_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 + +// Field: [21:18] XOSCLF_CMIRRWR_RATIO +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 + +// Field: [9:8] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// 6P0MEG Internal. Only to be used through TI provided API. +// 6P5MEG Internal. Only to be used through TI provided API. +// 7P0MEG Internal. Only to be used through TI provided API. +// 7P5MEG Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 + +// Field: [7:0] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCHFCTL +// +//***************************************************************************** +// Field: [15:8] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_RCOSCMFCTL +// +//***************************************************************************** +// Field: [15:9] RCOSC_MF_CAP_ARRAY +// +// Adjust RCOSC_MF capacitor array. +// +// 0x0: nominal frequency, 0.625pF +// 0x40: highest frequency, 0.125pF +// 0x3F: lowest frequency, 1.125pF +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 + +// Field: [8] RCOSC_MF_REG_SEL +// +// Choose regulator type. +// +// 0: default +// 1: alternate +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 + +// Field: [7:6] RCOSC_MF_RES_COARSE +// +// Select coarse resistor for frequency adjustment. +// +// 0x0: 400kohms, default +// 0x1: 300kohms, min +// 0x2: 600kohms, max +// 0x3: 500kohms +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 + +// Field: [5:4] RCOSC_MF_RES_FINE +// +// Select fine resistor for frequency adjustment. +// +// 0x0: 11kohms, minimum resistance, max freq +// 0x1: 13kohms +// 0x2: 16kohms +// 0x3: 20kohms, max resistance, min freq +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 + +// Field: [3:0] RCOSC_MF_BIAS_ADJ +// +// Adjusts bias current to RCOSC_MF. +// +// 0x8 minimum current +// 0x0 default current +// 0x7 maximum current +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT0 +// +//***************************************************************************** +// Field: [30:29] SCLK_LF_SRC +// +// Indicates source for the sclk_lf +// ENUMs: +// XOSCLF Low frequency XOSC +// RCOSCLF Low frequency RCOSC +// XOSCHFDLF Low frequency clock derived from High Frequency +// XOSC +// RCOSCHFDLF Low frequency clock derived from High Frequency +// RCOSC +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 + +// Field: [28] SCLK_HF_SRC +// +// Indicates source for the sclk_hf +// ENUMs: +// XOSC High frequency XOSC +// RCOSC High frequency RCOSC clock +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 + +// Field: [22] RCOSC_HF_EN +// +// RCOSC_HF_EN +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 + +// Field: [21] RCOSC_LF_EN +// +// RCOSC_LF_EN +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 + +// Field: [20] XOSC_LF_EN +// +// XOSC_LF_EN +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 + +// Field: [19] CLK_DCDC_RDY +// +// CLK_DCDC_RDY +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 + +// Field: [18] CLK_DCDC_RDY_ACK +// +// CLK_DCDC_RDY_ACK +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 + +// Field: [17] SCLK_HF_LOSS +// +// Indicates sclk_hf is lost +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 + +// Field: [16] SCLK_LF_LOSS +// +// Indicates sclk_lf is lost +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 + +// Field: [15] XOSC_HF_EN +// +// Indicates that XOSC_HF is enabled. +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 + +// Field: [13] XB_48M_CLK_EN +// +// Indicates that the 48MHz clock from the DOUBLER is enabled. +// +// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler +// bypass for the 48MHz crystal). +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 + +// Field: [11] XOSC_HF_LP_BUF_EN +// +// XOSC_HF_LP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 + +// Field: [10] XOSC_HF_HP_BUF_EN +// +// XOSC_HF_HP_BUF_EN +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 + +// Field: [8] ADC_THMET +// +// ADC_THMET +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 + +// Field: [7] ADC_DATA_READY +// +// indicates when adc_data is ready. +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 + +// Field: [6:1] ADC_DATA +// +// adc_data +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 + +// Field: [0] PENDINGSCLKHFSWITCHING +// +// Indicates when SCLK_HF clock source is ready to be switched +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT1 +// +//***************************************************************************** +// Field: [31:28] RAMPSTATE +// +// AMPCOMP FSM State +// ENUMs: +// FAST_START_SETTLE FAST_START_SETTLE +// FAST_START FAST_START +// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 +// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE +// IBIAS_INC IBIAS_INCREMENT +// LPM_UPDATE LPM_UPDATE +// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE +// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE +// IDAC_INCREMENT IDAC_INCREMENT +// HPM_UPDATE HPM_UPDATE +// HPM_RAMP3 HPM_RAMP3 +// HPM_RAMP2 HPM_RAMP2 +// HPM_RAMP1 HPM_RAMP1 +// INITIALIZATION INITIALIZATION +// RESET RESET +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 + +// Field: [27:22] HPM_UPDATE_AMP +// +// XOSC_HF amplitude during HPM_UPDATE state. +// When amplitude compensation of XOSC_HF is enabled in high performance mode, +// this value is the amplitude of the crystal oscillations measured by the +// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 +// would indicate that the amplitude of the crystal is approximately 480 mV. +// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 + +// Field: [21:16] LPM_UPDATE_AMP +// +// XOSC_HF amplitude during LPM_UPDATE state +// When amplitude compensation of XOSC_HF is enabled in low power mode, this +// value is the amplitude of the crystal oscillations measured by the on-chip +// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would +// indicate that the amplitude of the crystal is approximately 480 mV. To +// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero +// value. +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 + +// Field: [15] FORCE_RCOSC_HF +// +// force_rcosc_hf +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 + +// Field: [14] SCLK_HF_EN +// +// SCLK_HF_EN +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 + +// Field: [13] SCLK_MF_EN +// +// SCLK_MF_EN +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 + +// Field: [12] ACLK_ADC_EN +// +// ACLK_ADC_EN +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 + +// Field: [11] ACLK_TDC_EN +// +// ACLK_TDC_EN +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 + +// Field: [10] ACLK_REF_EN +// +// ACLK_REF_EN +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 + +// Field: [9] CLK_CHP_EN +// +// CLK_CHP_EN +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 + +// Field: [8] CLK_DCDC_EN +// +// CLK_DCDC_EN +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 + +// Field: [7] SCLK_HF_GOOD +// +// SCLK_HF_GOOD +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 + +// Field: [6] SCLK_MF_GOOD +// +// SCLK_MF_GOOD +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 + +// Field: [5] SCLK_LF_GOOD +// +// SCLK_LF_GOOD +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 + +// Field: [4] ACLK_ADC_GOOD +// +// ACLK_ADC_GOOD +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 + +// Field: [3] ACLK_TDC_GOOD +// +// ACLK_TDC_GOOD +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 + +// Field: [2] ACLK_REF_GOOD +// +// ACLK_REF_GOOD. +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 + +// Field: [1] CLK_CHP_GOOD +// +// CLK_CHP_GOOD +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 + +// Field: [0] CLK_DCDC_GOOD +// +// CLK_DCDC_GOOD +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 + +//***************************************************************************** +// +// Register: DDI_0_OSC_O_STAT2 +// +//***************************************************************************** +// Field: [31:26] ADC_DCBIAS +// +// DC Bias read by RADC during SAR mode +// The value is an unsigned integer. It is used for debug only. +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 + +// Field: [25] HPM_RAMP1_THMET +// +// Indication of threshold is met for hpm_ramp1 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 + +// Field: [24] HPM_RAMP2_THMET +// +// Indication of threshold is met for hpm_ramp2 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 + +// Field: [23] HPM_RAMP3_THMET +// +// Indication of threshold is met for hpm_ramp3 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 + +// Field: [15:12] RAMPSTATE +// +// xosc_hf amplitude compensation FSM +// +// This is identical to STAT1.RAMPSTATE. See that description for encoding. +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 + +// Field: [3] AMPCOMP_REQ +// +// ampcomp_req +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 + +// Field: [2] XOSC_HF_AMPGOOD +// +// amplitude of xosc_hf is within the required threshold (set by DDI). Not used +// for anything just for debug/status +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 + +// Field: [1] XOSC_HF_FREQGOOD +// +// frequency of xosc_hf is good to use for the digital clocks +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 + +// Field: [0] XOSC_HF_RF_FREQGOOD +// +// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio +// operations. Used for SW to start synthesizer. +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 + + +#endif // __DDI_0_OSC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_event.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_event.h new file mode 100644 index 00000000..fe2ac655 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_event.h @@ -0,0 +1,3688 @@ +/****************************************************************************** +* Filename: hw_event_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_EVENT_H__ +#define __HW_EVENT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// EVENT component +// +//***************************************************************************** +// Output Selection for CPU Interrupt 0 +#define EVENT_O_CPUIRQSEL0 0x00000000 + +// Output Selection for CPU Interrupt 1 +#define EVENT_O_CPUIRQSEL1 0x00000004 + +// Output Selection for CPU Interrupt 2 +#define EVENT_O_CPUIRQSEL2 0x00000008 + +// Output Selection for CPU Interrupt 3 +#define EVENT_O_CPUIRQSEL3 0x0000000C + +// Output Selection for CPU Interrupt 4 +#define EVENT_O_CPUIRQSEL4 0x00000010 + +// Output Selection for CPU Interrupt 5 +#define EVENT_O_CPUIRQSEL5 0x00000014 + +// Output Selection for CPU Interrupt 6 +#define EVENT_O_CPUIRQSEL6 0x00000018 + +// Output Selection for CPU Interrupt 7 +#define EVENT_O_CPUIRQSEL7 0x0000001C + +// Output Selection for CPU Interrupt 8 +#define EVENT_O_CPUIRQSEL8 0x00000020 + +// Output Selection for CPU Interrupt 9 +#define EVENT_O_CPUIRQSEL9 0x00000024 + +// Output Selection for CPU Interrupt 10 +#define EVENT_O_CPUIRQSEL10 0x00000028 + +// Output Selection for CPU Interrupt 11 +#define EVENT_O_CPUIRQSEL11 0x0000002C + +// Output Selection for CPU Interrupt 12 +#define EVENT_O_CPUIRQSEL12 0x00000030 + +// Output Selection for CPU Interrupt 13 +#define EVENT_O_CPUIRQSEL13 0x00000034 + +// Output Selection for CPU Interrupt 14 +#define EVENT_O_CPUIRQSEL14 0x00000038 + +// Output Selection for CPU Interrupt 15 +#define EVENT_O_CPUIRQSEL15 0x0000003C + +// Output Selection for CPU Interrupt 16 +#define EVENT_O_CPUIRQSEL16 0x00000040 + +// Output Selection for CPU Interrupt 17 +#define EVENT_O_CPUIRQSEL17 0x00000044 + +// Output Selection for CPU Interrupt 18 +#define EVENT_O_CPUIRQSEL18 0x00000048 + +// Output Selection for CPU Interrupt 19 +#define EVENT_O_CPUIRQSEL19 0x0000004C + +// Output Selection for CPU Interrupt 20 +#define EVENT_O_CPUIRQSEL20 0x00000050 + +// Output Selection for CPU Interrupt 21 +#define EVENT_O_CPUIRQSEL21 0x00000054 + +// Output Selection for CPU Interrupt 22 +#define EVENT_O_CPUIRQSEL22 0x00000058 + +// Output Selection for CPU Interrupt 23 +#define EVENT_O_CPUIRQSEL23 0x0000005C + +// Output Selection for CPU Interrupt 24 +#define EVENT_O_CPUIRQSEL24 0x00000060 + +// Output Selection for CPU Interrupt 25 +#define EVENT_O_CPUIRQSEL25 0x00000064 + +// Output Selection for CPU Interrupt 26 +#define EVENT_O_CPUIRQSEL26 0x00000068 + +// Output Selection for CPU Interrupt 27 +#define EVENT_O_CPUIRQSEL27 0x0000006C + +// Output Selection for CPU Interrupt 28 +#define EVENT_O_CPUIRQSEL28 0x00000070 + +// Output Selection for CPU Interrupt 29 +#define EVENT_O_CPUIRQSEL29 0x00000074 + +// Output Selection for CPU Interrupt 30 +#define EVENT_O_CPUIRQSEL30 0x00000078 + +// Output Selection for CPU Interrupt 31 +#define EVENT_O_CPUIRQSEL31 0x0000007C + +// Output Selection for CPU Interrupt 32 +#define EVENT_O_CPUIRQSEL32 0x00000080 + +// Output Selection for CPU Interrupt 33 +#define EVENT_O_CPUIRQSEL33 0x00000084 + +// Output Selection for CPU Interrupt 34 +#define EVENT_O_CPUIRQSEL34 0x00000088 + +// Output Selection for CPU Interrupt 35 +#define EVENT_O_CPUIRQSEL35 0x0000008C + +// Output Selection for CPU Interrupt 36 +#define EVENT_O_CPUIRQSEL36 0x00000090 + +// Output Selection for CPU Interrupt 37 +#define EVENT_O_CPUIRQSEL37 0x00000094 + +// Output Selection for RFC Event 0 +#define EVENT_O_RFCSEL0 0x00000100 + +// Output Selection for RFC Event 1 +#define EVENT_O_RFCSEL1 0x00000104 + +// Output Selection for RFC Event 2 +#define EVENT_O_RFCSEL2 0x00000108 + +// Output Selection for RFC Event 3 +#define EVENT_O_RFCSEL3 0x0000010C + +// Output Selection for RFC Event 4 +#define EVENT_O_RFCSEL4 0x00000110 + +// Output Selection for RFC Event 5 +#define EVENT_O_RFCSEL5 0x00000114 + +// Output Selection for RFC Event 6 +#define EVENT_O_RFCSEL6 0x00000118 + +// Output Selection for RFC Event 7 +#define EVENT_O_RFCSEL7 0x0000011C + +// Output Selection for RFC Event 8 +#define EVENT_O_RFCSEL8 0x00000120 + +// Output Selection for RFC Event 9 +#define EVENT_O_RFCSEL9 0x00000124 + +// Output Selection for GPT0 0 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 + +// Output Selection for GPT0 1 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 + +// Output Selection for GPT1 0 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 + +// Output Selection for GPT1 1 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 + +// Output Selection for GPT2 0 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 + +// Output Selection for GPT2 1 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 + +// Output Selection for DMA Channel 1 SREQ +#define EVENT_O_UDMACH1SSEL 0x00000508 + +// Output Selection for DMA Channel 1 REQ +#define EVENT_O_UDMACH1BSEL 0x0000050C + +// Output Selection for DMA Channel 2 SREQ +#define EVENT_O_UDMACH2SSEL 0x00000510 + +// Output Selection for DMA Channel 2 REQ +#define EVENT_O_UDMACH2BSEL 0x00000514 + +// Output Selection for DMA Channel 3 SREQ +#define EVENT_O_UDMACH3SSEL 0x00000518 + +// Output Selection for DMA Channel 3 REQ +#define EVENT_O_UDMACH3BSEL 0x0000051C + +// Output Selection for DMA Channel 4 SREQ +#define EVENT_O_UDMACH4SSEL 0x00000520 + +// Output Selection for DMA Channel 4 REQ +#define EVENT_O_UDMACH4BSEL 0x00000524 + +// Output Selection for DMA Channel 5 SREQ +#define EVENT_O_UDMACH5SSEL 0x00000528 + +// Output Selection for DMA Channel 5 REQ +#define EVENT_O_UDMACH5BSEL 0x0000052C + +// Output Selection for DMA Channel 6 SREQ +#define EVENT_O_UDMACH6SSEL 0x00000530 + +// Output Selection for DMA Channel 6 REQ +#define EVENT_O_UDMACH6BSEL 0x00000534 + +// Output Selection for DMA Channel 7 SREQ +#define EVENT_O_UDMACH7SSEL 0x00000538 + +// Output Selection for DMA Channel 7 REQ +#define EVENT_O_UDMACH7BSEL 0x0000053C + +// Output Selection for DMA Channel 8 SREQ +#define EVENT_O_UDMACH8SSEL 0x00000540 + +// Output Selection for DMA Channel 8 REQ +#define EVENT_O_UDMACH8BSEL 0x00000544 + +// Output Selection for DMA Channel 9 SREQ +#define EVENT_O_UDMACH9SSEL 0x00000548 + +// Output Selection for DMA Channel 9 REQ +#define EVENT_O_UDMACH9BSEL 0x0000054C + +// Output Selection for DMA Channel 10 SREQ +#define EVENT_O_UDMACH10SSEL 0x00000550 + +// Output Selection for DMA Channel 10 REQ +#define EVENT_O_UDMACH10BSEL 0x00000554 + +// Output Selection for DMA Channel 11 SREQ +#define EVENT_O_UDMACH11SSEL 0x00000558 + +// Output Selection for DMA Channel 11 REQ +#define EVENT_O_UDMACH11BSEL 0x0000055C + +// Output Selection for DMA Channel 12 SREQ +#define EVENT_O_UDMACH12SSEL 0x00000560 + +// Output Selection for DMA Channel 12 REQ +#define EVENT_O_UDMACH12BSEL 0x00000564 + +// Output Selection for DMA Channel 13 REQ +#define EVENT_O_UDMACH13BSEL 0x0000056C + +// Output Selection for DMA Channel 14 REQ +#define EVENT_O_UDMACH14BSEL 0x00000574 + +// Output Selection for DMA Channel 15 REQ +#define EVENT_O_UDMACH15BSEL 0x0000057C + +// Output Selection for DMA Channel 16 SREQ +#define EVENT_O_UDMACH16SSEL 0x00000580 + +// Output Selection for DMA Channel 16 REQ +#define EVENT_O_UDMACH16BSEL 0x00000584 + +// Output Selection for DMA Channel 17 SREQ +#define EVENT_O_UDMACH17SSEL 0x00000588 + +// Output Selection for DMA Channel 17 REQ +#define EVENT_O_UDMACH17BSEL 0x0000058C + +// Output Selection for DMA Channel 21 SREQ +#define EVENT_O_UDMACH21SSEL 0x000005A8 + +// Output Selection for DMA Channel 21 REQ +#define EVENT_O_UDMACH21BSEL 0x000005AC + +// Output Selection for DMA Channel 22 SREQ +#define EVENT_O_UDMACH22SSEL 0x000005B0 + +// Output Selection for DMA Channel 22 REQ +#define EVENT_O_UDMACH22BSEL 0x000005B4 + +// Output Selection for DMA Channel 23 SREQ +#define EVENT_O_UDMACH23SSEL 0x000005B8 + +// Output Selection for DMA Channel 23 REQ +#define EVENT_O_UDMACH23BSEL 0x000005BC + +// Output Selection for DMA Channel 24 SREQ +#define EVENT_O_UDMACH24SSEL 0x000005C0 + +// Output Selection for DMA Channel 24 REQ +#define EVENT_O_UDMACH24BSEL 0x000005C4 + +// Output Selection for GPT3 0 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 + +// Output Selection for GPT3 1 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 + +// Output Selection for AUX Subscriber 0 +#define EVENT_O_AUXSEL0 0x00000700 + +// Output Selection for NMI Subscriber 0 +#define EVENT_O_CM3NMISEL0 0x00000800 + +// Output Selection for I2S Subscriber 0 +#define EVENT_O_I2SSTMPSEL0 0x00000900 + +// Output Selection for FRZ Subscriber +#define EVENT_O_FRZSEL0 0x00000A00 + +// Set or Clear Software Events +#define EVENT_O_SWEV 0x00000F00 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2C_IRQ Interrupt event from I2C +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// PKA_IRQ PKA Interrupt event +#define EVENT_CPUIRQSEL3_EV_W 7 +#define EVENT_CPUIRQSEL3_EV_M 0x0000007F +#define EVENT_CPUIRQSEL3_EV_S 0 +#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV0 AUX software event 0, triggered by +// AUX_EVCTL:SWEVSET.SWEV0, also available as +// AUX_EVENT0 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL10 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL11 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL12 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// I2S_IRQ Interrupt event from I2S +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL13 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL14 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL15 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL16 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL17 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL18 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL19 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL20 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL21 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL22 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL23 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL24 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL25 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL26 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL27 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL28 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL29 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL30 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// NONE Always inactive +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL31 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL32 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL33 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL34 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// OSC_COMB Combined event from Oscillator control +#define EVENT_CPUIRQSEL34_EV_W 7 +#define EVENT_CPUIRQSEL34_EV_M 0x0000007F +#define EVENT_CPUIRQSEL34_EV_S 0 +#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL35 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +#define EVENT_CPUIRQSEL35_EV_W 7 +#define EVENT_CPUIRQSEL35_EV_M 0x0000007F +#define EVENT_CPUIRQSEL35_EV_S 0 +#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL36 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +#define EVENT_CPUIRQSEL36_EV_W 7 +#define EVENT_CPUIRQSEL36_EV_M 0x0000007F +#define EVENT_CPUIRQSEL36_EV_S 0 +#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 + +//***************************************************************************** +// +// Register: EVENT_O_CPUIRQSEL37 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// BATMON_COMB Combined event from battery monitor +#define EVENT_CPUIRQSEL37_EV_W 7 +#define EVENT_CPUIRQSEL37_EV_M 0x0000007F +#define EVENT_CPUIRQSEL37_EV_S 0 +#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL1 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL2 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL3 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL4 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL5 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL6 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL7 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL8 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 + +//***************************************************************************** +// +// Register: EVENT_O_RFCSEL9 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2S_IRQ Interrupt event from I2S +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT0BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT1BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT2BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH1BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH2BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH3BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH4BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by +// UART1:DMACTL.RXDMAE +#define EVENT_UDMACH5SSEL_EV_W 7 +#define EVENT_UDMACH5SSEL_EV_M 0x0000007F +#define EVENT_UDMACH5SSEL_EV_S 0 +#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH5BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by +// UART1:DMACTL.RXDMAE +#define EVENT_UDMACH5BSEL_EV_W 7 +#define EVENT_UDMACH5BSEL_EV_M 0x0000007F +#define EVENT_UDMACH5BSEL_EV_S 0 +#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by +// UART1:DMACTL.TXDMAE +#define EVENT_UDMACH6SSEL_EV_W 7 +#define EVENT_UDMACH6SSEL_EV_M 0x0000007F +#define EVENT_UDMACH6SSEL_EV_S 0 +#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH6BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by +// UART1:DMACTL.TXDMAE +#define EVENT_UDMACH6BSEL_EV_W 7 +#define EVENT_UDMACH6BSEL_EV_M 0x0000007F +#define EVENT_UDMACH6BSEL_EV_S 0 +#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH7BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH8BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH9BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH10BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH11BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// TIE_LOW Not used tied to 0 +// NONE Always inactive +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH12BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// NONE Always inactive +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH13BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH14BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_DMABREQ DMA burst request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_DMASREQ DMA single request event from AUX, configured by +// AUX_EVCTL:DMACTL +// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by +// AUX_EVCTL:DMASWREQ.START +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg +// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled +// by CRYPTO:IRQEN.DMA_IN_DONE +// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the +// corresponding flag is found here +// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by +// CRYPTO:IRQSTAT.RESULT_AVAIL +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// PORT_EVENT5 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT4 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT4 wil be routed here. +// PORT_EVENT3 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT3 wil be routed here. +// PORT_EVENT2 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT2 wil be routed here. +// PORT_EVENT1 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT1 wil be routed here. +// PORT_EVENT0 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT0 wil be routed here. +// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV +// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV +// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV +// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV +// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV +// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV +// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV +// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by +// UART1:DMACTL.TXDMAE +// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by +// UART1:DMACTL.TXDMAE +// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by +// UART1:DMACTL.RXDMAE +// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by +// UART1:DMACTL.RXDMAE +// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by +// UART0:DMACTL.TXDMAE +// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by +// UART0:DMACTL.RXDMAE +// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by +// UART0:DMACTL.RXDMAE +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +// DMA_DONE_COMB Combined DMA done, corresponding flags are here +// UDMA0:REQDONE +// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// PKA_IRQ PKA Interrupt event +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// AUX_SWEV1 AUX software event 1, triggered by +// AUX_EVCTL:SWEVSET.SWEV1, also available as +// AUX_EVENT2 AON wake up event. +// MCU domain wakeup control +// AON_EVENT:MCUWUSEL +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// WDT_IRQ Watchdog interrupt event, controlled by +// WDT:CTL.INTEN +// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, +// see UDMA0:SOFTREQ +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see +// UDMA0:SOFTREQ +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 +// I2C_IRQ Interrupt event from I2C +// I2S_IRQ Interrupt event from I2S +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// AON_PROG2 AON programmable event 2. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV +// AON_PROG1 AON programmable event 1. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV +// AON_PROG0 AON programmable event 0. Event selected by +// AON_EVENT MCU event selector, +// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV +// NONE Always inactive +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 +#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH15BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH16BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by +// SSI0:DMACR.RXDMAE +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH17BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by +// SSI0:DMACR.TXDMAE +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH21BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV0 Software event 0, triggered by SWEV.SWEV0 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH22BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV1 Software event 1, triggered by SWEV.SWEV1 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH23BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV2 Software event 2, triggered by SWEV.SWEV2 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24SSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_UDMACH24BSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// SWEV3 Software event 3, triggered by SWEV.SWEV3 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3ACAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_GPT3BCAPTSEL +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// AON_RTC_UPD RTC periodic event controlled by +// AON_RTC:CTL.RTC_UPD_EN +// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status +// flags are found here AUX_EVCTL:EVTOMCUFLAGS +// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 +// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL +// AUX_ADC_DONE AUX ADC done, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE +// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by +// AUX_SMPH:AUTOTAKE +// AUX_TIMER1_EV AUX timer 1 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV +// AUX_TIMER0_EV AUX timer 0 event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV +// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the +// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and +// the AUX_TDC status AUX_TDC:STAT.DONE +// AUX_COMPB AUX Compare B event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB +// AUX_COMPA AUX Compare A event, corresponds to +// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA +// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here +// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV +// PORT_EVENT7 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT7 wil be routed here. +// PORT_EVENT6 Port capture event from IOC, configured by +// IOC:IOCFGn.PORT_ID. Events on ports configured +// with ENUM PORT_EVENT6 wil be routed here. +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE +// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 +// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 +// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 +// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag +// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 +// UART1_COMB UART1 combined interrupt, interrupt flags are +// found here UART1:MIS +// UART0_COMB UART0 combined interrupt, interrupt flags are +// found here UART0:MIS +// SSI1_COMB SSI1 combined interrupt, interrupt flags are found +// here SSI1:MIS +// SSI0_COMB SSI0 combined interrupt, interrupt flags are found +// here SSI0:MIS +// RFC_CPE_1 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_1 event +// RFC_CPE_0 Combined Interrupt for CPE Generated events. +// Corresponding flags are here +// RFC_DBELL:RFCPEIFG. Only interrupts selected +// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a +// RFC_CPE_0 event +// RFC_HW_COMB Combined RFC hardware interrupt, corresponding +// flag is here RFC_DBELL:RFHWIFG +// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, +// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG +// FLASH FLASH controller error event, the status flags +// are FLASH:FEDACSTAT.FSM_DONE and +// FLASH:FEDACSTAT.RVF_INT +// AUX_COMB AUX combined event, the corresponding flag +// register is here AUX_EVCTL:EVTOMCUFLAGS +// I2C_IRQ Interrupt event from I2C +// AON_RTC_COMB Event from AON_RTC, controlled by the +// AON_RTC:CTL.COMB_EV_MASK setting +// OSC_COMB Combined event from Oscillator control +// BATMON_COMB Combined event from battery monitor +// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the +// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET +// settings +// NONE Always inactive +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_AUXSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT +// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT +// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT +// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT +// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT +// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT +// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT +// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT +// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR +// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR +// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR +// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR +// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR +// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR +// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR +// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR +// NONE Always inactive +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 +#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 +#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 +#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 +#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 +#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F +#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E +#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_CM3NMISEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read only selection value +// ENUMs: +// WDT_NMI Watchdog non maskable interrupt event, controlled +// by WDT:CTL.INTTYPE +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 + +//***************************************************************************** +// +// Register: EVENT_O_I2SSTMPSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// NONE Always inactive +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_FRZSEL0 +// +//***************************************************************************** +// Field: [6:0] EV +// +// Read/write selection value +// +// Writing any other value than values defined by a ENUM may result in +// undefined behavior. +// ENUMs: +// ALWAYS_ACTIVE Always asserted +// CPU_HALTED CPU halted +// NONE Always inactive +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 + +//***************************************************************************** +// +// Register: EVENT_O_SWEV +// +//***************************************************************************** +// Field: [24] SWEV3 +// +// Writing "1" to this bit when the value is "0" triggers the Software 3 event. +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 + +// Field: [16] SWEV2 +// +// Writing "1" to this bit when the value is "0" triggers the Software 2 event. +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 + +// Field: [8] SWEV1 +// +// Writing "1" to this bit when the value is "0" triggers the Software 1 event. +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 + +// Field: [0] SWEV0 +// +// Writing "1" to this bit when the value is "0" triggers the Software 0 event. +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 + + +#endif // __EVENT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg1.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg1.h new file mode 100644 index 00000000..5e1f436e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg1.h @@ -0,0 +1,2872 @@ +/****************************************************************************** +* Filename: hw_fcfg1_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG1_H__ +#define __HW_FCFG1_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG1 component +// +//***************************************************************************** +// Misc configurations +#define FCFG1_O_MISC_CONF_1 0x000000A0 + +// Internal +#define FCFG1_O_MISC_CONF_2 0x000000A4 + +// Internal +#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 + +// Internal +#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 + +// Internal +#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 + +// Internal +#define FCFG1_O_HPOSC_MEAS_2 0x000000BC + +// Internal +#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 + +// Internal +#define FCFG1_O_CONFIG_CC26_FE 0x000000C4 + +// Internal +#define FCFG1_O_CONFIG_CC13_FE 0x000000C8 + +// Internal +#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 + +// Internal +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 + +// Flash information +#define FCFG1_O_FLASH_NUMBER 0x00000164 + +// Flash information +#define FCFG1_O_FLASH_COORDINATE 0x0000016C + +// Internal +#define FCFG1_O_FLASH_E_P 0x00000170 + +// Internal +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +// Internal +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +// Internal +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +// Internal +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +// Internal +#define FCFG1_O_FLASH_PP 0x00000184 + +// Internal +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +// Internal +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +// Internal +#define FCFG1_O_FLASH_VHV 0x00000190 + +// Internal +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +// Internal +#define FCFG1_O_FLASH_V 0x00000198 + +// User Identification. +#define FCFG1_O_USER_ID 0x00000294 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +// Internal +#define FCFG1_O_ANA2_TRIM 0x000002B4 + +// Internal +#define FCFG1_O_LDO_TRIM 0x000002B8 + +// MAC BLE Address 0 +#define FCFG1_O_MAC_BLE_0 0x000002E8 + +// MAC BLE Address 1 +#define FCFG1_O_MAC_BLE_1 0x000002EC + +// MAC IEEE 802.15.4 Address 0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 + +// MAC IEEE 802.15.4 Address 1 +#define FCFG1_O_MAC_15_4_1 0x000002F4 + +// Internal +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +// Miscellaneous Trim Parameters +#define FCFG1_O_MISC_TRIM 0x0000030C + +// Internal +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 + +// IcePick Device Identification +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 + +// Factory Configuration (FCFG1) Revision +#define FCFG1_O_FCFG1_REVISION 0x0000031C + +// Misc OTP Data +#define FCFG1_O_MISC_OTP_DATA 0x00000320 + +// IO Configuration +#define FCFG1_O_IOCONF 0x00000344 + +// Internal +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C + +// Internal +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 + +// AUX_ADC Gain in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C + +// AUX_ADC Gain in Relative Reference Mode +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 + +// AUX_ADC Temperature Offsets in Absolute Reference Mode +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 + +// Internal +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C + +// Internal +#define FCFG1_O_AMPCOMP_TH1 0x00000370 + +// Internal +#define FCFG1_O_AMPCOMP_TH2 0x00000374 + +// Internal +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 + +// Internal +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C + +// Internal +#define FCFG1_O_VOLT_TRIM 0x00000388 + +// OSC Configuration +#define FCFG1_O_OSC_CONF 0x0000038C + +// Internal +#define FCFG1_O_FREQ_OFFSET 0x00000390 + +// Internal +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 + +// Shadow of EFUSE:DIE_ID_0 register +#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 + +// Shadow of EFUSE:DIE_ID_1 register +#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 + +// Shadow of EFUSE:DIE_ID_2 register +#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 + +// Shadow of EFUSE:DIE_ID_3 register +#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC + +// Internal +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 + +// Internal +#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC + +// Internal +#define FCFG1_O_DAC_BIAS_CNF 0x0000040C + +// Internal +#define FCFG1_O_TFW_PROBE 0x00000418 + +// Internal +#define FCFG1_O_TFW_FT 0x0000041C + +// Internal +#define FCFG1_O_DAC_CAL0 0x00000420 + +// Internal +#define FCFG1_O_DAC_CAL1 0x00000424 + +// Internal +#define FCFG1_O_DAC_CAL2 0x00000428 + +// Internal +#define FCFG1_O_DAC_CAL3 0x0000042C + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_1 +// +//***************************************************************************** +// Field: [7:0] DEVICE_MINOR_REV +// +// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). +// Any test of this field by SW should be implemented as a 'greater or equal' +// comparison as signed integer. +// Value may change without warning. +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_CONF_2 +// +//***************************************************************************** +// Field: [7:0] HPOSC_COMP_P3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_5 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 + +// Field: [15:8] HPOSC_T5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 + +// Field: [7:0] HPOSC_DT5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_4 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 + +// Field: [15:8] HPOSC_T4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 + +// Field: [7:0] HPOSC_DT4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_3 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 + +// Field: [15:8] HPOSC_T3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 + +// Field: [7:0] HPOSC_DT3 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_2 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 + +// Field: [15:8] HPOSC_T2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 + +// Field: [7:0] HPOSC_DT2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_HPOSC_MEAS_1 +// +//***************************************************************************** +// Field: [31:16] HPOSC_D1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 + +// Field: [15:8] HPOSC_T1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 + +// Field: [7:0] HPOSC_DT1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_CC26_FE +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 + +// Field: [12] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 + +// Field: [7:0] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_CC13_FE +// +//***************************************************************************** +// Field: [31:28] IFAMP_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 + +// Field: [27:24] LNA_IB +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 + +// Field: [23:19] IFAMP_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 + +// Field: [18:14] CTL_PA0_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 + +// Field: [13] PATRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 + +// Field: [12] RSSITRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 + +// Field: [7:0] RSSI_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_RF_COMMON +// +//***************************************************************************** +// Field: [31] DISABLE_CORNER_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 + +// Field: [30:25] SLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 + +// Field: [21] PA20DBMTRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 + +// Field: [20:16] CTL_PA_20DBM_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 + +// Field: [15:9] RFLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 + +// Field: [8:6] QUANTCTLTHRES +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 + +// Field: [5:0] DACTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV5 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV10 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV15 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_SYNTH_DIV30 +// +//***************************************************************************** +// Field: [31:28] MIN_ALLOWED_RTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 + +// Field: [27:12] RFC_MDM_DEMIQMC0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 + +// Field: [11:6] LDOVCO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 + +// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ + 5 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ + 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ + 5 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_NUMBER +// +//***************************************************************************** +// Field: [31:0] LOT_NUMBER +// +// Number of the manufacturing lot that produced this unit. +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_COORDINATE +// +//***************************************************************************** +// Field: [31:16] XCOORDINATE +// +// X coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 + +// Field: [15:0] YCOORDINATE +// +// Y coordinate of this unit on the wafer. +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_E_P +// +//***************************************************************************** +// Field: [31:24] PSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +// Field: [23:16] ESU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +// Field: [15:8] PVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +// Field: [7:0] EVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_C_E_P_R +// +//***************************************************************************** +// Field: [31:24] RVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +// Field: [23:16] PV_ACCESS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +// Field: [15:12] A_EXEZ_SETUP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +// Field: [11:0] CVSU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_P_R_PV +// +//***************************************************************************** +// Field: [31:24] PH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +// Field: [23:16] RH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +// Field: [15:8] PVH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +// Field: [7:0] PVH2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_EH_SEQ +// +//***************************************************************************** +// Field: [31:24] EH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +// Field: [23:16] SEQ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 + +// Field: [15:12] VSTAT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +// Field: [11:0] SM_FREQUENCY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_E +// +//***************************************************************************** +// Field: [31:16] VHV_E_START +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +// Field: [15:0] VHV_E_STEP_HIGHT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PP +// +//***************************************************************************** +// Field: [31:24] PUMP_SU +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 + +// Field: [23:16] TRIM3P4 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_TRIM3P4_W 8 +#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 +#define FCFG1_FLASH_PP_TRIM3P4_S 16 + +// Field: [15:0] MAX_PP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_PROG_EP +// +//***************************************************************************** +// Field: [31:16] MAX_EP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +// Field: [15:0] PROGRAM_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_ERA_PW +// +//***************************************************************************** +// Field: [31:0] ERASE_PW +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV +// +//***************************************************************************** +// Field: [27:24] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +// Field: [19:16] VHV_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +// Field: [11:8] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +// Field: [3:0] VHV_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_VHV_PV +// +//***************************************************************************** +// Field: [27:24] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +// Field: [19:16] VHV_PV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +// Field: [15:8] VCG2P5 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +// Field: [7:0] VINH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_V +// +//***************************************************************************** +// Field: [31:24] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +// Field: [23:16] VWL_P +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +// Field: [15:8] V_READ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +// Field: [7:0] TRIM0P8 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_V_TRIM0P8_W 8 +#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF +#define FCFG1_FLASH_V_TRIM0P8_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_USER_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 + +// Field: [27:26] VER +// +// Version number. +// +// 0x0: Bits [25:12] of this register has the stated meaning. +// +// Any other setting indicate a different encoding of these bits. +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 + +// Field: [25] PA +// +// 0: Does not support 20dBm PA +// 1: Supports 20dBM PA +#define FCFG1_USER_ID_PA 0x02000000 +#define FCFG1_USER_ID_PA_BITN 25 +#define FCFG1_USER_ID_PA_M 0x02000000 +#define FCFG1_USER_ID_PA_S 25 + +// Field: [23] CC13 +// +// 0: CC26xx device type +// 1: CC13xx device type +#define FCFG1_USER_ID_CC13 0x00800000 +#define FCFG1_USER_ID_CC13_BITN 23 +#define FCFG1_USER_ID_CC13_M 0x00800000 +#define FCFG1_USER_ID_CC13_S 23 + +// Field: [22:19] SEQUENCE +// +// Sequence. +// +// Used to differentiate between marketing/orderable product where other fields +// of this register are the same (temp range, flash size, voltage range etc) +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 + +// Field: [18:16] PKG +// +// Package type. +// +// 0x0: 4x4mm QFN (RHB) package +// 0x1: 5x5mm QFN (RSM) package +// 0x2: 7x7mm QFN (RGZ) package +// 0x3: Wafer sale package (naked die) +// 0x4: WCSP (YFV) +// 0x5: 7x7mm QFN package with Wettable Flanks +// +// Other values are reserved for future use. +// Packages available for a specific device are shown in the device datasheet. +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 + +// Field: [15:12] PROTOCOL +// +// Protocols supported. +// +// 0x1: BLE +// 0x2: RF4CE +// 0x4: Zigbee/6lowpan +// 0x8: Proprietary +// +// More than one protocol can be supported on same device - values above are +// then combined. +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA3 +// +//***************************************************************************** +// Field: [31:23] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +// Field: [22] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +// Field: [21:18] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +// Field: [17:16] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +// Field: [15:8] FLASH_SIZE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 + +// Field: [7:0] WAIT_SYSCODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANA2_TRIM +// +//***************************************************************************** +// Field: [31] RCOSCHFCTRIMFRACT_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 + +// Field: [30:26] RCOSCHFCTRIMFRACT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 + +// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 + +// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 + +// Field: [21:15] NANOAMP_RES_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 + +// Field: [11] DITHER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 + +// Field: [10:8] DCDC_IPEAK +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 + +// Field: [7:6] DEAD_TIME_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 + +// Field: [5:3] DCDC_LOW_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 + +// Field: [2:0] DCDC_HIGH_EN_SEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_LDO_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_SLEEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 + +// Field: [18:16] GLDO_CURSRC +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 + +// Field: [12:11] ITRIM_DIGLDO_LOAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 + +// Field: [10:8] ITRIM_UDIGLDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 + +// Field: [2:0] VTRIM_DELTA +// +// Internal. Only to be used through TI provided API. +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_BLE_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC BLE address +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_0 +// +//***************************************************************************** +// Field: [31:0] ADDR_0_31 +// +// The first 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MAC_15_4_1 +// +//***************************************************************************** +// Field: [31:0] ADDR_32_63 +// +// The last 32-bits of the 64-bit MAC 15.4 address +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FLASH_OTP_DATA4 +// +//***************************************************************************** +// Field: [31] STANDBY_MODE_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +// Field: [30:29] STANDBY_PW_SEL_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +// Field: [28] DIS_STANDBY_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 + +// Field: [26:24] VIN_AT_X_INT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +// Field: [23] STANDBY_MODE_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +// Field: [22:21] STANDBY_PW_SEL_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +// Field: [20] DIS_STANDBY_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 + +// Field: [18:16] VIN_AT_X_EXT_WRT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +// Field: [15] STANDBY_MODE_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +// Field: [14:13] STANDBY_PW_SEL_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +// Field: [12] DIS_STANDBY_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 + +// Field: [10:8] VIN_AT_X_INT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +// Field: [7] STANDBY_MODE_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +// Field: [6:5] STANDBY_PW_SEL_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +// Field: [4] DIS_STANDBY_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 + +// Field: [2:0] VIN_AT_X_EXT_RD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_TRIM +// +//***************************************************************************** +// Field: [16:12] TRIM_RECHARGE_COMP_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 + +// Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 + +// Field: [7:0] TEMPVSLOPE +// +// Signed byte value representing the TEMP slope with battery voltage, in +// degrees C / V, with four fractional bits. +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_RCOSC_HF_TEMPCOMP +// +//***************************************************************************** +// Field: [31:24] FINE_RESISTOR +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 + +// Field: [23:16] CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 + +// Field: [15:8] CTRIMFRACT_QUAD +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 + +// Field: [7:0] CTRIMFRACT_SLOPE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ICEPICK_DEVICE_ID +// +//***************************************************************************** +// Field: [31:28] PG_REV +// +// Field used to distinguish revisions of the device. +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 + +// Field: [27:12] WAFER_ID +// +// Field used to identify silicon die. +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 + +// Field: [11:0] MANUFACTURER_ID +// +// Manufacturer code. +// +// 0x02F: Texas Instruments +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FCFG1_REVISION +// +//***************************************************************************** +// Field: [31:0] REV +// +// The revision number of the FCFG1 layout. This value will be read by +// application SW in order to determine which FCFG1 parameters that have valid +// values. This revision number must be incremented by 1 before any devices are +// to be produced if the FCFG1 layout has changed since the previous production +// of devices. +// Value migth change without warning. +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA +// +//***************************************************************************** +// Field: [31:28] RCOSC_HF_ITUNE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 + +// Field: [27:20] RCOSC_HF_CRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 + +// Field: [19:15] PER_M +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 + +// Field: [14:12] PER_E +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 + +//***************************************************************************** +// +// Register: FCFG1_O_IOCONF +// +//***************************************************************************** +// Field: [6:0] GPIO_CNT +// +// Number of available DIOs. +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_IF_ADC +// +//***************************************************************************** +// Field: [31:28] FF2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 + +// Field: [27:24] FF3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 + +// Field: [23:20] INT3ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 + +// Field: [19:16] FF1ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 + +// Field: [15:14] AAFCAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 + +// Field: [13:10] INT2ADJ +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 + +// Field: [9:5] IFDIGLDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 + +// Field: [4:0] IFANALDO_TRIM_OUTPUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_CONFIG_OSC_TOP +// +//***************************************************************************** +// Field: [29:26] XOSC_HF_ROW_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 + +// Field: [25:10] XOSC_HF_COLUMN_Q12 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 + +// Field: [9:2] RCOSCLF_CTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 + +// Field: [1:0] RCOSCLF_RTUNE_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_ABS_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 +// +// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REL_GAIN +// +//***************************************************************************** +// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 +// +// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated +// in production test.. +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_OFFSET_INT +// +//***************************************************************************** +// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 +// +// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 + +// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 +// +// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed +// 8-bit number. Calculated in production test.. +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT +// +//***************************************************************************** +// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ + 6 +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ + 0x0000003F +#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ + 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH1 +// +//***************************************************************************** +// Field: [23:18] HPMRAMP3_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 + +// Field: [15:10] HPMRAMP3_HTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 + +// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 + +// Field: [5:0] HPMRAMP1_TH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_TH2 +// +//***************************************************************************** +// Field: [31:26] LPMUPDATE_LTH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 + +// Field: [23:18] LPMUPDATE_HTM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 + +// Field: [15:10] ADC_COMP_AMPTH_LPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 + +// Field: [7:2] ADC_COMP_AMPTH_HPM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 + +//***************************************************************************** +// +// Register: FCFG1_O_AMPCOMP_CTRL1 +// +//***************************************************************************** +// Field: [30] AMPCOMP_REQ_MODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 + +// Field: [23:20] IBIAS_OFFSET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 + +// Field: [19:16] IBIAS_INIT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 + +// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 + +// Field: [7:4] CAP_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 + +// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_ANABYPASS_VALUE2 +// +//***************************************************************************** +// Field: [13:0] XOSC_HF_IBIASTHERM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_VOLT_TRIM +// +//***************************************************************************** +// Field: [28:24] VDDR_TRIM_HH +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 + +// Field: [20:16] VDDR_TRIM_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 + +// Field: [12:8] VDDR_TRIM_SLEEP_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 + +// Field: [4:0] TRIMBOD_H +// +// Internal. Only to be used through TI provided API. +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_OSC_CONF +// +//***************************************************************************** +// Field: [29] ADC_SH_VBUF_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 + +// Field: [28] ADC_SH_MODE_EN +// +// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 + +// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM +// +// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 + +// Field: [26:25] XOSCLF_REGULATOR_TRIM +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 + +// Field: [24:21] XOSCLF_CMIRRWR_RATIO +// +// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 + +// Field: [20:19] XOSC_HF_FAST_START +// +// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 + +// Field: [18] XOSC_OPTION +// +// 0: XOSC_HF unavailable (may not be bonded out) +// 1: XOSC_HF available (default) +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 + +// Field: [17] HPOSC_OPTION +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 + +// Field: [16] HPOSC_BIAS_HOLD_MODE_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 + +// Field: [15:12] HPOSC_CURRMIRR_RATIO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 + +// Field: [11:8] HPOSC_BIAS_RES_SET +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 + +// Field: [7] HPOSC_FILTER_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 + +// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 + +// Field: [2:1] HPOSC_SERIES_CAP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 + +// Field: [0] HPOSC_DIV3_BYPASS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_FREQ_OFFSET +// +//***************************************************************************** +// Field: [31:16] HPOSC_COMP_P0 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 + +// Field: [15:8] HPOSC_COMP_P1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 + +// Field: [7:0] HPOSC_COMP_P2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_MISC_OTP_DATA_1 +// +//***************************************************************************** +// Field: [28:27] PEAK_DET_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 + +// Field: [26:24] HP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 + +// Field: [23:22] LP_BUF_ITRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 + +// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 + +// Field: [19:10] HPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 + +// Field: [9:4] LPM_IBIAS_WAIT_CNT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 + +// Field: [3:0] IDAC_STEP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_0 +// +//***************************************************************************** +// Field: [31:0] ID_31_0 +// +// Shadow of DIE_ID_0 register in eFuse row number 5 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_1 +// +//***************************************************************************** +// Field: [31:0] ID_63_32 +// +// Shadow of DIE_ID_1 register in eFuse row number 6 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_2 +// +//***************************************************************************** +// Field: [31:0] ID_95_64 +// +// Shadow of DIE_ID_2 register in eFuse row number 7 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_DIE_ID_3 +// +//***************************************************************************** +// Field: [31:0] ID_127_96 +// +// Shadow of DIE_ID_3 register in eFuse row number 8 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM +// +//***************************************************************************** +// Field: [26:23] TRIMMAG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 + +// Field: [22:18] TRIMIREF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 + +// Field: [17:16] ITRIM_DIG_LDO +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 + +// Field: [15:12] VTRIM_DIG +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 + +// Field: [11:8] VTRIM_COARSE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 + +// Field: [7:0] RCOSCHF_CTRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_SHDW_ANA_TRIM +// +//***************************************************************************** +// Field: [30] ALT_VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 + +// Field: [29] DET_LOGIC_DIS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 + +// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 + +// Field: [26:25] BOD_BANDGAP_TRIM_CNF +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 + +// Field: [24] VDDR_ENABLE_PG1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 + +// Field: [23] VDDR_OK_HYS +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 + +// Field: [22:21] IPTAT_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 + +// Field: [20:16] VDDR_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 + +// Field: [15:11] TRIMBOD_INTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 + +// Field: [10:6] TRIMBOD_EXTMODE +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 + +// Field: [5:0] TRIMTEMP +// +// Internal. Only to be used through TI provided API. +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_BIAS_CNF +// +//***************************************************************************** +// Field: [17:12] LPM_TRIM_IOUT +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 + +// Field: [11:9] LPM_BIAS_WIDTH_TRIM +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 + +// Field: [8] LPM_BIAS_BACKUP_EN +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 + +//***************************************************************************** +// +// Register: FCFG1_O_TFW_PROBE +// +//***************************************************************************** +// Field: [31:0] REV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TFW_PROBE_REV_W 32 +#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF +#define FCFG1_TFW_PROBE_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_TFW_FT +// +//***************************************************************************** +// Field: [31:0] REV +// +// Internal. Only to be used through TI provided API. +#define FCFG1_TFW_FT_REV_W 32 +#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF +#define FCFG1_TFW_FT_REV_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL0 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL1 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL2 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 + +//***************************************************************************** +// +// Register: FCFG1_O_DAC_CAL3 +// +//***************************************************************************** +// Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 + +// Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 +// +// Internal. Only to be used through TI provided API. +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 + + +#endif // __FCFG1__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg2.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg2.h new file mode 100644 index 00000000..bae31bf3 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_fcfg2.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: hw_fcfg2_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FCFG2_H__ +#define __HW_FCFG2_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FCFG2 component +// +//***************************************************************************** + +#endif // __FCFG2__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_flash.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_flash.h new file mode 100644 index 00000000..51ee5939 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_flash.h @@ -0,0 +1,3770 @@ +/****************************************************************************** +* Filename: hw_flash_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_FLASH_H__ +#define __HW_FLASH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// FLASH component +// +//***************************************************************************** +// FMC and Efuse Status +#define FLASH_O_STAT 0x0000001C + +// Internal +#define FLASH_O_CFG 0x00000024 + +// Internal +#define FLASH_O_FLASH_SIZE 0x0000002C + +// Internal +#define FLASH_O_FWLOCK 0x0000003C + +// Internal +#define FLASH_O_FWFLAG 0x00000040 + +// Internal +#define FLASH_O_EFUSE 0x00001000 + +// Internal +#define FLASH_O_EFUSEADDR 0x00001004 + +// Internal +#define FLASH_O_DATAUPPER 0x00001008 + +// Internal +#define FLASH_O_DATALOWER 0x0000100C + +// Internal +#define FLASH_O_EFUSECFG 0x00001010 + +// Internal +#define FLASH_O_EFUSESTAT 0x00001014 + +// Internal +#define FLASH_O_ACC 0x00001018 + +// Internal +#define FLASH_O_BOUNDARY 0x0000101C + +// Internal +#define FLASH_O_EFUSEFLAG 0x00001020 + +// Internal +#define FLASH_O_EFUSEKEY 0x00001024 + +// Internal +#define FLASH_O_EFUSERELEASE 0x00001028 + +// Internal +#define FLASH_O_EFUSEPINS 0x0000102C + +// Internal +#define FLASH_O_EFUSECRA 0x00001030 + +// Internal +#define FLASH_O_EFUSEREAD 0x00001034 + +// Internal +#define FLASH_O_EFUSEPROGRAM 0x00001038 + +// Internal +#define FLASH_O_EFUSEERROR 0x0000103C + +// Internal +#define FLASH_O_SINGLEBIT 0x00001040 + +// Internal +#define FLASH_O_TWOBIT 0x00001044 + +// Internal +#define FLASH_O_SELFTESTCYC 0x00001048 + +// Internal +#define FLASH_O_SELFTESTSIGN 0x0000104C + +// Internal +#define FLASH_O_FRDCTL 0x00002000 + +// Internal +#define FLASH_O_FSPRD 0x00002004 + +// Internal +#define FLASH_O_FEDACCTL1 0x00002008 + +// Internal +#define FLASH_O_FEDACSTAT 0x0000201C + +// Internal +#define FLASH_O_FBPROT 0x00002030 + +// Internal +#define FLASH_O_FBSE 0x00002034 + +// Internal +#define FLASH_O_FBBUSY 0x00002038 + +// Internal +#define FLASH_O_FBAC 0x0000203C + +// Internal +#define FLASH_O_FBFALLBACK 0x00002040 + +// Internal +#define FLASH_O_FBPRDY 0x00002044 + +// Internal +#define FLASH_O_FPAC1 0x00002048 + +// Internal +#define FLASH_O_FPAC2 0x0000204C + +// Internal +#define FLASH_O_FMAC 0x00002050 + +// Internal +#define FLASH_O_FMSTAT 0x00002054 + +// Internal +#define FLASH_O_FLOCK 0x00002064 + +// Internal +#define FLASH_O_FVREADCT 0x00002080 + +// Internal +#define FLASH_O_FVHVCT1 0x00002084 + +// Internal +#define FLASH_O_FVHVCT2 0x00002088 + +// Internal +#define FLASH_O_FVHVCT3 0x0000208C + +// Internal +#define FLASH_O_FVNVCT 0x00002090 + +// Internal +#define FLASH_O_FVSLP 0x00002094 + +// Internal +#define FLASH_O_FVWLCT 0x00002098 + +// Internal +#define FLASH_O_FEFUSECTL 0x0000209C + +// Internal +#define FLASH_O_FEFUSESTAT 0x000020A0 + +// Internal +#define FLASH_O_FEFUSEDATA 0x000020A4 + +// Internal +#define FLASH_O_FSEQPMP 0x000020A8 + +// Internal +#define FLASH_O_FBSTROBES 0x00002100 + +// Internal +#define FLASH_O_FPSTROBES 0x00002104 + +// Internal +#define FLASH_O_FBMODE 0x00002108 + +// Internal +#define FLASH_O_FTCR 0x0000210C + +// Internal +#define FLASH_O_FADDR 0x00002110 + +// Internal +#define FLASH_O_FTCTL 0x0000211C + +// Internal +#define FLASH_O_FWPWRITE0 0x00002120 + +// Internal +#define FLASH_O_FWPWRITE1 0x00002124 + +// Internal +#define FLASH_O_FWPWRITE2 0x00002128 + +// Internal +#define FLASH_O_FWPWRITE3 0x0000212C + +// Internal +#define FLASH_O_FWPWRITE4 0x00002130 + +// Internal +#define FLASH_O_FWPWRITE5 0x00002134 + +// Internal +#define FLASH_O_FWPWRITE6 0x00002138 + +// Internal +#define FLASH_O_FWPWRITE7 0x0000213C + +// Internal +#define FLASH_O_FWPWRITE_ECC 0x00002140 + +// Internal +#define FLASH_O_FSWSTAT 0x00002144 + +// Internal +#define FLASH_O_FSM_GLBCTL 0x00002200 + +// Internal +#define FLASH_O_FSM_STATE 0x00002204 + +// Internal +#define FLASH_O_FSM_STAT 0x00002208 + +// Internal +#define FLASH_O_FSM_CMD 0x0000220C + +// Internal +#define FLASH_O_FSM_PE_OSU 0x00002210 + +// Internal +#define FLASH_O_FSM_VSTAT 0x00002214 + +// Internal +#define FLASH_O_FSM_PE_VSU 0x00002218 + +// Internal +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +// Internal +#define FLASH_O_FSM_EX_VAL 0x00002220 + +// Internal +#define FLASH_O_FSM_RD_H 0x00002224 + +// Internal +#define FLASH_O_FSM_P_OH 0x00002228 + +// Internal +#define FLASH_O_FSM_ERA_OH 0x0000222C + +// Internal +#define FLASH_O_FSM_SAV_PPUL 0x00002230 + +// Internal +#define FLASH_O_FSM_PE_VH 0x00002234 + +// Internal +#define FLASH_O_FSM_PRG_PW 0x00002240 + +// Internal +#define FLASH_O_FSM_ERA_PW 0x00002244 + +// Internal +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 + +// Internal +#define FLASH_O_FSM_TIMER 0x00002258 + +// Internal +#define FLASH_O_FSM_MODE 0x0000225C + +// Internal +#define FLASH_O_FSM_PGM 0x00002260 + +// Internal +#define FLASH_O_FSM_ERA 0x00002264 + +// Internal +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +// Internal +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +// Internal +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +// Internal +#define FLASH_O_FSM_PUL_CNTR 0x00002274 + +// Internal +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +// Internal +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +// Internal +#define FLASH_O_FSM_FLES 0x00002280 + +// Internal +#define FLASH_O_FSM_WR_ENA 0x00002288 + +// Internal +#define FLASH_O_FSM_ACC_PP 0x0000228C + +// Internal +#define FLASH_O_FSM_ACC_EP 0x00002290 + +// Internal +#define FLASH_O_FSM_ADDR 0x000022A0 + +// Internal +#define FLASH_O_FSM_SECTOR 0x000022A4 + +// Internal +#define FLASH_O_FMC_REV_ID 0x000022A8 + +// Internal +#define FLASH_O_FSM_ERR_ADDR 0x000022AC + +// Internal +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 + +// Internal +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +// Internal +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +// Internal +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +// Internal +#define FLASH_O_FSM_BSLE0 0x000022E0 + +// Internal +#define FLASH_O_FSM_BSLE1 0x000022E4 + +// Internal +#define FLASH_O_FSM_BSLP0 0x000022F0 + +// Internal +#define FLASH_O_FSM_BSLP1 0x000022F4 + +// FMC FSM Enable 128-bit Wide Programming +#define FLASH_O_FSM_PGM128 0x000022F8 + +// FMC FSM Enable Parallell Reads for Multibanks +#define FLASH_O_FSM_EN_PRL_BNK_RD 0x000022FC + +// Internal +#define FLASH_O_FCFG_BANK 0x00002400 + +// Internal +#define FLASH_O_FCFG_WRAPPER 0x00002404 + +// Internal +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 + +// Internal +#define FLASH_O_FCFG_B0_START 0x00002410 + +// Internal +#define FLASH_O_FCFG_B1_START 0x00002414 + +// Internal +#define FLASH_O_FCFG_B2_START 0x00002418 + +// Internal +#define FLASH_O_FCFG_B3_START 0x0000241C + +// Internal +#define FLASH_O_FCFG_B4_START 0x00002420 + +// Internal +#define FLASH_O_FCFG_B5_START 0x00002424 + +// Internal +#define FLASH_O_FCFG_B6_START 0x00002428 + +// Internal +#define FLASH_O_FCFG_B7_START 0x0000242C + +// Internal +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +// Internal +#define FLASH_O_FCFG_B0_SSIZE1 0x00002434 + +// Internal +#define FLASH_O_FCFG_B0_SSIZE2 0x00002438 + +// Internal +#define FLASH_O_FCFG_B0_SSIZE3 0x0000243C + +// Internal +#define FLASH_O_FCFG_B1_SSIZE0 0x00002440 + +// Internal +#define FLASH_O_FCFG_B1_SSIZE1 0x00002444 + +// Internal +#define FLASH_O_FCFG_B1_SSIZE2 0x00002448 + +// Internal +#define FLASH_O_FCFG_B1_SSIZE3 0x0000244C + +// Internal +#define FLASH_O_FCFG_B2_SSIZE0 0x00002450 + +// Internal +#define FLASH_O_FCFG_B2_SSIZE1 0x00002454 + +// Internal +#define FLASH_O_FCFG_B2_SSIZE2 0x00002458 + +// Internal +#define FLASH_O_FCFG_B2_SSIZE3 0x0000245C + +// Internal +#define FLASH_O_FCFG_B3_SSIZE0 0x00002460 + +// Internal +#define FLASH_O_FCFG_B3_SSIZE1 0x00002464 + +// Internal +#define FLASH_O_FCFG_B3_SSIZE2 0x00002468 + +// Internal +#define FLASH_O_FCFG_B3_SSIZE3 0x0000246C + +// Internal +#define FLASH_O_FCFG_B4_SSIZE0 0x00002470 + +// Internal +#define FLASH_O_FCFG_B4_SSIZE1 0x00002474 + +// Internal +#define FLASH_O_FCFG_B4_SSIZE2 0x00002478 + +// Internal +#define FLASH_O_FCFG_B4_SSIZE3 0x0000247C + +// Internal +#define FLASH_O_FCFG_B5_SSIZE0 0x00002480 + +// Internal +#define FLASH_O_FCFG_B5_SSIZE1 0x00002484 + +// Internal +#define FLASH_O_FCFG_B5_SSIZE2 0x00002488 + +// Internal +#define FLASH_O_FCFG_B5_SSIZE3 0x0000248C + +// Internal +#define FLASH_O_FCFG_B6_SSIZE0 0x00002490 + +// Internal +#define FLASH_O_FCFG_B6_SSIZE1 0x00002494 + +// Internal +#define FLASH_O_FCFG_B6_SSIZE2 0x00002498 + +// Internal +#define FLASH_O_FCFG_B6_SSIZE3 0x0000249C + +// Internal +#define FLASH_O_FCFG_B7_SSIZE0 0x000024A0 + +// Internal +#define FLASH_O_FCFG_B7_SSIZE1 0x000024A4 + +// Internal +#define FLASH_O_FCFG_B7_SSIZE2 0x000024A8 + +// Internal +#define FLASH_O_FCFG_B7_SSIZE3 0x000024AC + +//***************************************************************************** +// +// Register: FLASH_O_STAT +// +//***************************************************************************** +// Field: [15] EFUSE_BLANK +// +// Efuse scanning detected if fuse ROM is blank: +// 0 : Not blank +// 1 : Blank +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 + +// Field: [14] EFUSE_TIMEOUT +// +// Efuse scanning resulted in timeout error. +// 0 : No Timeout error +// 1 : Timeout Error +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 + +// Field: [13] SPRS_BYTE_NOT_OK +// +// Efuse scanning resulted in scan chain Sparse byte error. +// 0 : No Sparse error +// 1 : Sparse Error +#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13 + +// Field: [12:8] EFUSE_ERRCODE +// +// Same as EFUSEERROR.CODE +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 + +// Field: [5:4] BUSY +// +// Fast version of the FMC FMSTAT.BUSY bit. +// This flag is valid immediately after the operation setting it (FMSTAT.BUSY +// is delayed some cycles) +// 0 : Not busy +// 1 : Busy +// +// Bit 4 is for the busy state for Bank0 which is at logical address 0x0 +// Bit 5 for Bank1. +#define FLASH_STAT_BUSY_W 2 +#define FLASH_STAT_BUSY_M 0x00000030 +#define FLASH_STAT_BUSY_S 4 + +// Field: [1:0] POWER_MODE +// +// Power state of each of the 2 flash bank instances in the flash sub-system. +// 0 : Active +// 1 : Low power +// +// Bit 0 is for the power state for Bank0 which is at logical address 0x0 +// Bit 1 for Bank1 +#define FLASH_STAT_POWER_MODE_W 2 +#define FLASH_STAT_POWER_MODE_M 0x00000003 +#define FLASH_STAT_POWER_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_CFG +// +//***************************************************************************** +// Field: [9] FORCE_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_FORCE_STANDBY 0x00000200 +#define FLASH_CFG_FORCE_STANDBY_BITN 9 +#define FLASH_CFG_FORCE_STANDBY_M 0x00000200 +#define FLASH_CFG_FORCE_STANDBY_S 9 + +// Field: [8] STANDBY_MODE_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +// Field: [7:6] STANDBY_PW_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +// Field: [5] DIS_EFUSECLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 + +// Field: [4] DIS_READACCESS +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 + +// Field: [3] ENABLE_SWINTF +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 + +// Field: [1] DIS_STANDBY +// +// Internal. Only to be used through TI provided API. +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FLASH_SIZE +// +//***************************************************************************** +// Field: [7:0] SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWLOCK +// +//***************************************************************************** +// Field: [2:0] FWLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWFLAG +// +//***************************************************************************** +// Field: [2:0] FWFLAG +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSE +// +//***************************************************************************** +// Field: [28:24] INSTRUCTION +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 + +// Field: [15:0] DUMPWORD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEADDR +// +//***************************************************************************** +// Field: [15:11] BLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 + +// Field: [10:0] ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATAUPPER +// +//***************************************************************************** +// Field: [7:3] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 + +// Field: [2] P +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 + +// Field: [1] R +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 + +// Field: [0] EEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_DATALOWER +// +//***************************************************************************** +// Field: [31:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECFG +// +//***************************************************************************** +// Field: [8] IDLEGATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 + +// Field: [4:3] SLAVEPOWER +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 + +// Field: [0] GATING +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSESTAT +// +//***************************************************************************** +// Field: [0] RESETDONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_ACC +// +//***************************************************************************** +// Field: [23:0] ACCUMULATOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_BOUNDARY +// +//***************************************************************************** +// Field: [23] DISROW0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 + +// Field: [22] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 + +// Field: [21] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 + +// Field: [20] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 + +// Field: [19] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 + +// Field: [18] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 + +// Field: [17:14] OUTPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 + +// Field: [11] EFC_FDI +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 + +// Field: [10] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 + +// Field: [9:8] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 + +// Field: [7:4] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 + +// Field: [3:0] INPUTENABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEFLAG +// +//***************************************************************************** +// Field: [0] KEY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEKEY +// +//***************************************************************************** +// Field: [31:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSERELEASE +// +//***************************************************************************** +// Field: [31:25] ODPYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 + +// Field: [24:21] ODPMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 + +// Field: [20:16] ODPDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 + +// Field: [15:9] EFUSEYEAR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 + +// Field: [8:5] EFUSEMONTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 + +// Field: [4:0] EFUSEDAY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPINS +// +//***************************************************************************** +// Field: [15] EFC_SELF_TEST_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 + +// Field: [14] EFC_SELF_TEST_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 + +// Field: [13] SYS_ECC_SELF_TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 + +// Field: [12] EFC_INSTRUCTION_INFO +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 + +// Field: [11] EFC_INSTRUCTION_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 + +// Field: [10] EFC_AUTOLOAD_ERROR +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 + +// Field: [9] SYS_ECC_OVERRIDE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 + +// Field: [8] EFC_READY +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 + +// Field: [7] EFC_FCLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 + +// Field: [6] SYS_DIEID_AUTOLOAD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 + +// Field: [5:4] SYS_REPAIR_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 + +// Field: [3:0] SYS_WS_READ_STATES +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSECRA +// +//***************************************************************************** +// Field: [5:0] DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEREAD +// +//***************************************************************************** +// Field: [9:8] DATABIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 + +// Field: [7:4] READCLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 + +// Field: [3] DEBUG +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 + +// Field: [2] SPARE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 + +// Field: [1:0] MARGIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEPROGRAM +// +//***************************************************************************** +// Field: [30] COMPAREDISABLE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 + +// Field: [29:14] CLOCKSTALL +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 + +// Field: [13] VPPTOVDD +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 + +// Field: [12:9] ITERATIONS +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 + +// Field: [8:0] WRITECLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_EFUSEERROR +// +//***************************************************************************** +// Field: [5] DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 + +// Field: [4:0] CODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SINGLEBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_TWOBIT +// +//***************************************************************************** +// Field: [31:1] FROMN +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 + +// Field: [0] FROM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTCYC +// +//***************************************************************************** +// Field: [31:0] CYCLES +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_SELFTESTSIGN +// +//***************************************************************************** +// Field: [31:0] SIGNATURE +// +// Internal. Only to be used through TI provided API. +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FRDCTL +// +//***************************************************************************** +// Field: [11:8] RWAIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSPRD +// +//***************************************************************************** +// Field: [15:8] RMBSEM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 + +// Field: [1] RM1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 + +// Field: [0] RM0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACCTL1 +// +//***************************************************************************** +// Field: [24] SUSP_IGNR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FEDACSTAT +// +//***************************************************************************** +// Field: [25] RVF_INT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 + +// Field: [24] FSM_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 + +//***************************************************************************** +// +// Register: FLASH_O_FBPROT +// +//***************************************************************************** +// Field: [0] PROTL1DIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBSE +// +//***************************************************************************** +// Field: [15:0] BSE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBBUSY +// +//***************************************************************************** +// Field: [7:0] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBAC +// +//***************************************************************************** +// Field: [17:16] OTPPROTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_OTPPROTDIS_W 2 +#define FLASH_FBAC_OTPPROTDIS_M 0x00030000 +#define FLASH_FBAC_OTPPROTDIS_S 16 + +// Field: [15:8] BAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 + +// Field: [7:0] VREADS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBFALLBACK +// +//***************************************************************************** +// Field: [27:24] FSM_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 + +// Field: [19:16] REG_PWRSAV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 + +// Field: [15:14] BANKPWR7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 + +// Field: [13:12] BANKPWR6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 + +// Field: [11:10] BANKPWR5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 + +// Field: [9:8] BANKPWR4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 + +// Field: [7:6] BANKPWR3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 + +// Field: [5:4] BANKPWR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 + +// Field: [3:2] BANKPWR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 + +// Field: [1:0] BANKPWR0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBPRDY +// +//***************************************************************************** +// Field: [17:16] BANKBUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKBUSY_W 2 +#define FLASH_FBPRDY_BANKBUSY_M 0x00030000 +#define FLASH_FBPRDY_BANKBUSY_S 16 + +// Field: [15] PUMPRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 + +// Field: [1:0] BANKRDY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBPRDY_BANKRDY_W 2 +#define FLASH_FBPRDY_BANKRDY_M 0x00000003 +#define FLASH_FBPRDY_BANKRDY_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC1 +// +//***************************************************************************** +// Field: [27:16] PSLEEPTDIS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 + +// Field: [15:4] PUMPRESET_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 + +// Field: [1:0] PUMPPWR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FPAC2 +// +//***************************************************************************** +// Field: [15:0] PAGP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMAC +// +//***************************************************************************** +// Field: [2:0] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMSTAT +// +//***************************************************************************** +// Field: [17] RVSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 + +// Field: [16] RDVER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 + +// Field: [15] RVF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 + +// Field: [14] ILA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 + +// Field: [13] DBF +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 + +// Field: [12] PGV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 + +// Field: [11] PCV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 + +// Field: [10] EV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 + +// Field: [9] CV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 + +// Field: [8] BUSY +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 + +// Field: [7] ERS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 + +// Field: [6] PGM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 + +// Field: [5] INVDAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 + +// Field: [4] CSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 + +// Field: [3] VOLSTAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 + +// Field: [2] ESUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 + +// Field: [1] PSUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 + +// Field: [0] SLOCK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FLOCK +// +//***************************************************************************** +// Field: [15:0] ENCOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVREADCT +// +//***************************************************************************** +// Field: [3:0] VREADCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT1 +// +//***************************************************************************** +// Field: [23:20] TRIM13_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +// Field: [19:16] VHVCT_E +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +// Field: [7:4] TRIM13_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +// Field: [3:0] VHVCT_PV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT2 +// +//***************************************************************************** +// Field: [23:20] TRIM13_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +// Field: [19:16] VHVCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FVHVCT3 +// +//***************************************************************************** +// Field: [19:16] WCT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 + +// Field: [3:0] VHVCT_READ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVNVCT +// +//***************************************************************************** +// Field: [12:8] VCG2P5CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +// Field: [4:0] VIN_CT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FVSLP +// +//***************************************************************************** +// Field: [15:12] VSL_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FVWLCT +// +//***************************************************************************** +// Field: [4:0] VWLCT_P +// +// Internal. Only to be used through TI provided API. +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSECTL +// +//***************************************************************************** +// Field: [26:24] CHAIN_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 + +// Field: [17] WRITE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 + +// Field: [16] BP_SEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 + +// Field: [8] EF_CLRZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 + +// Field: [4] EF_TEST +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 + +// Field: [3:0] EFUSE_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSESTAT +// +//***************************************************************************** +// Field: [0] SHIFT_DONE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FEFUSEDATA +// +//***************************************************************************** +// Field: [31:0] FEFUSEDATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSEQPMP +// +//***************************************************************************** +// Field: [27:24] TRIM_3P4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 + +// Field: [21:20] TRIM_1P7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +// Field: [19:16] TRIM_0P8 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 + +// Field: [14:12] VIN_AT_X +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +// Field: [8] VIN_BY_PASS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FBSTROBES +// +//***************************************************************************** +// Field: [24] ECBIT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 + +// Field: [18] RWAIT2_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 + +// Field: [17] RWAIT_FLCLK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 + +// Field: [16] FLCLKEN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 + +// Field: [8] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 + +// Field: [6] NOCOLRED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 + +// Field: [5] PRECOL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 + +// Field: [4] TI_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 + +// Field: [3] OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 + +// Field: [2] TEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 + +//***************************************************************************** +// +// Register: FLASH_O_FPSTROBES +// +//***************************************************************************** +// Field: [8] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 + +// Field: [1] V3PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 + +// Field: [0] V5PWRDNZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FBMODE +// +//***************************************************************************** +// Field: [2:0] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCR +// +//***************************************************************************** +// Field: [6:0] TCR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FADDR +// +//***************************************************************************** +// Field: [31:0] FADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FTCTL +// +//***************************************************************************** +// Field: [16] WDATA_BLK_CLR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 + +// Field: [1] TEST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE0 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE1 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE2 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE3 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE4 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE4 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE5 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE5 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE6 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE6 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE7 +// +//***************************************************************************** +// Field: [31:0] FWPWRITE7 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FWPWRITE_ECC +// +//***************************************************************************** +// Field: [31:24] ECCBYTES07_00 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 + +// Field: [23:16] ECCBYTES15_08 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 + +// Field: [15:8] ECCBYTES23_16 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 + +// Field: [7:0] ECCBYTES31_24 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSWSTAT +// +//***************************************************************************** +// Field: [0] SAFELV +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_GLBCTL +// +//***************************************************************************** +// Field: [0] CLKSEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STATE +// +//***************************************************************************** +// Field: [11] CTRLENZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 + +// Field: [10] EXECUTEZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 + +// Field: [8] FSM_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 + +// Field: [7] TIOTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 + +// Field: [6] OTP_ACT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STAT +// +//***************************************************************************** +// Field: [2] NON_OP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 + +// Field: [1] OVR_PUL_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 + +// Field: [0] INV_DAT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMD +// +//***************************************************************************** +// Field: [5:0] FSMCMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_OSU +// +//***************************************************************************** +// Field: [15:8] PGM_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +// Field: [7:0] ERA_OSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_VSTAT +// +//***************************************************************************** +// Field: [15:12] VSTAT_CNT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VSU +// +//***************************************************************************** +// Field: [15:8] PGM_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +// Field: [7:0] ERA_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_CMP_VSU +// +//***************************************************************************** +// Field: [15:12] ADD_EXZ +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EX_VAL +// +//***************************************************************************** +// Field: [15:8] REP_VSU +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +// Field: [7:0] EXE_VALD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_RD_H +// +//***************************************************************************** +// Field: [7:0] RD_H +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_P_OH +// +//***************************************************************************** +// Field: [15:8] PGM_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_OH +// +//***************************************************************************** +// Field: [15:0] ERA_OH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_PPUL +// +//***************************************************************************** +// Field: [11:0] SAV_P_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PE_VH +// +//***************************************************************************** +// Field: [15:8] PGM_VH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PW +// +//***************************************************************************** +// Field: [15:0] PROG_PUL_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PW +// +//***************************************************************************** +// Field: [31:0] FSM_ERA_PW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SAV_ERA_PUL +// +//***************************************************************************** +// Field: [11:0] SAV_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_TIMER +// +//***************************************************************************** +// Field: [31:0] FSM_TIMER +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_MODE +// +//***************************************************************************** +// Field: [19:18] RDV_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 + +// Field: [17:16] PGM_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 + +// Field: [15:14] ERA_SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 + +// Field: [13:12] SUBMODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 + +// Field: [11:9] SAV_PGM_CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 + +// Field: [8:6] SAV_ERA_MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 + +// Field: [5:3] MODE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 + +// Field: [2:0] CMD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM +// +//***************************************************************************** +// Field: [25:23] PGM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 + +// Field: [22:0] PGM_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA +// +//***************************************************************************** +// Field: [25:23] ERA_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 + +// Field: [22:0] ERA_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PRG_PUL +// +//***************************************************************************** +// Field: [19:16] BEG_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +// Field: [11:0] MAX_PRG_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERA_PUL +// +//***************************************************************************** +// Field: [19:16] MAX_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +// Field: [11:0] MAX_ERA_PUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_STEP_SIZE +// +//***************************************************************************** +// Field: [24:16] EC_STEP_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PUL_CNTR +// +//***************************************************************************** +// Field: [24:16] CUR_EC_LEVEL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 + +// Field: [11:0] PUL_CNTR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EC_STEP_HEIGHT +// +//***************************************************************************** +// Field: [3:0] EC_STEP_HEIGHT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ST_MACHINE +// +//***************************************************************************** +// Field: [23] DO_PRECOND +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +// Field: [22] FSM_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 + +// Field: [21] ALL_BANKS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 + +// Field: [20] CMPV_ALLOWED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 + +// Field: [19] RANDOM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 + +// Field: [18] RV_SEC_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 + +// Field: [17] RV_RES +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 + +// Field: [16] RV_INT_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 + +// Field: [14] ONE_TIME_GOOD +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 + +// Field: [11] DO_REDU_COL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 + +// Field: [10:7] DBG_SHORT_ROW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 + +// Field: [5] PGM_SEC_COF_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 + +// Field: [4] PREC_STOP_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 + +// Field: [3] DIS_TST_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 + +// Field: [2] CMD_EN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 + +// Field: [1] INV_DATA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 + +// Field: [0] OVERRIDE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_FLES +// +//***************************************************************************** +// Field: [11:8] BLK_TIOTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 + +// Field: [7:0] BLK_OTP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_WR_ENA +// +//***************************************************************************** +// Field: [2:0] WR_ENA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_PP +// +//***************************************************************************** +// Field: [31:0] FSM_ACC_PP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ACC_EP +// +//***************************************************************************** +// Field: [15:0] ACC_EP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ADDR +// +//***************************************************************************** +// Field: [30:28] BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 + +// Field: [27:0] CUR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR +// +//***************************************************************************** +// Field: [31:16] SECT_ERASED +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 + +// Field: [15:8] FSM_SECTOR_EXTENSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 + +// Field: [7:4] SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 + +// Field: [3:0] SEC_OUT +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FMC_REV_ID +// +//***************************************************************************** +// Field: [31:12] MOD_VERSION +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 + +// Field: [11:0] CONFIG_CRC +// +// Internal. Only to be used through TI provided API. +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_ERR_ADDR +// +//***************************************************************************** +// Field: [30:28] FSM_ERR_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 3 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x70000000 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 28 + +// Field: [23:0] FSM_ERR_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0x00FFFFFF +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM_MAXPUL +// +//***************************************************************************** +// Field: [11:0] FSM_PGM_MAXPUL +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EXECUTE +// +//***************************************************************************** +// Field: [19:16] SUSPEND_NOW +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 + +// Field: [4:0] FSMEXECUTE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR1 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_SECTOR2 +// +//***************************************************************************** +// Field: [31:0] FSM_SECTOR2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLE1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLE1_FSM_BSLE1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSLE1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSLE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP0 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP0 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_BSLP1 +// +//***************************************************************************** +// Field: [31:0] FSM_BSLP1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FSM_BSLP1_FSM_BSLP1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSLP1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSLP1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_PGM128 +// +//***************************************************************************** +// Field: [0] EN_PGM128 +// +// 1: Enables 128-bit wide programming. This mode requires programming supply +// voltage to be greater than 2.5v at the Flash Pump. The primary use case for +// this mode is manufacturing test for test time reduction. +// +// 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit +// word is divided into two 64-bit words for programming. [default] +// +// This register is write protected with the FSM_WR_ENA register. +#define FLASH_FSM_PGM128_EN_PGM128 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_BITN 0 +#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FSM_EN_PRL_BNK_RD +// +//***************************************************************************** +// Field: [0] EN_PRL_BNK_RD +// +// 1: Enables parallel reads of multiple banks The primary use case for this +// mode is manufacturing test for test time reduction. +// +// 0: Read of one bank only. [default] +// +// This register is write protected with the FSM_WR_ENA register. +#define FLASH_FSM_EN_PRL_BNK_RD_EN_PRL_BNK_RD 0x00000001 +#define FLASH_FSM_EN_PRL_BNK_RD_EN_PRL_BNK_RD_BITN 0 +#define FLASH_FSM_EN_PRL_BNK_RD_EN_PRL_BNK_RD_M 0x00000001 +#define FLASH_FSM_EN_PRL_BNK_RD_EN_PRL_BNK_RD_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BANK +// +//***************************************************************************** +// Field: [31:20] EE_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 + +// Field: [19:16] EE_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 + +// Field: [15:4] MAIN_BANK_WIDTH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 + +// Field: [3:0] MAIN_NUM_BANK +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_WRAPPER +// +//***************************************************************************** +// Field: [31:24] FAMILY_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 + +// Field: [20] MEM_MAP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 + +// Field: [19:16] CPU2 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 + +// Field: [15:12] EE_IN_MAIN +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 + +// Field: [11] ROM +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 + +// Field: [10] IFLUSH +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 + +// Field: [9] SIL3 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 + +// Field: [8] ECCA +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 + +// Field: [7:6] AUTO_SUSP +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 + +// Field: [5:4] UERR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 + +// Field: [3:0] CPU_TYPE1 +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_BNK_TYPE +// +//***************************************************************************** +// Field: [31:28] B7_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 + +// Field: [27:24] B6_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 + +// Field: [23:20] B5_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 + +// Field: [19:16] B4_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 + +// Field: [15:12] B3_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 + +// Field: [11:8] B2_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 + +// Field: [7:4] B1_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 + +// Field: [3:0] B0_TYPE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_START +// +//***************************************************************************** +// Field: [31:28] B0_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 + +// Field: [27:24] B0_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 + +// Field: [23:0] B0_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_START +// +//***************************************************************************** +// Field: [31:28] B1_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 + +// Field: [27:24] B1_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 + +// Field: [23:0] B1_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_START +// +//***************************************************************************** +// Field: [31:28] B2_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 + +// Field: [27:24] B2_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 + +// Field: [23:0] B2_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_START +// +//***************************************************************************** +// Field: [31:28] B3_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 + +// Field: [27:24] B3_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 + +// Field: [23:0] B3_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_START +// +//***************************************************************************** +// Field: [31:28] B4_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 + +// Field: [27:24] B4_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 + +// Field: [23:0] B4_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_START +// +//***************************************************************************** +// Field: [31:28] B5_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 + +// Field: [27:24] B5_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 + +// Field: [23:0] B5_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_START +// +//***************************************************************************** +// Field: [31:28] B6_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 + +// Field: [27:24] B6_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 + +// Field: [23:0] B6_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_START +// +//***************************************************************************** +// Field: [31:28] B7_MAX_SECTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 + +// Field: [27:24] B7_MUX_FACTOR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 + +// Field: [23:0] B7_START_ADDR +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B0_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B1_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B1_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B1_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B1_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B1_SSIZE0_B0_SECT_SIZE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B1_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_SSIZE0 +// +//***************************************************************************** +// Field: [27:16] B0_NUM_SECTORS +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B2_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B2_SSIZE0_B0_NUM_SECTORS_S 16 + +// Field: [3:0] B0_SECT_SIZE +// +// Internal. Only to be used through TI provided API. +#define FLASH_FCFG_B2_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B2_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B2_SSIZE0_B0_SECT_SIZE_S 0 + +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B2_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_SSIZE0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B3_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_SSIZE0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B4_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_SSIZE0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B5_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_SSIZE0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B6_SSIZE3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_SSIZE0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_SSIZE1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_SSIZE2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: FLASH_O_FCFG_B7_SSIZE3 +// +//***************************************************************************** + +#endif // __FLASH__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpio.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpio.h new file mode 100644 index 00000000..9975f073 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpio.h @@ -0,0 +1,2247 @@ +/****************************************************************************** +* Filename: hw_gpio_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPIO component +// +//***************************************************************************** +// Data Out 0 to 3 +#define GPIO_O_DOUT3_0 0x00000000 + +// Data Out 4 to 7 +#define GPIO_O_DOUT7_4 0x00000004 + +// Data Out 8 to 11 +#define GPIO_O_DOUT11_8 0x00000008 + +// Data Out 12 to 15 +#define GPIO_O_DOUT15_12 0x0000000C + +// Data Out 16 to 19 +#define GPIO_O_DOUT19_16 0x00000010 + +// Data Out 20 to 23 +#define GPIO_O_DOUT23_20 0x00000014 + +// Data Out 24 to 27 +#define GPIO_O_DOUT27_24 0x00000018 + +// Data Out 28 to 31 +#define GPIO_O_DOUT31_28 0x0000001C + +// Data Output for DIO 0 to 31 +#define GPIO_O_DOUT31_0 0x00000080 + +// Data Out Set +#define GPIO_O_DOUTSET31_0 0x00000090 + +// Data Out Clear +#define GPIO_O_DOUTCLR31_0 0x000000A0 + +// Data Out Toggle +#define GPIO_O_DOUTTGL31_0 0x000000B0 + +// Data Input from DIO 0 to 31 +#define GPIO_O_DIN31_0 0x000000C0 + +// Data Output Enable for DIO 0 to 31 +#define GPIO_O_DOE31_0 0x000000D0 + +// Event Register for DIO 0 to 31 +#define GPIO_O_EVFLAGS31_0 0x000000E0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT3_0 +// +//***************************************************************************** +// Field: [24] DIO3 +// +// Sets the state of the pin that is configured as DIO#3, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 + +// Field: [16] DIO2 +// +// Sets the state of the pin that is configured as DIO#2, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 + +// Field: [8] DIO1 +// +// Sets the state of the pin that is configured as DIO#1, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 + +// Field: [0] DIO0 +// +// Sets the state of the pin that is configured as DIO#0, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT7_4 +// +//***************************************************************************** +// Field: [24] DIO7 +// +// Sets the state of the pin that is configured as DIO#7, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 + +// Field: [16] DIO6 +// +// Sets the state of the pin that is configured as DIO#6, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 + +// Field: [8] DIO5 +// +// Sets the state of the pin that is configured as DIO#5, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 + +// Field: [0] DIO4 +// +// Sets the state of the pin that is configured as DIO#4, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT11_8 +// +//***************************************************************************** +// Field: [24] DIO11 +// +// Sets the state of the pin that is configured as DIO#11, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 + +// Field: [16] DIO10 +// +// Sets the state of the pin that is configured as DIO#10, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 + +// Field: [8] DIO9 +// +// Sets the state of the pin that is configured as DIO#9, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 + +// Field: [0] DIO8 +// +// Sets the state of the pin that is configured as DIO#8, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT15_12 +// +//***************************************************************************** +// Field: [24] DIO15 +// +// Sets the state of the pin that is configured as DIO#15, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 + +// Field: [16] DIO14 +// +// Sets the state of the pin that is configured as DIO#14, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 + +// Field: [8] DIO13 +// +// Sets the state of the pin that is configured as DIO#13, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 + +// Field: [0] DIO12 +// +// Sets the state of the pin that is configured as DIO#12, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT19_16 +// +//***************************************************************************** +// Field: [24] DIO19 +// +// Sets the state of the pin that is configured as DIO#19, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 + +// Field: [16] DIO18 +// +// Sets the state of the pin that is configured as DIO#18, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 + +// Field: [8] DIO17 +// +// Sets the state of the pin that is configured as DIO#17, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 + +// Field: [0] DIO16 +// +// Sets the state of the pin that is configured as DIO#16, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT23_20 +// +//***************************************************************************** +// Field: [24] DIO23 +// +// Sets the state of the pin that is configured as DIO#23, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 + +// Field: [16] DIO22 +// +// Sets the state of the pin that is configured as DIO#22, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 + +// Field: [8] DIO21 +// +// Sets the state of the pin that is configured as DIO#21, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 + +// Field: [0] DIO20 +// +// Sets the state of the pin that is configured as DIO#20, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT27_24 +// +//***************************************************************************** +// Field: [24] DIO27 +// +// Sets the state of the pin that is configured as DIO#27, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 + +// Field: [16] DIO26 +// +// Sets the state of the pin that is configured as DIO#26, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 + +// Field: [8] DIO25 +// +// Sets the state of the pin that is configured as DIO#25, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 + +// Field: [0] DIO24 +// +// Sets the state of the pin that is configured as DIO#24, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_28 +// +//***************************************************************************** +// Field: [24] DIO31 +// +// Sets the state of the pin that is configured as DIO#31, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 + +// Field: [16] DIO30 +// +// Sets the state of the pin that is configured as DIO#30, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 + +// Field: [8] DIO29 +// +// Sets the state of the pin that is configured as DIO#29, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 + +// Field: [0] DIO28 +// +// Sets the state of the pin that is configured as DIO#28, if the corresponding +// DOE31_0 bitfield is set. +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUT31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output for DIO 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output for DIO 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output for DIO 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output for DIO 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output for DIO 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output for DIO 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output for DIO 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output for DIO 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output for DIO 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output for DIO 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output for DIO 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output for DIO 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output for DIO 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output for DIO 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output for DIO 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output for DIO 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output for DIO 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output for DIO 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output for DIO 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output for DIO 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output for DIO 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output for DIO 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output for DIO 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output for DIO 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output for DIO 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output for DIO 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output for DIO 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output for DIO 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output for DIO 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output for DIO 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output for DIO 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output for DIO 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTSET31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Set bit 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Set bit 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Set bit 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Set bit 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Set bit 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Set bit 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Set bit 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Set bit 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Set bit 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Set bit 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Set bit 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Set bit 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Set bit 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Set bit 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Set bit 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Set bit 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Set bit 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Set bit 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Set bit 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Set bit 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Set bit 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Set bit 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Set bit 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Set bit 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Set bit 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Set bit 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Set bit 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Set bit 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Set bit 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Set bit 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Set bit 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Set bit 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTCLR31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Clears bit 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Clears bit 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Clears bit 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Clears bit 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Clears bit 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Clears bit 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Clears bit 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Clears bit 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Clears bit 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Clears bit 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Clears bit 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Clears bit 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Clears bit 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Clears bit 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Clears bit 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Clears bit 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Clears bit 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Clears bit 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Clears bit 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Clears bit 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Clears bit 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Clears bit 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Clears bit 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Clears bit 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Clears bit 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Clears bit 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Clears bit 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Clears bit 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Clears bit 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Clears bit 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Clears bit 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Clears bit 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOUTTGL31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Toggles bit 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Toggles bit 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Toggles bit 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Toggles bit 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Toggles bit 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Toggles bit 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Toggles bit 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Toggles bit 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Toggles bit 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Toggles bit 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Toggles bit 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Toggles bit 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Toggles bit 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Toggles bit 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Toggles bit 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Toggles bit 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Toggles bit 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Toggles bit 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Toggles bit 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Toggles bit 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Toggles bit 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Toggles bit 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Toggles bit 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Toggles bit 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Toggles bit 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Toggles bit 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Toggles bit 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Toggles bit 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Toggles bit 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Toggles bit 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Toggles bit 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Toggles bit 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DIN31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data input from DIO 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data input from DIO 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data input from DIO 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data input from DIO 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data input from DIO 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data input from DIO 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data input from DIO 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data input from DIO 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data input from DIO 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data input from DIO 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data input from DIO 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data input from DIO 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data input from DIO 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data input from DIO 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data input from DIO 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data input from DIO 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data input from DIO 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data input from DIO 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data input from DIO 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data input from DIO 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data input from DIO 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data input from DIO 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data input from DIO 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data input from DIO 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data input from DIO 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data input from DIO 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data input from DIO 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data input from DIO 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data input from DIO 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data input from DIO 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data input from DIO 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data input from DIO 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_DOE31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Data output enable for DIO 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Data output enable for DIO 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Data output enable for DIO 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Data output enable for DIO 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Data output enable for DIO 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Data output enable for DIO 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Data output enable for DIO 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Data output enable for DIO 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Data output enable for DIO 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Data output enable for DIO 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Data output enable for DIO 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Data output enable for DIO 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Data output enable for DIO 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Data output enable for DIO 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Data output enable for DIO 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Data output enable for DIO 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Data output enable for DIO 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Data output enable for DIO 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Data output enable for DIO 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Data output enable for DIO 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Data output enable for DIO 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Data output enable for DIO 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Data output enable for DIO 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Data output enable for DIO 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Data output enable for DIO 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Data output enable for DIO 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Data output enable for DIO 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Data output enable for DIO 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Data output enable for DIO 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Data output enable for DIO 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Data output enable for DIO 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Data output enable for DIO 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 + +//***************************************************************************** +// +// Register: GPIO_O_EVFLAGS31_0 +// +//***************************************************************************** +// Field: [31] DIO31 +// +// Event for DIO 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 + +// Field: [30] DIO30 +// +// Event for DIO 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 + +// Field: [29] DIO29 +// +// Event for DIO 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 + +// Field: [28] DIO28 +// +// Event for DIO 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 + +// Field: [27] DIO27 +// +// Event for DIO 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 + +// Field: [26] DIO26 +// +// Event for DIO 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 + +// Field: [25] DIO25 +// +// Event for DIO 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 + +// Field: [24] DIO24 +// +// Event for DIO 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 + +// Field: [23] DIO23 +// +// Event for DIO 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 + +// Field: [22] DIO22 +// +// Event for DIO 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 + +// Field: [21] DIO21 +// +// Event for DIO 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 + +// Field: [20] DIO20 +// +// Event for DIO 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 + +// Field: [19] DIO19 +// +// Event for DIO 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 + +// Field: [18] DIO18 +// +// Event for DIO 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 + +// Field: [17] DIO17 +// +// Event for DIO 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 + +// Field: [16] DIO16 +// +// Event for DIO 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 + +// Field: [15] DIO15 +// +// Event for DIO 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 + +// Field: [14] DIO14 +// +// Event for DIO 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 + +// Field: [13] DIO13 +// +// Event for DIO 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 + +// Field: [12] DIO12 +// +// Event for DIO 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 + +// Field: [11] DIO11 +// +// Event for DIO 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 + +// Field: [10] DIO10 +// +// Event for DIO 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 + +// Field: [9] DIO9 +// +// Event for DIO 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 + +// Field: [8] DIO8 +// +// Event for DIO 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 + +// Field: [7] DIO7 +// +// Event for DIO 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 + +// Field: [6] DIO6 +// +// Event for DIO 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 + +// Field: [5] DIO5 +// +// Event for DIO 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 + +// Field: [4] DIO4 +// +// Event for DIO 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 + +// Field: [3] DIO3 +// +// Event for DIO 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 + +// Field: [2] DIO2 +// +// Event for DIO 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 + +// Field: [1] DIO1 +// +// Event for DIO 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 + +// Field: [0] DIO0 +// +// Event for DIO 0 +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 + + +#endif // __GPIO__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpram.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpram.h new file mode 100644 index 00000000..1794f4e7 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_gpram_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPRAM_H__ +#define __HW_GPRAM_H__ + + +#define GPRAM_O_BANK0 0x00000000 +#define GPRAM_BANK0_BYTE_SIZE 8192 + +#define GPRAM_TOT_BYTE_SIZE 8192 + + + +#endif // __HW_GPRAM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpt.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpt.h new file mode 100644 index 00000000..8783b9e4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_gpt.h @@ -0,0 +1,1697 @@ +/****************************************************************************** +* Filename: hw_gpt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_GPT_H__ +#define __HW_GPT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// GPT component +// +//***************************************************************************** +// Configuration +#define GPT_O_CFG 0x00000000 + +// Timer A Mode +#define GPT_O_TAMR 0x00000004 + +// Timer B Mode +#define GPT_O_TBMR 0x00000008 + +// Control +#define GPT_O_CTL 0x0000000C + +// Synch Register +#define GPT_O_SYNC 0x00000010 + +// Interrupt Mask +#define GPT_O_IMR 0x00000018 + +// Raw Interrupt Status +#define GPT_O_RIS 0x0000001C + +// Masked Interrupt Status +#define GPT_O_MIS 0x00000020 + +// Interrupt Clear +#define GPT_O_ICLR 0x00000024 + +// Timer A Interval Load Register +#define GPT_O_TAILR 0x00000028 + +// Timer B Interval Load Register +#define GPT_O_TBILR 0x0000002C + +// Timer A Match Register +#define GPT_O_TAMATCHR 0x00000030 + +// Timer B Match Register +#define GPT_O_TBMATCHR 0x00000034 + +// Timer A Pre-scale +#define GPT_O_TAPR 0x00000038 + +// Timer B Pre-scale +#define GPT_O_TBPR 0x0000003C + +// Timer A Pre-scale Match +#define GPT_O_TAPMR 0x00000040 + +// Timer B Pre-scale Match +#define GPT_O_TBPMR 0x00000044 + +// Timer A Register +#define GPT_O_TAR 0x00000048 + +// Timer B Register +#define GPT_O_TBR 0x0000004C + +// Timer A Value +#define GPT_O_TAV 0x00000050 + +// Timer B Value +#define GPT_O_TBV 0x00000054 + +// Timer A Pre-scale Snap-shot +#define GPT_O_TAPS 0x0000005C + +// Timer B Pre-scale Snap-shot +#define GPT_O_TBPS 0x00000060 + +// Timer A Pre-scale Value +#define GPT_O_TAPV 0x00000064 + +// Timer B Pre-scale Value +#define GPT_O_TBPV 0x00000068 + +// DMA Event +#define GPT_O_DMAEV 0x0000006C + +// Peripheral Version +#define GPT_O_VERSION 0x00000FB0 + +// Combined CCP Output +#define GPT_O_ANDCCP 0x00000FB4 + +//***************************************************************************** +// +// Register: GPT_O_CFG +// +//***************************************************************************** +// Field: [2:0] CFG +// +// GPT Configuration +// 0x2- 0x3 - Reserved +// 0x5- 0x7 - Reserved +// ENUMs: +// 16BIT_TIMER 16-bit timer configuration. +// Configure for two 16-bit +// timers. +// Also see TAMR.TAMR and +// TBMR.TBMR. +// 32BIT_TIMER 32-bit timer configuration +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_TAMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TACINTD +// +// One-Shot/Periodic Interrupt Disable +// ENUMs: +// DIS_TO_INTR Time-out interrupt are disabled +// EN_TO_INTR Time-out interrupt function as normal +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TAPLO +// +// GPTM Timer A PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TAILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TAILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 + +// Field: [10] TAMRSU +// +// Timer A Match Register Update mode +// +// This bit defines when the TAMATCHR and TAPR registers are updated. +// +// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and +// TAPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and +// TAPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TAMATCHR and TAPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next +// cycle. +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TAPWMIE +// +// GPTM Timer A PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TAEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 + +// Field: [8] TAILD +// +// GPT Timer A PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TAR register with the value in the +// TAILR register on the next timeout. If the +// prescaler is used, update the TAPS register +// with the value in the TAPR register on the next +// timeout. +// CYCLEUPDATE Update the TAR register with the value in the +// TAILR register on the next clock cycle. If the +// pre-scaler is used, update the TAPS register +// with the value in the TAPR register on the next +// clock cycle. +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TASNAPS +// +// GPT Timer A Snap-Shot Mode +// ENUMs: +// EN If Timer A is configured in the periodic mode, the +// actual free-running value of Timer A is loaded +// at the time-out event into the GPT Timer A +// (TAR) register. +// DIS Snap-shot mode is disabled. +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 + +// Field: [6] TAWOT +// +// GPT Timer A Wait-On-Trigger +// ENUMs: +// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does +// not begin counting until it receives a trigger +// from the timer in the previous position in the +// daisy chain. This bit must be clear for GPT +// Module 0, Timer A. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer A begins counting as soon as it is enabled. +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 + +// Field: [5] TAMIE +// +// GPT Timer A Match Interrupt Enable +// ENUMs: +// EN An interrupt is generated when the match value in +// TAMATCHR is reached in the one-shot and +// periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 + +// Field: [4] TACDIR +// +// GPT Timer A Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 + +// Field: [3] TAAMS +// +// GPT Timer A Alternate Mode +// +// Note: To enable PWM mode, you must also clear TACM and then configure TAMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 + +// Field: [2] TACM +// +// GPT Timer A Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 + +// Field: [1:0] TAMR +// +// GPT Timer A Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_TBMR +// +//***************************************************************************** +// Field: [15:13] TCACT +// +// Timer Compare Action Select +// ENUMs: +// CLRSET_ON_TO Clear CCP output pin immediately and set on +// Time-Out +// SETCLR_ON_TO Set CCP output pin immediately and clear on +// Time-Out +// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on +// Time-Out +// SETTOG_ON_TO Set CCP output pin immediately and toggle on +// Time-Out +// SET_ON_TO Set CCP output pin on Time-Out +// CLR_ON_TO Clear CCP output pin on Time-Out +// TOG_ON_TO Toggle State on Time-Out +// DIS_CMP Disable compare operations +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 + +// Field: [12] TBCINTD +// +// One-Shot/Periodic Interrupt Mode +// ENUMs: +// DIS_TO_INTR Mask Time-Out Interrupt +// EN_TO_INTR Normal Time-Out Interrupt +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 + +// Field: [11] TBPLO +// +// GPTM Timer B PWM Legacy Operation +// +// 0 Legacy operation with CCP pin driven Low when the TBILR +// register is reloaded after the timer reaches 0. +// +// 1 CCP is driven High when the TBILR register is reloaded after the timer +// reaches 0. +// +// This bit is only valid in PWM mode. +// ENUMs: +// CCP_ON_TO CCP output pin is set to 1 on time-out +// LEGACY Legacy operation +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 + +// Field: [10] TBMRSU +// +// Timer B Match Register Update mode +// +// This bit defines when the TBMATCHR and TBPR registers are updated +// +// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR +// and TBPR are updated when the timer is enabled. +// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR +// and TBPR are updated according to the configuration of this bit. +// ENUMs: +// TOUPDATE Update TBMATCHR and TBPR, if used, on the next +// time-out. +// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next +// cycle. +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 + +// Field: [9] TBPWMIE +// +// GPTM Timer B PWM Interrupt Enable +// This bit enables interrupts in PWM mode on rising, falling, or both edges of +// the CCP output, as defined by the CTL.TBEVENT +// In addition, when this bit is set and a capture event occurs, Timer A +// automatically generates triggers to the DMA if the trigger capability is +// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit +// respectively. +// +// 0 Capture event interrupt is disabled. +// 1 Capture event interrupt is enabled. +// This bit is only valid in PWM mode. +// ENUMs: +// EN Interrupt is enabled. This bit is only valid in +// PWM mode. +// DIS Interrupt is disabled. +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 + +// Field: [8] TBILD +// +// GPT Timer B PWM Interval Load Write +// ENUMs: +// TOUPDATE Update the TBR register with the value in the +// TBILR register on the next timeout. If the +// prescaler is used, update the TBPS register +// with the value in the TBPR register on the next +// timeout. +// CYCLEUPDATE Update the TBR register with the value in the +// TBILR register on the next clock cycle. If the +// pre-scaler is used, update the TBPS register +// with the value in the TBPR register on the next +// clock cycle. +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 + +// Field: [7] TBSNAPS +// +// GPT Timer B Snap-Shot Mode +// ENUMs: +// EN If Timer B is configured in the periodic mode +// DIS Snap-shot mode is disabled. +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 + +// Field: [6] TBWOT +// +// GPT Timer B Wait-On-Trigger +// ENUMs: +// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B +// does not begin counting until it receives a +// trigger from the timer in the previous position +// in the daisy chain. This function is valid for +// one-shot, periodic, and PWM modes +// NOWAIT Timer B begins counting as soon as it is enabled. +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 + +// Field: [5] TBMIE +// +// GPT Timer B Match Interrupt Enable. +// ENUMs: +// EN An interrupt is generated when the match value in +// the TBMATCHR register is reached in the +// one-shot and periodic modes. +// DIS The match interrupt is disabled for match events. +// Additionally, output triggers on match events +// are prevented. +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 + +// Field: [4] TBCDIR +// +// GPT Timer B Count Direction +// ENUMs: +// UP The timer counts up. When counting up, the timer +// starts from a value of 0x0. +// DOWN The timer counts down. +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 + +// Field: [3] TBAMS +// +// GPT Timer B Alternate Mode +// +// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR +// field to 0x2. +// ENUMs: +// PWM PWM mode is enabled +// CAP_COMP Capture/Compare mode is enabled. +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 + +// Field: [2] TBCM +// +// GPT Timer B Capture Mode +// ENUMs: +// EDGTIME Edge-Time mode +// EDGCNT Edge-Count mode +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 + +// Field: [1:0] TBMR +// +// GPT Timer B Mode +// +// 0x0 Reserved +// 0x1 One-Shot Timer mode +// 0x2 Periodic Timer mode +// 0x3 Capture mode +// The Timer mode is based on the timer configuration defined by bits 2:0 in +// the CFG register +// ENUMs: +// CAPTURE Capture mode +// PERIODIC Periodic Timer mode +// ONE_SHOT One-Shot Timer mode +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 + +//***************************************************************************** +// +// Register: GPT_O_CTL +// +//***************************************************************************** +// Field: [14] TBPWML +// +// GPT Timer B PWM Output Level +// +// 0: Output is unaffected. +// 1: Output is inverted. +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 + +// Field: [11:10] TBEVENT +// +// GPT Timer B Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 + +// Field: [9] TBSTALL +// +// GPT Timer B Stall Enable +// ENUMs: +// EN Timer B freezes counting while the processor is +// halted by the debugger. +// DIS Timer B continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 + +// Field: [8] TBEN +// +// GPT Timer B Enable +// ENUMs: +// EN Timer B is enabled and begins counting or the +// capture logic is enabled based on CFG register. +// DIS Timer B is disabled. +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 + +// Field: [6] TAPWML +// +// GPT Timer A PWM Output Level +// ENUMs: +// INVERTED Inverted +// NORMAL Not inverted +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 + +// Field: [3:2] TAEVENT +// +// GPT Timer A Event Mode +// +// The values in this register are defined as follows: +// Value Description +// 0x0 Positive edge +// 0x1 Negative edge +// 0x2 Reserved +// 0x3 Both edges +// Note: If PWM output inversion is enabled, edge detection interrupt +// behavior is reversed. Thus, if a positive-edge interrupt trigger +// has been set and the PWM inversion generates a postive +// edge, no event-trigger interrupt asserts. Instead, the interrupt +// is generated on the negative edge of the PWM signal. +// ENUMs: +// BOTH Both edges +// NEG Negative edge +// POS Positive edge +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 + +// Field: [1] TASTALL +// +// GPT Timer A Stall Enable +// ENUMs: +// EN Timer A freezes counting while the processor is +// halted by the debugger. +// DIS Timer A continues counting while the processor is +// halted by the debugger. +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 + +// Field: [0] TAEN +// +// GPT Timer A Enable +// ENUMs: +// EN Timer A is enabled and begins counting or the +// capture logic is enabled based on the CFG +// register. +// DIS Timer A is disabled. +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_SYNC +// +//***************************************************************************** +// Field: [7:6] SYNC3 +// +// Synchronize GPT Timer 3. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT3 is triggered +// TIMERB A timeout event for Timer B of GPT3 is triggered +// TIMERA A timeout event for Timer A of GPT3 is triggered +// NOSYNC No Sync. GPT3 is not affected. +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 + +// Field: [5:4] SYNC2 +// +// Synchronize GPT Timer 2. +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT2 is triggered +// TIMERB A timeout event for Timer B of GPT2 is triggered +// TIMERA A timeout event for Timer A of GPT2 is triggered +// NOSYNC No Sync. GPT2 is not affected. +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 + +// Field: [3:2] SYNC1 +// +// Synchronize GPT Timer 1 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT1 is triggered +// TIMERB A timeout event for Timer B of GPT1 is triggered +// TIMERA A timeout event for Timer A of GPT1 is triggered +// NOSYNC No Sync. GPT1 is not affected. +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 + +// Field: [1:0] SYNC0 +// +// Synchronize GPT Timer 0 +// ENUMs: +// BOTH A timeout event for both Timer A and Timer B of +// GPT0 is triggered +// TIMERB A timeout event for Timer B of GPT0 is triggered +// TIMERA A timeout event for Timer A of GPT0 is triggered +// NOSYNC No Sync. GPT0 is not affected. +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_IMR +// +//***************************************************************************** +// Field: [13] DMABIM +// +// Enabling this bit will make the RIS.DMABRIS interrupt propagate to +// MIS.DMABMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 + +// Field: [11] TBMIM +// +// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 + +// Field: [10] CBEIM +// +// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 + +// Field: [9] CBMIM +// +// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 + +// Field: [8] TBTOIM +// +// Enabling this bit will make the RIS.TBTORIS interrupt propagate to +// MIS.TBTOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 + +// Field: [5] DMAAIM +// +// Enabling this bit will make the RIS.DMAARIS interrupt propagate to +// MIS.DMAAMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 + +// Field: [4] TAMIM +// +// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 + +// Field: [2] CAEIM +// +// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 + +// Field: [1] CAMIM +// +// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 + +// Field: [0] TATOIM +// +// Enabling this bit will make the RIS.TATORIS interrupt propagate to +// MIS.TATOMIS +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: GPT_O_RIS +// +//***************************************************************************** +// Field: [13] DMABRIS +// +// GPT Timer B DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 + +// Field: [11] TBMRIS +// +// GPT Timer B Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 + +// Field: [10] CBERIS +// +// GPT Timer B Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 + +// Field: [9] CBMRIS +// +// GPT Timer B Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer B has not occurred. +// 1: A capture mode match has occurred for Timer B. This interrupt +// asserts when the values in the TBR and TBPR +// match the values in the TBMATCHR and TBPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 + +// Field: [8] TBTORIS +// +// GPT Timer B Time-out Raw Interrupt +// +// 0: Timer B has not timed out +// 1: Timer B has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TBILR, +// depending on the count direction. +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 + +// Field: [5] DMAARIS +// +// GPT Timer A DMA Done Raw Interrupt Status +// +// 0: Transfer has not completed +// 1: Transfer has completed +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 + +// Field: [4] TAMRIS +// +// GPT Timer A Match Raw Interrupt +// +// 0: The match value has not been reached +// 1: The match value is reached. +// +// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR +// have been reached when configured in one-shot or periodic mode. +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 + +// Field: [2] CAERIS +// +// GPT Timer A Capture Mode Event Raw Interrupt +// +// 0: The event has not occured. +// 1: The event has occured. +// +// This interrupt asserts when the subtimer is configured in Input Edge-Time +// mode +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 + +// Field: [1] CAMRIS +// +// GPT Timer A Capture Mode Match Raw Interrupt +// +// 0: The capture mode match for Timer A has not occurred. +// 1: A capture mode match has occurred for Timer A. This interrupt +// asserts when the values in the TAR and TAPR +// match the values in the TAMATCHR and TAPMR +// when configured in Input Edge-Time mode. +// +// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 + +// Field: [0] TATORIS +// +// GPT Timer A Time-out Raw Interrupt +// +// 0: Timer A has not timed out +// 1: Timer A has timed out. +// +// This interrupt is asserted when a one-shot or periodic mode timer reaches +// its count limit. The count limit is 0 or the value loaded into TAILR, +// depending on the count direction. +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_MIS +// +//***************************************************************************** +// Field: [13] DMABMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 + +// Field: [11] TBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 + +// Field: [10] CBEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 + +// Field: [9] CBMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 + +// Field: [8] TBTOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 + +// Field: [5] DMAAMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 + +// Field: [4] TAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 + +// Field: [2] CAEMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 + +// Field: [1] CAMMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 + +// Field: [0] TATOMIS +// +// 0: No interrupt or interrupt not enabled +// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ICLR +// +//***************************************************************************** +// Field: [13] DMABINT +// +// 0: Do nothing. +// 1: Clear RIS.DMABRIS and MIS.DMABMIS +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 + +// Field: [11] TBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBMRIS and MIS.TBMMIS +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 + +// Field: [10] CBECINT +// +// 0: Do nothing. +// 1: Clear RIS.CBERIS and MIS.CBEMIS +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 + +// Field: [9] CBMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CBMRIS and MIS.CBMMIS +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 + +// Field: [8] TBTOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TBTORIS and MIS.TBTOMIS +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 + +// Field: [5] DMAAINT +// +// 0: Do nothing. +// 1: Clear RIS.DMAARIS and MIS.DMAAMIS +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 + +// Field: [4] TAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.TAMRIS and MIS.TAMMIS +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 + +// Field: [2] CAECINT +// +// 0: Do nothing. +// 1: Clear RIS.CAERIS and MIS.CAEMIS +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 + +// Field: [1] CAMCINT +// +// 0: Do nothing. +// 1: Clear RIS.CAMRIS and MIS.CAMMIS +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 + +// Field: [0] TATOCINT +// +// 0: Do nothing. +// 1: Clear RIS.TATORIS and MIS.TATOMIS +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAILR +// +//***************************************************************************** +// Field: [31:0] TAILR +// +// GPT Timer A Interval Load Register +// +// Writing this field loads the counter for Timer A. A read returns the current +// value of TAILR. +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBILR +// +//***************************************************************************** +// Field: [31:0] TBILR +// +// GPT Timer B Interval Load Register +// +// Writing this field loads the counter for Timer B. A read returns the current +// value of TBILR. +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAMATCHR +// +//***************************************************************************** +// Field: [31:0] TAMATCHR +// +// GPT Timer A Match Register +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBMATCHR +// +//***************************************************************************** +// Field: [15:0] TBMATCHR +// +// GPT Timer B Match Register +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPR +// +//***************************************************************************** +// Field: [7:0] TAPSR +// +// Timer A Pre-scale. +// +// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPR +// +//***************************************************************************** +// Field: [7:0] TBPSR +// +// Timer B Pre-scale. +// +// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: +// +// 0: Prescaler ratio = 1 +// 1: Prescaler ratio = 2 +// 2: Prescaler ratio = 3 +// ... +// 255: Prescaler ratio = 256 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPMR +// +//***************************************************************************** +// Field: [7:0] TAPSMR +// +// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPMR +// +//***************************************************************************** +// Field: [7:0] TBPSMR +// +// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits +// 23 to 16. +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAR +// +//***************************************************************************** +// Field: [31:0] TAR +// +// GPT Timer A Register +// +// Based on the value in the register field TAMR.TAILD, this register is +// updated with the value from TAILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer A Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBR +// +//***************************************************************************** +// Field: [31:0] TBR +// +// GPT Timer B Register +// +// Based on the value in the register field TBMR.TBILD, this register is +// updated with the value from TBILR register either on the next cycle or on +// the next timeout. +// +// A read returns the current value of the Timer B Count Register, in all cases +// except for Input Edge count and Timer modes. +// In the Input Edge Count Mode, this register contains the number of edges +// that have occurred. In the Input Edge Time mode, this register contains the +// time at which the last edge event took place. +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAV +// +//***************************************************************************** +// Field: [31:0] TAV +// +// GPT Timer A Register +// A read returns the current, free-running value of Timer A in all modes. +// When written, the value written into this register is loaded into the +// TAR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBV +// +//***************************************************************************** +// Field: [31:0] TBV +// +// GPT Timer B Register +// A read returns the current, free-running value of Timer B in all modes. +// When written, the value written into this register is loaded into the +// TBR register on the next clock cycle. +// Note: In 16-bit mode, only the lower 16-bits of this +// register can be written with a new value. Writes to the prescaler bits have +// no effect +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer A Pre-scaler +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPS +// +//***************************************************************************** +// Field: [7:0] PSS +// +// GPT Timer B Pre-scaler +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TAPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer A Pre-scaler Value +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_TBPV +// +//***************************************************************************** +// Field: [7:0] PSV +// +// GPT Timer B Pre-scaler Value +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 + +//***************************************************************************** +// +// Register: GPT_O_DMAEV +// +//***************************************************************************** +// Field: [11] TBMDMAEN +// +// GPT Timer B Match DMA Trigger Enable +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 + +// Field: [10] CBEDMAEN +// +// GPT Timer B Capture Event DMA Trigger Enable +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 + +// Field: [9] CBMDMAEN +// +// GPT Timer B Capture Match DMA Trigger Enable +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 + +// Field: [8] TBTODMAEN +// +// GPT Timer B Time-Out DMA Trigger Enable +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 + +// Field: [4] TAMDMAEN +// +// GPT Timer A Match DMA Trigger Enable +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 + +// Field: [2] CAEDMAEN +// +// GPT Timer A Capture Event DMA Trigger Enable +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 + +// Field: [1] CAMDMAEN +// +// GPT Timer A Capture Match DMA Trigger Enable +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 + +// Field: [0] TATODMAEN +// +// GPT Timer A Time-Out DMA Trigger Enable +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 + +//***************************************************************************** +// +// Register: GPT_O_VERSION +// +//***************************************************************************** +// Field: [31:0] VERSION +// +// Timer Revision. +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 + +//***************************************************************************** +// +// Register: GPT_O_ANDCCP +// +//***************************************************************************** +// Field: [1] LD_TO_EN +// +// PWM assertion would happen at timeout +// +// 0: PWM assertion happens when counter matches load value +// 1: PWM assertion happens at timeout of the counter +#define GPT_ANDCCP_LD_TO_EN 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_BITN 1 +#define GPT_ANDCCP_LD_TO_EN_M 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_S 1 + +// Field: [0] CCP_AND_EN +// +// Enables AND operation of the CCP outputs for timers A and B. +// +// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM +// signals of the respective timers. +// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM +// signals and Timer B PWM ouput is Timer B PWM signal only. +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 + + +#endif // __GPT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2c.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2c.h new file mode 100644 index 00000000..926bd967 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2c.h @@ -0,0 +1,728 @@ +/****************************************************************************** +* Filename: hw_i2c_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2C component +// +//***************************************************************************** +// Slave Own Address +#define I2C_O_SOAR 0x00000000 + +// Slave Status +#define I2C_O_SSTAT 0x00000004 + +// Slave Control +#define I2C_O_SCTL 0x00000004 + +// Slave Data +#define I2C_O_SDR 0x00000008 + +// Slave Interrupt Mask +#define I2C_O_SIMR 0x0000000C + +// Slave Raw Interrupt Status +#define I2C_O_SRIS 0x00000010 + +// Slave Masked Interrupt Status +#define I2C_O_SMIS 0x00000014 + +// Slave Interrupt Clear +#define I2C_O_SICR 0x00000018 + +// Master Salve Address +#define I2C_O_MSA 0x00000800 + +// Master Status +#define I2C_O_MSTAT 0x00000804 + +// Master Control +#define I2C_O_MCTRL 0x00000804 + +// Master Data +#define I2C_O_MDR 0x00000808 + +// I2C Master Timer Period +#define I2C_O_MTPR 0x0000080C + +// Master Interrupt Mask +#define I2C_O_MIMR 0x00000810 + +// Master Raw Interrupt Status +#define I2C_O_MRIS 0x00000814 + +// Master Masked Interrupt Status +#define I2C_O_MMIS 0x00000818 + +// Master Interrupt Clear +#define I2C_O_MICR 0x0000081C + +// Master Configuration +#define I2C_O_MCR 0x00000820 + +//***************************************************************************** +// +// Register: I2C_O_SOAR +// +//***************************************************************************** +// Field: [6:0] OAR +// +// I2C slave own address +// This field specifies bits a6 through a0 of the slave address. +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SSTAT +// +//***************************************************************************** +// Field: [2] FBR +// +// First byte received +// +// 0: The first byte has not been received. +// 1: The first byte following the slave's own address has been received. +// +// This bit is only valid when the RREQ bit is set and is automatically cleared +// when data has been read from the SDR register. +// Note: This bit is not used for slave transmit operations. +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 + +// Field: [1] TREQ +// +// Transmit request +// +// 0: No outstanding transmit request. +// 1: The I2C controller has been addressed as a slave transmitter and is using +// clock stretching to delay the master until data has been written to the SDR +// register. +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 + +// Field: [0] RREQ +// +// Receive request +// +// 0: No outstanding receive data +// 1: The I2C controller has outstanding receive data from the I2C master and +// is using clock stretching to delay the master until data has been read from +// the SDR register. +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SCTL +// +//***************************************************************************** +// Field: [0] DA +// +// Device active +// +// 0: Disables the I2C slave operation +// 1: Enables the I2C slave operation +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// Data for transfer +// This field contains the data for transfer during a slave receive or transmit +// operation. When written the register data is used as transmit data. When +// read, this register returns the last data received. +// Data is stored until next update, either by a system write for transmit or +// by an external master for receive. +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SIMR +// +//***************************************************************************** +// Field: [2] STOPIM +// +// Stop condition interrupt mask +// +// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 + +// Field: [1] STARTIM +// +// Start condition interrupt mask +// +// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt +// controller. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 + +// Field: [0] DATAIM +// +// Data interrupt mask +// +// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt +// controller. +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SRIS +// +//***************************************************************************** +// Field: [2] STOPRIS +// +// Stop condition raw interrupt status +// +// 0: No interrupt +// 1: A Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STOPIC. +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 + +// Field: [1] STARTRIS +// +// Start condition raw interrupt status +// +// 0: No interrupt +// 1: A Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to SICR.STARTIC. +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 + +// Field: [0] DATARIS +// +// Data raw interrupt status +// +// 0: No interrupt +// 1: A data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SMIS +// +//***************************************************************************** +// Field: [2] STOPMIS +// +// Stop condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Stop condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STOPIC. +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 + +// Field: [1] STARTMIS +// +// Start condition masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked Start condition interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.STARTIC. +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 + +// Field: [0] DATAMIS +// +// Data masked interrupt status +// +// 0: An interrupt has not occurred or is masked/disabled. +// 1: An unmasked data received or data requested interrupt is pending. +// +// This bit is cleared by writing a 1 to the SICR.DATAIC. +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_SICR +// +//***************************************************************************** +// Field: [2] STOPIC +// +// Stop condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 + +// Field: [1] STARTIC +// +// Start condition interrupt clear +// +// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 + +// Field: [0] DATAIC +// +// Data interrupt clear +// +// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MSA +// +//***************************************************************************** +// Field: [7:1] SA +// +// I2C master slave address +// Defines which slave is addressed for the transaction in master mode +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 + +// Field: [0] RS +// +// Receive or Send +// This bit-field specifies if the next operation is a receive (high) or a +// transmit/send (low) from the addressed slave SA. +// ENUMs: +// RX Receive data from slave +// TX Transmit/send data to slave +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MSTAT +// +//***************************************************************************** +// Field: [6] BUSBSY +// +// Bus busy +// +// 0: The I2C bus is idle. +// 1: The I2C bus is busy. +// +// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 + +// Field: [5] IDLE +// +// I2C idle +// +// 0: The I2C controller is not idle. +// 1: The I2C controller is idle. +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 + +// Field: [4] ARBLST +// +// Arbitration lost +// +// 0: The I2C controller won arbitration. +// 1: The I2C controller lost arbitration. +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 + +// Field: [3] DATACK_N +// +// Data Was Not Acknowledge +// +// 0: The transmitted data was acknowledged. +// 1: The transmitted data was not acknowledged. +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 + +// Field: [2] ADRACK_N +// +// Address Was Not Acknowledge +// +// 0: The transmitted address was acknowledged. +// 1: The transmitted address was not acknowledged. +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 + +// Field: [1] ERR +// +// Error +// +// 0: No error was detected on the last operation. +// 1: An error occurred on the last operation. +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 + +// Field: [0] BUSY +// +// I2C busy +// +// 0: The controller is idle. +// 1: The controller is busy. +// +// When this bit-field is set, the other status bits are not valid. +// +// Note: The I2C controller requires four SYSBUS clock cycles to assert the +// BUSY status after I2C master operation has been initiated through MCTRL +// register. +// Hence after programming MCTRL register, application is requested to wait for +// four SYSBUS clock cycles before issuing a controller status inquiry through +// MSTAT register. +// Any prior inquiry would result in wrong status being reported. +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCTRL +// +//***************************************************************************** +// Field: [3] ACK +// +// Data acknowledge enable +// +// 0: The received data byte is not acknowledged automatically by the master. +// 1: The received data byte is acknowledged automatically by the master. +// +// This bit-field must be cleared when the I2C bus controller requires no +// further data to be transmitted from the slave transmitter. +// ENUMs: +// EN Enable acknowledge +// DIS Disable acknowledge +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 + +// Field: [2] STOP +// +// This bit-field determines if the cycle stops at the end of the data cycle or +// continues on to a repeated START condition. +// +// 0: The controller does not generate the Stop condition. +// 1: The controller generates the Stop condition. +// ENUMs: +// EN Enable STOP +// DIS Disable STOP +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 + +// Field: [1] START +// +// This bit-field generates the Start or Repeated Start condition. +// +// 0: The controller does not generate the Start condition. +// 1: The controller generates the Start condition. +// ENUMs: +// EN Enable START +// DIS Disable START +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 + +// Field: [0] RUN +// +// I2C master enable +// +// 0: The master is disabled. +// 1: The master is enabled to transmit or receive data. +// ENUMs: +// EN Enable Master +// DIS Disable Master +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MDR +// +//***************************************************************************** +// Field: [7:0] DATA +// +// When Read: Last RX Data is returned +// When Written: Data is transferred during TX transaction +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MTPR +// +//***************************************************************************** +// Field: [7] TPR_7 +// +// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 + +// Field: [6:0] TPR +// +// SCL clock period +// This field specifies the period of the SCL clock. +// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD +// where: +// SCL_PRD is the SCL line period (I2C clock). +// TPR is the timer period register value (range of 1 to 127) +// SCL_LP is the SCL low period (fixed at 6). +// SCL_HP is the SCL high period (fixed at 4). +// CLK_PRD is the system clock period in ns. +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MIMR +// +//***************************************************************************** +// Field: [0] IM +// +// Interrupt mask +// +// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt +// controller. +// 1: The master interrupt is sent to the interrupt controller when the +// MRIS.RIS is set. +// ENUMs: +// EN Enable Interrupt +// DIS Disable Interrupt +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2C_O_MRIS +// +//***************************************************************************** +// Field: [0] RIS +// +// Raw interrupt status +// +// 0: No interrupt +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MMIS +// +//***************************************************************************** +// Field: [0] MIS +// +// Masked interrupt status +// +// 0: An interrupt has not occurred or is masked. +// 1: A master interrupt is pending. +// +// This bit is cleared by writing 1 to the MICR.IC bit . +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MICR +// +//***************************************************************************** +// Field: [0] IC +// +// Interrupt clear +// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . +// +// Reading this register returns no meaningful data. +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 + +//***************************************************************************** +// +// Register: I2C_O_MCR +// +//***************************************************************************** +// Field: [5] SFE +// +// I2C slave function enable +// ENUMs: +// EN Slave mode is enabled. +// DIS Slave mode is disabled. +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 + +// Field: [4] MFE +// +// I2C master function enable +// ENUMs: +// EN Master mode is enabled. +// DIS Master mode is disabled. +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 + +// Field: [0] LPBK +// +// I2C loopback +// +// 0: Normal operation +// 1: Loopback operation (test mode) +// ENUMs: +// EN Enable Test Mode +// DIS Disable Test Mode +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 + + +#endif // __I2C__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2s.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2s.h new file mode 100644 index 00000000..8c774b06 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_i2s.h @@ -0,0 +1,967 @@ +/****************************************************************************** +* Filename: hw_i2s_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_I2S_H__ +#define __HW_I2S_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// I2S component +// +//***************************************************************************** +// WCLK Source Selection +#define I2S_O_AIFWCLKSRC 0x00000000 + +// DMA Buffer Size Configuration +#define I2S_O_AIFDMACFG 0x00000004 + +// Pin Direction +#define I2S_O_AIFDIRCFG 0x00000008 + +// Serial Interface Format Configuration +#define I2S_O_AIFFMTCFG 0x0000000C + +// Word Selection Bit Mask for Pin 0 +#define I2S_O_AIFWMASK0 0x00000010 + +// Word Selection Bit Mask for Pin 1 +#define I2S_O_AIFWMASK1 0x00000014 + +// Audio Interface PWM Debug Value +#define I2S_O_AIFPWMVALUE 0x0000001C + +// DMA Input Buffer Next Pointer +#define I2S_O_AIFINPTRNEXT 0x00000020 + +// DMA Input Buffer Current Pointer +#define I2S_O_AIFINPTR 0x00000024 + +// DMA Output Buffer Next Pointer +#define I2S_O_AIFOUTPTRNEXT 0x00000028 + +// DMA Output Buffer Current Pointer +#define I2S_O_AIFOUTPTR 0x0000002C + +// Samplestamp Generator Control Register +#define I2S_O_STMPCTL 0x00000034 + +// Captured XOSC Counter Value, Capture Channel 0 +#define I2S_O_STMPXCNTCAPT0 0x00000038 + +// XOSC Period Value +#define I2S_O_STMPXPER 0x0000003C + +// Captured WCLK Counter Value, Capture Channel 0 +#define I2S_O_STMPWCNTCAPT0 0x00000040 + +// WCLK Counter Period Value +#define I2S_O_STMPWPER 0x00000044 + +// WCLK Counter Trigger Value for Input Pins +#define I2S_O_STMPINTRIG 0x00000048 + +// WCLK Counter Trigger Value for Output Pins +#define I2S_O_STMPOUTTRIG 0x0000004C + +// WCLK Counter Set Operation +#define I2S_O_STMPWSET 0x00000050 + +// WCLK Counter Add Operation +#define I2S_O_STMPWADD 0x00000054 + +// XOSC Minimum Period Value +#define I2S_O_STMPXPERMIN 0x00000058 + +// Current Value of WCNT +#define I2S_O_STMPWCNT 0x0000005C + +// Current Value of XCNT +#define I2S_O_STMPXCNT 0x00000060 + +// Internal +#define I2S_O_STMPXCNTCAPT1 0x00000064 + +// Internal +#define I2S_O_STMPWCNTCAPT1 0x00000068 + +// Interrupt Mask Register +#define I2S_O_IRQMASK 0x00000070 + +// Raw Interrupt Status Register +#define I2S_O_IRQFLAGS 0x00000074 + +// Interrupt Set Register +#define I2S_O_IRQSET 0x00000078 + +// Interrupt Clear Register +#define I2S_O_IRQCLR 0x0000007C + +//***************************************************************************** +// +// Register: I2S_O_AIFWCLKSRC +// +//***************************************************************************** +// Field: [2] WCLK_INV +// +// Inverts WCLK source (pad or internal) when set. +// +// 0: Not inverted +// 1: Inverted +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 + +// Field: [1:0] WCLK_SRC +// +// Selects WCLK source for AIF (should be the same as the BCLK source). The +// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC +// ENUMs: +// RESERVED Not supported. Will give same WCLK as 'NONE' +// ('00') +// INT Internal WCLK generator, from module PRCM +// EXT External WCLK generator, from pad +// NONE None ('0') +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFDMACFG +// +//***************************************************************************** +// Field: [7:0] END_FRAME_IDX +// +// Defines the length of the DMA buffer. Writing a non-zero value to this +// register field enables and initializes AIF. Note that before doing so, all +// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must +// have been loaded. +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFDIRCFG +// +//***************************************************************************** +// Field: [5:4] AD1 +// +// Configures the AD1 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 + +// Field: [1:0] AD0 +// +// Configures the AD0 audio data pin usage: +// +// 0x3: Reserved +// ENUMs: +// OUT Output mode +// IN Input mode +// DIS Not in use (disabled) +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 + +//***************************************************************************** +// +// Register: I2S_O_AIFFMTCFG +// +//***************************************************************************** +// Field: [15:8] DATA_DELAY +// +// The number of BCLK periods between a WCLK edge and MSB of the first word in +// a phase: +// +// 0x00: LJF and DSP format +// 0x01: I2S and DSP format +// 0x02: RJF format +// ... +// 0xFF: RJF format +// +// Note: When 0, MSB of the next word will be output in the idle period between +// LSB of the previous word and the start of the next word. Otherwise logical 0 +// will be output until the data delay has expired. +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 + +// Field: [7] MEM_LEN_24 +// +// The size of each word stored to or loaded from memory: +// ENUMs: +// 24BIT 24-bit (one 8 bit and one 16 bit locked access per +// sample) +// 16BIT 16-bit (one 16 bit access per sample) +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 + +// Field: [6] SMPL_EDGE +// +// On the serial audio interface, data (and wclk) is sampled and clocked out on +// opposite edges of BCLK. +// ENUMs: +// POS Data is sampled on the positive edge and clocked +// out on the negative edge. +// NEG Data is sampled on the negative edge and clocked +// out on the positive edge. +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 + +// Field: [5] DUAL_PHASE +// +// Selects dual- or single-phase format. +// +// 0: Single-phase: DSP format +// 1: Dual-phase: I2S, LJF and RJF formats +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 + +// Field: [4:0] WORD_LEN +// +// Number of bits per word (8-24): +// In single-phase format, this is the exact number of bits per word. +// In dual-phase format, this is the maximum number of bits per word. +// +// Values below 8 and above 24 give undefined behavior. Data written to memory +// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that +// differ from this alignment will either be truncated or zero padded. +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK0 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD0. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFWMASK1 +// +//***************************************************************************** +// Field: [7:0] MASK +// +// Bit-mask indicating valid channels in a frame on AD1. +// +// In single-phase mode, each bit represents one channel, starting with LSB for +// the first word in the frame. A frame can contain up to 8 channels. Channels +// that are not included in the mask will not be sampled and stored in memory, +// and clocked out as '0'. +// +// In dual-phase mode, only the two LSBs are considered. For a stereo +// configuration, set both bits. For a mono configuration, set bit 0 only. In +// mono mode, only channel 0 will be sampled and stored to memory, and channel +// 0 will be repeated when clocked out. +// +// In mono mode, only channel 0 will be sampled and stored to memory, and +// channel 0 will be repeated in the second phase when clocked out. +// +// If all bits are zero, no input words will be stored to memory, and the +// output data lines will be constant '0'. This can be utilized when PWM debug +// output is desired without any actively used output pins. +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFPWMVALUE +// +//***************************************************************************** +// Field: [15:0] PULSE_WIDTH +// +// The value written to this register determines the width of the active high +// PWM pulse (pwm_debug), which starts together with MSB of the first output +// word in a DMA buffer: +// +// 0x0000: Constant low +// 0x0001: Width of the pulse (number of BCLK cycles, here 1). +// ... +// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). +// 0xFFFF: Constant high +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA input buffer. +// +// The read value equals the last written value until the currently used DMA +// input buffer is completed, and then becomes null when the last written value +// is transferred to the DMA controller to start on the next buffer. This event +// is signalized by IRQFLAGS.AIF_DMA_IN. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFINPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA input buffer pointer currently used by the DMA controller. +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTRNEXT +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Pointer to the first byte in the next DMA output buffer. +// +// The read value equals the last written value until the currently used DMA +// output buffer is completed, and then becomes null when the last written +// value is transferred to the DMA controller to start on the next buffer. This +// event is signalized by IRQFLAGS.AIF_DMA_OUT. +// +// At startup, the value must be written once before and once after configuring +// the DMA buffer size in AIFDMACFG. At this time, the first two samples will +// be fetched from memory. +// +// The next pointer must be written to this register while the DMA function +// uses the previously written pointer. If not written in time, +// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_AIFOUTPTR +// +//***************************************************************************** +// Field: [31:0] PTR +// +// Value of the DMA output buffer pointer currently used by the DMA controller +// Incremented by 1 (byte) or 2 (word) for each AHB access. +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPCTL +// +//***************************************************************************** +// Field: [2] OUT_RDY +// +// Low until the output pins are ready to be started by the samplestamp +// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the +// bit goes back low. +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 + +// Field: [1] IN_RDY +// +// Low until the input pins are ready to be started by the samplestamp +// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit +// goes back low. +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 + +// Field: [0] STMP_EN +// +// Enables the samplestamp generator. The samplestamp generator must only be +// enabled after it has been properly configured. +// When cleared, all samplestamp generator counters and capture values are +// cleared. +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for +// channel 0). This number corresponds to the number of 24 MHz clock cycles +// since the last positive edge of the selected WCLK. +// The value is cleared when STMPCTL.STMP_EN = 0. +// Note: Due to buffering and synchronization, WCLK is delayed by a small +// number of BCLK periods and clk periods. +// Note: When calculating the fractional part of the sample stamp, STMPXPER may +// be less than this bit field. +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// The number of 24 MHz clock cycles in the previous WCLK period (that is - +// the next value of the XOSC counter at the positive WCLK edge, had it not +// been reset to 0). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT0 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an +// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel +// 0). This number corresponds to the number of positive WCLK edges since the +// samplestamp generator was enabled (not taking modification through +// STMPWADD/STMPWSET into account). +// The value is cleared when STMPCTL.STMP_EN = 0. +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWPER +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Used to define when STMPWCNT is to be reset so number of WCLK edges are +// found for the size of the sample buffer. This is thus a modulo value for the +// WCLK counter. This number must correspond to the size of the sample buffer +// used by the system (that is the index of the last sample plus 1). +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPINTRIG +// +//***************************************************************************** +// Field: [15:0] IN_START_WCNT +// +// Compare value used to start the incoming audio streams. +// This bit field shall equal the WCLK counter value during the WCLK period in +// which the first input word(s) are sampled and stored to memory (that is the +// sample at the start of the very first DMA input buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as inputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and at least 32 +// BCLK cycle ticks have happened. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPOUTTRIG +// +//***************************************************************************** +// Field: [15:0] OUT_START_WCNT +// +// Compare value used to start the outgoing audio streams. +// +// This bit field must equal the WCLK counter value during the WCLK period in +// which the first output word(s) read from memory are clocked out (that is the +// sample at the start of the very first DMA output buffer). +// +// The value of this register takes effect when the following conditions are +// met: +// - One or more pins are configured as outputs in AIFDIRCFG. +// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK +// cycle ticks have happened. +// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register +// if necessary). +// Note: The memory read access is only performed when required, that is +// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. +// +// Note: To avoid false triggers, this bit field should be set higher than +// STMPWPER.VALUE. +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWSET +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// WCLK counter modification: Sets the running WCLK counter equal to the +// written value. +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWADD +// +//***************************************************************************** +// Field: [15:0] VALUE_INC +// +// WCLK counter modification: Adds the written value to the running WCLK +// counter. If a positive edge of WCLK occurs at the same time as the +// operation, this will be taken into account. +// To add a negative value, write "STMPWPER.VALUE - value". +// +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXPERMIN +// +//***************************************************************************** +// Field: [15:0] VALUE +// +// Each time STMPXPER is updated, the value is also loaded into this register, +// provided that the value is smaller than the current value in this register. +// When written, the register is reset to 0xFFFF (65535), regardless of the +// value written. +// The minimum value can be used to detect extra WCLK pulses (this registers +// value will be significantly smaller than STMPXPER.VALUE). +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the WCLK counter +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNT +// +//***************************************************************************** +// Field: [15:0] CURR_VALUE +// +// Current value of the XOSC counter, latched when reading STMPWCNT. +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPXCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_STMPWCNTCAPT1 +// +//***************************************************************************** +// Field: [15:0] CAPT_VALUE +// +// Internal. Only to be used through TI provided API. +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQMASK +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// IRQFLAGS.AIF_DMA_IN interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// IRQFLAGS.AIF_DMA_OUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// IRQFLAGS.WCLK_TIMEOUT interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// IRQFLAGS.BUS_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// IRQFLAGS.WCLK_ERR interrupt mask +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// IRQFLAGS.PTR_ERR interrupt mask. +// +// 0: Disable +// 1: Enable +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQFLAGS +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// Set when condition for this bit field event occurs (auto cleared when input +// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register +// for details. +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// Set when condition for this bit field event occurs (auto cleared when output +// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT +// register for details +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// Set when the sample stamp generator does not detect a positive WCLK edge for +// 65535 clk periods. This signalizes that the internal or external BCLK and +// WCLK generator source has been disabled. +// +// The bit is sticky and may only be cleared by software (by writing '1' to +// IRQCLR.WCLK_TIMEOUT). +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// Set when a DMA operation is not completed in time (that is audio output +// buffer underflow, or audio input buffer overflow). +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.BUS_ERR). +// +// Note that DMA initiated transactions to illegal addresses will not trigger +// an interrupt. The response to such transactions is undefined. +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// Set when: +// - An unexpected WCLK edge occurs during the data delay period of a phase. +// Note unexpected WCLK edges during the word and idle periods of the phase are +// not detected. +// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles +// apart. +// - In single-phase mode, when a WCLK pulse occurs before the last channel. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.WCLK_ERR). +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next +// block address in time. +// This error requires a complete restart since word synchronization has been +// lost. The bit is sticky and may only be cleared by software (by writing '1' +// to IRQCLR.PTR_ERR). +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQSET +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria +// was given at the same time, in which the set will be ignored) +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Sets the interrupt of IRQFLAGS.BUS_ERR +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Sets the interrupt of IRQFLAGS.PTR_ERR +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 + +//***************************************************************************** +// +// Register: I2S_O_IRQCLR +// +//***************************************************************************** +// Field: [5] AIF_DMA_IN +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 + +// Field: [4] AIF_DMA_OUT +// +// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 + +// Field: [3] WCLK_TIMEOUT +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 + +// Field: [2] BUS_ERR +// +// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 + +// Field: [1] WCLK_ERR +// +// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was +// given at the same time in which the clear will be ignored) +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 + +// Field: [0] PTR_ERR +// +// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given +// at the same time in which the clear will be ignored) +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 + + +#endif // __I2S__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ints.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ints.h new file mode 100644 index 00000000..ded28ef4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ints.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Filename: hw_ints_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) + // Fault +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the + // System Timer in NVIC. +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE + // Generated events +#define INT_PKA_IRQ 19 // PKA Interrupt event +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE + // Generated events +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command + // Acknowledgement Interrupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt + // event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event +#define INT_OSC_COMB 50 // Combined event from Oscillator + // control +#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0 +#define INT_UART1_COMB 52 // UART1 combined interrupt +#define INT_BATMON_COMB 53 // Combined event from battery + // monitor + +//***************************************************************************** +// +// The following are defines for number of interrupts and priority levels. +// +//***************************************************************************** +#define NUM_INTERRUPTS 54 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels + + +//***************************************************************************** +// +// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 +// +//***************************************************************************** + +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ioc.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ioc.h new file mode 100644 index 00000000..07cf8d9f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ioc.h @@ -0,0 +1,11951 @@ +/****************************************************************************** +* Filename: hw_ioc_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_IOC_H__ +#define __HW_IOC_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// IOC component +// +//***************************************************************************** +// Configuration of DIO0 +#define IOC_O_IOCFG0 0x00000000 + +// Configuration of DIO1 +#define IOC_O_IOCFG1 0x00000004 + +// Configuration of DIO2 +#define IOC_O_IOCFG2 0x00000008 + +// Configuration of DIO3 +#define IOC_O_IOCFG3 0x0000000C + +// Configuration of DIO4 +#define IOC_O_IOCFG4 0x00000010 + +// Configuration of DIO5 +#define IOC_O_IOCFG5 0x00000014 + +// Configuration of DIO6 +#define IOC_O_IOCFG6 0x00000018 + +// Configuration of DIO7 +#define IOC_O_IOCFG7 0x0000001C + +// Configuration of DIO8 +#define IOC_O_IOCFG8 0x00000020 + +// Configuration of DIO9 +#define IOC_O_IOCFG9 0x00000024 + +// Configuration of DIO10 +#define IOC_O_IOCFG10 0x00000028 + +// Configuration of DIO11 +#define IOC_O_IOCFG11 0x0000002C + +// Configuration of DIO12 +#define IOC_O_IOCFG12 0x00000030 + +// Configuration of DIO13 +#define IOC_O_IOCFG13 0x00000034 + +// Configuration of DIO14 +#define IOC_O_IOCFG14 0x00000038 + +// Configuration of DIO15 +#define IOC_O_IOCFG15 0x0000003C + +// Configuration of DIO16 +#define IOC_O_IOCFG16 0x00000040 + +// Configuration of DIO17 +#define IOC_O_IOCFG17 0x00000044 + +// Configuration of DIO18 +#define IOC_O_IOCFG18 0x00000048 + +// Configuration of DIO19 +#define IOC_O_IOCFG19 0x0000004C + +// Configuration of DIO20 +#define IOC_O_IOCFG20 0x00000050 + +// Configuration of DIO21 +#define IOC_O_IOCFG21 0x00000054 + +// Configuration of DIO22 +#define IOC_O_IOCFG22 0x00000058 + +// Configuration of DIO23 +#define IOC_O_IOCFG23 0x0000005C + +// Configuration of DIO24 +#define IOC_O_IOCFG24 0x00000060 + +// Configuration of DIO25 +#define IOC_O_IOCFG25 0x00000064 + +// Configuration of DIO26 +#define IOC_O_IOCFG26 0x00000068 + +// Configuration of DIO27 +#define IOC_O_IOCFG27 0x0000006C + +// Configuration of DIO28 +#define IOC_O_IOCFG28 0x00000070 + +// Configuration of DIO29 +#define IOC_O_IOCFG29 0x00000074 + +// Configuration of DIO30 +#define IOC_O_IOCFG30 0x00000078 + +// Configuration of DIO31 +#define IOC_O_IOCFG31 0x0000007C + +//***************************************************************************** +// +// Register: IOC_O_IOCFG0 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input/output +// OPENSRC Open Source +// Normal input / outut +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO0 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG1 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO1 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG2 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO2 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG3 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO3 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG4 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO4 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG5 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO5 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG6 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO6 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG7 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO7 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG8 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO8 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG9 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO9 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG10 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO10 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG11 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO11 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG12 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO12 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG13 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO13 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG14 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO14 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG15 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO15 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG16 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO16 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG17 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO17 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG18 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO18 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG19 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO19 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG20 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO20 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG21 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO21 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG22 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO22 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG23 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO23 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG24 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO24 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG25 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO25 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG26 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO26 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG27 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO27 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG28 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO28 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG29 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO29 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG30 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO30 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 + +//***************************************************************************** +// +// Register: IOC_O_IOCFG31 +// +//***************************************************************************** +// Field: [30] HYST_EN +// +// 0: Input hysteresis disable +// 1: Input hysteresis enable +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 + +// Field: [29] IE +// +// 0: Input disabled +// 1: Input enabled +// +// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be +// ignored. +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 + +// Field: [28:27] WU_CFG +// +// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or +// >0x08: +// +// 00: No wake-up +// 01: No wake-up +// 10: Wakes up from shutdown if this pad is going low. +// 11: Wakes up from shutdown if this pad is going high. +// +// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, +// this register only sets wakeup enable or not. +// +// 00, 01: Wakeup disabled +// 10, 11: Wakeup enabled +// +// Polarity is controlled from AON registers. +// +// Note:When the MSB is set, the IOC will deactivate the output enable for the +// DIO. +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 + +// Field: [26:24] IOMODE +// +// IO Mode +// Not applicable for IO configured for AON periph. signals and AUX PORT_ID +// 0x01-0x08 +// AUX has its own open_source/drain configuration. +// +// 0x2: Reserved. Undefined behavior. +// 0x3: Reserved. Undefined behavior. +// ENUMs: +// OPENSRC_INV Open Source +// Inverted input / output +// OPENSRC Open Source +// Normal input / output +// OPENDR_INV Open Drain +// Inverted input / output +// OPENDR Open Drain, +// Normal input / output +// INV Inverted input / ouput +// NORMAL Normal input / output +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 + +// Field: [23] IOEV_AON_PROG2_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG2 event +// 1: Input edge detection asserts AON_PROG2 event +#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 + +// Field: [22] IOEV_AON_PROG1_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG1 event +// 1: Input edge detection asserts AON_PROG1 event +#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 + +// Field: [21] IOEV_AON_PROG0_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert AON_PROG0 event +// 1: Input edge detection asserts AON_PROG0 event +#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 + +// Field: [18] EDGE_IRQ_EN +// +// 0: No interrupt generation +// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is +// enabled) +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 + +// Field: [17:16] EDGE_DET +// +// Enable generation of edge detection events on this IO +// ENUMs: +// BOTH Positive and negative edge detection +// POS Positive edge detection +// NEG Negative edge detection +// NONE No edge detection +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 + +// Field: [14:13] PULL_CTL +// +// Pull control +// ENUMs: +// DIS No pull +// UP Pull up +// DWN Pull down +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 + +// Field: [12] SLEW_RED +// +// 0: Normal slew rate +// 1: Enables reduced slew rate in output driver. +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 + +// Field: [11:10] IOCURR +// +// Selects IO current mode of this IO. +// ENUMs: +// 4_8MA Extended-Current (EC) mode: Min 8 mA for double +// drive strength IOs (min 4 mA for normal IOs) +// when IOSTR is set to AUTO +// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set +// to AUTO +// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set +// to AUTO +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 + +// Field: [9:8] IOSTR +// +// Select source for drive strength control of this IO. +// This setting controls the drive strength of the Low-Current (LC) mode. +// Higher drive strength can be selected in IOCURR +// ENUMs: +// MAX Maximum drive strength, controlled by +// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default +// values) +// MED Medium drive strength, controlled by +// AON_IOC:IOSTRMED (min 2 mA @2.5V with default +// values) +// MIN Minimum drive strength, controlled by +// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default +// values) +// AUTO Automatic drive strength, controlled by AON BATMON +// based on battery voltage. (min 2 mA @VDDS) +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 + +// Field: [7] IOEV_RTC_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert RTC event +// 1: Input edge detection asserts RTC event +#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_S 7 + +// Field: [6] IOEV_MCU_WU_EN +// +// Event asserted by this IO when edge detection is enabled +// +// 0: Input edge detection does not assert MCU_WU event +// 1: Input edge detection asserts MCU_WU event +#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 + +// Field: [5:0] PORT_ID +// +// Selects usage for DIO31 +// Note: This field should not be written other than the times when PORT_ID +// value is specifically required to change. +// ENUMs: +// RFC_SMI_CL_IN RF Core SMI Command Link In +// RFC_SMI_CL_OUT RF Core SMI Command Link Out +// RFC_SMI_DL_IN RF Core SMI Data Link In +// RFC_SMI_DL_OUT RF Core SMI Data Link Out +// RFC_GPI1 RF Core Data In 1 +// RFC_GPI0 RF Core Data In 0 +// RFC_GPO3 RF Core Data Out 3 +// RFC_GPO2 RF Core Data Out 2 +// RFC_GPO1 RF Core Data Out 1 +// RFC_GPO0 RF Core Data Out 0 +// RFC_TRC RF Core Trace +// I2S_MCLK I2S MCLK +// I2S_BCLK I2S BCLK +// I2S_WCLK I2S WCLK +// I2S_AD1 I2S Data 1 +// I2S_AD0 I2S Data 0 +// SSI1_CLK SSI1 CLK +// SSI1_FSS SSI1 FSS +// SSI1_TX SSI1 TX +// SSI1_RX SSI1 RX +// CPU_SWV CPU SWV +// PORT_EVENT7 PORT EVENT 7 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT6 PORT EVENT 6 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT5 PORT EVENT 5 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT4 PORT EVENT 4 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT3 PORT EVENT 3 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT2 PORT EVENT 2 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT1 PORT EVENT 1 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// PORT_EVENT0 PORT EVENT 0 +// Can be used as a general +// purpose IO event by selecting it through +// registers in the EVENT module, for example +// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, +// and so on +// UART1_RTS UART1 RTS +// UART1_CTS UART1 CTS +// UART1_TX UART1 TX +// UART1_RX UART1 RX +// UART0_RTS UART0 RTS +// UART0_CTS UART0 CTS +// UART0_TX UART0 TX +// UART0_RX UART0 RX +// I2C_MSSCL I2C Clock +// I2C_MSSDA I2C Data +// SSI0_CLK SSI0 CLK +// SSI0_FSS SSI0 FSS +// SSI0_TX SSI0 TX +// SSI0_RX SSI0 RX +// AUX_IO AUX IO +// AON_CLK32K AON 32 KHz clock (SCLK_LF) +// GPIO General Purpose IO +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 + + +#endif // __IOC__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap.h new file mode 100644 index 00000000..5c0d847e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap.h @@ -0,0 +1,180 @@ +/****************************************************************************** +* Filename: hw_memmap_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the CPU_MMAP interface +// +//***************************************************************************** +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define UART1_BASE 0x4000B000 // UART +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define PKA_BASE 0x40025000 // PKA +#define PKA_RAM_BASE 0x40026000 // PKA_RAM +#define PKA_INT_BASE 0x40027000 // PKA_INT +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM +#define AUX_MAC_BASE 0x400C2000 // AUX_MAC +#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF +#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO +#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO +#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 +#ifndef CCFG_BASE +#define CCFG_BASE 0x50003000 // CCFG +#endif +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base +#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base +#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base +#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base +#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base +#define AUX_TIMER01_NONBUF_BASE \ + 0x600C7000 // AUX_TIMER01 CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base +#define AUX_DDI0_OSC_NONBUF_BASE \ + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_AIODIO0_NONBUF_BASE \ + 0x600CC000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO1_NONBUF_BASE \ + 0x600CD000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO2_NONBUF_BASE \ + 0x600CE000 // AUX_AIODIO CPU nonbuf base +#define AUX_AIODIO3_NONBUF_BASE \ + 0x600CF000 // AUX_AIODIO CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + +#endif // __HW_MEMMAP__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap_common.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap_common.h new file mode 100644 index 00000000..2843421b --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_memmap_common.h @@ -0,0 +1,52 @@ +/****************************************************************************** +* Filename: hw_memmap_common.h +* +* Description: Common memory map macros. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_MEMMAP_COMMON_H__ +#define __HW_MEMMAP_COMMON_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Offset for secure peripheral addresses. Defined for all devices as a +// convenience, but only relevant on M33 and M33F cores with TrustZone. +// +//***************************************************************************** +#define NONSECURE_OFFSET 0x0 + +#endif // __HW_MEMMAP_COMMON_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_nvic.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_nvic.h new file mode 100644 index 00000000..88715761 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_nvic.h @@ -0,0 +1,1024 @@ +/****************************************************************************** +* Filename: hw_nvic.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka.h new file mode 100644 index 00000000..f92d630d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka.h @@ -0,0 +1,606 @@ +/****************************************************************************** +* Filename: hw_pka_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_H__ +#define __HW_PKA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PKA component +// +//***************************************************************************** +// PKA Vector A Address +#define PKA_O_APTR 0x00000000 + +// PKA Vector B Address +#define PKA_O_BPTR 0x00000004 + +// PKA Vector C Address +#define PKA_O_CPTR 0x00000008 + +// PKA Vector D Address +#define PKA_O_DPTR 0x0000000C + +// PKA Vector A Length +#define PKA_O_ALENGTH 0x00000010 + +// PKA Vector B Length +#define PKA_O_BLENGTH 0x00000014 + +// PKA Bit Shift Value +#define PKA_O_SHIFT 0x00000018 + +// PKA Function +#define PKA_O_FUNCTION 0x0000001C + +// PKA compare result +#define PKA_O_COMPARE 0x00000020 + +// PKA most-significant-word of result vector +#define PKA_O_MSW 0x00000024 + +// PKA most-significant-word of divide remainder +#define PKA_O_DIVMSW 0x00000028 + +// PKA sequencer control and status register +#define PKA_O_SEQCTRL 0x000000C8 + +// PKA hardware options register +#define PKA_O_OPTIONS 0x000000F4 + +// PKA firmware revision and capabilities register +#define PKA_O_FWREV 0x000000F8 + +// PKA hardware revision register +#define PKA_O_HWREV 0x000000FC + +//***************************************************************************** +// +// Register: PKA_O_APTR +// +//***************************************************************************** +// Field: [10:0] APTR +// +// This register specifies the location of vector A within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_APTR_APTR_W 11 +#define PKA_APTR_APTR_M 0x000007FF +#define PKA_APTR_APTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_BPTR +// +//***************************************************************************** +// Field: [10:0] BPTR +// +// This register specifies the location of vector B within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_BPTR_BPTR_W 11 +#define PKA_BPTR_BPTR_M 0x000007FF +#define PKA_BPTR_BPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_CPTR +// +//***************************************************************************** +// Field: [10:0] CPTR +// +// This register specifies the location of vector C within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_CPTR_CPTR_W 11 +#define PKA_CPTR_CPTR_M 0x000007FF +#define PKA_CPTR_CPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_DPTR +// +//***************************************************************************** +// Field: [10:0] DPTR +// +// This register specifies the location of vector D within the PKA RAM. Vectors +// are identified through the location of their least-significant 32-bit word. +// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte +// boundary. +#define PKA_DPTR_DPTR_W 11 +#define PKA_DPTR_DPTR_M 0x000007FF +#define PKA_DPTR_DPTR_S 0 + +//***************************************************************************** +// +// Register: PKA_O_ALENGTH +// +//***************************************************************************** +// Field: [8:0] ALENGTH +// +// This register specifies the length (in 32-bit words) of Vector A. +#define PKA_ALENGTH_ALENGTH_W 9 +#define PKA_ALENGTH_ALENGTH_M 0x000001FF +#define PKA_ALENGTH_ALENGTH_S 0 + +//***************************************************************************** +// +// Register: PKA_O_BLENGTH +// +//***************************************************************************** +// Field: [8:0] BLENGTH +// +// This register specifies the length (in 32-bit words) of Vector B. +#define PKA_BLENGTH_BLENGTH_W 9 +#define PKA_BLENGTH_BLENGTH_M 0x000001FF +#define PKA_BLENGTH_BLENGTH_S 0 + +//***************************************************************************** +// +// Register: PKA_O_SHIFT +// +//***************************************************************************** +// Field: [4:0] NUM_BITS_TO_SHIFT +// +// This register specifies the number of bits to shift the input vector (in the +// range 0-31) during a Rshift or Lshift operation. +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 + +//***************************************************************************** +// +// Register: PKA_O_FUNCTION +// +//***************************************************************************** +// Field: [24] STALL_RESULT +// +// When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW +// registers, as well as resetting the run bit is stalled beyond the point that +// a running operation is actually finished. Use this to allow software enough +// time to read results from a previous operation when the newly started +// operation is known to take only a short amount of time. If a result is +// waiting, the result registers is updated and the run bit is reset in the +// clock cycle following writing the stall result bit back to 0b. The Stall +// result function may only be used for basic PKCP operations. +#define PKA_FUNCTION_STALL_RESULT 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_BITN 24 +#define PKA_FUNCTION_STALL_RESULT_M 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_S 24 + +// Field: [15] RUN +// +// The host sets this bit to instruct the PKA module to begin processing the +// basic PKCP or complex sequencer operation. This bit is reset low +// automatically when the operation is complete. +// After a reset, the run bit is always set to 1b. Depending on the option, +// program ROM or program RAM, the following applies: +// Program ROM - The first sequencer instruction sets the bit to 0b. This is +// done immediately after the hardware reset is released. +// Program RAM - The sequencer must set the bit to 0b. As a valid firmware may +// not have been loaded, the sequencer is held in software reset after the +// hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the +// FW image is loaded and the Reset bit is cleared, the sequencer starts to +// execute the FW. The first instruction clears the run bit. +// In both cases a few clock cycles are needed before the first instruction is +// executed and the run bit state has been propagated. +#define PKA_FUNCTION_RUN 0x00008000 +#define PKA_FUNCTION_RUN_BITN 15 +#define PKA_FUNCTION_RUN_M 0x00008000 +#define PKA_FUNCTION_RUN_S 15 + +// Field: [14:12] SEQUENCER_OPERATIONS +// +// These bits select the complex sequencer operation to perform: +// 0x0: None +// 0x1: ExpMod-CRT +// 0x2: ECmontMUL +// 0x3: ECC-ADD (if available in firmware, otherwise reserved) +// 0x4: ExpMod-ACT2 +// 0x5: ECC-MUL (if available in firmware, otherwise reserved) +// 0x6: ExpMod-variable +// 0x7: ModInv (if available in firmware, otherwise reserved) +// The encoding of these operations is determined by sequencer firmware. +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 + +// Field: [11] COPY +// +// Perform copy operation +#define PKA_FUNCTION_COPY 0x00000800 +#define PKA_FUNCTION_COPY_BITN 11 +#define PKA_FUNCTION_COPY_M 0x00000800 +#define PKA_FUNCTION_COPY_S 11 + +// Field: [10] COMPARE +// +// Perform compare operation +#define PKA_FUNCTION_COMPARE 0x00000400 +#define PKA_FUNCTION_COMPARE_BITN 10 +#define PKA_FUNCTION_COMPARE_M 0x00000400 +#define PKA_FUNCTION_COMPARE_S 10 + +// Field: [9] MODULO +// +// Perform modulo operation +#define PKA_FUNCTION_MODULO 0x00000200 +#define PKA_FUNCTION_MODULO_BITN 9 +#define PKA_FUNCTION_MODULO_M 0x00000200 +#define PKA_FUNCTION_MODULO_S 9 + +// Field: [8] DIVIDE +// +// Perform divide operation +#define PKA_FUNCTION_DIVIDE 0x00000100 +#define PKA_FUNCTION_DIVIDE_BITN 8 +#define PKA_FUNCTION_DIVIDE_M 0x00000100 +#define PKA_FUNCTION_DIVIDE_S 8 + +// Field: [7] LSHIFT +// +// Perform left shift operation +#define PKA_FUNCTION_LSHIFT 0x00000080 +#define PKA_FUNCTION_LSHIFT_BITN 7 +#define PKA_FUNCTION_LSHIFT_M 0x00000080 +#define PKA_FUNCTION_LSHIFT_S 7 + +// Field: [6] RSHIFT +// +// Perform right shift operation +#define PKA_FUNCTION_RSHIFT 0x00000040 +#define PKA_FUNCTION_RSHIFT_BITN 6 +#define PKA_FUNCTION_RSHIFT_M 0x00000040 +#define PKA_FUNCTION_RSHIFT_S 6 + +// Field: [5] SUBTRACT +// +// Perform subtract operation +#define PKA_FUNCTION_SUBTRACT 0x00000020 +#define PKA_FUNCTION_SUBTRACT_BITN 5 +#define PKA_FUNCTION_SUBTRACT_M 0x00000020 +#define PKA_FUNCTION_SUBTRACT_S 5 + +// Field: [4] ADD +// +// Perform add operation +#define PKA_FUNCTION_ADD 0x00000010 +#define PKA_FUNCTION_ADD_BITN 4 +#define PKA_FUNCTION_ADD_M 0x00000010 +#define PKA_FUNCTION_ADD_S 4 + +// Field: [3] MS_ONE +// +// Loads the location of the Most Significant one bit within the result word +// indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS +// register - can only be used with basic PKCP operations, except for Divide, +// Modulo and Compare. +#define PKA_FUNCTION_MS_ONE 0x00000008 +#define PKA_FUNCTION_MS_ONE_BITN 3 +#define PKA_FUNCTION_MS_ONE_M 0x00000008 +#define PKA_FUNCTION_MS_ONE_S 3 + +// Field: [1] ADDSUB +// +// Perform combined add/subtract operation +#define PKA_FUNCTION_ADDSUB 0x00000002 +#define PKA_FUNCTION_ADDSUB_BITN 1 +#define PKA_FUNCTION_ADDSUB_M 0x00000002 +#define PKA_FUNCTION_ADDSUB_S 1 + +// Field: [0] MULTIPLY +// +// Perform multiply operation +#define PKA_FUNCTION_MULTIPLY 0x00000001 +#define PKA_FUNCTION_MULTIPLY_BITN 0 +#define PKA_FUNCTION_MULTIPLY_M 0x00000001 +#define PKA_FUNCTION_MULTIPLY_S 0 + +//***************************************************************************** +// +// Register: PKA_O_COMPARE +// +//***************************************************************************** +// Field: [2] A_GREATER_THAN_B +// +// Vector_A is greater than Vector_B +#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 +#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_S 2 + +// Field: [1] A_LESS_THAN_B +// +// Vector_A is less than Vector_B +#define PKA_COMPARE_A_LESS_THAN_B 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_BITN 1 +#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_S 1 + +// Field: [0] A_EQUALS_B +// +// Vector_A is equal to Vector_B +#define PKA_COMPARE_A_EQUALS_B 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_BITN 0 +#define PKA_COMPARE_A_EQUALS_B_M 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_S 0 + +//***************************************************************************** +// +// Register: PKA_O_MSW +// +//***************************************************************************** +// Field: [15] RESULT_IS_ZERO +// +// The result vector is all zeroes, ignore the address returned in bits [10:0] +#define PKA_MSW_RESULT_IS_ZERO 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_BITN 15 +#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_S 15 + +// Field: [10:0] MSW_ADDRESS +// +// Address of the most-significant nonzero 32-bit word of the result vector in +// PKA RAM +#define PKA_MSW_MSW_ADDRESS_W 11 +#define PKA_MSW_MSW_ADDRESS_M 0x000007FF +#define PKA_MSW_MSW_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: PKA_O_DIVMSW +// +//***************************************************************************** +// Field: [15] RESULT_IS_ZERO +// +// The result vector is all zeroes, ignore the address returned in bits [10:0] +#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 +#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_S 15 + +// Field: [10:0] MSW_ADDRESS +// +// Address of the most significant nonzero 32-bit word of the remainder result +// vector in PKA RAM +#define PKA_DIVMSW_MSW_ADDRESS_W 11 +#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF +#define PKA_DIVMSW_MSW_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: PKA_O_SEQCTRL +// +//***************************************************************************** +// Field: [31] RESET +// +// Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). +// Writing 1b resets the sequencer, write to 0b to restart operations again. As +// the reset value is 0b, the sequencer will automatically start operations +// executing from program ROM. This bit should always be written with zero and +// ignored when reading this register. +// +// Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When +// 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is +// accessible for loading the sequencer program (while the PKA_DATA_RAM is +// inaccessible), write to 0b to (re)start sequencer operations and disable +// PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). +// Resetting the sequencer (in order to load other firmware) should only be +// done when the PKA Engine is not performing any operations (i.e. the +// FUNCTION.RUN bit should be zero). +#define PKA_SEQCTRL_RESET 0x80000000 +#define PKA_SEQCTRL_RESET_BITN 31 +#define PKA_SEQCTRL_RESET_M 0x80000000 +#define PKA_SEQCTRL_RESET_S 31 + +// Field: [15:8] SEQUENCER_STAT +// +// These read-only bits can be used by the sequencer to communicate status to +// the outside world. Bit [8] is also used as sequencer interrupt, with the +// complement of this bit ORed into the FUNCTION.RUN bit. This field should +// always be written with zeroes and ignored when reading this register. +#define PKA_SEQCTRL_SEQUENCER_STAT_W 8 +#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 +#define PKA_SEQCTRL_SEQUENCER_STAT_S 8 + +// Field: [7:0] SW_CONTROL_STAT +// +// These bits can be used by software to trigger sequencer operations. External +// logic can set these bits by writing 1b, cannot reset them by writing 0b. The +// sequencer can reset these bits by writing 0b, cannot set them by writing 1b. +// Setting the FUNCTION.RUN bit together with a nonzero sequencer operations +// field automatically sets bit [0] here. This field should always be written +// with zeroes and ignored when reading this register. +#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 +#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF +#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 + +//***************************************************************************** +// +// Register: PKA_O_OPTIONS +// +//***************************************************************************** +// Field: [11] INT_MASKING +// +// Interrupt Masking +// 0x0: indicates that the main interrupt output (bit [1] of the interrupts +// output bus) is the direct complement of the run bit in the PKA_CONTROL +// register, 0x1 : indicates +// that interrupt masking logic is present for this output. +// Note: Reset value is undefined +#define PKA_OPTIONS_INT_MASKING 0x00000800 +#define PKA_OPTIONS_INT_MASKING_BITN 11 +#define PKA_OPTIONS_INT_MASKING_M 0x00000800 +#define PKA_OPTIONS_INT_MASKING_S 11 + +// Field: [10:8] PROTECTION_OPTION +// +// Protection Option +// 0x0: indicates no additional protection against side channel attacks, +// +// 0x1: indicates the SCAP option +// 0x2: Reserved +// 0x3: indicates the PROT option; +// Note: Reset value is undefined +#define PKA_OPTIONS_PROTECTION_OPTION_W 3 +#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 +#define PKA_OPTIONS_PROTECTION_OPTION_S 8 + +// Field: [7] PROGRAM_RAM +// +// Program RAM +// 0x1: indicates sequencer program storage in RAM, 0x0: +// indicates sequencer program storage in ROM. +// Note: Reset value is undefined +#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_BITN 7 +#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_S 7 + +// Field: [6:5] SEQUENCER_CONFIGURATION +// +// Sequencer Configuration +// 0x0: Reserved +// 0x1 : Indicates a standard sequencer +// 0x2: Reserved +// 0x3: Reserved +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 + +// Field: [1:0] PKCP_CONFIGURATION +// +// PKCP Configuration 0x0 +// : Reserved +// 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: +// indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved +// Note: Reset value is undefined. +#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 +#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 +#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 + +//***************************************************************************** +// +// Register: PKA_O_FWREV +// +//***************************************************************************** +// Field: [31:28] FW_CAPABILITIES +// +// Firmware Capabilities +// +// 4-bit binary encoding for the functionality implemented +// in the firmware. +// 0x0: indicates basic ModExp with/without CRT. 0x1: +// adds Modular Inversion, 0x2: value +// 2 adds Modular Inversion and ECC operations. +// 0x3-0xF : Reserved. +#define PKA_FWREV_FW_CAPABILITIES_W 4 +#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 +#define PKA_FWREV_FW_CAPABILITIES_S 28 + +// Field: [27:24] MAJOR_FW_REVISION +// +// 4-bit binary encoding of the major firmware revision number +#define PKA_FWREV_MAJOR_FW_REVISION_W 4 +#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 +#define PKA_FWREV_MAJOR_FW_REVISION_S 24 + +// Field: [23:20] MINOR_FW_REVISION +// +// 4-bit binary encoding of the minor firmware revision number +#define PKA_FWREV_MINOR_FW_REVISION_W 4 +#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 +#define PKA_FWREV_MINOR_FW_REVISION_S 20 + +// Field: [19:16] FW_PATCH_LEVEL +// +// 4-bit binary encoding of the firmware patch level, initial release will +// carry value zero +// Patches are used to remove bugs without changing the functionality or +// interface of a module. +#define PKA_FWREV_FW_PATCH_LEVEL_W 4 +#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 +#define PKA_FWREV_FW_PATCH_LEVEL_S 16 + +//***************************************************************************** +// +// Register: PKA_O_HWREV +// +//***************************************************************************** +// Field: [27:24] MAJOR_HW_REVISION +// +// 4-bit binary encoding of the major hardware revision number +#define PKA_HWREV_MAJOR_HW_REVISION_W 4 +#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 +#define PKA_HWREV_MAJOR_HW_REVISION_S 24 + +// Field: [23:20] MINOR_HW_REVISION +// +// 4-bit binary encoding of the minor hardware revision number +#define PKA_HWREV_MINOR_HW_REVISION_W 4 +#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 +#define PKA_HWREV_MINOR_HW_REVISION_S 20 + +// Field: [19:16] HW_PATCH_LEVEL +// +// 4-bit binary encoding of the hardware patch level, initial release will +// carry value zero +// Patches are used to remove bugs without changing the functionality or +// interface of a module. +#define PKA_HWREV_HW_PATCH_LEVEL_W 4 +#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 +#define PKA_HWREV_HW_PATCH_LEVEL_S 16 + +// Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER +// +// Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 + +// Field: [7:0] BASIC_EIP_NUMBER +// +// 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C +#define PKA_HWREV_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF +#define PKA_HWREV_BASIC_EIP_NUMBER_S 0 + + +#endif // __PKA__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_int.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_int.h new file mode 100644 index 00000000..ae5935c8 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_int.h @@ -0,0 +1,157 @@ +/****************************************************************************** +* Filename: hw_pka_int_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_INT_H__ +#define __HW_PKA_INT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PKA_INT component +// +//***************************************************************************** +// PKA Options register +#define PKA_INT_O_OPTIONS 0x00000FF8 + +// PKA hardware revision register +#define PKA_INT_O_REVISION 0x00000FFC + +//***************************************************************************** +// +// Register: PKA_INT_O_OPTIONS +// +//***************************************************************************** +// Field: [10] AIC_PRESENT +// +// When set to '1', indicates that an EIP201 AIC is included in the EIP150 +#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 +#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_S 10 + +// Field: [9] EIP76_PRESENT +// +// When set to '1', indicates that the EIP76 TRNG is included in the EIP150 +#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 +#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 + +// Field: [8] EIP28_PRESENT +// +// When set to '1', indicates that the EIP28 PKA is included in the EIP150 +#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 +#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 + +// Field: [3] AXI_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a AXI interface +#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 +#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 + +// Field: [2] AHB_IS_ASYNC +// +// When set to '1', indicates that AHB interface is asynchronous Only +// applicable when AHB_INTERFACE is 1 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 + +// Field: [1] AHB_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a AHB interface +#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 +#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 + +// Field: [0] PLB_INTERFACE +// +// When set to '1', indicates that the EIP150 is equipped with a PLB interface +#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 +#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 + +//***************************************************************************** +// +// Register: PKA_INT_O_REVISION +// +//***************************************************************************** +// Field: [27:24] MAJOR_REVISION +// +// These bits encode the major version number for this module +#define PKA_INT_REVISION_MAJOR_REVISION_W 4 +#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 +#define PKA_INT_REVISION_MAJOR_REVISION_S 24 + +// Field: [23:20] MINOR_REVISION +// +// These bits encode the minor version number for this module +#define PKA_INT_REVISION_MINOR_REVISION_W 4 +#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 +#define PKA_INT_REVISION_MINOR_REVISION_S 20 + +// Field: [19:16] PATCH_LEVEL +// +// These bits encode the hardware patch level for this module they start at +// value 0 on the first release +#define PKA_INT_REVISION_PATCH_LEVEL_W 4 +#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 +#define PKA_INT_REVISION_PATCH_LEVEL_S 16 + +// Field: [15:8] COMP_EIP_NUM +// +// These bits simply contain the complement of bits [7:0], used by a driver to +// ascertain that the EIP150 revision register is indeed read +#define PKA_INT_REVISION_COMP_EIP_NUM_W 8 +#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 +#define PKA_INT_REVISION_COMP_EIP_NUM_S 8 + +// Field: [7:0] EIP_NUM +// +// These bits encode the AuthenTec EIP number for the EIP150 +#define PKA_INT_REVISION_EIP_NUM_W 8 +#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF +#define PKA_INT_REVISION_EIP_NUM_S 0 + + +#endif // __PKA_INT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_ram.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_ram.h new file mode 100644 index 00000000..65cf6b27 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_pka_ram.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* Filename: hw_pka_ram_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PKA_RAM_H__ +#define __HW_PKA_RAM_H__ + + +#define PKA_RAM_O_BANK0 0x00000000 +#define PKA_RAM_BANK0_BYTE_SIZE 2048 + +#define PKA_RAM_TOT_BYTE_SIZE 2048 + + + +#endif // __HW_PKA_RAM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_prcm.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_prcm.h new file mode 100644 index 00000000..1b8dd558 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_prcm.h @@ -0,0 +1,2525 @@ +/****************************************************************************** +* Filename: hw_prcm_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_PRCM_H__ +#define __HW_PRCM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// PRCM component +// +//***************************************************************************** +// Infrastructure Clock Division Factor For Run Mode +#define PRCM_O_INFRCLKDIVR 0x00000000 + +// Infrastructure Clock Division Factor For Sleep Mode +#define PRCM_O_INFRCLKDIVS 0x00000004 + +// Infrastructure Clock Division Factor For DeepSleep Mode +#define PRCM_O_INFRCLKDIVDS 0x00000008 + +// MCU Voltage Domain Control +#define PRCM_O_VDCTL 0x0000000C + +// Load PRCM Settings To CLKCTRL Power Domain +#define PRCM_O_CLKLOADCTL 0x00000028 + +// RFC Clock Gate +#define PRCM_O_RFCCLKG 0x0000002C + +// VIMS Clock Gate +#define PRCM_O_VIMSCLKG 0x00000030 + +// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes +#define PRCM_O_SECDMACLKGR 0x0000003C + +// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode +#define PRCM_O_SECDMACLKGS 0x00000040 + +// SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode +#define PRCM_O_SECDMACLKGDS 0x00000044 + +// GPIO Clock Gate For Run And All Modes +#define PRCM_O_GPIOCLKGR 0x00000048 + +// GPIO Clock Gate For Sleep Mode +#define PRCM_O_GPIOCLKGS 0x0000004C + +// GPIO Clock Gate For Deep Sleep Mode +#define PRCM_O_GPIOCLKGDS 0x00000050 + +// GPT Clock Gate For Run And All Modes +#define PRCM_O_GPTCLKGR 0x00000054 + +// GPT Clock Gate For Sleep Mode +#define PRCM_O_GPTCLKGS 0x00000058 + +// GPT Clock Gate For Deep Sleep Mode +#define PRCM_O_GPTCLKGDS 0x0000005C + +// I2C Clock Gate For Run And All Modes +#define PRCM_O_I2CCLKGR 0x00000060 + +// I2C Clock Gate For Sleep Mode +#define PRCM_O_I2CCLKGS 0x00000064 + +// I2C Clock Gate For Deep Sleep Mode +#define PRCM_O_I2CCLKGDS 0x00000068 + +// UART Clock Gate For Run And All Modes +#define PRCM_O_UARTCLKGR 0x0000006C + +// UART Clock Gate For Sleep Mode +#define PRCM_O_UARTCLKGS 0x00000070 + +// UART Clock Gate For Deep Sleep Mode +#define PRCM_O_UARTCLKGDS 0x00000074 + +// SSI Clock Gate For Run And All Modes +#define PRCM_O_SSICLKGR 0x00000078 + +// SSI Clock Gate For Sleep Mode +#define PRCM_O_SSICLKGS 0x0000007C + +// SSI Clock Gate For Deep Sleep Mode +#define PRCM_O_SSICLKGDS 0x00000080 + +// I2S Clock Gate For Run And All Modes +#define PRCM_O_I2SCLKGR 0x00000084 + +// I2S Clock Gate For Sleep Mode +#define PRCM_O_I2SCLKGS 0x00000088 + +// I2S Clock Gate For Deep Sleep Mode +#define PRCM_O_I2SCLKGDS 0x0000008C + +// Internal +#define PRCM_O_SYSBUSCLKDIV 0x000000B4 + +// Internal +#define PRCM_O_CPUCLKDIV 0x000000B8 + +// Internal +#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC + +// Internal +#define PRCM_O_PERDMACLKDIV 0x000000C4 + +// I2S Clock Control +#define PRCM_O_I2SBCLKSEL 0x000000C8 + +// GPT Scalar +#define PRCM_O_GPTCLKDIV 0x000000CC + +// I2S Clock Control +#define PRCM_O_I2SCLKCTL 0x000000D0 + +// MCLK Division Ratio +#define PRCM_O_I2SMCLKDIV 0x000000D4 + +// BCLK Division Ratio +#define PRCM_O_I2SBCLKDIV 0x000000D8 + +// WCLK Division Ratio +#define PRCM_O_I2SWCLKDIV 0x000000DC + +// RESET For SEC (PKA And TRNG And CRYPTO) And UDMA +#define PRCM_O_RESETSECDMA 0x000000F0 + +// RESET For GPIO IPs +#define PRCM_O_RESETGPIO 0x000000F4 + +// RESET For GPT Ips +#define PRCM_O_RESETGPT 0x000000F8 + +// RESET For I2C IPs +#define PRCM_O_RESETI2C 0x000000FC + +// RESET For UART IPs +#define PRCM_O_RESETUART 0x00000100 + +// RESET For SSI IPs +#define PRCM_O_RESETSSI 0x00000104 + +// RESET For I2S IP +#define PRCM_O_RESETI2S 0x00000108 + +// Power Domain Control +#define PRCM_O_PDCTL0 0x0000012C + +// RFC Power Domain Control +#define PRCM_O_PDCTL0RFC 0x00000130 + +// SERIAL Power Domain Control +#define PRCM_O_PDCTL0SERIAL 0x00000134 + +// PERIPH Power Domain Control +#define PRCM_O_PDCTL0PERIPH 0x00000138 + +// Power Domain Status +#define PRCM_O_PDSTAT0 0x00000140 + +// RFC Power Domain Status +#define PRCM_O_PDSTAT0RFC 0x00000144 + +// SERIAL Power Domain Status +#define PRCM_O_PDSTAT0SERIAL 0x00000148 + +// PERIPH Power Domain Status +#define PRCM_O_PDSTAT0PERIPH 0x0000014C + +// Power Domain Control +#define PRCM_O_PDCTL1 0x0000017C + +// CPU Power Domain Direct Control +#define PRCM_O_PDCTL1CPU 0x00000184 + +// RFC Power Domain Direct Control +#define PRCM_O_PDCTL1RFC 0x00000188 + +// VIMS Mode Direct Control +#define PRCM_O_PDCTL1VIMS 0x0000018C + +// Power Manager Status +#define PRCM_O_PDSTAT1 0x00000194 + +// BUS Power Domain Direct Read Status +#define PRCM_O_PDSTAT1BUS 0x00000198 + +// RFC Power Domain Direct Read Status +#define PRCM_O_PDSTAT1RFC 0x0000019C + +// CPU Power Domain Direct Read Status +#define PRCM_O_PDSTAT1CPU 0x000001A0 + +// VIMS Mode Direct Read Status +#define PRCM_O_PDSTAT1VIMS 0x000001A4 + +// Control To RFC +#define PRCM_O_RFCBITS 0x000001CC + +// Selected RFC Mode +#define PRCM_O_RFCMODESEL 0x000001D0 + +// Allowed RFC Modes +#define PRCM_O_RFCMODEHWOPT 0x000001D4 + +// Power Profiler Register +#define PRCM_O_PWRPROFSTAT 0x000001E0 + +// Memory Retention Control +#define PRCM_O_RAMRETEN 0x00000224 + +// Oscillator Interrupt Mask Control +#define PRCM_O_OSCIMSC 0x00000290 + +// Oscillator Raw Interrupt Status +#define PRCM_O_OSCRIS 0x00000294 + +// Oscillator Raw Interrupt Clear +#define PRCM_O_OSCICR 0x00000298 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVR +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in run mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in sleep mode. Division ratio affects both infrastructure clock and +// perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_INFRCLKDIVDS +// +//***************************************************************************** +// Field: [1:0] RATIO +// +// Division rate for clocks driving modules in the MCU_AON domain when system +// CPU is in seepsleep mode. Division ratio affects both infrastructure clock +// and perbusull clock. +// ENUMs: +// DIV32 Divide by 32 +// DIV8 Divide by 8 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_VDCTL +// +//***************************************************************************** +// Field: [0] ULDO +// +// Request PMCTL to switch to uLDO. +// +// 0: No request +// 1: Assert request when possible +// +// The bit will have no effect before the following requirements are met: +// 1. PDCTL1.CPU_ON = 0 +// 2. PDCTL1.VIMS_MODE = x0 +// 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and +// SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with +// CLKLOADCTL.LOAD) +// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 +// (Note: Settings must be loaded with CLKLOADCTL.LOAD) +// 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be +// loaded with CLKLOADCTL.LOAD) +// 6. RFC do no request access to BUS +// 7. System CPU in deepsleep +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_CLKLOADCTL +// +//***************************************************************************** +// Field: [1] LOAD_DONE +// +// Status of LOAD. +// Will be cleared to 0 when any of the registers requiring a LOAD is written +// to, and be set to 1 when a LOAD is done. +// Note that writing no change to a register will result in the LOAD_DONE being +// cleared. +// +// 0 : One or more registers have been write accessed after last LOAD +// 1 : No registers are write accessed after last LOAD +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 + +// Field: [0] LOAD +// +// +// 0: No action +// 1: Load settings to CLKCTRL. Bit is HW cleared. +// +// Multiple changes to settings may be done before LOAD is written once so all +// changes takes place at the same time. LOAD can also be done after single +// setting updates. +// +// Registers that needs to be followed by LOAD before settings being applied +// are: +// - SYSBUSCLKDIV +// - CPUCLKDIV +// - PERBUSCPUCLKDIV +// - PERDMACLKDIV +// - PERBUSCPUCLKG +// - RFCCLKG +// - VIMSCLKG +// - SECDMACLKGR +// - SECDMACLKGS +// - SECDMACLKGDS +// - GPIOCLKGR +// - GPIOCLKGS +// - GPIOCLKGDS +// - GPTCLKGR +// - GPTCLKGS +// - GPTCLKGDS +// - GPTCLKDIV +// - I2CCLKGR +// - I2CCLKGS +// - I2CCLKGDS +// - SSICLKGR +// - SSICLKGS +// - SSICLKGDS +// - UARTCLKGR +// - UARTCLKGS +// - UARTCLKGDS +// - I2SCLKGR +// - I2SCLKGS +// - I2SCLKGDS +// - I2SBCLKSEL +// - I2SCLKCTL +// - I2SMCLKDIV +// - I2SBCLKDIV +// - I2SWCLKDIV +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCCLKG +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable Clock +// 1: Enable clock if RFC power domain is on +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_VIMSCLKG +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// 00: Disable clock +// 01: Disable clock when SYSBUS clock is disabled +// 11: Enable clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGR +// +//***************************************************************************** +// Field: [24] DMA_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN +// when enabled. +// +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 + +// Field: [19] PKA_ZERIOZE_RESET_N +// +// Zeroization logic hardware reset. +// +// 0: pka_zeroize logic inactive. +// 1: pka_zeroize of memory is enabled. +// +// This register must remain active until the memory are completely zeroized +// which requires 256 periods on systembus clock. +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 + +// Field: [18] PKA_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN +// when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 + +// Field: [17] TRNG_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN +// when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 + +// Field: [16] CRYPTO_AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and +// SECDMACLKGDS.CRYPTO_CLK_EN when enabled. +// +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 + +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SECDMACLKGDS +// +//***************************************************************************** +// Field: [8] DMA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 + +// Field: [2] PKA_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 + +// Field: [1] TRNG_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 + +// Field: [0] CRYPTO_CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPIOCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPIOCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPIOCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGR +// +//***************************************************************************** +// Field: [11:8] AM_CLK_EN +// +// Each bit below has the following meaning: +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_GPT3 Enable clock for GPT3 in all modes +// AM_GPT2 Enable clock for GPT2 in all modes +// AM_GPT1 Enable clock for GPT1 in all modes +// AM_GPT0 Enable clock for GPT0 in all modes +#define PRCM_GPTCLKGR_AM_CLK_EN_W 4 +#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 +#define PRCM_GPTCLKGR_AM_CLK_EN_S 8 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 + +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPTCLKGR.AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKGDS +// +//***************************************************************************** +// Field: [3:0] CLK_EN +// +// Each bit below has the following meaning: +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by GPTCLKGR.AM_CLK_EN +// +// ENUMs can be combined +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// GPT3 Enable clock for GPT3 +// GPT2 Enable clock for GPT2 +// GPT1 Enable clock for GPT1 +// GPT0 Enable clock for GPT0 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2CCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2CCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2CCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGR +// +//***************************************************************************** +// Field: [9:8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGR_AM_CLK_EN_W 2 +#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_UARTCLKGR_AM_CLK_EN_S 8 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 + +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// UART1 Enable clock for UART1 +// UART0 Enable clock for UART0 +#define PRCM_UARTCLKGR_CLK_EN_W 2 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGR_CLK_EN_S 0 +#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 +#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by UARTCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGS_CLK_EN_W 2 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGS_CLK_EN_S 0 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_UARTCLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by UARTCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// AM_UART1 Enable clock for UART1 +// AM_UART0 Enable clock for UART0 +#define PRCM_UARTCLKGDS_CLK_EN_W 2 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGR +// +//***************************************************************************** +// Field: [9:8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_AM_CLK_EN_W 2 +#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_SSICLKGR_AM_CLK_EN_S 8 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 + +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SSICLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_SSICLKGDS +// +//***************************************************************************** +// Field: [1:0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by SSICLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +// ENUMs: +// SSI1 Enable clock for SSI1 +// SSI0 Enable clock for SSI0 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGR +// +//***************************************************************************** +// Field: [8] AM_CLK_EN +// +// +// 0: No force +// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) +// +// Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. +// SYSBUS clock will always run when enabled +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_S 8 + +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// Can be forced on by I2SCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKGDS +// +//***************************************************************************** +// Field: [0] CLK_EN +// +// +// 0: Disable clock +// 1: Enable clock +// +// SYSBUS clock will always run when enabled +// +// Can be forced on by I2SCLKGR.AM_CLK_EN +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_SYSBUSCLKDIV +// +//***************************************************************************** +// Field: [2:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_SYSBUSCLKDIV_RATIO_W 3 +#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 +#define PRCM_SYSBUSCLKDIV_RATIO_S 0 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_CPUCLKDIV +// +//***************************************************************************** +// Field: [0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_PERBUSCPUCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV256 Internal. Only to be used through TI provided API. +// DIV128 Internal. Only to be used through TI provided API. +// DIV64 Internal. Only to be used through TI provided API. +// DIV32 Internal. Only to be used through TI provided API. +// DIV16 Internal. Only to be used through TI provided API. +// DIV8 Internal. Only to be used through TI provided API. +// DIV4 Internal. Only to be used through TI provided API. +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 +#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F +#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_PERDMACLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Internal. Only to be used through TI provided API. +// ENUMs: +// DIV256 Internal. Only to be used through TI provided API. +// DIV128 Internal. Only to be used through TI provided API. +// DIV64 Internal. Only to be used through TI provided API. +// DIV32 Internal. Only to be used through TI provided API. +// DIV16 Internal. Only to be used through TI provided API. +// DIV8 Internal. Only to be used through TI provided API. +// DIV4 Internal. Only to be used through TI provided API. +// DIV2 Internal. Only to be used through TI provided API. +// DIV1 Internal. Only to be used through TI provided API. +#define PRCM_PERDMACLKDIV_RATIO_W 4 +#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F +#define PRCM_PERDMACLKDIV_RATIO_S 0 +#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKSEL +// +//***************************************************************************** +// Field: [0] SRC +// +// BCLK source selector +// +// 0: Use external BCLK +// 1: Use internally generated clock +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_GPTCLKDIV +// +//***************************************************************************** +// Field: [3:0] RATIO +// +// Scalar used for GPTs. The division rate will be constant and ungated for Run +// / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD +// needs to be written Other values are not supported. +// ENUMs: +// DIV256 Divide by 256 +// DIV128 Divide by 128 +// DIV64 Divide by 64 +// DIV32 Divide by 32 +// DIV16 Divide by 16 +// DIV8 Divide by 8 +// DIV4 Divide by 4 +// DIV2 Divide by 2 +// DIV1 Divide by 1 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_I2SCLKCTL +// +//***************************************************************************** +// Field: [3] SMPL_ON_POSEDGE +// +// On the I2S serial interface, data and WCLK is sampled and clocked out on +// opposite edges of BCLK. +// +// 0 - data and WCLK are sampled on the negative edge and clocked out on the +// positive edge. +// 1 - data and WCLK are sampled on the positive edge and clocked out on the +// negative edge. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 + +// Field: [2:1] WCLK_PHASE +// +// Decides how the WCLK division ratio is calculated and used to generate +// different duty cycles (See I2SWCLKDIV.WDIV). +// +// 0: Single phase +// 1: Dual phase +// 2: User Defined +// 3: Reserved/Undefined +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 + +// Field: [0] EN +// +// +// 0: MCLK, BCLK and WCLK will be static low +// 1: Enables the generation of MCLK, BCLK and WCLK +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SMCLKDIV +// +//***************************************************************************** +// Field: [9:0] MDIV +// +// An unsigned factor of the division ratio used to generate MCLK [2-1024]: +// +// MCLK = MCUCLK/MDIV[Hz] +// MCUCLK is 48MHz. +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If MDIV is odd the low phase of the clock is one MCUCLK period longer than +// the high phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SBCLKDIV +// +//***************************************************************************** +// Field: [9:0] BDIV +// +// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: +// +// BCLK = MCUCLK/BDIV[Hz] +// MCUCLK is 48MHz. +// +// A value of 0 is interpreted as 1024. +// A value of 1 is invalid. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock +// is one MCUCLK period longer than the high phase. +// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the +// clock is one MCUCLK period longer than the low phase. +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_I2SWCLKDIV +// +//***************************************************************************** +// Field: [15:0] WDIV +// +// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. +// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] +// MCUCLK is 48MHz. +// +// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. +// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK +// periods. +// +// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] +// +// If I2SCLKCTL.WCLK_PHASE = 2, User defined. +// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] +// (unsigned, [1-255]) BCLK periods. +// +// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] +// +// For changes to take effect, CLKLOADCTL.LOAD needs to be written +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETSECDMA +// +//***************************************************************************** +// Field: [8] DMA +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_DMA 0x00000100 +#define PRCM_RESETSECDMA_DMA_BITN 8 +#define PRCM_RESETSECDMA_DMA_M 0x00000100 +#define PRCM_RESETSECDMA_DMA_S 8 + +// Field: [2] PKA +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_PKA 0x00000004 +#define PRCM_RESETSECDMA_PKA_BITN 2 +#define PRCM_RESETSECDMA_PKA_M 0x00000004 +#define PRCM_RESETSECDMA_PKA_S 2 + +// Field: [1] TRNG +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_TRNG 0x00000002 +#define PRCM_RESETSECDMA_TRNG_BITN 1 +#define PRCM_RESETSECDMA_TRNG_M 0x00000002 +#define PRCM_RESETSECDMA_TRNG_S 1 + +// Field: [0] CRYPTO +// +// Write 1 to reset. HW cleared. +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSECDMA_CRYPTO 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_BITN 0 +#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETGPIO +// +//***************************************************************************** +// Field: [0] GPIO +// +// +// 0: No action +// 1: Reset GPIO. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETGPIO_GPIO 0x00000001 +#define PRCM_RESETGPIO_GPIO_BITN 0 +#define PRCM_RESETGPIO_GPIO_M 0x00000001 +#define PRCM_RESETGPIO_GPIO_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETGPT +// +//***************************************************************************** +// Field: [0] GPT +// +// +// 0: No action +// 1: Reset all GPTs. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETGPT_GPT 0x00000001 +#define PRCM_RESETGPT_GPT_BITN 0 +#define PRCM_RESETGPT_GPT_M 0x00000001 +#define PRCM_RESETGPT_GPT_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETI2C +// +//***************************************************************************** +// Field: [0] I2C +// +// +// 0: No action +// 1: Reset I2C. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETI2C_I2C 0x00000001 +#define PRCM_RESETI2C_I2C_BITN 0 +#define PRCM_RESETI2C_I2C_M 0x00000001 +#define PRCM_RESETI2C_I2C_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETUART +// +//***************************************************************************** +// Field: [1] UART1 +// +// +// 0: No action +// 1: Reset UART1. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETUART_UART1 0x00000002 +#define PRCM_RESETUART_UART1_BITN 1 +#define PRCM_RESETUART_UART1_M 0x00000002 +#define PRCM_RESETUART_UART1_S 1 + +// Field: [0] UART0 +// +// +// 0: No action +// 1: Reset UART0. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETUART_UART0 0x00000001 +#define PRCM_RESETUART_UART0_BITN 0 +#define PRCM_RESETUART_UART0_M 0x00000001 +#define PRCM_RESETUART_UART0_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETSSI +// +//***************************************************************************** +// Field: [1:0] SSI +// +// SSI 0: +// +// 0: No action +// 1: Reset SSI. HW cleared. +// +// Acess will only have effect when SERIAL power domain is on, +// PDSTAT0.SERIAL_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +// +// SSI 1: +// +// 0: No action +// 1: Reset SSI. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETSSI_SSI_W 2 +#define PRCM_RESETSSI_SSI_M 0x00000003 +#define PRCM_RESETSSI_SSI_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RESETI2S +// +//***************************************************************************** +// Field: [0] I2S +// +// +// 0: No action +// 1: Reset module. HW cleared. +// +// Acess will only have effect when PERIPH power domain is on, +// PDSTAT0.PERIPH_ON = 1 +// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not +// activated while executing from flash. This means one cannot execute from +// flash when using the SW reset. +#define PRCM_RESETI2S_I2S 0x00000001 +#define PRCM_RESETI2S_I2S_BITN 0 +#define PRCM_RESETI2S_I2S_M 0x00000001 +#define PRCM_RESETI2S_I2S_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: PERIPH power domain is powered down +// 1: PERIPH power domain is powered up +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: SERIAL power domain is powered down +// 1: SERIAL power domain is powered up +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// +// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 +// 1: RFC power domain powered on +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.RFC_ON +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.SERIAL_ON +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDCTL0.PERIPH_ON +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0 +// +//***************************************************************************** +// Field: [2] PERIPH_ON +// +// PERIPH Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 + +// Field: [1] SERIAL_ON +// +// SERIAL Power domain. +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 + +// Field: [0] RFC_ON +// +// RFC Power domain +// +// 0: Domain may be powered down +// 1: Domain powered up (guaranteed) +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0RFC +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.RFC_ON +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0SERIAL +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.SERIAL_ON +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT0PERIPH +// +//***************************************************************************** +// Field: [0] ON +// +// Alias for PDSTAT0.PERIPH_ON +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1 +// +//***************************************************************************** +// Field: [4:3] VIMS_MODE +// +// +// 00: VIMS power domain is only powered when CPU power domain is powered. +// 01: VIMS power domain is powered whenever the BUS power domain is powered. +// 1X: Block power up of VIMS power domain at next wake up. This mode only has +// effect when VIMS power domain is not powered. Used for Autonomous RF Core. +#define PRCM_PDCTL1_VIMS_MODE_W 2 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 +#define PRCM_PDCTL1_VIMS_MODE_S 3 + +// Field: [2] RFC_ON +// +// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power +// domain powered on Bit shall be used by RFC in autonomous mode but there is +// no HW restrictions fom system CPU to access the bit. +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: Causes a power down of the CPU power domain when system CPU indicates it +// is idle. +// 1: Initiates power-on of the CPU power domain. +// +// This bit is automatically set by a WIC power-on event. +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.CPU_ON +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDCTL1.RFC_ON +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDCTL1VIMS +// +//***************************************************************************** +// Field: [1:0] MODE +// +// This is an alias for PDCTL1.VIMS_MODE +#define PRCM_PDCTL1VIMS_MODE_W 2 +#define PRCM_PDCTL1VIMS_MODE_M 0x00000003 +#define PRCM_PDCTL1VIMS_MODE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1 +// +//***************************************************************************** +// Field: [4] BUS_ON +// +// +// 0: BUS domain not accessible +// 1: BUS domain is currently accessible +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 + +// Field: [3] VIMS_ON +// +// +// 0: VIMS domain not accessible +// 1: VIMS domain is currently accessible +#define PRCM_PDSTAT1_VIMS_ON 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_BITN 3 +#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_S 3 + +// Field: [2] RFC_ON +// +// +// 0: RFC domain not accessible +// 1: RFC domain is currently accessible +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 + +// Field: [1] CPU_ON +// +// +// 0: CPU and BUS domain not accessible +// 1: CPU and BUS domains are both currently accessible +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1BUS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.BUS_ON +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1RFC +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.RFC_ON +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1CPU +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.CPU_ON +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_PDSTAT1VIMS +// +//***************************************************************************** +// Field: [0] ON +// +// This is an alias for PDSTAT1.VIMS_ON +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCBITS +// +//***************************************************************************** +// Field: [31:0] READ +// +// Control bits for RFC. The RF core CPE processor will automatically check +// this register when it boots, and it can be used to immediately instruct CPE +// to perform some tasks at its start-up. The supported functionality is +// ROM-defined and may vary. See the technical reference manual for more +// details. +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODESEL +// +//***************************************************************************** +// Field: [2:0] CURR +// +// Selects the set of commands that the RFC will accept. Only modes permitted +// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for +// details. +// ENUMs: +// MODE7 Select Mode 7 +// MODE6 Select Mode 6 +// MODE5 Select Mode 5 +// MODE4 Select Mode 4 +// MODE3 Select Mode 3 +// MODE2 Select Mode 2 +// MODE1 Select Mode 1 +// MODE0 Select Mode 0 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 + +//***************************************************************************** +// +// Register: PRCM_O_RFCMODEHWOPT +// +//***************************************************************************** +// Field: [7:0] AVAIL +// +// Permitted RFC modes. More than one mode can be permitted. +// ENUMs: +// MODE7 Mode 7 permitted +// MODE6 Mode 6 permitted +// MODE5 Mode 5 permitted +// MODE4 Mode 4 permitted +// MODE3 Mode 3 permitted +// MODE2 Mode 2 permitted +// MODE1 Mode 1 permitted +// MODE0 Mode 0 permitted +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 + +//***************************************************************************** +// +// Register: PRCM_O_PWRPROFSTAT +// +//***************************************************************************** +// Field: [7:0] VALUE +// +// SW can use these bits to timestamp the application. These bits are also +// available through the testtap and can thus be used by the emulator to +// profile in real time. +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_RAMRETEN +// +//***************************************************************************** +// Field: [3] RFCULL +// +// 0: Retention for RFC ULL SRAM disabled +// 1: Retention for RFC ULL SRAM enabled +// +// Memories controlled: +// CPEULLRAM +#define PRCM_RAMRETEN_RFCULL 0x00000008 +#define PRCM_RAMRETEN_RFCULL_BITN 3 +#define PRCM_RAMRETEN_RFCULL_M 0x00000008 +#define PRCM_RAMRETEN_RFCULL_S 3 + +// Field: [2] RFC +// +// 0: Retention for RFC SRAM disabled +// 1: Retention for RFC SRAM enabled +// +// Memories controlled: CPERAM MCERAM RFERAM DSBRAM +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 + +// Field: [1:0] VIMS +// +// +// 0: Memory retention disabled +// 1: Memory retention enabled +// +// Bit 0: VIMS_TRAM +// Bit 1: VIMS_CRAM +// +// Legal modes depend on settings in VIMS:CTL.MODE +// +// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to +// CACHE or SPLIT mode after waking up again +// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in +// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE +// or SPILT mode. +// 10: Illegal mode +// 11: No restrictions +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCIMSC +// +//***************************************************************************** +// Field: [7] HFSRCPENDIM +// +// 0: Disable interrupt generation when HFSRCPEND is qualified +// 1: Enable interrupt generation when HFSRCPEND is qualified +#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 +#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_S 7 + +// Field: [6] LFSRCDONEIM +// +// 0: Disable interrupt generation when LFSRCDONE is qualified +// 1: Enable interrupt generation when LFSRCDONE is qualified +#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 +#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_S 6 + +// Field: [5] XOSCDLFIM +// +// 0: Disable interrupt generation when XOSCDLF is qualified +// 1: Enable interrupt generation when XOSCDLF is qualified +#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 +#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_S 5 + +// Field: [4] XOSCLFIM +// +// 0: Disable interrupt generation when XOSCLF is qualified +// 1: Enable interrupt generation when XOSCLF is qualified +#define PRCM_OSCIMSC_XOSCLFIM 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_BITN 4 +#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_S 4 + +// Field: [3] RCOSCDLFIM +// +// 0: Disable interrupt generation when RCOSCDLF is qualified +// 1: Enable interrupt generation when RCOSCDLF is qualified +#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 +#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_S 3 + +// Field: [2] RCOSCLFIM +// +// 0: Disable interrupt generation when RCOSCLF is qualified +// 1: Enable interrupt generation when RCOSCLF is qualified +#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 +#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_S 2 + +// Field: [1] XOSCHFIM +// +// 0: Disable interrupt generation when XOSCHF is qualified +// 1: Enable interrupt generation when XOSCHF is qualified +#define PRCM_OSCIMSC_XOSCHFIM 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_BITN 1 +#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_S 1 + +// Field: [0] RCOSCHFIM +// +// 0: Disable interrupt generation when RCOSCHF is qualified +// 1: Enable interrupt generation when RCOSCHF is qualified +#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 +#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCRIS +// +//***************************************************************************** +// Field: [7] HFSRCPENDRIS +// +// SCLK_HF source switch pending interrupt. +// +// After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source +// change request, then the requested SCLK_HF source will be enabled and +// qualified. When the new source is ready to be used as a clock source, then +// the interrupt HSSRCPENDRIS will go high. When the Flash allows SCLK_HF +// source switching to take place after flash memory read access is disabled. +// At this time the actual SCLK_HF clock source switch will be performed, and +// the interrupt status HSSRCPENDRIS will go low. +// +// 0: Indicates SCLK_HF source is not ready to be switched +// 1: Indicates SCLK_HF source is ready to be switched +// +// Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.HFSRCPENDC +#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 +#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_S 7 + +// Field: [6] LFSRCDONERIS +// +// SCLK_LF source switch done. +// +// The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that +// the SCLK_LF source shall be changed. After an SCLK_LF clock source change is +// requested, the new source may need to be enabled and qualified before +// switching of clock source can be done. The interrupt LFRSRCDONERIS goes high +// to indicate that the SCLK_LF clock source switching has been performed. +// LFRSRCDONERIS will go low again when the next clock source change is +// requested by writing to DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL . +// +// 0: Indicates SCLK_LF source switch has not completed +// 1: Indicates SCLK_LF source switch has completed +// +// Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.LFSRCDONEC +#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 +#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_S 6 + +// Field: [5] XOSCDLFRIS +// +// The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to +// be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. +// When XOSCDLFRIS is high, XOSC_HF will be used as source for SCLK_LF when +// selected. When none of the system clocks have XOSC_HF selected as clock +// source, the XOSC_HF source is automatically disabled and the XOSCDLFRIS +// interrupt status will go low. +// +// 0: XOSCDLF has not been qualified +// 1: XOSCDLF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCDLFC +#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 +#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_S 5 + +// Field: [4] XOSCLFRIS +// +// The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator +// has been qualified with respect to frequency. The XOSCLFRIS interrupt status +// goes high when the XOSC_LF oscillator is ready to be used as a clock source. +// After the clock qualification is successful, XOSCLFRIS interrupt status +// remains high, and further qualification is turned off until the XOSC_LF +// oscillator is disabled. XOSCLFRIS interrupt status will go low only at +// initial power-on, or after the XOSC_LF oscillator has been disabled when +// being deselected as a clock source. +// +// 0: XOSCLF has not been qualified +// 1: XOSCLF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCLFC +#define PRCM_OSCRIS_XOSCLFRIS 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_BITN 4 +#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_S 4 + +// Field: [3] RCOSCDLFRIS +// +// The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to +// be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. +// When RCOSCDLFRIS is high, RCOSC_HF will be used as source for SCLK_LF when +// selected. When none of the system clocks have RCOSC_HF selected as clock +// source, the RCOSC_HF source is automatically disabled and the RCOSCDLFRIS +// interrupt status will go low. +// If the SCLK_LF or ACLK_REF source is changed from RCOSC_HF derived to +// XOSC_HF derived low-frequency clock and the new source has not been +// qualified, then the clock will remain running on the original source. The +// RCOSCDLFRIS interrupt will then remain high. +// +// 0: RCOSCDLF has not been qualified +// 1: RCOSCDLF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order +// of qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCDLFC +#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 +#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_S 3 + +// Field: [2] RCOSCLFRIS +// +// The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF +// oscillator has been qualified with respect to frequency. The RCOSCLFRIS +// interrupt status goes high when the RCOSC_LF oscillator is ready to be used +// as a clock source. +// After the clock qualification is successful, RCOSCLFRIS interrupt status +// remains high, and further qualification is turned off until the RCOSC_LF +// oscillator is disabled. RCOSCLFRIS interrupt status will go low only at +// initial power-on, or after the RCOSC_LF oscillator has been disabled when +// being deselected as a clock source. +// +// 0: RCOSCLF has not been qualified +// 1: RCOSCLF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCLFC +#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 +#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_S 2 + +// Field: [1] XOSCHFRIS +// +// The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been +// qualified for use as a clock source. XOSCHFRIS is also used in TCXO mode +// (when DDI_0_OSC:XOSCHFCTL.TCXO_MODE is 1). +// When the XOSCHFRIS interrupt is high, the oscillator is qualified and will +// be used as a clock source when selected. The XOSCHFRIS interrupt goes low +// when the oscillator is disabled after being deselected as a clock source. +// +// +// 0: XOSC_HF has not been qualified +// 1: XOSC_HF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.XOSCHFC +#define PRCM_OSCRIS_XOSCHFRIS 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_BITN 1 +#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_S 1 + +// Field: [0] RCOSCHFRIS +// +// The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been +// qualified for use as a clock source When the RCOSCHFRIS interrupt is high, +// the oscillator is qualified and will be used as a clock source when +// selected. The RCOSCHFRIS interrupt goes low when the oscillator is disabled +// after being deselected as a clock source. +// +// 0: RCOSC_HF has not been qualified +// 1: RCOSC_HF has been qualified +// +// Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of +// qualifying raw interrupt and enable of interrupt mask is indifferent for +// generating an OSC Interrupt. +// +// Set by HW. Cleared by writing to OSCICR.RCOSCHFC +#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 +#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_S 0 + +//***************************************************************************** +// +// Register: PRCM_O_OSCICR +// +//***************************************************************************** +// Field: [7] HFSRCPENDC +// +// Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_HFSRCPENDC 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_BITN 7 +#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_S 7 + +// Field: [6] LFSRCDONEC +// +// Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_LFSRCDONEC 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_BITN 6 +#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_S 6 + +// Field: [5] XOSCDLFC +// +// Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCDLFC 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_BITN 5 +#define PRCM_OSCICR_XOSCDLFC_M 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_S 5 + +// Field: [4] XOSCLFC +// +// Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCLFC 0x00000010 +#define PRCM_OSCICR_XOSCLFC_BITN 4 +#define PRCM_OSCICR_XOSCLFC_M 0x00000010 +#define PRCM_OSCICR_XOSCLFC_S 4 + +// Field: [3] RCOSCDLFC +// +// Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCDLFC 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_BITN 3 +#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_S 3 + +// Field: [2] RCOSCLFC +// +// Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCLFC 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_BITN 2 +#define PRCM_OSCICR_RCOSCLFC_M 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_S 2 + +// Field: [1] XOSCHFC +// +// Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_XOSCHFC 0x00000002 +#define PRCM_OSCICR_XOSCHFC_BITN 1 +#define PRCM_OSCICR_XOSCHFC_M 0x00000002 +#define PRCM_OSCICR_XOSCHFC_S 1 + +// Field: [0] RCOSCHFC +// +// Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 +// has no effect. +#define PRCM_OSCICR_RCOSCHFC 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_BITN 0 +#define PRCM_OSCICR_RCOSCHFC_M 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_S 0 + + +#endif // __PRCM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_dbell.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_dbell.h new file mode 100644 index 00000000..6e8359e2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_dbell.h @@ -0,0 +1,1672 @@ +/****************************************************************************** +* Filename: hw_rfc_dbell_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_DBELL_H__ +#define __HW_RFC_DBELL_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_DBELL component +// +//***************************************************************************** +// Doorbell Command Register +#define RFC_DBELL_O_CMDR 0x00000000 + +// Doorbell Command Status Register +#define RFC_DBELL_O_CMDSTA 0x00000004 + +// Interrupt Flags From RF Hardware Modules +#define RFC_DBELL_O_RFHWIFG 0x00000008 + +// Interrupt Enable For RF Hardware Modules +#define RFC_DBELL_O_RFHWIEN 0x0000000C + +// Interrupt Flags For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIFG 0x00000010 + +// Interrupt Enable For Command and Packet Engine Generated Interrupts +#define RFC_DBELL_O_RFCPEIEN 0x00000014 + +// Interrupt Vector Selection For Command and Packet Engine Generated +// Interrupts +#define RFC_DBELL_O_RFCPEISL 0x00000018 + +// Doorbell Command Acknowledgement Interrupt Flag +#define RFC_DBELL_O_RFACKIFG 0x0000001C + +// RF Core General Purpose Output Control +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDR +// +//***************************************************************************** +// Field: [31:0] CMD +// +// Command register. Raises an interrupt to the Command and packet engine (CPE) +// upon write. +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_CMDSTA +// +//***************************************************************************** +// Field: [31:0] STAT +// +// Status of the last command used +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIFG +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// RF engine command done interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Modem software defined interrupt flag. Write zero to clear flag. Write to +// one has no effect. +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has +// no effect. +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Modem command done interrupt flag. Write zero to clear flag. Write to one +// has no effect. +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Frequency synthesizer calibration accelerator interrupt flag. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFHWIEN +// +//***************************************************************************** +// Field: [19] RATCH7 +// +// Interrupt enable for RFHWIFG.RATCH7. +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 + +// Field: [18] RATCH6 +// +// Interrupt enable for RFHWIFG.RATCH6. +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 + +// Field: [17] RATCH5 +// +// Interrupt enable for RFHWIFG.RATCH5. +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 + +// Field: [16] RATCH4 +// +// Interrupt enable for RFHWIFG.RATCH4. +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 + +// Field: [15] RATCH3 +// +// Interrupt enable for RFHWIFG.RATCH3. +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 + +// Field: [14] RATCH2 +// +// Interrupt enable for RFHWIFG.RATCH2. +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 + +// Field: [13] RATCH1 +// +// Interrupt enable for RFHWIFG.RATCH1. +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 + +// Field: [12] RATCH0 +// +// Interrupt enable for RFHWIFG.RATCH0. +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 + +// Field: [11] RFESOFT2 +// +// Interrupt enable for RFHWIFG.RFESOFT2. +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 + +// Field: [10] RFESOFT1 +// +// Interrupt enable for RFHWIFG.RFESOFT1. +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 + +// Field: [9] RFESOFT0 +// +// Interrupt enable for RFHWIFG.RFESOFT0. +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 + +// Field: [8] RFEDONE +// +// Interrupt enable for RFHWIFG.RFEDONE. +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 + +// Field: [6] TRCTK +// +// Interrupt enable for RFHWIFG.TRCTK. +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 + +// Field: [5] MDMSOFT +// +// Interrupt enable for RFHWIFG.MDMSOFT. +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 + +// Field: [4] MDMOUT +// +// Interrupt enable for RFHWIFG.MDMOUT. +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 + +// Field: [3] MDMIN +// +// Interrupt enable for RFHWIFG.MDMIN. +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 + +// Field: [2] MDMDONE +// +// Interrupt enable for RFHWIFG.MDMDONE. +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 + +// Field: [1] FSCA +// +// Interrupt enable for RFHWIFG.FSCA. +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIFG +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt flag 31. The command and packet engine (CPE) has observed an +// unexpected error. A reset of the CPE is needed. This can be done by +// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt flag 30. The command and packet engine (CPE) boot is finished. +// Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt flag 29. As part of command and packet engine (CPE) boot process, +// it has opened access to RF Core modules and memories. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt flag 28. The phase-locked loop in frequency synthesizer has +// reported loss of lock. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt flag 26. Packet reception stopped before packet was done. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt flag 25. Specified number of bytes written to partial read Rx +// buffer. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt flag 23. Rx queue data entry changing state to finished. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: +// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame +// received that did not fit in the Rx queue. Write zero to clear flag. Write +// to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, +// not to be ignored, then acknowledgement sent. Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, +// not to be ignored. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be +// ignored, no payload. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet +// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received +// with ignore flag set. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received +// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with +// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received +// with CRC OK. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 + +// Field: [13] FG_COMMAND_STARTED +// +// Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation +// command has gone into active state. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 + +// Field: [12] COMMAND_STARTED +// +// Interrupt flag 12. A radio operation command has gone into active state. +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt flag 11. BLE mode only: A buffer change is complete after +// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted +// LL control packet, and acknowledgement transmitted for that packet. Write +// zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL +// control packet. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted +// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to +// clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been +// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero +// to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio +// operation command in a chain of commands has finished. Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation +// command has finished. Write zero to clear flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt flag 1. The last radio operation command in a chain of commands +// has finished. (IEEE 802.15.4 mode: The last background level radio operation +// command in a chain of commands has finished.) Write zero to clear flag. +// Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A +// background level radio operation command has finished.) Write zero to clear +// flag. Write to one has no effect. +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEIEN +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 + +// Field: [30] BOOT_DONE +// +// Interrupt enable for RFCPEIFG.BOOT_DONE. +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 + +// Field: [29] MODULES_UNLOCKED +// +// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 + +// Field: [28] SYNTH_NO_LOCK +// +// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 + +// Field: [27] IRQ27 +// +// Interrupt enable for RFCPEIFG.IRQ27. +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 + +// Field: [26] RX_ABORTED +// +// Interrupt enable for RFCPEIFG.RX_ABORTED. +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 + +// Field: [24] RX_DATA_WRITTEN +// +// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 + +// Field: [23] RX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 + +// Field: [22] RX_BUF_FULL +// +// Interrupt enable for RFCPEIFG.RX_BUF_FULL. +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 + +// Field: [21] RX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 + +// Field: [20] RX_CTRL +// +// Interrupt enable for RFCPEIFG.RX_CTRL. +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 + +// Field: [19] RX_EMPTY +// +// Interrupt enable for RFCPEIFG.RX_EMPTY. +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 + +// Field: [18] RX_IGNORED +// +// Interrupt enable for RFCPEIFG.RX_IGNORED. +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 + +// Field: [17] RX_NOK +// +// Interrupt enable for RFCPEIFG.RX_NOK. +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 + +// Field: [16] RX_OK +// +// Interrupt enable for RFCPEIFG.RX_OK. +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 + +// Field: [15] IRQ15 +// +// Interrupt enable for RFCPEIFG.IRQ15. +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 + +// Field: [14] IRQ14 +// +// Interrupt enable for RFCPEIFG.IRQ14. +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 + +// Field: [13] FG_COMMAND_STARTED +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 + +// Field: [12] COMMAND_STARTED +// +// Interrupt enable for RFCPEIFG.COMMAND_STARTED. +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 + +// Field: [11] TX_BUFFER_CHANGED +// +// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 + +// Field: [10] TX_ENTRY_DONE +// +// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 + +// Field: [9] TX_RETRANS +// +// Interrupt enable for RFCPEIFG.TX_RETRANS. +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 + +// Field: [7] TX_CTRL_ACK +// +// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 + +// Field: [6] TX_CTRL +// +// Interrupt enable for RFCPEIFG.TX_CTRL. +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 + +// Field: [5] TX_ACK +// +// Interrupt enable for RFCPEIFG.TX_ACK. +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 + +// Field: [4] TX_DONE +// +// Interrupt enable for RFCPEIFG.TX_DONE. +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 + +// Field: [2] FG_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 + +// Field: [1] LAST_COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 + +// Field: [0] COMMAND_DONE +// +// Interrupt enable for RFCPEIFG.COMMAND_DONE. +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFCPEISL +// +//***************************************************************************** +// Field: [31] INTERNAL_ERROR +// +// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 + +// Field: [30] BOOT_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 + +// Field: [29] MODULES_UNLOCKED +// +// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 + +// Field: [28] SYNTH_NO_LOCK +// +// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 + +// Field: [27] IRQ27 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 + +// Field: [26] RX_ABORTED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 + +// Field: [25] RX_N_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [24] RX_DATA_WRITTEN +// +// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 + +// Field: [23] RX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [22] RX_BUF_FULL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 + +// Field: [21] RX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 + +// Field: [20] RX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 + +// Field: [19] RX_EMPTY +// +// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 + +// Field: [18] RX_IGNORED +// +// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 + +// Field: [17] RX_NOK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 + +// Field: [16] RX_OK +// +// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 + +// Field: [15] IRQ15 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 + +// Field: [14] IRQ14 +// +// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 + +// Field: [13] FG_COMMAND_STARTED +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 + +// Field: [12] COMMAND_STARTED +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 + +// Field: [11] TX_BUFFER_CHANGED +// +// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 + +// Field: [10] TX_ENTRY_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 + +// Field: [9] TX_RETRANS +// +// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 + +// Field: [8] TX_CTRL_ACK_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 + +// Field: [7] TX_CTRL_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 + +// Field: [6] TX_CTRL +// +// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 + +// Field: [5] TX_ACK +// +// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 + +// Field: [4] TX_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 + +// Field: [3] LAST_FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE +// interrupt should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [2] FG_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 + +// Field: [1] LAST_COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt +// should use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 + +// Field: [0] COMMAND_DONE +// +// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should +// use. +// ENUMs: +// CPE1 Associate this interrupt line with INT_RF_CPE1 +// interrupt vector +// CPE0 Associate this interrupt line with INT_RF_CPE0 +// interrupt vector +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_RFACKIFG +// +//***************************************************************************** +// Field: [0] ACKFLAG +// +// Interrupt flag for Command ACK +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 + +//***************************************************************************** +// +// Register: RFC_DBELL_O_SYSGPOCTL +// +//***************************************************************************** +// Field: [15:12] GPOCTL3 +// +// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO +// line 3. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 + +// Field: [11:8] GPOCTL2 +// +// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO +// line 2. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 + +// Field: [7:4] GPOCTL1 +// +// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO +// line 1. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 + +// Field: [3:0] GPOCTL0 +// +// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO +// line 0. +// ENUMs: +// RATGPO3 RAT GPO line 3 +// RATGPO2 RAT GPO line 2 +// RATGPO1 RAT GPO line 1 +// RATGPO0 RAT GPO line 0 +// RFEGPO3 RFE GPO line 3 +// RFEGPO2 RFE GPO line 2 +// RFEGPO1 RFE GPO line 1 +// RFEGPO0 RFE GPO line 0 +// MCEGPO3 MCE GPO line 3 +// MCEGPO2 MCE GPO line 2 +// MCEGPO1 MCE GPO line 1 +// MCEGPO0 MCE GPO line 0 +// CPEGPO3 CPE GPO line 3 +// CPEGPO2 CPE GPO line 2 +// CPEGPO1 CPE GPO line 1 +// CPEGPO0 CPE GPO line 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 + + +#endif // __RFC_DBELL__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_pwr.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_pwr.h new file mode 100644 index 00000000..e5e98c2d --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_pwr.h @@ -0,0 +1,153 @@ +/****************************************************************************** +* Filename: hw_rfc_pwr_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_PWR_H__ +#define __HW_RFC_PWR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_PWR component +// +//***************************************************************************** +// RF Core Power Management and Clock Enable +#define RFC_PWR_O_PWMCLKEN 0x00000000 + +//***************************************************************************** +// +// Register: RFC_PWR_O_PWMCLKEN +// +//***************************************************************************** +// Field: [10] RFCTRC +// +// Enable clock to the RF Core Tracer (RFCTRC) module. +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 + +// Field: [9] FSCA +// +// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) +// module. +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 + +// Field: [8] PHA +// +// Enable clock to the Packet Handling Accelerator (PHA) module. +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 + +// Field: [7] RAT +// +// Enable clock to the Radio Timer (RAT) module. +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 + +// Field: [6] RFERAM +// +// Enable clock to the RF Engine RAM module. +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 + +// Field: [5] RFE +// +// Enable clock to the RF Engine (RFE) module. +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 + +// Field: [4] MDMRAM +// +// Enable clock to the Modem RAM module. +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 + +// Field: [3] MDM +// +// Enable clock to the Modem (MDM) module. +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 + +// Field: [2] CPERAM +// +// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of +// RF Core initialization, set this bit together with CPE bit to enable CPE to +// boot. +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 + +// Field: [1] CPE +// +// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As +// part of RF Core initialization, set this bit together with CPERAM bit to +// enable CPE to boot. +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 + +// Field: [0] RFC +// +// Enable essential clocks for the RF Core interface. This includes the +// interconnect, the radio doorbell DBELL command interface, the power +// management (PWR) clock control module, and bus clock (sclk) for the CPE. To +// remove possibility of locking yourself out from the RF Core, this bit can +// not be cleared. If you need to disable all clocks to the RF Core, see the +// PRCM:RFCCLKG.CLK_EN register. +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 + + +#endif // __RFC_PWR__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_rat.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_rat.h new file mode 100644 index 00000000..8401caca --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_rat.h @@ -0,0 +1,198 @@ +/****************************************************************************** +* Filename: hw_rfc_rat_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_RAT_H__ +#define __HW_RFC_RAT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_RAT component +// +//***************************************************************************** +// Radio Timer Counter Value +#define RFC_RAT_O_RATCNT 0x00000004 + +// Timer Channel 0 Capture/Compare Register +#define RFC_RAT_O_RATCH0VAL 0x00000080 + +// Timer Channel 1 Capture/Compare Register +#define RFC_RAT_O_RATCH1VAL 0x00000084 + +// Timer Channel 2 Capture/Compare Register +#define RFC_RAT_O_RATCH2VAL 0x00000088 + +// Timer Channel 3 Capture/Compare Register +#define RFC_RAT_O_RATCH3VAL 0x0000008C + +// Timer Channel 4 Capture/Compare Register +#define RFC_RAT_O_RATCH4VAL 0x00000090 + +// Timer Channel 5 Capture/Compare Register +#define RFC_RAT_O_RATCH5VAL 0x00000094 + +// Timer Channel 6 Capture/Compare Register +#define RFC_RAT_O_RATCH6VAL 0x00000098 + +// Timer Channel 7 Capture/Compare Register +#define RFC_RAT_O_RATCH7VAL 0x0000009C + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCNT +// +//***************************************************************************** +// Field: [31:0] CNT +// +// Counter value. This is not writable while radio timer counter is enabled. +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH0VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH1VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH2VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH3VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH4VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH5VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH6VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 + +//***************************************************************************** +// +// Register: RFC_RAT_O_RATCH7VAL +// +//***************************************************************************** +// Field: [31:0] VAL +// +// Capture/compare value. Only writable when the channel is configured for +// compare mode. In compare mode, a write to this register will auto-arm the +// channel. +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 + + +#endif // __RFC_RAT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_ullram.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_ullram.h new file mode 100644 index 00000000..3804fb50 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_rfc_ullram.h @@ -0,0 +1,30767 @@ +/****************************************************************************** +* Filename: hw_rfc_ullram_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_RFC_ULLRAM_H__ +#define __HW_RFC_ULLRAM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// RFC_ULLRAM component +// +//***************************************************************************** +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK10 0x00000000 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11 0x00000004 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12 0x00000008 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK13 0x0000000C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK14 0x00000010 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK15 0x00000014 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK16 0x00000018 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK17 0x0000001C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK18 0x00000020 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK19 0x00000024 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK110 0x00000028 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK111 0x0000002C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK112 0x00000030 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK113 0x00000034 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK114 0x00000038 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK115 0x0000003C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK116 0x00000040 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK117 0x00000044 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK118 0x00000048 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK119 0x0000004C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK120 0x00000050 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK121 0x00000054 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK122 0x00000058 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK123 0x0000005C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK124 0x00000060 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK125 0x00000064 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK126 0x00000068 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK127 0x0000006C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK128 0x00000070 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK129 0x00000074 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK130 0x00000078 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK131 0x0000007C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK132 0x00000080 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK133 0x00000084 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK134 0x00000088 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK135 0x0000008C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK136 0x00000090 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK137 0x00000094 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK138 0x00000098 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK139 0x0000009C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK140 0x000000A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK141 0x000000A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK142 0x000000A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK143 0x000000AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK144 0x000000B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK145 0x000000B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK146 0x000000B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK147 0x000000BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK148 0x000000C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK149 0x000000C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK150 0x000000C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK151 0x000000CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK152 0x000000D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK153 0x000000D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK154 0x000000D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK155 0x000000DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK156 0x000000E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK157 0x000000E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK158 0x000000E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK159 0x000000EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK160 0x000000F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK161 0x000000F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK162 0x000000F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK163 0x000000FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK164 0x00000100 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK165 0x00000104 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK166 0x00000108 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK167 0x0000010C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK168 0x00000110 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK169 0x00000114 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK170 0x00000118 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK171 0x0000011C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK172 0x00000120 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK173 0x00000124 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK174 0x00000128 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK175 0x0000012C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK176 0x00000130 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK177 0x00000134 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK178 0x00000138 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK179 0x0000013C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK180 0x00000140 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK181 0x00000144 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK182 0x00000148 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK183 0x0000014C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK184 0x00000150 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK185 0x00000154 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK186 0x00000158 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK187 0x0000015C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK188 0x00000160 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK189 0x00000164 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK190 0x00000168 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK191 0x0000016C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK192 0x00000170 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK193 0x00000174 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK194 0x00000178 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK195 0x0000017C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK196 0x00000180 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK197 0x00000184 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK198 0x00000188 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK199 0x0000018C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1100 0x00000190 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1101 0x00000194 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1102 0x00000198 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1103 0x0000019C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1104 0x000001A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1105 0x000001A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1106 0x000001A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1107 0x000001AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1108 0x000001B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1109 0x000001B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1110 0x000001B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1111 0x000001BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1112 0x000001C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1113 0x000001C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1114 0x000001C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1115 0x000001CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1116 0x000001D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1117 0x000001D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1118 0x000001D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1119 0x000001DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1120 0x000001E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1121 0x000001E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1122 0x000001E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1123 0x000001EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1124 0x000001F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1125 0x000001F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1126 0x000001F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1127 0x000001FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1128 0x00000200 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1129 0x00000204 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1130 0x00000208 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1131 0x0000020C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1132 0x00000210 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1133 0x00000214 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1134 0x00000218 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1135 0x0000021C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1136 0x00000220 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1137 0x00000224 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1138 0x00000228 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1139 0x0000022C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1140 0x00000230 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1141 0x00000234 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1142 0x00000238 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1143 0x0000023C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1144 0x00000240 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1145 0x00000244 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1146 0x00000248 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1147 0x0000024C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1148 0x00000250 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1149 0x00000254 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1150 0x00000258 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1151 0x0000025C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1152 0x00000260 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1153 0x00000264 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1154 0x00000268 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1155 0x0000026C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1156 0x00000270 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1157 0x00000274 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1158 0x00000278 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1159 0x0000027C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1160 0x00000280 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1161 0x00000284 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1162 0x00000288 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1163 0x0000028C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1164 0x00000290 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1165 0x00000294 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1166 0x00000298 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1167 0x0000029C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1168 0x000002A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1169 0x000002A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1170 0x000002A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1171 0x000002AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1172 0x000002B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1173 0x000002B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1174 0x000002B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1175 0x000002BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1176 0x000002C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1177 0x000002C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1178 0x000002C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1179 0x000002CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1180 0x000002D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1181 0x000002D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1182 0x000002D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1183 0x000002DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1184 0x000002E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1185 0x000002E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1186 0x000002E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1187 0x000002EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1188 0x000002F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1189 0x000002F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1190 0x000002F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1191 0x000002FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1192 0x00000300 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1193 0x00000304 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1194 0x00000308 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1195 0x0000030C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1196 0x00000310 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1197 0x00000314 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1198 0x00000318 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1199 0x0000031C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1200 0x00000320 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1201 0x00000324 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1202 0x00000328 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1203 0x0000032C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1204 0x00000330 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1205 0x00000334 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1206 0x00000338 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1207 0x0000033C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1208 0x00000340 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1209 0x00000344 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1210 0x00000348 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1211 0x0000034C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1212 0x00000350 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1213 0x00000354 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1214 0x00000358 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1215 0x0000035C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1216 0x00000360 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1217 0x00000364 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1218 0x00000368 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1219 0x0000036C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1220 0x00000370 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1221 0x00000374 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1222 0x00000378 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1223 0x0000037C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1224 0x00000380 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1225 0x00000384 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1226 0x00000388 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1227 0x0000038C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1228 0x00000390 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1229 0x00000394 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1230 0x00000398 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1231 0x0000039C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1232 0x000003A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1233 0x000003A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1234 0x000003A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1235 0x000003AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1236 0x000003B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1237 0x000003B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1238 0x000003B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1239 0x000003BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1240 0x000003C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1241 0x000003C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1242 0x000003C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1243 0x000003CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1244 0x000003D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1245 0x000003D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1246 0x000003D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1247 0x000003DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1248 0x000003E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1249 0x000003E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1250 0x000003E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1251 0x000003EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1252 0x000003F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1253 0x000003F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1254 0x000003F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1255 0x000003FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1256 0x00000400 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1257 0x00000404 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1258 0x00000408 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1259 0x0000040C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1260 0x00000410 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1261 0x00000414 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1262 0x00000418 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1263 0x0000041C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1264 0x00000420 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1265 0x00000424 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1266 0x00000428 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1267 0x0000042C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1268 0x00000430 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1269 0x00000434 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1270 0x00000438 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1271 0x0000043C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1272 0x00000440 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1273 0x00000444 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1274 0x00000448 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1275 0x0000044C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1276 0x00000450 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1277 0x00000454 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1278 0x00000458 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1279 0x0000045C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1280 0x00000460 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1281 0x00000464 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1282 0x00000468 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1283 0x0000046C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1284 0x00000470 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1285 0x00000474 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1286 0x00000478 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1287 0x0000047C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1288 0x00000480 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1289 0x00000484 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1290 0x00000488 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1291 0x0000048C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1292 0x00000490 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1293 0x00000494 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1294 0x00000498 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1295 0x0000049C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1296 0x000004A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1297 0x000004A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1298 0x000004A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1299 0x000004AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1300 0x000004B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1301 0x000004B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1302 0x000004B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1303 0x000004BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1304 0x000004C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1305 0x000004C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1306 0x000004C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1307 0x000004CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1308 0x000004D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1309 0x000004D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1310 0x000004D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1311 0x000004DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1312 0x000004E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1313 0x000004E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1314 0x000004E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1315 0x000004EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1316 0x000004F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1317 0x000004F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1318 0x000004F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1319 0x000004FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1320 0x00000500 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1321 0x00000504 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1322 0x00000508 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1323 0x0000050C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1324 0x00000510 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1325 0x00000514 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1326 0x00000518 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1327 0x0000051C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1328 0x00000520 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1329 0x00000524 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1330 0x00000528 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1331 0x0000052C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1332 0x00000530 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1333 0x00000534 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1334 0x00000538 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1335 0x0000053C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1336 0x00000540 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1337 0x00000544 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1338 0x00000548 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1339 0x0000054C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1340 0x00000550 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1341 0x00000554 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1342 0x00000558 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1343 0x0000055C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1344 0x00000560 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1345 0x00000564 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1346 0x00000568 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1347 0x0000056C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1348 0x00000570 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1349 0x00000574 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1350 0x00000578 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1351 0x0000057C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1352 0x00000580 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1353 0x00000584 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1354 0x00000588 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1355 0x0000058C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1356 0x00000590 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1357 0x00000594 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1358 0x00000598 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1359 0x0000059C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1360 0x000005A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1361 0x000005A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1362 0x000005A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1363 0x000005AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1364 0x000005B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1365 0x000005B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1366 0x000005B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1367 0x000005BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1368 0x000005C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1369 0x000005C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1370 0x000005C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1371 0x000005CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1372 0x000005D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1373 0x000005D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1374 0x000005D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1375 0x000005DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1376 0x000005E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1377 0x000005E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1378 0x000005E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1379 0x000005EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1380 0x000005F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1381 0x000005F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1382 0x000005F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1383 0x000005FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1384 0x00000600 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1385 0x00000604 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1386 0x00000608 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1387 0x0000060C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1388 0x00000610 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1389 0x00000614 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1390 0x00000618 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1391 0x0000061C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1392 0x00000620 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1393 0x00000624 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1394 0x00000628 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1395 0x0000062C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1396 0x00000630 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1397 0x00000634 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1398 0x00000638 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1399 0x0000063C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1400 0x00000640 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1401 0x00000644 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1402 0x00000648 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1403 0x0000064C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1404 0x00000650 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1405 0x00000654 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1406 0x00000658 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1407 0x0000065C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1408 0x00000660 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1409 0x00000664 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1410 0x00000668 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1411 0x0000066C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1412 0x00000670 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1413 0x00000674 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1414 0x00000678 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1415 0x0000067C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1416 0x00000680 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1417 0x00000684 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1418 0x00000688 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1419 0x0000068C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1420 0x00000690 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1421 0x00000694 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1422 0x00000698 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1423 0x0000069C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1424 0x000006A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1425 0x000006A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1426 0x000006A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1427 0x000006AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1428 0x000006B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1429 0x000006B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1430 0x000006B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1431 0x000006BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1432 0x000006C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1433 0x000006C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1434 0x000006C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1435 0x000006CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1436 0x000006D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1437 0x000006D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1438 0x000006D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1439 0x000006DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1440 0x000006E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1441 0x000006E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1442 0x000006E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1443 0x000006EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1444 0x000006F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1445 0x000006F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1446 0x000006F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1447 0x000006FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1448 0x00000700 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1449 0x00000704 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1450 0x00000708 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1451 0x0000070C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1452 0x00000710 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1453 0x00000714 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1454 0x00000718 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1455 0x0000071C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1456 0x00000720 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1457 0x00000724 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1458 0x00000728 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1459 0x0000072C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1460 0x00000730 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1461 0x00000734 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1462 0x00000738 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1463 0x0000073C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1464 0x00000740 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1465 0x00000744 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1466 0x00000748 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1467 0x0000074C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1468 0x00000750 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1469 0x00000754 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1470 0x00000758 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1471 0x0000075C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1472 0x00000760 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1473 0x00000764 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1474 0x00000768 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1475 0x0000076C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1476 0x00000770 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1477 0x00000774 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1478 0x00000778 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1479 0x0000077C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1480 0x00000780 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1481 0x00000784 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1482 0x00000788 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1483 0x0000078C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1484 0x00000790 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1485 0x00000794 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1486 0x00000798 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1487 0x0000079C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1488 0x000007A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1489 0x000007A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1490 0x000007A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1491 0x000007AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1492 0x000007B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1493 0x000007B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1494 0x000007B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1495 0x000007BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1496 0x000007C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1497 0x000007C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1498 0x000007C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1499 0x000007CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1500 0x000007D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1501 0x000007D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1502 0x000007D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1503 0x000007DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1504 0x000007E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1505 0x000007E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1506 0x000007E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1507 0x000007EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1508 0x000007F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1509 0x000007F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1510 0x000007F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1511 0x000007FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1512 0x00000800 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1513 0x00000804 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1514 0x00000808 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1515 0x0000080C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1516 0x00000810 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1517 0x00000814 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1518 0x00000818 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1519 0x0000081C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1520 0x00000820 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1521 0x00000824 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1522 0x00000828 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1523 0x0000082C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1524 0x00000830 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1525 0x00000834 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1526 0x00000838 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1527 0x0000083C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1528 0x00000840 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1529 0x00000844 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1530 0x00000848 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1531 0x0000084C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1532 0x00000850 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1533 0x00000854 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1534 0x00000858 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1535 0x0000085C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1536 0x00000860 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1537 0x00000864 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1538 0x00000868 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1539 0x0000086C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1540 0x00000870 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1541 0x00000874 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1542 0x00000878 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1543 0x0000087C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1544 0x00000880 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1545 0x00000884 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1546 0x00000888 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1547 0x0000088C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1548 0x00000890 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1549 0x00000894 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1550 0x00000898 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1551 0x0000089C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1552 0x000008A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1553 0x000008A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1554 0x000008A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1555 0x000008AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1556 0x000008B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1557 0x000008B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1558 0x000008B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1559 0x000008BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1560 0x000008C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1561 0x000008C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1562 0x000008C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1563 0x000008CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1564 0x000008D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1565 0x000008D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1566 0x000008D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1567 0x000008DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1568 0x000008E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1569 0x000008E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1570 0x000008E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1571 0x000008EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1572 0x000008F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1573 0x000008F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1574 0x000008F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1575 0x000008FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1576 0x00000900 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1577 0x00000904 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1578 0x00000908 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1579 0x0000090C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1580 0x00000910 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1581 0x00000914 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1582 0x00000918 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1583 0x0000091C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1584 0x00000920 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1585 0x00000924 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1586 0x00000928 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1587 0x0000092C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1588 0x00000930 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1589 0x00000934 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1590 0x00000938 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1591 0x0000093C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1592 0x00000940 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1593 0x00000944 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1594 0x00000948 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1595 0x0000094C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1596 0x00000950 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1597 0x00000954 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1598 0x00000958 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1599 0x0000095C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1600 0x00000960 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1601 0x00000964 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1602 0x00000968 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1603 0x0000096C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1604 0x00000970 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1605 0x00000974 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1606 0x00000978 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1607 0x0000097C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1608 0x00000980 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1609 0x00000984 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1610 0x00000988 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1611 0x0000098C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1612 0x00000990 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1613 0x00000994 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1614 0x00000998 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1615 0x0000099C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1616 0x000009A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1617 0x000009A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1618 0x000009A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1619 0x000009AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1620 0x000009B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1621 0x000009B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1622 0x000009B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1623 0x000009BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1624 0x000009C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1625 0x000009C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1626 0x000009C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1627 0x000009CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1628 0x000009D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1629 0x000009D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1630 0x000009D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1631 0x000009DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1632 0x000009E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1633 0x000009E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1634 0x000009E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1635 0x000009EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1636 0x000009F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1637 0x000009F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1638 0x000009F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1639 0x000009FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1640 0x00000A00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1641 0x00000A04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1642 0x00000A08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1643 0x00000A0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1644 0x00000A10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1645 0x00000A14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1646 0x00000A18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1647 0x00000A1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1648 0x00000A20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1649 0x00000A24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1650 0x00000A28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1651 0x00000A2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1652 0x00000A30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1653 0x00000A34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1654 0x00000A38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1655 0x00000A3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1656 0x00000A40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1657 0x00000A44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1658 0x00000A48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1659 0x00000A4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1660 0x00000A50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1661 0x00000A54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1662 0x00000A58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1663 0x00000A5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1664 0x00000A60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1665 0x00000A64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1666 0x00000A68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1667 0x00000A6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1668 0x00000A70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1669 0x00000A74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1670 0x00000A78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1671 0x00000A7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1672 0x00000A80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1673 0x00000A84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1674 0x00000A88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1675 0x00000A8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1676 0x00000A90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1677 0x00000A94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1678 0x00000A98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1679 0x00000A9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1680 0x00000AA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1681 0x00000AA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1682 0x00000AA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1683 0x00000AAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1684 0x00000AB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1685 0x00000AB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1686 0x00000AB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1687 0x00000ABC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1688 0x00000AC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1689 0x00000AC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1690 0x00000AC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1691 0x00000ACC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1692 0x00000AD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1693 0x00000AD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1694 0x00000AD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1695 0x00000ADC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1696 0x00000AE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1697 0x00000AE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1698 0x00000AE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1699 0x00000AEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1700 0x00000AF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1701 0x00000AF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1702 0x00000AF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1703 0x00000AFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1704 0x00000B00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1705 0x00000B04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1706 0x00000B08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1707 0x00000B0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1708 0x00000B10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1709 0x00000B14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1710 0x00000B18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1711 0x00000B1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1712 0x00000B20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1713 0x00000B24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1714 0x00000B28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1715 0x00000B2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1716 0x00000B30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1717 0x00000B34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1718 0x00000B38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1719 0x00000B3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1720 0x00000B40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1721 0x00000B44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1722 0x00000B48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1723 0x00000B4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1724 0x00000B50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1725 0x00000B54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1726 0x00000B58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1727 0x00000B5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1728 0x00000B60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1729 0x00000B64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1730 0x00000B68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1731 0x00000B6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1732 0x00000B70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1733 0x00000B74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1734 0x00000B78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1735 0x00000B7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1736 0x00000B80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1737 0x00000B84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1738 0x00000B88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1739 0x00000B8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1740 0x00000B90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1741 0x00000B94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1742 0x00000B98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1743 0x00000B9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1744 0x00000BA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1745 0x00000BA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1746 0x00000BA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1747 0x00000BAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1748 0x00000BB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1749 0x00000BB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1750 0x00000BB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1751 0x00000BBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1752 0x00000BC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1753 0x00000BC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1754 0x00000BC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1755 0x00000BCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1756 0x00000BD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1757 0x00000BD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1758 0x00000BD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1759 0x00000BDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1760 0x00000BE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1761 0x00000BE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1762 0x00000BE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1763 0x00000BEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1764 0x00000BF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1765 0x00000BF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1766 0x00000BF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1767 0x00000BFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1768 0x00000C00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1769 0x00000C04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1770 0x00000C08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1771 0x00000C0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1772 0x00000C10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1773 0x00000C14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1774 0x00000C18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1775 0x00000C1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1776 0x00000C20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1777 0x00000C24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1778 0x00000C28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1779 0x00000C2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1780 0x00000C30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1781 0x00000C34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1782 0x00000C38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1783 0x00000C3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1784 0x00000C40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1785 0x00000C44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1786 0x00000C48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1787 0x00000C4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1788 0x00000C50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1789 0x00000C54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1790 0x00000C58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1791 0x00000C5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1792 0x00000C60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1793 0x00000C64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1794 0x00000C68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1795 0x00000C6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1796 0x00000C70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1797 0x00000C74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1798 0x00000C78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1799 0x00000C7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1800 0x00000C80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1801 0x00000C84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1802 0x00000C88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1803 0x00000C8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1804 0x00000C90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1805 0x00000C94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1806 0x00000C98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1807 0x00000C9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1808 0x00000CA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1809 0x00000CA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1810 0x00000CA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1811 0x00000CAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1812 0x00000CB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1813 0x00000CB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1814 0x00000CB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1815 0x00000CBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1816 0x00000CC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1817 0x00000CC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1818 0x00000CC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1819 0x00000CCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1820 0x00000CD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1821 0x00000CD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1822 0x00000CD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1823 0x00000CDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1824 0x00000CE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1825 0x00000CE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1826 0x00000CE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1827 0x00000CEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1828 0x00000CF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1829 0x00000CF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1830 0x00000CF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1831 0x00000CFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1832 0x00000D00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1833 0x00000D04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1834 0x00000D08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1835 0x00000D0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1836 0x00000D10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1837 0x00000D14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1838 0x00000D18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1839 0x00000D1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1840 0x00000D20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1841 0x00000D24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1842 0x00000D28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1843 0x00000D2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1844 0x00000D30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1845 0x00000D34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1846 0x00000D38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1847 0x00000D3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1848 0x00000D40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1849 0x00000D44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1850 0x00000D48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1851 0x00000D4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1852 0x00000D50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1853 0x00000D54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1854 0x00000D58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1855 0x00000D5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1856 0x00000D60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1857 0x00000D64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1858 0x00000D68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1859 0x00000D6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1860 0x00000D70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1861 0x00000D74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1862 0x00000D78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1863 0x00000D7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1864 0x00000D80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1865 0x00000D84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1866 0x00000D88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1867 0x00000D8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1868 0x00000D90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1869 0x00000D94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1870 0x00000D98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1871 0x00000D9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1872 0x00000DA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1873 0x00000DA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1874 0x00000DA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1875 0x00000DAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1876 0x00000DB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1877 0x00000DB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1878 0x00000DB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1879 0x00000DBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1880 0x00000DC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1881 0x00000DC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1882 0x00000DC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1883 0x00000DCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1884 0x00000DD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1885 0x00000DD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1886 0x00000DD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1887 0x00000DDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1888 0x00000DE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1889 0x00000DE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1890 0x00000DE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1891 0x00000DEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1892 0x00000DF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1893 0x00000DF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1894 0x00000DF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1895 0x00000DFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1896 0x00000E00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1897 0x00000E04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1898 0x00000E08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1899 0x00000E0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1900 0x00000E10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1901 0x00000E14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1902 0x00000E18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1903 0x00000E1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1904 0x00000E20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1905 0x00000E24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1906 0x00000E28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1907 0x00000E2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1908 0x00000E30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1909 0x00000E34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1910 0x00000E38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1911 0x00000E3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1912 0x00000E40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1913 0x00000E44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1914 0x00000E48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1915 0x00000E4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1916 0x00000E50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1917 0x00000E54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1918 0x00000E58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1919 0x00000E5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1920 0x00000E60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1921 0x00000E64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1922 0x00000E68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1923 0x00000E6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1924 0x00000E70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1925 0x00000E74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1926 0x00000E78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1927 0x00000E7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1928 0x00000E80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1929 0x00000E84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1930 0x00000E88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1931 0x00000E8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1932 0x00000E90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1933 0x00000E94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1934 0x00000E98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1935 0x00000E9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1936 0x00000EA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1937 0x00000EA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1938 0x00000EA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1939 0x00000EAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1940 0x00000EB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1941 0x00000EB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1942 0x00000EB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1943 0x00000EBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1944 0x00000EC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1945 0x00000EC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1946 0x00000EC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1947 0x00000ECC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1948 0x00000ED0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1949 0x00000ED4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1950 0x00000ED8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1951 0x00000EDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1952 0x00000EE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1953 0x00000EE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1954 0x00000EE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1955 0x00000EEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1956 0x00000EF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1957 0x00000EF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1958 0x00000EF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1959 0x00000EFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1960 0x00000F00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1961 0x00000F04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1962 0x00000F08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1963 0x00000F0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1964 0x00000F10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1965 0x00000F14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1966 0x00000F18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1967 0x00000F1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1968 0x00000F20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1969 0x00000F24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1970 0x00000F28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1971 0x00000F2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1972 0x00000F30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1973 0x00000F34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1974 0x00000F38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1975 0x00000F3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1976 0x00000F40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1977 0x00000F44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1978 0x00000F48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1979 0x00000F4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1980 0x00000F50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1981 0x00000F54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1982 0x00000F58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1983 0x00000F5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1984 0x00000F60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1985 0x00000F64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1986 0x00000F68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1987 0x00000F6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1988 0x00000F70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1989 0x00000F74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1990 0x00000F78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1991 0x00000F7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1992 0x00000F80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1993 0x00000F84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1994 0x00000F88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1995 0x00000F8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1996 0x00000F90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1997 0x00000F94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1998 0x00000F98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK1999 0x00000F9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11000 0x00000FA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11001 0x00000FA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11002 0x00000FA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11003 0x00000FAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11004 0x00000FB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11005 0x00000FB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11006 0x00000FB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11007 0x00000FBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11008 0x00000FC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11009 0x00000FC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11010 0x00000FC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11011 0x00000FCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11012 0x00000FD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11013 0x00000FD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11014 0x00000FD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11015 0x00000FDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11016 0x00000FE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11017 0x00000FE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11018 0x00000FE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11019 0x00000FEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11020 0x00000FF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11021 0x00000FF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11022 0x00000FF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11023 0x00000FFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11024 0x00001000 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11025 0x00001004 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11026 0x00001008 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11027 0x0000100C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11028 0x00001010 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11029 0x00001014 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11030 0x00001018 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11031 0x0000101C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11032 0x00001020 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11033 0x00001024 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11034 0x00001028 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11035 0x0000102C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11036 0x00001030 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11037 0x00001034 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11038 0x00001038 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11039 0x0000103C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11040 0x00001040 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11041 0x00001044 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11042 0x00001048 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11043 0x0000104C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11044 0x00001050 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11045 0x00001054 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11046 0x00001058 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11047 0x0000105C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11048 0x00001060 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11049 0x00001064 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11050 0x00001068 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11051 0x0000106C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11052 0x00001070 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11053 0x00001074 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11054 0x00001078 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11055 0x0000107C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11056 0x00001080 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11057 0x00001084 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11058 0x00001088 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11059 0x0000108C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11060 0x00001090 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11061 0x00001094 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11062 0x00001098 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11063 0x0000109C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11064 0x000010A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11065 0x000010A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11066 0x000010A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11067 0x000010AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11068 0x000010B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11069 0x000010B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11070 0x000010B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11071 0x000010BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11072 0x000010C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11073 0x000010C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11074 0x000010C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11075 0x000010CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11076 0x000010D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11077 0x000010D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11078 0x000010D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11079 0x000010DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11080 0x000010E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11081 0x000010E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11082 0x000010E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11083 0x000010EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11084 0x000010F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11085 0x000010F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11086 0x000010F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11087 0x000010FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11088 0x00001100 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11089 0x00001104 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11090 0x00001108 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11091 0x0000110C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11092 0x00001110 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11093 0x00001114 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11094 0x00001118 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11095 0x0000111C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11096 0x00001120 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11097 0x00001124 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11098 0x00001128 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11099 0x0000112C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11100 0x00001130 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11101 0x00001134 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11102 0x00001138 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11103 0x0000113C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11104 0x00001140 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11105 0x00001144 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11106 0x00001148 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11107 0x0000114C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11108 0x00001150 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11109 0x00001154 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11110 0x00001158 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11111 0x0000115C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11112 0x00001160 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11113 0x00001164 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11114 0x00001168 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11115 0x0000116C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11116 0x00001170 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11117 0x00001174 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11118 0x00001178 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11119 0x0000117C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11120 0x00001180 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11121 0x00001184 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11122 0x00001188 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11123 0x0000118C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11124 0x00001190 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11125 0x00001194 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11126 0x00001198 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11127 0x0000119C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11128 0x000011A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11129 0x000011A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11130 0x000011A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11131 0x000011AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11132 0x000011B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11133 0x000011B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11134 0x000011B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11135 0x000011BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11136 0x000011C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11137 0x000011C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11138 0x000011C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11139 0x000011CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11140 0x000011D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11141 0x000011D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11142 0x000011D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11143 0x000011DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11144 0x000011E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11145 0x000011E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11146 0x000011E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11147 0x000011EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11148 0x000011F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11149 0x000011F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11150 0x000011F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11151 0x000011FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11152 0x00001200 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11153 0x00001204 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11154 0x00001208 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11155 0x0000120C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11156 0x00001210 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11157 0x00001214 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11158 0x00001218 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11159 0x0000121C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11160 0x00001220 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11161 0x00001224 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11162 0x00001228 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11163 0x0000122C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11164 0x00001230 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11165 0x00001234 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11166 0x00001238 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11167 0x0000123C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11168 0x00001240 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11169 0x00001244 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11170 0x00001248 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11171 0x0000124C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11172 0x00001250 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11173 0x00001254 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11174 0x00001258 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11175 0x0000125C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11176 0x00001260 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11177 0x00001264 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11178 0x00001268 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11179 0x0000126C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11180 0x00001270 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11181 0x00001274 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11182 0x00001278 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11183 0x0000127C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11184 0x00001280 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11185 0x00001284 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11186 0x00001288 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11187 0x0000128C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11188 0x00001290 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11189 0x00001294 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11190 0x00001298 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11191 0x0000129C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11192 0x000012A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11193 0x000012A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11194 0x000012A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11195 0x000012AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11196 0x000012B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11197 0x000012B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11198 0x000012B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11199 0x000012BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11200 0x000012C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11201 0x000012C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11202 0x000012C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11203 0x000012CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11204 0x000012D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11205 0x000012D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11206 0x000012D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11207 0x000012DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11208 0x000012E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11209 0x000012E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11210 0x000012E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11211 0x000012EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11212 0x000012F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11213 0x000012F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11214 0x000012F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11215 0x000012FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11216 0x00001300 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11217 0x00001304 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11218 0x00001308 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11219 0x0000130C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11220 0x00001310 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11221 0x00001314 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11222 0x00001318 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11223 0x0000131C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11224 0x00001320 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11225 0x00001324 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11226 0x00001328 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11227 0x0000132C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11228 0x00001330 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11229 0x00001334 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11230 0x00001338 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11231 0x0000133C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11232 0x00001340 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11233 0x00001344 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11234 0x00001348 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11235 0x0000134C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11236 0x00001350 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11237 0x00001354 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11238 0x00001358 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11239 0x0000135C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11240 0x00001360 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11241 0x00001364 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11242 0x00001368 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11243 0x0000136C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11244 0x00001370 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11245 0x00001374 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11246 0x00001378 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11247 0x0000137C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11248 0x00001380 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11249 0x00001384 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11250 0x00001388 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11251 0x0000138C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11252 0x00001390 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11253 0x00001394 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11254 0x00001398 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11255 0x0000139C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11256 0x000013A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11257 0x000013A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11258 0x000013A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11259 0x000013AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11260 0x000013B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11261 0x000013B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11262 0x000013B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11263 0x000013BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11264 0x000013C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11265 0x000013C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11266 0x000013C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11267 0x000013CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11268 0x000013D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11269 0x000013D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11270 0x000013D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11271 0x000013DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11272 0x000013E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11273 0x000013E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11274 0x000013E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11275 0x000013EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11276 0x000013F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11277 0x000013F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11278 0x000013F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11279 0x000013FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11280 0x00001400 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11281 0x00001404 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11282 0x00001408 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11283 0x0000140C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11284 0x00001410 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11285 0x00001414 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11286 0x00001418 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11287 0x0000141C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11288 0x00001420 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11289 0x00001424 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11290 0x00001428 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11291 0x0000142C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11292 0x00001430 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11293 0x00001434 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11294 0x00001438 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11295 0x0000143C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11296 0x00001440 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11297 0x00001444 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11298 0x00001448 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11299 0x0000144C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11300 0x00001450 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11301 0x00001454 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11302 0x00001458 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11303 0x0000145C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11304 0x00001460 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11305 0x00001464 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11306 0x00001468 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11307 0x0000146C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11308 0x00001470 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11309 0x00001474 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11310 0x00001478 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11311 0x0000147C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11312 0x00001480 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11313 0x00001484 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11314 0x00001488 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11315 0x0000148C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11316 0x00001490 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11317 0x00001494 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11318 0x00001498 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11319 0x0000149C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11320 0x000014A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11321 0x000014A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11322 0x000014A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11323 0x000014AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11324 0x000014B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11325 0x000014B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11326 0x000014B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11327 0x000014BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11328 0x000014C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11329 0x000014C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11330 0x000014C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11331 0x000014CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11332 0x000014D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11333 0x000014D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11334 0x000014D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11335 0x000014DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11336 0x000014E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11337 0x000014E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11338 0x000014E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11339 0x000014EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11340 0x000014F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11341 0x000014F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11342 0x000014F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11343 0x000014FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11344 0x00001500 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11345 0x00001504 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11346 0x00001508 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11347 0x0000150C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11348 0x00001510 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11349 0x00001514 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11350 0x00001518 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11351 0x0000151C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11352 0x00001520 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11353 0x00001524 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11354 0x00001528 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11355 0x0000152C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11356 0x00001530 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11357 0x00001534 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11358 0x00001538 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11359 0x0000153C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11360 0x00001540 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11361 0x00001544 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11362 0x00001548 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11363 0x0000154C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11364 0x00001550 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11365 0x00001554 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11366 0x00001558 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11367 0x0000155C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11368 0x00001560 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11369 0x00001564 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11370 0x00001568 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11371 0x0000156C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11372 0x00001570 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11373 0x00001574 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11374 0x00001578 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11375 0x0000157C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11376 0x00001580 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11377 0x00001584 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11378 0x00001588 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11379 0x0000158C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11380 0x00001590 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11381 0x00001594 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11382 0x00001598 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11383 0x0000159C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11384 0x000015A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11385 0x000015A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11386 0x000015A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11387 0x000015AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11388 0x000015B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11389 0x000015B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11390 0x000015B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11391 0x000015BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11392 0x000015C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11393 0x000015C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11394 0x000015C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11395 0x000015CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11396 0x000015D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11397 0x000015D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11398 0x000015D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11399 0x000015DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11400 0x000015E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11401 0x000015E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11402 0x000015E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11403 0x000015EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11404 0x000015F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11405 0x000015F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11406 0x000015F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11407 0x000015FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11408 0x00001600 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11409 0x00001604 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11410 0x00001608 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11411 0x0000160C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11412 0x00001610 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11413 0x00001614 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11414 0x00001618 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11415 0x0000161C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11416 0x00001620 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11417 0x00001624 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11418 0x00001628 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11419 0x0000162C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11420 0x00001630 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11421 0x00001634 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11422 0x00001638 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11423 0x0000163C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11424 0x00001640 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11425 0x00001644 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11426 0x00001648 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11427 0x0000164C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11428 0x00001650 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11429 0x00001654 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11430 0x00001658 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11431 0x0000165C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11432 0x00001660 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11433 0x00001664 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11434 0x00001668 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11435 0x0000166C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11436 0x00001670 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11437 0x00001674 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11438 0x00001678 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11439 0x0000167C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11440 0x00001680 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11441 0x00001684 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11442 0x00001688 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11443 0x0000168C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11444 0x00001690 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11445 0x00001694 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11446 0x00001698 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11447 0x0000169C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11448 0x000016A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11449 0x000016A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11450 0x000016A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11451 0x000016AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11452 0x000016B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11453 0x000016B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11454 0x000016B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11455 0x000016BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11456 0x000016C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11457 0x000016C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11458 0x000016C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11459 0x000016CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11460 0x000016D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11461 0x000016D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11462 0x000016D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11463 0x000016DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11464 0x000016E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11465 0x000016E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11466 0x000016E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11467 0x000016EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11468 0x000016F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11469 0x000016F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11470 0x000016F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11471 0x000016FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11472 0x00001700 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11473 0x00001704 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11474 0x00001708 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11475 0x0000170C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11476 0x00001710 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11477 0x00001714 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11478 0x00001718 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11479 0x0000171C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11480 0x00001720 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11481 0x00001724 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11482 0x00001728 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11483 0x0000172C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11484 0x00001730 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11485 0x00001734 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11486 0x00001738 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11487 0x0000173C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11488 0x00001740 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11489 0x00001744 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11490 0x00001748 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11491 0x0000174C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11492 0x00001750 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11493 0x00001754 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11494 0x00001758 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11495 0x0000175C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11496 0x00001760 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11497 0x00001764 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11498 0x00001768 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11499 0x0000176C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11500 0x00001770 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11501 0x00001774 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11502 0x00001778 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11503 0x0000177C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11504 0x00001780 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11505 0x00001784 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11506 0x00001788 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11507 0x0000178C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11508 0x00001790 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11509 0x00001794 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11510 0x00001798 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11511 0x0000179C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11512 0x000017A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11513 0x000017A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11514 0x000017A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11515 0x000017AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11516 0x000017B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11517 0x000017B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11518 0x000017B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11519 0x000017BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11520 0x000017C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11521 0x000017C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11522 0x000017C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11523 0x000017CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11524 0x000017D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11525 0x000017D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11526 0x000017D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11527 0x000017DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11528 0x000017E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11529 0x000017E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11530 0x000017E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11531 0x000017EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11532 0x000017F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11533 0x000017F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11534 0x000017F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11535 0x000017FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11536 0x00001800 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11537 0x00001804 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11538 0x00001808 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11539 0x0000180C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11540 0x00001810 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11541 0x00001814 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11542 0x00001818 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11543 0x0000181C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11544 0x00001820 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11545 0x00001824 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11546 0x00001828 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11547 0x0000182C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11548 0x00001830 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11549 0x00001834 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11550 0x00001838 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11551 0x0000183C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11552 0x00001840 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11553 0x00001844 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11554 0x00001848 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11555 0x0000184C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11556 0x00001850 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11557 0x00001854 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11558 0x00001858 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11559 0x0000185C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11560 0x00001860 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11561 0x00001864 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11562 0x00001868 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11563 0x0000186C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11564 0x00001870 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11565 0x00001874 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11566 0x00001878 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11567 0x0000187C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11568 0x00001880 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11569 0x00001884 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11570 0x00001888 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11571 0x0000188C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11572 0x00001890 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11573 0x00001894 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11574 0x00001898 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11575 0x0000189C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11576 0x000018A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11577 0x000018A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11578 0x000018A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11579 0x000018AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11580 0x000018B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11581 0x000018B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11582 0x000018B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11583 0x000018BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11584 0x000018C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11585 0x000018C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11586 0x000018C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11587 0x000018CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11588 0x000018D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11589 0x000018D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11590 0x000018D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11591 0x000018DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11592 0x000018E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11593 0x000018E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11594 0x000018E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11595 0x000018EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11596 0x000018F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11597 0x000018F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11598 0x000018F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11599 0x000018FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11600 0x00001900 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11601 0x00001904 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11602 0x00001908 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11603 0x0000190C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11604 0x00001910 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11605 0x00001914 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11606 0x00001918 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11607 0x0000191C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11608 0x00001920 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11609 0x00001924 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11610 0x00001928 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11611 0x0000192C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11612 0x00001930 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11613 0x00001934 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11614 0x00001938 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11615 0x0000193C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11616 0x00001940 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11617 0x00001944 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11618 0x00001948 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11619 0x0000194C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11620 0x00001950 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11621 0x00001954 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11622 0x00001958 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11623 0x0000195C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11624 0x00001960 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11625 0x00001964 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11626 0x00001968 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11627 0x0000196C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11628 0x00001970 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11629 0x00001974 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11630 0x00001978 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11631 0x0000197C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11632 0x00001980 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11633 0x00001984 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11634 0x00001988 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11635 0x0000198C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11636 0x00001990 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11637 0x00001994 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11638 0x00001998 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11639 0x0000199C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11640 0x000019A0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11641 0x000019A4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11642 0x000019A8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11643 0x000019AC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11644 0x000019B0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11645 0x000019B4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11646 0x000019B8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11647 0x000019BC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11648 0x000019C0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11649 0x000019C4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11650 0x000019C8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11651 0x000019CC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11652 0x000019D0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11653 0x000019D4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11654 0x000019D8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11655 0x000019DC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11656 0x000019E0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11657 0x000019E4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11658 0x000019E8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11659 0x000019EC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11660 0x000019F0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11661 0x000019F4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11662 0x000019F8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11663 0x000019FC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11664 0x00001A00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11665 0x00001A04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11666 0x00001A08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11667 0x00001A0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11668 0x00001A10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11669 0x00001A14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11670 0x00001A18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11671 0x00001A1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11672 0x00001A20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11673 0x00001A24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11674 0x00001A28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11675 0x00001A2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11676 0x00001A30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11677 0x00001A34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11678 0x00001A38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11679 0x00001A3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11680 0x00001A40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11681 0x00001A44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11682 0x00001A48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11683 0x00001A4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11684 0x00001A50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11685 0x00001A54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11686 0x00001A58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11687 0x00001A5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11688 0x00001A60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11689 0x00001A64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11690 0x00001A68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11691 0x00001A6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11692 0x00001A70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11693 0x00001A74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11694 0x00001A78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11695 0x00001A7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11696 0x00001A80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11697 0x00001A84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11698 0x00001A88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11699 0x00001A8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11700 0x00001A90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11701 0x00001A94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11702 0x00001A98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11703 0x00001A9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11704 0x00001AA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11705 0x00001AA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11706 0x00001AA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11707 0x00001AAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11708 0x00001AB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11709 0x00001AB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11710 0x00001AB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11711 0x00001ABC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11712 0x00001AC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11713 0x00001AC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11714 0x00001AC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11715 0x00001ACC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11716 0x00001AD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11717 0x00001AD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11718 0x00001AD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11719 0x00001ADC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11720 0x00001AE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11721 0x00001AE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11722 0x00001AE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11723 0x00001AEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11724 0x00001AF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11725 0x00001AF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11726 0x00001AF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11727 0x00001AFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11728 0x00001B00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11729 0x00001B04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11730 0x00001B08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11731 0x00001B0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11732 0x00001B10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11733 0x00001B14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11734 0x00001B18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11735 0x00001B1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11736 0x00001B20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11737 0x00001B24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11738 0x00001B28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11739 0x00001B2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11740 0x00001B30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11741 0x00001B34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11742 0x00001B38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11743 0x00001B3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11744 0x00001B40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11745 0x00001B44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11746 0x00001B48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11747 0x00001B4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11748 0x00001B50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11749 0x00001B54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11750 0x00001B58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11751 0x00001B5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11752 0x00001B60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11753 0x00001B64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11754 0x00001B68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11755 0x00001B6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11756 0x00001B70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11757 0x00001B74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11758 0x00001B78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11759 0x00001B7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11760 0x00001B80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11761 0x00001B84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11762 0x00001B88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11763 0x00001B8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11764 0x00001B90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11765 0x00001B94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11766 0x00001B98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11767 0x00001B9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11768 0x00001BA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11769 0x00001BA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11770 0x00001BA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11771 0x00001BAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11772 0x00001BB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11773 0x00001BB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11774 0x00001BB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11775 0x00001BBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11776 0x00001BC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11777 0x00001BC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11778 0x00001BC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11779 0x00001BCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11780 0x00001BD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11781 0x00001BD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11782 0x00001BD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11783 0x00001BDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11784 0x00001BE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11785 0x00001BE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11786 0x00001BE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11787 0x00001BEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11788 0x00001BF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11789 0x00001BF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11790 0x00001BF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11791 0x00001BFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11792 0x00001C00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11793 0x00001C04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11794 0x00001C08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11795 0x00001C0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11796 0x00001C10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11797 0x00001C14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11798 0x00001C18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11799 0x00001C1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11800 0x00001C20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11801 0x00001C24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11802 0x00001C28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11803 0x00001C2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11804 0x00001C30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11805 0x00001C34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11806 0x00001C38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11807 0x00001C3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11808 0x00001C40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11809 0x00001C44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11810 0x00001C48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11811 0x00001C4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11812 0x00001C50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11813 0x00001C54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11814 0x00001C58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11815 0x00001C5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11816 0x00001C60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11817 0x00001C64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11818 0x00001C68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11819 0x00001C6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11820 0x00001C70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11821 0x00001C74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11822 0x00001C78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11823 0x00001C7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11824 0x00001C80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11825 0x00001C84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11826 0x00001C88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11827 0x00001C8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11828 0x00001C90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11829 0x00001C94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11830 0x00001C98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11831 0x00001C9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11832 0x00001CA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11833 0x00001CA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11834 0x00001CA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11835 0x00001CAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11836 0x00001CB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11837 0x00001CB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11838 0x00001CB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11839 0x00001CBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11840 0x00001CC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11841 0x00001CC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11842 0x00001CC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11843 0x00001CCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11844 0x00001CD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11845 0x00001CD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11846 0x00001CD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11847 0x00001CDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11848 0x00001CE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11849 0x00001CE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11850 0x00001CE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11851 0x00001CEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11852 0x00001CF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11853 0x00001CF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11854 0x00001CF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11855 0x00001CFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11856 0x00001D00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11857 0x00001D04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11858 0x00001D08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11859 0x00001D0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11860 0x00001D10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11861 0x00001D14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11862 0x00001D18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11863 0x00001D1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11864 0x00001D20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11865 0x00001D24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11866 0x00001D28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11867 0x00001D2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11868 0x00001D30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11869 0x00001D34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11870 0x00001D38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11871 0x00001D3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11872 0x00001D40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11873 0x00001D44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11874 0x00001D48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11875 0x00001D4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11876 0x00001D50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11877 0x00001D54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11878 0x00001D58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11879 0x00001D5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11880 0x00001D60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11881 0x00001D64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11882 0x00001D68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11883 0x00001D6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11884 0x00001D70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11885 0x00001D74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11886 0x00001D78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11887 0x00001D7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11888 0x00001D80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11889 0x00001D84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11890 0x00001D88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11891 0x00001D8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11892 0x00001D90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11893 0x00001D94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11894 0x00001D98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11895 0x00001D9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11896 0x00001DA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11897 0x00001DA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11898 0x00001DA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11899 0x00001DAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11900 0x00001DB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11901 0x00001DB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11902 0x00001DB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11903 0x00001DBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11904 0x00001DC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11905 0x00001DC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11906 0x00001DC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11907 0x00001DCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11908 0x00001DD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11909 0x00001DD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11910 0x00001DD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11911 0x00001DDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11912 0x00001DE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11913 0x00001DE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11914 0x00001DE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11915 0x00001DEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11916 0x00001DF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11917 0x00001DF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11918 0x00001DF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11919 0x00001DFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11920 0x00001E00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11921 0x00001E04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11922 0x00001E08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11923 0x00001E0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11924 0x00001E10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11925 0x00001E14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11926 0x00001E18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11927 0x00001E1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11928 0x00001E20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11929 0x00001E24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11930 0x00001E28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11931 0x00001E2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11932 0x00001E30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11933 0x00001E34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11934 0x00001E38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11935 0x00001E3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11936 0x00001E40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11937 0x00001E44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11938 0x00001E48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11939 0x00001E4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11940 0x00001E50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11941 0x00001E54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11942 0x00001E58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11943 0x00001E5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11944 0x00001E60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11945 0x00001E64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11946 0x00001E68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11947 0x00001E6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11948 0x00001E70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11949 0x00001E74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11950 0x00001E78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11951 0x00001E7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11952 0x00001E80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11953 0x00001E84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11954 0x00001E88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11955 0x00001E8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11956 0x00001E90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11957 0x00001E94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11958 0x00001E98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11959 0x00001E9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11960 0x00001EA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11961 0x00001EA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11962 0x00001EA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11963 0x00001EAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11964 0x00001EB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11965 0x00001EB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11966 0x00001EB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11967 0x00001EBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11968 0x00001EC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11969 0x00001EC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11970 0x00001EC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11971 0x00001ECC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11972 0x00001ED0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11973 0x00001ED4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11974 0x00001ED8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11975 0x00001EDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11976 0x00001EE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11977 0x00001EE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11978 0x00001EE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11979 0x00001EEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11980 0x00001EF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11981 0x00001EF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11982 0x00001EF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11983 0x00001EFC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11984 0x00001F00 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11985 0x00001F04 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11986 0x00001F08 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11987 0x00001F0C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11988 0x00001F10 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11989 0x00001F14 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11990 0x00001F18 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11991 0x00001F1C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11992 0x00001F20 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11993 0x00001F24 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11994 0x00001F28 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11995 0x00001F2C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11996 0x00001F30 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11997 0x00001F34 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11998 0x00001F38 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK11999 0x00001F3C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12000 0x00001F40 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12001 0x00001F44 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12002 0x00001F48 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12003 0x00001F4C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12004 0x00001F50 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12005 0x00001F54 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12006 0x00001F58 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12007 0x00001F5C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12008 0x00001F60 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12009 0x00001F64 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12010 0x00001F68 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12011 0x00001F6C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12012 0x00001F70 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12013 0x00001F74 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12014 0x00001F78 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12015 0x00001F7C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12016 0x00001F80 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12017 0x00001F84 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12018 0x00001F88 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12019 0x00001F8C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12020 0x00001F90 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12021 0x00001F94 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12022 0x00001F98 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12023 0x00001F9C + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12024 0x00001FA0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12025 0x00001FA4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12026 0x00001FA8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12027 0x00001FAC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12028 0x00001FB0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12029 0x00001FB4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12030 0x00001FB8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12031 0x00001FBC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12032 0x00001FC0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12033 0x00001FC4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12034 0x00001FC8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12035 0x00001FCC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12036 0x00001FD0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12037 0x00001FD4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12038 0x00001FD8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12039 0x00001FDC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12040 0x00001FE0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12041 0x00001FE4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12042 0x00001FE8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12043 0x00001FEC + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12044 0x00001FF0 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12045 0x00001FF4 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12046 0x00001FF8 + +// 8 kB ULL SRAM +#define RFC_ULLRAM_O_BANK12047 0x00001FFC + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK10 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK10_DATA_W 32 +#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK10_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11_DATA_W 32 +#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12_DATA_W 32 +#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK13 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK13_DATA_W 32 +#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK13_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK14 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK14_DATA_W 32 +#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK14_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK15 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK15_DATA_W 32 +#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK15_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK16 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK16_DATA_W 32 +#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK16_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK17 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK17_DATA_W 32 +#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK17_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK18 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK18_DATA_W 32 +#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK18_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK19 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK19_DATA_W 32 +#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK19_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK110_DATA_W 32 +#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK111_DATA_W 32 +#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK112_DATA_W 32 +#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK113_DATA_W 32 +#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK114_DATA_W 32 +#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK115_DATA_W 32 +#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK116_DATA_W 32 +#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK117_DATA_W 32 +#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK118_DATA_W 32 +#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK119_DATA_W 32 +#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK120_DATA_W 32 +#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK121_DATA_W 32 +#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK122_DATA_W 32 +#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK123_DATA_W 32 +#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK124_DATA_W 32 +#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK125_DATA_W 32 +#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK126_DATA_W 32 +#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK127_DATA_W 32 +#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK128_DATA_W 32 +#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK129_DATA_W 32 +#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK130_DATA_W 32 +#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK131_DATA_W 32 +#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK132_DATA_W 32 +#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK133_DATA_W 32 +#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK134_DATA_W 32 +#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK135_DATA_W 32 +#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK136_DATA_W 32 +#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK137_DATA_W 32 +#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK138_DATA_W 32 +#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK139_DATA_W 32 +#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK140_DATA_W 32 +#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK141_DATA_W 32 +#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK142_DATA_W 32 +#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK143_DATA_W 32 +#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK144_DATA_W 32 +#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK145_DATA_W 32 +#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK146_DATA_W 32 +#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK147_DATA_W 32 +#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK148_DATA_W 32 +#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK149_DATA_W 32 +#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK150_DATA_W 32 +#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK151_DATA_W 32 +#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK152_DATA_W 32 +#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK153_DATA_W 32 +#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK154_DATA_W 32 +#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK155_DATA_W 32 +#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK156_DATA_W 32 +#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK157_DATA_W 32 +#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK158_DATA_W 32 +#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK159_DATA_W 32 +#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK160_DATA_W 32 +#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK161_DATA_W 32 +#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK162_DATA_W 32 +#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK163_DATA_W 32 +#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK164_DATA_W 32 +#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK165_DATA_W 32 +#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK166_DATA_W 32 +#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK167_DATA_W 32 +#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK168_DATA_W 32 +#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK169_DATA_W 32 +#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK170_DATA_W 32 +#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK171_DATA_W 32 +#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK172_DATA_W 32 +#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK173_DATA_W 32 +#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK174_DATA_W 32 +#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK175_DATA_W 32 +#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK176_DATA_W 32 +#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK177_DATA_W 32 +#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK178_DATA_W 32 +#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK179_DATA_W 32 +#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK180_DATA_W 32 +#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK181_DATA_W 32 +#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK182_DATA_W 32 +#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK183_DATA_W 32 +#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK184_DATA_W 32 +#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK185_DATA_W 32 +#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK186_DATA_W 32 +#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK187_DATA_W 32 +#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK188_DATA_W 32 +#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK189_DATA_W 32 +#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK190_DATA_W 32 +#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK191_DATA_W 32 +#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK192_DATA_W 32 +#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK193_DATA_W 32 +#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK194_DATA_W 32 +#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK195_DATA_W 32 +#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK196_DATA_W 32 +#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK197_DATA_W 32 +#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK198_DATA_W 32 +#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK199_DATA_W 32 +#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1100 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1100_DATA_W 32 +#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1100_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1101 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1101_DATA_W 32 +#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1101_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1102 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1102_DATA_W 32 +#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1102_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1103 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1103_DATA_W 32 +#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1103_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1104 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1104_DATA_W 32 +#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1104_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1105 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1105_DATA_W 32 +#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1105_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1106 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1106_DATA_W 32 +#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1106_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1107 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1107_DATA_W 32 +#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1107_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1108 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1108_DATA_W 32 +#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1108_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1109 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1109_DATA_W 32 +#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1109_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1110_DATA_W 32 +#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1111_DATA_W 32 +#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1112_DATA_W 32 +#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1113_DATA_W 32 +#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1114_DATA_W 32 +#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1115_DATA_W 32 +#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1116_DATA_W 32 +#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1117_DATA_W 32 +#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1118_DATA_W 32 +#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1119_DATA_W 32 +#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1120_DATA_W 32 +#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1121_DATA_W 32 +#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1122_DATA_W 32 +#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1123_DATA_W 32 +#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1124_DATA_W 32 +#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1125_DATA_W 32 +#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1126_DATA_W 32 +#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1127_DATA_W 32 +#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1128_DATA_W 32 +#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1129_DATA_W 32 +#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1130_DATA_W 32 +#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1131_DATA_W 32 +#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1132_DATA_W 32 +#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1133_DATA_W 32 +#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1134_DATA_W 32 +#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1135_DATA_W 32 +#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1136_DATA_W 32 +#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1137_DATA_W 32 +#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1138_DATA_W 32 +#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1139_DATA_W 32 +#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1140_DATA_W 32 +#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1141_DATA_W 32 +#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1142_DATA_W 32 +#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1143_DATA_W 32 +#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1144_DATA_W 32 +#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1145_DATA_W 32 +#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1146_DATA_W 32 +#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1147_DATA_W 32 +#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1148_DATA_W 32 +#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1149_DATA_W 32 +#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1150_DATA_W 32 +#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1151_DATA_W 32 +#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1152_DATA_W 32 +#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1153_DATA_W 32 +#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1154_DATA_W 32 +#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1155_DATA_W 32 +#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1156_DATA_W 32 +#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1157_DATA_W 32 +#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1158_DATA_W 32 +#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1159_DATA_W 32 +#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1160_DATA_W 32 +#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1161_DATA_W 32 +#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1162_DATA_W 32 +#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1163_DATA_W 32 +#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1164_DATA_W 32 +#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1165_DATA_W 32 +#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1166_DATA_W 32 +#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1167_DATA_W 32 +#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1168_DATA_W 32 +#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1169_DATA_W 32 +#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1170_DATA_W 32 +#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1171_DATA_W 32 +#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1172_DATA_W 32 +#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1173_DATA_W 32 +#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1174_DATA_W 32 +#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1175_DATA_W 32 +#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1176_DATA_W 32 +#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1177_DATA_W 32 +#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1178_DATA_W 32 +#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1179_DATA_W 32 +#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1180_DATA_W 32 +#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1181_DATA_W 32 +#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1182_DATA_W 32 +#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1183_DATA_W 32 +#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1184_DATA_W 32 +#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1185_DATA_W 32 +#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1186_DATA_W 32 +#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1187_DATA_W 32 +#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1188_DATA_W 32 +#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1189_DATA_W 32 +#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1190_DATA_W 32 +#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1191_DATA_W 32 +#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1192_DATA_W 32 +#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1193_DATA_W 32 +#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1194_DATA_W 32 +#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1195_DATA_W 32 +#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1196_DATA_W 32 +#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1197_DATA_W 32 +#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1198_DATA_W 32 +#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1199_DATA_W 32 +#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1200 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1200_DATA_W 32 +#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1200_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1201 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1201_DATA_W 32 +#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1201_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1202 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1202_DATA_W 32 +#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1202_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1203 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1203_DATA_W 32 +#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1203_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1204 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1204_DATA_W 32 +#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1204_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1205 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1205_DATA_W 32 +#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1205_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1206 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1206_DATA_W 32 +#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1206_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1207 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1207_DATA_W 32 +#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1207_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1208 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1208_DATA_W 32 +#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1208_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1209 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1209_DATA_W 32 +#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1209_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1210 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1210_DATA_W 32 +#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1210_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1211 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1211_DATA_W 32 +#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1211_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1212 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1212_DATA_W 32 +#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1212_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1213 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1213_DATA_W 32 +#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1213_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1214 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1214_DATA_W 32 +#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1214_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1215 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1215_DATA_W 32 +#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1215_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1216 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1216_DATA_W 32 +#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1216_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1217 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1217_DATA_W 32 +#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1217_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1218 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1218_DATA_W 32 +#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1218_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1219 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1219_DATA_W 32 +#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1219_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1220 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1220_DATA_W 32 +#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1220_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1221 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1221_DATA_W 32 +#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1221_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1222 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1222_DATA_W 32 +#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1222_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1223 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1223_DATA_W 32 +#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1223_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1224 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1224_DATA_W 32 +#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1224_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1225 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1225_DATA_W 32 +#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1225_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1226 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1226_DATA_W 32 +#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1226_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1227 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1227_DATA_W 32 +#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1227_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1228 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1228_DATA_W 32 +#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1228_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1229 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1229_DATA_W 32 +#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1229_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1230 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1230_DATA_W 32 +#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1230_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1231 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1231_DATA_W 32 +#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1231_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1232 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1232_DATA_W 32 +#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1232_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1233 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1233_DATA_W 32 +#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1233_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1234 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1234_DATA_W 32 +#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1234_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1235 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1235_DATA_W 32 +#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1235_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1236 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1236_DATA_W 32 +#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1236_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1237 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1237_DATA_W 32 +#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1237_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1238 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1238_DATA_W 32 +#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1238_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1239 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1239_DATA_W 32 +#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1239_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1240 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1240_DATA_W 32 +#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1240_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1241 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1241_DATA_W 32 +#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1241_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1242 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1242_DATA_W 32 +#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1242_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1243 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1243_DATA_W 32 +#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1243_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1244 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1244_DATA_W 32 +#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1244_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1245 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1245_DATA_W 32 +#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1245_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1246 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1246_DATA_W 32 +#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1246_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1247 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1247_DATA_W 32 +#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1247_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1248 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1248_DATA_W 32 +#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1248_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1249 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1249_DATA_W 32 +#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1249_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1250 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1250_DATA_W 32 +#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1250_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1251 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1251_DATA_W 32 +#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1251_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1252 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1252_DATA_W 32 +#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1252_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1253 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1253_DATA_W 32 +#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1253_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1254 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1254_DATA_W 32 +#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1254_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1255 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1255_DATA_W 32 +#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1255_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1256 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1256_DATA_W 32 +#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1256_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1257 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1257_DATA_W 32 +#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1257_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1258 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1258_DATA_W 32 +#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1258_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1259 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1259_DATA_W 32 +#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1259_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1260 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1260_DATA_W 32 +#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1260_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1261 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1261_DATA_W 32 +#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1261_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1262 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1262_DATA_W 32 +#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1262_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1263 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1263_DATA_W 32 +#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1263_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1264 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1264_DATA_W 32 +#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1264_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1265 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1265_DATA_W 32 +#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1265_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1266 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1266_DATA_W 32 +#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1266_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1267 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1267_DATA_W 32 +#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1267_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1268 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1268_DATA_W 32 +#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1268_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1269 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1269_DATA_W 32 +#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1269_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1270 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1270_DATA_W 32 +#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1270_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1271 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1271_DATA_W 32 +#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1271_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1272 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1272_DATA_W 32 +#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1272_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1273 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1273_DATA_W 32 +#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1273_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1274 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1274_DATA_W 32 +#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1274_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1275 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1275_DATA_W 32 +#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1275_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1276 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1276_DATA_W 32 +#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1276_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1277 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1277_DATA_W 32 +#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1277_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1278 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1278_DATA_W 32 +#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1278_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1279 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1279_DATA_W 32 +#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1279_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1280 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1280_DATA_W 32 +#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1280_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1281 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1281_DATA_W 32 +#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1281_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1282 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1282_DATA_W 32 +#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1282_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1283 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1283_DATA_W 32 +#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1283_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1284 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1284_DATA_W 32 +#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1284_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1285 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1285_DATA_W 32 +#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1285_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1286 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1286_DATA_W 32 +#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1286_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1287 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1287_DATA_W 32 +#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1287_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1288 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1288_DATA_W 32 +#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1288_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1289 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1289_DATA_W 32 +#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1289_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1290 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1290_DATA_W 32 +#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1290_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1291 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1291_DATA_W 32 +#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1291_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1292 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1292_DATA_W 32 +#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1292_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1293 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1293_DATA_W 32 +#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1293_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1294 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1294_DATA_W 32 +#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1294_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1295 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1295_DATA_W 32 +#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1295_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1296 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1296_DATA_W 32 +#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1296_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1297 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1297_DATA_W 32 +#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1297_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1298 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1298_DATA_W 32 +#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1298_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1299 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1299_DATA_W 32 +#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1299_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1300 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1300_DATA_W 32 +#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1300_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1301 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1301_DATA_W 32 +#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1301_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1302 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1302_DATA_W 32 +#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1302_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1303 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1303_DATA_W 32 +#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1303_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1304 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1304_DATA_W 32 +#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1304_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1305 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1305_DATA_W 32 +#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1305_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1306 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1306_DATA_W 32 +#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1306_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1307 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1307_DATA_W 32 +#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1307_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1308 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1308_DATA_W 32 +#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1308_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1309 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1309_DATA_W 32 +#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1309_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1310 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1310_DATA_W 32 +#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1310_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1311 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1311_DATA_W 32 +#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1311_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1312 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1312_DATA_W 32 +#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1312_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1313 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1313_DATA_W 32 +#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1313_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1314 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1314_DATA_W 32 +#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1314_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1315 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1315_DATA_W 32 +#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1315_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1316 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1316_DATA_W 32 +#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1316_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1317 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1317_DATA_W 32 +#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1317_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1318 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1318_DATA_W 32 +#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1318_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1319 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1319_DATA_W 32 +#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1319_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1320 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1320_DATA_W 32 +#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1320_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1321 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1321_DATA_W 32 +#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1321_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1322 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1322_DATA_W 32 +#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1322_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1323 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1323_DATA_W 32 +#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1323_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1324 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1324_DATA_W 32 +#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1324_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1325 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1325_DATA_W 32 +#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1325_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1326 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1326_DATA_W 32 +#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1326_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1327 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1327_DATA_W 32 +#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1327_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1328 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1328_DATA_W 32 +#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1328_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1329 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1329_DATA_W 32 +#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1329_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1330 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1330_DATA_W 32 +#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1330_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1331 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1331_DATA_W 32 +#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1331_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1332 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1332_DATA_W 32 +#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1332_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1333 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1333_DATA_W 32 +#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1333_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1334 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1334_DATA_W 32 +#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1334_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1335 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1335_DATA_W 32 +#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1335_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1336 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1336_DATA_W 32 +#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1336_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1337 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1337_DATA_W 32 +#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1337_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1338 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1338_DATA_W 32 +#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1338_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1339 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1339_DATA_W 32 +#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1339_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1340 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1340_DATA_W 32 +#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1340_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1341 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1341_DATA_W 32 +#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1341_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1342 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1342_DATA_W 32 +#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1342_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1343 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1343_DATA_W 32 +#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1343_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1344 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1344_DATA_W 32 +#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1344_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1345 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1345_DATA_W 32 +#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1345_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1346 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1346_DATA_W 32 +#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1346_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1347 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1347_DATA_W 32 +#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1347_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1348 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1348_DATA_W 32 +#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1348_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1349 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1349_DATA_W 32 +#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1349_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1350 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1350_DATA_W 32 +#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1350_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1351 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1351_DATA_W 32 +#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1351_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1352 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1352_DATA_W 32 +#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1352_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1353 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1353_DATA_W 32 +#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1353_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1354 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1354_DATA_W 32 +#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1354_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1355 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1355_DATA_W 32 +#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1355_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1356 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1356_DATA_W 32 +#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1356_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1357 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1357_DATA_W 32 +#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1357_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1358 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1358_DATA_W 32 +#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1358_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1359 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1359_DATA_W 32 +#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1359_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1360 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1360_DATA_W 32 +#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1360_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1361 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1361_DATA_W 32 +#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1361_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1362 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1362_DATA_W 32 +#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1362_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1363 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1363_DATA_W 32 +#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1363_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1364 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1364_DATA_W 32 +#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1364_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1365 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1365_DATA_W 32 +#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1365_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1366 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1366_DATA_W 32 +#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1366_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1367 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1367_DATA_W 32 +#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1367_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1368 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1368_DATA_W 32 +#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1368_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1369 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1369_DATA_W 32 +#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1369_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1370 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1370_DATA_W 32 +#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1370_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1371 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1371_DATA_W 32 +#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1371_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1372 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1372_DATA_W 32 +#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1372_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1373 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1373_DATA_W 32 +#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1373_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1374 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1374_DATA_W 32 +#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1374_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1375 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1375_DATA_W 32 +#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1375_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1376 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1376_DATA_W 32 +#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1376_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1377 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1377_DATA_W 32 +#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1377_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1378 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1378_DATA_W 32 +#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1378_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1379 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1379_DATA_W 32 +#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1379_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1380 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1380_DATA_W 32 +#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1380_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1381 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1381_DATA_W 32 +#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1381_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1382 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1382_DATA_W 32 +#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1382_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1383 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1383_DATA_W 32 +#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1383_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1384 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1384_DATA_W 32 +#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1384_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1385 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1385_DATA_W 32 +#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1385_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1386 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1386_DATA_W 32 +#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1386_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1387 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1387_DATA_W 32 +#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1387_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1388 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1388_DATA_W 32 +#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1388_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1389 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1389_DATA_W 32 +#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1389_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1390 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1390_DATA_W 32 +#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1390_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1391 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1391_DATA_W 32 +#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1391_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1392 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1392_DATA_W 32 +#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1392_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1393 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1393_DATA_W 32 +#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1393_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1394 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1394_DATA_W 32 +#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1394_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1395 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1395_DATA_W 32 +#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1395_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1396 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1396_DATA_W 32 +#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1396_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1397 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1397_DATA_W 32 +#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1397_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1398 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1398_DATA_W 32 +#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1398_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1399 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1399_DATA_W 32 +#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1399_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1400 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1400_DATA_W 32 +#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1400_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1401 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1401_DATA_W 32 +#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1401_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1402 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1402_DATA_W 32 +#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1402_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1403 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1403_DATA_W 32 +#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1403_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1404 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1404_DATA_W 32 +#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1404_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1405 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1405_DATA_W 32 +#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1405_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1406 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1406_DATA_W 32 +#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1406_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1407 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1407_DATA_W 32 +#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1407_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1408 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1408_DATA_W 32 +#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1408_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1409 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1409_DATA_W 32 +#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1409_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1410 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1410_DATA_W 32 +#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1410_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1411 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1411_DATA_W 32 +#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1411_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1412 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1412_DATA_W 32 +#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1412_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1413 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1413_DATA_W 32 +#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1413_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1414 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1414_DATA_W 32 +#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1414_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1415 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1415_DATA_W 32 +#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1415_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1416 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1416_DATA_W 32 +#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1416_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1417 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1417_DATA_W 32 +#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1417_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1418 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1418_DATA_W 32 +#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1418_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1419 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1419_DATA_W 32 +#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1419_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1420 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1420_DATA_W 32 +#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1420_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1421 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1421_DATA_W 32 +#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1421_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1422 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1422_DATA_W 32 +#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1422_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1423 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1423_DATA_W 32 +#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1423_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1424 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1424_DATA_W 32 +#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1424_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1425 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1425_DATA_W 32 +#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1425_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1426 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1426_DATA_W 32 +#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1426_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1427 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1427_DATA_W 32 +#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1427_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1428 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1428_DATA_W 32 +#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1428_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1429 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1429_DATA_W 32 +#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1429_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1430 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1430_DATA_W 32 +#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1430_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1431 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1431_DATA_W 32 +#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1431_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1432 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1432_DATA_W 32 +#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1432_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1433 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1433_DATA_W 32 +#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1433_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1434 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1434_DATA_W 32 +#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1434_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1435 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1435_DATA_W 32 +#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1435_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1436 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1436_DATA_W 32 +#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1436_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1437 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1437_DATA_W 32 +#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1437_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1438 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1438_DATA_W 32 +#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1438_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1439 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1439_DATA_W 32 +#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1439_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1440 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1440_DATA_W 32 +#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1440_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1441 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1441_DATA_W 32 +#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1441_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1442 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1442_DATA_W 32 +#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1442_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1443 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1443_DATA_W 32 +#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1443_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1444 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1444_DATA_W 32 +#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1444_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1445 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1445_DATA_W 32 +#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1445_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1446 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1446_DATA_W 32 +#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1446_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1447 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1447_DATA_W 32 +#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1447_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1448 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1448_DATA_W 32 +#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1448_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1449 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1449_DATA_W 32 +#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1449_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1450 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1450_DATA_W 32 +#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1450_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1451 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1451_DATA_W 32 +#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1451_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1452 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1452_DATA_W 32 +#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1452_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1453 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1453_DATA_W 32 +#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1453_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1454 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1454_DATA_W 32 +#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1454_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1455 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1455_DATA_W 32 +#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1455_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1456 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1456_DATA_W 32 +#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1456_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1457 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1457_DATA_W 32 +#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1457_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1458 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1458_DATA_W 32 +#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1458_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1459 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1459_DATA_W 32 +#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1459_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1460 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1460_DATA_W 32 +#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1460_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1461 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1461_DATA_W 32 +#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1461_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1462 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1462_DATA_W 32 +#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1462_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1463 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1463_DATA_W 32 +#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1463_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1464 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1464_DATA_W 32 +#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1464_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1465 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1465_DATA_W 32 +#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1465_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1466 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1466_DATA_W 32 +#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1466_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1467 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1467_DATA_W 32 +#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1467_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1468 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1468_DATA_W 32 +#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1468_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1469 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1469_DATA_W 32 +#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1469_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1470 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1470_DATA_W 32 +#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1470_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1471 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1471_DATA_W 32 +#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1471_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1472 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1472_DATA_W 32 +#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1472_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1473 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1473_DATA_W 32 +#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1473_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1474 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1474_DATA_W 32 +#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1474_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1475 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1475_DATA_W 32 +#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1475_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1476 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1476_DATA_W 32 +#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1476_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1477 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1477_DATA_W 32 +#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1477_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1478 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1478_DATA_W 32 +#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1478_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1479 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1479_DATA_W 32 +#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1479_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1480 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1480_DATA_W 32 +#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1480_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1481 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1481_DATA_W 32 +#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1481_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1482 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1482_DATA_W 32 +#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1482_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1483 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1483_DATA_W 32 +#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1483_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1484 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1484_DATA_W 32 +#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1484_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1485 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1485_DATA_W 32 +#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1485_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1486 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1486_DATA_W 32 +#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1486_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1487 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1487_DATA_W 32 +#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1487_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1488 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1488_DATA_W 32 +#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1488_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1489 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1489_DATA_W 32 +#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1489_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1490 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1490_DATA_W 32 +#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1490_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1491 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1491_DATA_W 32 +#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1491_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1492 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1492_DATA_W 32 +#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1492_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1493 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1493_DATA_W 32 +#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1493_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1494 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1494_DATA_W 32 +#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1494_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1495 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1495_DATA_W 32 +#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1495_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1496 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1496_DATA_W 32 +#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1496_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1497 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1497_DATA_W 32 +#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1497_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1498 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1498_DATA_W 32 +#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1498_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1499 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1499_DATA_W 32 +#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1499_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1500 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1500_DATA_W 32 +#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1500_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1501 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1501_DATA_W 32 +#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1501_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1502 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1502_DATA_W 32 +#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1502_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1503 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1503_DATA_W 32 +#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1503_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1504 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1504_DATA_W 32 +#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1504_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1505 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1505_DATA_W 32 +#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1505_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1506 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1506_DATA_W 32 +#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1506_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1507 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1507_DATA_W 32 +#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1507_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1508 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1508_DATA_W 32 +#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1508_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1509 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1509_DATA_W 32 +#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1509_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1510 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1510_DATA_W 32 +#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1510_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1511 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1511_DATA_W 32 +#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1511_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1512 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1512_DATA_W 32 +#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1512_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1513 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1513_DATA_W 32 +#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1513_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1514 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1514_DATA_W 32 +#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1514_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1515 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1515_DATA_W 32 +#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1515_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1516 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1516_DATA_W 32 +#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1516_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1517 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1517_DATA_W 32 +#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1517_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1518 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1518_DATA_W 32 +#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1518_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1519 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1519_DATA_W 32 +#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1519_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1520 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1520_DATA_W 32 +#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1520_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1521 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1521_DATA_W 32 +#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1521_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1522 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1522_DATA_W 32 +#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1522_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1523 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1523_DATA_W 32 +#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1523_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1524 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1524_DATA_W 32 +#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1524_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1525 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1525_DATA_W 32 +#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1525_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1526 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1526_DATA_W 32 +#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1526_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1527 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1527_DATA_W 32 +#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1527_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1528 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1528_DATA_W 32 +#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1528_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1529 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1529_DATA_W 32 +#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1529_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1530 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1530_DATA_W 32 +#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1530_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1531 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1531_DATA_W 32 +#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1531_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1532 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1532_DATA_W 32 +#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1532_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1533 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1533_DATA_W 32 +#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1533_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1534 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1534_DATA_W 32 +#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1534_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1535 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1535_DATA_W 32 +#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1535_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1536 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1536_DATA_W 32 +#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1536_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1537 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1537_DATA_W 32 +#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1537_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1538 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1538_DATA_W 32 +#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1538_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1539 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1539_DATA_W 32 +#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1539_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1540 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1540_DATA_W 32 +#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1540_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1541 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1541_DATA_W 32 +#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1541_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1542 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1542_DATA_W 32 +#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1542_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1543 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1543_DATA_W 32 +#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1543_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1544 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1544_DATA_W 32 +#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1544_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1545 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1545_DATA_W 32 +#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1545_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1546 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1546_DATA_W 32 +#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1546_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1547 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1547_DATA_W 32 +#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1547_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1548 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1548_DATA_W 32 +#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1548_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1549 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1549_DATA_W 32 +#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1549_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1550 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1550_DATA_W 32 +#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1550_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1551 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1551_DATA_W 32 +#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1551_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1552 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1552_DATA_W 32 +#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1552_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1553 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1553_DATA_W 32 +#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1553_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1554 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1554_DATA_W 32 +#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1554_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1555 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1555_DATA_W 32 +#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1555_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1556 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1556_DATA_W 32 +#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1556_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1557 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1557_DATA_W 32 +#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1557_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1558 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1558_DATA_W 32 +#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1558_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1559 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1559_DATA_W 32 +#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1559_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1560 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1560_DATA_W 32 +#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1560_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1561 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1561_DATA_W 32 +#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1561_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1562 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1562_DATA_W 32 +#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1562_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1563 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1563_DATA_W 32 +#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1563_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1564 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1564_DATA_W 32 +#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1564_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1565 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1565_DATA_W 32 +#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1565_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1566 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1566_DATA_W 32 +#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1566_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1567 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1567_DATA_W 32 +#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1567_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1568 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1568_DATA_W 32 +#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1568_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1569 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1569_DATA_W 32 +#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1569_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1570 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1570_DATA_W 32 +#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1570_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1571 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1571_DATA_W 32 +#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1571_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1572 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1572_DATA_W 32 +#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1572_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1573 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1573_DATA_W 32 +#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1573_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1574 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1574_DATA_W 32 +#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1574_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1575 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1575_DATA_W 32 +#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1575_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1576 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1576_DATA_W 32 +#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1576_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1577 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1577_DATA_W 32 +#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1577_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1578 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1578_DATA_W 32 +#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1578_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1579 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1579_DATA_W 32 +#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1579_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1580 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1580_DATA_W 32 +#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1580_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1581 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1581_DATA_W 32 +#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1581_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1582 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1582_DATA_W 32 +#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1582_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1583 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1583_DATA_W 32 +#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1583_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1584 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1584_DATA_W 32 +#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1584_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1585 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1585_DATA_W 32 +#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1585_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1586 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1586_DATA_W 32 +#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1586_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1587 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1587_DATA_W 32 +#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1587_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1588 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1588_DATA_W 32 +#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1588_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1589 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1589_DATA_W 32 +#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1589_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1590 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1590_DATA_W 32 +#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1590_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1591 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1591_DATA_W 32 +#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1591_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1592 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1592_DATA_W 32 +#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1592_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1593 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1593_DATA_W 32 +#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1593_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1594 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1594_DATA_W 32 +#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1594_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1595 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1595_DATA_W 32 +#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1595_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1596 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1596_DATA_W 32 +#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1596_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1597 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1597_DATA_W 32 +#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1597_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1598 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1598_DATA_W 32 +#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1598_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1599 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1599_DATA_W 32 +#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1599_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1600 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1600_DATA_W 32 +#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1600_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1601 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1601_DATA_W 32 +#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1601_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1602 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1602_DATA_W 32 +#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1602_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1603 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1603_DATA_W 32 +#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1603_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1604 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1604_DATA_W 32 +#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1604_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1605 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1605_DATA_W 32 +#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1605_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1606 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1606_DATA_W 32 +#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1606_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1607 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1607_DATA_W 32 +#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1607_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1608 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1608_DATA_W 32 +#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1608_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1609 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1609_DATA_W 32 +#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1609_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1610 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1610_DATA_W 32 +#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1610_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1611 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1611_DATA_W 32 +#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1611_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1612 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1612_DATA_W 32 +#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1612_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1613 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1613_DATA_W 32 +#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1613_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1614 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1614_DATA_W 32 +#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1614_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1615 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1615_DATA_W 32 +#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1615_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1616 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1616_DATA_W 32 +#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1616_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1617 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1617_DATA_W 32 +#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1617_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1618 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1618_DATA_W 32 +#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1618_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1619 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1619_DATA_W 32 +#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1619_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1620 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1620_DATA_W 32 +#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1620_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1621 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1621_DATA_W 32 +#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1621_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1622 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1622_DATA_W 32 +#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1622_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1623 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1623_DATA_W 32 +#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1623_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1624 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1624_DATA_W 32 +#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1624_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1625 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1625_DATA_W 32 +#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1625_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1626 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1626_DATA_W 32 +#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1626_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1627 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1627_DATA_W 32 +#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1627_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1628 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1628_DATA_W 32 +#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1628_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1629 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1629_DATA_W 32 +#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1629_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1630 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1630_DATA_W 32 +#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1630_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1631 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1631_DATA_W 32 +#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1631_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1632 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1632_DATA_W 32 +#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1632_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1633 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1633_DATA_W 32 +#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1633_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1634 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1634_DATA_W 32 +#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1634_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1635 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1635_DATA_W 32 +#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1635_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1636 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1636_DATA_W 32 +#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1636_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1637 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1637_DATA_W 32 +#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1637_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1638 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1638_DATA_W 32 +#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1638_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1639 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1639_DATA_W 32 +#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1639_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1640 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1640_DATA_W 32 +#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1640_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1641 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1641_DATA_W 32 +#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1641_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1642 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1642_DATA_W 32 +#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1642_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1643 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1643_DATA_W 32 +#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1643_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1644 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1644_DATA_W 32 +#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1644_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1645 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1645_DATA_W 32 +#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1645_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1646 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1646_DATA_W 32 +#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1646_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1647 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1647_DATA_W 32 +#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1647_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1648 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1648_DATA_W 32 +#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1648_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1649 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1649_DATA_W 32 +#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1649_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1650 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1650_DATA_W 32 +#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1650_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1651 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1651_DATA_W 32 +#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1651_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1652 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1652_DATA_W 32 +#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1652_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1653 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1653_DATA_W 32 +#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1653_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1654 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1654_DATA_W 32 +#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1654_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1655 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1655_DATA_W 32 +#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1655_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1656 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1656_DATA_W 32 +#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1656_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1657 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1657_DATA_W 32 +#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1657_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1658 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1658_DATA_W 32 +#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1658_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1659 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1659_DATA_W 32 +#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1659_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1660 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1660_DATA_W 32 +#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1660_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1661 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1661_DATA_W 32 +#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1661_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1662 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1662_DATA_W 32 +#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1662_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1663 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1663_DATA_W 32 +#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1663_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1664 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1664_DATA_W 32 +#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1664_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1665 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1665_DATA_W 32 +#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1665_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1666 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1666_DATA_W 32 +#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1666_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1667 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1667_DATA_W 32 +#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1667_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1668 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1668_DATA_W 32 +#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1668_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1669 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1669_DATA_W 32 +#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1669_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1670 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1670_DATA_W 32 +#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1670_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1671 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1671_DATA_W 32 +#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1671_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1672 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1672_DATA_W 32 +#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1672_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1673 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1673_DATA_W 32 +#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1673_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1674 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1674_DATA_W 32 +#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1674_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1675 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1675_DATA_W 32 +#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1675_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1676 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1676_DATA_W 32 +#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1676_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1677 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1677_DATA_W 32 +#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1677_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1678 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1678_DATA_W 32 +#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1678_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1679 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1679_DATA_W 32 +#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1679_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1680 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1680_DATA_W 32 +#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1680_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1681 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1681_DATA_W 32 +#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1681_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1682 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1682_DATA_W 32 +#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1682_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1683 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1683_DATA_W 32 +#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1683_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1684 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1684_DATA_W 32 +#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1684_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1685 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1685_DATA_W 32 +#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1685_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1686 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1686_DATA_W 32 +#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1686_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1687 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1687_DATA_W 32 +#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1687_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1688 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1688_DATA_W 32 +#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1688_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1689 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1689_DATA_W 32 +#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1689_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1690 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1690_DATA_W 32 +#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1690_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1691 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1691_DATA_W 32 +#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1691_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1692 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1692_DATA_W 32 +#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1692_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1693 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1693_DATA_W 32 +#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1693_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1694 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1694_DATA_W 32 +#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1694_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1695 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1695_DATA_W 32 +#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1695_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1696 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1696_DATA_W 32 +#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1696_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1697 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1697_DATA_W 32 +#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1697_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1698 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1698_DATA_W 32 +#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1698_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1699 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1699_DATA_W 32 +#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1699_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1700 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1700_DATA_W 32 +#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1700_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1701 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1701_DATA_W 32 +#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1701_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1702 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1702_DATA_W 32 +#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1702_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1703 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1703_DATA_W 32 +#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1703_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1704 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1704_DATA_W 32 +#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1704_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1705 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1705_DATA_W 32 +#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1705_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1706 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1706_DATA_W 32 +#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1706_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1707 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1707_DATA_W 32 +#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1707_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1708 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1708_DATA_W 32 +#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1708_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1709 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1709_DATA_W 32 +#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1709_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1710 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1710_DATA_W 32 +#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1710_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1711 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1711_DATA_W 32 +#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1711_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1712 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1712_DATA_W 32 +#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1712_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1713 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1713_DATA_W 32 +#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1713_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1714 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1714_DATA_W 32 +#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1714_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1715 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1715_DATA_W 32 +#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1715_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1716 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1716_DATA_W 32 +#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1716_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1717 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1717_DATA_W 32 +#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1717_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1718 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1718_DATA_W 32 +#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1718_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1719 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1719_DATA_W 32 +#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1719_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1720 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1720_DATA_W 32 +#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1720_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1721 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1721_DATA_W 32 +#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1721_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1722 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1722_DATA_W 32 +#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1722_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1723 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1723_DATA_W 32 +#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1723_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1724 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1724_DATA_W 32 +#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1724_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1725 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1725_DATA_W 32 +#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1725_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1726 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1726_DATA_W 32 +#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1726_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1727 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1727_DATA_W 32 +#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1727_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1728 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1728_DATA_W 32 +#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1728_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1729 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1729_DATA_W 32 +#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1729_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1730 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1730_DATA_W 32 +#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1730_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1731 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1731_DATA_W 32 +#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1731_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1732 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1732_DATA_W 32 +#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1732_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1733 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1733_DATA_W 32 +#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1733_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1734 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1734_DATA_W 32 +#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1734_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1735 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1735_DATA_W 32 +#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1735_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1736 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1736_DATA_W 32 +#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1736_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1737 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1737_DATA_W 32 +#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1737_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1738 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1738_DATA_W 32 +#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1738_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1739 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1739_DATA_W 32 +#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1739_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1740 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1740_DATA_W 32 +#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1740_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1741 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1741_DATA_W 32 +#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1741_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1742 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1742_DATA_W 32 +#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1742_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1743 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1743_DATA_W 32 +#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1743_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1744 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1744_DATA_W 32 +#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1744_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1745 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1745_DATA_W 32 +#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1745_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1746 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1746_DATA_W 32 +#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1746_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1747 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1747_DATA_W 32 +#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1747_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1748 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1748_DATA_W 32 +#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1748_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1749 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1749_DATA_W 32 +#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1749_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1750 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1750_DATA_W 32 +#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1750_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1751 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1751_DATA_W 32 +#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1751_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1752 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1752_DATA_W 32 +#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1752_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1753 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1753_DATA_W 32 +#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1753_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1754 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1754_DATA_W 32 +#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1754_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1755 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1755_DATA_W 32 +#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1755_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1756 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1756_DATA_W 32 +#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1756_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1757 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1757_DATA_W 32 +#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1757_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1758 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1758_DATA_W 32 +#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1758_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1759 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1759_DATA_W 32 +#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1759_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1760 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1760_DATA_W 32 +#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1760_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1761 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1761_DATA_W 32 +#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1761_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1762 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1762_DATA_W 32 +#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1762_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1763 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1763_DATA_W 32 +#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1763_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1764 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1764_DATA_W 32 +#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1764_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1765 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1765_DATA_W 32 +#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1765_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1766 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1766_DATA_W 32 +#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1766_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1767 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1767_DATA_W 32 +#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1767_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1768 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1768_DATA_W 32 +#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1768_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1769 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1769_DATA_W 32 +#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1769_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1770 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1770_DATA_W 32 +#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1770_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1771 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1771_DATA_W 32 +#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1771_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1772 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1772_DATA_W 32 +#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1772_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1773 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1773_DATA_W 32 +#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1773_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1774 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1774_DATA_W 32 +#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1774_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1775 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1775_DATA_W 32 +#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1775_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1776 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1776_DATA_W 32 +#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1776_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1777 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1777_DATA_W 32 +#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1777_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1778 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1778_DATA_W 32 +#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1778_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1779 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1779_DATA_W 32 +#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1779_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1780 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1780_DATA_W 32 +#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1780_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1781 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1781_DATA_W 32 +#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1781_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1782 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1782_DATA_W 32 +#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1782_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1783 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1783_DATA_W 32 +#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1783_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1784 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1784_DATA_W 32 +#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1784_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1785 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1785_DATA_W 32 +#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1785_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1786 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1786_DATA_W 32 +#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1786_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1787 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1787_DATA_W 32 +#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1787_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1788 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1788_DATA_W 32 +#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1788_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1789 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1789_DATA_W 32 +#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1789_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1790 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1790_DATA_W 32 +#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1790_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1791 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1791_DATA_W 32 +#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1791_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1792 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1792_DATA_W 32 +#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1792_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1793 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1793_DATA_W 32 +#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1793_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1794 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1794_DATA_W 32 +#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1794_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1795 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1795_DATA_W 32 +#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1795_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1796 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1796_DATA_W 32 +#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1796_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1797 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1797_DATA_W 32 +#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1797_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1798 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1798_DATA_W 32 +#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1798_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1799 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1799_DATA_W 32 +#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1799_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1800 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1800_DATA_W 32 +#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1800_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1801 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1801_DATA_W 32 +#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1801_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1802 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1802_DATA_W 32 +#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1802_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1803 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1803_DATA_W 32 +#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1803_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1804 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1804_DATA_W 32 +#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1804_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1805 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1805_DATA_W 32 +#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1805_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1806 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1806_DATA_W 32 +#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1806_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1807 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1807_DATA_W 32 +#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1807_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1808 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1808_DATA_W 32 +#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1808_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1809 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1809_DATA_W 32 +#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1809_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1810 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1810_DATA_W 32 +#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1810_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1811 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1811_DATA_W 32 +#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1811_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1812 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1812_DATA_W 32 +#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1812_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1813 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1813_DATA_W 32 +#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1813_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1814 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1814_DATA_W 32 +#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1814_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1815 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1815_DATA_W 32 +#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1815_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1816 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1816_DATA_W 32 +#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1816_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1817 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1817_DATA_W 32 +#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1817_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1818 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1818_DATA_W 32 +#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1818_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1819 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1819_DATA_W 32 +#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1819_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1820 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1820_DATA_W 32 +#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1820_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1821 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1821_DATA_W 32 +#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1821_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1822 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1822_DATA_W 32 +#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1822_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1823 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1823_DATA_W 32 +#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1823_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1824 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1824_DATA_W 32 +#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1824_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1825 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1825_DATA_W 32 +#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1825_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1826 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1826_DATA_W 32 +#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1826_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1827 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1827_DATA_W 32 +#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1827_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1828 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1828_DATA_W 32 +#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1828_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1829 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1829_DATA_W 32 +#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1829_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1830 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1830_DATA_W 32 +#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1830_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1831 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1831_DATA_W 32 +#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1831_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1832 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1832_DATA_W 32 +#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1832_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1833 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1833_DATA_W 32 +#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1833_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1834 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1834_DATA_W 32 +#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1834_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1835 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1835_DATA_W 32 +#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1835_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1836 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1836_DATA_W 32 +#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1836_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1837 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1837_DATA_W 32 +#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1837_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1838 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1838_DATA_W 32 +#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1838_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1839 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1839_DATA_W 32 +#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1839_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1840 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1840_DATA_W 32 +#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1840_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1841 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1841_DATA_W 32 +#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1841_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1842 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1842_DATA_W 32 +#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1842_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1843 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1843_DATA_W 32 +#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1843_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1844 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1844_DATA_W 32 +#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1844_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1845 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1845_DATA_W 32 +#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1845_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1846 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1846_DATA_W 32 +#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1846_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1847 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1847_DATA_W 32 +#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1847_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1848 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1848_DATA_W 32 +#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1848_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1849 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1849_DATA_W 32 +#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1849_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1850 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1850_DATA_W 32 +#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1850_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1851 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1851_DATA_W 32 +#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1851_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1852 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1852_DATA_W 32 +#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1852_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1853 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1853_DATA_W 32 +#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1853_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1854 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1854_DATA_W 32 +#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1854_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1855 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1855_DATA_W 32 +#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1855_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1856 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1856_DATA_W 32 +#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1856_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1857 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1857_DATA_W 32 +#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1857_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1858 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1858_DATA_W 32 +#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1858_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1859 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1859_DATA_W 32 +#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1859_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1860 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1860_DATA_W 32 +#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1860_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1861 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1861_DATA_W 32 +#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1861_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1862 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1862_DATA_W 32 +#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1862_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1863 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1863_DATA_W 32 +#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1863_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1864 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1864_DATA_W 32 +#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1864_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1865 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1865_DATA_W 32 +#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1865_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1866 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1866_DATA_W 32 +#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1866_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1867 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1867_DATA_W 32 +#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1867_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1868 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1868_DATA_W 32 +#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1868_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1869 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1869_DATA_W 32 +#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1869_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1870 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1870_DATA_W 32 +#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1870_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1871 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1871_DATA_W 32 +#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1871_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1872 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1872_DATA_W 32 +#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1872_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1873 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1873_DATA_W 32 +#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1873_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1874 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1874_DATA_W 32 +#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1874_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1875 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1875_DATA_W 32 +#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1875_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1876 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1876_DATA_W 32 +#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1876_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1877 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1877_DATA_W 32 +#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1877_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1878 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1878_DATA_W 32 +#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1878_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1879 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1879_DATA_W 32 +#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1879_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1880 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1880_DATA_W 32 +#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1880_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1881 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1881_DATA_W 32 +#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1881_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1882 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1882_DATA_W 32 +#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1882_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1883 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1883_DATA_W 32 +#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1883_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1884 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1884_DATA_W 32 +#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1884_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1885 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1885_DATA_W 32 +#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1885_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1886 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1886_DATA_W 32 +#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1886_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1887 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1887_DATA_W 32 +#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1887_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1888 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1888_DATA_W 32 +#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1888_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1889 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1889_DATA_W 32 +#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1889_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1890 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1890_DATA_W 32 +#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1890_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1891 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1891_DATA_W 32 +#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1891_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1892 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1892_DATA_W 32 +#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1892_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1893 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1893_DATA_W 32 +#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1893_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1894 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1894_DATA_W 32 +#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1894_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1895 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1895_DATA_W 32 +#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1895_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1896 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1896_DATA_W 32 +#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1896_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1897 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1897_DATA_W 32 +#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1897_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1898 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1898_DATA_W 32 +#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1898_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1899 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1899_DATA_W 32 +#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1899_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1900 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1900_DATA_W 32 +#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1900_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1901 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1901_DATA_W 32 +#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1901_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1902 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1902_DATA_W 32 +#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1902_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1903 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1903_DATA_W 32 +#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1903_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1904 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1904_DATA_W 32 +#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1904_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1905 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1905_DATA_W 32 +#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1905_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1906 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1906_DATA_W 32 +#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1906_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1907 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1907_DATA_W 32 +#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1907_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1908 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1908_DATA_W 32 +#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1908_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1909 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1909_DATA_W 32 +#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1909_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1910 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1910_DATA_W 32 +#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1910_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1911 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1911_DATA_W 32 +#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1911_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1912 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1912_DATA_W 32 +#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1912_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1913 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1913_DATA_W 32 +#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1913_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1914 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1914_DATA_W 32 +#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1914_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1915 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1915_DATA_W 32 +#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1915_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1916 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1916_DATA_W 32 +#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1916_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1917 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1917_DATA_W 32 +#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1917_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1918 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1918_DATA_W 32 +#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1918_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1919 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1919_DATA_W 32 +#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1919_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1920 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1920_DATA_W 32 +#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1920_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1921 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1921_DATA_W 32 +#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1921_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1922 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1922_DATA_W 32 +#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1922_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1923 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1923_DATA_W 32 +#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1923_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1924 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1924_DATA_W 32 +#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1924_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1925 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1925_DATA_W 32 +#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1925_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1926 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1926_DATA_W 32 +#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1926_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1927 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1927_DATA_W 32 +#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1927_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1928 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1928_DATA_W 32 +#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1928_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1929 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1929_DATA_W 32 +#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1929_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1930 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1930_DATA_W 32 +#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1930_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1931 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1931_DATA_W 32 +#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1931_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1932 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1932_DATA_W 32 +#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1932_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1933 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1933_DATA_W 32 +#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1933_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1934 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1934_DATA_W 32 +#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1934_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1935 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1935_DATA_W 32 +#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1935_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1936 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1936_DATA_W 32 +#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1936_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1937 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1937_DATA_W 32 +#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1937_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1938 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1938_DATA_W 32 +#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1938_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1939 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1939_DATA_W 32 +#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1939_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1940 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1940_DATA_W 32 +#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1940_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1941 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1941_DATA_W 32 +#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1941_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1942 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1942_DATA_W 32 +#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1942_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1943 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1943_DATA_W 32 +#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1943_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1944 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1944_DATA_W 32 +#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1944_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1945 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1945_DATA_W 32 +#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1945_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1946 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1946_DATA_W 32 +#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1946_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1947 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1947_DATA_W 32 +#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1947_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1948 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1948_DATA_W 32 +#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1948_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1949 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1949_DATA_W 32 +#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1949_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1950 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1950_DATA_W 32 +#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1950_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1951 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1951_DATA_W 32 +#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1951_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1952 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1952_DATA_W 32 +#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1952_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1953 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1953_DATA_W 32 +#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1953_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1954 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1954_DATA_W 32 +#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1954_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1955 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1955_DATA_W 32 +#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1955_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1956 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1956_DATA_W 32 +#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1956_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1957 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1957_DATA_W 32 +#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1957_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1958 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1958_DATA_W 32 +#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1958_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1959 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1959_DATA_W 32 +#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1959_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1960 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1960_DATA_W 32 +#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1960_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1961 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1961_DATA_W 32 +#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1961_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1962 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1962_DATA_W 32 +#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1962_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1963 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1963_DATA_W 32 +#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1963_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1964 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1964_DATA_W 32 +#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1964_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1965 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1965_DATA_W 32 +#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1965_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1966 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1966_DATA_W 32 +#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1966_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1967 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1967_DATA_W 32 +#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1967_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1968 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1968_DATA_W 32 +#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1968_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1969 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1969_DATA_W 32 +#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1969_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1970 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1970_DATA_W 32 +#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1970_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1971 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1971_DATA_W 32 +#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1971_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1972 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1972_DATA_W 32 +#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1972_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1973 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1973_DATA_W 32 +#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1973_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1974 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1974_DATA_W 32 +#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1974_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1975 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1975_DATA_W 32 +#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1975_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1976 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1976_DATA_W 32 +#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1976_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1977 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1977_DATA_W 32 +#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1977_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1978 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1978_DATA_W 32 +#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1978_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1979 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1979_DATA_W 32 +#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1979_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1980 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1980_DATA_W 32 +#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1980_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1981 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1981_DATA_W 32 +#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1981_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1982 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1982_DATA_W 32 +#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1982_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1983 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1983_DATA_W 32 +#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1983_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1984 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1984_DATA_W 32 +#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1984_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1985 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1985_DATA_W 32 +#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1985_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1986 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1986_DATA_W 32 +#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1986_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1987 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1987_DATA_W 32 +#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1987_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1988 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1988_DATA_W 32 +#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1988_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1989 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1989_DATA_W 32 +#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1989_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1990 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1990_DATA_W 32 +#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1990_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1991 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1991_DATA_W 32 +#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1991_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1992 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1992_DATA_W 32 +#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1992_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1993 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1993_DATA_W 32 +#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1993_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1994 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1994_DATA_W 32 +#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1994_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1995 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1995_DATA_W 32 +#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1995_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1996 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1996_DATA_W 32 +#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1996_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1997 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1997_DATA_W 32 +#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1997_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1998 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1998_DATA_W 32 +#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1998_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK1999 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK1999_DATA_W 32 +#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1999_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11000 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11000_DATA_W 32 +#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11000_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11001 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11001_DATA_W 32 +#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11001_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11002 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11002_DATA_W 32 +#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11002_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11003 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11003_DATA_W 32 +#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11003_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11004 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11004_DATA_W 32 +#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11004_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11005 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11005_DATA_W 32 +#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11005_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11006 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11006_DATA_W 32 +#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11006_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11007 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11007_DATA_W 32 +#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11007_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11008 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11008_DATA_W 32 +#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11008_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11009 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11009_DATA_W 32 +#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11009_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11010 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11010_DATA_W 32 +#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11010_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11011 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11011_DATA_W 32 +#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11011_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11012 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11012_DATA_W 32 +#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11012_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11013 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11013_DATA_W 32 +#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11013_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11014 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11014_DATA_W 32 +#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11014_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11015 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11015_DATA_W 32 +#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11015_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11016 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11016_DATA_W 32 +#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11016_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11017 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11017_DATA_W 32 +#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11017_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11018 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11018_DATA_W 32 +#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11018_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11019 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11019_DATA_W 32 +#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11019_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11020 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11020_DATA_W 32 +#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11020_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11021 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11021_DATA_W 32 +#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11021_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11022 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11022_DATA_W 32 +#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11022_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11023 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11023_DATA_W 32 +#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11023_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11024 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11024_DATA_W 32 +#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11024_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11025 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11025_DATA_W 32 +#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11025_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11026 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11026_DATA_W 32 +#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11026_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11027 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11027_DATA_W 32 +#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11027_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11028 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11028_DATA_W 32 +#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11028_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11029 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11029_DATA_W 32 +#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11029_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11030 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11030_DATA_W 32 +#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11030_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11031 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11031_DATA_W 32 +#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11031_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11032 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11032_DATA_W 32 +#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11032_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11033 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11033_DATA_W 32 +#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11033_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11034 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11034_DATA_W 32 +#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11034_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11035 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11035_DATA_W 32 +#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11035_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11036 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11036_DATA_W 32 +#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11036_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11037 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11037_DATA_W 32 +#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11037_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11038 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11038_DATA_W 32 +#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11038_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11039 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11039_DATA_W 32 +#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11039_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11040 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11040_DATA_W 32 +#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11040_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11041 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11041_DATA_W 32 +#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11041_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11042 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11042_DATA_W 32 +#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11042_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11043 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11043_DATA_W 32 +#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11043_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11044 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11044_DATA_W 32 +#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11044_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11045 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11045_DATA_W 32 +#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11045_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11046 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11046_DATA_W 32 +#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11046_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11047 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11047_DATA_W 32 +#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11047_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11048 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11048_DATA_W 32 +#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11048_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11049 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11049_DATA_W 32 +#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11049_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11050 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11050_DATA_W 32 +#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11050_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11051 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11051_DATA_W 32 +#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11051_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11052 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11052_DATA_W 32 +#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11052_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11053 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11053_DATA_W 32 +#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11053_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11054 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11054_DATA_W 32 +#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11054_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11055 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11055_DATA_W 32 +#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11055_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11056 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11056_DATA_W 32 +#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11056_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11057 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11057_DATA_W 32 +#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11057_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11058 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11058_DATA_W 32 +#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11058_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11059 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11059_DATA_W 32 +#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11059_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11060 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11060_DATA_W 32 +#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11060_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11061 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11061_DATA_W 32 +#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11061_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11062 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11062_DATA_W 32 +#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11062_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11063 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11063_DATA_W 32 +#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11063_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11064 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11064_DATA_W 32 +#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11064_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11065 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11065_DATA_W 32 +#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11065_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11066 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11066_DATA_W 32 +#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11066_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11067 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11067_DATA_W 32 +#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11067_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11068 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11068_DATA_W 32 +#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11068_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11069 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11069_DATA_W 32 +#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11069_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11070 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11070_DATA_W 32 +#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11070_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11071 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11071_DATA_W 32 +#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11071_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11072 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11072_DATA_W 32 +#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11072_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11073 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11073_DATA_W 32 +#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11073_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11074 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11074_DATA_W 32 +#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11074_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11075 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11075_DATA_W 32 +#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11075_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11076 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11076_DATA_W 32 +#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11076_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11077 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11077_DATA_W 32 +#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11077_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11078 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11078_DATA_W 32 +#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11078_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11079 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11079_DATA_W 32 +#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11079_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11080 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11080_DATA_W 32 +#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11080_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11081 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11081_DATA_W 32 +#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11081_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11082 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11082_DATA_W 32 +#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11082_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11083 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11083_DATA_W 32 +#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11083_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11084 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11084_DATA_W 32 +#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11084_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11085 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11085_DATA_W 32 +#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11085_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11086 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11086_DATA_W 32 +#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11086_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11087 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11087_DATA_W 32 +#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11087_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11088 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11088_DATA_W 32 +#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11088_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11089 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11089_DATA_W 32 +#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11089_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11090 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11090_DATA_W 32 +#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11090_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11091 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11091_DATA_W 32 +#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11091_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11092 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11092_DATA_W 32 +#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11092_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11093 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11093_DATA_W 32 +#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11093_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11094 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11094_DATA_W 32 +#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11094_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11095 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11095_DATA_W 32 +#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11095_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11096 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11096_DATA_W 32 +#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11096_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11097 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11097_DATA_W 32 +#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11097_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11098 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11098_DATA_W 32 +#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11098_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11099 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11099_DATA_W 32 +#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11099_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11100 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11100_DATA_W 32 +#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11100_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11101 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11101_DATA_W 32 +#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11101_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11102 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11102_DATA_W 32 +#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11102_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11103 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11103_DATA_W 32 +#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11103_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11104 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11104_DATA_W 32 +#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11104_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11105 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11105_DATA_W 32 +#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11105_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11106 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11106_DATA_W 32 +#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11106_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11107 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11107_DATA_W 32 +#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11107_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11108 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11108_DATA_W 32 +#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11108_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11109 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11109_DATA_W 32 +#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11109_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11110 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11110_DATA_W 32 +#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11110_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11111 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11111_DATA_W 32 +#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11111_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11112 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11112_DATA_W 32 +#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11112_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11113 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11113_DATA_W 32 +#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11113_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11114 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11114_DATA_W 32 +#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11114_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11115 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11115_DATA_W 32 +#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11115_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11116 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11116_DATA_W 32 +#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11116_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11117 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11117_DATA_W 32 +#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11117_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11118 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11118_DATA_W 32 +#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11118_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11119 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11119_DATA_W 32 +#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11119_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11120 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11120_DATA_W 32 +#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11120_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11121 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11121_DATA_W 32 +#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11121_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11122 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11122_DATA_W 32 +#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11122_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11123 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11123_DATA_W 32 +#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11123_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11124 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11124_DATA_W 32 +#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11124_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11125 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11125_DATA_W 32 +#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11125_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11126 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11126_DATA_W 32 +#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11126_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11127 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11127_DATA_W 32 +#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11127_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11128 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11128_DATA_W 32 +#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11128_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11129 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11129_DATA_W 32 +#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11129_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11130 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11130_DATA_W 32 +#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11130_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11131 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11131_DATA_W 32 +#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11131_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11132 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11132_DATA_W 32 +#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11132_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11133 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11133_DATA_W 32 +#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11133_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11134 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11134_DATA_W 32 +#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11134_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11135 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11135_DATA_W 32 +#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11135_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11136 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11136_DATA_W 32 +#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11136_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11137 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11137_DATA_W 32 +#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11137_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11138 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11138_DATA_W 32 +#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11138_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11139 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11139_DATA_W 32 +#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11139_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11140 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11140_DATA_W 32 +#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11140_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11141 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11141_DATA_W 32 +#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11141_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11142 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11142_DATA_W 32 +#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11142_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11143 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11143_DATA_W 32 +#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11143_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11144 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11144_DATA_W 32 +#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11144_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11145 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11145_DATA_W 32 +#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11145_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11146 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11146_DATA_W 32 +#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11146_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11147 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11147_DATA_W 32 +#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11147_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11148 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11148_DATA_W 32 +#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11148_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11149 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11149_DATA_W 32 +#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11149_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11150 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11150_DATA_W 32 +#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11150_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11151 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11151_DATA_W 32 +#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11151_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11152 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11152_DATA_W 32 +#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11152_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11153 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11153_DATA_W 32 +#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11153_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11154 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11154_DATA_W 32 +#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11154_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11155 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11155_DATA_W 32 +#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11155_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11156 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11156_DATA_W 32 +#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11156_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11157 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11157_DATA_W 32 +#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11157_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11158 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11158_DATA_W 32 +#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11158_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11159 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11159_DATA_W 32 +#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11159_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11160 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11160_DATA_W 32 +#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11160_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11161 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11161_DATA_W 32 +#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11161_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11162 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11162_DATA_W 32 +#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11162_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11163 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11163_DATA_W 32 +#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11163_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11164 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11164_DATA_W 32 +#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11164_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11165 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11165_DATA_W 32 +#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11165_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11166 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11166_DATA_W 32 +#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11166_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11167 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11167_DATA_W 32 +#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11167_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11168 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11168_DATA_W 32 +#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11168_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11169 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11169_DATA_W 32 +#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11169_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11170 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11170_DATA_W 32 +#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11170_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11171 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11171_DATA_W 32 +#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11171_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11172 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11172_DATA_W 32 +#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11172_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11173 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11173_DATA_W 32 +#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11173_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11174 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11174_DATA_W 32 +#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11174_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11175 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11175_DATA_W 32 +#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11175_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11176 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11176_DATA_W 32 +#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11176_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11177 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11177_DATA_W 32 +#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11177_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11178 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11178_DATA_W 32 +#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11178_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11179 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11179_DATA_W 32 +#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11179_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11180 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11180_DATA_W 32 +#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11180_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11181 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11181_DATA_W 32 +#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11181_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11182 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11182_DATA_W 32 +#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11182_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11183 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11183_DATA_W 32 +#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11183_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11184 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11184_DATA_W 32 +#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11184_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11185 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11185_DATA_W 32 +#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11185_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11186 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11186_DATA_W 32 +#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11186_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11187 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11187_DATA_W 32 +#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11187_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11188 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11188_DATA_W 32 +#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11188_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11189 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11189_DATA_W 32 +#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11189_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11190 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11190_DATA_W 32 +#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11190_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11191 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11191_DATA_W 32 +#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11191_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11192 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11192_DATA_W 32 +#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11192_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11193 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11193_DATA_W 32 +#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11193_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11194 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11194_DATA_W 32 +#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11194_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11195 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11195_DATA_W 32 +#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11195_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11196 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11196_DATA_W 32 +#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11196_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11197 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11197_DATA_W 32 +#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11197_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11198 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11198_DATA_W 32 +#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11198_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11199 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11199_DATA_W 32 +#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11199_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11200 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11200_DATA_W 32 +#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11200_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11201 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11201_DATA_W 32 +#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11201_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11202 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11202_DATA_W 32 +#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11202_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11203 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11203_DATA_W 32 +#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11203_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11204 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11204_DATA_W 32 +#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11204_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11205 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11205_DATA_W 32 +#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11205_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11206 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11206_DATA_W 32 +#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11206_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11207 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11207_DATA_W 32 +#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11207_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11208 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11208_DATA_W 32 +#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11208_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11209 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11209_DATA_W 32 +#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11209_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11210 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11210_DATA_W 32 +#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11210_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11211 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11211_DATA_W 32 +#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11211_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11212 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11212_DATA_W 32 +#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11212_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11213 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11213_DATA_W 32 +#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11213_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11214 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11214_DATA_W 32 +#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11214_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11215 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11215_DATA_W 32 +#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11215_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11216 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11216_DATA_W 32 +#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11216_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11217 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11217_DATA_W 32 +#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11217_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11218 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11218_DATA_W 32 +#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11218_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11219 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11219_DATA_W 32 +#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11219_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11220 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11220_DATA_W 32 +#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11220_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11221 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11221_DATA_W 32 +#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11221_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11222 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11222_DATA_W 32 +#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11222_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11223 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11223_DATA_W 32 +#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11223_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11224 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11224_DATA_W 32 +#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11224_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11225 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11225_DATA_W 32 +#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11225_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11226 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11226_DATA_W 32 +#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11226_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11227 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11227_DATA_W 32 +#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11227_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11228 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11228_DATA_W 32 +#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11228_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11229 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11229_DATA_W 32 +#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11229_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11230 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11230_DATA_W 32 +#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11230_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11231 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11231_DATA_W 32 +#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11231_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11232 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11232_DATA_W 32 +#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11232_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11233 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11233_DATA_W 32 +#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11233_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11234 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11234_DATA_W 32 +#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11234_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11235 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11235_DATA_W 32 +#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11235_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11236 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11236_DATA_W 32 +#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11236_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11237 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11237_DATA_W 32 +#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11237_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11238 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11238_DATA_W 32 +#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11238_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11239 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11239_DATA_W 32 +#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11239_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11240 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11240_DATA_W 32 +#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11240_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11241 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11241_DATA_W 32 +#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11241_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11242 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11242_DATA_W 32 +#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11242_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11243 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11243_DATA_W 32 +#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11243_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11244 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11244_DATA_W 32 +#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11244_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11245 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11245_DATA_W 32 +#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11245_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11246 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11246_DATA_W 32 +#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11246_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11247 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11247_DATA_W 32 +#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11247_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11248 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11248_DATA_W 32 +#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11248_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11249 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11249_DATA_W 32 +#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11249_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11250 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11250_DATA_W 32 +#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11250_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11251 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11251_DATA_W 32 +#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11251_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11252 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11252_DATA_W 32 +#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11252_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11253 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11253_DATA_W 32 +#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11253_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11254 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11254_DATA_W 32 +#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11254_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11255 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11255_DATA_W 32 +#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11255_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11256 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11256_DATA_W 32 +#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11256_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11257 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11257_DATA_W 32 +#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11257_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11258 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11258_DATA_W 32 +#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11258_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11259 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11259_DATA_W 32 +#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11259_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11260 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11260_DATA_W 32 +#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11260_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11261 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11261_DATA_W 32 +#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11261_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11262 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11262_DATA_W 32 +#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11262_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11263 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11263_DATA_W 32 +#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11263_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11264 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11264_DATA_W 32 +#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11264_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11265 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11265_DATA_W 32 +#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11265_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11266 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11266_DATA_W 32 +#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11266_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11267 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11267_DATA_W 32 +#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11267_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11268 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11268_DATA_W 32 +#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11268_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11269 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11269_DATA_W 32 +#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11269_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11270 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11270_DATA_W 32 +#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11270_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11271 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11271_DATA_W 32 +#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11271_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11272 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11272_DATA_W 32 +#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11272_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11273 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11273_DATA_W 32 +#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11273_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11274 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11274_DATA_W 32 +#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11274_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11275 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11275_DATA_W 32 +#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11275_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11276 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11276_DATA_W 32 +#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11276_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11277 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11277_DATA_W 32 +#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11277_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11278 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11278_DATA_W 32 +#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11278_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11279 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11279_DATA_W 32 +#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11279_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11280 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11280_DATA_W 32 +#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11280_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11281 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11281_DATA_W 32 +#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11281_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11282 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11282_DATA_W 32 +#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11282_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11283 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11283_DATA_W 32 +#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11283_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11284 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11284_DATA_W 32 +#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11284_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11285 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11285_DATA_W 32 +#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11285_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11286 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11286_DATA_W 32 +#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11286_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11287 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11287_DATA_W 32 +#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11287_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11288 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11288_DATA_W 32 +#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11288_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11289 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11289_DATA_W 32 +#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11289_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11290 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11290_DATA_W 32 +#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11290_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11291 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11291_DATA_W 32 +#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11291_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11292 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11292_DATA_W 32 +#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11292_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11293 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11293_DATA_W 32 +#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11293_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11294 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11294_DATA_W 32 +#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11294_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11295 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11295_DATA_W 32 +#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11295_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11296 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11296_DATA_W 32 +#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11296_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11297 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11297_DATA_W 32 +#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11297_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11298 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11298_DATA_W 32 +#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11298_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11299 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11299_DATA_W 32 +#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11299_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11300 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11300_DATA_W 32 +#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11300_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11301 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11301_DATA_W 32 +#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11301_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11302 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11302_DATA_W 32 +#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11302_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11303 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11303_DATA_W 32 +#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11303_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11304 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11304_DATA_W 32 +#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11304_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11305 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11305_DATA_W 32 +#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11305_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11306 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11306_DATA_W 32 +#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11306_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11307 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11307_DATA_W 32 +#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11307_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11308 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11308_DATA_W 32 +#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11308_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11309 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11309_DATA_W 32 +#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11309_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11310 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11310_DATA_W 32 +#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11310_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11311 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11311_DATA_W 32 +#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11311_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11312 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11312_DATA_W 32 +#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11312_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11313 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11313_DATA_W 32 +#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11313_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11314 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11314_DATA_W 32 +#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11314_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11315 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11315_DATA_W 32 +#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11315_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11316 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11316_DATA_W 32 +#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11316_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11317 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11317_DATA_W 32 +#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11317_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11318 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11318_DATA_W 32 +#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11318_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11319 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11319_DATA_W 32 +#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11319_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11320 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11320_DATA_W 32 +#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11320_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11321 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11321_DATA_W 32 +#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11321_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11322 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11322_DATA_W 32 +#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11322_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11323 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11323_DATA_W 32 +#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11323_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11324 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11324_DATA_W 32 +#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11324_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11325 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11325_DATA_W 32 +#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11325_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11326 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11326_DATA_W 32 +#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11326_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11327 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11327_DATA_W 32 +#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11327_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11328 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11328_DATA_W 32 +#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11328_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11329 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11329_DATA_W 32 +#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11329_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11330 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11330_DATA_W 32 +#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11330_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11331 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11331_DATA_W 32 +#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11331_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11332 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11332_DATA_W 32 +#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11332_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11333 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11333_DATA_W 32 +#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11333_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11334 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11334_DATA_W 32 +#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11334_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11335 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11335_DATA_W 32 +#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11335_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11336 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11336_DATA_W 32 +#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11336_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11337 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11337_DATA_W 32 +#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11337_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11338 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11338_DATA_W 32 +#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11338_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11339 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11339_DATA_W 32 +#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11339_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11340 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11340_DATA_W 32 +#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11340_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11341 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11341_DATA_W 32 +#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11341_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11342 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11342_DATA_W 32 +#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11342_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11343 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11343_DATA_W 32 +#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11343_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11344 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11344_DATA_W 32 +#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11344_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11345 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11345_DATA_W 32 +#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11345_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11346 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11346_DATA_W 32 +#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11346_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11347 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11347_DATA_W 32 +#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11347_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11348 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11348_DATA_W 32 +#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11348_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11349 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11349_DATA_W 32 +#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11349_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11350 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11350_DATA_W 32 +#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11350_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11351 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11351_DATA_W 32 +#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11351_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11352 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11352_DATA_W 32 +#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11352_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11353 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11353_DATA_W 32 +#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11353_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11354 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11354_DATA_W 32 +#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11354_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11355 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11355_DATA_W 32 +#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11355_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11356 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11356_DATA_W 32 +#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11356_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11357 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11357_DATA_W 32 +#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11357_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11358 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11358_DATA_W 32 +#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11358_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11359 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11359_DATA_W 32 +#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11359_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11360 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11360_DATA_W 32 +#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11360_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11361 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11361_DATA_W 32 +#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11361_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11362 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11362_DATA_W 32 +#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11362_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11363 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11363_DATA_W 32 +#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11363_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11364 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11364_DATA_W 32 +#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11364_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11365 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11365_DATA_W 32 +#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11365_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11366 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11366_DATA_W 32 +#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11366_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11367 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11367_DATA_W 32 +#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11367_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11368 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11368_DATA_W 32 +#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11368_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11369 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11369_DATA_W 32 +#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11369_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11370 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11370_DATA_W 32 +#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11370_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11371 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11371_DATA_W 32 +#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11371_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11372 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11372_DATA_W 32 +#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11372_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11373 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11373_DATA_W 32 +#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11373_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11374 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11374_DATA_W 32 +#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11374_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11375 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11375_DATA_W 32 +#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11375_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11376 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11376_DATA_W 32 +#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11376_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11377 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11377_DATA_W 32 +#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11377_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11378 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11378_DATA_W 32 +#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11378_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11379 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11379_DATA_W 32 +#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11379_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11380 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11380_DATA_W 32 +#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11380_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11381 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11381_DATA_W 32 +#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11381_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11382 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11382_DATA_W 32 +#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11382_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11383 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11383_DATA_W 32 +#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11383_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11384 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11384_DATA_W 32 +#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11384_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11385 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11385_DATA_W 32 +#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11385_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11386 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11386_DATA_W 32 +#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11386_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11387 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11387_DATA_W 32 +#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11387_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11388 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11388_DATA_W 32 +#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11388_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11389 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11389_DATA_W 32 +#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11389_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11390 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11390_DATA_W 32 +#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11390_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11391 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11391_DATA_W 32 +#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11391_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11392 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11392_DATA_W 32 +#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11392_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11393 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11393_DATA_W 32 +#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11393_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11394 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11394_DATA_W 32 +#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11394_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11395 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11395_DATA_W 32 +#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11395_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11396 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11396_DATA_W 32 +#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11396_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11397 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11397_DATA_W 32 +#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11397_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11398 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11398_DATA_W 32 +#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11398_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11399 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11399_DATA_W 32 +#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11399_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11400 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11400_DATA_W 32 +#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11400_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11401 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11401_DATA_W 32 +#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11401_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11402 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11402_DATA_W 32 +#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11402_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11403 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11403_DATA_W 32 +#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11403_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11404 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11404_DATA_W 32 +#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11404_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11405 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11405_DATA_W 32 +#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11405_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11406 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11406_DATA_W 32 +#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11406_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11407 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11407_DATA_W 32 +#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11407_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11408 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11408_DATA_W 32 +#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11408_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11409 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11409_DATA_W 32 +#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11409_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11410 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11410_DATA_W 32 +#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11410_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11411 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11411_DATA_W 32 +#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11411_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11412 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11412_DATA_W 32 +#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11412_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11413 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11413_DATA_W 32 +#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11413_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11414 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11414_DATA_W 32 +#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11414_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11415 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11415_DATA_W 32 +#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11415_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11416 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11416_DATA_W 32 +#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11416_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11417 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11417_DATA_W 32 +#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11417_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11418 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11418_DATA_W 32 +#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11418_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11419 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11419_DATA_W 32 +#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11419_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11420 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11420_DATA_W 32 +#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11420_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11421 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11421_DATA_W 32 +#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11421_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11422 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11422_DATA_W 32 +#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11422_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11423 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11423_DATA_W 32 +#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11423_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11424 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11424_DATA_W 32 +#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11424_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11425 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11425_DATA_W 32 +#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11425_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11426 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11426_DATA_W 32 +#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11426_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11427 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11427_DATA_W 32 +#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11427_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11428 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11428_DATA_W 32 +#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11428_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11429 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11429_DATA_W 32 +#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11429_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11430 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11430_DATA_W 32 +#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11430_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11431 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11431_DATA_W 32 +#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11431_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11432 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11432_DATA_W 32 +#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11432_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11433 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11433_DATA_W 32 +#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11433_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11434 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11434_DATA_W 32 +#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11434_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11435 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11435_DATA_W 32 +#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11435_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11436 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11436_DATA_W 32 +#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11436_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11437 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11437_DATA_W 32 +#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11437_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11438 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11438_DATA_W 32 +#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11438_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11439 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11439_DATA_W 32 +#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11439_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11440 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11440_DATA_W 32 +#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11440_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11441 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11441_DATA_W 32 +#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11441_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11442 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11442_DATA_W 32 +#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11442_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11443 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11443_DATA_W 32 +#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11443_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11444 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11444_DATA_W 32 +#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11444_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11445 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11445_DATA_W 32 +#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11445_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11446 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11446_DATA_W 32 +#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11446_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11447 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11447_DATA_W 32 +#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11447_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11448 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11448_DATA_W 32 +#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11448_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11449 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11449_DATA_W 32 +#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11449_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11450 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11450_DATA_W 32 +#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11450_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11451 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11451_DATA_W 32 +#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11451_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11452 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11452_DATA_W 32 +#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11452_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11453 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11453_DATA_W 32 +#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11453_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11454 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11454_DATA_W 32 +#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11454_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11455 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11455_DATA_W 32 +#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11455_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11456 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11456_DATA_W 32 +#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11456_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11457 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11457_DATA_W 32 +#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11457_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11458 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11458_DATA_W 32 +#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11458_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11459 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11459_DATA_W 32 +#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11459_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11460 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11460_DATA_W 32 +#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11460_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11461 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11461_DATA_W 32 +#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11461_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11462 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11462_DATA_W 32 +#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11462_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11463 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11463_DATA_W 32 +#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11463_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11464 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11464_DATA_W 32 +#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11464_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11465 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11465_DATA_W 32 +#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11465_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11466 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11466_DATA_W 32 +#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11466_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11467 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11467_DATA_W 32 +#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11467_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11468 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11468_DATA_W 32 +#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11468_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11469 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11469_DATA_W 32 +#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11469_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11470 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11470_DATA_W 32 +#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11470_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11471 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11471_DATA_W 32 +#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11471_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11472 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11472_DATA_W 32 +#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11472_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11473 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11473_DATA_W 32 +#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11473_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11474 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11474_DATA_W 32 +#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11474_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11475 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11475_DATA_W 32 +#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11475_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11476 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11476_DATA_W 32 +#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11476_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11477 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11477_DATA_W 32 +#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11477_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11478 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11478_DATA_W 32 +#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11478_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11479 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11479_DATA_W 32 +#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11479_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11480 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11480_DATA_W 32 +#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11480_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11481 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11481_DATA_W 32 +#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11481_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11482 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11482_DATA_W 32 +#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11482_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11483 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11483_DATA_W 32 +#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11483_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11484 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11484_DATA_W 32 +#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11484_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11485 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11485_DATA_W 32 +#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11485_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11486 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11486_DATA_W 32 +#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11486_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11487 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11487_DATA_W 32 +#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11487_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11488 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11488_DATA_W 32 +#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11488_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11489 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11489_DATA_W 32 +#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11489_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11490 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11490_DATA_W 32 +#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11490_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11491 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11491_DATA_W 32 +#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11491_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11492 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11492_DATA_W 32 +#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11492_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11493 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11493_DATA_W 32 +#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11493_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11494 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11494_DATA_W 32 +#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11494_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11495 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11495_DATA_W 32 +#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11495_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11496 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11496_DATA_W 32 +#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11496_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11497 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11497_DATA_W 32 +#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11497_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11498 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11498_DATA_W 32 +#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11498_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11499 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11499_DATA_W 32 +#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11499_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11500 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11500_DATA_W 32 +#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11500_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11501 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11501_DATA_W 32 +#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11501_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11502 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11502_DATA_W 32 +#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11502_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11503 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11503_DATA_W 32 +#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11503_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11504 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11504_DATA_W 32 +#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11504_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11505 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11505_DATA_W 32 +#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11505_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11506 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11506_DATA_W 32 +#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11506_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11507 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11507_DATA_W 32 +#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11507_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11508 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11508_DATA_W 32 +#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11508_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11509 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11509_DATA_W 32 +#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11509_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11510 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11510_DATA_W 32 +#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11510_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11511 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11511_DATA_W 32 +#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11511_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11512 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11512_DATA_W 32 +#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11512_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11513 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11513_DATA_W 32 +#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11513_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11514 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11514_DATA_W 32 +#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11514_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11515 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11515_DATA_W 32 +#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11515_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11516 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11516_DATA_W 32 +#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11516_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11517 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11517_DATA_W 32 +#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11517_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11518 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11518_DATA_W 32 +#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11518_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11519 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11519_DATA_W 32 +#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11519_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11520 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11520_DATA_W 32 +#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11520_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11521 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11521_DATA_W 32 +#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11521_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11522 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11522_DATA_W 32 +#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11522_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11523 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11523_DATA_W 32 +#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11523_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11524 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11524_DATA_W 32 +#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11524_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11525 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11525_DATA_W 32 +#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11525_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11526 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11526_DATA_W 32 +#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11526_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11527 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11527_DATA_W 32 +#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11527_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11528 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11528_DATA_W 32 +#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11528_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11529 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11529_DATA_W 32 +#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11529_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11530 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11530_DATA_W 32 +#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11530_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11531 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11531_DATA_W 32 +#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11531_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11532 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11532_DATA_W 32 +#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11532_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11533 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11533_DATA_W 32 +#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11533_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11534 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11534_DATA_W 32 +#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11534_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11535 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11535_DATA_W 32 +#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11535_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11536 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11536_DATA_W 32 +#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11536_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11537 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11537_DATA_W 32 +#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11537_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11538 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11538_DATA_W 32 +#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11538_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11539 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11539_DATA_W 32 +#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11539_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11540 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11540_DATA_W 32 +#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11540_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11541 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11541_DATA_W 32 +#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11541_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11542 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11542_DATA_W 32 +#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11542_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11543 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11543_DATA_W 32 +#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11543_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11544 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11544_DATA_W 32 +#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11544_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11545 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11545_DATA_W 32 +#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11545_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11546 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11546_DATA_W 32 +#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11546_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11547 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11547_DATA_W 32 +#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11547_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11548 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11548_DATA_W 32 +#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11548_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11549 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11549_DATA_W 32 +#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11549_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11550 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11550_DATA_W 32 +#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11550_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11551 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11551_DATA_W 32 +#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11551_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11552 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11552_DATA_W 32 +#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11552_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11553 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11553_DATA_W 32 +#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11553_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11554 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11554_DATA_W 32 +#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11554_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11555 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11555_DATA_W 32 +#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11555_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11556 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11556_DATA_W 32 +#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11556_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11557 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11557_DATA_W 32 +#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11557_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11558 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11558_DATA_W 32 +#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11558_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11559 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11559_DATA_W 32 +#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11559_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11560 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11560_DATA_W 32 +#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11560_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11561 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11561_DATA_W 32 +#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11561_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11562 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11562_DATA_W 32 +#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11562_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11563 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11563_DATA_W 32 +#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11563_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11564 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11564_DATA_W 32 +#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11564_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11565 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11565_DATA_W 32 +#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11565_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11566 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11566_DATA_W 32 +#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11566_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11567 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11567_DATA_W 32 +#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11567_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11568 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11568_DATA_W 32 +#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11568_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11569 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11569_DATA_W 32 +#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11569_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11570 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11570_DATA_W 32 +#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11570_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11571 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11571_DATA_W 32 +#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11571_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11572 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11572_DATA_W 32 +#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11572_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11573 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11573_DATA_W 32 +#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11573_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11574 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11574_DATA_W 32 +#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11574_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11575 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11575_DATA_W 32 +#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11575_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11576 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11576_DATA_W 32 +#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11576_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11577 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11577_DATA_W 32 +#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11577_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11578 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11578_DATA_W 32 +#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11578_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11579 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11579_DATA_W 32 +#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11579_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11580 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11580_DATA_W 32 +#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11580_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11581 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11581_DATA_W 32 +#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11581_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11582 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11582_DATA_W 32 +#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11582_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11583 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11583_DATA_W 32 +#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11583_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11584 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11584_DATA_W 32 +#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11584_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11585 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11585_DATA_W 32 +#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11585_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11586 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11586_DATA_W 32 +#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11586_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11587 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11587_DATA_W 32 +#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11587_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11588 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11588_DATA_W 32 +#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11588_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11589 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11589_DATA_W 32 +#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11589_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11590 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11590_DATA_W 32 +#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11590_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11591 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11591_DATA_W 32 +#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11591_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11592 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11592_DATA_W 32 +#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11592_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11593 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11593_DATA_W 32 +#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11593_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11594 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11594_DATA_W 32 +#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11594_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11595 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11595_DATA_W 32 +#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11595_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11596 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11596_DATA_W 32 +#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11596_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11597 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11597_DATA_W 32 +#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11597_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11598 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11598_DATA_W 32 +#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11598_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11599 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11599_DATA_W 32 +#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11599_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11600 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11600_DATA_W 32 +#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11600_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11601 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11601_DATA_W 32 +#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11601_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11602 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11602_DATA_W 32 +#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11602_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11603 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11603_DATA_W 32 +#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11603_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11604 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11604_DATA_W 32 +#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11604_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11605 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11605_DATA_W 32 +#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11605_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11606 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11606_DATA_W 32 +#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11606_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11607 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11607_DATA_W 32 +#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11607_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11608 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11608_DATA_W 32 +#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11608_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11609 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11609_DATA_W 32 +#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11609_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11610 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11610_DATA_W 32 +#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11610_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11611 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11611_DATA_W 32 +#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11611_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11612 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11612_DATA_W 32 +#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11612_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11613 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11613_DATA_W 32 +#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11613_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11614 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11614_DATA_W 32 +#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11614_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11615 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11615_DATA_W 32 +#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11615_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11616 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11616_DATA_W 32 +#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11616_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11617 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11617_DATA_W 32 +#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11617_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11618 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11618_DATA_W 32 +#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11618_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11619 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11619_DATA_W 32 +#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11619_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11620 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11620_DATA_W 32 +#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11620_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11621 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11621_DATA_W 32 +#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11621_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11622 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11622_DATA_W 32 +#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11622_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11623 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11623_DATA_W 32 +#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11623_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11624 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11624_DATA_W 32 +#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11624_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11625 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11625_DATA_W 32 +#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11625_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11626 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11626_DATA_W 32 +#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11626_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11627 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11627_DATA_W 32 +#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11627_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11628 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11628_DATA_W 32 +#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11628_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11629 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11629_DATA_W 32 +#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11629_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11630 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11630_DATA_W 32 +#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11630_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11631 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11631_DATA_W 32 +#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11631_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11632 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11632_DATA_W 32 +#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11632_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11633 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11633_DATA_W 32 +#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11633_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11634 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11634_DATA_W 32 +#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11634_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11635 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11635_DATA_W 32 +#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11635_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11636 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11636_DATA_W 32 +#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11636_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11637 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11637_DATA_W 32 +#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11637_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11638 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11638_DATA_W 32 +#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11638_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11639 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11639_DATA_W 32 +#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11639_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11640 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11640_DATA_W 32 +#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11640_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11641 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11641_DATA_W 32 +#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11641_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11642 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11642_DATA_W 32 +#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11642_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11643 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11643_DATA_W 32 +#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11643_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11644 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11644_DATA_W 32 +#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11644_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11645 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11645_DATA_W 32 +#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11645_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11646 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11646_DATA_W 32 +#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11646_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11647 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11647_DATA_W 32 +#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11647_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11648 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11648_DATA_W 32 +#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11648_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11649 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11649_DATA_W 32 +#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11649_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11650 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11650_DATA_W 32 +#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11650_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11651 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11651_DATA_W 32 +#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11651_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11652 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11652_DATA_W 32 +#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11652_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11653 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11653_DATA_W 32 +#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11653_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11654 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11654_DATA_W 32 +#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11654_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11655 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11655_DATA_W 32 +#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11655_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11656 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11656_DATA_W 32 +#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11656_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11657 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11657_DATA_W 32 +#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11657_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11658 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11658_DATA_W 32 +#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11658_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11659 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11659_DATA_W 32 +#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11659_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11660 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11660_DATA_W 32 +#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11660_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11661 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11661_DATA_W 32 +#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11661_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11662 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11662_DATA_W 32 +#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11662_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11663 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11663_DATA_W 32 +#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11663_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11664 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11664_DATA_W 32 +#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11664_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11665 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11665_DATA_W 32 +#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11665_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11666 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11666_DATA_W 32 +#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11666_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11667 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11667_DATA_W 32 +#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11667_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11668 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11668_DATA_W 32 +#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11668_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11669 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11669_DATA_W 32 +#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11669_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11670 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11670_DATA_W 32 +#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11670_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11671 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11671_DATA_W 32 +#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11671_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11672 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11672_DATA_W 32 +#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11672_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11673 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11673_DATA_W 32 +#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11673_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11674 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11674_DATA_W 32 +#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11674_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11675 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11675_DATA_W 32 +#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11675_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11676 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11676_DATA_W 32 +#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11676_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11677 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11677_DATA_W 32 +#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11677_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11678 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11678_DATA_W 32 +#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11678_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11679 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11679_DATA_W 32 +#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11679_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11680 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11680_DATA_W 32 +#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11680_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11681 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11681_DATA_W 32 +#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11681_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11682 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11682_DATA_W 32 +#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11682_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11683 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11683_DATA_W 32 +#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11683_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11684 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11684_DATA_W 32 +#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11684_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11685 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11685_DATA_W 32 +#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11685_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11686 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11686_DATA_W 32 +#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11686_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11687 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11687_DATA_W 32 +#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11687_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11688 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11688_DATA_W 32 +#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11688_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11689 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11689_DATA_W 32 +#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11689_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11690 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11690_DATA_W 32 +#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11690_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11691 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11691_DATA_W 32 +#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11691_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11692 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11692_DATA_W 32 +#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11692_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11693 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11693_DATA_W 32 +#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11693_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11694 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11694_DATA_W 32 +#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11694_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11695 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11695_DATA_W 32 +#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11695_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11696 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11696_DATA_W 32 +#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11696_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11697 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11697_DATA_W 32 +#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11697_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11698 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11698_DATA_W 32 +#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11698_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11699 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11699_DATA_W 32 +#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11699_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11700 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11700_DATA_W 32 +#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11700_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11701 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11701_DATA_W 32 +#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11701_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11702 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11702_DATA_W 32 +#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11702_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11703 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11703_DATA_W 32 +#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11703_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11704 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11704_DATA_W 32 +#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11704_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11705 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11705_DATA_W 32 +#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11705_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11706 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11706_DATA_W 32 +#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11706_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11707 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11707_DATA_W 32 +#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11707_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11708 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11708_DATA_W 32 +#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11708_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11709 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11709_DATA_W 32 +#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11709_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11710 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11710_DATA_W 32 +#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11710_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11711 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11711_DATA_W 32 +#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11711_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11712 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11712_DATA_W 32 +#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11712_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11713 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11713_DATA_W 32 +#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11713_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11714 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11714_DATA_W 32 +#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11714_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11715 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11715_DATA_W 32 +#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11715_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11716 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11716_DATA_W 32 +#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11716_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11717 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11717_DATA_W 32 +#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11717_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11718 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11718_DATA_W 32 +#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11718_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11719 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11719_DATA_W 32 +#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11719_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11720 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11720_DATA_W 32 +#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11720_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11721 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11721_DATA_W 32 +#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11721_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11722 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11722_DATA_W 32 +#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11722_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11723 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11723_DATA_W 32 +#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11723_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11724 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11724_DATA_W 32 +#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11724_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11725 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11725_DATA_W 32 +#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11725_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11726 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11726_DATA_W 32 +#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11726_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11727 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11727_DATA_W 32 +#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11727_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11728 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11728_DATA_W 32 +#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11728_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11729 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11729_DATA_W 32 +#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11729_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11730 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11730_DATA_W 32 +#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11730_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11731 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11731_DATA_W 32 +#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11731_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11732 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11732_DATA_W 32 +#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11732_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11733 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11733_DATA_W 32 +#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11733_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11734 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11734_DATA_W 32 +#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11734_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11735 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11735_DATA_W 32 +#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11735_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11736 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11736_DATA_W 32 +#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11736_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11737 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11737_DATA_W 32 +#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11737_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11738 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11738_DATA_W 32 +#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11738_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11739 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11739_DATA_W 32 +#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11739_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11740 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11740_DATA_W 32 +#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11740_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11741 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11741_DATA_W 32 +#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11741_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11742 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11742_DATA_W 32 +#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11742_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11743 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11743_DATA_W 32 +#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11743_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11744 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11744_DATA_W 32 +#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11744_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11745 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11745_DATA_W 32 +#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11745_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11746 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11746_DATA_W 32 +#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11746_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11747 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11747_DATA_W 32 +#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11747_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11748 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11748_DATA_W 32 +#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11748_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11749 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11749_DATA_W 32 +#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11749_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11750 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11750_DATA_W 32 +#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11750_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11751 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11751_DATA_W 32 +#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11751_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11752 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11752_DATA_W 32 +#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11752_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11753 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11753_DATA_W 32 +#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11753_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11754 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11754_DATA_W 32 +#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11754_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11755 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11755_DATA_W 32 +#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11755_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11756 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11756_DATA_W 32 +#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11756_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11757 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11757_DATA_W 32 +#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11757_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11758 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11758_DATA_W 32 +#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11758_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11759 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11759_DATA_W 32 +#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11759_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11760 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11760_DATA_W 32 +#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11760_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11761 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11761_DATA_W 32 +#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11761_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11762 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11762_DATA_W 32 +#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11762_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11763 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11763_DATA_W 32 +#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11763_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11764 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11764_DATA_W 32 +#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11764_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11765 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11765_DATA_W 32 +#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11765_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11766 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11766_DATA_W 32 +#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11766_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11767 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11767_DATA_W 32 +#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11767_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11768 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11768_DATA_W 32 +#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11768_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11769 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11769_DATA_W 32 +#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11769_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11770 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11770_DATA_W 32 +#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11770_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11771 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11771_DATA_W 32 +#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11771_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11772 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11772_DATA_W 32 +#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11772_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11773 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11773_DATA_W 32 +#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11773_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11774 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11774_DATA_W 32 +#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11774_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11775 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11775_DATA_W 32 +#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11775_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11776 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11776_DATA_W 32 +#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11776_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11777 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11777_DATA_W 32 +#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11777_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11778 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11778_DATA_W 32 +#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11778_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11779 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11779_DATA_W 32 +#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11779_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11780 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11780_DATA_W 32 +#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11780_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11781 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11781_DATA_W 32 +#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11781_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11782 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11782_DATA_W 32 +#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11782_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11783 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11783_DATA_W 32 +#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11783_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11784 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11784_DATA_W 32 +#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11784_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11785 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11785_DATA_W 32 +#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11785_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11786 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11786_DATA_W 32 +#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11786_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11787 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11787_DATA_W 32 +#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11787_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11788 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11788_DATA_W 32 +#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11788_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11789 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11789_DATA_W 32 +#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11789_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11790 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11790_DATA_W 32 +#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11790_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11791 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11791_DATA_W 32 +#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11791_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11792 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11792_DATA_W 32 +#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11792_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11793 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11793_DATA_W 32 +#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11793_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11794 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11794_DATA_W 32 +#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11794_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11795 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11795_DATA_W 32 +#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11795_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11796 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11796_DATA_W 32 +#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11796_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11797 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11797_DATA_W 32 +#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11797_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11798 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11798_DATA_W 32 +#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11798_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11799 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11799_DATA_W 32 +#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11799_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11800 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11800_DATA_W 32 +#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11800_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11801 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11801_DATA_W 32 +#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11801_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11802 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11802_DATA_W 32 +#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11802_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11803 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11803_DATA_W 32 +#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11803_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11804 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11804_DATA_W 32 +#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11804_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11805 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11805_DATA_W 32 +#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11805_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11806 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11806_DATA_W 32 +#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11806_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11807 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11807_DATA_W 32 +#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11807_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11808 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11808_DATA_W 32 +#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11808_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11809 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11809_DATA_W 32 +#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11809_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11810 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11810_DATA_W 32 +#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11810_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11811 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11811_DATA_W 32 +#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11811_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11812 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11812_DATA_W 32 +#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11812_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11813 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11813_DATA_W 32 +#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11813_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11814 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11814_DATA_W 32 +#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11814_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11815 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11815_DATA_W 32 +#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11815_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11816 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11816_DATA_W 32 +#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11816_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11817 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11817_DATA_W 32 +#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11817_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11818 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11818_DATA_W 32 +#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11818_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11819 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11819_DATA_W 32 +#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11819_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11820 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11820_DATA_W 32 +#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11820_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11821 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11821_DATA_W 32 +#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11821_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11822 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11822_DATA_W 32 +#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11822_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11823 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11823_DATA_W 32 +#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11823_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11824 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11824_DATA_W 32 +#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11824_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11825 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11825_DATA_W 32 +#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11825_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11826 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11826_DATA_W 32 +#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11826_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11827 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11827_DATA_W 32 +#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11827_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11828 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11828_DATA_W 32 +#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11828_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11829 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11829_DATA_W 32 +#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11829_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11830 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11830_DATA_W 32 +#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11830_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11831 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11831_DATA_W 32 +#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11831_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11832 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11832_DATA_W 32 +#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11832_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11833 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11833_DATA_W 32 +#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11833_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11834 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11834_DATA_W 32 +#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11834_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11835 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11835_DATA_W 32 +#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11835_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11836 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11836_DATA_W 32 +#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11836_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11837 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11837_DATA_W 32 +#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11837_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11838 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11838_DATA_W 32 +#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11838_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11839 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11839_DATA_W 32 +#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11839_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11840 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11840_DATA_W 32 +#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11840_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11841 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11841_DATA_W 32 +#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11841_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11842 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11842_DATA_W 32 +#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11842_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11843 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11843_DATA_W 32 +#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11843_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11844 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11844_DATA_W 32 +#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11844_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11845 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11845_DATA_W 32 +#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11845_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11846 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11846_DATA_W 32 +#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11846_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11847 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11847_DATA_W 32 +#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11847_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11848 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11848_DATA_W 32 +#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11848_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11849 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11849_DATA_W 32 +#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11849_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11850 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11850_DATA_W 32 +#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11850_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11851 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11851_DATA_W 32 +#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11851_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11852 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11852_DATA_W 32 +#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11852_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11853 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11853_DATA_W 32 +#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11853_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11854 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11854_DATA_W 32 +#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11854_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11855 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11855_DATA_W 32 +#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11855_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11856 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11856_DATA_W 32 +#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11856_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11857 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11857_DATA_W 32 +#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11857_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11858 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11858_DATA_W 32 +#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11858_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11859 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11859_DATA_W 32 +#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11859_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11860 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11860_DATA_W 32 +#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11860_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11861 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11861_DATA_W 32 +#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11861_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11862 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11862_DATA_W 32 +#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11862_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11863 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11863_DATA_W 32 +#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11863_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11864 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11864_DATA_W 32 +#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11864_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11865 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11865_DATA_W 32 +#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11865_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11866 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11866_DATA_W 32 +#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11866_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11867 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11867_DATA_W 32 +#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11867_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11868 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11868_DATA_W 32 +#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11868_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11869 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11869_DATA_W 32 +#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11869_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11870 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11870_DATA_W 32 +#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11870_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11871 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11871_DATA_W 32 +#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11871_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11872 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11872_DATA_W 32 +#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11872_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11873 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11873_DATA_W 32 +#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11873_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11874 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11874_DATA_W 32 +#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11874_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11875 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11875_DATA_W 32 +#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11875_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11876 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11876_DATA_W 32 +#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11876_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11877 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11877_DATA_W 32 +#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11877_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11878 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11878_DATA_W 32 +#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11878_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11879 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11879_DATA_W 32 +#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11879_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11880 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11880_DATA_W 32 +#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11880_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11881 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11881_DATA_W 32 +#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11881_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11882 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11882_DATA_W 32 +#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11882_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11883 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11883_DATA_W 32 +#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11883_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11884 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11884_DATA_W 32 +#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11884_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11885 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11885_DATA_W 32 +#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11885_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11886 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11886_DATA_W 32 +#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11886_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11887 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11887_DATA_W 32 +#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11887_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11888 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11888_DATA_W 32 +#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11888_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11889 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11889_DATA_W 32 +#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11889_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11890 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11890_DATA_W 32 +#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11890_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11891 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11891_DATA_W 32 +#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11891_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11892 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11892_DATA_W 32 +#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11892_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11893 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11893_DATA_W 32 +#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11893_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11894 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11894_DATA_W 32 +#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11894_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11895 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11895_DATA_W 32 +#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11895_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11896 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11896_DATA_W 32 +#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11896_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11897 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11897_DATA_W 32 +#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11897_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11898 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11898_DATA_W 32 +#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11898_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11899 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11899_DATA_W 32 +#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11899_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11900 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11900_DATA_W 32 +#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11900_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11901 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11901_DATA_W 32 +#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11901_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11902 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11902_DATA_W 32 +#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11902_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11903 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11903_DATA_W 32 +#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11903_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11904 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11904_DATA_W 32 +#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11904_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11905 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11905_DATA_W 32 +#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11905_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11906 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11906_DATA_W 32 +#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11906_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11907 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11907_DATA_W 32 +#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11907_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11908 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11908_DATA_W 32 +#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11908_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11909 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11909_DATA_W 32 +#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11909_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11910 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11910_DATA_W 32 +#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11910_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11911 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11911_DATA_W 32 +#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11911_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11912 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11912_DATA_W 32 +#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11912_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11913 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11913_DATA_W 32 +#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11913_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11914 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11914_DATA_W 32 +#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11914_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11915 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11915_DATA_W 32 +#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11915_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11916 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11916_DATA_W 32 +#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11916_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11917 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11917_DATA_W 32 +#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11917_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11918 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11918_DATA_W 32 +#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11918_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11919 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11919_DATA_W 32 +#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11919_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11920 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11920_DATA_W 32 +#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11920_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11921 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11921_DATA_W 32 +#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11921_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11922 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11922_DATA_W 32 +#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11922_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11923 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11923_DATA_W 32 +#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11923_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11924 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11924_DATA_W 32 +#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11924_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11925 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11925_DATA_W 32 +#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11925_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11926 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11926_DATA_W 32 +#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11926_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11927 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11927_DATA_W 32 +#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11927_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11928 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11928_DATA_W 32 +#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11928_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11929 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11929_DATA_W 32 +#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11929_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11930 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11930_DATA_W 32 +#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11930_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11931 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11931_DATA_W 32 +#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11931_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11932 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11932_DATA_W 32 +#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11932_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11933 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11933_DATA_W 32 +#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11933_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11934 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11934_DATA_W 32 +#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11934_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11935 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11935_DATA_W 32 +#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11935_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11936 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11936_DATA_W 32 +#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11936_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11937 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11937_DATA_W 32 +#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11937_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11938 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11938_DATA_W 32 +#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11938_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11939 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11939_DATA_W 32 +#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11939_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11940 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11940_DATA_W 32 +#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11940_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11941 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11941_DATA_W 32 +#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11941_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11942 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11942_DATA_W 32 +#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11942_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11943 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11943_DATA_W 32 +#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11943_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11944 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11944_DATA_W 32 +#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11944_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11945 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11945_DATA_W 32 +#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11945_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11946 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11946_DATA_W 32 +#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11946_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11947 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11947_DATA_W 32 +#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11947_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11948 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11948_DATA_W 32 +#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11948_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11949 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11949_DATA_W 32 +#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11949_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11950 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11950_DATA_W 32 +#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11950_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11951 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11951_DATA_W 32 +#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11951_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11952 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11952_DATA_W 32 +#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11952_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11953 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11953_DATA_W 32 +#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11953_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11954 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11954_DATA_W 32 +#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11954_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11955 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11955_DATA_W 32 +#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11955_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11956 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11956_DATA_W 32 +#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11956_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11957 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11957_DATA_W 32 +#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11957_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11958 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11958_DATA_W 32 +#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11958_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11959 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11959_DATA_W 32 +#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11959_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11960 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11960_DATA_W 32 +#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11960_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11961 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11961_DATA_W 32 +#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11961_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11962 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11962_DATA_W 32 +#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11962_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11963 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11963_DATA_W 32 +#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11963_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11964 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11964_DATA_W 32 +#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11964_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11965 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11965_DATA_W 32 +#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11965_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11966 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11966_DATA_W 32 +#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11966_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11967 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11967_DATA_W 32 +#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11967_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11968 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11968_DATA_W 32 +#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11968_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11969 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11969_DATA_W 32 +#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11969_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11970 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11970_DATA_W 32 +#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11970_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11971 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11971_DATA_W 32 +#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11971_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11972 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11972_DATA_W 32 +#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11972_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11973 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11973_DATA_W 32 +#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11973_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11974 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11974_DATA_W 32 +#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11974_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11975 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11975_DATA_W 32 +#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11975_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11976 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11976_DATA_W 32 +#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11976_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11977 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11977_DATA_W 32 +#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11977_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11978 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11978_DATA_W 32 +#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11978_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11979 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11979_DATA_W 32 +#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11979_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11980 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11980_DATA_W 32 +#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11980_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11981 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11981_DATA_W 32 +#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11981_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11982 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11982_DATA_W 32 +#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11982_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11983 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11983_DATA_W 32 +#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11983_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11984 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11984_DATA_W 32 +#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11984_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11985 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11985_DATA_W 32 +#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11985_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11986 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11986_DATA_W 32 +#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11986_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11987 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11987_DATA_W 32 +#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11987_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11988 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11988_DATA_W 32 +#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11988_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11989 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11989_DATA_W 32 +#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11989_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11990 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11990_DATA_W 32 +#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11990_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11991 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11991_DATA_W 32 +#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11991_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11992 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11992_DATA_W 32 +#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11992_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11993 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11993_DATA_W 32 +#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11993_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11994 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11994_DATA_W 32 +#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11994_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11995 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11995_DATA_W 32 +#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11995_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11996 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11996_DATA_W 32 +#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11996_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11997 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11997_DATA_W 32 +#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11997_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11998 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11998_DATA_W 32 +#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11998_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK11999 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK11999_DATA_W 32 +#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11999_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12000 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12000_DATA_W 32 +#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12000_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12001 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12001_DATA_W 32 +#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12001_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12002 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12002_DATA_W 32 +#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12002_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12003 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12003_DATA_W 32 +#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12003_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12004 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12004_DATA_W 32 +#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12004_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12005 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12005_DATA_W 32 +#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12005_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12006 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12006_DATA_W 32 +#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12006_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12007 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12007_DATA_W 32 +#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12007_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12008 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12008_DATA_W 32 +#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12008_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12009 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12009_DATA_W 32 +#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12009_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12010 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12010_DATA_W 32 +#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12010_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12011 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12011_DATA_W 32 +#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12011_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12012 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12012_DATA_W 32 +#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12012_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12013 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12013_DATA_W 32 +#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12013_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12014 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12014_DATA_W 32 +#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12014_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12015 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12015_DATA_W 32 +#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12015_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12016 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12016_DATA_W 32 +#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12016_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12017 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12017_DATA_W 32 +#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12017_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12018 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12018_DATA_W 32 +#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12018_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12019 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12019_DATA_W 32 +#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12019_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12020 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12020_DATA_W 32 +#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12020_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12021 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12021_DATA_W 32 +#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12021_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12022 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12022_DATA_W 32 +#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12022_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12023 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12023_DATA_W 32 +#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12023_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12024 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12024_DATA_W 32 +#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12024_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12025 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12025_DATA_W 32 +#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12025_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12026 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12026_DATA_W 32 +#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12026_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12027 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12027_DATA_W 32 +#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12027_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12028 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12028_DATA_W 32 +#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12028_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12029 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12029_DATA_W 32 +#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12029_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12030 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12030_DATA_W 32 +#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12030_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12031 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12031_DATA_W 32 +#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12031_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12032 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12032_DATA_W 32 +#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12032_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12033 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12033_DATA_W 32 +#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12033_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12034 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12034_DATA_W 32 +#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12034_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12035 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12035_DATA_W 32 +#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12035_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12036 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12036_DATA_W 32 +#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12036_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12037 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12037_DATA_W 32 +#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12037_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12038 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12038_DATA_W 32 +#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12038_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12039 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12039_DATA_W 32 +#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12039_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12040 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12040_DATA_W 32 +#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12040_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12041 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12041_DATA_W 32 +#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12041_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12042 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12042_DATA_W 32 +#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12042_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12043 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12043_DATA_W 32 +#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12043_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12044 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12044_DATA_W 32 +#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12044_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12045 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12045_DATA_W 32 +#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12045_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12046 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12046_DATA_W 32 +#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12046_DATA_S 0 + +//***************************************************************************** +// +// Register: RFC_ULLRAM_O_BANK12047 +// +//***************************************************************************** +// Field: [31:0] DATA +// +// SRAM data +#define RFC_ULLRAM_BANK12047_DATA_W 32 +#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12047_DATA_S 0 + + +#endif // __RFC_ULLRAM__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_smph.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_smph.h new file mode 100644 index 00000000..5ca6d64a --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_smph.h @@ -0,0 +1,1455 @@ +/****************************************************************************** +* Filename: hw_smph_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SMPH_H__ +#define __HW_SMPH_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SMPH component +// +//***************************************************************************** +// MCU SEMAPHORE 0 +#define SMPH_O_SMPH0 0x00000000 + +// MCU SEMAPHORE 1 +#define SMPH_O_SMPH1 0x00000004 + +// MCU SEMAPHORE 2 +#define SMPH_O_SMPH2 0x00000008 + +// MCU SEMAPHORE 3 +#define SMPH_O_SMPH3 0x0000000C + +// MCU SEMAPHORE 4 +#define SMPH_O_SMPH4 0x00000010 + +// MCU SEMAPHORE 5 +#define SMPH_O_SMPH5 0x00000014 + +// MCU SEMAPHORE 6 +#define SMPH_O_SMPH6 0x00000018 + +// MCU SEMAPHORE 7 +#define SMPH_O_SMPH7 0x0000001C + +// MCU SEMAPHORE 8 +#define SMPH_O_SMPH8 0x00000020 + +// MCU SEMAPHORE 9 +#define SMPH_O_SMPH9 0x00000024 + +// MCU SEMAPHORE 10 +#define SMPH_O_SMPH10 0x00000028 + +// MCU SEMAPHORE 11 +#define SMPH_O_SMPH11 0x0000002C + +// MCU SEMAPHORE 12 +#define SMPH_O_SMPH12 0x00000030 + +// MCU SEMAPHORE 13 +#define SMPH_O_SMPH13 0x00000034 + +// MCU SEMAPHORE 14 +#define SMPH_O_SMPH14 0x00000038 + +// MCU SEMAPHORE 15 +#define SMPH_O_SMPH15 0x0000003C + +// MCU SEMAPHORE 16 +#define SMPH_O_SMPH16 0x00000040 + +// MCU SEMAPHORE 17 +#define SMPH_O_SMPH17 0x00000044 + +// MCU SEMAPHORE 18 +#define SMPH_O_SMPH18 0x00000048 + +// MCU SEMAPHORE 19 +#define SMPH_O_SMPH19 0x0000004C + +// MCU SEMAPHORE 20 +#define SMPH_O_SMPH20 0x00000050 + +// MCU SEMAPHORE 21 +#define SMPH_O_SMPH21 0x00000054 + +// MCU SEMAPHORE 22 +#define SMPH_O_SMPH22 0x00000058 + +// MCU SEMAPHORE 23 +#define SMPH_O_SMPH23 0x0000005C + +// MCU SEMAPHORE 24 +#define SMPH_O_SMPH24 0x00000060 + +// MCU SEMAPHORE 25 +#define SMPH_O_SMPH25 0x00000064 + +// MCU SEMAPHORE 26 +#define SMPH_O_SMPH26 0x00000068 + +// MCU SEMAPHORE 27 +#define SMPH_O_SMPH27 0x0000006C + +// MCU SEMAPHORE 28 +#define SMPH_O_SMPH28 0x00000070 + +// MCU SEMAPHORE 29 +#define SMPH_O_SMPH29 0x00000074 + +// MCU SEMAPHORE 30 +#define SMPH_O_SMPH30 0x00000078 + +// MCU SEMAPHORE 31 +#define SMPH_O_SMPH31 0x0000007C + +// MCU SEMAPHORE 0 ALIAS +#define SMPH_O_PEEK0 0x00000800 + +// MCU SEMAPHORE 1 ALIAS +#define SMPH_O_PEEK1 0x00000804 + +// MCU SEMAPHORE 2 ALIAS +#define SMPH_O_PEEK2 0x00000808 + +// MCU SEMAPHORE 3 ALIAS +#define SMPH_O_PEEK3 0x0000080C + +// MCU SEMAPHORE 4 ALIAS +#define SMPH_O_PEEK4 0x00000810 + +// MCU SEMAPHORE 5 ALIAS +#define SMPH_O_PEEK5 0x00000814 + +// MCU SEMAPHORE 6 ALIAS +#define SMPH_O_PEEK6 0x00000818 + +// MCU SEMAPHORE 7 ALIAS +#define SMPH_O_PEEK7 0x0000081C + +// MCU SEMAPHORE 8 ALIAS +#define SMPH_O_PEEK8 0x00000820 + +// MCU SEMAPHORE 9 ALIAS +#define SMPH_O_PEEK9 0x00000824 + +// MCU SEMAPHORE 10 ALIAS +#define SMPH_O_PEEK10 0x00000828 + +// MCU SEMAPHORE 11 ALIAS +#define SMPH_O_PEEK11 0x0000082C + +// MCU SEMAPHORE 12 ALIAS +#define SMPH_O_PEEK12 0x00000830 + +// MCU SEMAPHORE 13 ALIAS +#define SMPH_O_PEEK13 0x00000834 + +// MCU SEMAPHORE 14 ALIAS +#define SMPH_O_PEEK14 0x00000838 + +// MCU SEMAPHORE 15 ALIAS +#define SMPH_O_PEEK15 0x0000083C + +// MCU SEMAPHORE 16 ALIAS +#define SMPH_O_PEEK16 0x00000840 + +// MCU SEMAPHORE 17 ALIAS +#define SMPH_O_PEEK17 0x00000844 + +// MCU SEMAPHORE 18 ALIAS +#define SMPH_O_PEEK18 0x00000848 + +// MCU SEMAPHORE 19 ALIAS +#define SMPH_O_PEEK19 0x0000084C + +// MCU SEMAPHORE 20 ALIAS +#define SMPH_O_PEEK20 0x00000850 + +// MCU SEMAPHORE 21 ALIAS +#define SMPH_O_PEEK21 0x00000854 + +// MCU SEMAPHORE 22 ALIAS +#define SMPH_O_PEEK22 0x00000858 + +// MCU SEMAPHORE 23 ALIAS +#define SMPH_O_PEEK23 0x0000085C + +// MCU SEMAPHORE 24 ALIAS +#define SMPH_O_PEEK24 0x00000860 + +// MCU SEMAPHORE 25 ALIAS +#define SMPH_O_PEEK25 0x00000864 + +// MCU SEMAPHORE 26 ALIAS +#define SMPH_O_PEEK26 0x00000868 + +// MCU SEMAPHORE 27 ALIAS +#define SMPH_O_PEEK27 0x0000086C + +// MCU SEMAPHORE 28 ALIAS +#define SMPH_O_PEEK28 0x00000870 + +// MCU SEMAPHORE 29 ALIAS +#define SMPH_O_PEEK29 0x00000874 + +// MCU SEMAPHORE 30 ALIAS +#define SMPH_O_PEEK30 0x00000878 + +// MCU SEMAPHORE 31 ALIAS +#define SMPH_O_PEEK31 0x0000087C + +//***************************************************************************** +// +// Register: SMPH_O_SMPH0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_SMPH31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Reading the register causes it to change value to 0. Releasing the semaphore +// is done by writing 1. +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK0 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK1 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK2 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK3 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK4 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK5 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK6 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK7 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK8 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK9 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK10 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK11 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK12 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK13 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK14 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK15 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK16 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK17 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK18 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK19 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK20 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK21 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK22 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK23 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK24 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK25 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK26 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK27 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK28 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK29 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK30 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 + +//***************************************************************************** +// +// Register: SMPH_O_PEEK31 +// +//***************************************************************************** +// Field: [0] STAT +// +// Status when reading: +// +// 0: Semaphore is taken +// 1: Semaphore is available +// +// Used for semaphore debugging. A read operation will not change register +// value. Register writing is not possible. +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 + + +#endif // __SMPH__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sram_mmr.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sram_mmr.h new file mode 100644 index 00000000..709affc9 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sram_mmr.h @@ -0,0 +1,150 @@ +/****************************************************************************** +* Filename: hw_sram_mmr_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SRAM_MMR_H__ +#define __HW_SRAM_MMR_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SRAM_MMR component +// +//***************************************************************************** +// Parity Error Control +#define SRAM_MMR_O_PER_CTL 0x00000000 + +// Parity Error Check +#define SRAM_MMR_O_PER_CHK 0x00000004 + +// Parity Error Debug +#define SRAM_MMR_O_PER_DBG 0x00000008 + +// Memory Control +#define SRAM_MMR_O_MEM_CTL 0x0000000C + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_CTL +// +//***************************************************************************** +// Field: [8] PER_DISABLE +// +// Parity Status Disable +// +// 0: A parity error will update PER_CHK.PER_ADDR field +// 1: Parity error does not update PER_CHK.PER_ADDR field +#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8 +#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8 + +// Field: [0] PER_DEBUG_ENABLE +// +// Parity Error Debug Enable +// +// 0: Normal operation +// 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity +// errors will be generated on reads from within this offset +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_CHK +// +//***************************************************************************** +// Field: [23:0] PER_ADDR +// +// Parity Error Address Offset +// Returns the last address offset which resulted in a parity error during an +// SRAM read. The address offset returned is always the word-aligned address +// that contains the location with the parity error. For parity faults on non +// word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the +// location that resulted in parity error. +#define SRAM_MMR_PER_CHK_PER_ADDR_W 24 +#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_CHK_PER_ADDR_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_PER_DBG +// +//***************************************************************************** +// Field: [23:0] PER_DEBUG_ADDR +// +// Debug Parity Error Address Offset +// When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug +// address offset. The address offset must be a word-aligned address. Writes +// within this address offset will force incorrect parity bits to be stored +// together with the data written. The following reads within this same address +// offset will thus result in parity errors to be generated. +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24 +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0 + +//***************************************************************************** +// +// Register: SRAM_MMR_O_MEM_CTL +// +//***************************************************************************** +// Field: [1] MEM_BUSY +// +// Memory Busy status +// +// 0: Memory accepts transfers +// 1: Memory controller is busy during initialization. Read and write transfers +// are not performed. +#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1 + +// Field: [0] MEM_CLR_EN +// +// Memory Contents Initialization enable +// +// Writing 1 to MEM_CLR_EN will start memory initialization. The contents of +// all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until +// memory initialization has completed. +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0 + + +#endif // __SRAM_MMR__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ssi.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ssi.h new file mode 100644 index 00000000..299366c4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_ssi.h @@ -0,0 +1,544 @@ +/****************************************************************************** +* Filename: hw_ssi_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SSI_H__ +#define __HW_SSI_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// SSI component +// +//***************************************************************************** +// Control 0 +#define SSI_O_CR0 0x00000000 + +// Control 1 +#define SSI_O_CR1 0x00000004 + +// Data +#define SSI_O_DR 0x00000008 + +// Status +#define SSI_O_SR 0x0000000C + +// Clock Prescale +#define SSI_O_CPSR 0x00000010 + +// Interrupt Mask Set and Clear +#define SSI_O_IMSC 0x00000014 + +// Raw Interrupt Status +#define SSI_O_RIS 0x00000018 + +// Masked Interrupt Status +#define SSI_O_MIS 0x0000001C + +// Interrupt Clear +#define SSI_O_ICR 0x00000020 + +// DMA Control +#define SSI_O_DMACR 0x00000024 + +//***************************************************************************** +// +// Register: SSI_O_CR0 +// +//***************************************************************************** +// Field: [15:8] SCR +// +// Serial clock rate: +// This is used to generate the transmit and receive bit rate of the SSI. The +// bit rate is +// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). +// SCR is a value from 0-255. +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 + +// Field: [7] SPH +// +// CLKOUT phase (Motorola SPI frame format only) +// This bit selects the clock edge that captures data and enables it to change +// state. It +// has the most impact on the first bit transmitted by either permitting or not +// permitting a clock transition before the first data capture edge. +// ENUMs: +// 2ND_CLK_EDGE Data is captured on the second clock edge +// transition. +// 1ST_CLK_EDGE Data is captured on the first clock edge +// transition. +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 + +// Field: [6] SPO +// +// CLKOUT polarity (Motorola SPI frame format only) +// ENUMs: +// HIGH SSI produces a steady state HIGH value on the +// CLKOUT pin when data is not being transferred. +// LOW SSI produces a steady state LOW value on the +// CLKOUT pin when data is +// not being transferred. +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 + +// Field: [5:4] FRF +// +// Frame format. +// The supported frame formats are Motorola SPI, TI synchronous serial and +// National Microwire. +// Value 0'b11 is reserved and shall not be used. +// ENUMs: +// NATIONAL_MICROWIRE National Microwire frame format +// TI_SYNC_SERIAL TI synchronous serial frame format +// MOTOROLA_SPI Motorola SPI frame format +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 + +// Field: [3:0] DSS +// +// Data Size Select. +// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. +// ENUMs: +// 16_BIT 16-bit data +// 15_BIT 15-bit data +// 14_BIT 14-bit data +// 13_BIT 13-bit data +// 12_BIT 12-bit data +// 11_BIT 11-bit data +// 10_BIT 10-bit data +// 9_BIT 9-bit data +// 8_BIT 8-bit data +// 7_BIT 7-bit data +// 6_BIT 6-bit data +// 5_BIT 5-bit data +// 4_BIT 4-bit data +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 + +//***************************************************************************** +// +// Register: SSI_O_CR1 +// +//***************************************************************************** +// Field: [3] SOD +// +// Slave-mode output disabled +// This bit is relevant only in the slave mode, MS=1. In multiple-slave +// systems, it is possible for an SSI master to broadcast a message to all +// slaves in the system while ensuring that only one slave drives data onto its +// serial output line. In such systems the RXD lines from multiple slaves could +// be tied together. To operate in such systems, this bitfield can be set if +// the SSI slave is not supposed to drive the TXD line: +// +// 0: SSI can drive the TXD output in slave mode. +// 1: SSI cannot drive the TXD output in slave mode. +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 + +// Field: [2] MS +// +// Master or slave mode select. This bit can be modified only when SSI is +// disabled, SSE=0. +// ENUMs: +// SLAVE Device configured as slave +// MASTER Device configured as master +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 + +// Field: [1] SSE +// +// Synchronous serial interface enable. +// ENUMs: +// SSI_ENABLED Operation enabled +// SSI_DISABLED Operation disabled +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 + +// Field: [0] LBM +// +// Loop back mode: +// +// 0: Normal serial port operation enabled. +// 1: Output of transmit serial shifter is connected to input of receive serial +// shifter internally. +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DR +// +//***************************************************************************** +// Field: [15:0] DATA +// +// Transmit/receive data +// The values read from this field or written to this field must be +// right-justified when SSI is programmed for a data size that is less than 16 +// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit +// logic. The receive logic automatically right-justifies. +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: SSI_O_SR +// +//***************************************************************************** +// Field: [4] BSY +// +// Serial interface busy: +// +// 0: SSI is idle +// 1: SSI is currently transmitting and/or receiving a frame or the transmit +// FIFO is not empty. +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 + +// Field: [3] RFF +// +// Receive FIFO full: +// +// 0: Receive FIFO is not full. +// 1: Receive FIFO is full. +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 + +// Field: [2] RNE +// +// Receive FIFO not empty +// +// 0: Receive FIFO is empty. +// 1: Receive FIFO is not empty. +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 + +// Field: [1] TNF +// +// Transmit FIFO not full: +// +// 0: Transmit FIFO is full. +// 1: Transmit FIFO is not full. +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 + +// Field: [0] TFE +// +// Transmit FIFO empty: +// +// 0: Transmit FIFO is not empty. +// 1: Transmit FIFO is empty. +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 + +//***************************************************************************** +// +// Register: SSI_O_CPSR +// +//***************************************************************************** +// Field: [7:0] CPSDVSR +// +// Clock prescale divisor: +// This field specifies the division factor by which the input system clock to +// SSI must be internally divided before further use. +// The value programmed into this field must be an even non-zero number +// (2-254). The least significant bit of the programmed number is hard-coded to +// zero. If an odd number is written to this register, data read back from +// this register has the least significant bit as zero. +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// Register: SSI_O_IMSC +// +//***************************************************************************** +// Field: [3] TXIM +// +// Transmit FIFO interrupt mask: +// A read returns the current mask for transmit FIFO interrupt. On a write of +// 1, the mask for transmit FIFO interrupt is set which means the interrupt +// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which +// means MIS.TXMIS will not reflect the interrupt. +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 + +// Field: [2] RXIM +// +// Receive FIFO interrupt mask: +// A read returns the current mask for receive FIFO interrupt. On a write of 1, +// the mask for receive FIFO interrupt is set which means the interrupt state +// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means +// MIS.RXMIS will not reflect the interrupt. +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 + +// Field: [1] RTIM +// +// Receive timeout interrupt mask: +// A read returns the current mask for receive timeout interrupt. On a write of +// 1, the mask for receive timeout interrupt is set which means the interrupt +// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which +// means MIS.RTMIS will not reflect the interrupt. +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 + +// Field: [0] RORIM +// +// Receive overrun interrupt mask: +// A read returns the current mask for receive overrun interrupt. On a write of +// 1, the mask for receive overrun interrupt is set which means the interrupt +// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which +// means MIS.RORMIS will not reflect the interrupt. +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 + +//***************************************************************************** +// +// Register: SSI_O_RIS +// +//***************************************************************************** +// Field: [3] TXRIS +// +// Raw transmit FIFO interrupt status: +// The transmit interrupt is asserted when there are four or fewer valid +// entries in the transmit FIFO. The transmit interrupt is not qualified with +// the SSI enable signal. Therefore one of the following ways can be used: +// - data can be written to the transmit FIFO prior to enabling the SSI and +// the +// interrupts. +// - SSI and interrupts can be enabled so that data can be written to the +// transmit FIFO by an interrupt service routine. +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 + +// Field: [2] RXRIS +// +// Raw interrupt state of receive FIFO interrupt: +// The receive interrupt is asserted when there are four or more valid entries +// in the receive FIFO. +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 + +// Field: [1] RTRIS +// +// Raw interrupt state of receive timeout interrupt: +// The receive timeout interrupt is asserted when the receive FIFO is not empty +// and SSI has remained idle for a fixed 32 bit period. This mechanism can be +// used to notify the user that data is still present in the receive FIFO and +// requires servicing. This interrupt is deasserted if the receive FIFO becomes +// empty by subsequent reads, or if new data is received on RXD. +// It can also be cleared by writing to ICR.RTIC. +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 + +// Field: [0] RORRIS +// +// Raw interrupt state of receive overrun interrupt: +// The receive overrun interrupt is asserted when the FIFO is already full and +// an additional data frame is received, causing an overrun of the FIFO. Data +// is over-written in the +// receive shift register, but not the FIFO so the FIFO contents stay valid. +// It can also be cleared by writing to ICR.RORIC. +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_MIS +// +//***************************************************************************** +// Field: [3] TXMIS +// +// Masked interrupt state of transmit FIFO interrupt: +// This field returns the masked interrupt state of transmit FIFO interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 + +// Field: [2] RXMIS +// +// Masked interrupt state of receive FIFO interrupt: +// This field returns the masked interrupt state of receive FIFO interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 + +// Field: [1] RTMIS +// +// Masked interrupt state of receive timeout interrupt: +// This field returns the masked interrupt state of receive timeout interrupt +// which is the AND product of raw interrupt state RIS.RTRIS and the mask +// setting IMSC.RTIM. +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 + +// Field: [0] RORMIS +// +// Masked interrupt state of receive overrun interrupt: +// This field returns the masked interrupt state of receive overrun interrupt +// which is the AND product of raw interrupt state RIS.RORRIS and the mask +// setting IMSC.RORIM. +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 + +//***************************************************************************** +// +// Register: SSI_O_ICR +// +//***************************************************************************** +// Field: [1] RTIC +// +// Clear the receive timeout interrupt: +// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 +// has no effect. +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 + +// Field: [0] RORIC +// +// Clear the receive overrun interrupt: +// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). +// Writing 0 has no effect. +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 + +//***************************************************************************** +// +// Register: SSI_O_DMACR +// +//***************************************************************************** +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 + + +#endif // __SSI__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sysctl.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sysctl.h new file mode 100644 index 00000000..973698ce --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_sysctl.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: hw_sysctl.h +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_SYSCTL_H__ +#define __HW_SYSCTL_H__ + + +//***************************************************************************** +// +// The following are initial defines for the MCU clock +// +//***************************************************************************** +#define GET_MCU_CLOCK 48000000 + + +#endif // __HW_SYSCTL_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_trng.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_trng.h new file mode 100644 index 00000000..e6628bbe --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_trng.h @@ -0,0 +1,609 @@ +/****************************************************************************** +* Filename: hw_trng_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TRNG_H__ +#define __HW_TRNG_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// TRNG component +// +//***************************************************************************** +// Random Number Lower Word Readout Value +#define TRNG_O_OUT0 0x00000000 + +// Random Number Upper Word Readout Value +#define TRNG_O_OUT1 0x00000004 + +// Interrupt Status +#define TRNG_O_IRQFLAGSTAT 0x00000008 + +// Interrupt Mask +#define TRNG_O_IRQFLAGMASK 0x0000000C + +// Interrupt Flag Clear +#define TRNG_O_IRQFLAGCLR 0x00000010 + +// Control +#define TRNG_O_CTL 0x00000014 + +// Configuration 0 +#define TRNG_O_CFG0 0x00000018 + +// Alarm Control +#define TRNG_O_ALARMCNT 0x0000001C + +// FRO Enable +#define TRNG_O_FROEN 0x00000020 + +// FRO De-tune Bit +#define TRNG_O_FRODETUNE 0x00000024 + +// Alarm Event +#define TRNG_O_ALARMMASK 0x00000028 + +// Alarm Shutdown +#define TRNG_O_ALARMSTOP 0x0000002C + +// LFSR Readout Value +#define TRNG_O_LFSR0 0x00000030 + +// LFSR Readout Value +#define TRNG_O_LFSR1 0x00000034 + +// LFSR Readout Value +#define TRNG_O_LFSR2 0x00000038 + +// TRNG Engine Options Information +#define TRNG_O_HWOPT 0x00000078 + +// HW Version 0 +#define TRNG_O_HWVER0 0x0000007C + +// Interrupt Status After Masking +#define TRNG_O_IRQSTATMASK 0x00001FD8 + +// HW Version 1 +#define TRNG_O_HWVER1 0x00001FE0 + +// Interrupt Set +#define TRNG_O_IRQSET 0x00001FEC + +// SW Reset Control +#define TRNG_O_SWRESET 0x00001FF0 + +// Interrupt Status +#define TRNG_O_IRQSTAT 0x00001FF8 + +//***************************************************************************** +// +// Register: TRNG_O_OUT0 +// +//***************************************************************************** +// Field: [31:0] VALUE_31_0 +// +// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_OUT1 +// +//***************************************************************************** +// Field: [31:0] VALUE_63_32 +// +// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGSTAT +// +//***************************************************************************** +// Field: [31] NEED_CLOCK +// +// 1: Indicates that the TRNG is busy generating entropy or is in one of its +// test modes - clocks may not be turned off and the power supply voltage must +// be kept stable. +// 0: TRNG is idle and can be shut down +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 + +// Field: [1] SHUTDOWN_OVF +// +// 1: The number of FROs shut down (i.e. the number of '1' bits in the +// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR +// +// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Data are available in OUT0 and OUT1. +// +// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to +// '0'. +// If a new number is already available in the internal register of the TRNG, +// the number is directly clocked into the result register. In this case the +// status bit is asserted again, after one clock cycle. +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this +// module. +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQFLAGCLR +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// 1: Clear IRQFLAGSTAT.RDY. +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_CTL +// +//***************************************************************************** +// Field: [31:16] STARTUP_CYCLES +// +// This field determines the number of samples (between 2^8 and 2^24) taken to +// gather entropy from the FROs during startup. If the written value of this +// field is zero, the number of samples is 2^24, otherwise the number of +// samples equals the written value times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while TRNG_EN is 0. If 1 an update will be +// ignored. +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 + +// Field: [10] TRNG_EN +// +// 0: Forces all TRNG logic back into the idle state immediately. +// 1: Starts TRNG, gathering entropy from the FROs for the number of samples +// determined by STARTUP_CYCLES. +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 + +// Field: [2] NO_LFSR_FB +// +// 1: Remove XNOR feedback from the main LFSR, converting it into a normal +// shift register for the XOR-ed outputs of the FROs (shifting data in on the +// LSB side). A '1' also forces the LFSR to sample continuously. +// +// This bit can only be set to '1' when TEST_MODE is also set to '1' and should +// not be used for other than test purposes +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 + +// Field: [1] TEST_MODE +// +// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter +// are automatically cleared before enabling access) and keeps +// IRQFLAGSTAT.NEED_CLOCK at '1'. +// +// This bit shall not be used unless you need to change the LFSR seed prior to +// creating a new random value. All other testing is done external to register +// control. +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 + +//***************************************************************************** +// +// Register: TRNG_O_CFG0 +// +//***************************************************************************** +// Field: [31:16] MAX_REFILL_CYCLES +// +// This field determines the maximum number of samples (between 2^8 and 2^24) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the written value of this field is zero, the number of +// samples is 2^24, otherwise the number of samples equals the written value +// times 2^8. +// +// 0x0000: 2^24 samples +// 0x0001: 1*2^8 samples +// 0x0002: 2*2^8 samples +// 0x0003: 3*2^8 samples +// ... +// 0x8000: 32768*2^8 samples +// 0xC000: 49152*2^8 samples +// ... +// 0xFFFF: 65535*2^8 samples +// +// This field can only be modified while CTL.TRNG_EN is 0. +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 + +// Field: [11:8] SMPL_DIV +// +// This field directly controls the number of clock cycles between samples +// taken from the FROs. Default value 0 indicates that samples are taken every +// clock cycle, +// maximum value 0xF takes one sample every 16 clock cycles. +// This field must be set to a value such that the slowest FRO (even under +// worst-case +// conditions) has a cycle time less than twice the sample period. +// +// This field can only be modified while CTL.TRNG_EN is '0'. +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 + +// Field: [7:0] MIN_REFILL_CYCLES +// +// This field determines the minimum number of samples (between 2^6 and 2^14) +// taken to re-generate entropy from the FROs after reading out a 64 bits +// random number. If the value of this field is zero, the number of samples is +// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the +// minimum number of samples equals the written value times 64 (which can be up +// to 2^14). To ensure same entropy in all generated random numbers the value 0 +// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. +// The number of samples defined here cannot be higher than the number defined +// by the 'max_refill_cycles' field (i.e. that field takes precedence). No +// random value will be created if min refill > max refill. +// +// This field can only be modified while CTL.TRNG_EN = 0. +// +// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) +// 0x01: 1*2^6 samples +// 0x02: 2*2^6 samples +// ... +// 0xFF: 255*2^6 samples +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMCNT +// +//***************************************************************************** +// Field: [29:24] SHUTDOWN_CNT +// +// Read-only, indicates the number of '1' bits in ALARMSTOP register. +// The maximum value equals the number of FROs. +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 + +// Field: [20:16] SHUTDOWN_THR +// +// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The +// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 + +// Field: [7:0] ALARM_THR +// +// Alarm detection threshold for the repeating pattern detectors on each FRO. +// An FRO 'alarm event' is declared when a repeating pattern (of up to four +// samples length) is detected continuously for the number of samples defined +// by this field's value. Reset value 0xFF should keep the number of 'alarm +// events' to a manageable level. +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FROEN +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. +// Default state is all '1's to enable all FROs after power-up. Note that they +// are not actually started up before the CTL.TRNG_EN bit is set to '1'. +// +// Bits are automatically forced to '0' here (and cannot be written to '1') +// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_FRODETUNE +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run +// approximately 5% faster. The value of one of these bits may only be changed +// while the corresponding FRO is turned off (by temporarily writing a '0' in +// the corresponding +// bit of the FROEN.FRO_MASK register). +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMMASK +// +//***************************************************************************** +// Field: [23:0] FRO_MASK +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced an 'alarm event'. +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_ALARMSTOP +// +//***************************************************************************** +// Field: [23:0] FRO_FLAGS +// +// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] +// indicates FRO 'n' experienced more than one 'alarm event' in quick +// succession and has been turned off. A '1' in this field forces the +// corresponding bit in FROEN.FRO_MASK to '0'. +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR0 +// +//***************************************************************************** +// Field: [31:0] LFSR_31_0 +// +// Bits [31:0] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR1 +// +//***************************************************************************** +// Field: [31:0] LFSR_63_32 +// +// Bits [63:32] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_LFSR2 +// +//***************************************************************************** +// Field: [16:0] LFSR_80_64 +// +// Bits [80:64] of the main entropy accumulation LFSR. Register can only be +// accessed when CTL.TEST_MODE = 1. +// Register contents will be cleared to zero before access is enabled. +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWOPT +// +//***************************************************************************** +// Field: [11:6] NR_OF_FROS +// +// Number of FROs implemented in this TRNG, value 24 (decimal). +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER0 +// +//***************************************************************************** +// Field: [27:24] HW_MAJOR_VER +// +// 4 bits binary encoding of the major hardware revision number. +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 + +// Field: [23:20] HW_MINOR_VER +// +// 4 bits binary encoding of the minor hardware revision number. +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 + +// Field: [19:16] HW_PATCH_LVL +// +// 4 bits binary encoding of the hardware patch level, initial release will +// carry value zero. +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 + +// Field: [15:8] EIP_NUM_COMPL +// +// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 + +// Field: [7:0] EIP_NUM +// +// 8 bits binary encoding of the module number. This TRNG gives 0x4B. +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTATMASK +// +//***************************************************************************** +// Field: [1] SHUTDOWN_OVF +// +// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with +// IRQFLAGMASK.SHUTDOWN_OVF) +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 + +// Field: [0] RDY +// +// New random value available (result of IRQFLAGSTAT.RDY AND'ed with +// IRQFLAGMASK.RDY) +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_HWVER1 +// +//***************************************************************************** +// Field: [7:0] REV +// +// The revision number of this module is Rev 2.0. +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSET +// +//***************************************************************************** +//***************************************************************************** +// +// Register: TRNG_O_SWRESET +// +//***************************************************************************** +// Field: [0] RESET +// +// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 +// for reset to be completed. +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 + +//***************************************************************************** +// +// Register: TRNG_O_IRQSTAT +// +//***************************************************************************** +// Field: [0] STAT +// +// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and +// IRQFLAGSTAT.RDY +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 + + +#endif // __TRNG__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_types.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_types.h new file mode 100644 index 00000000..24e25670 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_types.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* Filename: hw_types.h +* +* Description: Common types and macros. +* +* Copyright (c) 2015 - 2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +#include +#include +#include "../inc/hw_chip_def.h" + +//***************************************************************************** +// +// Common driverlib types +// +//***************************************************************************** +typedef void (* FPTR_VOID_VOID_T) (void); +typedef void (* FPTR_VOID_UINT8_T) (uint8_t); + +//***************************************************************************** +// +// This symbol forces simple driverlib functions to be inlined in the code +// instead of using function calls. +// +//***************************************************************************** +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +//***************************************************************************** +// +// C99 types only allows bitfield defintions on certain datatypes. +// +//***************************************************************************** +typedef unsigned int __UINT32; + +//***************************************************************************** +// +// Macros for direct hardware access. +// +// If using these macros the programmer should be aware of any limitations to +// the address accessed i.e. if it supports word and/or byte access. +// +//***************************************************************************** +// Word (32 bit) access to address x +// Read example : my32BitVar = HWREG(base_addr + offset) ; +// Write example : HWREG(base_addr + offset) = my32BitVar ; +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) + +// Half word (16 bit) access to address x +// Read example : my16BitVar = HWREGH(base_addr + offset) ; +// Write example : HWREGH(base_addr + offset) = my16BitVar ; +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) + +// Byte (8 bit) access to address x +// Read example : my8BitVar = HWREGB(base_addr + offset) ; +// Write example : HWREGB(base_addr + offset) = my8BitVar ; +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// Macros for hardware access to bit-band supported addresses via the bit-band region. +// +// Macros calculate the corresponding address to access in the bit-band region +// based on the actual address of the memory/register and the bit number. +// +// Do NOT use these macros to access the bit-band region directly! +// +//***************************************************************************** +// Bit-band access to address x bit number b using word access (32 bit) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using half word access (16 bit) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +// Bit-band access to address x bit number b using byte access (8 bit) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +#endif // __HW_TYPES_H__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_uart.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_uart.h new file mode 100644 index 00000000..caf2ed2c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_uart.h @@ -0,0 +1,1087 @@ +/****************************************************************************** +* Filename: hw_uart_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UART component +// +//***************************************************************************** +// Data +#define UART_O_DR 0x00000000 + +// Status +#define UART_O_RSR 0x00000004 + +// Error Clear +#define UART_O_ECR 0x00000004 + +// Flag +#define UART_O_FR 0x00000018 + +// Integer Baud-Rate Divisor +#define UART_O_IBRD 0x00000024 + +// Fractional Baud-Rate Divisor +#define UART_O_FBRD 0x00000028 + +// Line Control +#define UART_O_LCRH 0x0000002C + +// Control +#define UART_O_CTL 0x00000030 + +// Interrupt FIFO Level Select +#define UART_O_IFLS 0x00000034 + +// Interrupt Mask Set/Clear +#define UART_O_IMSC 0x00000038 + +// Raw Interrupt Status +#define UART_O_RIS 0x0000003C + +// Masked Interrupt Status +#define UART_O_MIS 0x00000040 + +// Interrupt Clear +#define UART_O_ICR 0x00000044 + +// DMA Control +#define UART_O_DMACTL 0x00000048 + +//***************************************************************************** +// +// Register: UART_O_DR +// +//***************************************************************************** +// Field: [11] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 + +// Field: [10] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is., the oldest received data character since last read). When a +// break occurs, a 0 character is loaded into the FIFO. The next character is +// enabled after the receive data input (UARTRXD input pin) goes to a 1 +// (marking state), and the next valid start bit is received. +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 + +// Field: [9] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is, the oldest received data character since last read). +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 + +// Field: [8] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +// In FIFO mode, this error is associated with the character at the top of the +// FIFO (that is., the oldest received data character since last read). +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 + +// Field: [7:0] DATA +// +// Data transmitted or received: +// On writes, the transmit data character is pushed into the FIFO. +// On reads, the oldest received data character since the last read is +// returned. +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// Register: UART_O_RSR +// +//***************************************************************************** +// Field: [3] OE +// +// UART Overrun Error: +// This bit is set to 1 if data is received and the receive FIFO is already +// full. The FIFO contents remain valid because no more data is written when +// the FIFO is full, , only the contents of the shift register are overwritten. +// This is cleared to 0 once there is an empty space in the FIFO and a new +// character can be written to it. +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 + +// Field: [2] BE +// +// UART Break Error: +// This bit is set to 1 if a break condition was detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +// When a break occurs, a 0 character is loaded into the FIFO. The next +// character is enabled after the receive data input (UARTRXD input pin) goes +// to a 1 (marking state), and the next valid start bit is received. +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 + +// Field: [1] PE +// +// UART Parity Error: +// When set to 1, it indicates that the parity of the received data character +// does not match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 + +// Field: [0] FE +// +// UART Framing Error: +// When set to 1, it indicates that the received character did not have a valid +// stop bit (a valid stop bit is 1). +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_ECR +// +//***************************************************************************** +// Field: [3] OE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 + +// Field: [2] BE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 + +// Field: [1] PE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 + +// Field: [0] FE +// +// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are +// cleared to 0 by any write to this register. +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 + +//***************************************************************************** +// +// Register: UART_O_FR +// +//***************************************************************************** +// Field: [7] TXFE +// +// UART Transmit FIFO Empty: +// The meaning of this bit depends on the state of LCRH.FEN . +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. +// This bit does not indicate if there is data in the transmit shift register. +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 + +// Field: [6] RXFF +// +// UART Receive FIFO Full: +// The meaning of this bit depends on the state of LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is full. +// - If the FIFO is enabled, this bit is set when the receive FIFO is full. +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 + +// Field: [5] TXFF +// +// UART Transmit FIFO Full: +// Transmit FIFO full. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the transmit holding +// register is full. +// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 + +// Field: [4] RXFE +// +// UART Receive FIFO Empty: +// Receive FIFO empty. The meaning of this bit depends on the state of +// LCRH.FEN. +// - If the FIFO is disabled, this bit is set when the receive holding +// register is empty. +// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 + +// Field: [3] BUSY +// +// UART Busy: +// If this bit is set to 1, the UART is busy transmitting data. This bit +// remains set until the complete byte, including all the stop bits, has been +// sent from the shift register. +// This bit is set as soon as the transmit FIFO becomes non-empty, regardless +// of whether the UART is enabled or not. +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 + +// Field: [0] CTS +// +// Clear To Send: +// This bit is the complement of the active-low UART CTS input pin. +// That is, the bit is 1 when CTS input pin is LOW. +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 + +//***************************************************************************** +// +// Register: UART_O_IBRD +// +//***************************************************************************** +// Field: [15:0] DIVINT +// +// The integer baud rate divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, DIVINT=0 does not give a valid baud rate. +// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// Register: UART_O_FBRD +// +//***************************************************************************** +// Field: [5:0] DIVFRAC +// +// Fractional Baud-Rate Divisor: +// The baud rate divisor is calculated using the formula below: +// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) +// Baud rate divisor must be minimum 1 and maximum 65535. +// That is, IBRD.DIVINT=0 does not give a valid baud rate. +// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be +// illegal. +// A valid value must be written to this field before the UART can be used for +// RX or TX operations. +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// Register: UART_O_LCRH +// +//***************************************************************************** +// Field: [7] SPS +// +// UART Stick Parity Select: +// +// 0: Stick parity is disabled +// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. +// the parity bit is transmitted and checked as 1 when EPS = 0). +// +// This bit has no effect when PEN disables parity checking and generation. +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 + +// Field: [6:5] WLEN +// +// UART Word Length: +// These bits indicate the number of data bits transmitted or received in a +// frame. +// ENUMs: +// 8 Word Length 8 bits +// 7 Word Length 7 bits +// 6 Word Length 6 bits +// 5 Word Length 5 bits +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 + +// Field: [4] FEN +// +// UART Enable FIFOs +// ENUMs: +// EN Transmit and receive FIFO buffers are enabled +// (FIFO mode) +// DIS FIFOs are disabled (character mode) that is, the +// FIFOs become 1-byte-deep holding registers. +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 + +// Field: [3] STP2 +// +// UART Two Stop Bits Select: +// If this bit is set to 1, two stop bits are transmitted at the end of the +// frame. The receive logic does not check for two stop bits being received. +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 + +// Field: [2] EPS +// +// UART Even Parity Select +// ENUMs: +// EVEN Even parity: The UART generates or checks for an +// even number of 1s in the data and parity bits. +// ODD Odd parity: The UART generates or checks for an +// odd number of 1s in the data and parity bits. +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 + +// Field: [1] PEN +// +// UART Parity Enable +// This bit controls generation and checking of parity bit. +// ENUMs: +// EN Parity checking and generation is enabled. +// DIS Parity is disabled and no parity bit is added to +// the data frame +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 + +// Field: [0] BRK +// +// UART Send Break +// If this bit is set to 1, a low-level is continually output on the UARTTXD +// output pin, after completing transmission of the current character. For the +// proper execution of the break command, the +// software must set this bit for at least two complete frames. For normal use, +// this bit must be cleared to 0. +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 + +//***************************************************************************** +// +// Register: UART_O_CTL +// +//***************************************************************************** +// Field: [15] CTSEN +// +// CTS hardware flow control enable +// ENUMs: +// EN CTS hardware flow control enabled +// DIS CTS hardware flow control disabled +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 + +// Field: [14] RTSEN +// +// RTS hardware flow control enable +// ENUMs: +// EN RTS hardware flow control enabled +// DIS RTS hardware flow control disabled +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 + +// Field: [11] RTS +// +// Request to Send +// This bit is the complement of the active-low UART RTS output. That is, when +// the bit is programmed to a 1 then RTS output on the pins is LOW. +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 + +// Field: [9] RXE +// +// UART Receive Enable +// If the UART is disabled in the middle of reception, it completes the current +// character before stopping. +// ENUMs: +// EN UART Receive enabled +// DIS UART Receive disabled +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 + +// Field: [8] TXE +// +// UART Transmit Enable +// If the UART is disabled in the middle of transmission, it completes the +// current character before stopping. +// ENUMs: +// EN UART Transmit enabled +// DIS UART Transmit disabled +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 + +// Field: [7] LBE +// +// UART Loop Back Enable: +// Enabling the loop-back mode connects the UARTTXD output from the UART to +// UARTRXD input of the UART. +// ENUMs: +// EN Loop Back enabled +// DIS Loop Back disabled +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 + +// Field: [0] UARTEN +// +// UART Enable +// ENUMs: +// EN UART enabled +// DIS UART disabled +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IFLS +// +//***************************************************************************** +// Field: [5:3] RXSEL +// +// Receive interrupt FIFO level select: +// This field sets the trigger points for the receive interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Receive FIFO becomes >= 7/8 full +// 6_8 Receive FIFO becomes >= 3/4 full +// 4_8 Receive FIFO becomes >= 1/2 full +// 2_8 Receive FIFO becomes >= 1/4 full +// 1_8 Receive FIFO becomes >= 1/8 full +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 + +// Field: [2:0] TXSEL +// +// Transmit interrupt FIFO level select: +// This field sets the trigger points for the transmit interrupt. Values +// 0b101-0b111 are reserved. +// ENUMs: +// 7_8 Transmit FIFO becomes <= 7/8 full +// 6_8 Transmit FIFO becomes <= 3/4 full +// 4_8 Transmit FIFO becomes <= 1/2 full +// 2_8 Transmit FIFO becomes <= 1/4 full +// 1_8 Transmit FIFO becomes <= 1/8 full +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 + +//***************************************************************************** +// +// Register: UART_O_IMSC +// +//***************************************************************************** +// Field: [11] EOTIM +// +// End of Transmission interrupt mask. A read returns the current mask for +// UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set +// which means the interrupt state will be reflected in MIS.EOTMIS. A write of +// 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. +#define UART_IMSC_EOTIM 0x00000800 +#define UART_IMSC_EOTIM_BITN 11 +#define UART_IMSC_EOTIM_M 0x00000800 +#define UART_IMSC_EOTIM_S 11 + +// Field: [10] OEIM +// +// Overrun error interrupt mask. A read returns the current mask for UART's +// overrun error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not +// reflect the interrupt. +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 + +// Field: [9] BEIM +// +// Break error interrupt mask. A read returns the current mask for UART's break +// error interrupt. On a write of 1, the mask of the overrun error interrupt is +// set which means the interrupt state will be reflected in MIS.BEMIS. A write +// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 + +// Field: [8] PEIM +// +// Parity error interrupt mask. A read returns the current mask for UART's +// parity error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not +// reflect the interrupt. +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 + +// Field: [7] FEIM +// +// Framing error interrupt mask. A read returns the current mask for UART's +// framing error interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not +// reflect the interrupt. +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 + +// Field: [6] RTIM +// +// Receive timeout interrupt mask. A read returns the current mask for UART's +// receive timeout interrupt. On a write of 1, the mask of the overrun error +// interrupt is set which means the interrupt state will be reflected in +// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not +// reflect the interrupt. +// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the +// mask is set (RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 + +// Field: [5] TXIM +// +// Transmit interrupt mask. A read returns the current mask for UART's transmit +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 +// clears the mask which means MIS.TXMIS will not reflect the interrupt. +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 + +// Field: [4] RXIM +// +// Receive interrupt mask. A read returns the current mask for UART's receive +// interrupt. On a write of 1, the mask of the overrun error interrupt is set +// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 +// clears the mask which means MIS.RXMIS will not reflect the interrupt. +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 + +// Field: [1] CTSMIM +// +// Clear to Send (CTS) modem interrupt mask. A read returns the current mask +// for UART's clear to send interrupt. On a write of 1, the mask of the overrun +// error interrupt is set which means the interrupt state will be reflected in +// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not +// reflect the interrupt. +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 + +//***************************************************************************** +// +// Register: UART_O_RIS +// +//***************************************************************************** +// Field: [11] EOTRIS +// +// End of Transmission interrupt status: +// This field returns the raw interrupt state of UART's end of transmission +// interrupt. End of transmission flag is set when all the Transmit data in the +// FIFO and on the TX Line is tranmitted. +#define UART_RIS_EOTRIS 0x00000800 +#define UART_RIS_EOTRIS_BITN 11 +#define UART_RIS_EOTRIS_M 0x00000800 +#define UART_RIS_EOTRIS_S 11 + +// Field: [10] OERIS +// +// Overrun error interrupt status: +// This field returns the raw interrupt state of UART's overrun error +// interrupt. Overrun error occurs if data is received and the receive FIFO is +// full. +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 + +// Field: [9] BERIS +// +// Break error interrupt status: +// This field returns the raw interrupt state of UART's break error interrupt. +// Break error is set when a break condition is detected, indicating that the +// received data input (UARTRXD input pin) was held LOW for longer than a +// full-word transmission time (defined as start, data, parity and stop bits). +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 + +// Field: [8] PERIS +// +// Parity error interrupt status: +// This field returns the raw interrupt state of UART's parity error interrupt. +// Parity error is set if the parity of the received data character does not +// match the parity that the LCRH.EPS and LCRH.SPS select. +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 + +// Field: [7] FERIS +// +// Framing error interrupt status: +// This field returns the raw interrupt state of UART's framing error +// interrupt. Framing error is set if the received character does not have a +// valid stop bit (a valid stop bit is 1). +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 + +// Field: [6] RTRIS +// +// Receive timeout interrupt status: +// This field returns the raw interrupt state of UART's receive timeout +// interrupt. The receive timeout interrupt is asserted when the receive FIFO +// is not empty, and no more data is received during a 32-bit period. The +// receive timeout interrupt is cleared either when the FIFO becomes empty +// through reading all the data, or when a 1 is written to ICR.RTIC. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 + +// Field: [5] TXRIS +// +// Transmit interrupt status: +// This field returns the raw interrupt state of UART's transmit interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if +// the number of bytes in transmit FIFO is equal to or lower than the +// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by +// writing data to the transmit FIFO until it becomes greater than the trigger +// level, or by clearing the interrupt through ICR.TXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the transmit interrupt is asserted if there is no data present in +// the transmitters single location. It is cleared by performing a single write +// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 + +// Field: [4] RXRIS +// +// Receive interrupt status: +// This field returns the raw interrupt state of UART's receive interrupt. +// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if +// the receive FIFO reaches the programmed trigger +// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from +// the receive FIFO until it becomes less than the trigger level, or by +// clearing the interrupt through ICR.RXIC. +// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one +// location, the receive interrupt is asserted if data is received +// thereby filling the location. The receive interrupt is cleared by performing +// a single read of the receive FIFO, or by clearing the interrupt through +// ICR.RXIC. +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 + +// Field: [1] CTSRMIS +// +// Clear to Send (CTS) modem interrupt status: +// This field returns the raw interrupt state of UART's clear to send +// interrupt. +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_MIS +// +//***************************************************************************** +// Field: [11] EOTMIS +// +// End of Transmission interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.EOTRIS and the mask setting +// IMSC.EOTIM. +#define UART_MIS_EOTMIS 0x00000800 +#define UART_MIS_EOTMIS_BITN 11 +#define UART_MIS_EOTMIS_M 0x00000800 +#define UART_MIS_EOTMIS_S 11 + +// Field: [10] OEMIS +// +// Overrun error masked interrupt status: +// This field returns the masked interrupt state of the overrun interrupt which +// is the AND product of raw interrupt state RIS.OERIS and the mask setting +// IMSC.OEIM. +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 + +// Field: [9] BEMIS +// +// Break error masked interrupt status: +// This field returns the masked interrupt state of the break error interrupt +// which is the AND product of raw interrupt state RIS.BERIS and the mask +// setting IMSC.BEIM. +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 + +// Field: [8] PEMIS +// +// Parity error masked interrupt status: +// This field returns the masked interrupt state of the parity error interrupt +// which is the AND product of raw interrupt state RIS.PERIS and the mask +// setting IMSC.PEIM. +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 + +// Field: [7] FEMIS +// +// Framing error masked interrupt status: Returns the masked interrupt state of +// the framing error interrupt which is the AND product of raw interrupt state +// RIS.FERIS and the mask setting IMSC.FEIM. +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 + +// Field: [6] RTMIS +// +// Receive timeout masked interrupt status: +// Returns the masked interrupt state of the receive timeout interrupt. +// The raw interrupt for receive timeout cannot be set unless the mask is set +// (IMSC.RTIM = 1). This is because the mask acts as an enable for power +// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 + +// Field: [5] TXMIS +// +// Transmit masked interrupt status: +// This field returns the masked interrupt state of the transmit interrupt +// which is the AND product of raw interrupt state RIS.TXRIS and the mask +// setting IMSC.TXIM. +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 + +// Field: [4] RXMIS +// +// Receive masked interrupt status: +// This field returns the masked interrupt state of the receive interrupt +// which is the AND product of raw interrupt state RIS.RXRIS and the mask +// setting IMSC.RXIM. +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 + +// Field: [1] CTSMMIS +// +// Clear to Send (CTS) modem masked interrupt status: +// This field returns the masked interrupt state of the clear to send interrupt +// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask +// setting IMSC.CTSMIM. +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 + +//***************************************************************************** +// +// Register: UART_O_ICR +// +//***************************************************************************** +// Field: [11] EOTIC +// +// End of Transmission interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). +// Writing 0 has no effect. +#define UART_ICR_EOTIC 0x00000800 +#define UART_ICR_EOTIC_BITN 11 +#define UART_ICR_EOTIC_M 0x00000800 +#define UART_ICR_EOTIC_S 11 + +// Field: [10] OEIC +// +// Overrun error interrupt clear: +// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). +// Writing 0 has no effect. +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 + +// Field: [9] BEIC +// +// Break error interrupt clear: +// Writing 1 to this field clears the break error interrupt (RIS.BERIS). +// Writing 0 has no effect. +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 + +// Field: [8] PEIC +// +// Parity error interrupt clear: +// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). +// Writing 0 has no effect. +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 + +// Field: [7] FEIC +// +// Framing error interrupt clear: +// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). +// Writing 0 has no effect. +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 + +// Field: [6] RTIC +// +// Receive timeout interrupt clear: +// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). +// Writing 0 has no effect. +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 + +// Field: [5] TXIC +// +// Transmit interrupt clear: +// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 +// has no effect. +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 + +// Field: [4] RXIC +// +// Receive interrupt clear: +// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 +// has no effect. +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 + +// Field: [1] CTSMIC +// +// Clear to Send (CTS) modem interrupt clear: +// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). +// Writing 0 has no effect. +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 + +//***************************************************************************** +// +// Register: UART_O_DMACTL +// +//***************************************************************************** +// Field: [2] DMAONERR +// +// DMA on error. If this bit is set to 1, the DMA receive request outputs (for +// single and burst requests) are disabled when the UART error interrupt is +// asserted (more specifically if any of the error interrupts RIS.PERIS, +// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 + +// Field: [1] TXDMAE +// +// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is +// enabled. +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 + +// Field: [0] RXDMAE +// +// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is +// enabled. +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 + + +#endif // __UART__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_udma.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_udma.h new file mode 100644 index 00000000..6896cbca --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_udma.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* Filename: hw_udma_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// UDMA component +// +//***************************************************************************** +// Status +#define UDMA_O_STATUS 0x00000000 + +// Configuration +#define UDMA_O_CFG 0x00000004 + +// Channel Control Data Base Pointer +#define UDMA_O_CTRL 0x00000008 + +// Channel Alternate Control Data Base Pointer +#define UDMA_O_ALTCTRL 0x0000000C + +// Channel Wait On Request Status +#define UDMA_O_WAITONREQ 0x00000010 + +// Channel Software Request +#define UDMA_O_SOFTREQ 0x00000014 + +// Channel Set UseBurst +#define UDMA_O_SETBURST 0x00000018 + +// Channel Clear UseBurst +#define UDMA_O_CLEARBURST 0x0000001C + +// Channel Set Request Mask +#define UDMA_O_SETREQMASK 0x00000020 + +// Clear Channel Request Mask +#define UDMA_O_CLEARREQMASK 0x00000024 + +// Set Channel Enable +#define UDMA_O_SETCHANNELEN 0x00000028 + +// Clear Channel Enable +#define UDMA_O_CLEARCHANNELEN 0x0000002C + +// Channel Set Primary-Alternate +#define UDMA_O_SETCHNLPRIALT 0x00000030 + +// Channel Clear Primary-Alternate +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 + +// Set Channel Priority +#define UDMA_O_SETCHNLPRIORITY 0x00000038 + +// Clear Channel Priority +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C + +// Error Status and Clear +#define UDMA_O_ERROR 0x0000004C + +// Channel Request Done +#define UDMA_O_REQDONE 0x00000504 + +// Channel Request Done Mask +#define UDMA_O_DONEMASK 0x00000520 + +//***************************************************************************** +// +// Register: UDMA_O_STATUS +// +//***************************************************************************** +// Field: [31:28] TEST +// +// +// 0x0: Controller does not include the integration test logic +// 0x1: Controller includes the integration test logic +// 0x2: Undefined +// ... +// 0xF: Undefined +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 + +// Field: [20:16] TOTALCHANNELS +// +// Register value returns number of available uDMA channels minus one. For +// example a read out value of: +// +// 0x00: Show that the controller is configured to use 1 uDMA channel +// 0x01: Shows that the controller is configured to use 2 uDMA channels +// ... +// 0x1F: Shows that the controller is configured to use 32 uDMA channels +// (32-1=31=0x1F) +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 + +// Field: [7:4] STATE +// +// Current state of the control state machine. State can be one of the +// following: +// +// 0x0: Idle +// 0x1: Reading channel controller data +// 0x2: Reading source data end pointer +// 0x3: Reading destination data end pointer +// 0x4: Reading source data +// 0x5: Writing destination data +// 0x6: Waiting for uDMA request to clear +// 0x7: Writing channel controller data +// 0x8: Stalled +// 0x9: Done +// 0xA: Peripheral scatter-gather transition +// 0xB: Undefined +// ... +// 0xF: Undefined. +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 + +// Field: [0] MASTERENABLE +// +// Shows the enable status of the controller as configured by CFG.MASTERENABLE: +// +// 0: Controller is disabled +// 1: Controller is enabled +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CFG +// +//***************************************************************************** +// Field: [7:5] PRTOCTRL +// +// Sets the AHB-Lite bus protocol protection state by controlling the AHB +// signal HProt[3:1] as follows: +// +// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. +// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. +// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. +// +// When bit [n] = 1 then the corresponding HProt bit is high. +// When bit [n] = 0 then the corresponding HProt bit is low. +// +// This field controls HProt[3:1] signal for all transactions initiated by uDMA +// except two transactions below: +// - the read from the address indicated by source address pointer +// - the write to the address indicated by destination address pointer +// HProt[3:1] for these two exceptions can be controlled by dedicated fields in +// the channel configutation descriptor. +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 + +// Field: [0] MASTERENABLE +// +// Enables the controller: +// +// 0: Disables the controller +// 1: Enables the controller +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CTRL +// +//***************************************************************************** +// Field: [31:10] BASEPTR +// +// This register point to the base address for the primary data structures of +// each DMA channel. This is not stored in module, but in system memory, thus +// space must be allocated for this usage when DMA is in usage +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 + +//***************************************************************************** +// +// Register: UDMA_O_ALTCTRL +// +//***************************************************************************** +// Field: [31:0] BASEPTR +// +// This register shows the base address for the alternate data structures and +// is calculated by module, thus read only +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_WAITONREQ +// +//***************************************************************************** +// Field: [31:0] CHNLSTATUS +// +// Channel wait on request status: +// +// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, +// this channel may come out of active state even if request is still present. +// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it +// keeps channel Ch in active state until the requests are deasserted. This +// handshake is necessary for channels where the requester is in an +// asynchronous domain or can run at slower clock speed than uDMA +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SOFTREQ +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to generate a software uDMA request on the +// corresponding uDMA channel +// +// Bit [Ch] = 0: Does not create a uDMA request for channel Ch +// Bit [Ch] = 1: Creates a uDMA request for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented does not create a +// uDMA request for that channel +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the useburst status, or disables individual channels from generating +// single uDMA requests. The value R is the arbitration rate and stored in the +// controller data structure. +// +// Read as: +// +// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on +// channel C. The controller performs 2^R, or single, bus transfers. +// +// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. +// The controller only responds to burst transfer requests and performs 2^R +// transfers. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. +// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The +// controller performs 2^R transfers for burst requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARBURST +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable single transfer requests. +// +// Write as: +// +// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer +// requests. +// +// Bit [Ch] = 1: Enables single transfer requests on channel Ch. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the burst and single request mask status, or disables the +// corresponding channel from generating uDMA requests. +// +// Read as: +// Bit [Ch] = 0: External requests are enabled for channel Ch. +// Bit [Ch] = 1: External requests are disabled for channel Ch. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. +// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single +// request channel [C] input from generating uDMA requests. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARREQMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to enable DMA request for the channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from +// generating requests. +// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. +// +// Writing to a bit where a DMA channel is not implemented has no effect. +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the enable status of the channels, or enables the corresponding +// channels. +// +// Read as: +// Bit [Ch] = 0: Channel Ch is disabled. +// Bit [Ch] = 1: Channel Ch is enabled. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel +// Bit [Ch] = 1: Enables channel Ch +// +// Writing to a bit where a DMA channel is not implemented has no effect +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHANNELEN +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Set the appropriate bit to disable the corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. +// Bit [Ch] = 1: Disables channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel control data structure status, or selects the alternate +// data structure for the corresponding uDMA channel. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. +// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel +// Bit [Ch] = 1: Selects the alternate data structure for channel Ch +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIALT +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clears the appropriate bit to select the primary data structure for the +// corresponding uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate +// data structure. +// Bit [Ch] = 1: Selects the primary data structure for channel Ch. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_SETCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Returns the channel priority mask status, or sets the channel priority to +// high. +// +// Read as: +// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. +// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch +// to the default priority level. +// Bit [Ch] = 1: Channel Ch uses the high priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_CLEARCHNLPRIORITY +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Clear the appropriate bit to select the default priority level for the +// specified uDMA channel. +// +// Write as: +// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to +// the high priority level. +// Bit [Ch] = 1: Channel Ch uses the default priority level. +// +// Writing to a bit where a uDMA channel is not implemented has no effect +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_ERROR +// +//***************************************************************************** +// Field: [0] STATUS +// +// Returns the status of bus error flag in uDMA, or clears this bit +// +// Read as: +// +// 0: No bus error detected +// 1: Bus error detected +// +// Write as: +// +// 0: No effect, status of bus error flag is unchanged. +// 1: Clears the bus error flag. +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_REQDONE +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Reflects the uDMA done status for the given channel, channel [Ch]. It's a +// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. +// +// Read as: +// Bit [Ch] = 0: Request has not completed for channel Ch +// Bit [Ch] = 1: Request has completed for the channel Ch +// +// Writing a 1 to individual bits would clear the corresponding bit. +// +// Write as: +// Bit [Ch] = 0: No effect. +// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 + +//***************************************************************************** +// +// Register: UDMA_O_DONEMASK +// +//***************************************************************************** +// Field: [31:0] CHNLS +// +// Controls the propagation of the uDMA done and active state to the assigned +// peripheral. Specifically used for software channels. +// +// Read as: +// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is blocked from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from +// reaching to the peripherals. +// Note that the uDMA done state for channel [Ch] is not blocked from +// contributing to generation of combined uDMA done signal +// +// Write as: +// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the +// peripherals. +// Note that this disables uDMA done state for channel [Ch] from contributing +// to generation of combined uDMA done signal +// +// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the +// peripherals. +// Note that this enables uDMA done for channel [Ch] to contribute to +// generation of combined uDMA done signal. +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 + + +#endif // __UDMA__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_vims.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_vims.h new file mode 100644 index 00000000..ff1d79fc --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_vims.h @@ -0,0 +1,204 @@ +/****************************************************************************** +* Filename: hw_vims_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_VIMS_H__ +#define __HW_VIMS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// VIMS component +// +//***************************************************************************** +// Status +#define VIMS_O_STAT 0x00000000 + +// Control +#define VIMS_O_CTL 0x00000004 + +//***************************************************************************** +// +// Register: VIMS_O_STAT +// +//***************************************************************************** +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer status +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enabled or in transition to disabled +// 1: Disabled and flushed +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 + +// Field: [3] MODE_CHANGING +// +// VIMS mode change status +// +// 0: VIMS is in the mode defined by MODE +// 1: VIMS is in the process of changing to the mode given in CTL.MODE +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 + +// Field: [2] INV +// +// This bit is set when invalidation of the cache memory is active / ongoing +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 + +// Field: [1:0] MODE +// +// Current VIMS mode +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 + +//***************************************************************************** +// +// Register: VIMS_O_CTL +// +//***************************************************************************** +// Field: [31] STATS_CLR +// +// Set this bit to clear statistic counters. +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 + +// Field: [30] STATS_EN +// +// Set this bit to enable statistic counters. +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 + +// Field: [29] DYN_CG_EN +// +// 0: The in-built clock gate functionality is bypassed. +// 1: The in-built clock gate functionality is enabled, automatically gating +// the clock when not needed. +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 + +// Field: [5] IDCODE_LB_DIS +// +// Icode/Dcode flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 + +// Field: [4] SYSBUS_LB_DIS +// +// Sysbus flash line buffer control +// +// 0: Enable +// 1: Disable +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 + +// Field: [3] ARB_CFG +// +// Icode/Dcode and sysbus arbitation scheme +// +// 0: Static arbitration (icode/docde > sysbus) +// 1: Round-robin arbitration +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 + +// Field: [2] PREF_EN +// +// Tag prefetch control +// +// 0: Disabled +// 1: Enabled +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 + +// Field: [1:0] MODE +// +// VIMS mode request. +// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set +// to 1. +// ENUMs: +// OFF VIMS Off mode +// CACHE VIMS Cache mode +// GPRAM VIMS GPRAM mode +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 + + +#endif // __VIMS__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_wdt.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_wdt.h new file mode 100644 index 00000000..b71797d9 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/inc/hw_wdt.h @@ -0,0 +1,290 @@ +/****************************************************************************** +* Filename: hw_wdt_h +* Revised: $Date$ +* Revision: $Revision$ +* +* Copyright (c) 2015 - 2017, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// WDT component +// +//***************************************************************************** +// Configuration +#define WDT_O_LOAD 0x00000000 + +// Current Count Value +#define WDT_O_VALUE 0x00000004 + +// Control +#define WDT_O_CTL 0x00000008 + +// Interrupt Clear +#define WDT_O_ICR 0x0000000C + +// Raw Interrupt Status +#define WDT_O_RIS 0x00000010 + +// Masked Interrupt Status +#define WDT_O_MIS 0x00000014 + +// Test Mode +#define WDT_O_TEST 0x00000418 + +// Interrupt Cause Test Mode +#define WDT_O_INT_CAUS 0x0000041C + +// Lock +#define WDT_O_LOCK 0x00000C00 + +//***************************************************************************** +// +// Register: WDT_O_LOAD +// +//***************************************************************************** +// Field: [31:0] WDTLOAD +// +// This register is the 32-bit interval value used by the 32-bit counter. When +// this register is written, the value is immediately loaded and the counter is +// restarted to count down from the new value. If this register is loaded with +// 0x0000.0000, an interrupt is immediately generated. +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 + +//***************************************************************************** +// +// Register: WDT_O_VALUE +// +//***************************************************************************** +// Field: [31:0] WDTVALUE +// +// This register contains the current count value of the timer. +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 + +//***************************************************************************** +// +// Register: WDT_O_CTL +// +//***************************************************************************** +// Field: [2] INTTYPE +// +// WDT Interrupt Type +// +// 0: WDT interrupt is a standard interrupt. +// 1: WDT interrupt is a non-maskable interrupt. +// ENUMs: +// NONMASKABLE Non-maskable interrupt +// MASKABLE Maskable interrupt +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 + +// Field: [1] RESEN +// +// WDT Reset Enable. Defines the function of the WDT reset source (see +// PRCM:WARMRESET.WDT_STAT if enabled) +// +// 0: Disabled. +// 1: Enable the Watchdog reset output. +// ENUMs: +// EN Reset output Enabled +// DIS Reset output Disabled +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 + +// Field: [0] INTEN +// +// WDT Interrupt Enable +// +// 0: Interrupt event disabled. +// 1: Interrupt event enabled. Once set, this bit can only be cleared by a +// hardware reset. +// ENUMs: +// EN Interrupt Enabled +// DIS Interrupt Disabled +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_ICR +// +//***************************************************************************** +// Field: [31:0] WDTICR +// +// This register is the interrupt clear register. A write of any value to this +// register clears the WDT interrupt and reloads the 32-bit counter from the +// LOAD register. +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_RIS +// +//***************************************************************************** +// Field: [0] WDTRIS +// +// This register is the raw interrupt status register. WDT interrupt events can +// be monitored via this register if the controller interrupt is masked. +// +// Value Description +// +// 0: The WDT has not timed out +// 1: A WDT time-out event has occurred +// +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_MIS +// +//***************************************************************************** +// Field: [0] WDTMIS +// +// This register is the masked interrupt status register. The value of this +// register is the logical AND of the raw interrupt bit and the WDT interrupt +// enable bit CTL.INTEN. +// +// Value Description +// +// 0: The WDT has not timed out or is masked. +// 1: An unmasked WDT time-out event has occurred. +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 + +//***************************************************************************** +// +// Register: WDT_O_TEST +// +//***************************************************************************** +// Field: [8] STALL +// +// WDT Stall Enable +// +// 0: The WDT timer continues counting if the CPU is stopped with a debugger. +// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the +// CPU is restarted, the WDT resumes counting. +// ENUMs: +// EN Enable STALL +// DIS Disable STALL +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 + +// Field: [0] TEST_EN +// +// The test enable bit +// +// 0: Enable external reset +// 1: Disables the generation of an external reset. Instead bit 1 of the +// INT_CAUS register is set and an interrupt is generated +// ENUMs: +// EN Test mode Enabled +// DIS Test mode Disabled +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 + +//***************************************************************************** +// +// Register: WDT_O_INT_CAUS +// +//***************************************************************************** +// Field: [1] CAUSE_RESET +// +// Indicates that the cause of an interrupt was a reset generated but blocked +// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 + +// Field: [0] CAUSE_INTR +// +// Replica of RIS.WDTRIS +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 + +//***************************************************************************** +// +// Register: WDT_O_LOCK +// +//***************************************************************************** +// Field: [31:0] WDTLOCK +// +// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers +// for write access. A write of any other value reapplies the lock, preventing +// any register updates (NOTE: TEST.TEST_EN bit is not lockable). +// +// A read of this register returns the following values: +// +// 0x0000.0000: Unlocked +// 0x0000.0001: Locked +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 + + +#endif // __WDT__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.c new file mode 100644 index 00000000..37585b41 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.c @@ -0,0 +1,527 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_bt5.c +* +* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2021, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_bt5.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageBt5[] = { + 0x210043f5, + 0x21004079, + 0x21004095, + 0x21004469, + 0x210044a5, + 0x210040c5, + 0x210040d1, + 0x210040dd, + 0x210040f9, + 0x2100454f, + 0x21004141, + 0xd00507db, + 0xf803f000, + 0x70084902, + 0xb570bd70, + 0x47284d01, + 0x210004e0, + 0x0002241d, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0x4700b570, + 0xfa16f000, + 0x47004800, + 0x00007f57, + 0xfa16f000, + 0x47004800, + 0x0000881b, + 0x0a889905, + 0xd1052880, + 0x78884913, + 0x0f800780, + 0xfa20f000, + 0x47004800, + 0x00006ed9, + 0x480fb40f, + 0x290088c1, + 0x4610d002, + 0xfa14f000, + 0x0a9b9b07, + 0x2b834d08, + 0x4c08d108, + 0x069b8923, + 0xf000d504, + 0x2800f805, + 0x3542d000, + 0x4728bc0f, + 0x4804b570, + 0x00004700, + 0x00020b1f, + 0x21000160, + 0x21000380, + 0x000209eb, + 0x4a094808, + 0x429a6803, + 0x4808d10a, + 0x4b088902, + 0xd0011ad2, + 0xd1032a01, + 0x49066e40, + 0x99034788, + 0x47184b05, + 0x210002a8, + 0x000203bd, + 0x21000160, + 0x00001821, + 0x000035f1, + 0x000006bd, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x4c86b510, + 0x31404621, + 0x28017d08, + 0x4884d134, + 0x08407dc0, + 0xd02f07c0, + 0x30604620, + 0x08527942, + 0xd02907d2, + 0x0b808940, + 0xd1252801, + 0x09417e08, + 0xd00c07c9, + 0x07006fa1, + 0x0fc08809, + 0x04090240, + 0x66604308, + 0x1c806fa0, + 0xf980f000, + 0x4874e013, + 0x69803020, + 0x28006840, + 0x4a72d00e, + 0x78012300, + 0x1a5956d3, + 0x00c9d408, + 0x78411808, + 0xd00307c9, + 0x66616801, + 0x66a06840, + 0x4780486b, + 0xb5f8bd10, + 0x496a4c66, + 0x36204626, + 0x46257b70, + 0x90003540, + 0x00b8792f, + 0x68801840, + 0x28004780, + 0x4960d128, + 0x09097dc9, + 0xd02307c9, + 0x32644622, + 0xd0202f15, + 0x23007e29, + 0x07ff094f, + 0x7d6dd003, + 0xd0002d00, + 0x9f002301, + 0x43bb6fa5, + 0x7b73d012, + 0xd00f2b00, + 0x065b7d23, + 0x88d2d50c, + 0x2a010b92, + 0x08c9d108, + 0xd00507c9, + 0x0b8988a9, + 0xd1012901, + 0x73712100, + 0x7eabbdf8, + 0x2b017de9, + 0x2300d0e3, + 0xb570e7e1, + 0x46254c46, + 0x35806a60, + 0xd11d2800, + 0x5d002054, + 0x28002200, + 0x2064d017, + 0x08805d00, + 0xd01207c0, + 0x888868a9, + 0x28010b80, + 0x483dd10d, + 0x08407dc0, + 0xd00807c0, + 0x3020483a, + 0x68006980, + 0xd0022800, + 0x60a86229, + 0x622ae000, + 0x47804839, + 0x29006a61, + 0x6a29d103, + 0xd0002900, + 0xbd7060a9, + 0x4c2fb5f8, + 0x46204934, + 0x7d023040, + 0xd02f2a00, + 0x46257e80, + 0x28033580, + 0x2804d002, + 0xe027d003, + 0x75e82001, + 0x2064e024, + 0x08805d00, + 0xd01f07c0, + 0x888068a8, + 0x28010b80, + 0x4822d11a, + 0x7dc07dea, + 0xd0132a00, + 0x07c008c0, + 0x4626d012, + 0x7b773620, + 0x46014788, + 0xd1084339, + 0x06097d21, + 0x8869d505, + 0x29010b89, + 0x2100d101, + 0xbdf87371, + 0xe7ea0880, + 0xbdf84788, + 0x30804812, + 0x75c12100, + 0x47004817, + 0x3140490f, + 0x28267108, + 0xdc06d014, + 0xd0132815, + 0xd00b281b, + 0xd104281f, + 0x283de00a, + 0x2847d00e, + 0x490bd00a, + 0x18400080, + 0x47706880, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x21000160, + 0x210000c8, + 0x210004e0, + 0x00024959, + 0x00025500, + 0x00023d8f, + 0x00023075, + 0x00022a15, + 0x210043e9, + 0x21004375, + 0x21004317, + 0x21004297, + 0x21004219, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x4810b510, + 0x481088c1, + 0xd0182905, + 0x68214c0f, + 0x0052084a, + 0x6ba26022, + 0x00520852, + 0x602163a2, + 0xfdfcf7ff, + 0x07006ba0, + 0x2001d408, + 0x60606020, + 0x1c402000, + 0xdbfc280c, + 0x62202014, + 0xf7ffbd10, + 0xbd10fded, + 0x21000380, + 0x00005b3f, + 0x40046000, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x79c94908, + 0x07d208ca, + 0x40c1d008, + 0x07c94806, + 0x4906d001, + 0x4906e000, + 0x60c11c49, + 0x20004770, + 0x00004770, + 0x210000e8, + 0x21000028, + 0x00000188, + 0x00000150, + 0x07810882, + 0x0ec90092, + 0x78c0ca0c, + 0x424940ca, + 0x408b3120, + 0x0211431a, + 0x06000a09, + 0x47704308, +}; +#define _NWORD_PATCHIMAGE_BT5 334 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_BT5 1 + +#define _NWORD_PATCHSYS_BT5 0 + +#define _IRQ_PATCH_0 0x2100417d + + +#ifndef _BT5_SYSRAM_START +#define _BT5_SYSRAM_START 0x20000000 +#endif + +#ifndef _BT5_CPERAM_START +#define _BT5_CPERAM_START 0x21000000 +#endif + +#define _BT5_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _BT5_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _BT5_PATCH_TAB_OFFSET 0x03D4 +#define _BT5_IRQPATCH_OFFSET 0x0480 +#define _BT5_PATCH_VEC_OFFSET 0x404C + +#define _BT5_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _BT5_NO_PROG_STATE_VAR +static uint8_t bBt5PatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterBt5CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_BT5 > 0) + uint32_t *pPatchVec = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageBt5, sizeof(patchImageBt5)); +#endif +} + +PATCH_FUN_SPEC void enterBt5CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_BT5 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterBt5SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureBt5Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_BT5_CPERAM_START + _BT5_IRQPATCH_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[21] = 1; + pPatchTab[76] = 2; + pPatchTab[91] = 3; + pPatchTab[79] = 4; + pPatchTab[140] = 5; + pPatchTab[150] = 6; + pPatchTab[107] = 7; + pPatchTab[13] = 8; + pPatchTab[31] = 9; + pPatchTab[40] = 10; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyBt5Patch(void) +{ +#ifdef _BT5_NO_PROG_STATE_VAR + enterBt5SysPatch(); + enterBt5CpePatch(); +#else + if (!bBt5PatchEntered) + { + enterBt5SysPatch(); + enterBt5CpePatch(); + bBt5PatchEntered = 1; + } +#endif + enterBt5CpeHdPatch(); + configureBt5Patch(); +} + +void refreshBt5Patch(void) +{ + enterBt5CpeHdPatch(); + configureBt5Patch(); +} + +void cleanBt5Patch(void) +{ +#ifndef _BT5_NO_PROG_STATE_VAR + bBt5PatchEntered = 0; +#endif +} + +void rf_patch_cpe_bt5(void) +{ + applyBt5Patch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.h new file mode 100644 index 00000000..53502eb2 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_bt5.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_bt5.h +* +* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2021, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_BT5_H +#define _RF_PATCH_CPE_BT5_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanBt5Patch(void); +extern void refreshBt5Patch(void); +extern void rf_patch_cpe_bt5(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_BT5_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.c new file mode 100644 index 00000000..f317b32c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.c @@ -0,0 +1,286 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee_802_15_4.c +* +* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_ieee_802_15_4.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageIeee802154[] = { + 0x21004061, + 0x2100408d, + 0x21004099, + 0x210040ff, + 0x2100416f, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf80af000, + 0x47004800, + 0x00007f57, + 0xf80af000, + 0x47004800, + 0x0000881b, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x4833b510, + 0x47804c31, + 0xd0072801, + 0x7d213420, + 0xd1032900, + 0x4a2f2101, + 0x60910509, + 0x2807bd10, + 0x4a2dd001, + 0x4a2d4710, + 0x72c8604a, + 0x22014770, + 0x21024b2c, + 0x4718482a, + 0xb5104827, + 0x478030f8, + 0x6a404829, + 0xd10d2800, + 0x200a4928, + 0x28005608, + 0x1c40da09, + 0x4608d007, + 0x6a403820, + 0x42884924, + 0x4780d100, + 0xf7ffbd10, + 0xbd10ffe2, + 0x4b222100, + 0x46084a20, + 0x20014718, + 0x02404920, + 0x48206008, + 0x780122fb, + 0x70014011, + 0x300c4813, + 0xb5104700, + 0x4788491c, + 0x39204915, + 0xd0072801, + 0xd5040402, + 0x85082000, + 0x62484818, + 0xbd102001, + 0x4b0a6a4a, + 0x429a330c, + 0x4a15d101, + 0x490be005, + 0x4b146a4a, + 0xd1f2429a, + 0x624a4a13, + 0x0000bd10, + 0x21000160, + 0x0002a675, + 0x40041100, + 0x000291a9, + 0x210040e1, + 0x00000806, + 0x0000069f, + 0x21000108, + 0x21000154, + 0x00029263, + 0x21004119, + 0x0002b4b5, + 0xe000e180, + 0x21000380, + 0x000296f7, + 0x2100410f, + 0x21004157, + 0x00029569, + 0x2100414d, +}; +#define _NWORD_PATCHIMAGE_IEEE_802_15_4 107 + +#define _NWORD_PATCHCPEHD_IEEE_802_15_4 0 + +#define _NWORD_PATCHSYS_IEEE_802_15_4 0 + + + +#ifndef _IEEE_802_15_4_SYSRAM_START +#define _IEEE_802_15_4_SYSRAM_START 0x20000000 +#endif + +#ifndef _IEEE_802_15_4_CPERAM_START +#define _IEEE_802_15_4_CPERAM_START 0x21000000 +#endif + +#define _IEEE_802_15_4_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _IEEE_802_15_4_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x03D4 +#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0480 +#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x404C + +#define _IEEE_802_15_4_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR +static uint8_t bIeee802154PatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterIeee802154CpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_IEEE_802_15_4 > 0) + uint32_t *pPatchVec = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageIeee802154, sizeof(patchImageIeee802154)); +#endif +} + +PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterIeee802154SysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureIeee802154Patch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[140] = 1; + pPatchTab[150] = 2; + pPatchTab[7] = 3; + pPatchTab[164] = 4; +} + +PATCH_FUN_SPEC void applyIeee802154Patch(void) +{ +#ifdef _IEEE_802_15_4_NO_PROG_STATE_VAR + enterIeee802154SysPatch(); + enterIeee802154CpePatch(); +#else + if (!bIeee802154PatchEntered) + { + enterIeee802154SysPatch(); + enterIeee802154CpePatch(); + bIeee802154PatchEntered = 1; + } +#endif + enterIeee802154CpeHdPatch(); + configureIeee802154Patch(); +} + +void refreshIeee802154Patch(void) +{ + enterIeee802154CpeHdPatch(); + configureIeee802154Patch(); +} + +void cleanIeee802154Patch(void) +{ +#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR + bIeee802154PatchEntered = 0; +#endif +} + +void rf_patch_cpe_ieee_802_15_4(void) +{ + applyIeee802154Patch(); +} + + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.h new file mode 100644 index 00000000..676fd2ad --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_802_15_4.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee_802_15_4.h +* +* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_IEEE_802_15_4_H +#define _RF_PATCH_CPE_IEEE_802_15_4_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanIeee802154Patch(void); +extern void refreshIeee802154Patch(void); +extern void rf_patch_cpe_ieee_802_15_4(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_IEEE_802_15_4_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.c new file mode 100644 index 00000000..d077fe6f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.c @@ -0,0 +1,1196 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee_coex.c +* +* Description: RF core patch for IEEE 802.15.4-Coex support ("IEEE" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_ieee_coex.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageIeeeCoex[] = { + 0x21004071, + 0x2100409d, + 0x210040a9, + 0x21004127, + 0x2100419f, + 0x21004d11, + 0x21004d33, + 0x21004d53, + 0x21004dd1, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf816f000, + 0x47004800, + 0x00007f57, + 0xf816f000, + 0x47004800, + 0x0000881b, + 0x4700b570, + 0x4700b5f8, + 0xb082b5f7, + 0x47204c00, + 0x000006bd, + 0x4700b5f8, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x483cb510, + 0x47804c3a, + 0xd0072801, + 0x7d213420, + 0xd1032900, + 0x4a382101, + 0x60910509, + 0x2807bd10, + 0x4a36d001, + 0x4a364710, + 0x72c8604a, + 0x22014770, + 0x21024b35, + 0x47184833, + 0xf000b510, + 0x482ffe62, + 0x478030f8, + 0x6a404831, + 0xd10d2800, + 0x200a4930, + 0x28005608, + 0x1c40da09, + 0x4608d007, + 0x6a403820, + 0x4288492c, + 0x4780d100, + 0xf7ffbd10, + 0xbd10ffe0, + 0x4b2a2100, + 0x46084a28, + 0x20014718, + 0x02404928, + 0x48286008, + 0x780122fb, + 0x40114b24, + 0x21137001, + 0x20014a25, + 0xb5704718, + 0x46064924, + 0x4d1c4788, + 0x3d204604, + 0xd0082801, + 0xd5040420, + 0x85282000, + 0x6268481f, + 0x46202401, + 0x4630bd70, + 0xf95bf000, + 0x480e6a69, + 0x4281300c, + 0x481ad101, + 0x6a68e005, + 0x31ba490a, + 0xd1024288, + 0x62684817, + 0x480be7eb, + 0x4a166a41, + 0xd1e64291, + 0x62414915, + 0x0000e7e3, + 0x21000160, + 0x0002a675, + 0x40041100, + 0x000291a9, + 0x21004109, + 0x00000806, + 0x0000069f, + 0x21000108, + 0x21000154, + 0x00029263, + 0x21004141, + 0x0002b4b5, + 0xe000e180, + 0x21000380, + 0x21004735, + 0x000296f7, + 0x21004137, + 0x21004183, + 0x21004969, + 0x00029569, + 0x21004179, + 0x22ff0783, + 0x409a0edb, + 0x0e090789, + 0x28004099, + 0x0700da0b, + 0x38080f00, + 0x009b0883, + 0x181848ff, + 0x439369c3, + 0x61c3430b, + 0x08834770, + 0x009b48fc, + 0x68031818, + 0x430b4393, + 0x47706003, + 0x4684b5f0, + 0x7bc048f8, + 0xd07c2800, + 0x69634cf7, + 0xd0782b00, + 0x07f0781e, + 0xd0740fc0, + 0xd0722b00, + 0x25047858, + 0xd0072800, + 0x28012705, + 0x2802d006, + 0x2803d006, + 0xe006d109, + 0xe00272e5, + 0xe00372e5, + 0x72a572e7, + 0x72e7e001, + 0x08f072a7, + 0x4fe94de8, + 0xd04307c0, + 0x42014660, + 0x8858d040, + 0x0c010480, + 0x02002005, + 0xd0012a00, + 0xe0007aa2, + 0x2a057ae2, + 0x2900d021, + 0x69aad02e, + 0x181243ba, + 0x686861aa, + 0x4686696a, + 0x0200200f, + 0x32ff4382, + 0x320232ff, + 0x48d7616a, + 0x30402201, + 0x69aa6082, + 0x32ff43ba, + 0x320232ff, + 0x4ad261aa, + 0x32804471, + 0x7a606091, + 0xd0052801, + 0x69a9e00e, + 0x180843b9, + 0xe00961a8, + 0x4acd2002, + 0x03417260, + 0x4acc6011, + 0x4aca6011, + 0x60113a80, + 0x21017860, + 0x70604308, + 0x07c00870, + 0x4660d011, + 0x28002208, + 0x786049c5, + 0x0785d00c, + 0x694dd409, + 0x614d4315, + 0x43082102, + 0x79187060, + 0x43082101, + 0xbdf07118, + 0xd5fc0786, + 0x4396694e, + 0x21fd614e, + 0x79194008, + 0x00490849, + 0x69a97119, + 0x43b92201, + 0x18890292, + 0x084061a9, + 0x70600040, + 0x49afbdf0, + 0x4aaf2800, + 0x69884bac, + 0x4390d002, + 0xe0017a9a, + 0x7ada4390, + 0x43100212, + 0x47706188, + 0x49a5b530, + 0x29007bc9, + 0x49a3d04a, + 0x31404ba3, + 0x615a69ca, + 0xd0432a00, + 0x79514ca6, + 0x24011900, + 0xd0092800, + 0x1b4002a5, + 0x2801d004, + 0x2802d01b, + 0xe036d124, + 0xe0177a50, + 0x70dc7990, + 0x0fe40704, + 0x0784711c, + 0x719c0fe4, + 0x07e4088c, + 0x070cd002, + 0x719c0fe4, + 0x0fc007c0, + 0x07c873d8, + 0x0788d00e, + 0x73d80fc0, + 0x7a10e00a, + 0x070470dc, + 0x711c0fe4, + 0x0fe40784, + 0x715c07c0, + 0x73980fc0, + 0x24fd7910, + 0x78dc4020, + 0x43200064, + 0x08887110, + 0xd00207c0, + 0x0fc00708, + 0x07c87158, + 0x0788d002, + 0x73980fc0, + 0x79d0bd30, + 0x4983e7e0, + 0x42498800, + 0xd0084288, + 0x42884981, + 0x1c49d005, + 0xd0024288, + 0x42881c49, + 0xe79dd100, + 0xb5f04770, + 0x4a734694, + 0x7bd22500, + 0x2a004c72, + 0x6962d048, + 0xd0452a00, + 0x07de7813, + 0xd0410ff6, + 0xd03f2a00, + 0x07d2089a, + 0x74a02701, + 0xd0012a00, + 0xe00070a7, + 0x085a70a5, + 0xd01f07d2, + 0x74677427, + 0xd11e2800, + 0x74227962, + 0x40327ba6, + 0x29007462, + 0x79a2d104, + 0x7be67422, + 0x74624032, + 0x46664a5e, + 0x2e0079d2, + 0x7c26d004, + 0x4316408e, + 0xe00871e6, + 0x43ba408f, + 0x742571e2, + 0xe002d109, + 0x74657425, + 0x786171e5, + 0x42114662, + 0xf7ffd002, + 0xbdf0ff48, + 0x07c908d9, + 0x7465d100, + 0x7c614602, + 0xf7ff7c20, + 0xbdf0fea5, + 0xbdf070a5, + 0xb5104b4b, + 0x4619789a, + 0x78c94614, + 0xd0024384, + 0x430b795b, + 0x2a00d011, + 0x4381d00f, + 0x2001d10d, + 0x03c0494b, + 0x484a60c8, + 0x6ac03840, + 0xd5040400, + 0xf000207e, + 0x2000fcb1, + 0x2001bd10, + 0xb5f8bd10, + 0x25004c3b, + 0x7a926962, + 0x29020092, + 0x7ac1d011, + 0x7b5b4623, + 0xd00e2916, + 0xd0162915, + 0xd0012914, + 0xd1072917, + 0xd0052b00, + 0x21012200, + 0xf7ff4610, + 0x7365ff74, + 0x4937bdf8, + 0x07497809, + 0x2201d505, + 0x20004611, + 0xff69f7ff, + 0x2b00bdf8, + 0x2101d1fc, + 0x73614b2a, + 0x601e030e, + 0x601e4b29, + 0x37404f25, + 0x6a406039, + 0x1a8161a0, + 0x30804822, + 0x68016001, + 0x68404820, + 0xfc76f000, + 0xd0012800, + 0xe7de603d, + 0x3880481e, + 0xbdf86006, + 0xb510491a, + 0x31404822, + 0x48186048, + 0x220268c1, + 0x60c14311, + 0x03144818, + 0x21006004, + 0xf7ff200d, + 0x4911fe0f, + 0x73082001, + 0x6ac1481a, + 0x431100a2, + 0x481062c1, + 0x60043880, + 0xb570bd10, + 0x480d2401, + 0x600403a4, + 0x6004480c, + 0x69414808, + 0x0212220f, + 0x61414311, + 0x21014d05, + 0xe01d3540, + 0xe000ed00, + 0xe000e400, + 0x210000a8, + 0x21004fb4, + 0x40043000, + 0x00000700, + 0xe000e180, + 0xe000e280, + 0x40041100, + 0xffffd7ff, + 0x00002c01, + 0x40045040, + 0x21000380, + 0x00001702, + 0x40046080, + 0x49f960a9, + 0x6a092229, + 0x188a0112, + 0x608a49f7, + 0x68406889, + 0xfc16f000, + 0xd0032800, + 0x60a82000, + 0x600448f3, + 0x600448f3, + 0xb570bd70, + 0x21004dee, + 0x28007a28, + 0x4aedd103, + 0x68523a80, + 0x1c40622a, + 0x4aeab2c0, + 0x68547228, + 0x2a021e82, + 0x69ead81d, + 0x3a3c1aa2, + 0xd8152a0c, + 0xd1162804, + 0x680048e6, + 0x42904ae6, + 0x2101d100, + 0x72682001, + 0x20004602, + 0xfec3f7ff, + 0x28017a68, + 0x2003d107, + 0xf7ff7268, + 0xe002ff90, + 0x72282000, + 0xbf007268, + 0xbd7061ec, + 0x48dcb5f8, + 0x7ac04cda, + 0x07812500, + 0x29002602, + 0x48d9da03, + 0x72a68120, + 0x07c0e006, + 0x48d6d006, + 0x81201f40, + 0x72a02000, + 0xe0092503, + 0x46204629, + 0xff0df7ff, + 0x47806860, + 0xd0f70005, + 0xd0512d01, + 0x6a784fce, + 0xd0012800, + 0x47806a78, + 0x302048cb, + 0x5641210a, + 0xd0031c89, + 0x5641210a, + 0xd1091cc9, + 0x49c76838, + 0x42888800, + 0x6838d00a, + 0x88001c49, + 0xd0054288, + 0x1e4048c0, + 0x72a68120, + 0xe0032503, + 0xd0012d03, + 0xd12d2d02, + 0x382048ba, + 0x2d036806, + 0x2002d114, + 0xfb94f000, + 0x388048b0, + 0x69e16845, + 0xf0004628, + 0x2800fb87, + 0x2000d001, + 0x48b5e005, + 0x69e08941, + 0xf0001b40, + 0x81e0fb89, + 0x757089e0, + 0x61b06a20, + 0x6a2148ab, + 0x61813820, + 0x75b07b60, + 0x89207aa1, + 0xf0002201, + 0x6a78fb7f, + 0xd0012800, + 0x47806a78, + 0x48a0bdf8, + 0x49a76800, + 0xd10d4288, + 0x499b2001, + 0x39800300, + 0x489d6008, + 0x7b0038e0, + 0xd0052802, + 0x46112201, + 0xe62e2000, + 0x4700489f, + 0xb5f84770, + 0x4c964897, + 0x25007ac0, + 0x26020780, + 0xda032800, + 0x81204894, + 0x250372a6, + 0x78c04898, + 0xd0042800, + 0x1c404892, + 0x72a68120, + 0xb6722503, + 0x300120ff, + 0xfb4ef000, + 0x4f83b662, + 0x7838e00a, + 0xd0042800, + 0xf000207d, + 0x2503fb27, + 0x6860e004, + 0x46054780, + 0xd0f22d00, + 0x20ffb672, + 0xf0003001, + 0xb662fb3f, + 0x78404886, + 0xd00f2800, + 0x68404885, + 0xd50b0740, + 0x68004877, + 0xd5070700, + 0xf0002083, + 0x487bfb0b, + 0x81201d00, + 0x250372a6, + 0x28007838, + 0x2000d009, + 0x20817338, + 0xfafef000, + 0x1d404874, + 0x72a68120, + 0x2d03e004, + 0x2d02d002, + 0xbdf8d006, + 0xfb1cf000, + 0xfb20f000, + 0xfb24f000, + 0x89207aa1, + 0xf0002201, + 0x4864fb01, + 0x29006801, + 0x6800d0ef, + 0xbdf84780, + 0x4607b5f8, + 0x485d2401, + 0x38800424, + 0x4d5a6004, + 0x3d402600, + 0x4859612e, + 0x60043080, + 0x20104631, + 0xfc88f7ff, + 0x61282001, + 0x61074853, + 0x48526901, + 0x68403880, + 0xfaccf000, + 0xd0062800, + 0x2201612e, + 0x46104611, + 0xfd9ff7ff, + 0x484dbdf8, + 0xbdf86004, + 0x4c51b510, + 0x200a3420, + 0x1c805620, + 0x7ae0d113, + 0x43082120, + 0x400821bf, + 0x484b72e0, + 0x29006a41, + 0x6a40d001, + 0x200a4780, + 0x1cc05620, + 0x4843d12a, + 0x38e02102, + 0x493b7301, + 0x70082000, + 0x07807848, + 0x6949d418, + 0x7a894842, + 0x4a3d38a0, + 0x3a200089, + 0x6a128c00, + 0x1812460b, + 0x42833314, + 0x1a50d204, + 0xf7ff3814, + 0xe008ffa5, + 0x46112201, + 0xf7ff4610, + 0xe002fd62, + 0xf7ff2001, + 0x2118fcec, + 0x4a394b3a, + 0x47982001, + 0xb510bd10, + 0x4c2a4938, + 0x8005f3ef, + 0xd004281e, + 0x8005f3ef, + 0xd0222820, + 0x4834e036, + 0x28047d00, + 0x0300d132, + 0x491e6008, + 0x28027a48, + 0x2803d002, + 0xe029d005, + 0x72482003, + 0xfe0ff7ff, + 0x482cbd10, + 0x280e7800, + 0x2000d020, + 0x72087248, + 0x68204601, + 0x42904a18, + 0x2101d100, + 0x46102200, + 0x2001e011, + 0x60080400, + 0x20102101, + 0xfbfaf7ff, + 0x491c6820, + 0xd0034288, + 0x491f6820, + 0xd1054288, + 0x46112201, + 0xf7ff4610, + 0xbd10fd16, + 0x8005f3ef, + 0xf000381e, + 0x6820fa6b, + 0xd0f62800, + 0x47806820, + 0x0000bd10, + 0x21004fb4, + 0x40043080, + 0xe000e200, + 0xe000e100, + 0x210002a8, + 0x00028fe7, + 0x21000240, + 0x21000154, + 0x00002407, + 0x21000108, + 0x00002801, + 0x210000c8, + 0x21004735, + 0x00000b73, + 0x21000380, + 0x40045080, + 0x21004847, + 0x0002b4b5, + 0xe000e180, + 0x210002c0, + 0x21000018, + 0x21004969, + 0x4ee9b5f8, + 0x27007b30, + 0x28004ce8, + 0x48e8d004, + 0x0a006840, + 0xd0062817, + 0x7d0548e6, + 0x478048e6, + 0xd02d2d06, + 0x4ae5e034, + 0x60512101, + 0x73377031, + 0x230348e2, + 0x60033040, + 0x016d2561, + 0x604160c5, + 0x23596143, + 0x6203019b, + 0x20076181, + 0x49d86210, + 0x68483940, + 0x684a3018, + 0xd3fc4282, + 0xf0002000, + 0x48d7fa0d, + 0x22026941, + 0x61414391, + 0x48d3bf00, + 0x6ac13080, + 0x0c490449, + 0x031062c1, + 0xbdf86020, + 0x280078b0, + 0x7830d0fb, + 0xd1f82800, + 0xfd4cf7ff, + 0xd1f42d04, + 0xfda9f7ff, + 0x780048ca, + 0xd1ee280e, + 0x60200328, + 0x210048c8, + 0x4ac86800, + 0xd1004290, + 0x72772101, + 0x20002201, + 0xfc7ff7ff, + 0xbdf87237, + 0x48beb5f8, + 0x4fc26ac0, + 0x4eb74dc2, + 0xd00107c1, + 0xe05a2403, + 0x0f840700, + 0xd0042c01, + 0xd1072c02, + 0x28007fb8, + 0x2001d14d, + 0xfcbaf7ff, + 0xd0042800, + 0xd0282c01, + 0xd0232c02, + 0x4cb0e040, + 0x60602001, + 0x48b54601, + 0xf9c0f000, + 0x210120a1, + 0xf0000100, + 0x20c3f9bb, + 0x01002101, + 0xf9bcf000, + 0x62202007, + 0x20012403, + 0x20007030, + 0x48a47330, + 0x6ac13080, + 0x0c490449, + 0x200162c1, + 0x0340499c, + 0xe0246008, + 0x28007fb8, + 0x2001d11d, + 0xf998f000, + 0x08407ae8, + 0xd01107c0, + 0x07c07870, + 0x4995d009, + 0x69883940, + 0x02122207, + 0x7ab24390, + 0x43100212, + 0x48946188, + 0x22026941, + 0x61414311, + 0xd0022c02, + 0xd0042c03, + 0x2001e025, + 0xf98cf000, + 0x2000e021, + 0x488b7330, + 0x6ac13080, + 0x0c490449, + 0x210162c1, + 0xf7ff200d, + 0x4983fae3, + 0x60482000, + 0x4e802001, + 0x60300340, + 0xf0002000, + 0x2001f975, + 0x60300280, + 0x08407ae8, + 0xd00407c0, + 0x6941487e, + 0x43912202, + 0x77bc6141, + 0xb510bdf8, + 0x6ac04879, + 0xd02407c0, + 0x7bc1487d, + 0x29002000, + 0x4a70d01f, + 0x29006951, + 0x7808d003, + 0x0fc907c1, + 0x4979d017, + 0x06c06809, + 0x17c06849, + 0xd1104208, + 0x20014970, + 0x4b756809, + 0xd1004299, + 0x21012000, + 0x79d04081, + 0x71d04388, + 0x46112200, + 0xf7ff4610, + 0x486ffabf, + 0xbd104780, + 0x2400b510, + 0xf7ff486d, + 0x4864f9cd, + 0x49646800, + 0xd1004288, + 0x22002401, + 0x46104621, + 0xfbb7f7ff, + 0xb510bd10, + 0x6a404862, + 0x4288495d, + 0x2200d004, + 0x46104611, + 0xfbabf7ff, + 0x38b44860, + 0xf9b4f7ff, + 0xb5f7bd10, + 0x26014858, + 0x20007bc4, + 0x40964f4b, + 0x2c004615, + 0x6979d017, + 0xd0032900, + 0x07c47808, + 0xd0100fe4, + 0x793a7839, + 0xd1024391, + 0x07c00900, + 0x79f8d109, + 0x43b02200, + 0x461171f8, + 0xf7ff4610, + 0x2000fa7b, + 0x462a7038, + 0x98009901, + 0xf98ef7ff, + 0xd0012d00, + 0xe0004d46, + 0x68284d49, + 0x207fb281, + 0xf8eef000, + 0xd00a2c00, + 0x28006828, + 0x79f8d107, + 0x43b02200, + 0x461171f8, + 0xf7ff4610, + 0xbdfefa5d, + 0x4d40b570, + 0x48402400, + 0xf976f7ff, + 0x7d683520, + 0xd0062800, + 0x20004929, + 0x22017008, + 0x46104601, + 0x482ee008, + 0x492e6800, + 0xd1004288, + 0x22002401, + 0x46104621, + 0xfb4bf7ff, + 0xb570bd70, + 0x2500482a, + 0x28007bc0, + 0x491dd038, + 0x28006948, + 0x7800d003, + 0x0fc007c0, + 0x4c2bd030, + 0x380e7ae0, + 0xd82b2804, + 0x4e1b7808, + 0xd01a2800, + 0x07c06af0, + 0x2501d017, + 0xf882f000, + 0x20204917, + 0x20006088, + 0xf8a6f000, + 0x38404810, + 0x49186840, + 0x8cc93980, + 0x21001840, + 0xf0006160, + 0x6822f8a1, + 0x20024621, + 0x7ae04790, + 0xd1022812, + 0x07c06af0, + 0x2d00d101, + 0x2200d004, + 0x46104611, + 0xfb0bf7ff, + 0x0000bd70, + 0x21004fb4, + 0xe000e180, + 0x40043040, + 0x210002c0, + 0x000074f5, + 0x40046000, + 0x40041100, + 0x21000018, + 0x210002a8, + 0x00028fe7, + 0x210002a0, + 0x210000a8, + 0x00001670, + 0x21000134, + 0x21004141, + 0x00004089, + 0x00005b3f, + 0x21000108, + 0x21000160, + 0x00029de9, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x000075d1, + 0x4801b403, + 0xbd019001, + 0x00000fc1, + 0x4801b403, + 0xbd019001, + 0x00009361, + 0x4801b403, + 0xbd019001, + 0x0000069f, + 0x4801b403, + 0xbd019001, + 0x0000424f, + 0x4801b403, + 0xbd019001, + 0x0000423d, + 0x4801b403, + 0xbd019001, + 0x00007d65, + 0x4801b403, + 0xbd019001, + 0x00006655, + 0x4801b403, + 0xbd019001, + 0x00005d1b, + 0x4801b403, + 0xbd019001, + 0x00000c45, + 0x4801b403, + 0xbd019001, + 0x000085bd, + 0x4801b403, + 0xbd019001, + 0x00004e75, + 0x4801b403, + 0xbd019001, + 0x00004e4f, + 0x4801b403, + 0xbd019001, + 0x0000900f, + 0x4801b403, + 0xbd019001, + 0x00003ca9, + 0x4801b403, + 0xbd019001, + 0x00008303, + 0x4801b403, + 0xbd019001, + 0x000075f7, + 0x01000000, + 0x00000000, + 0x04050000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_IEEE_COEX 996 + +#define _NWORD_PATCHCPEHD_IEEE_COEX 0 + +#define _NWORD_PATCHSYS_IEEE_COEX 0 + +#define _IRQ_PATCH_0 0x2100481b +#define _IRQ_PATCH_1 0x210049ef +#define _IRQ_PATCH_2 0x21004ae5 +#define _IRQ_PATCH_3 0x21004ba5 +#define _IRQ_PATCH_4 0x21004cb7 + + +#ifndef _IEEE_COEX_SYSRAM_START +#define _IEEE_COEX_SYSRAM_START 0x20000000 +#endif + +#ifndef _IEEE_COEX_CPERAM_START +#define _IEEE_COEX_CPERAM_START 0x21000000 +#endif + +#define _IEEE_COEX_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _IEEE_COEX_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _IEEE_COEX_PATCH_TAB_OFFSET 0x03D4 +#define _IEEE_COEX_IRQPATCH_OFFSET 0x0480 +#define _IEEE_COEX_PATCH_VEC_OFFSET 0x404C + +#define _IEEE_COEX_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _IEEE_COEX_NO_PROG_STATE_VAR +static uint8_t bIeeeCoexPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterIeeeCoexCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_IEEE_COEX > 0) + uint32_t *pPatchVec = (uint32_t *) (_IEEE_COEX_CPERAM_START + _IEEE_COEX_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageIeeeCoex, sizeof(patchImageIeeeCoex)); +#endif +} + +PATCH_FUN_SPEC void enterIeeeCoexCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_IEEE_COEX > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_COEX_CPERAM_START + _IEEE_COEX_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterIeeeCoexSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureIeeeCoexPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_IEEE_COEX_CPERAM_START + _IEEE_COEX_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_IEEE_COEX_CPERAM_START + _IEEE_COEX_IRQPATCH_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[140] = 1; + pPatchTab[150] = 2; + pPatchTab[7] = 3; + pPatchTab[164] = 4; + pPatchTab[79] = 5; + pPatchTab[78] = 6; + pPatchTab[40] = 7; + pPatchTab[57] = 8; + + pIrqPatch[15] = _IRQ_PATCH_0; + pIrqPatch[19] = _IRQ_PATCH_1; + pIrqPatch[17] = _IRQ_PATCH_2; + pIrqPatch[21] = _IRQ_PATCH_3; + pIrqPatch[11] = _IRQ_PATCH_4; +} + +PATCH_FUN_SPEC void applyIeeeCoexPatch(void) +{ +#ifdef _IEEE_COEX_NO_PROG_STATE_VAR + enterIeeeCoexSysPatch(); + enterIeeeCoexCpePatch(); +#else + if (!bIeeeCoexPatchEntered) + { + enterIeeeCoexSysPatch(); + enterIeeeCoexCpePatch(); + bIeeeCoexPatchEntered = 1; + } +#endif + enterIeeeCoexCpeHdPatch(); + configureIeeeCoexPatch(); +} + +void refreshIeeeCoexPatch(void) +{ + enterIeeeCoexCpeHdPatch(); + configureIeeeCoexPatch(); +} + +void cleanIeeeCoexPatch(void) +{ +#ifndef _IEEE_COEX_NO_PROG_STATE_VAR + bIeeeCoexPatchEntered = 0; +#endif +} + +void rf_patch_cpe_ieee_coex(void) +{ + applyIeeeCoexPatch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 +#undef _IRQ_PATCH_2 +#undef _IRQ_PATCH_3 +#undef _IRQ_PATCH_4 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.h new file mode 100644 index 00000000..887914fe --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_ieee_coex.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_ieee_coex.h +* +* Description: RF core patch for IEEE 802.15.4-Coex support ("IEEE" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_IEEE_COEX_H +#define _RF_PATCH_CPE_IEEE_COEX_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanIeeeCoexPatch(void); +extern void refreshIeeeCoexPatch(void); +extern void rf_patch_cpe_ieee_coex(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_IEEE_COEX_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.c new file mode 100644 index 00000000..4abd3c61 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.c @@ -0,0 +1,1734 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_bt5_coex.c +* +* Description: RF core patch for coexistence support for Bluetooth 5 ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_multi_bt5_coex.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiBt5Coex[] = { + 0x210044b5, + 0x210040a9, + 0x210040c5, + 0x2100412f, + 0x210040f1, + 0x21004529, + 0x21004565, + 0x21004161, + 0x2100416d, + 0x21004179, + 0x21004195, + 0x2100460f, + 0x210041dd, + 0x210041f5, + 0x210047c7, + 0x21004869, + 0x21004aff, + 0x2100508f, + 0x21005421, + 0x21004b4d, + 0x21004219, + 0x210055db, + 0x2100564b, + 0xd00507db, + 0xf803f000, + 0x70084902, + 0xb570bd70, + 0x47284d01, + 0x210004e0, + 0x0002241d, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x4910d107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490d2002, + 0x210c780a, + 0xd0024211, + 0x2280490b, + 0xb003600a, + 0xb5f0bdf0, + 0x4909b083, + 0x20004708, + 0x47884908, + 0x78014804, + 0x43912240, + 0x48067001, + 0x00004700, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x000063f7, + 0x00031b23, + 0x4700b570, + 0xfa28f000, + 0x47004800, + 0x00007f57, + 0xfa28f000, + 0x47004800, + 0x0000881b, + 0x0a889905, + 0xd1052880, + 0x78884913, + 0x0f800780, + 0xfa32f000, + 0x47004800, + 0x00006ed9, + 0x480fb40f, + 0x290088c1, + 0x4610d002, + 0xfa26f000, + 0x0a9b9b07, + 0x2b834d08, + 0x4c08d108, + 0x069b8923, + 0xf000d504, + 0x2800f805, + 0x3542d000, + 0x4728bc0f, + 0x4804b570, + 0x00004700, + 0x00020b1f, + 0x21000160, + 0x21000380, + 0x000209eb, + 0x781a4b09, + 0x43a22408, + 0xd0002800, + 0x701a4322, + 0x47104a00, + 0x00008e83, + 0x78084903, + 0xd4010700, + 0x47004802, + 0x00004770, + 0x21000380, + 0x00007e5f, + 0xb081b5f3, + 0xb5f84710, + 0x00004700, + 0x20284a04, + 0x48044790, + 0x60412101, + 0x4a044803, + 0x47106041, + 0x0000424f, + 0x40045000, + 0x40046000, + 0x00004285, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x4c86b510, + 0x31404621, + 0x28017d08, + 0x4884d134, + 0x08407dc0, + 0xd02f07c0, + 0x30604620, + 0x08527942, + 0xd02907d2, + 0x0b808940, + 0xd1252801, + 0x09417e08, + 0xd00c07c9, + 0x07006fa1, + 0x0fc08809, + 0x04090240, + 0x66604308, + 0x1c806fa0, + 0xf9d8f001, + 0x4874e013, + 0x69803020, + 0x28006840, + 0x4a72d00e, + 0x78012300, + 0x1a5956d3, + 0x00c9d408, + 0x78411808, + 0xd00307c9, + 0x66616801, + 0x66a06840, + 0x4780486b, + 0xb5f8bd10, + 0x496a4c66, + 0x36204626, + 0x46257b70, + 0x90003540, + 0x00b8792f, + 0x68801840, + 0x28004780, + 0x4960d128, + 0x09097dc9, + 0xd02307c9, + 0x32644622, + 0xd0202f15, + 0x23007e29, + 0x07ff094f, + 0x7d6dd003, + 0xd0002d00, + 0x9f002301, + 0x43bb6fa5, + 0x7b73d012, + 0xd00f2b00, + 0x065b7d23, + 0x88d2d50c, + 0x2a010b92, + 0x08c9d108, + 0xd00507c9, + 0x0b8988a9, + 0xd1012901, + 0x73712100, + 0x7eabbdf8, + 0x2b017de9, + 0x2300d0e3, + 0xb570e7e1, + 0x46254c46, + 0x35806a60, + 0xd11d2800, + 0x5d002054, + 0x28002200, + 0x2064d017, + 0x08805d00, + 0xd01207c0, + 0x888868a9, + 0x28010b80, + 0x483dd10d, + 0x08407dc0, + 0xd00807c0, + 0x3020483a, + 0x68006980, + 0xd0022800, + 0x60a86229, + 0x622ae000, + 0x47804839, + 0x29006a61, + 0x6a29d103, + 0xd0002900, + 0xbd7060a9, + 0x4c2fb5f8, + 0x46204934, + 0x7d023040, + 0xd02f2a00, + 0x46257e80, + 0x28033580, + 0x2804d002, + 0xe027d003, + 0x75e82001, + 0x2064e024, + 0x08805d00, + 0xd01f07c0, + 0x888068a8, + 0x28010b80, + 0x4822d11a, + 0x7dc07dea, + 0xd0132a00, + 0x07c008c0, + 0x4626d012, + 0x7b773620, + 0x46014788, + 0xd1084339, + 0x06097d21, + 0x8869d505, + 0x29010b89, + 0x2100d101, + 0xbdf87371, + 0xe7ea0880, + 0xbdf84788, + 0x30804812, + 0x75c12100, + 0x47004817, + 0x3140490f, + 0x28267108, + 0xdc06d014, + 0xd0132815, + 0xd00b281b, + 0xd104281f, + 0x283de00a, + 0x2847d00e, + 0x490bd00a, + 0x18400080, + 0x47706880, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x21000160, + 0x210000c8, + 0x210004e0, + 0x00024959, + 0x00025500, + 0x00023d8f, + 0x00023075, + 0x00022a15, + 0x210044a9, + 0x21004435, + 0x210043d7, + 0x21004357, + 0x210042d9, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x4810b510, + 0x481088c1, + 0xd0182905, + 0x68214c0f, + 0x0052084a, + 0x6ba26022, + 0x00520852, + 0x602163a2, + 0xfdeaf7ff, + 0x07006ba0, + 0x2001d408, + 0x60606020, + 0x1c402000, + 0xdbfc280c, + 0x62202014, + 0xf7ffbd10, + 0xbd10fddb, + 0x21000380, + 0x00005b3f, + 0x40046000, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x79c94908, + 0x07d208ca, + 0x40c1d008, + 0x07c94806, + 0x4906d001, + 0x4906e000, + 0x60c11c49, + 0x20004770, + 0x00004770, + 0x210000e8, + 0x21000028, + 0x00000188, + 0x00000150, + 0x22ff0783, + 0x409a0edb, + 0x0e090789, + 0x28004099, + 0x0700da0b, + 0x38080f00, + 0x009b0883, + 0x181848ff, + 0x439369c3, + 0x61c3430b, + 0x08834770, + 0x009b48fc, + 0x68031818, + 0x430b4393, + 0x47706003, + 0x4694b5f0, + 0x7bd24af8, + 0xd0702a00, + 0x69234cf7, + 0xd06c2b00, + 0x07ea781d, + 0xd0680fd2, + 0xd07f2b00, + 0x2704785e, + 0xd0072e00, + 0x2e012205, + 0x2e02d006, + 0x2e03d006, + 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0x4780d100, + 0xf7ffbd10, + 0xbd10ffe2, + 0x4b222100, + 0x46084a20, + 0x20014718, + 0x02404920, + 0x48206008, + 0x780122fb, + 0x70014011, + 0x300c4813, + 0xb5104700, + 0x4788491c, + 0x39204915, + 0xd0072801, + 0xd5040402, + 0x85082000, + 0x62484818, + 0xbd102001, + 0x4b0a6a4a, + 0x429a330c, + 0x4a15d101, + 0x490be005, + 0x4b146a4a, + 0xd1f2429a, + 0x624a4a13, + 0x0000bd10, + 0x21000160, + 0x0002a675, + 0x40041100, + 0x000291a9, + 0x210055bd, + 0x00000806, + 0x0000069f, + 0x21000108, + 0x21000154, + 0x00029263, + 0x210055f5, + 0x0002b4b5, + 0xe000e180, + 0x21000380, + 0x000296f7, + 0x210055eb, + 0x21005633, + 0x00029569, + 0x21005629, + 0x07810882, + 0x0ec90092, + 0x78c0ca0c, + 0x424940ca, + 0x408b3120, + 0x0211431a, + 0x06000a09, + 0x47704308, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x00004e75, + 0x4801b403, + 0xbd019001, + 0x00004e4f, + 0x4801b403, + 0xbd019001, + 0x000085bd, + 0x4801b403, + 0xbd019001, + 0x0000900f, + 0x4801b403, + 0xbd019001, + 0x00003f9d, + 0x4801b403, + 0xbd019001, + 0x000002f9, + 0x4801b403, + 0xbd019001, + 0x0000424f, + 0x4801b403, + 0xbd019001, + 0x000004bf, + 0x4801b403, + 0xbd019001, + 0x0000423d, + 0x4801b403, + 0xbd019001, + 0x00003ca9, + 0x4801b403, + 0xbd019001, + 0x00007d65, + 0x4801b403, + 0xbd019001, + 0x00005d1b, + 0x4801b403, + 0xbd019001, + 0x000035f1, + 0x4801b403, + 0xbd019001, + 0x00005e9d, + 0x4801b403, + 0xbd019001, + 0x00000fc1, + 0x4801b403, + 0xbd019001, + 0x0002035d, + 0x4801b403, + 0xbd019001, + 0x000090fd, + 0x4801b403, + 0xbd019001, + 0x00005bbb, + 0x4801b403, + 0xbd019001, + 0x00003c8f, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x00000000, + 0x04050001, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_MULTI_BT5_COEX 1523 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_BT5_COEX 1 + +#define _NWORD_PATCHSYS_MULTI_BT5_COEX 0 + +#define _IRQ_PATCH_0 0x2100423d +#define _IRQ_PATCH_1 0x210048c3 +#define _IRQ_PATCH_2 0x2100499b + + +#ifndef _MULTI_BT5_COEX_SYSRAM_START +#define _MULTI_BT5_COEX_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_BT5_COEX_CPERAM_START +#define _MULTI_BT5_COEX_CPERAM_START 0x21000000 +#endif + +#define _MULTI_BT5_COEX_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_BT5_COEX_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_BT5_COEX_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_BT5_COEX_IRQPATCH_OFFSET 0x0480 +#define _MULTI_BT5_COEX_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_BT5_COEX_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_BT5_COEX_NO_PROG_STATE_VAR +static uint8_t bMultiBt5CoexPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiBt5CoexCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_BT5_COEX > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_BT5_COEX_CPERAM_START + _MULTI_BT5_COEX_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiBt5Coex, sizeof(patchImageMultiBt5Coex)); +#endif +} + +PATCH_FUN_SPEC void enterMultiBt5CoexCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_BT5_COEX > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_BT5_COEX_CPERAM_START + _MULTI_BT5_COEX_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiBt5CoexSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiBt5CoexPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_BT5_COEX_CPERAM_START + _MULTI_BT5_COEX_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_MULTI_BT5_COEX_CPERAM_START + _MULTI_BT5_COEX_IRQPATCH_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[21] = 1; + pPatchTab[76] = 2; + pPatchTab[62] = 3; + pPatchTab[64] = 4; + pPatchTab[91] = 5; + pPatchTab[79] = 6; + pPatchTab[140] = 7; + pPatchTab[150] = 8; + pPatchTab[107] = 9; + pPatchTab[13] = 10; + pPatchTab[31] = 11; + pPatchTab[152] = 12; + pPatchTab[151] = 13; + pPatchTab[12] = 14; + pPatchTab[139] = 15; + pPatchTab[78] = 16; + pPatchTab[163] = 17; + pPatchTab[81] = 18; + pPatchTab[40] = 19; + pPatchTab[73] = 20; + pPatchTab[7] = 21; + pPatchTab[164] = 22; + + pIrqPatch[1] = _IRQ_PATCH_0; + pIrqPatch[17] = _IRQ_PATCH_1; + pIrqPatch[21] = _IRQ_PATCH_2; +} + +PATCH_FUN_SPEC void applyMultiBt5CoexPatch(void) +{ +#ifdef _MULTI_BT5_COEX_NO_PROG_STATE_VAR + enterMultiBt5CoexSysPatch(); + enterMultiBt5CoexCpePatch(); +#else + if (!bMultiBt5CoexPatchEntered) + { + enterMultiBt5CoexSysPatch(); + enterMultiBt5CoexCpePatch(); + bMultiBt5CoexPatchEntered = 1; + } +#endif + enterMultiBt5CoexCpeHdPatch(); + configureMultiBt5CoexPatch(); +} + +void refreshMultiBt5CoexPatch(void) +{ + enterMultiBt5CoexCpeHdPatch(); + configureMultiBt5CoexPatch(); +} + +void cleanMultiBt5CoexPatch(void) +{ +#ifndef _MULTI_BT5_COEX_NO_PROG_STATE_VAR + bMultiBt5CoexPatchEntered = 0; +#endif +} + +void rf_patch_cpe_multi_bt5_coex(void) +{ + applyMultiBt5CoexPatch(); +} + +#undef _IRQ_PATCH_0 +#undef _IRQ_PATCH_1 +#undef _IRQ_PATCH_2 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.h new file mode 100644 index 00000000..3de8fee1 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_bt5_coex.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_bt5_coex.h +* +* Description: RF core patch for coexistence support for Bluetooth 5 ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_BT5_COEX_H +#define _RF_PATCH_CPE_MULTI_BT5_COEX_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanMultiBt5CoexPatch(void); +extern void refreshMultiBt5CoexPatch(void); +extern void rf_patch_cpe_multi_bt5_coex(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_BT5_COEX_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.c new file mode 100644 index 00000000..4f74e4e9 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.c @@ -0,0 +1,717 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol.c +* +* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_multi_protocol.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocol[] = { + 0x210044e1, + 0x21004099, + 0x210040b5, + 0x2100411f, + 0x210040e1, + 0x21004555, + 0x21004591, + 0x21004151, + 0x2100415d, + 0x21004169, + 0x21004185, + 0x2100463b, + 0x210041cd, + 0x210041e5, + 0x210041fd, + 0x21004239, + 0x2100466f, + 0x210046df, + 0x210047eb, + 0xd00507db, + 0xf803f000, + 0x70084902, + 0xb570bd70, + 0x47284d01, + 0x210004e0, + 0x0002241d, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x4910d107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490d2002, + 0x210c780a, + 0xd0024211, + 0x2280490b, + 0xb003600a, + 0xb5f0bdf0, + 0x4909b083, + 0x20004708, + 0x47884908, + 0x78014804, + 0x43912240, + 0x48067001, + 0x00004700, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x000063f7, + 0x00031b23, + 0x4700b570, + 0xfa46f000, + 0x47004800, + 0x00007f57, + 0xfa46f000, + 0x47004800, + 0x0000881b, + 0x0a889905, + 0xd1052880, + 0x78884913, + 0x0f800780, + 0xfa50f000, + 0x47004800, + 0x00006ed9, + 0x480fb40f, + 0x290088c1, + 0x4610d002, + 0xfa44f000, + 0x0a9b9b07, + 0x2b834d08, + 0x4c08d108, + 0x069b8923, + 0xf000d504, + 0x2800f805, + 0x3542d000, + 0x4728bc0f, + 0x4804b570, + 0x00004700, + 0x00020b1f, + 0x21000160, + 0x21000380, + 0x000209eb, + 0x781a4b09, + 0x43a22408, + 0xd0002800, + 0x701a4322, + 0x47104a00, + 0x00008e83, + 0x78084903, + 0xd4010700, + 0x47004802, + 0x00004770, + 0x21000380, + 0x00007e5f, + 0x4a094808, + 0x429a6803, + 0x4808d10a, + 0x4b088902, + 0xd0011ad2, + 0xd1032a01, + 0x49066e40, + 0x99034788, + 0x47184b05, + 0x210002a8, + 0x000203bd, + 0x21000160, + 0x00001821, + 0x000035f1, + 0x000006bd, + 0x20284a04, + 0x48044790, + 0x60412101, + 0x4a044803, + 0x47106041, + 0x0000424f, + 0x40045000, + 0x40046000, + 0x00004285, + 0x4901b5f8, + 0x00004708, + 0x0000640d, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x4c86b510, + 0x31404621, + 0x28017d08, + 0x4884d134, + 0x08407dc0, + 0xd02f07c0, + 0x30604620, + 0x08527942, + 0xd02907d2, + 0x0b808940, + 0xd1252801, + 0x09417e08, + 0xd00c07c9, + 0x07006fa1, + 0x0fc08809, + 0x04090240, + 0x66604308, + 0x1c806fa0, + 0xfa76f000, + 0x4874e013, + 0x69803020, + 0x28006840, + 0x4a72d00e, + 0x78012300, + 0x1a5956d3, + 0x00c9d408, + 0x78411808, + 0xd00307c9, + 0x66616801, + 0x66a06840, + 0x4780486b, + 0xb5f8bd10, + 0x496a4c66, + 0x36204626, + 0x46257b70, + 0x90003540, + 0x00b8792f, + 0x68801840, + 0x28004780, + 0x4960d128, + 0x09097dc9, + 0xd02307c9, + 0x32644622, + 0xd0202f15, + 0x23007e29, + 0x07ff094f, + 0x7d6dd003, + 0xd0002d00, + 0x9f002301, + 0x43bb6fa5, + 0x7b73d012, + 0xd00f2b00, + 0x065b7d23, + 0x88d2d50c, + 0x2a010b92, + 0x08c9d108, + 0xd00507c9, + 0x0b8988a9, + 0xd1012901, + 0x73712100, + 0x7eabbdf8, + 0x2b017de9, + 0x2300d0e3, + 0xb570e7e1, + 0x46254c46, + 0x35806a60, + 0xd11d2800, + 0x5d002054, + 0x28002200, + 0x2064d017, + 0x08805d00, + 0xd01207c0, + 0x888868a9, + 0x28010b80, + 0x483dd10d, + 0x08407dc0, + 0xd00807c0, + 0x3020483a, + 0x68006980, + 0xd0022800, + 0x60a86229, + 0x622ae000, + 0x47804839, + 0x29006a61, + 0x6a29d103, + 0xd0002900, + 0xbd7060a9, + 0x4c2fb5f8, + 0x46204934, + 0x7d023040, + 0xd02f2a00, + 0x46257e80, + 0x28033580, + 0x2804d002, + 0xe027d003, + 0x75e82001, + 0x2064e024, + 0x08805d00, + 0xd01f07c0, + 0x888068a8, + 0x28010b80, + 0x4822d11a, + 0x7dc07dea, + 0xd0132a00, + 0x07c008c0, + 0x4626d012, + 0x7b773620, + 0x46014788, + 0xd1084339, + 0x06097d21, + 0x8869d505, + 0x29010b89, + 0x2100d101, + 0xbdf87371, + 0xe7ea0880, + 0xbdf84788, + 0x30804812, + 0x75c12100, + 0x47004817, + 0x3140490f, + 0x28267108, + 0xdc06d014, + 0xd0132815, + 0xd00b281b, + 0xd104281f, + 0x283de00a, + 0x2847d00e, + 0x490bd00a, + 0x18400080, + 0x47706880, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x4770480c, + 0x21000160, + 0x210000c8, + 0x210004e0, + 0x00024959, + 0x00025500, + 0x00023d8f, + 0x00023075, + 0x00022a15, + 0x210044d5, + 0x21004461, + 0x21004403, + 0x21004383, + 0x21004305, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x4810b510, + 0x481088c1, + 0xd0182905, + 0x68214c0f, + 0x0052084a, + 0x6ba26022, + 0x00520852, + 0x602163a2, + 0xfdccf7ff, + 0x07006ba0, + 0x2001d408, + 0x60606020, + 0x1c402000, + 0xdbfc280c, + 0x62202014, + 0xf7ffbd10, + 0xbd10fdbd, + 0x21000380, + 0x00005b3f, + 0x40046000, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x79c94908, + 0x07d208ca, + 0x40c1d008, + 0x07c94806, + 0x4906d001, + 0x4906e000, + 0x60c11c49, + 0x20004770, + 0x00004770, + 0x210000e8, + 0x21000028, + 0x00000188, + 0x00000150, + 0x4833b510, + 0x47804c31, + 0xd0072801, + 0x7d213420, + 0xd1032900, + 0x4a2f2101, + 0x60910509, + 0x2807bd10, + 0x4a2dd001, + 0x4a2d4710, + 0x72c8604a, + 0x22014770, + 0x21024b2c, + 0x4718482a, + 0xb5104827, + 0x478030f8, + 0x6a404829, + 0xd10d2800, + 0x200a4928, + 0x28005608, + 0x1c40da09, + 0x4608d007, + 0x6a403820, + 0x42884924, + 0x4780d100, + 0xf7ffbd10, + 0xbd10ffe2, + 0x4b222100, + 0x46084a20, + 0x20014718, + 0x02404920, + 0x48206008, + 0x780122fb, + 0x70014011, + 0x300c4813, + 0xb5104700, + 0x4788491c, + 0x39204915, + 0xd0072801, + 0xd5040402, + 0x85082000, + 0x62484818, + 0xbd102001, + 0x4b0a6a4a, + 0x429a330c, + 0x4a15d101, + 0x490be005, + 0x4b146a4a, + 0xd1f2429a, + 0x624a4a13, + 0x0000bd10, + 0x21000160, + 0x0002a675, + 0x40041100, + 0x000291a9, + 0x21004651, + 0x00000806, + 0x0000069f, + 0x21000108, + 0x21000154, + 0x00029263, + 0x21004689, + 0x0002b4b5, + 0xe000e180, + 0x21000380, + 0x000296f7, + 0x2100467f, + 0x210046c7, + 0x00029569, + 0x210046bd, + 0x4601b510, + 0x482c4b2b, + 0xbf20e000, + 0x07926942, + 0x4829d1fb, + 0x30407ada, + 0x2a0b6800, + 0xf000d101, + 0xbd10f843, + 0x1a522220, + 0x4a244090, + 0x6993ba00, + 0x48214043, + 0xbf20e000, + 0x07926942, + 0x0088d4fb, + 0x1840491f, + 0x481c63c3, + 0x60033040, + 0xb5104770, + 0xe0004819, + 0x6942bf20, + 0xd4fb0792, + 0x4b176b42, + 0x40506998, + 0x07d48a5a, + 0x2401d001, + 0x08524060, + 0x2220825a, + 0x40881a51, + 0xba00490f, + 0x60083140, + 0xb510bd10, + 0xf7ff4604, + 0x490cfd35, + 0x09897c09, + 0xd00807c8, + 0x07e1480b, + 0x490bd001, + 0x490be000, + 0x490b6201, + 0xbd106241, + 0x1a512220, + 0xba004088, + 0x00004770, + 0x21000160, + 0x40042000, + 0x21000028, + 0x400421c0, + 0x21000380, + 0x210047b7, + 0x2100478d, + 0x21004769, + 0x07810882, + 0x0ec90092, + 0x78c0ca0c, + 0x424940ca, + 0x408b3120, + 0x0211431a, + 0x06000a09, + 0x47704308, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 516 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL 1 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL 0 + +#define _IRQ_PATCH_0 0x21004269 + + +#ifndef _MULTI_PROTOCOL_SYSRAM_START +#define _MULTI_PROTOCOL_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_CPERAM_START +#define _MULTI_PROTOCOL_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocol, sizeof(patchImageMultiProtocol)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_IRQPATCH_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[21] = 1; + pPatchTab[76] = 2; + pPatchTab[62] = 3; + pPatchTab[64] = 4; + pPatchTab[91] = 5; + pPatchTab[79] = 6; + pPatchTab[140] = 7; + pPatchTab[150] = 8; + pPatchTab[107] = 9; + pPatchTab[13] = 10; + pPatchTab[31] = 11; + pPatchTab[152] = 12; + pPatchTab[151] = 13; + pPatchTab[40] = 14; + pPatchTab[73] = 15; + pPatchTab[7] = 16; + pPatchTab[164] = 17; + pPatchTab[85] = 18; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyMultiProtocolPatch(void) +{ +#ifdef _MULTI_PROTOCOL_NO_PROG_STATE_VAR + enterMultiProtocolSysPatch(); + enterMultiProtocolCpePatch(); +#else + if (!bMultiProtocolPatchEntered) + { + enterMultiProtocolSysPatch(); + enterMultiProtocolCpePatch(); + bMultiProtocolPatchEntered = 1; + } +#endif + enterMultiProtocolCpeHdPatch(); + configureMultiProtocolPatch(); +} + +void refreshMultiProtocolPatch(void) +{ + enterMultiProtocolCpeHdPatch(); + configureMultiProtocolPatch(); +} + +void cleanMultiProtocolPatch(void) +{ +#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR + bMultiProtocolPatchEntered = 0; +#endif +} + +void rf_patch_cpe_multi_protocol(void) +{ + applyMultiProtocolPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.h new file mode 100644 index 00000000..c3779f67 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol.h +* +* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanMultiProtocolPatch(void); +extern void refreshMultiProtocolPatch(void); +extern void rf_patch_cpe_multi_protocol(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.c new file mode 100644 index 00000000..f34cb9ce --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.c @@ -0,0 +1,2039 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_hid.c +* +* Description: RF core patch for multi-protocol support (all available API command sets) with HID components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_multi_protocol_hid.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocolHid[] = { + 0x210044cd, + 0x21004099, + 0x210040b5, + 0x2100411f, + 0x210040e1, + 0x21004541, + 0x2100457d, + 0x21004145, + 0x21004151, + 0x2100415d, + 0x21004179, + 0x21004627, + 0x210041c5, + 0x210041dd, + 0x210041f5, + 0x21004231, + 0x2100469b, + 0x21005adb, + 0x21004b07, + 0xd00507db, + 0xf803f000, + 0x70084902, + 0xb570bd70, + 0x47284d01, + 0x210004e0, + 0x0002241d, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x4700b570, + 0xfa42f000, + 0x47004800, + 0x00007f57, + 0xfa42f000, + 0x47004800, + 0x0000881b, + 0x0a889905, + 0xd1052880, + 0x78884913, + 0x0f800780, + 0xfa4cf000, + 0x47004800, + 0x00006ed9, + 0x4810b40f, + 0x290088c1, + 0x4610d002, + 0xfa40f000, + 0x0a9b9b07, + 0x2b834d08, + 0x4c08d108, + 0x069b8923, + 0xf000d504, + 0x2800f805, + 0x3542d000, + 0x4728bc0f, + 0x4805b570, + 0x00004700, + 0x00020b1f, + 0x21000160, + 0x00020b1f, + 0x21000380, + 0x000209eb, + 0x781a4b09, + 0x43a22408, + 0xd0002800, + 0x701a4322, + 0x47104a00, + 0x00008e83, + 0x78084903, + 0xd4010700, + 0x47004802, + 0x00004770, + 0x21000380, + 0x00007e5f, + 0x4a094808, + 0x429a6803, + 0x4808d10a, + 0x4b088902, + 0xd0011ad2, + 0xd1032a01, + 0x49066e40, + 0x99034788, + 0x47184b05, + 0x210002a8, + 0x000203bd, + 0x21000160, + 0x00001821, + 0x000035f1, + 0x000006bd, + 0x20284a04, + 0x48044790, + 0x60412101, + 0x4a044803, + 0x47106041, + 0x0000424f, + 0x40045000, + 0x40046000, + 0x00004285, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x4c86b510, + 0x31404621, + 0x28017d08, + 0x4884d134, + 0x08407dc0, + 0xd02f07c0, + 0x30604620, + 0x08527942, + 0xd02907d2, + 0x0b808940, + 0xd1252801, + 0x09417e08, + 0xd00c07c9, + 0x07006fa1, + 0x0fc08809, + 0x04090240, + 0x66604308, + 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0x7e28d1cb, + 0x07c00940, + 0x496ad0c4, + 0x31866b60, + 0x28004788, + 0x208bd1be, + 0xfccef000, + 0x20dfe7ba, + 0x76294001, + 0x61e7702f, + 0x26ef7b20, + 0x0fcd06c1, + 0x73204030, + 0x98024963, + 0x7b204788, + 0x40300129, + 0x73204308, + 0x68212011, + 0xf7ffe040, + 0x6ca1fbfe, + 0x70c87e28, + 0x8b686ca1, + 0x7af08108, + 0xd0062800, + 0x38984852, + 0x20028120, + 0x207e72a0, + 0x9801e039, + 0x7b202800, + 0x0880d007, + 0xd10707c0, + 0x81204852, + 0x209272a7, + 0x0840e02d, + 0xd02407c0, + 0xfbf5f000, + 0x38724841, + 0x484d4780, + 0x22fb7ac1, + 0x72c14011, + 0x68003820, + 0x7ec12204, + 0x230069c0, + 0x46029200, + 0x46189301, + 0xfc98f000, + 0xd0022800, + 0xf000208f, + 0x2083fc7b, + 0xfc78f000, + 0x200c6821, + 0x60604788, + 0xb0052000, + 0x2015bdf0, + 0x81200280, + 0x72a02001, + 0xf0002091, + 0x2003fc69, + 0xb5f8e7f3, + 0x4c264828, + 0x6ac03840, + 0xd04407c0, + 0xfd01f7ff, + 0x20104e34, + 0x6ba060b0, + 0xd0022800, + 0x1c497801, + 0x7b207001, + 0x08404f1c, + 0x250007c0, + 0xd01c2800, + 0x28007ba0, + 0x7d60d003, + 0x07c00880, + 0xf7ffd015, + 0x707dfcf2, + 0x20056821, + 0x60604788, + 0x5d002040, + 0x00c07ce1, + 0x48141809, + 0x8cc08dc2, + 0x6e224351, + 0x18100909, + 0x63e01808, + 0x4917e056, + 0x31866b60, + 0x28004788, + 0x2090d102, + 0xfc28f000, + 0x02802001, + 0x7b6060b0, + 0x1c404916, + 0x0f800780, + 0x39207360, + 0x75486809, + 0xe041e028, + 0x21005cf0, + 0x21000160, + 0x0002de75, + 0x40045080, + 0x21000028, + 0x00005b9b, + 0x000075f7, + 0x00008303, + 0x21000380, + 0x40046000, + 0x00005899, + 0x000064c9, + 0x0000359d, + 0xe000e280, + 0xe000e100, + 0x00003b77, + 0x0002d137, + 0x00005403, + 0x21000128, + 0x40041100, + 0xfa7bf7ff, + 0x707d48ff, + 0x07c07ac0, + 0x48fed007, + 0x72a58120, + 0xf000209e, + 0x2002fbe5, + 0x7c20bdf8, + 0x74201c40, + 0x478048f9, + 0x20016821, + 0x60604788, + 0xbdf82000, + 0x780148f6, + 0x00490849, + 0x49f57001, + 0x60082004, + 0xbdf82001, + 0x49f4b57c, + 0x20004cf2, + 0xf7ff4788, + 0xf000fad9, + 0xf7fffb26, + 0x48f0fa93, + 0x78804af0, + 0x47906d21, + 0x7ac148e6, + 0x401122fb, + 0x230072c1, + 0x48ea2204, + 0x92009301, + 0x8a4030a0, + 0x4de96be1, + 0x2182180a, + 0x47a84618, + 0x478048e7, + 0x20066821, + 0x60604788, + 0xbd7c2000, + 0x2098b570, + 0xfba0f000, + 0xfa22f7ff, + 0x20004605, + 0xe0004ce0, + 0x6821bf20, + 0xd0fb2900, + 0x4ade6821, + 0x42910c09, + 0x2101d104, + 0x4adc6061, + 0xe0046011, + 0x385e48d6, + 0x20004780, + 0x49d943c0, + 0x2100610d, + 0xbd706021, + 0x48c8b5f8, + 0x38204ccc, + 0x4ad56800, + 0x70512100, + 0x636069c0, + 0xf000208a, + 0x4ed2fb75, + 0x47b06b60, + 0xd0190005, + 0xf0002093, + 0x4ecffb6d, + 0x68706e21, + 0xfb86f000, + 0xd0012800, + 0x66206870, + 0x462849cb, + 0x61a04788, + 0x344088e8, + 0x48c97020, + 0x49c94780, + 0x47884604, + 0xbdf84620, + 0xf000207d, + 0xf7fffb53, + 0x2702ffad, + 0xd0052800, + 0xf0002082, + 0x48aefb4b, + 0xe0081c40, + 0x47b06b60, + 0xd1d60005, + 0xf000209c, + 0x200bfb41, + 0x812002c0, + 0x200372a7, + 0xb510bdf8, + 0x7b204ca9, + 0x07c00880, + 0x2000d001, + 0xf7ff43c0, + 0x2800f90c, + 0x6821db06, + 0x47882009, + 0x20006060, + 0xe01849b1, + 0xd0081c81, + 0xd01c1cc0, + 0x201049a6, + 0x499c6008, + 0x20016008, + 0x4898e4ce, + 0x28004780, + 0x6821d00c, + 0x47882001, + 0x209f6060, + 0xfb12f000, + 0x6b6049a0, + 0x47883154, + 0xe4bd2000, + 0x1ec0488e, + 0x20008120, + 0x200be003, + 0x812002c0, + 0x72a02002, + 0xe4b12003, + 0x4889b570, + 0x478030bc, + 0x46054c8a, + 0x20016821, + 0x68614788, + 0xd1064288, + 0xf000209a, + 0x4990faf1, + 0x31546b60, + 0x46284788, + 0xb5f8bd70, + 0x4c814d8b, + 0x28007828, + 0x2001d10e, + 0xf87af7ff, + 0x42082121, + 0x200bd006, + 0x812002c0, + 0x72a02002, + 0xbdf82003, + 0x70282001, + 0x35204625, + 0x7aee4887, + 0x90004780, + 0x682172ee, + 0x4788200e, + 0x42886861, + 0x4622d13f, + 0x32407ba8, + 0x78976c61, + 0x2800468c, + 0x2302d001, + 0x2301e000, + 0xe0042000, + 0x421e780e, + 0x310cd105, + 0x42b81c40, + 0x2000dbf8, + 0x280043c0, + 0x6ba0da18, + 0xd0022800, + 0x1c497941, + 0x20017141, + 0x06804967, + 0xf0006088, + 0x4871fa06, + 0x20004780, + 0x20867328, + 0xfa9ef000, + 0x200c6821, + 0x60604788, + 0xbdf82000, + 0x230c7310, + 0x44604358, + 0x780164a0, + 0x78417651, + 0x78c17051, + 0x89017611, + 0x68408351, + 0x98006360, + 0xb5f8bdf8, + 0x4c4f4d59, + 0x28007828, + 0x2001d10e, + 0xf816f7ff, + 0x42082121, + 0x200bd006, + 0x812002c0, + 0x72a02002, + 0xbdf82003, + 0x70282001, + 0x37204627, + 0x7afe4841, + 0x47803054, + 0x483d4605, + 0x7ac072fe, + 0xd5020740, + 0xf000207f, + 0x2d00fa63, + 0x6821d10c, + 0x47882001, + 0x42886861, + 0x208cd106, + 0xfa58f000, + 0x6b604943, + 0x47883154, + 0xbdf84628, + 0x4830b5f0, + 0x38204c34, + 0xb0856800, + 0x20009001, + 0x69e69002, + 0x90034943, + 0x48316008, + 0x95007c45, + 0xd90d2d10, + 0x200f4a3f, + 0x63d03a40, + 0x68414608, + 0xd5fc0789, + 0x90026b50, + 0x3d102010, + 0x9003b2ed, + 0x30724837, + 0x46274780, + 0x7a393720, + 0x00c97ce0, + 0x48231841, + 0x8d008dc2, + 0x6be24351, + 0x18100909, + 0x4a311808, + 0x66202101, + 0x28004790, + 0x2084d006, + 0xfa18f000, + 0x482d4921, + 0xe7fe6048, + 0x20014917, + 0x2d004788, + 0x4a27d061, + 0x3a401e6d, + 0x482563d5, + 0x07896841, + 0x6b50d5fc, + 0x4d0d9903, + 0x99024088, + 0x43086a2a, + 0x47909900, + 0x98006a69, + 0x7a794788, + 0xd1042900, + 0x22209900, + 0x40881a51, + 0x7bf9ba00, + 0xe0350909, + 0x21000128, + 0x00005405, + 0x0002d53b, + 0x21000380, + 0xe000e100, + 0x21000160, + 0x00008303, + 0x21000028, + 0x00006491, + 0x00000e43, + 0x000078d9, + 0x40041100, + 0x00000412, + 0xe000e280, + 0xe000ed00, + 0x21005cf0, + 0x0000359d, + 0x40043000, + 0x00003b77, + 0x0002d1cb, + 0x00004be3, + 0x00000fc1, + 0x0002dc99, + 0x00005b29, + 0x40045080, + 0x000075f7, + 0x80000000, + 0xd00a07c9, + 0xd0082e00, + 0xe0032100, + 0x1c767030, + 0x31080a00, + 0x42919a00, + 0x2100dbf8, + 0xf7ff2001, + 0x49abfb30, + 0x62082013, + 0x49ab48aa, + 0x02007880, + 0x61881c80, + 0x478048a9, + 0x478048a9, + 0x460549a9, + 0x7af8600e, + 0x714d7108, + 0x71ca7a3a, + 0x718b2301, + 0x390c2600, + 0x6b21700e, + 0xd00d2900, + 0xd0032d00, + 0x08497bf9, + 0xd10407c9, + 0xd1052a00, + 0x07c97bf9, + 0x2800d002, + 0x2000d000, + 0x28009901, + 0x636169c9, + 0x2095d007, + 0xf976f000, + 0xf8bdf7ff, + 0x38984893, + 0x4895e03e, + 0x48954780, + 0x00287ac7, + 0xd03a4d94, + 0xf0002094, + 0x4993f967, + 0x47886b60, + 0xd00607f8, + 0xf8a9f7ff, + 0x81204890, + 0x208572a6, + 0x488fe049, + 0x28004780, + 0x4887d01d, + 0x7046380c, + 0xf0002008, + 0x9801f975, + 0x69002200, + 0x46206520, + 0x30504611, + 0xf972f000, + 0xf0002088, + 0x2102f945, + 0xf7fe2011, + 0x4883fe91, + 0x48836005, + 0x48816005, + 0x60053880, + 0x208de064, + 0xf936f000, + 0xf87df7ff, + 0x1e80487a, + 0x72a68120, + 0x4977e01f, + 0x31326b60, + 0x28004788, + 0x2089d102, + 0xf926f000, + 0x49772001, + 0x60880280, + 0x496e7b60, + 0x07801c40, + 0x73600f80, + 0x68093920, + 0x07f87548, + 0xf7ffd009, + 0x486bf85e, + 0x72a68120, + 0xf0002099, + 0x2003f90f, + 0x9801e499, + 0x69c04965, + 0x63603954, + 0x00064788, + 0x495bd02d, + 0x39402002, + 0x49666048, + 0x47884630, + 0x88f161a0, + 0x55112240, + 0x485561e0, + 0x63812107, + 0x20014955, + 0x478839d2, + 0x4a53485f, + 0x3a387880, + 0x47906d21, + 0x495d7b20, + 0x478809c0, + 0x20026821, + 0x60604788, + 0x20112102, + 0xfe30f7fe, + 0x60054852, + 0x60054852, + 0x38804850, + 0x20006005, + 0x209be463, + 0xf8d4f000, + 0xf81bf7ff, + 0x20016821, + 0x60604788, + 0xb500e7f3, + 0x4603494e, + 0xf00072c8, + 0x2314f8f7, + 0x19232315, + 0x13110d17, + 0x0f210b23, + 0x231b1f23, + 0x231d2323, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0xbd004847, + 0x00804947, + 0x6b001840, + 0x492abd00, + 0x2000b510, + 0x478839d2, + 0x20004925, + 0x60083140, + 0x47804841, + 0xd1021c40, + 0xf0002087, + 0xe56ff88f, + 0x4b2fb530, + 0xd0322800, + 0x28006800, + 0x7944d02f, + 0x28027900, + 0x202fd12b, + 0x08855cc0, + 0xd00407ed, + 0x091b7b1b, + 0xd00007db, + 0x08c31c52, + 0xd00007db, + 0x09031c92, + 0xd00407db, + 0x7c5b4b1f, + 0x08db1ddb, + 0x0943189a, + 0xd00007db, + 0x09831c52, + 0xd00007db, + 0x09c01c52, + 0x1d12d000, + 0x0f800720, + 0x2801d007, + 0x2802d006, + 0x1e89d103, + 0x1210700a, + 0xbd307048, + 0x700a1e49, + 0x0000bd30, + 0x40046000, + 0x21000380, + 0x40045040, + 0x00005899, + 0x000064c9, + 0x21005cfc, + 0x00000d1d, + 0x21000128, + 0x00020000, + 0x000035f1, + 0x00005405, + 0x0002d53b, + 0xe000e280, + 0xe000e100, + 0x40041100, + 0x00003b77, + 0x21000028, + 0x0002d137, + 0x21000160, + 0x210057d1, + 0x21005767, + 0x2100569f, + 0x21005675, + 0x210055ff, + 0x21005571, + 0x210054d9, + 0x210053a7, + 0x2100503d, + 0x21004e2f, + 0x210048f7, + 0x21004751, + 0x00032dc0, + 0x000078d9, + 0x07810882, + 0x0ec90092, + 0x78c0ca0c, + 0x424940ca, + 0x408b3120, + 0x0211431a, + 0x06000a09, + 0x47704308, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x00003b11, + 0x4801b403, + 0xbd019001, + 0x00005bbb, + 0x4801b403, + 0xbd019001, + 0x00003c8f, + 0x4801b403, + 0xbd019001, + 0x00000e43, + 0x4801b403, + 0xbd019001, + 0x000075d1, + 0x4801b403, + 0xbd019001, + 0x0000424f, + 0x4801b403, + 0xbd019001, + 0x00005ee7, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_HID 1838 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_HID 1 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL_HID 0 + +#define _IRQ_PATCH_0 0x21004255 + + +#ifndef _MULTI_PROTOCOL_HID_SYSRAM_START +#define _MULTI_PROTOCOL_HID_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_HID_CPERAM_START +#define _MULTI_PROTOCOL_HID_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_HID_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_HID_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_HID_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_HID_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_HID_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_HID_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_HID_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolHidPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolHidCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_HID > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_HID_CPERAM_START + _MULTI_PROTOCOL_HID_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocolHid, sizeof(patchImageMultiProtocolHid)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolHidCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_HID > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_HID_CPERAM_START + _MULTI_PROTOCOL_HID_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolHidSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolHidPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_HID_CPERAM_START + _MULTI_PROTOCOL_HID_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_MULTI_PROTOCOL_HID_CPERAM_START + _MULTI_PROTOCOL_HID_IRQPATCH_OFFSET); + + + pPatchTab[1] = 0; + pPatchTab[21] = 1; + pPatchTab[76] = 2; + pPatchTab[62] = 3; + pPatchTab[64] = 4; + pPatchTab[91] = 5; + pPatchTab[79] = 6; + pPatchTab[140] = 7; + pPatchTab[150] = 8; + pPatchTab[107] = 9; + pPatchTab[13] = 10; + pPatchTab[31] = 11; + pPatchTab[152] = 12; + pPatchTab[151] = 13; + pPatchTab[40] = 14; + pPatchTab[73] = 15; + pPatchTab[164] = 16; + pPatchTab[4] = 17; + pPatchTab[139] = 18; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyMultiProtocolHidPatch(void) +{ +#ifdef _MULTI_PROTOCOL_HID_NO_PROG_STATE_VAR + enterMultiProtocolHidSysPatch(); + enterMultiProtocolHidCpePatch(); +#else + if (!bMultiProtocolHidPatchEntered) + { + enterMultiProtocolHidSysPatch(); + enterMultiProtocolHidCpePatch(); + bMultiProtocolHidPatchEntered = 1; + } +#endif + enterMultiProtocolHidCpeHdPatch(); + configureMultiProtocolHidPatch(); +} + +void refreshMultiProtocolHidPatch(void) +{ + enterMultiProtocolHidCpeHdPatch(); + configureMultiProtocolHidPatch(); +} + +void cleanMultiProtocolHidPatch(void) +{ +#ifndef _MULTI_PROTOCOL_HID_NO_PROG_STATE_VAR + bMultiProtocolHidPatchEntered = 0; +#endif +} + +void rf_patch_cpe_multi_protocol_hid(void) +{ + applyMultiProtocolHidPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.h new file mode 100644 index 00000000..0403b33e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_hid.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_hid.h +* +* Description: RF core patch for multi-protocol support (all available API command sets) with HID components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_HID_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_HID_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanMultiProtocolHidPatch(void); +extern void refreshMultiProtocolHidPatch(void); +extern void rf_patch_cpe_multi_protocol_hid(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_HID_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.c new file mode 100644 index 00000000..5c158353 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.c @@ -0,0 +1,1753 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_rtls.c +* +* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_multi_protocol_rtls.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = { + 0x210040a9, + 0x21005145, + 0x210047ff, + 0x210040c5, + 0x21005205, + 0x210052ed, + 0x210055b5, + 0x210040fd, + 0x21004167, + 0x21004129, + 0x21005625, + 0x21005661, + 0x21004199, + 0x210041a5, + 0x210041b1, + 0x210041cd, + 0x2100570b, + 0x21004215, + 0x2100422d, + 0x21004245, + 0x2100573f, + 0x210057af, + 0x21004269, + 0xd00507db, + 0xf803f000, + 0x70084902, + 0xb570bd70, + 0x47284d01, + 0x210004e0, + 0x0002241d, + 0x68084908, + 0x43902221, + 0x48076008, + 0x68c34700, + 0x230260c3, + 0xd1fd1e5b, + 0x68c32210, + 0x60c34393, + 0x4770618a, + 0x40048000, + 0x00005c01, + 0x4801b430, + 0x00004700, + 0x00020efd, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x4910d107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490d2002, + 0x210c780a, + 0xd0024211, + 0x2280490b, + 0xb003600a, + 0xb5f0bdf0, + 0x4909b083, + 0x20004708, + 0x47884908, + 0x78014804, + 0x43912240, + 0x48067001, + 0x00004700, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x000063f7, + 0x00031b23, + 0x4700b570, + 0xfa8af001, + 0x47004800, + 0x00007f57, + 0xfa8af001, + 0x47004800, + 0x0000881b, + 0x0a889905, + 0xd1052880, + 0x78884913, + 0x0f800780, + 0xfa94f001, + 0x47004800, + 0x00006ed9, + 0x480fb40f, + 0x290088c1, + 0x4610d002, + 0xfa88f001, + 0x0a9b9b07, + 0x2b834d08, + 0x4c08d108, + 0x069b8923, + 0xf000d504, + 0x2800f805, + 0x3542d000, + 0x4728bc0f, + 0x4804b570, + 0x00004700, + 0x00020b1f, + 0x21000160, + 0x21000380, + 0x000209eb, + 0x781a4b09, + 0x43a22408, + 0xd0002800, + 0x701a4322, + 0x47104a00, + 0x00008e83, + 0x78084903, + 0xd4010700, + 0x47004802, + 0x00004770, + 0x21000380, + 0x00007e5f, + 0x20284a04, + 0x48044790, + 0x60412101, + 0x4a044803, + 0x47106041, + 0x0000424f, + 0x40045000, + 0x40046000, + 0x00004285, + 0x78184b0d, + 0xd0042800, + 0x4a0d480c, + 0xb0056002, + 0x480abdf0, + 0x68034a0b, + 0xd10a429a, + 0x8902480a, + 0x1ad24b0a, + 0x2a01d001, + 0x6e40d103, + 0x47884908, + 0x4b089903, + 0x00004718, + 0x21005874, + 0x210002a8, + 0x210055a7, + 0x000203bd, + 0x21000160, + 0x00001821, + 0x000035f1, + 0x000006bd, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x21004877, + 0x487775c1, + 0xb5704700, + 0x4d744c74, + 0x6a603c80, + 0xd11d2800, + 0x5d002054, + 0x28002200, + 0x2064d017, + 0x08805d00, + 0xd01207c0, + 0x888868a9, + 0x28010b80, + 0x486cd10d, + 0x08407dc0, + 0xd00807c0, + 0x30204869, + 0x68006980, + 0xd0022800, + 0x60a86229, + 0x622ae000, + 0x47804865, + 0x29006a61, + 0x6a29d103, + 0xd0002900, + 0xbd7060a9, + 0x4c5db5f8, + 0x3c804960, + 0x30404620, + 0x2a007d02, + 0x7e80d02e, + 0x28034d58, + 0x2804d002, + 0xe027d003, + 0x75e82001, + 0x2064e024, + 0x08805d00, + 0xd01f07c0, + 0x888068a8, + 0x28010b80, + 0x4851d11a, + 0x7dc07dea, + 0xd0132a00, + 0x07c008c0, + 0x4626d012, + 0x7b773620, + 0x46014788, + 0xd1084339, + 0x06097d21, + 0x8869d505, + 0x29010b89, + 0x2100d101, + 0xbdf87371, + 0xe7ea0880, + 0xbdf84788, + 0x4c40b5f8, + 0x3c804944, + 0x36204626, + 0x46257b70, + 0x90003540, + 0x00b8792f, + 0x68801840, + 0x28004780, + 0x493ad128, + 0x09097dc9, + 0xd02307c9, + 0x32644622, + 0xd0202f15, + 0x23007e29, + 0x07ff094f, + 0x7d6dd003, + 0xd0002d00, + 0x9f002301, + 0x43bb6fa5, + 0x7b73d012, + 0xd00f2b00, + 0x065b7d23, + 0x88d2d50c, + 0x2a010b92, + 0x08c9d108, + 0xd00507c9, + 0x0b8988a9, + 0xd1012901, + 0x73712100, + 0x7eabbdf8, + 0x2b017de9, + 0x2300d0e3, + 0xb510e7e1, + 0x3c804c1f, + 0x31404621, + 0x28017d08, + 0x481ed134, + 0x08407dc0, + 0xd02f07c0, + 0x30604620, + 0x08527942, + 0xd02907d2, + 0x0b808940, + 0xd1252801, + 0x09417e08, + 0xd00c07c9, + 0x07006fa1, + 0x0fc08809, + 0x04090240, + 0x66604308, + 0x1c806fa0, + 0xf998f001, + 0x480ee013, + 0x69803020, + 0x28006840, + 0x4a0fd00e, + 0x78012300, + 0x1a5956d3, + 0x00c9d408, + 0x78411808, + 0xd00307c9, + 0x66616801, + 0x66a06840, + 0x47804808, + 0x0000bd10, + 0x210001e0, + 0x00022a15, + 0x210000c8, + 0x00023d8f, + 0x00023075, + 0x00025500, + 0x210004e0, + 0x00024959, + 0x22ff0783, + 0x409a0edb, + 0x0e090789, + 0x28004099, + 0x0700da0b, + 0x38080f00, + 0x009b0883, + 0x181848ff, + 0x439369c3, + 0x61c3430b, + 0x08834770, + 0x009b48fc, + 0x68031818, + 0x430b4393, + 0x47706003, + 0x206549f9, + 0x09805c40, + 0x48f807c2, + 0x7e82d00a, + 0xd1072a02, + 0x2a027d42, + 0x2a01d004, + 0x2200d002, + 0x734a3120, + 0x49f27900, + 0x18400080, + 0x47006880, + 0x4aedb5ff, + 0x185b7e93, + 0x600b49ee, + 0x4bee8911, + 0xd1044299, + 0x46112386, + 0x31a85c9d, + 0x217be003, + 0x46115c8d, + 0x7989317c, + 0xd17e0989, + 0x690949e7, + 0xd07e2900, + 0x0426680c, + 0xb2e30e36, + 0xd0222e01, + 0x006d2610, + 0x1eed46b6, + 0x7bd23220, + 0x2a0146ac, + 0x1422d01e, + 0x4cdeb252, + 0x6824684e, + 0x009b3108, + 0x1f1b185b, + 0x40341880, + 0x93023030, + 0x94004ad9, + 0x23019103, + 0x4bce6013, + 0x691d2222, + 0x433d2710, + 0x2300611d, + 0x2608e032, + 0x46b600ad, + 0xe7db1fad, + 0xe7e01622, + 0x4fd0c920, + 0x4034406c, + 0x462c9401, + 0x032d2501, + 0x4dcb603d, + 0x60283540, + 0x3d404dc9, + 0x1a2d686d, + 0x4dc8d506, + 0x682f3d80, + 0xd40104ff, + 0xe7fabf20, + 0x9d014fc2, + 0x9d02633d, + 0x42a94470, + 0x9903d900, + 0x686d4dbb, + 0xd0064215, + 0x3a804ab9, + 0x27026815, + 0x601543bd, + 0x1c5b2200, + 0xd3d14563, + 0x49b89d00, + 0x40354065, + 0x684b3940, + 0xd4fc1a1b, + 0x630548b3, + 0x210048b3, + 0x4ba96001, + 0x21106918, + 0x61184388, + 0xd00b2a00, + 0x684148aa, + 0xd0fc4211, + 0x388048a8, + 0x22026801, + 0xe002e000, + 0x60014391, + 0x48a4bdff, + 0x68422122, + 0xd0fc420a, + 0x3a804aa1, + 0x20026811, + 0x60114381, + 0xb510bdff, + 0x69634ca3, + 0x70427083, + 0x42911562, + 0x2102dd03, + 0x71017001, + 0x2101e001, + 0x69a17001, + 0x8041489d, + 0x3940499b, + 0x70416ac9, + 0xb5f3bd10, + 0x4a93488f, + 0xb0818901, + 0xd1024291, + 0x35a84605, + 0x4605e001, + 0x3020357c, + 0x48947bc6, + 0x05806900, + 0x2e011600, + 0x1c40d002, + 0xe0001040, + 0x498f301e, + 0x6a093140, + 0x4b824a8e, + 0x691a4351, + 0x6a1b0e09, + 0xd01d2e01, + 0x01591852, + 0x316731ff, + 0x18544b7f, + 0x68d93340, + 0xb2894f81, + 0xb2821a08, + 0x68783f40, + 0xd4fc1b00, + 0x802960da, + 0x20504982, + 0x81284788, + 0x28009801, + 0x79aad008, + 0xf7ff9902, + 0xe007ffaa, + 0x01191852, + 0xe7e131ce, + 0x38404876, + 0x70e86ac0, + 0x79294879, + 0x43486840, + 0x2e0108c1, + 0x4620d00b, + 0x340e380f, + 0x1b12687a, + 0x4a74d4fc, + 0x61930c0b, + 0x6151b289, + 0x4620bdfe, + 0x3409380d, + 0xb5f0e7f2, + 0x46844c5f, + 0xb0874620, + 0x90023020, + 0x90047bc0, + 0x30404620, + 0x79029003, + 0x35a84625, + 0x2a1c2700, + 0x2a07d006, + 0x2a34d00b, + 0x2a1dd009, + 0xe132d007, + 0x28007968, + 0x6a20d002, + 0xda7e2803, + 0x2a1de12a, + 0x7d20d040, + 0x357c4625, + 0x0fc10680, + 0x28007968, + 0x2900d074, + 0x494fd072, + 0x39209b04, + 0x7f099105, + 0xd0372b01, + 0x0f090709, + 0x712b004b, + 0x025b2301, + 0x2300469e, + 0x93019300, + 0xd0402900, + 0x07db0983, + 0x2321d00c, + 0x7f1b061b, + 0xd0012b00, + 0x401823f7, + 0x781b4b4b, + 0xd0012b00, + 0x401823ef, + 0x09c34e42, + 0x42337836, + 0x2100d000, + 0x06834e45, + 0x1f360f5b, + 0xd0122b07, + 0x07db08c3, + 0x2021d013, + 0x76470600, + 0xe01c9600, + 0x21017dc0, + 0x0f000700, + 0xd0bd2804, + 0xe7bb2100, + 0x71290909, + 0x2001e7c8, + 0x46860280, + 0x0900e7eb, + 0xd00907c0, + 0x20012321, + 0x7658061b, + 0x90004833, + 0x02402001, + 0xe0009001, + 0x48232100, + 0x38402307, + 0x232263c3, + 0x68404820, + 0xd0fb4218, + 0x3840481e, + 0x4b2b6b40, + 0x482861d8, + 0x69033040, + 0x43b32610, + 0x4b286103, + 0x07806958, + 0x4826d1fc, + 0x68003040, + 0x06c371a8, + 0xe09ce001, + 0x0edbe0aa, + 0x28131e98, + 0x2302d300, + 0xd0632a1d, + 0x5503207b, + 0x30084660, + 0x29004684, + 0x9805d06f, + 0x7f4600df, + 0x2e041bbe, + 0x2604da00, + 0x28019804, + 0x00b0d055, + 0x300e4b0e, + 0xe0293340, + 0xe000ed00, + 0xe000e400, + 0x21000160, + 0x210001a0, + 0x00025500, + 0x40045080, + 0x00001826, + 0x210000e8, + 0x40022080, + 0x40043040, + 0xe000e280, + 0x40046080, + 0x21005874, + 0x400452c0, + 0x00155556, + 0x0000424f, + 0x210002c0, + 0x40045180, + 0x21000020, + 0x40042100, + 0x40042000, + 0x46636298, + 0x48ff18fb, + 0x434e6203, + 0x457648fe, + 0x46706046, + 0x4606dd00, + 0x990148fc, + 0x99016041, + 0x1e491989, + 0x68016081, + 0x43192321, + 0x20026001, + 0x6a279001, + 0xd0122a1d, + 0x62271c7f, + 0x98026267, + 0x28017bc0, + 0xe018d014, + 0x55032086, + 0x00f7e79d, + 0x371648ef, + 0x01186287, + 0x18c34663, + 0x9803e7d3, + 0x7dc01ebf, + 0xd50806c0, + 0x90012005, + 0xe01ee005, + 0x49e848e4, + 0xf7ff3040, + 0x9801fb46, + 0xdd064287, + 0x463179aa, + 0xf7ff9800, + 0x2002fe5e, + 0x4631e00c, + 0xf7ff9800, + 0x49dffe6e, + 0x6ac93140, + 0x00f970e9, + 0xf7ff3908, + 0x2003fdab, + 0xb00770a8, + 0x2001bdf0, + 0x2a1d70a8, + 0x6a20d004, + 0x62201c40, + 0xe0046260, + 0x70a82004, + 0xe00076a7, + 0x48d170af, + 0x49cd6287, + 0x62084660, + 0xd0e82a1d, + 0x7bc09802, + 0xd1e42801, + 0x304048c8, + 0x06c968c1, + 0x2100d5fc, + 0x29021c49, + 0x49c8dbfc, + 0xfb07f7ff, + 0xb5fee7d7, + 0x4cc648c7, + 0x46264780, + 0x900036a0, + 0x28007b70, + 0x6a20d051, + 0xdb4e2803, + 0x28009800, + 0x4625d14b, + 0x792f3540, + 0xd0462f1b, + 0x7128201d, + 0x30804620, + 0x90022100, + 0x6a2060c1, + 0x00c07ea1, + 0x18083010, + 0xfe79f7ff, + 0x28007ab0, + 0x6aa0d034, + 0xd0032800, + 0x70017bb1, + 0x62a01c40, + 0x06c07de8, + 0x7ab0d521, + 0xd9092802, + 0x6ac148a8, + 0xd0fc07c9, + 0x384048a6, + 0x22026801, + 0x60014311, + 0x4eaa7da8, + 0x75a81ec0, + 0x2003a901, + 0x280047b0, + 0x9802dcfa, + 0x36604626, + 0x89f77980, + 0x18380140, + 0x49a381f0, + 0x47889801, + 0x7da881f7, + 0x18407e29, + 0x6be16260, + 0x47882022, + 0xe0006420, + 0x9800712f, + 0xb5f8bdfe, + 0x48924c97, + 0x35204625, + 0x6ac07bee, + 0x07c02700, + 0x2065d05b, + 0x09805d00, + 0x489507c1, + 0x7e81d025, + 0xd0012903, + 0xd1202902, + 0x2a027d42, + 0x2a01d01d, + 0x7dc2d01b, + 0xd4030693, + 0xd1162902, + 0xd51406d1, + 0x22007b69, + 0xd00f2900, + 0x2e024631, + 0x7ac3d103, + 0xd0002b00, + 0x23042103, + 0x73e94319, + 0x27017dc1, + 0xd5010689, + 0x550a219c, + 0x7900736a, + 0x00804981, + 0x68801840, + 0x90004780, + 0xd0002f00, + 0x980073ee, + 0xd0202801, + 0x7aa034a0, + 0xd31c2805, + 0x06092121, + 0x00807e48, + 0x7f021840, + 0xd0182a02, + 0x77012103, + 0x8a204975, + 0x496a4788, + 0x70082001, + 0x20112102, + 0xfc92f7ff, + 0x49712001, + 0x60080440, + 0x60084970, + 0x3980496e, + 0x98006008, + 0x2001bdf8, + 0x2004bdf8, + 0x496c7708, + 0xe7e37008, + 0x4d61b570, + 0x34a0462c, + 0x1e417aa0, + 0xd8012902, + 0x72a01cc0, + 0x2805b2c0, + 0xd112d321, + 0x28026a68, + 0x4963dd08, + 0x47881e80, + 0x62691c81, + 0xd0012800, + 0xbd702001, + 0x46082100, + 0xfd53f7ff, + 0xf7ff2110, + 0x484cfc95, + 0x07c96ac1, + 0x484ad0fc, + 0x68013840, + 0x43112202, + 0x49476001, + 0x31808920, + 0x485560c8, + 0x28004780, + 0x7aa1d1e5, + 0xd3e22905, + 0x35407ae1, + 0xbd707169, + 0x4850b5f8, + 0x00064780, + 0x4c42d10f, + 0x89224b4e, + 0x429a6820, + 0x7b81d10a, + 0xdd072924, + 0x02c02003, + 0x80e03440, + 0x72202002, + 0xbdf82003, + 0x21004d3d, + 0x429a3560, + 0x6981d12b, + 0x63a10209, + 0x69404943, + 0x4a434788, + 0x7ed14f43, + 0x0988783b, + 0xd10a4218, + 0x20ff2321, + 0x7658061b, + 0x20004b37, + 0x60181f1b, + 0x20016058, + 0x34207038, + 0x28007be0, + 0x2801d002, + 0xe003d10b, + 0x07007f10, + 0xe0010f00, + 0x09007f10, + 0xd0022800, + 0x07c00888, + 0x2100d103, + 0x2000e001, + 0x736972a8, + 0xbdf84630, + 0x491eb5f0, + 0x5c422044, + 0xd00c2a43, + 0xd00d2a04, + 0x3368460b, + 0x4f1e7818, + 0xd0742800, + 0xd01528ff, + 0xd0062a04, + 0x460be009, + 0xe7f3335b, + 0x337b460b, + 0x68cce7f0, + 0x19640145, + 0x242f60cc, + 0x2c015c64, + 0x0640d101, + 0x62480e00, + 0x701820ff, + 0x4c06202f, + 0x34400200, + 0x4d046020, + 0x68636a48, + 0xd04007db, + 0x63ab230f, + 0xe0314e16, + 0x40045040, + 0x21005874, + 0x40048000, + 0x40045300, + 0x40046000, + 0x21000160, + 0x00022dd7, + 0x000231b7, + 0x000232d7, + 0x210001a0, + 0x00025500, + 0x0000423d, + 0xe000e280, + 0xe000e100, + 0x21000020, + 0x0002175f, + 0x000234eb, + 0x00022775, + 0x00001826, + 0x00025247, + 0x210000c8, + 0x210004e1, + 0x0000ffff, + 0xdd072801, + 0x1e80632e, + 0xdd1a2800, + 0x07db6863, + 0xe006d1f6, + 0x63a82007, + 0x632820ff, + 0x2800e011, + 0x6863dd0f, + 0x42332614, + 0x4af9d0b5, + 0x02127b52, + 0x4bf86022, + 0x601a2208, + 0x601a4bf7, + 0x20016248, + 0x0090bdf0, + 0x688019c0, + 0x20006408, + 0xb5f8bdf0, + 0x49f34cf2, + 0x42888920, + 0x2101d14f, + 0x46084af1, + 0x46254790, + 0x35402602, + 0xd1182800, + 0x478048ee, + 0xd0022800, + 0x02c02003, + 0x2100e011, + 0x75296827, + 0x30804620, + 0x900068ba, + 0x38606042, + 0x7cc16761, + 0xd0082900, + 0x7bc049e5, + 0x28004788, + 0x80e8d003, + 0x2003722e, + 0x6938bdf8, + 0x020049e1, + 0x48d863a0, + 0x7c403820, + 0x68f876a0, + 0x22014788, + 0x21004bdb, + 0x3b6c4610, + 0x48d94798, + 0x478038ac, + 0x68419800, + 0x784a2000, + 0xd1cd0793, + 0xd5070752, + 0x78006848, + 0x0ec006c0, + 0x29131e81, + 0x2000d300, + 0x6be176e8, + 0x4788203d, + 0x20006420, + 0x48cebdf8, + 0xbdf84780, + 0x4cc6b570, + 0x5d002044, + 0x008049cb, + 0x68801840, + 0x46054780, + 0xd0212801, + 0x5d00207e, + 0xd31d2805, + 0x06002021, + 0x00897e41, + 0x7f0a1809, + 0xd0172a02, + 0x77082003, + 0x49c13480, + 0x478888a0, + 0x200149c0, + 0x21027008, + 0xf7ff2011, + 0x2101faf3, + 0x044948b1, + 0x48b16001, + 0x48af6001, + 0x60013880, + 0xbd704628, + 0x77012104, + 0x700148b7, + 0xb570e7e4, + 0x46254cab, + 0x7fa83560, + 0x28021e40, + 0x6aa0d80d, + 0xd0042800, + 0x5d092182, + 0x1c407001, + 0x6a6062a0, + 0x62601e40, + 0x1cc07fa8, + 0x7fa877a8, + 0xd3212805, + 0x6a60d112, + 0xdd082802, + 0x1e8049a8, + 0x1c814788, + 0x28006261, + 0x2001d001, + 0x2100bd70, + 0xf7ff4608, + 0x2110fbaa, + 0xfaecf7ff, + 0x6ac148a1, + 0xd0fc07c9, + 0x3840489f, + 0x22026801, + 0x60014311, + 0x8ba8499c, + 0x60c83180, + 0x36404626, + 0x49947930, + 0x18400080, + 0x47806880, + 0xd1df2800, + 0x29057fa9, + 0x7fead301, + 0x29047172, + 0x7de1d3d8, + 0xd1022900, + 0x29007e21, + 0x7eead0d2, + 0x015268e1, + 0x60e11889, + 0xb570bd70, + 0x20444d7f, + 0x487b5d46, + 0x30804984, + 0x00b07ec4, + 0x68801840, + 0x4b874780, + 0x781a09a1, + 0xd10a4211, + 0x21ff2221, + 0x76510612, + 0x2200497f, + 0x600a1f09, + 0x2101604a, + 0x212f7019, + 0x29025d49, + 0x2e31d008, + 0x07e1d003, + 0xd0032900, + 0x0861e003, + 0xe7f907c9, + 0x35802400, + 0xbd70706c, + 0x4c69b5f8, + 0x46272500, + 0x723d3760, + 0x5d00202f, + 0xd03b2802, + 0x38ac4868, + 0x46264780, + 0x495f3640, + 0x31807ff0, + 0x78496220, + 0x75604308, + 0x6265485b, + 0x7fc53060, + 0xd0062d00, + 0x21207d20, + 0x75204308, + 0x0ec006e8, + 0x49667238, + 0x47887f30, + 0x2d004a65, + 0x4865d011, + 0x4b6061c5, + 0x63982007, + 0x35404d5e, + 0x69502105, + 0xd1fc0780, + 0x42086868, + 0x485dd0f9, + 0x68003040, + 0x7f306318, + 0xd0012800, + 0x62106e60, + 0x20396be1, + 0x64204788, + 0xbdf82000, + 0xe7fa4857, + 0x46014845, + 0x7bca3120, + 0x76823060, + 0x73c82002, + 0x47004853, + 0xb5004940, + 0x71083140, + 0xd0512822, + 0x2815dc15, + 0xdc08d044, + 0xf0004603, + 0x350afb7d, + 0x472c2c31, + 0x372c2c2c, + 0x46032c39, + 0xf0003b19, + 0x3f09fb73, + 0x45223122, + 0x47223322, + 0x28380022, + 0xdc0cd020, + 0xd01f2831, + 0x2823dc04, + 0x2826d034, + 0xe023d111, + 0xd0192835, + 0xd10c2836, + 0x283de018, + 0xdc04d020, + 0xd021283b, + 0xd104283c, + 0x2843e01c, + 0x2847d01c, + 0x492bd014, + 0x18400080, + 0xbd006880, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xbd004834, + 0xb5104810, + 0x31604601, + 0x7e89460a, + 0x5419232f, + 0xd05f2902, + 0x06897d01, + 0x6a01d562, + 0xdd5f2901, + 0x78496ec1, + 0x0ec906c9, + 0x2b121e8b, + 0x7d43d858, + 0x75431e5b, + 0xe04de055, + 0x21000048, + 0xe000e280, + 0xe000e100, + 0x21000160, + 0x00001825, + 0x00020bcb, + 0x0002097f, + 0x000207f5, + 0x00025247, + 0x0002485d, + 0x00025500, + 0x0000423d, + 0x21005874, + 0x21000020, + 0x0002175f, + 0x40045040, + 0x210004e1, + 0x00020e45, + 0x40042000, + 0x40042100, + 0x0002469d, + 0x00020f47, + 0x21005131, + 0x210050a1, + 0x21005047, + 0x21004f97, + 0x21004f2d, + 0x2100435d, + 0x210043c5, + 0x21004367, + 0x21004439, + 0x210044bb, + 0x21004e7b, + 0x21004d69, + 0x21004cd1, + 0x21004c5d, + 0x21004b83, + 0x21004ac7, + 0x21004599, + 0xff0af7fe, + 0xd0002800, + 0xbd102001, + 0x76d12100, + 0xbd102000, + 0x48bcb5f0, + 0x7ec049bc, + 0xb087684d, + 0xd07e09c0, + 0x06122221, + 0x28ff7e50, + 0x49b6d079, + 0x694c3120, + 0xd0742c00, + 0x68617826, + 0x21019101, + 0x91030249, + 0x00804611, + 0x46841840, + 0x28047f00, + 0x9803d001, + 0x2001e002, + 0x90030280, + 0xd9004285, + 0x00a84605, + 0x20009000, + 0x98019004, + 0xd01f2800, + 0x2a006802, + 0x7950d01c, + 0x07000671, + 0x06b00f83, + 0x18180fc0, + 0x18400fc9, + 0x07811c80, + 0xd0030f89, + 0x1a792704, + 0xb2c01808, + 0x210088d2, + 0xd9004282, + 0x98001a11, + 0xd9034288, + 0x90001ac8, + 0x90042001, + 0x49974662, + 0x91057f57, + 0x20007b09, + 0xd0022900, + 0xd00007f1, + 0x06f92001, + 0x07b20ec9, + 0x2201d50d, + 0x2b131e8b, + 0x2200d300, + 0xd50006bb, + 0x09bb2200, + 0xd0012b03, + 0xd1002a00, + 0x78622001, + 0xd802428a, + 0x428a78a2, + 0x2001d200, + 0x077209b9, + 0x2900d501, + 0x0732d007, + 0x2901d501, + 0x06f2d003, + 0x2902d502, + 0x2001d100, + 0x290078e1, + 0x2800d001, + 0x7a60d005, + 0xe0c2e000, + 0x72601c40, + 0x4b7ae0bf, + 0x9900aa02, + 0x47989801, + 0xd0030780, + 0x1c407aa0, + 0xe0aa72a0, + 0x00809800, + 0xd90142a8, + 0x08859800, + 0x22219802, + 0x1c407007, + 0x90020612, + 0x008b7e51, + 0x4696189a, + 0x2a047f12, + 0x1c49d04b, + 0x9905b2ca, + 0x7b0923fd, + 0x9b044019, + 0x4319005b, + 0x685f4b64, + 0x429f9b03, + 0x2304d901, + 0x23e74319, + 0x00d24019, + 0x22df4311, + 0x9a054011, + 0x01527bd2, + 0x46724311, + 0x4a5b7f93, + 0x8852b2c9, + 0x0612468c, + 0x00570f12, + 0x19d22101, + 0xd3004293, + 0x46622100, + 0x401a23bf, + 0x430a0189, + 0x1c407002, + 0x06b19002, + 0x2121d508, + 0x7e4a0609, + 0x18510092, + 0x70017f89, + 0x90021c40, + 0xd5050670, + 0x7841484a, + 0x70019802, + 0x90021c40, + 0x07999b02, + 0xd00d0f89, + 0x22042000, + 0x46021a51, + 0x2203e003, + 0x541ae7b3, + 0x42811c40, + 0x9802dcfb, + 0x90021808, + 0x06002021, + 0x4f407e40, + 0x28019e02, + 0x4f3fd100, + 0x2050493f, + 0x23014788, + 0x4684025b, + 0xda08429d, + 0xe0032000, + 0x587a0081, + 0x1c405072, + 0xdbf942a8, + 0x2000e016, + 0x587a0081, + 0x50721c40, + 0xdbf94298, + 0x3dff2201, + 0x02d22100, + 0x48303dff, + 0xe0053d02, + 0x59c3008f, + 0x18bf19bf, + 0x603b1c49, + 0xdbf742a9, + 0x4660492b, + 0x4788311c, + 0x9801492a, + 0x7a204788, + 0x1c402101, + 0x48287220, + 0x608103c9, + 0x1e4078e0, + 0xd20028fe, + 0x212170e0, + 0x7e480609, + 0x18400080, + 0x2a047f02, + 0x2100d00e, + 0x20017701, + 0x0440491f, + 0x49166008, + 0x70082000, + 0x2080491c, + 0x60083180, + 0xbdf0b007, + 0x77082000, + 0x70084919, + 0x4810e7ed, + 0x30204b18, + 0x88c07a01, + 0x47182200, + 0x4b168801, + 0x42994a16, + 0x20a8d103, + 0x48158510, + 0x4b12e006, + 0x42991e5b, + 0x208cd105, + 0x48128510, + 0x20016250, + 0x49114770, + 0x00004708, + 0x210000c8, + 0x21005874, + 0x21000180, + 0x0000369b, + 0x21008000, + 0x2100c000, + 0x00004835, + 0x00003a5b, + 0x40041100, + 0xe000e180, + 0x21000020, + 0x0000069f, + 0x00001826, + 0x21000108, + 0x000205e3, + 0x000205e9, + 0x000205fb, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, + 0x4810b510, + 0x481088c1, + 0xd0182905, + 0x68214c0f, + 0x0052084a, + 0x6ba26022, + 0x00520852, + 0x602163a2, + 0xfd88f7fe, + 0x07006ba0, + 0x2001d408, + 0x60606020, + 0x1c402000, + 0xdbfc280c, + 0x62202014, + 0xf7febd10, + 0xbd10fd79, + 0x21000380, + 0x00005b3f, + 0x40046000, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x79c94908, + 0x07d208ca, + 0x40c1d008, + 0x07c94806, + 0x4906d001, + 0x4906e000, + 0x60c11c49, + 0x20004770, + 0x00004770, + 0x210000e8, + 0x21000028, + 0x00000188, + 0x00000150, + 0x4833b510, + 0x47804c31, + 0xd0072801, + 0x7d213420, + 0xd1032900, + 0x4a2f2101, + 0x60910509, + 0x2807bd10, + 0x4a2dd001, + 0x4a2d4710, + 0x72c8604a, + 0x22014770, + 0x21024b2c, + 0x4718482a, + 0xb5104827, + 0x478030f8, + 0x6a404829, + 0xd10d2800, + 0x200a4928, + 0x28005608, + 0x1c40da09, + 0x4608d007, + 0x6a403820, + 0x42884924, + 0x4780d100, + 0xf7ffbd10, + 0xbd10ffe2, + 0x4b222100, + 0x46084a20, + 0x20014718, + 0x02404920, + 0x48206008, + 0x780122fb, + 0x70014011, + 0x300c4813, + 0xb5104700, + 0x4788491c, + 0x39204915, + 0xd0072801, + 0xd5040402, + 0x85082000, + 0x62484818, + 0xbd102001, + 0x4b0a6a4a, + 0x429a330c, + 0x4a15d101, + 0x490be005, + 0x4b146a4a, + 0xd1f2429a, + 0x624a4a13, + 0x0000bd10, + 0x21000160, + 0x0002a675, + 0x40041100, + 0x000291a9, + 0x21005721, + 0x00000806, + 0x0000069f, + 0x21000108, + 0x21000154, + 0x00029263, + 0x21005759, + 0x0002b4b5, + 0xe000e180, + 0x21000380, + 0x000296f7, + 0x2100574f, + 0x21005797, + 0x00029569, + 0x2100578d, + 0x07810882, + 0x0ec90092, + 0x78c0ca0c, + 0x424940ca, + 0x408b3120, + 0x0211431a, + 0x06000a09, + 0x47704308, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x00000000, + 0x00000000, +}; +#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1548 + +CPE_PATCH_TYPE patchCpeHd[] = { + 0x00000000, +}; +#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1 + +#define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0 + +#define _IRQ_PATCH_0 0x210042c1 + + +#ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START +#define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000 +#endif + +#ifndef _MULTI_PROTOCOL_RTLS_CPERAM_START +#define _MULTI_PROTOCOL_RTLS_CPERAM_START 0x21000000 +#endif + +#define _MULTI_PROTOCOL_RTLS_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET 0x03D4 +#define _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET 0x0480 +#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET 0x404C + +#define _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR +static uint8_t bMultiProtocolRtlsPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET); + + + pPatchTab[21] = 0; + pPatchTab[1] = 1; + pPatchTab[18] = 2; + pPatchTab[81] = 3; + pPatchTab[26] = 4; + pPatchTab[139] = 5; + pPatchTab[163] = 6; + pPatchTab[76] = 7; + pPatchTab[62] = 8; + pPatchTab[64] = 9; + pPatchTab[91] = 10; + pPatchTab[79] = 11; + pPatchTab[140] = 12; + pPatchTab[150] = 13; + pPatchTab[107] = 14; + pPatchTab[13] = 15; + pPatchTab[31] = 16; + pPatchTab[152] = 17; + pPatchTab[151] = 18; + pPatchTab[73] = 19; + pPatchTab[7] = 20; + pPatchTab[164] = 21; + pPatchTab[40] = 22; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyMultiProtocolRtlsPatch(void) +{ +#ifdef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); +#else + if (!bMultiProtocolRtlsPatchEntered) + { + enterMultiProtocolRtlsSysPatch(); + enterMultiProtocolRtlsCpePatch(); + bMultiProtocolRtlsPatchEntered = 1; + } +#endif + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +void refreshMultiProtocolRtlsPatch(void) +{ + enterMultiProtocolRtlsCpeHdPatch(); + configureMultiProtocolRtlsPatch(); +} + +void cleanMultiProtocolRtlsPatch(void) +{ +#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR + bMultiProtocolRtlsPatchEntered = 0; +#endif +} + +void rf_patch_cpe_multi_protocol_rtls(void) +{ + applyMultiProtocolRtlsPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.h new file mode 100644 index 00000000..f790a0b0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_multi_protocol_rtls.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_multi_protocol_rtls.h +* +* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H +#define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanMultiProtocolRtlsPatch(void); +extern void refreshMultiProtocolRtlsPatch(void); +extern void rf_patch_cpe_multi_protocol_rtls(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.c new file mode 100644 index 00000000..a0ae8814 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.c @@ -0,0 +1,372 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_prop.c +* +* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#include "rf_patch_cpe_prop.h" + +#ifndef CPE_PATCH_TYPE +#define CPE_PATCH_TYPE static const uint32_t +#endif + +#ifndef SYS_PATCH_TYPE +#define SYS_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC static +#endif + +#ifndef _APPLY_PATCH_TAB +#define _APPLY_PATCH_TAB +#endif + + +CPE_PATCH_TYPE patchImageProp[] = { + 0x21004071, + 0x210040db, + 0x2100409d, + 0x21004109, + 0x21004115, + 0x21004121, + 0x21004139, + 0x21004151, + 0x210042db, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x4910d107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490d2002, + 0x210c780a, + 0xd0024211, + 0x2280490b, + 0xb003600a, + 0xb5f0bdf0, + 0x4909b083, + 0x20004708, + 0x47884908, + 0x78014804, + 0x43912240, + 0x48067001, + 0x00004700, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x000063f7, + 0x00031b23, + 0xf888f000, + 0x47004800, + 0x00007f57, + 0xf888f000, + 0x47004800, + 0x0000881b, + 0x781a4b09, + 0x43a22408, + 0xd0002800, + 0x701a4322, + 0x47104a00, + 0x00008e83, + 0x78084903, + 0xd4010700, + 0x47004802, + 0x00004770, + 0x21000380, + 0x00007e5f, + 0x20284a04, + 0x48044790, + 0x60412101, + 0x4a044803, + 0x47106041, + 0x0000424f, + 0x40045000, + 0x40046000, + 0x00004285, + 0x4901b5f8, + 0x00004708, + 0x0000640d, + 0x4d1fb570, + 0xb2c47828, + 0x4780481e, + 0x28037828, + 0x2c03d134, + 0x481cd032, + 0x0d406880, + 0x481a07c2, + 0x31604601, + 0x2a003080, + 0x241fd003, + 0x8845570c, + 0x241ee002, + 0x8805570c, + 0xd01f2c00, + 0x4a154813, + 0x79006941, + 0x10484341, + 0x69494911, + 0x49101840, + 0x7f493940, + 0x05404790, + 0x42691540, + 0xdb0d4288, + 0xdc0b42a8, + 0x69994b0c, + 0x4602b288, + 0x43620c09, + 0x12520409, + 0xb2801880, + 0x61984308, + 0x0000bd70, + 0x210002e4, + 0x00004179, + 0x21000028, + 0x21000380, + 0x21000300, + 0x000081cb, + 0x40044040, + 0x490c6b80, + 0x0f000700, + 0x47707148, + 0x490a4a09, + 0x79502318, + 0x7e4956cb, + 0x428118c0, + 0x4608dd01, + 0x280fe002, + 0x200fdd00, + 0x090989d1, + 0x43010109, + 0x477081d1, + 0x210002e0, + 0x21000088, + 0x4601b510, + 0x482c4b2b, + 0xbf20e000, + 0x07926942, + 0x4829d1fb, + 0x30407ada, + 0x2a0b6800, + 0xf000d101, + 0xbd10f843, + 0x1a522220, + 0x4a244090, + 0x6993ba00, + 0x48214043, + 0xbf20e000, + 0x07926942, + 0x0088d4fb, + 0x1840491f, + 0x481c63c3, + 0x60033040, + 0xb5104770, + 0xe0004819, + 0x6942bf20, + 0xd4fb0792, + 0x4b176b42, + 0x40506998, + 0x07d48a5a, + 0x2401d001, + 0x08524060, + 0x2220825a, + 0x40881a51, + 0xba00490f, + 0x60083140, + 0xb510bd10, + 0xf7ff4604, + 0x490cff49, + 0x09897c09, + 0xd00807c8, + 0x07e1480b, + 0x490bd001, + 0x490be000, + 0x490b6201, + 0xbd106241, + 0x1a512220, + 0xba004088, + 0x00004770, + 0x21000160, + 0x40042000, + 0x21000028, + 0x400421c0, + 0x21000380, + 0x210042a7, + 0x2100427d, + 0x21004259, +}; +#define _NWORD_PATCHIMAGE_PROP 184 + +#define _NWORD_PATCHCPEHD_PROP 0 + +#define _NWORD_PATCHSYS_PROP 0 + +#define _IRQ_PATCH_0 0x21004181 + + +#ifndef _PROP_SYSRAM_START +#define _PROP_SYSRAM_START 0x20000000 +#endif + +#ifndef _PROP_CPERAM_START +#define _PROP_CPERAM_START 0x21000000 +#endif + +#define _PROP_SYS_PATCH_FIXED_ADDR 0x20000000 + +#define _PROP_PATCH_VEC_ADDR_OFFSET 0x03D0 +#define _PROP_PATCH_TAB_OFFSET 0x03D4 +#define _PROP_IRQPATCH_OFFSET 0x0480 +#define _PROP_PATCH_VEC_OFFSET 0x404C + +#define _PROP_PATCH_CPEHD_OFFSET 0x04E0 + +#ifndef _PROP_NO_PROG_STATE_VAR +static uint8_t bPropPatchEntered = 0; +#endif + +PATCH_FUN_SPEC void enterPropCpePatch(void) +{ +#if (_NWORD_PATCHIMAGE_PROP > 0) + uint32_t *pPatchVec = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET); + + memcpy(pPatchVec, patchImageProp, sizeof(patchImageProp)); +#endif +} + +PATCH_FUN_SPEC void enterPropCpeHdPatch(void) +{ +#if (_NWORD_PATCHCPEHD_PROP > 0) + uint32_t *pPatchCpeHd = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); + + memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); +#endif +} + +PATCH_FUN_SPEC void enterPropSysPatch(void) +{ +} + +PATCH_FUN_SPEC void configurePropPatch(void) +{ + uint8_t *pPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); + uint32_t *pIrqPatch = (uint32_t *) (_PROP_CPERAM_START + _PROP_IRQPATCH_OFFSET); + + + pPatchTab[76] = 0; + pPatchTab[62] = 1; + pPatchTab[64] = 2; + pPatchTab[140] = 3; + pPatchTab[150] = 4; + pPatchTab[152] = 5; + pPatchTab[151] = 6; + pPatchTab[73] = 7; + pPatchTab[85] = 8; + + pIrqPatch[1] = _IRQ_PATCH_0; +} + +PATCH_FUN_SPEC void applyPropPatch(void) +{ +#ifdef _PROP_NO_PROG_STATE_VAR + enterPropSysPatch(); + enterPropCpePatch(); +#else + if (!bPropPatchEntered) + { + enterPropSysPatch(); + enterPropCpePatch(); + bPropPatchEntered = 1; + } +#endif + enterPropCpeHdPatch(); + configurePropPatch(); +} + +void refreshPropPatch(void) +{ + enterPropCpeHdPatch(); + configurePropPatch(); +} + +void cleanPropPatch(void) +{ +#ifndef _PROP_NO_PROG_STATE_VAR + bPropPatchEntered = 0; +#endif +} + +void rf_patch_cpe_prop(void) +{ + applyPropPatch(); +} + +#undef _IRQ_PATCH_0 + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.h new file mode 100644 index 00000000..61c79b3c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_cpe_prop.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* Filename: rf_patch_cpe_prop.h +* +* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2022, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ +#ifndef _RF_PATCH_CPE_PROP_H +#define _RF_PATCH_CPE_PROP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +extern void cleanPropPatch(void); +extern void refreshPropPatch(void); +extern void rf_patch_cpe_prop(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // _RF_PATCH_CPE_PROP_H + diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.c new file mode 100644 index 00000000..b60a06fc --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.c @@ -0,0 +1,289 @@ +/****************************************************************************** +* Filename: rf_patch_mce_bt5.h +* +* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x1 and CC26x1 +* +* Copyright (c) 2021, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_bt5.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +MCE_PATCH_TYPE patchBle5Mce[189] = { + 0x2dee6039, + 0x2dc22dce, + 0x2fef0f54, + 0x5f970fef, + 0x5000179d, + 0x40000240, + 0x0000000c, + 0x00091488, + 0x000105f9, + 0x008b8000, + 0x0f500080, + 0x0a1d0000, + 0x00000590, + 0x04000005, + 0x00c17b20, + 0x000f0000, + 0x017f7f27, + 0x000c8000, + 0x14980000, + 0x05f90009, + 0x80000000, + 0x0080008b, + 0x00000f70, + 0x0590121d, + 0x00050000, + 0x7b200400, + 0x000000c1, + 0x7f26000f, + 0x720d017f, + 0x720f720e, + 0xa35d7210, + 0x654aa4e5, + 0x7100b0d0, + 0xb110a0d0, + 0x8162721b, + 0x39621020, + 0x00200630, + 0x11011630, + 0x6c011401, + 0x605c605c, + 0x605c605c, + 0x605c605c, + 0x605c605c, + 0x6065605c, + 0x60cd6083, + 0x605d1220, + 0x73111210, + 0x73137312, + 0x001081b1, + 0xb07091b0, + 0xc2216040, + 0xc302c5fb, + 0x1820c460, + 0x6e236f13, + 0x16121611, + 0x94eb686a, + 0x9c8378a3, + 0x1e008170, + 0xc030445c, + 0xc1f092b0, + 0xc63292d0, + 0x1820c9c0, + 0x12034081, + 0x16126e23, + 0xb63c687e, + 0xb005605c, + 0xc1007291, + 0xb12891f0, + 0xb113b120, + 0xb0e8b111, + 0xb1287100, + 0xb230a0e8, + 0x8c80b910, + 0xb1119930, + 0x84b484a2, + 0xb0d1c0f3, + 0xb0127100, + 0xb111b002, + 0x7291a0d1, + 0xb630722c, + 0xb003b013, + 0x7100b0e0, + 0x8170b120, + 0x819092c0, + 0x71009640, + 0x92c3b120, + 0x71009642, + 0x9644b120, + 0xb1207100, + 0xa630a0e0, + 0xb0d3b633, + 0xb1137100, + 0xc030a0d3, + 0xc0209910, + 0xb0d19930, + 0xb1117100, + 0x7291a0d1, + 0xa002a003, + 0x7305656e, + 0x73917306, + 0xa2307291, + 0x9010c7c0, + 0x64f3605c, + 0x65247860, + 0x68d1c5f0, + 0xb0d5652a, + 0xc031b115, + 0x80907100, + 0x45342250, + 0xa910b074, + 0xb9107393, + 0x7313720f, + 0xa0d5b231, + 0x8b40b35d, + 0x97003920, + 0xb234653f, + 0x6558c261, + 0x44ed22f3, + 0xb0786566, + 0x6546c2a3, + 0x6574c030, + 0x84b0605c, + 0x997095a0, + 0x100e8980, + 0x959084a0, + 0x89809970, + 0xc080140e, + 0xc080180e, + 0x8351180e, + 0x39213981, + 0x16310661, + 0x14101100, + 0x311e6c00, + 0x318e311e, + 0x972e398e, + 0x22308240, + 0xb0d54516, + 0xb1157100, + 0x610ea0d5, + 0x91e0c100, + 0x99107810, + 0x789a13e7, + 0xc540b4e5, + 0xb0029010, + 0xb006b004, + 0x78507000, + 0x90309050, + 0x90607870, + 0x70009040, + 0xb06cb235, + 0xb089b011, + 0xa0d1b4e5, + 0xb13da0d0, + 0x7000b0fd, + 0x8a439a31, + 0x31338a54, + 0x31343d53, + 0x96933d54, + 0xb05396a4, + 0xa4e560d4, + 0xb064a044, + 0x1e038183, + 0x7000413f, + 0x91179933, + 0xa35d7100, + 0x73917223, + 0x72037291, + 0x656e7204, + 0x9000d030, + 0x9010ffc0, + 0x7305a008, + 0x70007306, + 0x8940895b, + 0x312318b0, + 0x18838ca8, + 0x18131803, + 0xa9109933, + 0xb910b111, + 0x7000b0d1, + 0x416c1e08, + 0xb7447100, + 0x9938b111, + 0x70007100, + 0xc8018630, + 0x04103151, + 0x70009630, + 0x89f09a00, + 0x45752200, + 0x7000b9e0 +}; + +PATCH_FUN_SPEC void rf_patch_mce_bt5(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 189; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchBle5Mce[i]; + } +#else + const uint32_t *pS = patchBle5Mce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 23; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.h new file mode 100644 index 00000000..e69d2832 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_bt5.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: rf_patch_mce_bt5.h +* +* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x1 and CC26x1 +* +* Copyright (c) 2021, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_MCE_BT5_H +#define _RF_PATCH_MCE_BT5_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_bt5(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.c new file mode 100644 index 00000000..6bf3d0c4 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.c @@ -0,0 +1,585 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genook.h +* +* Description: RF core patch for General OOK support in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_genook.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchGenookMce[489] = { + 0x0000603b, + 0x01952fcf, + 0x7fff0001, + 0x030c003f, + 0x070c680a, + 0x00010000, + 0xaaaa000f, + 0x00fc00aa, + 0x272d8080, + 0x00170003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00020387, + 0x00434074, + 0x00028000, + 0x06f00020, + 0x091e0000, + 0x00540500, + 0x00000000, + 0x00505014, + 0x000f0000, + 0x007f7f30, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72230000, + 0x73037263, + 0x72037305, + 0x73067304, + 0x73917204, + 0xc7c07291, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720e720d, + 0x7210720f, + 0x7100b0d0, + 0xa0d0b110, + 0x8162721b, + 0x06701020, + 0x407d1e00, + 0x407e1e10, + 0x40681e20, + 0x06f23982, + 0x11011632, + 0x6c011421, + 0x61936193, + 0x633f6329, + 0x39423982, + 0x11011632, + 0x6c011421, + 0x60ef60ef, + 0x12206118, + 0x12106074, + 0x73117223, + 0x73137312, + 0x001081b1, + 0xb07091b0, + 0x60736050, + 0xc2b2c121, + 0x1820c4e0, + 0x6e236f13, + 0x16121611, + 0x78706882, + 0x78809c80, + 0x78909c90, + 0x78b09ca0, + 0x790099c0, + 0x94909480, + 0xc750c4f2, + 0x409a1820, + 0x6e231203, + 0x68971612, + 0x979078a0, + 0x81906073, + 0x81709640, + 0x2a703980, + 0x16111001, + 0x84b484a2, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040c1, + 0x40b71c10, + 0x10134cb9, + 0x18301803, + 0x1a101a13, + 0x68b43912, + 0x13f360c1, + 0x13f360c1, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0e868bf, + 0xb1287100, + 0xb230a0e8, + 0xb012b002, + 0x22168246, + 0x817640c8, + 0x06f63d46, + 0x81708195, + 0x105106f0, + 0x65620611, + 0x68d13d15, + 0x22f08170, + 0x1a1644cb, + 0x87914cce, + 0x9a11d030, + 0x13f067cb, + 0x40e81c03, + 0x1021c0f0, + 0x65620611, + 0x68e33d12, + 0x1041c0f0, + 0x65620611, + 0x68e93d14, + 0x73117000, + 0xc0007312, + 0xb11191f0, + 0xc050b0d1, + 0xc0109910, + 0xc0089930, + 0x8ca3649d, + 0x39533983, + 0x82100613, + 0x410f2210, + 0x083181d1, + 0x65621017, + 0x39808160, + 0x1e103940, + 0x1071450e, + 0x65620a11, + 0x120160ff, + 0xb2346562, + 0xb111a0d1, + 0xc040a0d3, + 0x607367cb, + 0x73117223, + 0xc0007312, + 0xb11191f0, + 0xc050b0d1, + 0xc0109910, + 0xb2309930, + 0x22168246, + 0xb0024124, + 0xc008b012, + 0x78cac030, + 0x061110a1, + 0x391a6562, + 0xc0f0692c, + 0x10a178da, + 0x65620611, + 0x6933391a, + 0x78eac070, + 0x061110a1, + 0x391a6562, + 0xc090693a, + 0x10a178fa, + 0x65620611, + 0x6941391a, + 0x39838ca3, + 0x06133953, + 0x22108210, + 0xc0114157, + 0x65620831, + 0x67a781d1, + 0xc0016562, + 0x65620831, + 0xc011614a, + 0xc0016562, + 0xb2346562, + 0xb111a0d1, + 0xc050a0d3, + 0x607367cb, + 0x2208c029, + 0x22014568, + 0x6177417e, + 0x457e2201, + 0x22ff879f, + 0x65834177, + 0x92313111, + 0x10183911, + 0xc019811e, + 0xc0294576, + 0xb111617e, + 0x31117100, + 0x39119231, + 0xc0191018, + 0x7100b111, + 0x457e1a19, + 0x10f97000, + 0x04f9785f, + 0x10001000, + 0x10001000, + 0x10001000, + 0x10001000, + 0x10001000, + 0x45861a19, + 0x67617000, + 0x67cbc060, + 0xc01084ed, + 0x312d140d, + 0x8c9e142d, + 0x311e318e, + 0x8c99397e, + 0x39793149, + 0x31293949, + 0x99301090, + 0xb9147291, + 0xc662a914, + 0xb0029912, + 0xe070b012, + 0x9a2f9a1b, + 0xb63567cb, + 0x66aab63c, + 0x8c81a1b2, + 0x45bc22f1, + 0x22f18ca1, + 0x61f145bc, + 0x80b77100, + 0x460f2207, + 0x22b08090, + 0x105441c8, + 0x6648873c, + 0x61bc669f, + 0x22f18c81, + 0x223741d2, + 0xb13341d2, + 0x223080b0, + 0x61e045cd, + 0x41e522e1, + 0x22508090, + 0xb11541e5, + 0x22108240, + 0x993941bc, + 0xa914b914, + 0x61bcb116, + 0xb914993d, + 0xb116a914, + 0x8ca061bc, + 0x42eb22f0, + 0x42eb2237, + 0xb133b075, + 0x223080b0, + 0xb08745eb, + 0x710061bc, + 0x220780b7, + 0x2237460f, + 0x8090460e, + 0x420022b0, + 0x873c1054, + 0x669f6648, + 0x8c8161f1, + 0x41f122e1, + 0x22508090, + 0xb11541f1, + 0x22108240, + 0x993d41f1, + 0xa914b914, + 0x61f1b116, + 0xb130b1b2, + 0xb133a0f0, + 0xb074a0f3, + 0xa044b231, + 0x22408360, + 0xb0d24224, + 0x7100b112, + 0x22b08090, + 0x10544224, + 0x6648873c, + 0x621b669f, + 0xb112a0d2, + 0x9a1ad080, + 0xc00f67cb, + 0x7100c00e, + 0x22008090, + 0x873c4450, + 0x66481054, + 0x8160669f, + 0x06f03980, + 0x463a1e10, + 0x623b668b, + 0x8180667f, + 0x422b1e00, + 0x1cf01a10, + 0x62434e2b, + 0xa0d6622b, + 0xa0dbb116, + 0x6317b11b, + 0x8a72ba34, + 0x063189c1, + 0x42651e01, + 0x42571e21, + 0x425e1e31, + 0x14261056, + 0x10653916, + 0x10566266, + 0x18563126, + 0x39261426, + 0x62661065, + 0x31361056, + 0x14261856, + 0x10653936, + 0x10266266, + 0x39228242, + 0x4e741c26, + 0xc1011862, + 0x4e721c12, + 0x18211201, + 0x627c3121, + 0x627ccc01, + 0xc1011826, + 0x4e7b1c16, + 0x31211061, + 0xc401627c, + 0xb11b9731, + 0x1c8a7000, + 0x8240468a, + 0x1c043920, + 0xc0014e87, + 0xc0116288, + 0x161f91c1, + 0x1c8a7000, + 0x8730469e, + 0x3d803180, + 0x18701001, + 0x1e1e1017, + 0x3980469d, + 0x8ca13970, + 0x39513981, + 0x91c00810, + 0x0a1e161f, + 0x87317000, + 0x081010c0, + 0x42a62270, + 0x62a9120a, + 0x42a41cba, + 0x7000161a, + 0xb116b11b, + 0xb130b111, + 0xb115b133, + 0x720db112, + 0x720f720e, + 0xb0f0b0db, + 0x8c82b0f3, + 0x42bd22f2, + 0xb913b0d6, + 0x8ca062c0, + 0x42e022f0, + 0xa444b445, + 0xa469a468, + 0x3180caa0, + 0x0001caa1, + 0x94d194c1, + 0x31838ca3, + 0x84503983, + 0x39803180, + 0x00303183, + 0x84409450, + 0x39503150, + 0x39838ca3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899440, + 0x42ea22e2, + 0x394a8c9a, + 0x312a398a, + 0xb0d5993a, + 0xb913b0d6, + 0xb23f7000, + 0xa0f3a0f0, + 0x993ea0db, + 0xa914b914, + 0xb130b116, + 0xb11bb133, + 0x22008240, + 0xb11542f6, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x67cbc090, + 0xb9147100, + 0xb0d5b116, + 0x7100a23f, + 0xa0d5b115, + 0x90307820, + 0x78309002, + 0x90609040, + 0xa23fb072, + 0x993a66aa, + 0xb116a914, + 0xba3c61b5, + 0x8b5481b0, + 0x31843924, + 0x91b40004, + 0x67cbc0a0, + 0x72917391, + 0x72067263, + 0x72047202, + 0x73067305, + 0x67616073, + 0x67cbc0b0, + 0xb0dbb118, + 0xb005b11b, + 0x7100b258, + 0x8ca0b11b, + 0x433922e0, + 0x22108240, + 0x66484331, + 0x39708730, + 0x679d0a10, + 0x67616331, + 0x67cbc0c0, + 0xb074b0db, + 0x89ce120c, + 0x1e0e398e, + 0x1210434f, + 0x1a2030e0, + 0x66487100, + 0x71006b4c, + 0x22e08ca0, + 0x82404356, + 0x43472210, + 0x39716648, + 0x91c10a11, + 0x1e048184, + 0x161c4347, + 0x43171cc4, + 0x12006347, + 0xb11891e0, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78628440, + 0x81730420, + 0x2a733983, + 0xc1f294e3, + 0x31621832, + 0x31511021, + 0x00200012, + 0x78209440, + 0x90509030, + 0x90407830, + 0xc04b9060, + 0x39308360, + 0x1e000630, + 0x300b4386, + 0x1a1b10b8, + 0xc00a3918, + 0xa234108f, + 0x8360a233, + 0x43942240, + 0xc022165f, + 0x639a67ac, + 0x439a2230, + 0xc022163f, + 0xb23367ac, + 0xb072b235, + 0x22007000, + 0xb00547a1, + 0x800063a6, + 0x43a62250, + 0xa005b270, + 0x82d27000, + 0x06123972, + 0x70000821, + 0x302084a0, + 0x39818191, + 0x1823c083, + 0x14103831, + 0x84b09590, + 0x84a13020, + 0x38313981, + 0x95a01410, + 0x302084c0, + 0x39818191, + 0x14103831, + 0x84d095b0, + 0x84c13020, + 0x38313981, + 0x95c01410, + 0x9a007000, + 0x220089f0, + 0xb9e047cc, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_genook(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 489; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchGenookMce[i]; + } +#else + const uint32_t *pS = patchGenookMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 61; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.h new file mode 100644 index 00000000..6fabca19 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_genook.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Filename: rf_patch_mce_genook.h +* +* Description: RF core patch for General OOK support in CC13x2 and CC26x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_GENOOK_H +#define _RF_PATCH_MCE_GENOOK_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_genook(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.c new file mode 100644 index 00000000..4cff7790 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.c @@ -0,0 +1,463 @@ +/****************************************************************************** +* Filename: rf_patch_mce_iqdump.h +* +* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_iqdump.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchIqdumpMce[363] = { + 0x2fcf6030, + 0x00013f9d, + 0xff00003f, + 0x07ff0fff, + 0x0300f800, + 0x00068080, + 0x00170003, + 0x00003d1f, + 0x08000000, + 0x0000000f, + 0x00000387, + 0x00434074, + 0x00828000, + 0x06f00080, + 0x091e0000, + 0x00540510, + 0x00000007, + 0x00505014, + 0xc02f0000, + 0x017f0c30, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0000aa00, + 0x66ca7223, + 0xa4e5a35d, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xffc0b008, + 0xa0089010, + 0x720e720d, + 0x7210720f, + 0x7100b0d0, + 0xa0d0b110, + 0x8162721b, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60886087, + 0x613e6104, + 0x60876087, + 0x60876087, + 0x60886087, + 0x61e46104, + 0x60876087, + 0x60876087, + 0x60886087, + 0x614e6104, + 0x60876087, + 0x60876087, + 0x60886087, + 0x62006104, + 0x60876087, + 0x60876087, + 0x60886087, + 0x61866104, + 0x60876087, + 0x60876087, + 0x61126088, + 0x1210614e, + 0x73117223, + 0x73137312, + 0x001081b1, + 0xb07091b0, + 0x607d6044, + 0x66d0c030, + 0xc2b2c0c1, + 0x1820c4e0, + 0x6e236f13, + 0x16121611, + 0x7830688e, + 0x78a099c0, + 0x94909480, + 0xc750c4f2, + 0x40a01820, + 0x6e231203, + 0x689d1612, + 0x999078b0, + 0xb63c7263, + 0x8190607d, + 0x81709640, + 0x2a703980, + 0x16111001, + 0x84b484a2, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040c9, + 0x40bf1c10, + 0x10134cc1, + 0x18301803, + 0x1a101a13, + 0x68bc3912, + 0x13f360c9, + 0x13f360c9, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0e868c7, + 0xb1287100, + 0xb230a0e8, + 0x8990b910, + 0xb1119930, + 0x7100b0d1, + 0xb012b002, + 0xa0d1b111, + 0xb6307291, + 0xb013b003, + 0xb0e0722c, + 0xb1207100, + 0x92c08170, + 0xb1207100, + 0x22f08170, + 0x13f044e2, + 0x40ee1c03, + 0x964292c3, + 0xb1207100, + 0x964492c5, + 0xb1207100, + 0xa630b0e0, + 0xa0e17000, + 0x9910c030, + 0x9930c040, + 0xb0d1b111, + 0xb1117100, + 0x7291a0d1, + 0xa002a003, + 0x7000a230, + 0x73127311, + 0x66d0c040, + 0x91f0c100, + 0xb63364a5, + 0xb0d3b113, + 0xa0d37100, + 0x607d64f5, + 0x73127311, + 0x66d0c050, + 0x91f0c030, + 0xb0e8b634, + 0xb1287100, + 0xb230a0e8, + 0xb012b002, + 0xb013b003, + 0x92f01200, + 0xb0e1b121, + 0xb1217100, + 0x06208210, + 0x45261e20, + 0x66d0c060, + 0xb1217100, + 0x92f181d1, + 0x00000000, + 0x82120000, + 0x1e220622, + 0xc070412e, + 0xa63466d0, + 0x607d64f5, + 0xa0f0a0d2, + 0x7311a0f3, + 0x66447312, + 0x66d0c080, + 0xc035b0d2, + 0x9b757100, + 0xb074ba38, + 0x6148b112, + 0xa0f0a0d2, + 0x7311a0f3, + 0x66447312, + 0xc000c18b, + 0x120c91e0, + 0x786a1218, + 0x788e787d, + 0xb07410a9, + 0xc050b0d2, + 0x7100b112, + 0xc0906960, + 0xc03566d0, + 0x7100b112, + 0x8bf09b75, + 0x8ca165d9, + 0x41732201, + 0x1ca81080, + 0x12084572, + 0x65d01618, + 0x65d98c00, + 0x22018ca1, + 0x1090417e, + 0x1e091a19, + 0x10a9457e, + 0x818465d0, + 0x41661e04, + 0x1c4c14bc, + 0x61664eb3, + 0xa0f0a0d2, + 0x7311a0f3, + 0x66447312, + 0x120c721e, + 0xb0741205, + 0xc050b0d2, + 0x7100b112, + 0xc0a06992, + 0x789d66d0, + 0xb11289ce, + 0x8c907100, + 0x41a42200, + 0x22108230, + 0xb23145a4, + 0x66d0c0b0, + 0x8ab29a3d, + 0x3d823182, + 0x31808af0, + 0x18023d80, + 0x1e0e063e, + 0x1e2e41c6, + 0x1e3e41b8, + 0x105641bf, + 0x3d161426, + 0x61c71065, + 0x31261056, + 0x14261856, + 0x10653d26, + 0x105661c7, + 0x18563136, + 0x3d361426, + 0x61c71065, + 0x39761026, + 0x818491c6, + 0x41991e04, + 0x1c4c161c, + 0x61994eb3, + 0xc0b01001, + 0x391191c1, + 0x10001000, + 0x69d21000, + 0x31307000, + 0x1cd03d30, + 0x1ce04de0, + 0x700049e2, + 0x700010d0, + 0x700010e0, + 0x66d0c0c0, + 0xa0f0a0d2, + 0x7311a0f3, + 0x66447312, + 0xb0f0b130, + 0x80b07100, + 0x45f32200, + 0xb23161ee, + 0x66d0c0d0, + 0xa0f0b130, + 0xc035b0d2, + 0x9b757100, + 0xb074ba38, + 0x61fab112, + 0x66d0c0e0, + 0xa0f0a0d2, + 0x7311a0f3, + 0x66447312, + 0xc000c18b, + 0x120c91e0, + 0x786a1218, + 0x788e787d, + 0xb13010a9, + 0x7100b0f0, + 0x220080b0, + 0x62134618, + 0xb231b074, + 0x66d0c0f0, + 0xa0f0b130, + 0xc020b0d2, + 0x7100b112, + 0xc0356a20, + 0x7100b112, + 0x8bf09b75, + 0x8ca165d9, + 0x42312201, + 0x1ca81080, + 0x12084630, + 0x65d01618, + 0x65d98c00, + 0x22018ca1, + 0x1090423c, + 0x1e091a19, + 0x10a9463c, + 0x818465d0, + 0x42241e04, + 0x1c4c14bc, + 0x62244eb3, + 0x22308240, + 0xb0d5464c, + 0xb1157100, + 0x6244a0d5, + 0x66d0c100, + 0xb006b118, + 0xb004b016, + 0xb002b014, + 0x8440b012, + 0x04207842, + 0x39838173, + 0x94e32a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94400020, + 0x16101030, + 0x22103930, + 0x1220426a, + 0x10033150, + 0x16303180, + 0x12029380, + 0x22731204, + 0x84a0427c, + 0x89829970, + 0x84c01a82, + 0x89849970, + 0x627e1a84, + 0x42892263, + 0x997084b0, + 0x1a808980, + 0x84d01402, + 0x89809970, + 0x14041a80, + 0x84b06295, + 0x04107851, + 0x89829970, + 0x84d01a42, + 0x04107851, + 0x89849970, + 0x31521a44, + 0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x84a09722, + 0x84b09590, + 0x84c095a0, + 0x84d095b0, + 0x781095c0, + 0x90509030, + 0x90407820, + 0xb2359060, + 0x9170cd90, + 0xa2357000, + 0x7100b112, + 0xb112a0d2, + 0x81b0ba3c, + 0x39248b54, + 0x00043184, + 0xc11091b4, + 0x739166d0, + 0x66ca7291, + 0x72027206, + 0x73057204, + 0x607d7306, + 0xc8018630, + 0x04103151, + 0x70009630, + 0x89f09a00, + 0x46d12200, + 0x7000b9e0 +}; + +PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 363; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i]; + } +#else + const uint32_t *pS = patchIqdumpMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 45; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.h new file mode 100644 index 00000000..fc750eb6 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_iqdump.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Filename: rf_patch_mce_iqdump.h +* +* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_IQDUMP_H +#define _RF_PATCH_MCE_IQDUMP_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_iqdump(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.c new file mode 100644 index 00000000..6f16c9b5 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.c @@ -0,0 +1,411 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wb_dsss.h +* +* Description: RF core patch for WB-DSSS support for CC13x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_wb_dsss.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWbDsssMce[303] = { + 0x2fcf6076, + 0xdb3e0f9d, + 0x7f7f0303, + 0x00008080, + 0x00020001, + 0x00000003, + 0x000c0003, + 0x00cc000f, + 0x003c00c3, + 0xcccc0033, + 0x33cccc33, + 0x0f003333, + 0x04040f0f, + 0x02060305, + 0x00080107, + 0x000a0009, + 0x0c00000b, + 0x0a000b00, + 0x08000900, + 0x06020701, + 0x04040503, + 0x02020303, + 0x00000101, + 0x00000000, + 0x0c0c0000, + 0x0a0a0b0b, + 0x08080909, + 0x06060707, + 0x04040505, + 0x06060505, + 0x08080707, + 0x0a0a0909, + 0x00000b0b, + 0x00000000, + 0x00000000, + 0x02020101, + 0x00030303, + 0x001f0007, + 0x00000000, + 0x000f0400, + 0x03870000, + 0x48c80001, + 0x80000043, + 0x00800004, + 0x000006f0, + 0x0524091e, + 0x00070054, + 0x280a0000, + 0x00000028, + 0x7f7f001f, + 0x00000148, + 0x00000000, + 0x333c3c33, + 0x3cc3cccc, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x66587223, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xc7c0b008, + 0x8001a008, + 0x90010001, + 0x08019010, + 0x720d9001, + 0x720f720e, + 0xb0d07210, + 0xb1107100, + 0x721ba0d0, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60af6c01, + 0x60ca60b1, + 0x60af614a, + 0x60af60af, + 0x122060b0, + 0x121060a6, + 0x73117223, + 0x73137312, + 0x001081b1, + 0xb07091b0, + 0x60a5608d, + 0xc49160a5, + 0xc4e0c2b2, + 0x6f131820, + 0x16116e23, + 0x68b51612, + 0xc750c4f2, + 0x40c21820, + 0x6e231203, + 0x68bf1612, + 0x9c807840, + 0xb63c7272, + 0x94807860, + 0x60a59490, + 0x73127311, + 0x91f0c000, + 0x8c80c009, + 0x06703980, + 0xc0f41610, + 0xc036c0b5, + 0x44dc1e10, + 0xc008c077, + 0x60edc01e, + 0x44e21e20, + 0xc018c0b7, + 0x60edc03e, + 0x44e81e40, + 0xc038c0f7, + 0x60edc07e, + 0x44a31e80, + 0xc078c137, + 0x1062c0fe, + 0x10831612, + 0xe0301613, + 0x9a239a12, + 0x8190659d, + 0x81709640, + 0xb0e892c0, + 0xb1287100, + 0xb230a0e8, + 0xb003b630, + 0xb002b013, + 0xb0e0b012, + 0xb1207100, + 0x22f08170, + 0xc0f04503, + 0x84c092c0, + 0x71009640, + 0x84d0b120, + 0x71009640, + 0x84a0b120, + 0x71009640, + 0x84b0b120, + 0x81df9640, + 0x82106533, + 0x411f2210, + 0x10606119, + 0xc00f1620, + 0x69216533, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0x7223a002, + 0x061f60a5, + 0x00f9306f, + 0x04411091, + 0x898a9971, + 0x1091061a, + 0x99710451, + 0x061b898b, + 0x14ba311b, + 0x147a3919, + 0x71006fa3, + 0x9643b120, + 0x700092ce, + 0xc1f0b118, + 0x78509440, + 0x721e9450, + 0x39878c87, + 0x99770677, + 0x16188988, + 0x455a1e07, + 0x6165c006, + 0x455e1e17, + 0x6165c006, + 0x45621e37, + 0x6165c036, + 0x44a31e77, + 0x61a3c336, + 0x959084a0, + 0x95a084b0, + 0x95b084c0, + 0x95c084d0, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x90307810, + 0x78209050, + 0x90609040, + 0xb072b235, + 0x93f0c0b0, + 0xb0f6b136, + 0xb0737100, + 0xb136b127, + 0xb0e7a0f6, + 0x7100ba3e, + 0xb041b127, + 0xc0f0b061, + 0xba3f93f0, + 0x87208b14, + 0x31141404, + 0xa0449704, + 0xb1277100, + 0xb06db04d, + 0xb231b074, + 0xb1277100, + 0x9a007000, + 0x220089f0, + 0xb9e0459e, + 0xd0407000, + 0x659d9a17, + 0x6f10e471, + 0xc1009750, + 0xc7d2e481, + 0x6e236f13, + 0x16121611, + 0x1e0769ac, + 0x6566420e, + 0xb06fb04f, + 0xc004c0f5, + 0xb76065fe, + 0x39208780, + 0x49bf1c54, + 0x161491c0, + 0x1e018181, + 0x162141b8, + 0x4db81c41, + 0x797ea0e7, + 0x979e798f, + 0x120497af, + 0x8780b760, + 0x16143920, + 0x41d41c54, + 0x61cc91c0, + 0xc050a235, + 0xa0e7659d, + 0x7206a0e4, + 0x72047202, + 0x72047203, + 0x73067305, + 0x72917391, + 0x107060a5, + 0x71001209, + 0xba3db127, + 0x31838b63, + 0x20063d83, + 0x0bf341ee, + 0x69e51439, + 0x16293c89, + 0x1e893d29, + 0xc07949f7, + 0xc00361fc, + 0x1c391a83, + 0x10394dfc, + 0x700006f9, + 0xc29a65e3, + 0x6fab149a, + 0x149ac39a, + 0xc19a6fac, + 0x149a65e3, + 0x14db6fad, + 0x979c14dc, + 0x700097ab, + 0x659dc060, + 0xb04f6566, + 0xc0f5b06f, + 0x7100c004, + 0x7100b127, + 0x89acb127, + 0x979c89bb, + 0xb76097ab, + 0x39208780, + 0x4a231c54, + 0x161491c0, + 0x1e018181, + 0x16214215, + 0x4e151c41, + 0x797ea0e7, + 0x979e798f, + 0x120497af, + 0x8780b760, + 0x16143920, + 0x42381c54, + 0x623091c0, + 0xc070a235, + 0xa0e7659d, + 0x7206a0e4, + 0x72047202, + 0x72047203, + 0x73067305, + 0x72917391, + 0x000160a5, + 0x00080018, + 0x001a0003, + 0x002c000a, + 0x003e0011, + 0x00080003, + 0x001a0018, + 0x002c0011, + 0x003e000a, + 0xc8018630, + 0x04103151, + 0x70009630 +}; + +PATCH_FUN_SPEC void rf_patch_mce_wb_dsss(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 303; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWbDsssMce[i]; + } +#else + const uint32_t *pS = patchWbDsssMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 37; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.h new file mode 100644 index 00000000..fe9dc8fe --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wb_dsss.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wb_dsss.h +* +* Description: RF core patch for WB-DSSS support for CC13x2 +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WB_DSSS_H +#define _RF_PATCH_MCE_WB_DSSS_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_wb_dsss(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.c new file mode 100644 index 00000000..b388874c --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.c @@ -0,0 +1,602 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_ctmode.h +* +* Description: RF core patch for CC13x2 WMBUS C- and T-Mode +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_wmbus_ctmode.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWmbusCtmodeMce[500] = { + 0x2fcf60af, + 0xed0c3f9d, + 0x0acc0666, + 0x00ffabc2, + 0x003f0fff, + 0x05105555, + 0x002a0514, + 0x00042abc, + 0x00310018, + 0x00610047, + 0x0092007a, + 0x00ba00a8, + 0x00d000c7, + 0x00d600d4, + 0x001f0045, + 0x00e800f8, + 0x00c000d0, + 0x008800a8, + 0x00600078, + 0x00440057, + 0x00180031, + 0x00250004, + 0x05b205a2, + 0x05d305c3, + 0x05f405e3, + 0x06140604, + 0x06350625, + 0x06560646, + 0x06770666, + 0x06980687, + 0x06b806a8, + 0x06c906b8, + 0x06e906d9, + 0x070a06fa, + 0x0016071b, + 0x001c002c, + 0x000e0034, + 0x001a0026, + 0x000d0032, + 0x00190025, + 0x000b0031, + 0x00130023, + 0x00060029, + 0x0006000e, + 0x0002000e, + 0x00040008, + 0x0006000e, + 0x0006000a, + 0x0002000c, + 0x00040008, + 0x0006000c, + 0x0006000e, + 0x0002000e, + 0x0000000e, + 0x0006000e, + 0x0006000a, + 0x0002000e, + 0x0006000a, + 0x0007000e, + 0x0007000f, + 0x0003000d, + 0x00050009, + 0x0001000d, + 0x0007000f, + 0x0001000f, + 0x0005000f, + 0x0007000f, + 0x0007000b, + 0x0003000b, + 0x0007000b, + 0x0007000b, + 0x0007000f, + 0x0003000f, + 0x0007000f, + 0x0003000f, + 0x3d1f0007, + 0x00000000, + 0x000f0400, + 0x03840000, + 0x00f4000b, + 0x80000043, + 0x00280001, + 0x00000670, + 0x0514091e, + 0x00000004, + 0x44110200, + 0x0000006b, + 0x7223842f, + 0xa35d7263, + 0x7303a4e5, + 0x72037305, + 0x73067304, + 0x73917204, + 0xb0087291, + 0x9010ffc0, + 0x720da008, + 0x720f720e, + 0xb0d07210, + 0xb1107100, + 0x721ba0d0, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60e36c01, + 0x614f60e4, + 0x60e361a3, + 0x60e360e3, + 0x121060e3, + 0x73117223, + 0x73137312, + 0x001081b1, + 0xb07091b0, + 0x60d960c3, + 0xc2b2c951, + 0x1820c440, + 0x6e236f13, + 0x16121611, + 0xc4f268e8, + 0x1820c750, + 0x120340f5, + 0x16126e23, + 0x72ca68f2, + 0x95c078e0, + 0x819060d9, + 0x81709640, + 0x2a703980, + 0x16111001, + 0x84b484a2, + 0xc0f5c0f3, + 0x1c01c200, + 0xc100411d, + 0x41131c10, + 0x10134d15, + 0x18301803, + 0x1a101a13, + 0x69103912, + 0x13f3611d, + 0x13f3611d, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0e8691b, + 0xb1287100, + 0xb230a0e8, + 0xb003b630, + 0xb002b013, + 0x722cb012, + 0x7100b0e0, + 0x8170b120, + 0x710092c0, + 0x8170b120, + 0x452d22f0, + 0x1c0313f0, + 0x92c34139, + 0x71009642, + 0x92c5b120, + 0x71009644, + 0xb0e0b120, + 0x7000a630, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0xa230a002, + 0x73117000, + 0x8ca17312, + 0x39613981, + 0xd0300611, + 0x67e29a11, + 0x91f0c100, + 0x8ca064f9, + 0x458422e0, + 0xb113b633, + 0xb634b0d3, + 0x91f0c030, + 0xb0e1b121, + 0x22d58ca5, + 0x12f5416a, + 0x22308090, + 0x81d0457f, + 0xc4510850, + 0x6f121401, + 0x2252c063, + 0x12114177, + 0x13f16178, + 0xb12192f1, + 0x31127100, + 0x45731a13, + 0xa0e1616a, + 0xa0d3b121, + 0x60d96540, + 0xb630b0e0, + 0x92c0c070, + 0x964078d0, + 0x7100b120, + 0xa0e0b120, + 0xb633a630, + 0xb0d3b113, + 0xa0d37100, + 0x60d96540, + 0xd04087c1, + 0x67e29a11, + 0x72917391, + 0x72067263, + 0x72047202, + 0x73067305, + 0x123060d9, + 0x78c091e0, + 0xb35d93d0, + 0x7830b63c, + 0xb1189310, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x90307810, + 0x78209050, + 0x90609040, + 0x7293b445, + 0x72707291, + 0x93308cb0, + 0x93f0c030, + 0xb064b069, + 0xb116b089, + 0xb111a0d6, + 0xb112a0d1, + 0xb636b0d2, + 0x78ac786e, + 0xc00a67d3, + 0x13fb13ff, + 0x9930c1b0, + 0x9910c020, + 0x78ad7888, + 0xc024048d, + 0xc006c005, + 0xb112b235, + 0xba3d7100, + 0x46151e2a, + 0x39708cc0, + 0x140b311b, + 0x1ccb8240, + 0x222045e9, + 0x22204624, + 0xb91041ed, + 0xa91061ef, + 0x8ce0b111, + 0x08018cf1, + 0x41f82271, + 0x31163315, + 0x61dbc00a, + 0x41f41e3a, + 0x61db161a, + 0x22208240, + 0xb9104201, + 0xa9106203, + 0x8ce0b111, + 0x08018cf1, + 0x42112271, + 0x460d1e0a, + 0x33163115, + 0x3115620f, + 0xc00a3116, + 0x1e3a61db, + 0x161a420f, + 0x809061db, + 0x41fc2210, + 0x22c08ca0, + 0x10b14624, + 0x08d10481, + 0x89819971, + 0x4e031c41, + 0x67e2c050, + 0x72917293, + 0xb111a0d1, + 0xb231b3f2, + 0x99753135, + 0x3136898a, + 0x89899976, + 0x97aa189a, + 0x8af0ba39, + 0x3d803180, + 0x3d201620, + 0x1c80c0b8, + 0x12014fde, + 0x1c101881, + 0x8cb84be0, + 0xc1501808, + 0x1e4187a1, + 0xc0614a47, + 0xc00b1810, + 0x6727c00c, + 0x79da79c9, + 0xc10010a8, + 0x87a11808, + 0x4e5b1e11, + 0x46641e01, + 0x4e6418b9, + 0x10c510b5, + 0x4a641ca5, + 0x1a89626d, + 0x18b9108a, + 0x10b54e7d, + 0x1ca518c5, + 0x626d4a7d, + 0x18c07ab0, + 0x10c54e7d, + 0xc00018b5, + 0x4a7d1c05, + 0xc0fc6275, + 0x670ac0d0, + 0x1ac510d5, + 0x185d120d, + 0x10cb627f, + 0xc0d0c1ec, + 0x10d5670a, + 0x185d120d, + 0xc00d627f, + 0xa636627f, + 0x67b4a790, + 0xc00ac00b, + 0xc007c006, + 0x8ca0c009, + 0x468b22d0, + 0x78787899, + 0x78ad048e, + 0xc010048d, + 0xb9149930, + 0x9910c2b0, + 0xb111b116, + 0xb089b069, + 0x7100b112, + 0x1e2aba3d, + 0x8cc046a5, + 0x311b3970, + 0x048b140b, + 0x42c91ceb, + 0x809062b5, + 0x46ab2260, + 0x46c02210, + 0xc03062b1, + 0xb1169910, + 0xc1c0b111, + 0x1cdb9930, + 0xa91046b5, + 0x8ce0b910, + 0x08018cf1, + 0x42bc2271, + 0x62bf120a, + 0x42ba1e3a, + 0x6298161a, + 0xc0607223, + 0x7100b112, + 0x87b16ac2, + 0x97b11611, + 0xba3961b8, + 0x161a7291, + 0xc00b78d4, + 0xb074c00e, + 0xb112b133, + 0xba3d7100, + 0x46e21e2a, + 0x39708cc0, + 0x140b311b, + 0x1e6e161e, + 0x1c4b46f7, + 0xc0164342, + 0x62f7c00e, + 0x42ec1066, + 0x089bc550, + 0x6f0114b0, + 0xc00691c1, + 0x62f7c017, + 0x42f71077, + 0xc00b164f, + 0x8180c007, + 0x42f71e00, + 0x4ef71cf0, + 0x8ce06302, + 0x08018cf1, + 0x42fe2271, + 0x62d1c00a, + 0x42fc1e3a, + 0x62d1161a, + 0xa0d2a235, + 0xa0d1b112, + 0xb133b111, + 0x619667d3, + 0xc0011a10, + 0x6fcdc0c2, + 0x10b3161c, + 0x1051671f, + 0x6fcd1a10, + 0x671f161c, + 0x4b1a1c15, + 0x631d6b13, + 0x10021051, + 0x102d6b13, + 0x1cd37000, + 0x10354b24, + 0x700018d5, + 0x183510d5, + 0xb1127000, + 0xba3e7100, + 0x10128ac1, + 0x12014f2f, + 0x31311821, + 0x4f331c1b, + 0x8ad1101b, + 0x4f381012, + 0x18211201, + 0x1c1c3131, + 0x101c4f3c, + 0x1c20c172, + 0x93384f40, + 0x70006b27, + 0x7291b133, + 0x9930c070, + 0x78b09910, + 0x67d393d0, + 0x7100b112, + 0x223080b0, + 0x80904753, + 0x47532210, + 0xb073634a, + 0xa932a910, + 0x727cb910, + 0x1a11c001, + 0x435f1c1f, + 0x1cf0c040, + 0xb0114b60, + 0x31808af0, + 0x97003d80, + 0x8c618c50, + 0xa637a638, + 0x1801c022, + 0x4f741c21, + 0x4b721412, + 0x1c016375, + 0x4f744375, + 0x6375b637, + 0xa04eb638, + 0xb061b041, + 0xb133b790, + 0x223080b0, + 0xb0d14779, + 0xa0d2b111, + 0xb133b112, + 0xb04e7100, + 0xc090a910, + 0x99303120, + 0x91e01300, + 0xb111b910, + 0x72917100, + 0xb0d6b116, + 0xa0d1b111, + 0x1a101200, + 0xc3809930, + 0xc2809910, + 0x80909910, + 0x44c32200, + 0x1e048184, + 0x99344399, + 0x8940b116, + 0x1c018931, + 0x18014bb1, + 0x4baf1ef1, + 0x1af18931, + 0x71009931, + 0x16f1b116, + 0xa2359931, + 0xb1167100, + 0x6196a0d6, + 0xc2c197cd, + 0x141d16c1, + 0x101d6fd1, + 0x83103151, + 0xc1f23980, + 0x14010420, + 0x836298d1, + 0x06711021, + 0x06323952, + 0x16311421, + 0x3010c1b0, + 0xc07098e0, + 0x930d6bcc, + 0x965088f0, + 0x96608900, + 0x89907000, + 0x47d81e00, + 0x99908650, + 0x78409650, + 0x78509300, + 0x70009660, + 0x623f1080, + 0x623f1010, + 0x89f09a00, + 0x47e32200, + 0x7000b9e0 +}; + +PATCH_FUN_SPEC void rf_patch_mce_wmbus_ctmode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 500; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWmbusCtmodeMce[i]; + } +#else + const uint32_t *pS = patchWmbusCtmodeMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 62; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.h new file mode 100644 index 00000000..8e8f9948 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_ctmode.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_ctmode.h +* +* Description: RF core patch for CC13x2 WMBUS C- and T-Mode +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WMBUS_CTMODE_H +#define _RF_PATCH_MCE_WMBUS_CTMODE_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_wmbus_ctmode(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.c new file mode 100644 index 00000000..9fd743ae --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.c @@ -0,0 +1,569 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_smode.h +* +* Description: RF core patch for CC13x2 WMBUS S-Mode +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include +#include "rf_patch_mce_wmbus_smode.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef MCE_PATCH_TYPE +#define MCE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_MCERAM_BASE +#define RFC_MCERAM_BASE 0x21008000 +#endif + +#ifndef MCE_PATCH_MODE +#define MCE_PATCH_MODE 0 +#endif + +MCE_PATCH_TYPE patchWmbusStmodeMce[473] = { + 0x2fcf6042, + 0x030c3f9d, + 0x070c680a, + 0x003f0002, + 0x8080ff00, + 0x0014002a, + 0x00160006, + 0x001c002c, + 0x000e0034, + 0x001a0026, + 0x000d0032, + 0x00190025, + 0x000b0031, + 0x00130023, + 0x00000029, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x00828000, + 0x06700080, + 0x091e0000, + 0x00040510, + 0x02000005, + 0x00613e10, + 0x002f0000, + 0x027f3030, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0000aa00, + 0x67a57223, + 0xa4e5a35d, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xfff0b008, + 0x90103120, + 0x720da008, + 0x720f720e, + 0xb0d07210, + 0xb1107100, + 0x721ba0d0, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60786c01, + 0x60fd6079, + 0x607862f9, + 0x60786078, + 0x12106078, + 0x73117223, + 0x73137312, + 0x81b17314, + 0x91b00010, + 0x6057b070, + 0xc030606d, + 0xc1e167ab, + 0xc4e0c2b2, + 0x6f131820, + 0x16116e23, + 0x687f1612, + 0x9c807830, + 0x9c907840, + 0x9ca07850, + 0x97907860, + 0x94807890, + 0x83309490, + 0xc5129cb0, + 0x1820c750, + 0x12034099, + 0x16126e23, + 0x78c06896, + 0x72639990, + 0x606db63c, + 0x96408190, + 0x39808170, + 0x10012a70, + 0x84a21611, + 0xc0f384b4, + 0xc200c0f5, + 0x40c21c01, + 0x1c10c100, + 0x4cba40b8, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60c268b5, + 0x60c213f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68c03914, + 0x7100b0e8, + 0xa0e8b128, + 0xb910b230, + 0x99308990, + 0xb0d1b111, + 0xb0027100, + 0xb111b012, + 0x7291a0d1, + 0xb003b630, + 0x722cb013, + 0x7100b0e0, + 0x8170b120, + 0x710092c0, + 0x8170b120, + 0x44db22f0, + 0x1c0313f0, + 0x92c340e7, + 0x71009642, + 0x92c5b120, + 0x71009644, + 0xb0e0b120, + 0x7000a630, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0xa230a002, + 0x73117000, + 0x87917312, + 0xd0400631, + 0x67ab9a11, + 0x91f0c100, + 0xb633649e, + 0x06308790, + 0x41541e10, + 0x412f1e20, + 0xb0d3b113, + 0xc030b634, + 0xb12191f0, + 0xc005b0e1, + 0x22d08ca0, + 0x12f5411a, + 0x22308090, + 0x81d0454f, + 0xc0d10850, + 0x6f121401, + 0x2252c063, + 0x12114127, + 0x13f16128, + 0xb12192f1, + 0x31127100, + 0x45231a13, + 0xb113611a, + 0xb634b0d3, + 0x91f0c000, + 0xb0e1b121, + 0x39858ca5, + 0x06153955, + 0x22308090, + 0x81d0454f, + 0x06100850, + 0x13f04144, + 0x61461211, + 0x13f11210, + 0x101b100a, + 0xb12192f0, + 0x92f17100, + 0x7100b121, + 0xa0e1613a, + 0xa0d3b121, + 0x606d64ee, + 0xb630b0e0, + 0x92c0c070, + 0x964078a0, + 0x7100b120, + 0xa0e0b120, + 0xb633a630, + 0xb0d3b113, + 0xa0d37100, + 0x606d64ee, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78728440, + 0x81730420, + 0x2a733983, + 0xc1f294e3, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309440, + 0x39301610, + 0x41812210, + 0x31501220, + 0x31801003, + 0x93801630, + 0x12041202, + 0x41932273, + 0x997084a0, + 0x1a828982, + 0x997084c0, + 0x1a848984, + 0x22636195, + 0x84b041a0, + 0x89809970, + 0x14021a80, + 0x997084d0, + 0x1a808980, + 0x61ac1404, + 0x788184b0, + 0x99700410, + 0x1a428982, + 0x788184d0, + 0x99700410, + 0x1a448984, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x97220042, + 0x959084a0, + 0x95a084b0, + 0x95b084c0, + 0x95c084d0, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8cb2b235, + 0x93328333, + 0x9a12e050, + 0x67ab9a23, + 0xc00bc00c, + 0x720e720d, + 0xb121720f, + 0x7100b0e1, + 0xa0e1b072, + 0xb06ea04e, + 0xb06cb011, + 0x7291993a, + 0xa914b914, + 0x9912c662, + 0xc028c04f, + 0x7100667a, + 0xb910b073, + 0x220780b7, + 0xa910461c, + 0x22f18c81, + 0x223741f6, + 0xb13341f6, + 0x223080b0, + 0x620445f1, + 0x420922e1, + 0x22508090, + 0xb1154209, + 0x22208240, + 0x993941e5, + 0xa914b914, + 0x61e5b116, + 0xb914993d, + 0xb116a914, + 0x8ca061e5, + 0x421522f0, + 0x42152237, + 0xb133b075, + 0x223080b0, + 0xb087460f, + 0x22d161e5, + 0x809042bd, + 0x42bd2220, + 0x61e56640, + 0xa009993f, + 0xa0f0a008, + 0xa0d2a0f3, + 0xb111a0d5, + 0xa0d6b0d1, + 0x99387100, + 0xba3fb111, + 0x87208b11, + 0x97011801, + 0x8c418c30, + 0xa637a638, + 0x22e08ca0, + 0x82404238, + 0x45d02220, + 0xb04e7100, + 0xb074b06e, + 0x8c43b231, + 0x70008702, + 0x22b08c80, + 0x1e3b4646, + 0x62484678, + 0x46781e7b, + 0xba39c00b, + 0x31808af0, + 0x16403d80, + 0x140c3d30, + 0x220080b0, + 0x70004254, + 0x39838c83, + 0x8c8106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004e70, + 0x1c0c1810, + 0x80b04a72, + 0x42652200, + 0x10c27000, + 0x3c321612, + 0x83508cb1, + 0x42742210, + 0x93316276, + 0x7000b112, + 0x6261101c, + 0x6261100c, + 0x626d1821, + 0x626d1421, + 0x626e161b, + 0xb111b116, + 0xb133b130, + 0xb112b115, + 0x720e720d, + 0xb0f0720f, + 0x8c82b0f3, + 0x428b22f2, + 0xb913b0d6, + 0x8ca0628e, + 0x42ae22f0, + 0xa444b445, + 0xa469b468, + 0x3180caa0, + 0x0001caa1, + 0x94d194c1, + 0x31838ca3, + 0x84503983, + 0x39803180, + 0x00303183, + 0x84409450, + 0x39503150, + 0x39838ca3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899440, + 0x42b822e2, + 0x394a8c9a, + 0x312a398a, + 0xb0d5993a, + 0xb913b0d6, + 0x22d28c82, + 0xb0d242bc, + 0xb23f7000, + 0xa0f3a0f0, + 0xb914993e, + 0xb116a914, + 0xb133b130, + 0x22f08240, + 0xb11542c6, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x67abc060, + 0xb9147100, + 0xb0d5b116, + 0x7100a23f, + 0xa0d5b115, + 0x90307810, + 0x78209002, + 0x90609040, + 0xa23fb072, + 0x993a667a, + 0xb116a914, + 0xba3c61e5, + 0x8b5481b0, + 0x31843924, + 0x91b40004, + 0x67abc070, + 0x72917391, + 0x720667a5, + 0x72047202, + 0x73067305, + 0x8240606d, + 0x47012230, + 0x7100b0d5, + 0xa0d5b115, + 0x8c8162f9, + 0x430a22c1, + 0x67abc080, + 0xb008b009, + 0xb018b019, + 0x91e01200, + 0xc090b35d, + 0xb11867ab, + 0xb1116566, + 0xba3eb0d1, + 0xe0a08c43, + 0x9a229a13, + 0x710067ab, + 0xb111a0d1, + 0xb0d2b112, + 0x120ac00f, + 0x1a1f120f, + 0x12031204, + 0x39888ca8, + 0x06183958, + 0xb1127100, + 0x8ce0ba3d, + 0x3d803180, + 0x6334100b, + 0x121a120b, + 0x16131a14, + 0xb1127100, + 0x8ce0ba3d, + 0x3d803180, + 0x7100140b, + 0xba3db112, + 0x31808ce0, + 0x140b3d80, + 0x7100100d, + 0xba3db112, + 0x31808ce0, + 0x140b3d80, + 0x100c140d, + 0x4f5122fd, + 0x120d10d0, + 0x7100180d, + 0xba3db112, + 0x31808ce0, + 0x180b3d80, + 0x100e140c, + 0x4f5f22fc, + 0x120c10c0, + 0x7100180c, + 0xba3db112, + 0x31808ce0, + 0x180b3d80, + 0x22fe140e, + 0x10e04f6c, + 0x180e120e, + 0xb1127100, + 0x8ce0ba3d, + 0x3d803180, + 0x7100180b, + 0xba3db112, + 0x31808ce0, + 0x180b3d80, + 0x398b10b6, + 0x088b397b, + 0x161f91cb, + 0x1e008180, + 0x1a104387, + 0x4f871cf0, + 0x67996392, + 0x43911e1a, + 0x43301e4a, + 0xb1127100, + 0x1614121a, + 0x63281613, + 0x9a13e0b0, + 0x67ab9a24, + 0xb112a0d2, + 0xc01a62e7, + 0x140d78b0, + 0x1cec140e, + 0xc03a4ba1, + 0x1cdc10ec, + 0xc04a4ba4, + 0x86307000, + 0x3151c801, + 0x96300410, + 0x9a007000, + 0x220089f0, + 0xb9e047ac, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_mce_wmbus_smode(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 473; i++) { + HWREG(RFC_MCERAM_BASE + 4 * i) = patchWmbusStmodeMce[i]; + } +#else + const uint32_t *pS = patchWmbusStmodeMce; + volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 59; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + *pD++ = t1; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.h new file mode 100644 index 00000000..7a728ccd --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_mce_wmbus_smode.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* Filename: rf_patch_mce_wmbus_smode.h +* +* Description: RF core patch for CC13x2 WMBUS S-Mode +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef _RF_PATCH_MCE_WMBUS_SMODE_H +#define _RF_PATCH_MCE_WMBUS_SMODE_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_mce_wmbus_smode(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.c new file mode 100644 index 00000000..dfc0e085 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.c @@ -0,0 +1,617 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ble_coex.h +* +* Description: RF core patch for coexistence support for Bluetooth 5 in CC13x2 and CC26x2. +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#include +#include "rf_patch_rfe_ble_coex.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchBleCoexRfe[510] = { + 0x35f86145, + 0xa24675f9, + 0x1f40a357, + 0x34f11307, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x6fcf7fcf, + 0x4fcf5fcf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x403b2241, + 0x700006f1, + 0x9150c050, + 0xc0707000, + 0x70009150, + 0x00213182, + 0xb1609181, + 0x10257000, + 0x9100c050, + 0xc080c3f4, + 0x6f031420, + 0x04411031, + 0x22f082a0, + 0x26514058, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92551405, + 0x642b7000, + 0x1031c2b2, + 0x31610631, + 0x642e02c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x7000642e, + 0x82b16428, + 0x39813181, + 0x642ec0e2, + 0xc111642b, + 0x642ec122, + 0x688bc470, + 0xc0c2c111, + 0x64a4642e, + 0x700064b7, + 0x82b16440, + 0x39813181, + 0x6446c182, + 0xc1116443, + 0x6446c0a2, + 0x689dc470, + 0xc162c331, + 0x64a46446, + 0x700064b7, + 0xb054b050, + 0x80407100, + 0x44b12240, + 0x40a42200, + 0x8081b060, + 0x44a41e11, + 0xa0547000, + 0x80f0b064, + 0x40a42200, + 0x12407000, + 0xb03290b0, + 0x395382a3, + 0x64713953, + 0x68bfc2f0, + 0xc1f18080, + 0xc1510410, + 0x40cb1c10, + 0xc221642b, + 0x642ec0c2, + 0x644360cf, + 0xc162c441, + 0xce306446, + 0x128068d0, + 0xb03290b0, + 0x642b7000, + 0xc0c2c201, + 0x80a0642e, + 0x39403180, + 0xc10168dc, + 0x642ec0c2, + 0xc122c101, + 0x82a3642e, + 0x12c06471, + 0xb03290b0, + 0x64437000, + 0xc162c401, + 0x80a06446, + 0x39403180, + 0xc30168f0, + 0x6446c162, + 0xc0a2c101, + 0x82a36446, + 0x12c06471, + 0xb03290b0, + 0x642b7000, + 0xc081c272, + 0xc122642e, + 0x642ec111, + 0xc111c002, + 0xc062642e, + 0x642ec331, + 0xc111c362, + 0xc302642e, + 0x642ec111, + 0x395382a3, + 0xc3e26471, + 0x22116433, + 0xc2424113, + 0x642ec881, + 0xc111c252, + 0xc272642e, + 0x642ecee1, + 0xc881c202, + 0xc202642e, + 0x642ec801, + 0x6927c170, + 0x642b7000, + 0xc801c242, + 0xc252642e, + 0x642ec011, + 0xc0e1c272, + 0xc002642e, + 0x642ec101, + 0xc301c062, + 0xc122642e, + 0x642ec101, + 0xc101c362, + 0xc302642e, + 0x642ec101, + 0x647182a3, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0xeff08092, + 0x93529341, + 0x224167f5, + 0x80804569, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x618a618a, + 0x618a618a, + 0x618a618a, + 0x6191618d, + 0x619b6197, + 0x62b5618a, + 0xc0f062b8, + 0x31320402, + 0x14122a41, + 0x11011632, + 0x6c011421, + 0x618b61a9, + 0x618f61a9, + 0x61936199, + 0x618a618a, + 0x619d62d6, + 0x618f62d6, + 0x6193619f, + 0x618a618a, + 0x618b61af, + 0x618f61af, + 0x61936199, + 0x618a618a, + 0x65c061a2, + 0x648061a2, + 0x648061a2, + 0x64d567cd, + 0x649261a2, + 0x64e967cd, + 0x64fd61a2, + 0x64fd61a2, + 0x652965c0, + 0x66e061a2, + 0x64fd61a2, + 0x619b66e0, + 0x61a5b0b0, + 0x7306b0b1, + 0xb0307205, + 0x78106149, + 0x7832c451, + 0xc5247853, + 0x782061b4, + 0x7842c451, + 0xc4c47853, + 0x926091a4, + 0x92829271, + 0xc0159293, + 0xc3f09245, + 0xc0f092b0, + 0x61a290a0, + 0x66b1b0e3, + 0x80f0a054, + 0x45ca2250, + 0x22008040, + 0x61c246a9, + 0xc800a0e3, + 0x81a991b0, + 0x8091b050, + 0x46842241, + 0x12f18262, + 0x102f0412, + 0x142f311f, + 0x22d68266, + 0xc08045dd, + 0xc18061de, + 0x6f0d1420, + 0x10de396d, + 0x044ec3f4, + 0x3182c082, + 0x396d002e, + 0x3182c0a2, + 0x826a002d, + 0x06fa398a, + 0x31808270, + 0xc00b3980, + 0x10bc180b, + 0x825318ac, + 0x149b1439, + 0x06f08260, + 0x31101001, + 0x81a11410, + 0x140c1410, + 0x39408280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x22c691e1, + 0xb0034642, + 0xb063b013, + 0x8041b053, + 0x46a92201, + 0x92148204, + 0x1cb58225, + 0x18954e21, + 0x80f091b5, + 0x42132210, + 0x913d6284, + 0x913eb110, + 0x80e0b110, + 0x462b2200, + 0x422b22e6, + 0x1895b0e0, + 0x925f91b5, + 0x14f981a9, + 0x225080f0, + 0x221041c0, + 0x62bb4684, + 0x81a966b1, + 0x14598255, + 0x7100c0f0, + 0x6a3bb063, + 0x421322c6, + 0x625aa0e0, + 0x39808280, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x828791d1, + 0x39873947, + 0xb013b003, + 0xb053b063, + 0xb0637100, + 0xb012b002, + 0x22018041, + 0x81f446a9, + 0x82259214, + 0x4e681cb5, + 0x91b51895, + 0x221080f0, + 0x6284425a, + 0x92148204, + 0x18458224, + 0x4e721c75, + 0x221080f0, + 0x6284425a, + 0xb110913d, + 0x220080e0, + 0x22e6467a, + 0xb0e0427a, + 0x925f91b5, + 0x14f981a9, + 0x225080f0, + 0x221041c0, + 0x62bb4684, + 0x8280b063, + 0x100206f0, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb01391e1, + 0xb063b003, + 0xb064b053, + 0x7100b054, + 0x22018041, + 0xb06346a9, + 0x80f0b064, + 0x41c02250, + 0x46972240, + 0x92118201, + 0x18918221, + 0xb03191b1, + 0xa0e36297, + 0x8251a0e0, + 0x318281b2, + 0xa0033d82, + 0x82627000, + 0x06f23942, + 0x80a2604b, + 0x61a2644b, + 0x7100b050, + 0x829061a2, + 0x22018041, + 0x820446a9, + 0x82259214, + 0x91b51895, + 0x221180f1, + 0x6abc4684, + 0x22018041, + 0x820446a9, + 0x82259214, + 0x4a361cc5, + 0x91b51895, + 0x221080f0, + 0x628442c8, + 0x91e07860, + 0x9250c2d0, + 0x7870c4c4, + 0xc132c2e1, + 0x61b4cb03, + 0xb0e3a0e2, + 0x80f0a054, + 0x46ea2250, + 0x22008040, + 0x62e247c6, + 0xa040a0e3, + 0x8260827d, + 0x0410c0f1, + 0x826a1009, + 0x041a394a, + 0x39808260, + 0x100e0410, + 0x10bc10ab, + 0x644b10c2, + 0xb003b013, + 0xb053677a, + 0xb054b050, + 0xb013b064, + 0x6763675a, + 0x80417100, + 0x47c62201, + 0x221080f0, + 0x22f04716, + 0xb06447b3, + 0x43062231, + 0x6780b063, + 0x63066733, + 0x81bfb064, + 0x3d8f318f, + 0x80417100, + 0x47c62201, + 0x80f0b064, + 0x432c2250, + 0x8261b063, + 0x472722c1, + 0x82616780, + 0x471a22d1, + 0x631a6733, + 0x81c281b1, + 0x3d813181, + 0x3d823182, + 0x820062e0, + 0x82239210, + 0x4f4018d3, + 0x16130bf3, + 0x4b591ce3, + 0x82339213, + 0x6345143b, + 0x4b591ce3, + 0x82339213, + 0x1cab183b, + 0x1c9b4f55, + 0x1cbc4b57, + 0x10b24359, + 0x22d08260, + 0x80f04352, + 0x47592210, + 0x675a644b, + 0x10ab6359, + 0x109b6349, + 0x70006349, + 0xc0f18280, + 0xb0630410, + 0x6b5d7100, + 0xb0e010bc, + 0x82027000, + 0x82229212, + 0x18128251, + 0x181281a1, + 0x31818291, + 0x1c123d81, + 0xb0e24b71, + 0xc7f1b032, + 0x4f751421, + 0x91b2c812, + 0xb03191c2, + 0x7000b0e1, + 0xc0061208, + 0x91b0c800, + 0x700091c0, + 0x82008251, + 0x82209210, + 0x81a11810, + 0x14061810, + 0x829280e1, + 0x3d823182, + 0x4b921c20, + 0x2221b0e2, + 0xb0324796, + 0x43962221, + 0xb032a0e2, + 0x39418281, + 0x0401c0f0, + 0x43a41e01, + 0xc0101618, + 0x1c083010, + 0x106047b2, + 0x10063c10, + 0x1461c7f1, + 0xc8164fa8, + 0x81c191b6, + 0x3d813181, + 0x4baf1c16, + 0xb03191c6, + 0x1208c006, + 0xa0037000, + 0xb064b063, + 0x6529b0ef, + 0x80407100, + 0x47c62200, + 0x64fdb064, + 0x7100a0ef, + 0x22008040, + 0xb06447c6, + 0x6306b003, + 0x8251a0e3, + 0x318281b2, + 0xa0033d82, + 0x642b7000, + 0xb05fb06f, + 0x1e118081, + 0xb05043ee, + 0x7100b054, + 0x22f08040, + 0xb06f43e6, + 0x22f282b2, + 0xc40143e6, + 0x6446c162, + 0xc0c2c201, + 0xa05f642e, + 0x63eeb06f, + 0x22408040, + 0xa05443f1, + 0x80f1b064, + 0x47d32201, + 0xb06fa05f, + 0x22007000, + 0xb06043d3, + 0x933063d0, + 0x22008320, + 0xb31047f6, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_ble_coex(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 510; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchBleCoexRfe[i]; + } +#else + const uint32_t *pS = patchBleCoexRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 63; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.h new file mode 100644 index 00000000..7330815e --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_ble_coex.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_ble_coex.h +* +* Description: RF core patch for coexistence support for Bluetooth 5 in CC13x2 and CC26x2. +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_BLE_COEX_H +#define _RF_PATCH_RFE_BLE_COEX_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_rfe_ble_coex(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.c new file mode 100644 index 00000000..6fd9e308 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.c @@ -0,0 +1,492 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genook.h +* +* Description: RF core patch for General OOK support in CC13x2 and CC26x2. +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#include +#include "rf_patch_rfe_genook.h" +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#ifndef RFE_PATCH_TYPE +#define RFE_PATCH_TYPE static const uint32_t +#endif + +#ifndef PATCH_FUN_SPEC +#define PATCH_FUN_SPEC +#endif + +#ifndef RFC_RFERAM_BASE +#define RFC_RFERAM_BASE 0x2100C000 +#endif + +#ifndef RFE_PATCH_MODE +#define RFE_PATCH_MODE 0 +#endif + +RFE_PATCH_TYPE patchGenookRfe[383] = { + 0x00006122, + 0x11011000, + 0x004d1203, + 0x002e24f1, + 0x0a940018, + 0x003ffffe, + 0x00ff007f, + 0x000003ff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40300000, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x00000fcf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x406d2241, + 0x700006f1, + 0xc0501025, + 0xc3f49100, + 0x1420c2b0, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009255, + 0xc2b2645d, + 0x06311031, + 0x02c13161, + 0xc1126460, + 0x39211031, + 0x31510671, + 0x646002e1, + 0x645d7000, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0xc11140a4, + 0x6460c122, + 0x82b1645a, + 0x39813181, + 0x6460c0e2, + 0x68b5c300, + 0x1240645d, + 0xb03290b0, + 0x395382a3, + 0x64943953, + 0x68bfc360, + 0x90b01280, + 0x7000b032, + 0xc101645d, + 0x6460c122, + 0xc0c2c101, + 0x82a36460, + 0x12c06494, + 0xb03290b0, + 0x645d7000, + 0xc081c272, + 0xc1226460, + 0x6460c111, + 0xc111c002, + 0xc0626460, + 0x6460c331, + 0xc111c362, + 0xc3026460, + 0x6460c111, + 0x395382a3, + 0xc3e26494, + 0x22116465, + 0xc24240e7, + 0x6460c881, + 0xc111c252, + 0xc2726460, + 0x6460cee1, + 0xc881c202, + 0xc2026460, + 0x6460c801, + 0x68fbc170, + 0x645d7000, + 0xc801c242, + 0xc2526460, + 0x6460c011, + 0xc0e1c272, + 0xc0026460, + 0x6460c101, + 0xc301c062, + 0xc1226460, + 0x6460c101, + 0xc101c362, + 0xc3026460, + 0x6460c101, + 0x649482a3, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x224180a2, + 0x80804543, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x615e615e, + 0x615e615e, + 0x615e615e, + 0x615e615e, + 0x615e615e, + 0x615e615e, + 0x809162d5, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x617b616e, + 0x62d5616e, + 0x615e615f, + 0x615e615e, + 0x617b616e, + 0x62d5616e, + 0x615e615f, + 0x615e615e, + 0x64d16163, + 0x64fd657b, + 0x12106163, + 0x616690b0, + 0x9050c010, + 0x906078a0, + 0x1210720e, + 0x61269030, + 0x91a07850, + 0x92607860, + 0x92707870, + 0x92807880, + 0x92907890, + 0x90a0c1a0, + 0xa0bc6163, + 0xb060a0e1, + 0x80f0a054, + 0x45862250, + 0x22008040, + 0x617d46a2, + 0x66f7cff0, + 0x393080f0, + 0x22100630, + 0x7841418f, + 0x22006194, + 0x78314193, + 0x78216194, + 0x827d91e1, + 0x39408280, + 0x0410c0f1, + 0xc0121007, + 0x82693072, + 0x0419c0f1, + 0xc0f1826a, + 0x041a394a, + 0xc0f1826e, + 0x041e398e, + 0x10bc10ab, + 0x647210c2, + 0x78e7c00f, + 0xb003b013, + 0xb0536646, + 0xb013b050, + 0xc082661c, + 0x662d6682, + 0xb0637100, + 0x22018041, + 0x80f046a2, + 0x41b82250, + 0x45b82210, + 0x46c022f0, + 0x6682c082, + 0x392010f0, + 0x82239210, + 0x1030664c, + 0x4dd618d3, + 0x16130bf3, + 0x49ea1ce3, + 0x82339213, + 0x61db143b, + 0x49ea1ce3, + 0x82339213, + 0x1cab183b, + 0x1c9b4e29, + 0x1cbc4a2b, + 0x10b241ea, + 0x22d08260, + 0x80f041e8, + 0x45ea2210, + 0x65eb6472, + 0x10c061b8, + 0x49fd18b0, + 0x39101003, + 0x41f41e00, + 0x3807380f, + 0x420d2203, + 0x392010f0, + 0x1070180f, + 0x18073920, + 0x1003620d, + 0x1801c001, + 0x1e013911, + 0x301f4205, + 0x22033017, + 0x10f0420d, + 0x140f3920, + 0x39201070, + 0x66991407, + 0x06f08280, + 0x80f13110, + 0x06313931, + 0x42171e01, + 0xb0633810, + 0x6a177100, + 0x700010bc, + 0x06f08280, + 0x80f13110, + 0x06313931, + 0x42251e01, + 0xb0633810, + 0x6a257100, + 0x10ab7000, + 0x109b61df, + 0x10f261df, + 0x92123922, + 0x82518222, + 0x81a11812, + 0x82911812, + 0x3d813181, + 0x4a3e1c12, + 0xb032b0e1, + 0x66f7cfe0, + 0x1421c7f1, + 0xc8124e42, + 0x91c291b2, + 0x7000b031, + 0xc0061208, + 0x91b0c800, + 0x700091c0, + 0x10308251, + 0x81a11810, + 0x14061810, + 0x829280e1, + 0x3d823182, + 0x4a5e1c20, + 0x46682211, + 0xb032b0e1, + 0x66f7cfd0, + 0x42682211, + 0x1c201a32, + 0xa0e14e68, + 0xdfc0b032, + 0x66f79342, + 0x39418281, + 0x1e0106f1, + 0x16184273, + 0x3010c010, + 0x46811c08, + 0xc7f13c16, + 0x4e771461, + 0x91b6c816, + 0x318181c1, + 0x1c163d81, + 0x91c64a7e, + 0xc006b031, + 0x70001208, + 0x31238203, + 0x187110f1, + 0x10153c21, + 0x4e8b1c37, + 0x1037628d, + 0x1417628e, + 0x4a911c3f, + 0x103f6293, + 0x1e016299, + 0x12114696, + 0x42991e0f, + 0x10f1181f, + 0x39311471, + 0x063080e0, + 0x14103121, + 0x700090e0, + 0x81b28251, + 0x3d823182, + 0x9341efb0, + 0x66f79352, + 0x64fda003, + 0x81b16163, + 0x3d813181, + 0x39808290, + 0x1cf11801, + 0x14014abf, + 0x22c080b0, + 0xb0bc46bf, + 0xefa0b033, + 0x935f9341, + 0x700066f7, + 0xb063a003, + 0xb054b064, + 0x64fdb0e0, + 0x80407100, + 0x46a22200, + 0x64d1b064, + 0x7100a0e0, + 0x22008040, + 0xb06446a2, + 0xb003a054, + 0xcf9061b8, + 0x64a366f7, + 0xb054b0e1, + 0xb064645d, + 0x80f07100, + 0x46f22240, + 0x42e32210, + 0xc20162ee, + 0x6460c0c2, + 0x318080a0, + 0x6ae93940, + 0xc0c2c101, + 0x62db6460, + 0xc0c2c331, + 0x62db6460, + 0xcf80a054, + 0x64c466f7, + 0x93306163, + 0x22008320, + 0xb31046f8, + 0x00007000 +}; + +PATCH_FUN_SPEC void rf_patch_rfe_genook(void) +{ +#ifdef __PATCH_NO_UNROLLING + uint32_t i; + for (i = 0; i < 383; i++) { + HWREG(RFC_RFERAM_BASE + 4 * i) = patchGenookRfe[i]; + } +#else + const uint32_t *pS = patchGenookRfe; + volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); + uint32_t t1, t2, t3, t4, t5, t6, t7, t8; + uint32_t nIterations = 47; + + do { + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + t8 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; + *pD++ = t8; + } while (--nIterations); + + t1 = *pS++; + t2 = *pS++; + t3 = *pS++; + t4 = *pS++; + t5 = *pS++; + t6 = *pS++; + t7 = *pS++; + *pD++ = t1; + *pD++ = t2; + *pD++ = t3; + *pD++ = t4; + *pD++ = t5; + *pD++ = t6; + *pD++ = t7; +#endif +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.h b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.h new file mode 100644 index 00000000..5c10034f --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rf_patches/rf_patch_rfe_genook.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* Filename: rf_patch_rfe_genook.h +* +* Description: RF core patch for General OOK support in CC13x2 and CC26x2. +* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the ORGANIZATION nor the names of its contributors may +* be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +#ifndef _RF_PATCH_RFE_GENOOK_H +#define _RF_PATCH_RFE_GENOOK_H + +#include +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +extern void rf_patch_rfe_genook(void); + +#endif diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rom/driverlib.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rom/driverlib.c new file mode 100644 index 00000000..7cd0adf6 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/rom/driverlib.c @@ -0,0 +1,7733 @@ +#include "../driverlib/adi.h" +#include "../driverlib/aes.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_batmon.h" +#include "../driverlib/aon_event.h" +#include "../driverlib/aon_ioc.h" +#include "../driverlib/aon_rtc.h" +#include "../driverlib/aon_rtc.h" +#include "../driverlib/aux_adc.h" +#include "../driverlib/aux_ctrl.h" +#include "../driverlib/aux_tdc.h" +#include "../driverlib/chipinfo.h" +#include "../driverlib/cpu.h" +#include "../driverlib/cpu.h" +#include "../driverlib/crypto.h" +#include "../driverlib/ddi.h" +#include "../driverlib/ddi.h" +#include "../driverlib/event.h" +#include "../driverlib/flash.h" +#include "../driverlib/flash.h" +#include "../driverlib/gpio.h" +#include "../driverlib/i2c.h" +#include "../driverlib/i2s.h" +#include "../driverlib/interrupt.h" +#include "../driverlib/ioc.h" +#include "../driverlib/ioc.h" +#include "../driverlib/osc.h" +#include "../driverlib/osc.h" +#include "../driverlib/pka.h" +#include "../driverlib/prcm.h" +#include "../driverlib/pwr_ctrl.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/setup_rom.h" +#include "../driverlib/sha2.h" +#include "../driverlib/smph.h" +#include "../driverlib/ssi.h" +#include "../driverlib/sys_ctrl.h" +#include "../driverlib/sys_ctrl.h" +#include "../driverlib/sys_ctrl.h" +#include "../driverlib/timer.h" +#include "../driverlib/trng.h" +#include "../driverlib/uart.h" +#include "../driverlib/udma.h" +#include "../driverlib/vims.h" +#include "../inc/hw_adi.h" +#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_adi_4_aux.h" +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ddi_0_osc.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" +#include "../inc/hw_types.h" +#include "stdlib.h" + +//***************************************************************************** +// +// Disable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsid(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + mrs r0, PRIMASK; + cpsid i; + bx lr +} +#elif (defined(__TI_COMPILER_VERSION__) || defined(__clang__)) +uint32_t +CPUcpsid(void) +{ + // Read PRIMASK and disable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsid(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and disable interrupts + __asm volatile (" mrs %0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Enable all external interrupts +// +//***************************************************************************** +#if defined(DOXYGEN) +uint32_t +CPUcpsie(void) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n"); + + // "Warning[Pe940]: missing return statement at end of non-void function" + // is suppressed here to avoid putting a "bx lr" in the inline assembly + // above and a superfluous return statement here. +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + mrs r0, PRIMASK; + cpsie i; + bx lr +} +#elif (defined(__TI_COMPILER_VERSION__) || defined(__clang__)) +uint32_t +CPUcpsie(void) +{ + // Read PRIMASK and enable interrupts. + __asm(" mrs r0, PRIMASK\n" + " cpsie i\n" + " bx lr\n"); + + // The following keeps the compiler happy, because it wants to see a + // return value from this function. It will generate code to return + // a zero. However, the real return is the "bx lr" above, so the + // return(0) is never executed and the function returns with the value + // you expect in R0. + return(0); +} +#else +uint32_t __attribute__((naked)) +CPUcpsie(void) +{ + uint32_t ui32Ret; + + // Read PRIMASK and enable interrupts. + __asm volatile (" mrs %0, PRIMASK\n" + " cpsie i\n" + " bx lr\n" + : "=r"(ui32Ret) + ); + + // The return is handled in the inline assembly, but the compiler will + // still complain if there is not an explicit return here (despite the fact + // that this does not result in any code being produced because of the + // naked attribute). + return(ui32Ret); +} +#endif +//***************************************************************************** +// +// Provide a small delay +// +//***************************************************************************** +#if defined(DOXYGEN) +void +CPUdelay(uint32_t ui32Count) +{ + // This function is written in assembly. See cpu.c for compiler specific implementation. +} +#elif defined(__IAR_SYSTEMS_ICC__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +#pragma diag_suppress=Pe940 +} +#pragma diag_default=Pe940 +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +__asm void +CPUdelay(uint32_t ui32Count) +{ + // Delay the specified number of times (3 cycles pr. loop) +CPUdel + subs r0, #1; + bne CPUdel; + bx lr; +} +#elif defined(__TI_COMPILER_VERSION__) + // For CCS implement this function in pure assembly. This prevents the TI + // compiler from doing funny things with the optimizer. + + // Loop the specified number of times +__asm(" .sect \".text:CPUdelay\"\n" + " .clink\n" + " .thumbfunc CPUdelay\n" + " .thumb\n" + " .global CPUdelay\n" + "CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr\n"); +#elif defined(__clang__) +void +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm("CPUdelay:\n" + " subs r0, #1\n" + " bne.n CPUdelay\n" + " bx lr"); +} +#else +// GCC +void __attribute__((naked)) +CPUdelay(uint32_t ui32Count) +{ + // Loop the specified number of times + __asm volatile ("%=: subs %0, #1\n" + " bne %=b\n" + " bx lr\n" + : /* No output */ + : "r" (ui32Count) + ); +} +#endif + +void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) { + uint32_t ui32Shift ; + uint32_t ui32Mask ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + ASSERT( ui32EventSrc <= AON_EVENT_NONE ); + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32Mask = ( 0x3F << ui32Shift ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift ); +} + +uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) { + uint32_t ui32Shift ; + uint32_t ui32RegAdr ; + + // Check the arguments. + ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) + + ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); + ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); + if ( ui32MCUWUEvent > 3 ) { + ui32RegAdr += 4; + } + return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F ); +} + +void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) { + uint32_t ui32Ctrl; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + ASSERT(ui32EventSrc <= AON_EVENT_NONE); + + ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); + ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; + } + + HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; +} + +uint32_t AONEventMcuGet(uint32_t ui32MCUEvent) { + uint32_t ui32EventSrc; + + // Check the arguments. + ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || + (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); + + ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); + + if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); + } + else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) + { + return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> + AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); + } + + // Should never get to this statement, but suppress warning. + ASSERT(0); + return(0); +} + +uint64_t AONRTCCurrent64BitValueGet( void ) { + union { + uint64_t returnValue ; + uint32_t secAndSubSec[ 2 ] ; + } currentRtc ; + uint32_t ui32SecondSecRead ; + + // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC + // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. + do { + currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); + ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); + } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); + + return ( currentRtc.returnValue ); +} + +void AUXCTRLImageLoad(uint16_t *pui16Image, uint32_t ui32StartAddr, uint32_t ui32Size) { + uint16_t* pui16Src16; + uint16_t* pui16Dst16; + uint32_t ui32WordCnt; + + // Check the arguments. + ASSERT(ui32StartAddr < 512); + ASSERT(ui32Size <= 1024); + ASSERT((ui32Size / 2 + ui32StartAddr) <= 512); + + // Copy image to AUX RAM. + ui32WordCnt = (ui32Size >> 1); + pui16Src16 = pui16Image; + pui16Dst16 = (uint16_t*)(AUX_RAM_BASE + (ui32StartAddr << 1)); + + while(ui32WordCnt--) + { + *pui16Dst16++ = *pui16Src16++; + } +} + +void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition) { + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Make sure the AUX TDC is in the idle state before changing the + // configuration. + while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == + AUX_TDC_STAT_STATE_IDLE)) + { + } + + // Clear previous results. + HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; + + // Change the configuration. + HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; +} + +uint32_t AUXTDCMeasurementDone(uint32_t ui32Base) { + uint32_t ui32Reg; + uint32_t ui32Status; + + // Check the arguments. + ASSERT(AUXTDCBaseValid(ui32Base)); + + // Check if the AUX TDC is done measuring. + ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); + if(ui32Reg & AUX_TDC_STAT_DONE) + { + ui32Status = AUX_TDC_DONE; + } + else if(ui32Reg & AUX_TDC_STAT_SAT) + { + ui32Status = AUX_TDC_TIMEOUT; + } + else + { + ui32Status = AUX_TDC_BUSY; + } + + // Return the status. + return (ui32Status); +} + +void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) { + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(ui32Reg < DDI_SLAVE_REGS); + + // Write the value to the register. + HWREG(ui32Base + ui32Reg) = ui32Val; +} + +void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData) { + uint32_t ui32RegAddr; + uint32_t ui32Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); + ASSERT(!(ui32WrData & 0xFFFF0000)); + + // DDI 16-bit target is on 32-bit boundary so double offset + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 4; + ui32Mask >>= 16; + } + + // Write mask if data is not zero (to set mask bit), else write '0'. + ui32Data = ui32WrData ? ui32Mask : 0x0; + + // Update the register. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; +} + +void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data) { + uint32_t ui32RegAddr; + uint32_t ui32WrData; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // 16-bit target is on 32-bit boundary so double offset. + ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 4; + ui32Mask = ui32Mask >> 16; + } + + // Shift data in to position. + ui32WrData = ui32Data << ui32Shift; + + // Write data. + HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; +} + +uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) { + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the address of the register. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Mask & 0xFFFF0000) + { + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read a halfword on the DDI interface. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data. + ui16Data = ui16Data & ui32Mask; + + // Return masked data. + return(ui16Data); +} + +uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift) { + uint32_t ui32RegAddr; + uint16_t ui16Data; + + // Check the arguments. + ASSERT(DDIBaseValid(ui32Base)); + + // Calculate the register address. + ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; + + // Adjust for target bit in high half of the word. + if(ui32Shift >= 16) + { + ui32Shift = ui32Shift - 16; + ui32RegAddr += 2; + ui32Mask = ui32Mask >> 16; + } + + // Read the register. + ui16Data = HWREGH(ui32RegAddr); + + // Mask data and shift into place. + ui16Data &= ui32Mask; + ui16Data >>= ui32Shift; + + // Return data. + return(ui16Data); +} + +//***************************************************************************** +// +// Defines for accesses to the security control in the customer configuration +// area in flash top sector. +// +//***************************************************************************** +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 +#define CCFG_SIZE_SECURITY 0x00000014 +#define CCFG_SIZE_SECT_PROT 0x00000004 + +//***************************************************************************** +// +// Default values for security control in customer configuration area in flash +// top sector. +// +//***************************************************************************** +const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF + }; + +//***************************************************************************** +// +// Function prototypes for static functions +// +//***************************************************************************** +static void IssueFsmCommand(tFlashStateCommandsType eCommand); +static void EnableSectorsForWrite(uint32_t ui32BankNo); +static uint32_t ScaleCycleValues(uint32_t ui32SpecifiedTiming, + uint32_t ui32ScaleValue); +static void SetWriteMode(void); +static void TrimForWrite(void); +static void SetReadMode(void); + +void FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod) { + // Check the arguments. + ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || + ui32PowerMode == FLASH_PWR_OFF_MODE || + ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); + ASSERT(ui32BankGracePeriod <= 0xFF); + ASSERT(ui32PumpGracePeriod <= 0xFFFF); + + // Initialize flag requesting deprecated power mode + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) &= ~FW_PWRMODE_DEPRECATED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; + + switch(ui32PowerMode) + { + case FLASH_PWR_ACTIVE_MODE: + // Set bank power mode to ACTIVE. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = + (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + ~FLASH_FBFALLBACK_BANKPWR1_M) | (FBFALLBACK_ACTIVE << FLASH_FBFALLBACK_BANKPWR1_S); + + // Set charge pump power mode to ACTIVE mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) = + (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); + break; + + case FLASH_PWR_DEEP_STDBY_MODE: + // Deprecated power mode requested. Set flag. + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_PWRMODE_DEPRECATED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; + // Fall through to force FLASH_PWR_OFF_MODE power mode + case FLASH_PWR_OFF_MODE: + // Set bank grace period. + HWREG(FLASH_BASE + FLASH_O_FBAC) = + (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | + ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); + + // Set pump grace period. + HWREG(FLASH_BASE + FLASH_O_FPAC2) = + (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | + ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); + + // Set bank power mode to SLEEP. + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; + HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR1_M; + + // Set charge pump power mode to SLEEP mode. + HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; + break; + } +} + +uint32_t FlashPowerModeGet(void) { + uint32_t ui32PowerMode; + uint32_t ui32BankPwrMode; + + ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & + FLASH_FBFALLBACK_BANKPWR0_M; + + if(ui32BankPwrMode == FBFALLBACK_SLEEP) + { + ui32PowerMode = FLASH_PWR_OFF_MODE; + } + else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) + { + ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; + } + else + { + ui32PowerMode = FLASH_PWR_ACTIVE_MODE; + } + + // Return power mode. + return(ui32PowerMode); +} + +void FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) { + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(ui32ProtectMode == FLASH_WRITE_PROTECT) + { + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / + FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + if(ui32SectorNumber <= 31) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 43) + { + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= + (1 << (ui32SectorNumber & 0x1F)); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= + (1 << (ui32SectorNumber & 0x1F)); + } + else if(ui32SectorNumber <= 75) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x1; + ui32SectorNumber -= 44; + + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); + } + else if(ui32SectorNumber <= 87) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 76; + + HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= (1 << ui32SectorNumber); + HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= (1 << ui32SectorNumber); + } + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } +} + +uint32_t FlashProtectionGet(uint32_t ui32SectorAddress) { + uint32_t ui32SectorProtect; + uint32_t ui32SectorNumber; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32SectorProtect = FLASH_NO_PROTECT; + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + if(ui32SectorNumber <= 31) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 43) + { + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & + (1 << (ui32SectorNumber & 0x1F))) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & + (1 << (ui32SectorNumber & 0x1F)))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 75) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 44; + + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + else if(ui32SectorNumber <= 87) + { + // Select bank 1 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x01; + ui32SectorNumber -= 76; + + if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & (1 << ui32SectorNumber)) && + (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & (1 << ui32SectorNumber))) + { + ui32SectorProtect = FLASH_WRITE_PROTECT; + } + } + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + return(ui32SectorProtect); +} + +uint32_t FlashProtectionSave(uint32_t ui32SectorAddress) { + uint32_t ui32ErrorReturn; + uint32_t ui32SectorNumber; + uint32_t ui32CcfgSectorAddr; + uint32_t ui32ProgBuf; + + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) + { + // Find sector number for specified sector. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + + // Adjust CCFG address to the 32-bit CCFG word holding the + // protect-bit for the specified sector. + ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); + + // Find value to program by setting the protect-bit which + // corresponds to specified sector number, to 0. + // Leave other protect-bits unchanged. + ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & + *(uint32_t *)ui32CcfgSectorAddr; + + ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, + CCFG_SIZE_SECT_PROT); + } + + // Return status. + return(ui32ErrorReturn); +} + +uint32_t FlashSectorErase(uint32_t ui32SectorAddress) { + // The below code part constitutes the variant of the FlashSectorErase() + // function that is located in ROM. The source code of this variant is not + // visible in internal or external driverlib. The source code is + // only compiled during a ROM build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. + uint32_t ui32ErrorReturn; + uint32_t ui32Error; + uint32_t ui32SectorBit; + uint32_t ui32SectorNumber; + uint32_t ui32BankNo; + uint32_t ui32TopBankStartAddr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + // Find flash bank contaning sector to erase + ui32BankNo = 0; + if(ui32SectorAddress >= ui32TopBankStartAddr) + { + ui32BankNo = 1; + } + + // Enable all sectors for erase. + EnableSectorsForWrite(ui32BankNo); + + // Check the arguments. + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Unprotect sector to be erased. + ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + if(ui32SectorNumber <= 31) + { + ui32SectorBit = 1 << ui32SectorNumber; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; + } + else if(ui32SectorNumber <= 43) + { + ui32SectorNumber -= 32; + ui32SectorBit = 1 << ui32SectorNumber; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; + } + else if(ui32SectorNumber <= 75) + { + ui32SectorNumber -= 44; + ui32SectorBit = 1 << ui32SectorNumber; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = ~ui32SectorBit; + } + else if(ui32SectorNumber <= 87) + { + ui32SectorNumber -= 76; + ui32SectorBit = 1 << ui32SectorNumber; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = ~ui32SectorBit; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Write the address to the FSM. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // Issue the sector erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_SECTOR); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Check if flash top sector was erased. + if(ui32SectorAddress == (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())) + { + // Program security data to default values in the customer configuration + // area within the flash top sector. + ui32Error = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + + if((ui32Error != FAPI_STATUS_SUCCESS) && + (ui32ErrorReturn == FAPI_STATUS_SUCCESS)) + { + ui32ErrorReturn = ui32Error; + } +} + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashBankErase(bool bForcePrecondition) { + uint32_t ui32ErrorReturn = FAPI_STATUS_SUCCESS; + uint32_t ui32SectorAddress; + uint32_t ui32RegVal; + uint32_t ui32BankNo; + uint32_t ui32TopBankStartAddr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; + + for(ui32BankNo = 0; ui32BankNo < ((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_NUM_BANK_M) + >> FLASH_FCFG_BANK_MAIN_NUM_BANK_S); ui32BankNo++) + { + // Enable all sectors for erase. + EnableSectorsForWrite(ui32BankNo); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Enable erase of all sectors and enable precondition if required. + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if(bForcePrecondition) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ADDR_OFFSET + (ui32BankNo * ui32TopBankStartAddr); + + // Issue the bank erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_BANK); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Set configured precondition mode since it may have been forced on. + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + } + + // Program security data to default values in the customer configuration + // area within the flash top sector if erase was successful. + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + ui32SectorAddress = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); + ui32ErrorReturn = FlashProgram((uint8_t *)g_pui8CcfgDefaultSec, + (ui32SectorAddress + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + } + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashhOtpEngrErase(void) { + uint32_t ui32ErrorReturn = FAPI_STATUS_SUCCESS; + uint32_t ui32RegVal; + uint32_t ui32BankNo; + + for(ui32BankNo = 0; ui32BankNo < ((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_NUM_BANK_M) + >> FLASH_FCFG_BANK_MAIN_NUM_BANK_S); ui32BankNo++) + { + // Enable all sectors for erase. + EnableSectorsForWrite(ui32BankNo); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) = (HWREG(FLASH_BASE + FLASH_O_FBAC) & ~FLASH_FBAC_OTPPROTDIS_M) + | ((1 << ui32BankNo) << FLASH_FBAC_OTPPROTDIS_S); + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Set address to OTP. + if(ui32BankNo == 1) + { + HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0002000; + } + else + { + HWREG(FLASH_BASE + FLASH_O_FADDR) = 0xF0000000; + } + + // Enable for FSM test commands and erase precondition. + ui32RegVal = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + (FLASH_FSM_ST_MACHINE_CMD_EN | FLASH_FSM_ST_MACHINE_DO_PRECOND); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Issue the erase command to the FSM. + IssueFsmCommand(FAPI_ERASE_OTP); + + // Wait for erase to finish. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for erase. + FlashDisableSectorsForWrite(); + + // Disable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Renable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS_M; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + + // Set configured precondition mode since it may have been changed. + if(!(ui32RegVal & FLASH_FSM_ST_MACHINE_DO_PRECOND)) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + } + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) { + // The below code part constitutes the variant of the FlashProgram() function + // that is located in ROM. The source code of this variant is not visible in + // internal or external driverlib. The source code is only compiled during a ROM + // build. + // The two above code parts (seperated by compile switches) constitute wrapper + // functions which both call this ROM variant of the function. + // The ROM variant is called by referrencing it directly through the ROM API table. + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + uint32_t ui32BankNo; + uint32_t ui32TopBankStartAddr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; + + // Check the arguments. + ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); + + ui32BankNo = 0; + if(ui32Address >= ui32TopBankStartAddr) + { + ui32BankNo = 1; + } + + // Enable sectors for programming in target bank. + EnableSectorsForWrite(ui32BankNo); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32Address + ui32Count) > (FLASHMEM_BASE + FlashSizeGet())) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set the status to indicate success. + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Loop over the bytes to be programmed. + while(ui32Count) + { + // Setup the start position within the write data registers. + ui32StartIndex = ui32Address & (uint32_t)(ui8BankWidth - 1); + + // Setup number of bytes to program. + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32Address + ADDR_OFFSET; + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // Wait until the word has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Exit if an access violation occurred. + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // Prepare for next data burst. + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32Address += ((ui32StopIndex - ui32StartIndex) + 1); + // Check if next data burst require change of target bank + if((ui32BankNo == 0) && (ui32Address >= ui32TopBankStartAddr)) + { + // Change target bank. + FlashDisableSectorsForWrite(); + ui32BankNo = 1; + EnableSectorsForWrite(ui32BankNo); + } + } + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgramNowait(uint32_t ui32StartAddress, uint8_t *pui8DataBuffer, uint8_t ui8NoOfBytes) { + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint32_t ui32BankWidth; + uint32_t ui32ErrorReturn; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32BankNo; + uint32_t ui32TopBankStartAddr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; + + // Check the arguments. + ASSERT((ui32StartAddress + ui8NoOfBytes) <= (FLASHMEM_BASE + FlashSizeGet())); + + ui32BankNo = 0; + if(ui32StartAddress >= ui32TopBankStartAddr) + { + ui32BankNo = 1; + } + + // Enable all sectors for erase. + EnableSectorsForWrite(ui32BankNo); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32StartAddress + ui8NoOfBytes) > (FLASHMEM_BASE + FlashSizeGet())) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set status to indicate success + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui32BankWidth = (((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Setup the start position within the write data registers. + ui32StartIndex = ui32StartAddress & (ui32BankWidth - 1); + + // Check to see if there is more data in the buffer than the register. + // width. + if((ui8NoOfBytes == 0) || ((ui32StartIndex + ui8NoOfBytes) > ui32BankWidth)) + { + ui32ErrorReturn = FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH; + } + + if(ui32ErrorReturn == FAPI_STATUS_SUCCESS) + { + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32StartAddress + ADDR_OFFSET; + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); +} + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_DATA); + } + + // Return the function status. + return(ui32ErrorReturn); +} + +bool FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) { + bool bStatus; + + // Make sure the clock for the efuse is enabled + HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; + + // Set timing for EFUSE read operations. + HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & + FLASH_EFUSEREAD_READCLOCK_M); + + // Clear status register. + HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; + + // Select the FuseROM block 0. + HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; + + // Start the read operation. + HWREG(FLASH_BASE + FLASH_O_EFUSE) = + (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | + (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); + + // Wait for operation to finish. + while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) + { + } + + // Check if error reported. + if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) + { + // Set error status. + bStatus = 1; + + // Clear data. + *pui32EfuseData = 0; + } + else + { + // Set ok status. + bStatus = 0; + + // No error. Get data from data register. + *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); + } + + // Disable the efuse clock to conserve power + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; + + // Return the data. + return(bStatus); +} + +uint32_t FlashProgramPattern(uint32_t ui32SectorAddress, uint32_t ui32DataPattern, bool bInvertData) { + uint8_t ui8Index; + uint8_t ui8BankWidth; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + uint32_t ui32BankNo; + uint32_t ui32TopBankStartAddr = (HWREG(FLASH_BASE + FLASH_O_FCFG_B1_START) & + FLASH_FCFG_B1_START_B1_START_ADDR_M) + >> FLASH_FCFG_B1_START_B1_START_ADDR_S; + + // Check the arguments. + ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - + FlashSectorSizeGet())); + ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); + + ui32BankNo = 0; + if(ui32SectorAddress >= ui32TopBankStartAddr) + { + ui32BankNo = 1; + } + + // Enable all sectors for erase. + EnableSectorsForWrite(ui32BankNo); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if((ui32SectorAddress > + (FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet())) || + ((ui32SectorAddress & (FlashSectorSizeGet() - 1)) != 00)) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32SectorAddress + ADDR_OFFSET; + + // Write each byte of the pattern to the FWPWrite registers. + for(ui8Index = 0; ui8Index < ui8BankWidth; ui8Index++) + { + oFwpWriteByte[ui8Index] = ui32DataPattern >> ((ui8Index * 8) & + (PATTERN_BITS - 1)); + } + + // Enable for FSM test command and enable the Invert Data option if + // required. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + if(bInvertData) + { + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_INV_DATA; + } + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Issue the Program command to the FSM. + IssueFsmCommand(FAPI_PROGRAM_SECTOR); + + // Wait until the sector has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update status of the program operation. + ui32ErrorReturn = FlashCheckFsmForError(); + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Disable FSM test command mode and the Invert Data option. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_INV_DATA; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Return status of operation. + return(ui32ErrorReturn); +} + +uint32_t FlashProgramEngr(uint8_t *pui8DataBuffer, uint32_t ui32AddressOffset, uint32_t ui32Count) { + uint32_t ui32StartIndex; + uint32_t ui32StopIndex; + uint32_t ui32Index; + uint8_t ui8BankWidth; + uint8_t ui8NoOfBytes; + tFwpWriteByte *oFwpWriteByte; + uint32_t ui32ErrorReturn; + uint32_t ui32BankNo; + + // Check the arguments. + ASSERT((ui32AddressOffset + ui32Count) <= (2048 * 2)); + // Enable sectors for programming. + ui32BankNo = 0; + if(ui32AddressOffset >= 2048) + { + ui32BankNo = 1; + } + EnableSectorsForWrite(ui32BankNo); + oFwpWriteByte = FWPWRITE_BYTE_ADDRESS; + + // Check the arguments. + if(((ui32AddressOffset + ui32Count) > (2048 * 2)) || + ((ui32AddressOffset < 2048) && ((ui32AddressOffset + ui32Count) > 2048))) + { + // Invalid arguments. Exit function! + FlashDisableSectorsForWrite(); + return (FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH); + } + + // Set the status to indicate success. + ui32ErrorReturn = FAPI_STATUS_SUCCESS; + + // Find flash bank width in number of bytes. + ui8BankWidth = + (uint8_t)(((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M) >> + FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S) >> 3); + + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) = (HWREG(FLASH_BASE + FLASH_O_FBAC) & ~FLASH_FBAC_OTPPROTDIS_M) + | ((1 << ui32BankNo) << FLASH_FBAC_OTPPROTDIS_S); + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Enable for FSM test command. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Loop over the bytes to be programmed. + while(ui32Count) + { + // Setup the start position within the write data registers. + ui32StartIndex = ui32AddressOffset & (uint32_t)(ui8BankWidth - 1); + + // Setup number of bytes to program. + ui8NoOfBytes = ui8BankWidth - ui32StartIndex; + if(ui8NoOfBytes > ui32Count) + { + ui8NoOfBytes = ui32Count; + } + + // Clear the Status register. + IssueFsmCommand(FAPI_CLEAR_STATUS); + + // Write address to FADDR register. + if(ui32BankNo == 0) + { + HWREG(FLASH_BASE + FLASH_O_FADDR) = ui32AddressOffset + 0xF0080000; + } + else + { + HWREG(FLASH_BASE + FLASH_O_FADDR) = (ui32AddressOffset - 2048) + 0xF0082000; + } + + // Setup the stop position within the write data registers. + ui32StopIndex = ui32StartIndex + (uint32_t)(ui8NoOfBytes - 1); + + // Write each byte to the FWPWrite registers. + for(ui32Index = ui32StartIndex; ui32Index <= ui32StopIndex; ui32Index++) + { + oFwpWriteByte[ui32Index] = *(pui8DataBuffer++); + } + + // Issue programming command. + IssueFsmCommand(FAPI_PROGRAM_DATA); + + // Wait until the word has been programmed. + while(FlashCheckFsmForReady() == FAPI_STATUS_FSM_BUSY) + { + } + + // Update error status and exit if an error occurred. + ui32ErrorReturn = FlashCheckFsmForError(); + if(ui32ErrorReturn != FAPI_STATUS_SUCCESS) + { + break; + } + + // Prepare for next data burst. + ui32Count -= ((ui32StopIndex - ui32StartIndex) + 1); + ui32AddressOffset += ((ui32StopIndex - ui32StartIndex) + 1); + } + + // Disable sectors for programming. + FlashDisableSectorsForWrite(); + + // Re-enable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS_M; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable test commands. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + // Return status of operation. + return(ui32ErrorReturn); +} + +void FlashOtpProgramEraseSetup(void) { + // Disable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) |= FLASH_FBAC_OTPPROTDIS_M; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Enable test commands by performing the following steps: + // - Enable SW Interface mode + // - Enable for test commands + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) |= FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x000055AA; + + // Enable for FSM test commands. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +void FlashOtpProgramEraseCleanup(void) { + // Re-enable OTP protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + HWREG(FLASH_BASE + FLASH_O_FBAC) &= ~FLASH_FBAC_OTPPROTDIS_M; + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Disable test commands and turn off SW interface mode. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x0000AAAA; + HWREG(FLASH_BASE + FLASH_O_FTCTL) &= ~FLASH_FTCTL_TEST_EN; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Disable FSM test command mode. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~FLASH_FSM_ST_MACHINE_CMD_EN; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +void FlashDisableSectorsForWrite(void) { + uint32_t ui32BankNo; + // Configure flash back to read mode + SetReadMode(); + + for(ui32BankNo = 0; ui32BankNo < ((HWREG(FLASH_BASE + FLASH_O_FCFG_BANK) & + FLASH_FCFG_BANK_MAIN_NUM_BANK_M) + >> FLASH_FCFG_BANK_MAIN_NUM_BANK_S); ui32BankNo++) + { + // Select bank + HWREG(FLASH_BASE + FLASH_O_FMAC) = ui32BankNo; + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS_M; + + // Disable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + // Enable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + // Protect sectors from sector erase. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + // Select bank 0 + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x0; +} +//***************************************************************************** +// +//! \internal +//! Issues a command to the Flash State Machine. +//! +//! \param eCommand specifies the FSM command. +//! +//! Issues a command to the Flash State Machine. +//! +//! \return None +// +//***************************************************************************** +static void +IssueFsmCommand(tFlashStateCommandsType eCommand) +{ + // Check the arguments. + ASSERT( + eCommand == FAPI_ERASE_SECTOR || eCommand == FAPI_ERASE_BANK || + eCommand == FAPI_VALIDATE_SECTOR || eCommand == FAPI_CLEAR_STATUS || + eCommand == FAPI_PROGRAM_RESUME || eCommand == FAPI_ERASE_RESUME || + eCommand == FAPI_CLEAR_MORE || eCommand == FAPI_PROGRAM_SECTOR || + eCommand == FAPI_PROGRAM_DATA || eCommand == FAPI_ERASE_OTP); + + // Enable write to FSM register. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // Issue FSM command. + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = eCommand; + + // Start command execute. + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + // Disable write to FSM register. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +//***************************************************************************** +// +//! \internal +//! Enables all sectors for erase and programming on the active bank. +//! +//! This function disables the idle reading power reduction mode, selects the +//! flash bank and enables all sectors for erase and programming on the active +//! bank. +//! Sectors may be protected from programming depending on the value of the +//! FLASH_O_FSM_BSLPx registers. +//! Sectors may be protected from erase depending on the value of the +//! FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +//! the FLASH_O_FSM_SECTOR1 register. +//! +//! \return None +// +//***************************************************************************** +static void +EnableSectorsForWrite(uint32_t ui32BankNo) +{ + // Trim flash module for program/erase operation. + TrimForWrite(); + + // Configure flash to write mode + SetWriteMode(); + + // Select flash bank. + HWREG(FLASH_BASE + FLASH_O_FMAC) = ui32BankNo; + + // Disable Level 1 Protection. + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + // Enable all sectors for erase and programming. + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + // Enable Level 1 Protection + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Trims the Flash Bank and Flash Pump for program/erase functionality +//! +//! This trimming will make it possible to perform erase and program operations +//! of the flash. Trim values are loaded from factory configuration area +//! (referred to as FCGF1). The trimming done by this function is valid until +//! reset of the flash module. +//! +//! Some registers shall be written with a value that is a number of FCLK +//! cycles. The trim values controlling these registers have a value of +//! number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +//! +//! In order to calculate the register value for these registers the +//! following calculation must be done: +//! +//! OtpValue SysClkMHz +//! -------- us OtpValue x --------- +//! 2 (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ----------------- = --------------------- +//! 1 4 +//! -------------- +//! SysClkMHz +//! ------------ +//! (RWAIT+1)x 2 +//! +//! This is equivalent to: +//! +//! 16 x SysClkMHz +//! OtpValue x --------------- +//! (RWAIT+1) +//! RegValue_in_no_of_clk_cycles = ---------------------------- +//! 64 +//! +//! A scaling factor is set equal to: +//! +//! 16 x SysClkMHz +//! ui32FclkScale = -------------- +//! (RWAIT+1) +//! +//! which gives: +//! +//! OtpValue x ui32FclkScale +//! RegValue_in_no_of_clk_cycles = ------------------------ +//! 64 +//! +//! \return None. +// +//***************************************************************************** +static void +TrimForWrite(void) +{ + uint32_t ui32Value; + uint32_t ui32TempVal; + uint32_t ui32FclkScale; + uint32_t ui32RWait; + + // Return if flash is already trimmed for program/erase operations. + if(HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + { + return; + } + + //***********************************************************************// + // // + // Configure the FSM registers // + // // + //***********************************************************************// + + // Enable access to the FSM registers. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + // Determine the scaling value to be used on timing related trim values. + // The scaling value is based on the flash module clock frequency and RWAIT + ui32RWait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + ui32FclkScale = (16 * FLASH_MODULE_CLK_FREQ) / (ui32RWait + 1); + + // Configure Program pulse width bits 15:0. + // (FCFG1 offset 0x188 bits 15:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_PROGRAM_PW_M) >> + FCFG1_FLASH_PROG_EP_PROGRAM_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((ui32Value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + // Configure Erase pulse width bits 31:0. + // (FCFG1 offset 0x18C bits 31:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) & + FCFG1_FLASH_ERA_PW_ERASE_PW_M) >> + FCFG1_FLASH_ERA_PW_ERASE_PW_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((ui32Value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + + // Configure no of flash clock cycles from EXECUTEZ going low to the + // verify data can be read in the program verify mode bits 7:0. + // (FCFG1 offset 0x174 bits 23:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_PV_ACCESS_M) >> + FCFG1_FLASH_C_E_P_R_PV_ACCESS_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((ui32Value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + // Configure the number of flash clocks from the start of the Read mode at + // the end of the operations until the FSM clears the BUSY bit in FMSTAT. + // (FCFG1 offset 0x178 bits 23:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_RH_M) >> + FCFG1_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((ui32Value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + // Configure Program hold time + // (FCFG1 offset 0x178 bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PH_M) >> + FCFG1_FLASH_P_R_PV_PH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((ui32Value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + // Configure Erase hold time + // (FCFG1 offset 0x17C bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_EH_M) >> + FCFG1_FLASH_EH_SEQ_EH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((ui32Value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + // Configure Program verify row switch time + // (FCFG1 offset0x178 bits 15:8). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PVH_M) >> + FCFG1_FLASH_P_R_PV_PVH_S; + + ui32Value = ScaleCycleValues(ui32Value, ui32FclkScale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((ui32Value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + // Configure Program Operation Setup time + // (FCFG1 offset 0x170 bits 31:24). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PSU_M) >> + FCFG1_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + // Configure Erase Operation Setup time + // (FCGF1 offset 0x170 bits 23:16). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_ESU_M) >> + FCFG1_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((ui32Value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + // Configure Program Verify Setup time + // (FCFG1 offset 0x170 bits 15:8). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PVSU_M) >> + FCFG1_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + // Configure Erase Verify Setup time + // (FCFG1 offset 0x170 bits 7:0). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_EVSU_M) >> + FCFG1_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((ui32Value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + // Configure Addr to EXECUTEZ low setup time + // (FCFG1 offset 0x174 bits 15:12). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((ui32Value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + // Configure Voltage Status Count + // (FCFG1 offset 0x17C bits 15:12). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_VSTAT_M) >> + FCFG1_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((ui32Value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + // Configure Repeat Verify action setup + // (FCFG1 offset 0x174 bits 31:24). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_RVSU_M) >> + FCFG1_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((ui32Value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + // Configure Maximum Programming Pulses + // (FCFG1 offset 0x184 bits 15:0). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PP) & + FCFG1_FLASH_PP_MAX_PP_M) >> + FCFG1_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + // Configure Beginning level for VHVCT used during erase modes + // (FCFG1 offset 0x180 bits 31:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_START_M) >> + FCFG1_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + // Configure Maximum EC Level + // (FCFG1 offset 0x2B0 bits 21:18). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + // Configure Maximum Erase Pulses + // (FCFG1 offset 0x188 bits 31:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_MAX_EP_M) >> + FCFG1_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((ui32Value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + // Configure the VHVCT Step Size. This is the number of erase pulses that + // must be completed for each level before the FSM increments the + // CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + // equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + // voltage. + // (FCFG1 offset 0x2B0 bits 31:23). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((ui32Value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + // Configure the hight of each EC step. This is the number of counts that + // the CUR_EC_LEVEL will increment when going to a new level. Actual count + // size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + // voltage. + // The read trim value is decremented by 1 before written to the register + // since actual counts equals (register value + 1). + // (FCFG1 offset 0x180 bits 15:0). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((ui32Value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + // Configure Precondition used in erase operations + // (FCFG1 offset 0x2B0 bit 22). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((ui32Value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + // Enable the recommended Good Time function. + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + // Disable write access to FSM registers. + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + + //***********************************************************************// + // // + // Configure the voltage registers // + // // + //***********************************************************************// + + // Unlock voltage registers (0x2080 - 0x2098). + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + // Configure voltage level for the specified pump voltage of high + // voltage supply input during erase operation VHVCT_E and the TRIM13_E + // (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). + ui32TempVal = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_TRIM13_E_M)>> + FCFG1_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_VHV_E_M)>> + FCFG1_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program verify operation VHVCT_PV and the TRIM13_PV + // (OTP offset 0x194 bits[19:16] and bits[27:24]). + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_PV_TRIM13_PV_M)>> + FCFG1_FLASH_VHV_PV_TRIM13_PV_S) << + FLASH_FVHVCT1_TRIM13_PV_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_PV_VHV_PV_M)>> + FCFG1_FLASH_VHV_PV_VHV_PV_S) << + FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of high voltage + // supply input during program operation VHVCT_P and TRIM13_P + // (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). + ui32TempVal = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + ui32Value = ((ui32TempVal & FCFG1_FLASH_VHV_TRIM13_P_M)>> + FCFG1_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + ui32Value |= ((ui32TempVal & FCFG1_FLASH_VHV_VHV_P_M)>> + FCFG1_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = + (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | ui32Value; + + // Configure voltage level for the specified pump voltage of wordline power + // supply for read mode + // (FCFG1 offset 0x198 Bits 15:8). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_V_READ_M) >> + FCFG1_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((ui32Value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + // Configure the voltage level for the VCG 2.5 CT pump voltage + // (FCFG1 offset 0x194 bits 15:8). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV) & + FCFG1_FLASH_VHV_PV_VCG2P5_M) >> + FCFG1_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((ui32Value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + // Configure the voltage level for the specified pump voltage of high + // current power input during program operation + // (FCFG1 offset 0x198 bits 31:24). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VSL_P_M) >> + FCFG1_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((ui32Value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + // Configure the voltage level for the specified pump voltage of wordline + // power supply during programming operations + // (OTP offset 0x198 bits 23:16). + ui32Value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VWL_P_M) >> + FCFG1_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((ui32Value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + // Configure the pump's TRIM_1P7 port pins. + // (FCFG1 offset 0x2B0 bits 17:16). + ui32Value = + (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((ui32Value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + // Lock the voltage registers. + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + // Set trimmed flag. + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +//***************************************************************************** +// +//! \internal +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \param ui32SpecifiedTiming +//! \param ui32ScaleValue +//! +//! Used to scale the TI OTP values based on the FClk scaling value. +//! +//! \return Returns the scaled value +// +//***************************************************************************** +static uint32_t +ScaleCycleValues(uint32_t ui32SpecifiedTiming, uint32_t ui32ScaleValue) +{ + return((ui32SpecifiedTiming * ui32ScaleValue) >> 6); +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in read mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetReadMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for read mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 4). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 12). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) + ui32Value = (((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +//***************************************************************************** +// +//! \internal +//! Used to set flash in write mode. +//! +//! Flash is configured with values loaded from OTP dependent on the current +//! regulator mode. +//! +//! \return None. +// +//***************************************************************************** +static void +SetWriteMode(void) +{ + uint32_t ui32TrimValue; + uint32_t ui32Value; + + // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + // VIN_AT_X and VIN_BY_PASS for program/erase mode + if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) + { + // Select trim values for external regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 20). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 18:16) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } + else + { + // Select trim values for internal regulator mode: + // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + ui32TrimValue = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + // Configure DIS_STANDBY (OTP offset 0x308 bit 28). + ui32Value |= ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S) << + FLASH_CFG_DIS_STANDBY_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | + FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M)) | ui32Value; + + // Configure VIN_AT_X (OTP offset 0x308 bits 26:24) + ui32Value = ((ui32TrimValue & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + // VIN_BY_PASS should be 1 + if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + { + ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; + } + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast) { + uint32_t ui32SCLFreq; + uint32_t ui32TPR; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Must enable the device before doing anything else. + I2CMasterEnable(I2C0_BASE); + + // Get the desired SCL speed. + if(bFast == true) + { + ui32SCLFreq = 400000; + } + else + { + ui32SCLFreq = 100000; + } + + // Compute the clock divider that achieves the fastest speed less than or + // equal to the desired speed. The numerator is biased to favor a larger + // clock divider so that the resulting clock is always less than or equal + // to the desired clock, never greater. + ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; + HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; +} + +uint32_t I2CMasterErr(uint32_t ui32Base) { + uint32_t ui32Err; + + // Check the arguments. + ASSERT(I2CBaseValid(ui32Base)); + + // Get the raw error state. + ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); + + // If the I2C master is busy, then all the other status bits are invalid, + // and there is no error to report. + if(ui32Err & I2C_MSTAT_BUSY) + { + return(I2C_MASTER_ERR_NONE); + } + + // Check for errors. + if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) + { + return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); + } + else + { + return(I2C_MASTER_ERR_NONE); + } +} +//***************************************************************************** +// +//! This is a mapping between priority grouping encodings and the number of +//! preemption priority bits. +// +//***************************************************************************** +static const uint32_t g_pui32Priority[] = +{ + NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, + NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, + NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 +}; + +//***************************************************************************** +// +//! This is a mapping between interrupt number and the register that contains +//! the priority encoding for that interrupt. +// +//***************************************************************************** +static const uint32_t g_pui32Regs[] = +{ + 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, + NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, + NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 +}; + +void IntPriorityGroupingSet(uint32_t ui32Bits) { + // Check the arguments. + ASSERT(ui32Bits < NUM_PRIORITY); + + // Set the priority grouping. + HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; +} + +uint32_t IntPriorityGroupingGet(void) { + uint32_t ui32Loop, ui32Value; + + // Read the priority grouping. + ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; + + // Loop through the priority grouping values. + for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) + { + // Stop looping if this value matches. + if(ui32Value == g_pui32Priority[ui32Loop]) + { + break; + } + } + + // Return the number of priority bits. + return(ui32Loop); +} + +void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) { + uint32_t ui32Temp; + + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + ASSERT(ui8Priority <= INT_PRI_LEVEL7); + + // Set the interrupt priority. + ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); + ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); + ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); + HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; +} + +int32_t IntPriorityGet(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); + + // Return the interrupt priority. + return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & + 0xFF); +} + +void IntEnable(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to enable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Enable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Enable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Enable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Enable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Enable the general interrupt. + HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Enable the general interrupt. + HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); + } +} + +void IntDisable(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to disable. + if(ui32Interrupt == INT_MEMMANAGE_FAULT) + { + // Disable the MemManage interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); + } + else if(ui32Interrupt == INT_BUS_FAULT) + { + // Disable the bus fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); + } + else if(ui32Interrupt == INT_USAGE_FAULT) + { + // Disable the usage fault interrupt. + HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Disable the System Tick interrupt. + HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Disable the general interrupt. + HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Disable the general interrupt. + HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); + } +} + +void IntPendSet(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to pend. + if(ui32Interrupt == INT_NMI_FAULT) + { + // Pend the NMI interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; + } + else if(ui32Interrupt == INT_PENDSV) + { + // Pend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Pend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Pend the general interrupt. + HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Pend the general interrupt. + HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); + } +} + +bool IntPendGet(uint32_t ui32Interrupt) { + uint32_t ui32IntPending; + + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Assume no interrupts are pending. + ui32IntPending = 0; + + // The lower 16 IRQ vectors are unsupported by this function + if (ui32Interrupt < 16) + { + + return 0; + } + + // Subtract lower 16 irq vectors + ui32Interrupt -= 16; + + // Check if the interrupt is pending + ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); + ui32IntPending &= (1 << (ui32Interrupt & 31)); + + return ui32IntPending ? true : false; +} + +void IntPendClear(uint32_t ui32Interrupt) { + // Check the arguments. + ASSERT(ui32Interrupt < NUM_INTERRUPTS); + + // Determine the interrupt to unpend. + if(ui32Interrupt == INT_PENDSV) + { + // Unpend the PendSV interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; + } + else if(ui32Interrupt == INT_SYSTICK) + { + // Unpend the SysTick interrupt. + HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; + } + else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); + } + else if(ui32Interrupt >= 48) + { + // Unpend the general interrupt. + HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); + } +} + +void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the port. + HWREG(ui32Reg) = ui32IOConfig | ui32PortId; +} + +uint32_t IOCPortConfigureGet(uint32_t ui32IOId) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Return the IO configuration. + return HWREG(ui32Reg); +} + +void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || + (ui32IOShutdown == IOC_WAKE_ON_LOW) || + (ui32IOShutdown == IOC_WAKE_ON_HIGH)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_WU_CFG_M; + HWREG(ui32Reg) = ui32Config | ui32IOShutdown; +} + +void IOCIOJTagSet(uint32_t ui32IOId, uint32_t ui32IOJTag) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOJTag == IOC_JTAG_TDO_ENABLE) || + (ui32IOJTag == IOC_JTAG_TDI_ENABLE) || + (ui32IOJTag == IOC_JTAG_DISABLE)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~(IOC_IOCFG0_TDI | IOC_IOCFG0_TDO); + HWREG(ui32Reg) = ui32Config | ui32IOJTag; +} + +void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) { + uint32_t ui32Reg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || + (ui32IOMode == IOC_IOMODE_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || + (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); + + // Get the register address. + ui32Reg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32Reg); + ui32Config &= ~IOC_IOCFG0_IOMODE_M; + HWREG(ui32Reg) = ui32Config | ui32IOMode; +} + +void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Int == IOC_INT_ENABLE) || + (ui32Int == IOC_INT_DISABLE)); + ASSERT((ui32EdgeDet == IOC_NO_EDGE) || + (ui32EdgeDet == IOC_FALLING_EDGE) || + (ui32EdgeDet == IOC_RISING_EDGE) || + (ui32EdgeDet == IOC_BOTH_EDGES)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); + HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); +} + +void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the argument. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Pull == IOC_NO_IOPULL) || + (ui32Pull == IOC_IOPULL_UP) || + (ui32Pull == IOC_IOPULL_DOWN)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; + HWREG(ui32IOReg) = ui32Config | ui32Pull; +} + +void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || + (ui32Hysteresis == IOC_HYST_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_HYST_EN; + HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; +} + +void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32Input == IOC_INPUT_ENABLE) || + (ui32Input == IOC_INPUT_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_IE; + HWREG(ui32IOReg) = ui32Config | ui32Input; +} + +void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || + (ui32SlewEnable == IOC_SLEW_DISABLE)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_SLEW_RED; + HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; +} + +void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || + (ui32IOCurrent == IOC_CURRENT_4MA) || + (ui32IOCurrent == IOC_CURRENT_8MA)); + ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || + (ui32DrvStrength == IOC_STRENGTH_MAX) || + (ui32DrvStrength == IOC_STRENGTH_MED) || + (ui32DrvStrength == IOC_STRENGTH_AUTO)); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); + HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); +} + +void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Configure the IO. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_PORT_ID_M; + HWREG(ui32IOReg) = ui32Config | ui32PortId; +} + +void IOCIntEnable(uint32_t ui32IOId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Enable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +void IOCIntDisable(uint32_t ui32IOId) { + uint32_t ui32IOReg; + uint32_t ui32Config; + + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Get the register address. + ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); + + // Disable the specified interrupt. + ui32Config = HWREG(ui32IOReg); + ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; + HWREG(ui32IOReg) = ui32Config; +} + +void IOCPinTypeGpioInput(uint32_t ui32IOId) { + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); + + // Enable input mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); +} + +void IOCPinTypeGpioOutput(uint32_t ui32IOId) { + // Check the arguments. + ASSERT(ui32IOId <= IOID_31); + + // Setup the IO for standard input. + IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); + + // Enable output mode in the GPIO module. + GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); +} + +void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts) { + // Check the arguments. + ASSERT(ui32Base == UART0_BASE); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); + ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); + } + if(ui32Cts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); + } + if(ui32Rts != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); + } +} + +void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk) { + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); + } + } +} + +void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk) { + // Check the arguments. + ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); + ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); + ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); + ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Setup the IOs in the desired configuration. + if(ui32Base == SSI0_BASE) + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); + } + } + else + { + if(ui32Rx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); + } + if(ui32Tx != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); + } + if(ui32Fss != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); + } + if(ui32Clk != IOID_UNUSED) + { + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); + } + } +} + +void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) { + uint32_t ui32IOConfig; + + // Check the arguments. + ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); + ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); + + // Define the IO configuration parameters. + ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | + IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | + IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; + + // Setup the IOs in the desired configuration. + IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); + IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); +} + +void IOCPinTypeAux(uint32_t ui32IOId) { + // Check the arguments. + ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); + + // Setup the IO. + IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); +} + +//***************************************************************************** +// +// Arrays that maps the "peripheral set" number (which is stored in +// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that +// contains the relevant bit for that peripheral. +// +//***************************************************************************** + +// Run mode registers +static const uint32_t g_pui32RCGCRegs[] = +{ + PRCM_O_GPTCLKGR , // Index 0 + PRCM_O_SSICLKGR , // Index 1 + PRCM_O_UARTCLKGR , // Index 2 + PRCM_O_I2CCLKGR , // Index 3 + PRCM_O_SECDMACLKGR , // Index 4 + PRCM_O_GPIOCLKGR , // Index 5 + PRCM_O_I2SCLKGR // Index 6 +}; + +// Sleep mode registers +static const uint32_t g_pui32SCGCRegs[] = +{ + PRCM_O_GPTCLKGS , // Index 0 + PRCM_O_SSICLKGS , // Index 1 + PRCM_O_UARTCLKGS , // Index 2 + PRCM_O_I2CCLKGS , // Index 3 + PRCM_O_SECDMACLKGS , // Index 4 + PRCM_O_GPIOCLKGS , // Index 5 + PRCM_O_I2SCLKGS // Index 6 +}; + +// Deep sleep mode registers +static const uint32_t g_pui32DCGCRegs[] = +{ + PRCM_O_GPTCLKGDS , // Index 0 + PRCM_O_SSICLKGDS , // Index 1 + PRCM_O_UARTCLKGDS , // Index 2 + PRCM_O_I2CCLKGDS , // Index 3 + PRCM_O_SECDMACLKGDS , // Index 4 + PRCM_O_GPIOCLKGDS , // Index 5 + PRCM_O_I2SCLKGDS // Index 6 +}; + +//***************************************************************************** +// +// This macro extracts the array index out of the peripheral number +// +//***************************************************************************** +#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) + +//***************************************************************************** +// +// This macro extracts the peripheral instance number and generates bit mask +// +//***************************************************************************** +#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) + + +void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) { + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32)); + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32Divisor = 0; + + // Find the correct division factor. + if(ui32ClkDiv == PRCM_CLOCK_DIV_1) + { + ui32Divisor = 0x0; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) + { + ui32Divisor = 0x1; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) + { + ui32Divisor = 0x2; + } + else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) + { + ui32Divisor = 0x3; + } + + // Determine the correct power mode set the division factor accordingly. + if(ui32PowerMode == PRCM_RUN_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; + } +} + +uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode) { + uint32_t ui32ClkDiv; + uint32_t ui32Divisor; + + // Check the arguments. + ASSERT((ui32PowerMode == PRCM_RUN_MODE) || + (ui32PowerMode == PRCM_SLEEP_MODE) || + (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); + + ui32ClkDiv = 0; + ui32Divisor = 0; + + // Determine the correct power mode. + if(ui32PowerMode == PRCM_RUN_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); + } + else if(ui32PowerMode == PRCM_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); + } + else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); + } + + // Find the correct division factor. + if(ui32ClkDiv == 0x0) + { + ui32Divisor = PRCM_CLOCK_DIV_1; + } + else if(ui32ClkDiv == 0x1) + { + ui32Divisor = PRCM_CLOCK_DIV_2; + } + else if(ui32ClkDiv == 0x2) + { + ui32Divisor = PRCM_CLOCK_DIV_8; + } + else if(ui32ClkDiv == 0x3) + { + ui32Divisor = PRCM_CLOCK_DIV_32; + } + + // Return the clock division factor. + return ui32Divisor; +} + +void PRCMClockConfigureSet(uint32_t ui32Domains, uint32_t ui32ClkDiv) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_SYSBUS) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_TIMER) || + (ui32Domains & PRCM_DOMAIN_SERIAL)); + ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || + (ui32ClkDiv == PRCM_CLOCK_DIV_2) || + (ui32ClkDiv == PRCM_CLOCK_DIV_4) || + (ui32ClkDiv == PRCM_CLOCK_DIV_8) || + (ui32ClkDiv == PRCM_CLOCK_DIV_16) || + (ui32ClkDiv == PRCM_CLOCK_DIV_32) || + (ui32ClkDiv == PRCM_CLOCK_DIV_64) || + (ui32ClkDiv == PRCM_CLOCK_DIV_128) || + (ui32ClkDiv == PRCM_CLOCK_DIV_256)); + + // Configure the selected clock dividers. + if(ui32Domains & PRCM_DOMAIN_SYSBUS) + { + ui32Reg = PRCM_O_SYSBUSCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + ui32Reg = PRCM_O_CPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + ui32Reg = PRCM_O_PERBUSCPUCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + ui32Reg = PRCM_O_PERDMACLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } + if(ui32Domains & PRCM_DOMAIN_TIMER) + { + ui32Reg = PRCM_O_GPTCLKDIV; + HWREG(PRCM_BASE + ui32Reg) = ui32ClkDiv; + } +} + +uint32_t PRCMClockConfigureGet(uint32_t ui32Domain) { + uint32_t ui32ClkDiv; + + // Check the arguments. + ASSERT((ui32Domain == PRCM_DOMAIN_SYSBUS) || + (ui32Domain == PRCM_DOMAIN_CPU) || + (ui32Domain == PRCM_DOMAIN_PERIPH) || + (ui32Domain == PRCM_DOMAIN_TIMER) || + (ui32Domain == PRCM_DOMAIN_SERIAL)); + + ui32ClkDiv = 0; + + // Find the correct sub system. + if(ui32Domain == PRCM_DOMAIN_SYSBUS) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_SYSBUSCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_CPU) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_CPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_PERIPH) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERBUSCPUCLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_SERIAL) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_PERDMACLKDIV); + } + else if(ui32Domain == PRCM_DOMAIN_TIMER) + { + ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV); + } + + // Return the clock configuration. + return(ui32ClkDiv); +} + +void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) { + uint32_t ui32Reg; + uint32_t ui32MstDiv; + uint32_t ui32BitDiv; + uint32_t ui32WordDiv; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || + (ui32SampleRate == I2S_SAMPLE_RATE_24K) || + (ui32SampleRate == I2S_SAMPLE_RATE_32K) || + (ui32SampleRate == I2S_SAMPLE_RATE_48K)); + + ui32MstDiv = 0; + ui32BitDiv = 0; + ui32WordDiv = 0; + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Define the clock division factors for the audio interface. + switch(ui32SampleRate) + { + case I2S_SAMPLE_RATE_16K : + ui32MstDiv = 6; + ui32BitDiv = 60; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_24K : + ui32MstDiv = 4; + ui32BitDiv = 40; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_32K : + ui32MstDiv = 3; + ui32BitDiv = 30; + ui32WordDiv = 25; + break; + case I2S_SAMPLE_RATE_48K : + ui32MstDiv = 2; + ui32BitDiv = 20; + ui32WordDiv = 25; + break; + } + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); + + // Make sure the audio clock generation is disabled before reconfiguring. + PRCMAudioClockDisable(); + + // Make sure to compensate the Frame clock division factor if using single + // phase format. + if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) + { + ui32WordDiv -= 1; + } + + // Write the clock division factors. + HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; + HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; + HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; + + // Configure the Word clock format and polarity. + ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | + PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); + HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; +} + +void PRCMPowerDomainOn(uint32_t ui32Domains) { + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power on the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; + } +} + +void PRCMPowerDomainOff(uint32_t ui32Domains) { + // Check the arguments. + ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || + (ui32Domains & PRCM_DOMAIN_SERIAL) || + (ui32Domains & PRCM_DOMAIN_PERIPH) || + (ui32Domains & PRCM_DOMAIN_CPU) || + (ui32Domains & PRCM_DOMAIN_VIMS)); + + // Assert the request to power off the right domains. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; + } + if(ui32Domains & PRCM_DOMAIN_VIMS) + { + // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. + // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. + ASSERT(!(ui32Domains & 0x00010000)); + HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; + } + if(ui32Domains & PRCM_DOMAIN_CPU) + { + HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; + } +} + +void PRCMPeripheralRunEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralRunDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable module in Run Mode. + HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in sleep mode. + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in sleep mode + HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Enable this peripheral in deep-sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= + PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) { + // Check the arguments. + ASSERT(PRCMPeripheralValid(ui32Peripheral)); + + // Disable this peripheral in Deep Sleep mode. + HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= + ~PRCM_PERIPH_MASKBIT(ui32Peripheral); +} + +uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains) { + bool bStatus; + uint32_t ui32StatusRegister0; + uint32_t ui32StatusRegister1; + + // Check the arguments. + ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | + PRCM_DOMAIN_SERIAL | + PRCM_DOMAIN_PERIPH))); + + bStatus = true; + ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); + ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); + + // Return the correct power status. + if(ui32Domains & PRCM_DOMAIN_RFCORE) + { + bStatus = bStatus && + ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || + (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); + } + if(ui32Domains & PRCM_DOMAIN_SERIAL) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); + } + if(ui32Domains & PRCM_DOMAIN_PERIPH) + { + bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); + } + + // Return the status. + return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); +} + +void PRCMDeepSleep(void) { + // Enable deep-sleep. + HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; + + // Wait for an interrupt. + CPUwfi(); + + // Disable deep-sleep so that a future sleep will work correctly. + HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); +} + +void PRCMRetentionEnable(uint32_t ui32PowerDomain) { + uint32_t ui32Retention; + + // Check the arguments. + ASSERT(PRCM_DOMAIN_CPU & ui32PowerDomain); + + // Get the current register values. + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // Enable retention on RF core SRAM. + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFC_M; + } + + // Enable retention on VIMS cache. + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_VIMS_M; + } + + // Enable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention |= PRCM_RAMRETEN_RFCULL_M; + } + + // Reconfigure retention. + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} + +void PRCMRetentionDisable(uint32_t ui32PowerDomain) { + uint32_t ui32Retention; + + // Check the arguments. + ASSERT(PRCM_DOMAIN_CPU & ui32PowerDomain); + + // Get the current register values + ui32Retention = HWREG(PRCM_BASE + PRCM_O_RAMRETEN); + + // Disable retention on RF core SRAM + if(PRCM_DOMAIN_RFCORE & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFC_M; + } + + // Disable retention on VIMS cache + if(PRCM_DOMAIN_VIMS & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_VIMS_M; + } + + // Disable retention on RFC ULL SRAM. + if(PRCM_DOMAIN_RFCULL_SRAM & ui32PowerDomain) + { + ui32Retention &= ~PRCM_RAMRETEN_RFCULL_M; + } + + // Reconfigure retention. + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) = ui32Retention; +} + +void SMPHAcquire(uint32_t ui32Semaphore) { + // Check the arguments. + ASSERT((ui32Semaphore == SMPH_0) || + (ui32Semaphore == SMPH_1) || + (ui32Semaphore == SMPH_2) || + (ui32Semaphore == SMPH_3) || + (ui32Semaphore == SMPH_4) || + (ui32Semaphore == SMPH_5) || + (ui32Semaphore == SMPH_6) || + (ui32Semaphore == SMPH_7) || + (ui32Semaphore == SMPH_8) || + (ui32Semaphore == SMPH_9) || + (ui32Semaphore == SMPH_10) || + (ui32Semaphore == SMPH_11) || + (ui32Semaphore == SMPH_12) || + (ui32Semaphore == SMPH_13) || + (ui32Semaphore == SMPH_14) || + (ui32Semaphore == SMPH_15) || + (ui32Semaphore == SMPH_16) || + (ui32Semaphore == SMPH_17) || + (ui32Semaphore == SMPH_18) || + (ui32Semaphore == SMPH_19) || + (ui32Semaphore == SMPH_20) || + (ui32Semaphore == SMPH_21) || + (ui32Semaphore == SMPH_22) || + (ui32Semaphore == SMPH_23) || + (ui32Semaphore == SMPH_24) || + (ui32Semaphore == SMPH_25) || + (ui32Semaphore == SMPH_26) || + (ui32Semaphore == SMPH_27) || + (ui32Semaphore == SMPH_28) || + (ui32Semaphore == SMPH_29) || + (ui32Semaphore == SMPH_30) || + (ui32Semaphore == SMPH_31)); + + // Wait for semaphore to be release such that it can be claimed + // Semaphore register reads 1 when lock was acquired otherwise 0 + // (i.e. SMPH_CLAIMED). + while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == + SMPH_CLAIMED) + { + } +} + +void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth) { + uint32_t ui32MaxBitRate; + uint32_t ui32RegVal; + uint32_t ui32PreDiv; + uint32_t ui32SCR; + uint32_t ui32SPH_SPO; + + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || + (ui32Protocol == SSI_FRF_MOTO_MODE_1) || + (ui32Protocol == SSI_FRF_MOTO_MODE_2) || + (ui32Protocol == SSI_FRF_MOTO_MODE_3) || + (ui32Protocol == SSI_FRF_TI) || + (ui32Protocol == SSI_FRF_NMW)); + ASSERT((ui32Mode == SSI_MODE_MASTER) || + (ui32Mode == SSI_MODE_SLAVE) || + (ui32Mode == SSI_MODE_SLAVE_OD)); + ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || + ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); + ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); + ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); + + // Set the mode. + ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; + ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; + + // Set the clock predivider. + ui32MaxBitRate = ui32SSIClk / ui32BitRate; + ui32PreDiv = 0; + do + { + ui32PreDiv += 2; + ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; + } + while(ui32SCR > 255); + HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; + + // Set protocol and clock rate. + ui32SPH_SPO = (ui32Protocol & 3) << 6; + ui32Protocol &= SSI_CR0_FRF_M; + ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); + HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; +} + +int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Check for space to write. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) + { + HWREG(ui32Base + SSI_O_DR) = ui32Data; + return(1); + } + else + { + return(0); + } +} + +void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & + SSI_CR0_DSS_M))) == 0); + + // Wait until there is space. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) + { + } + + // Write the data to the SSI. + HWREG(ui32Base + SSI_O_DR) = ui32Data; +} + +void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Wait until there is data to be read. + while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) + { + } + + // Read data from SSI. + *pui32Data = HWREG(ui32Base + SSI_O_DR); +} + +int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) { + // Check the arguments. + ASSERT(SSIBaseValid(ui32Base)); + + // Check for data to read. + if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) + { + *pui32Data = HWREG(ui32Base + SSI_O_DR); + return(1); + } + else + { + return(0); + } +} + +void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || + (ui32Config == TIMER_CFG_ONE_SHOT_UP) || + (ui32Config == TIMER_CFG_PERIODIC) || + (ui32Config == TIMER_CFG_PERIODIC_UP) || + ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); + ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || + ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || + ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && + (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || + ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); + + // Disable the timers. + HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); + + // Set the global timer configuration. + HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; + + // Set the configuration of the A and B timers. Note that the B timer + // configuration is ignored by the hardware in 32-bit modes. + HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; + HWREG(ui32Base + GPT_O_TBMR) = + ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; +} + +void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the output levels as requested. + ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; + HWREG(ui32Base + GPT_O_CTL) = (bInvert ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & + ~(ui32Timer))); +} + +void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the stall mode. + ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; + HWREG(ui32Base + GPT_O_CTL) = (bStall ? + (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : + (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); +} + +void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) { + // Check the arguments. + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || + (ui32Timer == TIMER_BOTH)); + + // Set the wait on trigger mode for timer A. + if(ui32Timer & TIMER_A) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; + } + else + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); + } + } + + // Set the wait on trigger mode for timer B. + if(ui32Timer & TIMER_B) + { + if(bWait) + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; + } + else + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); + } + } +} + +void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) { + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; + } + } +} + +void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) { + // Check the arguments + ASSERT(TimerBaseValid(ui32Base)); + ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); + ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); + + // Set mode for timer A + if(ui32Timer & TIMER_A) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); + } + else + { + HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; + } + } + + // Set mode for timer B + if(ui32Timer & TIMER_B) + { + if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) + { + HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); + } + else + { + HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; + } + } +} + +void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample) { + uint32_t ui32Val; + + // Make sure the TRNG is disabled. + ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the startup number of samples. + ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; + ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); + HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; + + // Configure the minimum and maximum number of samples pr generated number + // and the number of clocks per sample. + HWREG(TRNG_BASE + TRNG_O_CFG0) = ( + ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | + ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | + ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); +} + +uint32_t TRNGNumberGet(uint32_t ui32Word) { + uint32_t ui32RandomNumber; + + // Check the arguments. + ASSERT((ui32Word == TRNG_HI_WORD) || + (ui32Word == TRNG_LOW_WORD)); + + // Return the right requested part of the generated number. + if(ui32Word == TRNG_HI_WORD) + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); + } + else + { + ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); + } + + // Initiate generation of new number. + HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; + + // Return the random number. + return ui32RandomNumber; +} + +void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel) { + uint32_t ui32Temp; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Read the FIFO level register. + ui32Temp = HWREG(ui32Base + UART_O_IFLS); + + // Extract the transmit and receive FIFO levels. + *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; + *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; +} + +void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config) { + uint32_t ui32Div; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + ASSERT(ui32Baud != 0); + + // Stop the UART. + UARTDisable(ui32Base); + + // Compute the fractional baud rate divider. + ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; + + // Set the baud rate. + HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; + HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; + + // Set parity, data length, and number of stop bits. + HWREG(ui32Base + UART_O_LCRH) = ui32Config; +} + +void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config) { + uint32_t ui32Int, ui32Frac; + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Compute the baud rate. + ui32Int = HWREG(ui32Base + UART_O_IBRD); + ui32Frac = HWREG(ui32Base + UART_O_FBRD); + *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); + + // Get the parity, data length, and number of stop bits. + *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & + (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | + UART_LCRH_EPS | UART_LCRH_PEN)); +} + +void UARTDisable(uint32_t ui32Base) { + + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait for end of TX. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) + { + } + + // Disable the FIFO. + HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); + + // Disable the UART. + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | + UART_CTL_RXE); +} + +int32_t UARTCharGetNonBlocking(uint32_t ui32Base) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there are any characters in the receive FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) + { + // Read and return the next character. + return(HWREG(ui32Base + UART_O_DR)); + } + else + { + // There are no characters, so return a failure. + return(-1); + } +} + +int32_t UARTCharGet(uint32_t ui32Base) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until a char is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) + { + } + + // Now get the character. + return(HWREG(ui32Base + UART_O_DR)); +} + +bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // See if there is space in the transmit FIFO. + if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) + { + // Write this character to the transmit FIFO. + HWREG(ui32Base + UART_O_DR) = ui8Data; + + // Success. + return(true); + } + else + { + // There is no space in the transmit FIFO, so return a failure. + return(false); + } +} + +void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) { + // Check the arguments. + ASSERT(UARTBaseValid(ui32Base)); + + // Wait until space is available. + while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) + { + } + + // Send the char. + HWREG(ui32Base + UART_O_DR) = ui8Data; +} + +void uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr) { + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Set the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; + } + + // Set the alternate control select bit for this channel, + // if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Set the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Set the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; + } +} + +void uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr) { + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | + UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); + + // Clear the useburst bit for this channel if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_USEBURST) + { + HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; + } + + // Clear the alternate control select bit for this channel, if set in + // ululAttr. + if(ui32Attr & UDMA_ATTR_ALTSELECT) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + } + + // Clear the high priority bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) + { + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; + } + + // Clear the request mask bit for this channel, if set in ui32Attr. + if(ui32Attr & UDMA_ATTR_REQMASK) + { + HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; + } +} + +uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) { + uint32_t ui32Attr = 0; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + + // Check to see if useburst bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_USEBURST; + } + + // Check to see if the alternate control bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_ALTSELECT; + } + + // Check to see if the high priority bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; + } + + // Check to see if the request mask bit is set for this channel. + if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) + { + ui32Attr |= UDMA_ATTR_REQMASK; + } + + // Return the configuration flags. + return(ui32Attr); +} + +void uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control) { + tDMAControlTable *pControlTable; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the fields to be + // changed, then OR in the new settings. + pControlTable[ui32ChannelStructIndex].ui32Control = + ((pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_DST_INC_M | + UDMA_SRC_INC_M | + UDMA_SIZE_M | + UDMA_ARB_M | + UDMA_NEXT_USEBURST)) | + ui32Control); +} + +void uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + uint32_t ui32Inc; + uint32_t ui32BufferBytes; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); + ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); + ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); + ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off the mode and size + // fields. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // Adjust the mode if the alt control structure is selected. + if(ui32ChannelStructIndex & UDMA_ALT_SELECT) + { + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Mode |= UDMA_MODE_ALT_SELECT; + } + } + + // Set the transfer size and mode in the control word (but don't write the + // control word yet as it could kick off a transfer). + ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); + + // Get the address increment value for the source, from the control word. + ui32Inc = (ui32Control & UDMA_SRC_INC_M); + + // Compute the ending source address of the transfer. If the source + // increment is set to none, then the ending address is the same as the + // beginning. + if(ui32Inc != UDMA_SRC_INC_NONE) + { + ui32Inc = ui32Inc >> UDMA_SRC_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); + } + + // Load the source ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; + + // Get the address increment value for the destination, from the control + // word. + ui32Inc = ui32Control & UDMA_DST_INC_M; + + // Compute the ending destination address of the transfer. If the + // destination increment is set to none, then the ending address is the + // same as the beginning. + if(ui32Inc != UDMA_DST_INC_NONE) + { + // There is a special case if this is setting up a scatter-gather + // transfer. The destination pointer needs to point to the end of + // the alternate structure for this channel instead of calculating + // the end of the buffer in the normal way. + if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || + (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) + { + pvDstAddr = + (void *)&pControlTable[ui32ChannelStructIndex | + UDMA_ALT_SELECT].ui32Spare; + } + // Not a scatter-gather transfer, calculate end pointer normally. + else + { + ui32Inc = ui32Inc >> UDMA_DST_INC_S; + ui32BufferBytes = ui32TransferSize << ui32Inc; + pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); + } + } + + // Load the destination ending address into the control block. + pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; + + // Write the new control word value. + pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; +} + +void uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG) { + tDMAControlTable *pControlTable; + tDMAControlTable *pTaskTable; + + // Check the parameters. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + ASSERT(pvTaskList != 0); + ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); + ASSERT(ui32TaskCount != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get a handy pointer to the task list. + pTaskTable = (tDMAControlTable *)pvTaskList; + + // Compute the ending address for the source pointer. This will be the + // last element of the last task in the task table. + pControlTable[ui32ChannelNum].pvSrcEndAddr = + &pTaskTable[ui32TaskCount - 1].ui32Spare; + + // Compute the ending address for the destination pointer. This will be + // the end of the alternate structure for this channel. + pControlTable[ui32ChannelNum].pvDstEndAddr = + &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; + + // Compute the control word. Most configurable items are fixed for + // scatter-gather. Item and increment sizes are all 32-bit and arb + // size must be 4. The count is the number of items in the task list + // times 4 (4 words per task). + pControlTable[ui32ChannelNum].ui32Control = + (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | + UDMA_SIZE_32 | UDMA_ARB_4 | + (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | + (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : + UDMA_MODE_MEM_SCATTER_GATHER)); + + // Scatter-gather operations can leave the alt bit set. So if doing + // back to back scatter-gather transfers, the second attempt may not + // work correctly because the alt bit is set. Therefore, clear the + // alt bit here to ensure that it is always cleared before a new SG + // transfer is started. + HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; + +} + +uint32_t uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the size field + // and the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + (UDMA_XFER_SIZE_M | UDMA_MODE_M)); + + // If the size field and mode field are 0 then the transfer is finished + // and there are no more items to transfer. + if(ui32Control == 0) + { + return(0); + } + + // Otherwise, if either the size field or more field is non-zero, then + // not all the items have been transferred. + else + { + // Shift the size field and add one, then return to user. + return((ui32Control >> UDMA_XFER_SIZE_S) + 1); + } +} + +uint32_t uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) { + tDMAControlTable *pControlTable; + uint32_t ui32Control; + + // Check the arguments. + ASSERT(uDMABaseValid(ui32Base)); + ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); + ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); + + // Get the base address of the control table. + pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); + + // Get the current control word value and mask off all but the mode field. + ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & + UDMA_MODE_M); + + // Check if scatter/gather mode, and if so, mask off the alt bit. + if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || + ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) + { + ui32Control &= ~UDMA_MODE_ALT_SELECT; + } + + // Return the mode to the caller. + return(ui32Control); +} + +void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); + if(bRoundRobin) + { + ui32Reg |= VIMS_CTL_ARB_CFG; + } + if(bPrefetch) + { + ui32Reg |= VIMS_CTL_PREF_EN; + } + + // Set the Arbitration and prefetch mode. + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ASSERT((ui32Mode == VIMS_MODE_DISABLED) || + (ui32Mode == VIMS_MODE_ENABLED) || + (ui32Mode == VIMS_MODE_OFF)); + + // Set the mode. + ui32Reg = HWREG(ui32Base + VIMS_O_CTL); + ui32Reg &= ~VIMS_CTL_MODE_M; + ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); + + HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; +} + +uint32_t VIMSModeGet(uint32_t ui32Base) { + uint32_t ui32Reg; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + + ui32Reg = HWREG(ui32Base + VIMS_O_STAT); + if(ui32Reg & VIMS_STAT_MODE_CHANGING) + { + return (VIMS_MODE_CHANGING); + } + else + { + return (ui32Reg & VIMS_STAT_MODE_M); + } +} + +void VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) { + uint32_t currentMode; + + // Check the arguments. + ASSERT(VIMSBaseValid(ui32Base)); + ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || + (ui32NewMode == VIMS_MODE_ENABLED) || + (ui32NewMode == VIMS_MODE_OFF)); + + // Make sure that only the mode bits are set in the input parameter + // (done just for security since it is critical to the code flow) + ui32NewMode &= VIMS_CTL_MODE_M; + + // Wait for any pending change to complete and get current VIMS mode + // (This is a blocking point but will typically only be a blocking point + // only if mode is changed multiple times with blocking=0) + do { + currentMode = VIMSModeGet( ui32Base ); + } while ( currentMode == VIMS_MODE_CHANGING ); + + // First check that it actually is a mode change request + if ( ui32NewMode != currentMode ) { + // Set new mode + VIMSModeSet( ui32Base, ui32NewMode ); + + // Wait for final mode change to complete - if blocking is requested + if ( blocking ) { + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for change to complete. + } + } + } +} + +void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) { + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + ASSERT((ui32Osc == OSC_RCOSC_HF) || + (ui32Osc == OSC_RCOSC_LF) || + (ui32Osc == OSC_XOSC_HF) || + (ui32Osc == OSC_XOSC_LF)); + + // Request the high frequency source clock (using 24 MHz XTAL) + if(ui32SrcClk & OSC_SRC_CLK_HF) + { + // Enable the HF XTAL as HF clock source + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, + ui32Osc); + } + + // Configure the low frequency source clock. + if(ui32SrcClk & OSC_SRC_CLK_LF) + { + // Change the clock source. + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, + DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, + ui32Osc); + } +} + +uint32_t OSCClockSourceGet(uint32_t ui32SrcClk) { + uint32_t ui32ClockSource; + + // Check the arguments. + ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || + (ui32SrcClk & OSC_SRC_CLK_HF)); + + // Return the source for the selected clock. + if(ui32SrcClk == OSC_SRC_CLK_LF) + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_LF_SRC_M, + DDI_0_OSC_STAT0_SCLK_LF_SRC_S); + } + else + { + ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, + DDI_0_OSC_STAT0_SCLK_HF_SRC_M, + DDI_0_OSC_STAT0_SCLK_HF_SRC_S); + } + return (ui32ClockSource); +} + +int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) { + // Estimate HPOSC frequency, using temperature and curve fitting parameters + uint32_t fitParams = HWREG(FCFG1_BASE + FCFG1_O_FREQ_OFFSET); + // Extract the P0,P1,P2 params, and sign extend them via shifting up/down + int32_t paramP0 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W)); + int32_t paramP1 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W)); + int32_t paramP2 = ((((int32_t) fitParams) << (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S)) + >> (32 - FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W)); + int32_t paramP3 = ((((int32_t) HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_2)) + << (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S)) + >> (32 - FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W)); + + // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency + // F_nom = nominal clock source frequency (e.g. 48.000 MHz) + // d = describes relative freq offset + + // We can estimate the d variable, using temperature compensation parameters: + // + // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 + // t = current temperature (from temp sensor) in deg C + // T0 = 27 deg C (fixed temperature constant) + int32_t tempDelta = (tempDegC - 27); + int32_t tempDeltaX2 = tempDelta * tempDelta; + int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); + + return ( d ); +} + +int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) { + // The input argument, hereby referred to simply as "d", describes the frequency offset + // of the HPOSC relative to the nominal frequency in this way: + // + // F_HPOSC = F_nom * (1 + d/(2^22)) + // + // But for use by the radio, to compensate the frequency error, we need to find the + // frequency offset "rfcFreqOffset" defined in the following format: + // + // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) + // + // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: + // + // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 + // + // Which can be rewritten into: + // + // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) + // + // = -d * [ 1 / (1 + d/(2^22)) ] + // + // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, + // we can use Taylor series (Maclaurin series) to approximate it: + // + // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) + // + // In our case, we have x = - d/(2^22), and we only include up to the first + // order term of the series, as the second order term ((d^2)/(2^44)) is very small: + // + // freqError ~= -d + d^2/(2^22) (+ small approximation error) + // + // The approximation error is negligible for our use. + + int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); + + return ( rfCoreFreqOffset ); +} + +void AUXADCDisable(void) { + // Disable the ADC reference + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); + + // Assert reset and disable the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); + + // Ensure that scaling is enabled by default before next use of the ADC + ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); + + // Flush the FIFO before disabling the clocks + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) + + // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; + + // Disable the ADC data interface + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; +} + +void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) { + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) { + // Enable the ADC reference, with the following options: + // - SRC: Set when using relative reference + // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us + uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; + if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { + adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; + } + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); + + // Enable the ADC clock + HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; + while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); + + // Enable the ADC data interface + if (trigger == AUXADC_TRIGGER_MANUAL) { + // Manual trigger: No need to configure event routing from GPT + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; + } else { + // GPT trigger: Configure event routing via MCU_EV to the AUX domain + HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; + HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; + } + + // Configure the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); + + // Release reset and enable the ADC + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); +} + +void AUXADCDisableInputScaling(void) { + ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); +} + +void AUXADCFlushFifo(void) { + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) + HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) +} + +uint32_t AUXADCReadFifo(void) { + + // Wait until there is at least one sample in the FIFO + while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); + + // Return the first sample from the FIFO + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +uint32_t AUXADCPopFifo(void) { + + // Return the first sample from the FIFO. If the FIFO is empty, this + // generates ADC FIFO underflow + return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +int32_t AUXADCGetAdjustmentGain(uint32_t refSource) { + int32_t gain; + if (refSource == AUXADC_REF_FIXED) { + // AUXADC_REF_FIXED ==> ABS_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_GAIN + gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; + } + return gain; +} + +int32_t AUXADCGetAdjustmentOffset(uint32_t refSource) { + int8_t offset; + if ( refSource == AUXADC_REF_FIXED ) { + // AUXADC_REF_FIXED ==> ABS_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; + } else { + // AUXADC_REF_VDDS_REL ==> REL_OFFSET + offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; + } + return offset; +} + +int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) { + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; +} + +int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) { + // Chop off 4 bits during calculations to avoid 32-bit overflow + fixedRefVoltage >>= 4; + microvolts >>= 4; + return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; +} + +int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) { + // Apply gain and offset adjustment + adcValue = (((adcValue + offset) * gain) + 16384) / 32768; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) { + // Apply inverse gain and offset adjustment + adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; + + // Saturate + if (adcValue < 0) { + return 0; + } else if (adcValue > 4095) { + return 4095; + } else { + return adcValue; + } +} + +void SysCtrl_DCDC_VoltageConditionalControl( void ) { + uint32_t batThreshold ; // Fractional format with 8 fractional bits. + uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. + uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. + uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register. + + // We could potentially call this function before any battery voltage measurement + // is made/available. In that case we must make sure that we do not turn off the DCDC. + // This can be done by doing nothing as long as the battery voltage is 0 (Since the + // reset value of the battery voltage register is 0). + aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); + if ( aonBatmonBat != 0 ) { + // Check if Voltage Conditional Control is enabled + // It is enabled if all the following are true: + // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). + // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) + // - Not in external regulator mode ( EXT_REG_MODE == 0 ) + ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + + if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || + (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && + (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && + (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) + { + aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ); + batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> + CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); + + if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) { + // DCDC is ON, check if it should be switched off + if ( aonBatmonBat < batThreshold ) { + aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ); + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } else { + // DCDC is OFF, check if it should be switched on + if ( aonBatmonBat > batThreshold ) { + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ; + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ; + + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; + } + } + } + } +} + +uint32_t SysCtrlResetSourceGet( void ) { + uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); + + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { + if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { + return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); + } else { + return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); + } + } else { + return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); + } +} + +int32_t AONBatMonTemperatureGetDegC( void ) { + int32_t signedTemp ; // Signed extended temperature with 8 fractional bits + int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits + int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. + + // Shift left then right to sign extend the BATMON_TEMP field + signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) + << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) + >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); + + // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly + // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); + tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); + + return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); +} + +void SetupStepVddrTrimTo( uint32_t toCode ) { + uint32_t pmctlResetctl_reg ; + int32_t targetTrim ; + int32_t currentTrim ; + + targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); + currentTrim = SetupSignExtendVddrTrimValue(( + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; + + if ( targetTrim != currentTrim ) { + pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate + } + + while ( targetTrim != currentTrim ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( targetTrim > currentTrim ) currentTrim++; + else currentTrim--; + + HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( + ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | + ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & + ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); + } + + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + + if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) + HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; + HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate + } + } +} + +void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) { + // Check for CC1352 boost mode + // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode + if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && + (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) + { + // Set VDDS_BOD trim - using masked write {MASK8:DATA8} + // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to + // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. + HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + // + // VDDS_BOD_LEVEL = 1 means that boost mode is selected + // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) + HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | + ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; + HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; + + SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; + } + + // 1. + // Do not allow DCDC to be enabled if in external regulator mode. + // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). + // + // 2. + // Adjusted battery monitor low limit in internal regulator mode. + // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. + if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { + ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); + } else { + HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; + } + + // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); + + // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + // Note: Inverse polarity + HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = + ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); +} + +void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) { + uint32_t ui32Trim; + + // Following sequence is required for using XOSCHF, if not included + // devices crashes when trying to switch to XOSCHF. + // + // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 + // register + ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); + + // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and + // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, + (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, + ui32Trim); + + // Trim XOSCHF IBIAS THERM. Get and set trim value for the + // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other + // register bit fields are set to 0. + ui32Trim = SetupGetTrimForXoscHfIbiastherm(); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, + ui32Trim< writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x20 | ( ui32Trim << 1 )); + + // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting + // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = + ( 0x10 | ( ui32Trim )); + + // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields + // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); + + // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting + // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) + // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) + // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and + // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) + ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = + ( 0x60 | ( ui32Trim << 1 )); + + // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from + // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM + // This is DDI_0_OSC_O_ATESTCTL bit[7] + // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) + // Using MASK4 write + 1 => writing to bits[7:4] + ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = + ( 0x80 | ( ui32Trim << 3 )); + + // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and + // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write + // This can be simplified since the registers are packed together in the same + // order both in FCFG1 and in the HW register. + // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] + // Using MASK8 write + 4 => writing to bits[23:16] + ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); + HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = + ( 0xFC00 | ( ui32Trim << 2 )); + + // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit + // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. + // Remaining register bit fields are set to their reset values of 0. + ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); + DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); + +} + +void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) { + uint32_t fcfg1OscConf; + uint32_t ui32Trim; +#if ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) + uint32_t currentHfClock; + uint32_t ccfgExtLfClk; +#endif + + // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { + case 2 : + // XOSC source is a 48 MHz crystal + // Do nothing (since this is the reset setting) + break; + case 1 : + // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) + + fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); + + if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { + // This is a HPOSC chip, apply HPOSC settings + // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; + + // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) + // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) + // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) + // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) + // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & + ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); + HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & + ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | + ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); + break; + } + // Not a HPOSC chip - fall through to default + default : + // XOSC source is a 24 MHz crystal (default) + // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; + break; + } + + // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; + } + + // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. + // This is typically already 0 except on Lizard where it is set in ROM-boot + HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; + + // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 + ui32Trim = SetupGetTrimForXoscHfFastStart(); + HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); + +#if ( defined( SKIP_SCLK_LF_SRC_CHANGE )) + // If SKIP_SCLK_LF_SRC_CHANGE is defined we will skip the switch-statement below, and + // remain on RCOSCHFDLF as LF source (since RCOSCHFDLF is the reset setting). + // (RCOSCHFDLF = Low frequency clock derived from RCOSC_HF). + // Note1: Function SetupAfterColdResetWakeupFromShutDownCfg3() is a ROM function in some devices (R2 and Agama) + // It must be removed from rom.h on these devices in order to avoid that the ROM version is called. + // Note2: It's not possible to enter STANDBY when running the LF clock from RCOSCHFDLF, however IDLE will work just fine. + // RCOSCHFDLF (RCOSC_HF/1536) -> SCLK_LF (=31250 Hz) + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency +#else + // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION + switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { + case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); + SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency + break; + case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + // Set SCLK_LF to use the same source as SCLK_HF + // Can be simplified a bit since possible return values for HF matches LF settings + currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); + OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); + while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { + // Wait until switched + } + ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); + SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); + IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis + // Set XOSC_LF in bypass mode to allow external 32 kHz clock + HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; + // Fall through to set XOSC_LF as SCLK_LF source + case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); + break; + default : // (=3) RCOSC_LF + OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); + break; + } +#endif // ( ! defined( SKIP_SCLK_LF_SRC_CHANGE )) + + // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 + HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = + ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << + ADI_4_AUX_ADCREF1_VTRIM_S ) & + ADI_4_AUX_ADCREF1_VTRIM_M ); + + // Sync with AON + SysCtrlAonSync(); +} + +uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) { + uint32_t ui32Fcfg1Value ; + uint32_t ui32XoscHfRow ; + uint32_t ui32XoscHfCol ; + uint32_t ui32TrimValue ; + + // Use device specific trim values located in factory configuration + // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in + // the ANABYPASS_VALUE1 register. Value for the other bit fields + // are set to 0. + + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); + ui32XoscHfRow = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); + ui32XoscHfCol = (( ui32Fcfg1Value & + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> + FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); + + if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { + // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation + // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg + // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by + // a define and sign extension must therefore be hard coded. + // ( A small test program is created verifying the code lines below: + // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + int32_t i32CustomerDeltaAdjust = + (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) + >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); + + while ( i32CustomerDeltaAdjust < 0 ) { + ui32XoscHfCol >>= 1; // COL 1 step down + if ( ui32XoscHfCol == 0 ) { // if COL below minimum + ui32XoscHfCol = 0xFFFF; // Set COL to maximum + ui32XoscHfRow >>= 1; // ROW 1 step down + if ( ui32XoscHfRow == 0 ) { // if ROW below minimum + ui32XoscHfRow = 1; // Set both ROW and COL + ui32XoscHfCol = 1; // to minimum + } + } + i32CustomerDeltaAdjust++; + } + while ( i32CustomerDeltaAdjust > 0 ) { + ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up + if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum + ui32XoscHfCol = 1; // Set COL to minimum + ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up + if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum + ui32XoscHfRow = 0xF; // Set both ROW and COL + ui32XoscHfCol = 0xFFFF; // to maximum + } + } + i32CustomerDeltaAdjust--; + } + } + + ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | + ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); + + return (ui32TrimValue); +} + +uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) { + uint32_t ui32TrimValue; + + // Use device specific trim values located in factory configuration + // area + ui32TrimValue = + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; + + ui32TrimValue |= + ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> + FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< + DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForXoscHfIbiastherm( void ) { + uint32_t ui32TrimValue; + + // Use device specific trim value located in factory configuration + // area + ui32TrimValue = + (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> + FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompTh2( void ) { + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim value located in factory configuration + // area. All defined register bit fields have corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); + ui32TrimValue = ((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> + FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< + DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> + FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< + DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompTh1( void ) { + uint32_t ui32TrimValue; + uint32_t ui32Fcfg1Value; + + // Use device specific trim values located in factory configuration + // area. All defined register bit fields have a corresponding trim + // value in the factory configuration area + ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); + ui32TrimValue = (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> + FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> + FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< + DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) { + uint32_t ui32TrimValue ; + uint32_t ui32Fcfg1Value ; + uint32_t ibiasOffset ; + uint32_t ibiasInit ; + uint32_t modeConf1 ; + int32_t deltaAdjust ; + + // Use device specific trim values located in factory configuration + // area. Register bit fields without trim values in the factory + // configuration area will be set to the value of 0. + ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); + + ibiasOffset = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; + ibiasInit = ( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> + FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; + + if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { + // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG + modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); + + // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); + deltaAdjust += (int32_t)ibiasOffset; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); + } + ibiasOffset = (uint32_t)deltaAdjust; + + deltaAdjust = + (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) + >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); + deltaAdjust += (int32_t)ibiasInit; + if ( deltaAdjust < 0 ) { + deltaAdjust = 0; + } + if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { + deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); + } + ibiasInit = (uint32_t)deltaAdjust; + } + ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | + ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; + + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> + FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< + DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> + FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< + DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); + ui32TrimValue |= (((ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> + FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< + DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + ui32TrimValue |= ((( ui32Fcfg1Value & + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> + FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << + DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); + } + + return(ui32TrimValue); +} + +uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) { + uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> + FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; + } + + return ( dblrLoopFilterResetVoltageValue ); +} + +uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; + } + + return ( getTrimForAdcShModeEnValue ); +} + +uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> + FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; + } + + return ( getTrimForAdcShVbufEnValue ); +} + +uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForXoschfCtlValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); + + getTrimForXoschfCtlValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> + FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << + DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); + } + + return ( getTrimForXoschfCtlValue ); +} + +uint32_t SetupGetTrimForXoscHfFastStart( void ) { + uint32_t ui32XoscHfFastStartValue ; + + // Get value from FCFG1 + ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> + FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; + + return ( ui32XoscHfFastStartValue ); +} + +uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) { + uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting + uint32_t fcfg1Data; + + if ( ui32Fcfg1Revision >= 0x00000020 ) { + fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); + getTrimForRadcExtCfgValue = + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> + FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << + DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); + + getTrimForRadcExtCfgValue |= + ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> + FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << + DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); + } + + return ( getTrimForRadcExtCfgValue ); +} + +uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) { + uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; + } + + return ( trimForRcOscLfIBiasTrimValue ); +} + +uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) { + uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields + + if ( ui32Fcfg1Revision >= 0x00000022 ) { + trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & + ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> + FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; + } + + return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); +} + +void SetupSetCacheModeAccordingToCcfgSetting( void ) { + // - Make sure to enable aggressive VIMS clock gating for power optimization + // Only for PG2 devices. + // - Enable cache prefetch enable as default setting + // (Slightly higher power consumption, but higher CPU performance) + // - IF ( CCFG_..._DIS_GPRAM == 1 ) + // then: Enable cache (set cache mode = 1), even if set by ROM boot code + // (This is done because it's not set by boot code when running inside + // a debugger supporting the Halt In Boot (HIB) functionality). + // else: Set MODE_GPRAM if not already set (see inline comments as well) + uint32_t vimsCtlMode0 ; + + while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { + // Do nothing - wait for an eventual ongoing mode change to complete. + // (There should typically be no wait time here, but need to be sure) + } + + // Note that Mode=0 is equal to MODE_GPRAM + vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); + +#if ( defined( DO_NOT_ENABLE_CACHE_IN_TRIM_DEVICE )) + #if ( defined( CODE_IN_FLASH )) + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + #else + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + #endif +#else + + if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { + // Enable cache (and hence disable GPRAM) + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); + } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { + // GPRAM is enabled in CCFG but not selected + // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM + HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); + while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { + // Do nothing - wait for an eventual mode change to complete (This goes fast). + } + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } else { + // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set + HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; + } +#endif +} + +void SetupSetAonRtcSubSecInc( uint32_t subSecInc ) { + // Loading a new RTCSUBSECINC value is done in 5 steps: + // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0 + // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1 + // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK + // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M ); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M ); + + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; + while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN ))); + HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0; +} + +void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) { + // Check the arguments. + ASSERT(I2SBaseValid(ui32Base)); + + // Update the next input/output pointer with the correct address. + if(bInput == true) + { + HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; + } + else + { + HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; + } +} + +uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) { + uint32_t ui32FrameClkCnt; + uint32_t ui32SysClkCnt; + uint32_t ui32PeriodSysClkCnt; + uint32_t ui32SampleStamp; + + // Get the number of Frame clock counts since last stamp. + ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); + + // Get the number of system clock ticks since last frame clock edge. + ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); + + // Get the number system clock ticks in the last frame clock period. + ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); + + // Calculate the sample stamp. + ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; + ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? + I2S_STMP_SATURATION : ui32SampleStamp; + ui32SampleStamp |= (ui32FrameClkCnt << 16); + + return (ui32SampleStamp); +} + +void PowerCtrlSourceSet(uint32_t ui32PowerConfig) { + // Check the arguments. + ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || + (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || + (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); + + // Configure the power. + if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |= + (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) + { + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &= + ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); + } + else + { + PRCMMcuUldoConfigure(true); + } +} + +void AESSetInitializationVector(const uint32_t *initializationVector) { + // Write initialization vector to the aes registers + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; + HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; +} + +void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + if (channel0Length && channel0Addr) { + // We actually want to perform an operation. Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Length && channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t AESWaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | + CRYPTO_IRQSTAT_RESULT_AVAIL_M | + CRYPTO_IRQSTAT_DMA_BUS_ERR_M | + CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; + + return irqTrigger; +} + +uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || + (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); + + uint32_t keySize = 0; + + switch (aesKeyLength) { + case AES_128_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; + break; + case AES_192_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; + break; + case AES_256_KEY_LENGTH_BYTES: + keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; + break; + } + + // Clear any previously written key at the keyLocation + AESInvalidateKey(keyStoreArea); + + // Disable the external interrupt to stop the interrupt form propagating + // from the module to the System CPU. + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // Enable internal interrupts. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; + HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; + + // Configure master control module. + HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); + + // Configure the size of keys contained within the key store + // Do not write to the register if the correct key size is already set. + // Writing to this register causes all current keys to be invalidated. + uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); + if (keySize != keyStoreKeySize) { + HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; + } + + // Enable key to write (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; + + // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). + AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); + + // Wait for the DMA operation to complete. + uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); + + // Re-enable interrupts globally. + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. + if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + // There was an error in writing to the keyStore. + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) { + // Check the arguments. + ASSERT((keyStoreArea == AES_KEY_AREA_0) || + (keyStoreArea == AES_KEY_AREA_1) || + (keyStoreArea == AES_KEY_AREA_2) || + (keyStoreArea == AES_KEY_AREA_3) || + (keyStoreArea == AES_KEY_AREA_4) || + (keyStoreArea == AES_KEY_AREA_5) || + (keyStoreArea == AES_KEY_AREA_6) || + (keyStoreArea == AES_KEY_AREA_7)); + + // Check if there is a valid key in the specified keyStoreArea + if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { + return AES_KEYSTORE_AREA_INVALID; + } + + // Enable keys to read (e.g. Key 0). + HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; + + // Wait until key is loaded to the AES module. + // We cannot simply poll the IRQ status as only an error is communicated through + // the IRQ status and not the completion of the transfer. + do { + CPUdelay(1); + } + while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); + + // Check for keyStore read error. + if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { + return AES_KEYSTORE_ERROR; + } + else { + return AES_SUCCESS; + } +} + +uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) { + // The intermediate array is used instead of a caller-provided one + // to enable a simple API with no unintuitive alignment or size requirements. + // This is a trade-off of stack-depth vs ease-of-use that came out on the + // ease-of-use side. + uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; + + // Wait until the computed tag is ready. + while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); + + // Read computed tag out from the HW registers + // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag + computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); + computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); + computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); + computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); + + memcpy(tag, computedTag, tagLength); + + return AES_SUCCESS; +} + +uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) { + uint32_t resultStatus; + // The intermediate array is allocated on the stack to ensure users do not + // point the tag they provide and the one computed at the same location. + // That would cause memcmp to compare an array against itself. We could add + // a check that verifies that the arrays are not the same. If we did that and + // modified AESReadTag to just copy all 128 bits into a provided array, + // we could save 16 bytes of stack space while making the API much more + // complicated. + uint8_t computedTag[AES_BLOCK_SIZE]; + + resultStatus = AESReadTag(computedTag, tagLength); + + if (resultStatus != AES_SUCCESS) { + return resultStatus; + } + + resultStatus = memcmp(computedTag, tag, tagLength); + + if (resultStatus != 0) { + return AES_TAG_VERIFICATION_FAILED; + } + + return AES_SUCCESS; +} + +void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) { + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if ( macLength >= 2 ) { + ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); + } + ctrlVal |= CRYPTO_AESCTL_CCM | + CRYPTO_AESCTL_CTR | + CRYPTO_AESCTL_SAVE_CONTEXT | + CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + AESSetCtrl(ctrlVal); +} + +void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) { + union { + uint32_t word[4]; + uint8_t byte[16]; + } initializationVector = {{0}}; + + initializationVector.byte[0] = 15 - nonceLength - 1; + + memcpy(&(initializationVector.byte[1]), nonce, nonceLength); + + AESSetInitializationVector(initializationVector.word); +} + + +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) + + +//***************************************************************************** +// +// Define for the maximum curve size supported by the PKA module in 32 bit +// word. +// \note PKA hardware module can support up to 384 bit curve size due to the +// 2K of PKA RAM. +// +//***************************************************************************** +#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 + +//***************************************************************************** +// +// Define for the maximum length of the big number supported by the PKA module +// in 32 bit word. +// +//***************************************************************************** +#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD + +//***************************************************************************** +// +// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that +// the base address of the parameter should not be written to a NPTR register. +// +//***************************************************************************** +#define PKA_NO_POINTER_REG 0xFF + +//***************************************************************************** +// +// NIST P224 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint224 NISTP224_generator = { + .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, + 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, + 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, + 0xBD, 0x0C, 0x0E, 0xB7, }}, + .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, + 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, + 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, + 0x88, 0x63, 0x37, 0xBD, }}, +}; + +const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, + 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, + 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, + 0x85, 0x0A, 0x05, 0xB4}}; + +const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, + 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}}; + +//***************************************************************************** +// +// NIST P256 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 NISTP256_generator = { + .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, + 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, + 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, + 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, + .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, + 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, + 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, + 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, +}; + +const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, + 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, + 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, + 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; + +const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, + 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; + +//***************************************************************************** +// +// NIST P384 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 NISTP384_generator = { + .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, + 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, + 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, + 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, + 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, + 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, + .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, + 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, + 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, + 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, + 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, + 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, +}; + +const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + +const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, + 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, + 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, + 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, + 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, + 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; + +const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, + 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, + 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; + + +//***************************************************************************** +// +// NIST P521 constants in little endian format. byte[0] is the least +// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint521 NISTP521_generator = { + .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, + 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, + 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, + 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, + 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, + 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, + 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, + 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, + 0xc6, 0x00}}, + .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, + 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, + 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, + 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, + 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, + 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, + 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, + 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, + 0x18, 0x01}}, +}; + +const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + +const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, + 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, + 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, + 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, + 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, + 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, + 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, + 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, + 0x51, 0x00}}; + +const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, + 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, + 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, + 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, + 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x01}}; + + +//***************************************************************************** +// +// Brainpool P256r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 BrainpoolP256R1_generator = { + .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, + 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, + 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, + 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, + .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, + 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, + 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, + 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, +}; + +const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, + 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, + 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, + 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, + 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, + 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; + +const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, + 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, + 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, + 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; + +const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, + 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, + 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, + 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; + +//***************************************************************************** +// +// Brainpool P384r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint384 BrainpoolP384R1_generator = { + .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, + 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, + 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, + 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, + 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, + 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, + .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, + 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, + 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, + 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, + 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, + 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, +}; + +const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, + 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, + 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, + 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, + 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, + 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, + 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, + 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, + 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; + +const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, + 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, + 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, + 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, + 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, + 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; + +const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, + 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, + 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, + 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, + 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, + 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; + +//***************************************************************************** +// +// Brainpool P512r1 constants in little endian format. byte[0] is the least +// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint512 BrainpoolP512R1_generator = { + .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, + 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, + 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, + 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, + 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, + 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, + 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, + 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, + .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, + 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, + 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, + 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, + 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, + 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, + 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, + 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, +}; + +const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, + 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, + 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, + 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, + 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, + 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, + 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, + 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, + 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, + 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, + 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, + 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; + +const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, + 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, + 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, + 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, + 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, + 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, + 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, + 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; + +const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, + 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, + 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, + 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, + 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, + 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, + 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, + 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; + +//***************************************************************************** +// +// Curve25519 constants in little endian format. byte[0] is the least +// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most +// significant. +// +//***************************************************************************** +const PKA_EccPoint256 Curve25519_generator = { + .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, + 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, + 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + +const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; + + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module, set required registers, and add an offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + uint32_t i; + uint32_t *paramWordAlias = (uint32_t *)param; + // Take the floor of paramLength in 32-bit words + uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); + + // Only copy data if it is specified. We may wish to simply allocate another buffer and get + // the required offset. + if (param) { + // Load the number in PKA RAM + for (i = 0; i < paramLengthInWords; i++) { + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. The extra zeros at the end should not matter, as the large + // number is little-endian and thus has no effect. + // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. + // However, we would not have been able to zero-out the extra few most significant + // bytes of the most significant word. That would have resulted in doing maths operations + // on whatever follows param in RAM. + if (paramLength % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the param remainder + temp = paramWordAlias[i]; + + // Zero-out all bytes beyond the end of the param + for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { + ((uint8_t *)&temp)[j] = 0; + } + + HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp; + + // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) + paramLengthInWords++; + } + } + + // Update the A, B, C, or D pointer with the offset address of the PKA RAM location + // where the number will be stored. + switch (ptrRegOffset) { + case PKA_O_APTR: + HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; + break; + case PKA_O_BPTR: + HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; + HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; + break; + case PKA_O_CPTR: + HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; + break; + case PKA_O_DPTR: + HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; + break; + } + + // Ensure 8-byte alignment of next parameter. + // Returns the offset for the next parameter. + return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); +} + +//***************************************************************************** +// +// Write a PKA parameter to the PKA module but return a larger offset. +// +//***************************************************************************** +static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) +{ + // Ensure 16-byte alignment. + return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); +} + +//***************************************************************************** +// +// Writes the result of a large number arithmetic operation to a provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t mswOffset; + uint32_t lswOffset; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + mswOffset = HWREG(PKA_BASE + PKA_O_MSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); + lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + if (mswOffset >= lswOffset) { + lengthInWords = mswOffset - lswOffset; + } + else { + return PKA_STATUS_RESULT_ADDRESS_INCORRECT; + } + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Retrieve the result of a modulo operation or the remainder of a division. +// +//***************************************************************************** +static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + uint32_t regMSWVal; + uint32_t lengthInWords; + uint32_t i; + uint32_t *resultWordAlias = (uint32_t *)resultBuf; + + // Check the arguments. + ASSERT(resultBuf); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Get the MSW register value. + regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); + + // If the result vector is zero, write back one zero byte so the caller does not need + // to handle a special error for the perhaps valid result of zero. + // They will only get the error status if they do not provide a buffer + if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { + if (*resultLength){ + if(resultBuf){ + resultBuf[0] = 0; + } + + *resultLength = 1; + + return PKA_STATUS_SUCCESS; + } + else { + return PKA_STATUS_BUF_UNDERFLOW; + } + } + + // Get the length of the result + lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); + + // Check if the provided buffer length is adequate to store the result data. + if (*resultLength < lengthInWords * sizeof(uint32_t)) { + return PKA_STATUS_BUF_UNDERFLOW; + } + + // Copy the resultant length. + *resultLength = lengthInWords * sizeof(uint32_t); + + if (resultBuf) { + // Copy the result into the resultBuf. + for (i = 0; i < lengthInWords; i++) { + resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + } + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Writes the resultant curve point of an ECC operation to the provided buffer. +// +//***************************************************************************** +static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + uint32_t i = 0; + uint32_t *xWordAlias = (uint32_t *)curvePointX; + uint32_t *yWordAlias = (uint32_t *)curvePointY; + uint32_t lengthInWordsCeiling = 0; + + // Check for the arguments. + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && + (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); + + // Verify that the operation is completed. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + if (HWREG(PKA_BASE + PKA_O_SHIFT)) { + return PKA_STATUS_FAILURE; + } + + // Check to make sure that the result vector is not the point at infinity. + if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { + return PKA_STATUS_POINT_AT_INFINITY; + } + + if (curvePointX != NULL) { + // Copy the x co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + + } + } + + lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); + + resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); + + if (curvePointY != NULL) { + // Copy the y co-ordinate value of the result from vector D into + // the curvePoint. + for (i = 0; i < (length / sizeof(uint32_t)); i++) { + yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + } + + // If the length is not a word-multiple, fill up a temporary word and copy that in + // to avoid a bus error. + if (length % sizeof(uint32_t)) { + uint32_t temp = 0; + uint8_t j; + + // Load the entire word line of the coordinate remainder + temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); + + // Write all remaining bytes to the coordinate + for (j = 0; j < length % sizeof(uint32_t); j++) { + curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; + } + } + } + + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Provides the PKA operation status. +// +//***************************************************************************** +uint32_t PKAGetOpsStatus(void) +{ + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { + return PKA_STATUS_OPERATION_BUSY; + } + else { + return PKA_STATUS_OPERATION_RDY; + } +} + +//***************************************************************************** +// +// Check if an array consists only of zeros. +// +//***************************************************************************** +bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + uint8_t arrayBits = 0; + + // We could speed things up by comparing word-wise rather than byte-wise. + // However, this extra overhead is inconsequential compared to running an + // actual PKA operation. Especially ECC operations. + for (i = 0; i < arrayLength; i++) { + arrayBits |= array[i]; + } + + if (arrayBits) { + return false; + } + else { + return true; + } + +} + +//***************************************************************************** +// +// Fill an array with zeros +// +//***************************************************************************** +void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) +{ + uint32_t i; + // Take the floor of paramLength in 32-bit words + uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); + + // Zero-out the array word-wise until i >= arrayLength + for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { + HWREG(array + i) = 0; + } + + // If i != arrayLength, there are some remaining bytes to zero-out + if (arrayLength % sizeof(uint32_t)) { + // Subtract 4 from i, since i has already overshot the array + for (i -= 4; i < arrayLength; i++) { + HWREGB(array + i * sizeof(uint32_t)); + } + } +} + +//***************************************************************************** +// +// Start the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number modulus operation. +// +//***************************************************************************** +uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(dividend); + ASSERT(divisor); + ASSERT(resultQuotientMemAddr); + ASSERT(resultRemainderMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); + + // Copy the remainder result vector address location. + if (resultRemainderMemAddr) { + *resultRemainderMemAddr = PKA_RAM_BASE + offset; + } + + // The remainder cannot ever be larger than the divisor. It should fit inside + // a buffer of that size. + offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); + + // Copy the remainder result vector address location. + if (resultQuotientMemAddr) { + *resultQuotientMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the quotient location in PKA RAM + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Start the PKCP modulo operation by setting the PKA Function register. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the quotient of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); +} + +//***************************************************************************** +// +// Get the remainder of the big number divide operation. +// +//***************************************************************************** +uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) +{ + return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); +} + + +//***************************************************************************** +// +// Start the comparison of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); + + // Set the PKA Function register for the Compare operation + // and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the comparison operation of two big numbers. +// +//***************************************************************************** +uint32_t PKABigNumCmpGetResult(void) +{ + uint32_t status; + + // verify that the operation is complete. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + // Check the COMPARE register. + switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { + case PKA_COMPARE_A_EQUALS_B: + status = PKA_STATUS_EQUAL; + break; + + case PKA_COMPARE_A_GREATER_THAN_B: + status = PKA_STATUS_A_GREATER_THAN_B; + break; + + case PKA_COMPARE_A_LESS_THAN_B: + status = PKA_STATUS_A_LESS_THAN_B; + break; + + default: + status = PKA_STATUS_FAILURE; + break; + } + + return status; +} + +//***************************************************************************** +// +// Start the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check the arguments. + ASSERT(bigNum); + ASSERT(modulus); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // set the PKA function to InvMod operation and the start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the big number inverse modulo operation. +// +//***************************************************************************** +uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) +{ + // Zero-out array in case modulo result is shorter than length + PKAZeroOutArray(resultBuf, length); + + return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(multiplicand); + ASSERT(multiplier); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); + + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the PKA function to the multiplication and start it. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the results of the big number multiplication. +// +//***************************************************************************** +uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(bigNum1); + ASSERT(bigNum2); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + +//***************************************************************************** +// +// Start the addition of two big number. +// +//***************************************************************************** +uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for arguments. + ASSERT(minuend); + ASSERT(subtrahend); + ASSERT(resultPKAMemAddr); + + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); + + offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); + + // Copy the result vector address location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load C pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; + + // Set the function for the add operation and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the addition operation on two big number. +// +//***************************************************************************** +uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) +{ + return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); +} + + +//***************************************************************************** +// +// Start ECC Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(curvePointY); + ASSERT(prime); + ASSERT(a); + ASSERT(b); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Start ECC Montgomery Multiplication. +// +//***************************************************************************** +uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(scalar); + ASSERT(curvePointX); + ASSERT(prime); + ASSERT(a); + ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); + ASSERT(resultPKAMemAddr); + + // Make sure no PKA operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); + + // Update the result location. + // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity + if (resultPKAMemAddr) { + *resultPKAMemAddr = PKA_RAM_BASE + offset; + } + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA function to Montgomery ECC-MULT and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + + +//***************************************************************************** +// +// Get the result of ECC Multiplication +// +//***************************************************************************** +uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Start the ECC Addition. +// +//***************************************************************************** +uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) +{ + uint32_t offset = 0; + + // Check for the arguments. + ASSERT(curvePoint1X); + ASSERT(curvePoint1Y); + ASSERT(curvePoint2X); + ASSERT(curvePoint2Y); + ASSERT(prime); + ASSERT(a); + ASSERT(resultPKAMemAddr); + + // Make sure no operation is in progress. + if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { + return PKA_STATUS_OPERATION_BUSY; + } + + offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); + offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); + + + offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); + offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); + + offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); + offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); + + // Copy the result vector location. + *resultPKAMemAddr = PKA_RAM_BASE + offset; + + // Load D pointer with the result location in PKA RAM. + HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; + + // Set the PKA Function to ECC-ADD and start the operation. + HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); + + return PKA_STATUS_SUCCESS; +} + +//***************************************************************************** +// +// Get the result of the ECC Addition +// +//***************************************************************************** +uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) +{ + return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); +} + +//***************************************************************************** +// +// Verify a public key against the supplied elliptic curve equation +// +//***************************************************************************** +uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) +{ + uint32_t pkaResult; + uint32_t resultAddress; + uint32_t resultLength; + uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); + uint8_t *scratchBuffer2 = scratchBuffer + 512; + + + // Verify X in range [0, prime - 1] + PKABigNumCmpStart(curvePointX, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_X_LARGER_THAN_PRIME; + } + + // Verify Y in range [0, prime - 1] + PKABigNumCmpStart(curvePointY, + prime, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { + return PKA_STATUS_Y_LARGER_THAN_PRIME; + } + + // Verify point on curve + // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P + // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b + + // tmp = X ^ 2 + PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += a + PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp *= x + PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp += b + PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + + // tmp2 = tmp % prime to ensure we have no fraction in the division. + // The number will only shrink from here on out. + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp = y^2 + PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + resultLength = 200; + pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp %= prime + PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + // If the result is not a multiple of the word-length, the PKA HW will round up + // because it deals in words only. That means that using 'length' directly + // would cause and underflow, since length refers to the actual length in bytes of + // the curve parameters while the PKA HW reports that rounded up to the next + // word boundary. + // Use 200 as the resultLength instead since we are copying to the scratch buffer + // anyway. + // Practically, this only happens with curves such as NIST-P521 that are not word + // multiples. + resultLength = 200; + pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) { + return PKA_STATUS_FAILURE; + } + + // tmp ?= tmp2 + PKABigNumCmpStart(scratchBuffer, + scratchBuffer2, + length); + + while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_EQUAL) { + return PKA_STATUS_POINT_NOT_ON_CURVE; + } + else { + return PKA_STATUS_SUCCESS; + } +} + + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); + + +void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) { + + // Clear any outstanding events. + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + if (channel0Addr) { + // Configure the DMA controller - enable both DMA channels. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; + + // Base address of the payload data in ext. memory. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; + + // Payload data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; + } + + if (channel1Addr) { + // Enable DMA channel 1. + HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; + + // Base address of the output data buffer. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; + + // Output data length in bytes, equal to the cipher text length. + HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; + } +} + +uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) { + uint32_t irqTrigger = 0; + // Wait for the DMA operation to complete. Add a delay to make sure we are + // not flooding the bus with requests too much. + do { + CPUdelay(1); + } + while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); + + // Save the IRQ trigger source + irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); + + // Clear IRQ flags + HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; + + while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); + + return irqTrigger; +} + +uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) { + ASSERT(message); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); +} + +uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) { + ASSERT(message); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); +} + +uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); +} + +uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) { + ASSERT(message); + ASSERT(totalMsgLength); + ASSERT(resultDigest); + ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || + (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); + + return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); +} + +static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) { + uint8_t digestLength = 0; + uint32_t dmaAlgorithmSelect = 0; + + SHA2ClearDigestAvailableFlag(); + + switch (hashAlgorithm) { + case SHA2_MODE_SELECT_SHA224: + digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA256: + digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; + break; + case SHA2_MODE_SELECT_SHA384: + digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + case SHA2_MODE_SELECT_SHA512: + digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; + dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; + break; + default: + return SHA2_INVALID_ALGORITHM; + } + + if (initialHash && finalHash) { + // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot + // handle running with a transfer length of 0. This workaround depends on the hash engine adding the + // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. + // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization + // and determines how many padding-bytes are added. + // Altering totalMsgLength would alter the final hash digest. + // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded + // through the DMA is irrelevant. It is overwritten internally in the hash engine. + messageLength = messageLength ? messageLength : 1; + } + + // Setting the incorrect number of bits here leads to the calculation of the correct result + // but a failure to read them out. + // The tag bit is set to read out the digest via DMA rather than through the slave interface. + SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); + + // Only load the intermediate digest if requested. + if (intermediateDigest && !initialHash) { + SHA2SetDigest(intermediateDigest, digestLength); + } + + // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section + // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. + if (finalHash) { + // This specific length must be specified in bits not bytes. + SHA2SetMessageLength(totalMsgLength * 8); + HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; + + } + + // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does + // hash operations in-place. + SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); + + return SHA2_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/ccfg.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/ccfg.c new file mode 100644 index 00000000..0d0f1657 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/ccfg.c @@ -0,0 +1,540 @@ +/****************************************************************************** +* Filename: ccfg.c + +* Description: Customer Configuration for: +* CC13x2x7, CC26x2x7 device family. +* +* Copyright (c) 2021-2022 Texas Instruments Incorporated. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1) Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2) Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3) Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ + +#ifndef __CCFC_C__ +#define __CCFC_C__ + +#include +#include "../inc/hw_types.h" +#include "../inc/hw_ccfg.h" +#include "../inc/hw_ccfg_simple_struct.h" + +/* Required for Zephyr __ti_ccfg_section macro */ +#include + +//***************************************************************************** +// +// Introduction +// +// This file contains fields used by Boot ROM, startup code, and SW radio +// stacks to configure chip behavior. +// +// Fields are documented in more details in hw_ccfg.h and CCFG.html in +// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). +// +// PLEASE NOTE: +// It is not recommended to do modifications inside the ccfg.c file. +// This file is part of the CoreSDK release and future releases may have +// important modifications and new fields added without notice. +// The recommended method to modify the CCFG settings is to have a separate +// .c file that defines the specific CCFG values to be +// overridden and then include the TI provided ccfg.c at the very end, +// giving default values for non-overriden settings. +// +// Example: +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +// //---- Use default values for all others ---- +// #include "/source/ti/devices//startup_files/ccfg.c" +// +//***************************************************************************** + +//***************************************************************************** +// +// Internal settings, forcing several bit-fields to be set to a specific value. +// +//***************************************************************************** + +//##################################### +// Force VDDR high setting (Higher output power but also higher power consumption) +// This is also called "boost mode" +// WARNING: CCFG_FORCE_VDDR_HH must not be set to 1 if running in external regulator mode. +//##################################### + +#ifndef CCFG_FORCE_VDDR_HH +#define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim +// #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) +#endif + +//***************************************************************************** +// +// Set the values of the individual bit fields. +// +//***************************************************************************** + +//##################################### +// Alternative DC/DC settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled +// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled +#endif + +#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK +#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current +#endif + +//##################################### +// XOSC override settings +//##################################### + +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET +#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 +#endif + +#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START +#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us +#endif + +//##################################### +// Power settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE +#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown +// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown +#endif + +#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE +#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode +// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode +#endif + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage +#else +#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL +// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V +#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) +#endif +#endif + +#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC +#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) +// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled +#endif + +//##################################### +// Clock settings +//##################################### + +#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from HF clock. Note: using this configuration will block the device from entering Standby mode. +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock +#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC +// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD +// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta +#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta +#endif + +#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA +#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_DIO +#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock +#endif + +#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT +#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency +#endif + +//##################################### +// Special HF clock source setting +//##################################### +#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x0 // HF source is 48 MHz TCXO +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // HF source is HPOSC (BAW) (only valid for CC2652RB) +#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal +// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (not supported) +#endif + +//##################################### +// Bootloader settings +//##################################### + +#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader +// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL +// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor +#endif + +#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE +// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor +#endif + +//##################################### +// Debug access settings +//##################################### + +#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE +#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option +// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock key +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE +// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE +//#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled +#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled +//#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +#ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE +#define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled +// #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG +#endif + +//##################################### +// Alternative IEEE 802.15.4 MAC address +//##################################### +#ifndef SET_CCFG_IEEE_MAC_0 +#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_MAC_1 +#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Alternative BLE address +//##################################### +#ifndef SET_CCFG_IEEE_BLE_0 +#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] +#endif + +#ifndef SET_CCFG_IEEE_BLE_1 +#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] +#endif + +//##################################### +// Flash erase settings +//##################################### + +#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored +#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW +#endif + +#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N +// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function +#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function +#endif + +//##################################### +// Flash image valid +//##################################### +#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID +#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table is at address +// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table address is invalid. ROM boot loader is called. +#endif + +//##################################### +// Flash sector write protection +//##################################### +#ifndef SET_CCFG_CCFG_PROT_31_0 +#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_63_32 +#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_95_64 +#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF +#endif + +#ifndef SET_CCFG_CCFG_PROT_127_96 +#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF +#endif + +//##################################### +// Select between cache or GPRAM +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM +// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) +#endif + +//##################################### +// TCXO settings +//##################################### +#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Deprecated. Must be set to 0x1. +#endif + +#ifndef SET_CCFG_MODE_CONF_1_TCXO_TYPE +#define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x1 // 1 = Clipped-sine type. +//#define SET_CCFG_MODE_CONF_1_TCXO_TYPE 0x0 // 0 = CMOS type. +#endif + +#ifndef SET_CCFG_MODE_CONF_1_TCXO_MAX_START +#define SET_CCFG_MODE_CONF_1_TCXO_MAX_START 0x7F // Maximum TCXO startup time in units of 100us. +#endif + +//***************************************************************************** +// +// CCFG values that should not be modified. +// +//***************************************************************************** +#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 +#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) + +#if ( CCFG_FORCE_VDDR_HH ) +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage +#else +#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 +#endif + +#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 +#define SET_CCFG_MODE_CONF_HF_COMP 0x1 + +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF +#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF + +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF +#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF + +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF +#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF + +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF +#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF + +//***************************************************************************** +// +// Concatenate bit fields to words. +// DO NOT EDIT! +// +//***************************************************************************** +#define DEFAULT_CCFG_EXT_LF_CLK ( \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ + ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) + +#define DEFAULT_CCFG_MODE_CONF_1 ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_TYPE )) << CCFG_MODE_CONF_1_TCXO_TYPE_S ) | ~CCFG_MODE_CONF_1_TCXO_TYPE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_TCXO_MAX_START )) << CCFG_MODE_CONF_1_TCXO_MAX_START_S ) | ~CCFG_MODE_CONF_1_TCXO_MAX_START_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) + +#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ + ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) + +#define DEFAULT_CCFG_MODE_CONF ( \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ + ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) + +#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ + ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) + +#define DEFAULT_CCFG_RTC_OFFSET ( \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) + +#define DEFAULT_CCFG_FREQ_OFFSET ( \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ + ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) + +#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 +#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 +#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 +#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 + +#define DEFAULT_CCFG_BL_CONFIG ( \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ + ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) + +#define DEFAULT_CCFG_ERASE_CONF ( \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ + ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) + +#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ + ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ + ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) + +#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID + +#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 +#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 +#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 +#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 + +//***************************************************************************** +// +// Customer Configuration Area in Lock Page +// +//***************************************************************************** +#if defined(__IAR_SYSTEMS_ICC__) +__root const ccfg_t __ccfg @ ".ccfg" = +#elif defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(__ccfg, ".ccfg") +#pragma RETAIN(__ccfg) +const ccfg_t __ccfg = +#elif defined(__llvm__) +const ccfg_t __ccfg __attribute__((section(".ccfg"), retain)) = +#else +/* Modified for Zephyr to use __ti_ccfg_section */ +const ccfg_t __ti_ccfg_section __ccfg = +#endif +{ // Mapped to address + DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last + DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. + DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) + DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 + DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 + DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC + DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 + DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 + DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 + DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC + DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 + DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 + DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 + DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC + DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 + DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 + DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 + DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC + DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 + DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 + DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 + DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC +}; + +#endif // __CCFC_C__ diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ccs.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ccs.c new file mode 100644 index 00000000..b2662f28 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ccs.c @@ -0,0 +1,232 @@ +/****************************************************************************** +* Filename: startup_ccs.c +* +* Description: Startup code for CC13x2x7, CC26x2x7 device family for use with CCS. +* +* Copyright (C) 2020-2022 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +//***************************************************************************** +// +// Check if compiler is CCS +// +//***************************************************************************** +#if !(defined(__TI_COMPILER_VERSION__)) +#error "startup_ccs.c: Unsupported compiler!" +#endif + +#include "../inc/hw_types.h" +#include "../driverlib/setup.h" + + +//***************************************************************************** +// +//! Forward declaration of the reset ISR and the default fault handlers. +// +//***************************************************************************** +void ResetISR( void ); +static void NmiSR( void ); +static void FaultISR( void ); +static void IntDefaultHandler( void ); +extern int main(void); + + +//***************************************************************************** +// +//! The entry point for the application startup code and device trim fxn. +// +//***************************************************************************** +extern void _c_int00(void); + + +//***************************************************************************** +// +// CCS: Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern unsigned long __STACK_END; + + +//! The vector table. Note that the proper constructs must be placed on this to +//! ensure that it ends up at physical address 0x0000.0000 or at the start of +//! the program if located at a start address other than 0. +// +//***************************************************************************** +#pragma DATA_SECTION(g_pfnVectors, ".resetVecs") +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)&__STACK_END), + // 0 The initial stack pointer + ResetISR, // 1 The reset handler + NmiSR, // 2 The NMI handler + FaultISR, // 3 The hard fault handler + IntDefaultHandler, // 4 Memory Management (MemManage) Fault + IntDefaultHandler, // 5 The bus fault handler + IntDefaultHandler, // 6 The usage fault handler + 0, // 7 Reserved + 0, // 8 Reserved + 0, // 9 Reserved + 0, // 10 Reserved + IntDefaultHandler, // 11 Supervisor Call (SVCall) + IntDefaultHandler, // 12 Debug monitor handler + 0, // 13 Reserved + IntDefaultHandler, // 14 The PendSV handler + IntDefaultHandler, // 15 The SysTick handler + //--- External interrupts --- + IntDefaultHandler, // 16 AON edge detect + IntDefaultHandler, // 17 I2C + IntDefaultHandler, // 18 RF Core Command & Packet Engine 1 + IntDefaultHandler, // 19 PKA Interrupt event + IntDefaultHandler, // 20 AON RTC + IntDefaultHandler, // 21 UART0 Rx and Tx + IntDefaultHandler, // 22 AUX software event 0 + IntDefaultHandler, // 23 SSI0 Rx and Tx + IntDefaultHandler, // 24 SSI1 Rx and Tx + IntDefaultHandler, // 25 RF Core Command & Packet Engine 0 + IntDefaultHandler, // 26 RF Core Hardware + IntDefaultHandler, // 27 RF Core Command Acknowledge + IntDefaultHandler, // 28 I2S + IntDefaultHandler, // 29 AUX software event 1 + IntDefaultHandler, // 30 Watchdog timer + IntDefaultHandler, // 31 Timer 0 subtimer A + IntDefaultHandler, // 32 Timer 0 subtimer B + IntDefaultHandler, // 33 Timer 1 subtimer A + IntDefaultHandler, // 34 Timer 1 subtimer B + IntDefaultHandler, // 35 Timer 2 subtimer A + IntDefaultHandler, // 36 Timer 2 subtimer B + IntDefaultHandler, // 37 Timer 3 subtimer A + IntDefaultHandler, // 38 Timer 3 subtimer B + IntDefaultHandler, // 39 Crypto Core Result available + IntDefaultHandler, // 40 uDMA Software + IntDefaultHandler, // 41 uDMA Error + IntDefaultHandler, // 42 Flash controller + IntDefaultHandler, // 43 Software Event 0 + IntDefaultHandler, // 44 AUX combined event + IntDefaultHandler, // 45 AON programmable 0 + IntDefaultHandler, // 46 Dynamic Programmable interrupt + // source (Default: PRCM) + IntDefaultHandler, // 47 AUX Comparator A + IntDefaultHandler, // 48 AUX ADC new sample or ADC DMA + // done, ADC underflow, ADC overflow + IntDefaultHandler, // 49 TRNG event + IntDefaultHandler, // 50 Combined event from Oscillator control + IntDefaultHandler, // 51 AUX Timer2 event 0 + IntDefaultHandler, // 52 UART1 combined interrupt + IntDefaultHandler // 53 Combined event from battery monitor +}; + + +//***************************************************************************** +// +//! This is the code that gets called when the processor first starts execution +//! following a reset event. Only the absolutely necessary set is performed, +//! after which the application supplied entry() routine is called. Any fancy +//! actions (such as making decisions based on the reset cause register, and +//! resetting the bits in that register) are left solely in the hands of the +//! application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Final trim of device + // + SetupTrimDevice(); + + // + // Jump to the CCS C Initialization Routine. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); + + // + // If we ever return signal Error + // + FaultISR(); +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a NMI. This +//! simply enters an infinite loop, preserving the system state for examination +//! by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a fault +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives an unexpected +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_gcc.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_gcc.c new file mode 100644 index 00000000..64f5c317 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_gcc.c @@ -0,0 +1,320 @@ +/****************************************************************************** +* Filename: startup_gcc.c +* +* Description: Startup code for CC13x2x7, CC26x2x7 device family for use with GCC. +* +* Copyright (C) 2020-2022 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +//***************************************************************************** +// +// Check if compiler is GNU Compiler +// +//***************************************************************************** +#if !(defined(__GNUC__)) +#error "startup_gcc.c: Unsupported compiler!" +#endif + +#include "../inc/hw_types.h" +#include "../driverlib/setup.h" + + +//***************************************************************************** +// +// Macro for weak symbol aliasing +// +//***************************************************************************** +#define WEAK_ALIAS(x) __attribute__ ((weak, alias(#x))) + +//***************************************************************************** +// +// Forward declaration of the reset ISR and the default fault handlers. +// +//***************************************************************************** +void ResetISR( void ); +static void NmiSRHandler( void ); +static void FaultISRHandler( void ); +static void IntDefaultHandler( void ); +extern int main( void ); + + +// Default interrupt handlers +void NmiSR(void) WEAK_ALIAS(NmiSRHandler); +void FaultISR(void) WEAK_ALIAS(FaultISRHandler); +void MPUFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void BusFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void UsageFaultIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void SVCallIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void DebugMonIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void PendSVIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void SysTickIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void GPIOIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void I2CIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void RFCCPE1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void PKAIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AONRTCIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void UART0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXSWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void SSI0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void SSI1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void RFCCPE0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void RFCHardwareIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void RFCCmdAckIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void I2SIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXSWEvent1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void WatchdogIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer0AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer0BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer1AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer1BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer2AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer2BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer3AIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void Timer3BIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void CryptoIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void uDMAIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void uDMAErrIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void FlashIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void SWEvent0IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXCombEventIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AONProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void DynProgIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXCompAIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXADCIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void TRNGIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void OSCIntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void AUXTimer2IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void UART1IntHandler(void) WEAK_ALIAS(IntDefaultHandler); +void BatMonIntHandler(void) WEAK_ALIAS(IntDefaultHandler); + + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. +// +//***************************************************************************** +extern uint32_t _ldata; +extern uint32_t _data; +extern uint32_t _edata; +extern uint32_t _bss; +extern uint32_t _ebss; +extern uint32_t _estack; + +//***************************************************************************** +// +//! The vector table. Note that the proper constructs must be placed on this to +//! ensure that it ends up at physical address 0x0000.0000 or at the start of +//! the program if located at a start address other than 0. +// +//***************************************************************************** +__attribute__ ((section(".resetVecs"), used)) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)&_estack), + // 0 The initial stack pointer + ResetISR, // 1 The reset handler + NmiSR, // 2 The NMI handler + FaultISR, // 3 The hard fault handler + MPUFaultIntHandler, // 4 Memory Management (MemManage) Fault + BusFaultIntHandler, // 5 The bus fault handler + UsageFaultIntHandler, // 6 The usage fault handler + 0, // 7 Reserved + 0, // 8 Reserved + 0, // 9 Reserved + 0, // 10 Reserved + SVCallIntHandler, // 11 Supervisor Call (SVCall) + DebugMonIntHandler, // 12 Debug monitor handler + 0, // 13 Reserved + PendSVIntHandler, // 14 The PendSV handler + SysTickIntHandler, // 15 The SysTick handler + //--- External interrupts --- + GPIOIntHandler, // 16 AON edge detect + I2CIntHandler, // 17 I2C + RFCCPE1IntHandler, // 18 RF Core Command & Packet Engine 1 + PKAIntHandler, // 19 PKA Interrupt event + AONRTCIntHandler, // 20 AON RTC + UART0IntHandler, // 21 UART0 Rx and Tx + AUXSWEvent0IntHandler, // 22 AUX software event 0 + SSI0IntHandler, // 23 SSI0 Rx and Tx + SSI1IntHandler, // 24 SSI1 Rx and Tx + RFCCPE0IntHandler, // 25 RF Core Command & Packet Engine 0 + RFCHardwareIntHandler, // 26 RF Core Hardware + RFCCmdAckIntHandler, // 27 RF Core Command Acknowledge + I2SIntHandler, // 28 I2S + AUXSWEvent1IntHandler, // 29 AUX software event 1 + WatchdogIntHandler, // 30 Watchdog timer + Timer0AIntHandler, // 31 Timer 0 subtimer A + Timer0BIntHandler, // 32 Timer 0 subtimer B + Timer1AIntHandler, // 33 Timer 1 subtimer A + Timer1BIntHandler, // 34 Timer 1 subtimer B + Timer2AIntHandler, // 35 Timer 2 subtimer A + Timer2BIntHandler, // 36 Timer 2 subtimer B + Timer3AIntHandler, // 37 Timer 3 subtimer A + Timer3BIntHandler, // 38 Timer 3 subtimer B + CryptoIntHandler, // 39 Crypto Core Result available + uDMAIntHandler, // 40 uDMA Software + uDMAErrIntHandler, // 41 uDMA Error + FlashIntHandler, // 42 Flash controller + SWEvent0IntHandler, // 43 Software Event 0 + AUXCombEventIntHandler, // 44 AUX combined event + AONProgIntHandler, // 45 AON programmable 0 + DynProgIntHandler, // 46 Dynamic Programmable interrupt + // source (Default: PRCM) + AUXCompAIntHandler, // 47 AUX Comparator A + AUXADCIntHandler, // 48 AUX ADC new sample or ADC DMA + // done, ADC underflow, ADC overflow + TRNGIntHandler, // 49 TRNG event + OSCIntHandler, // 50 Combined event from Oscillator control + AUXTimer2IntHandler, // 51 AUX Timer2 event 0 + UART1IntHandler, // 52 UART1 combined interrupt + BatMonIntHandler // 53 Combined event from battery monitor +}; + + +//***************************************************************************** +// +//! This is the code that gets called when the processor first starts execution +//! following a reset event. Only the absolutely necessary set is performed, +//! after which the application supplied entry() routine is called. Any fancy +//! actions (such as making decisions based on the reset cause register, and +//! resetting the bits in that register) are left solely in the hands of the +//! application. +// +//***************************************************************************** +void +ResetISR(void) +{ + uint32_t *pSrc; + uint32_t *pDest; + + // + // Final trim of device + // + SetupTrimDevice(); + + // + // Copy the data segment initializers from FLASH to SRAM. + // + pSrc = &_ldata; + for(pDest = &_data; pDest < &_edata; ) + { + *pDest++ = *pSrc++; + } + + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Enable the FPU + // CPACR is located at address 0xE000ED88 + // Set bits 20-23 in CPACR to enable CP10 and CP11 coprocessors + // + __asm(" ldr.w r0, =0xE000ED88\n" + " ldr r1, [r0]\n" + " orr r1, r1, #(0xF << 20)\n" + " str r1, [r0]\n"); + + // + // Call the application's entry point. + // + main(); + + // + // If we ever return signal Error + // + FaultISR(); +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a NMI. This +//! simply enters an infinite loop, preserving the system state for examination +//! by a debugger. +// +//***************************************************************************** +static void +NmiSRHandler(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a fault +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +FaultISRHandler(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives an unexpected +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_iar.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_iar.c new file mode 100644 index 00000000..72384662 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_iar.c @@ -0,0 +1,332 @@ +/****************************************************************************** +* Filename: startup_iar.c +* +* Description: Startup code for CC13x2x7, CC26x2x7 device family for use with IAR. +* +* Copyright (C) 2020-2022 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +//***************************************************************************** +// +// Check if compiler is IAR +// +//***************************************************************************** +#if !(defined(__IAR_SYSTEMS_ICC__)) +#error "startup_iar.c: Unsupported compiler!" +#endif + + +// We need intrinsic functions for IAR (if used in source code) +#include +#include "../inc/hw_types.h" +#include "../driverlib/setup.h" + + +//***************************************************************************** +// +//! Forward declaration of the reset ISR and the default fault handlers. +// +//***************************************************************************** +void ResetISR( void ); +static void NmiSRHandler( void ); +static void FaultISRHandler( void ); +static void IntDefaultHandler( void ); +extern int main( void ); + +extern void NmiSR( void ); +extern void FaultISR( void ); +extern void MPUFaultIntHandler( void ); +extern void BusFaultIntHandler( void ); +extern void UsageFaultIntHandler( void ); +extern void SVCallIntHandler( void ); +extern void DebugMonIntHandler( void ); +extern void PendSVIntHandler( void ); +extern void SysTickIntHandler( void ); +extern void GPIOIntHandler( void ); +extern void I2CIntHandler( void ); +extern void RFCCPE1IntHandler( void ); +extern void PKAIntHandler( void ); +extern void AONRTCIntHandler( void ); +extern void UART0IntHandler( void ); +extern void AUXSWEvent0IntHandler( void ); +extern void SSI0IntHandler( void ); +extern void SSI1IntHandler( void ); +extern void RFCCPE0IntHandler( void ); +extern void RFCHardwareIntHandler( void ); +extern void RFCCmdAckIntHandler( void ); +extern void I2SIntHandler( void ); +extern void AUXSWEvent1IntHandler( void ); +extern void WatchdogIntHandler( void ); +extern void Timer0AIntHandler( void ); +extern void Timer0BIntHandler( void ); +extern void Timer1AIntHandler( void ); +extern void Timer1BIntHandler( void ); +extern void Timer2AIntHandler( void ); +extern void Timer2BIntHandler( void ); +extern void Timer3AIntHandler( void ); +extern void Timer3BIntHandler( void ); +extern void CryptoIntHandler( void ); +extern void uDMAIntHandler( void ); +extern void uDMAErrIntHandler( void ); +extern void FlashIntHandler( void ); +extern void SWEvent0IntHandler( void ); +extern void AUXCombEventIntHandler( void ); +extern void AONProgIntHandler( void ); +extern void DynProgIntHandler( void ); +extern void AUXCompAIntHandler( void ); +extern void AUXADCIntHandler( void ); +extern void TRNGIntHandler( void ); +extern void OSCIntHandler( void ); +extern void AUXTimer2IntHandler( void ); +extern void UART1IntHandler( void ); +extern void BatMonIntHandler( void ); + +// Default interrupt handlers +#pragma weak NmiSR = NmiSRHandler +#pragma weak FaultISR = FaultISRHandler +#pragma weak MPUFaultIntHandler = IntDefaultHandler +#pragma weak BusFaultIntHandler = IntDefaultHandler +#pragma weak UsageFaultIntHandler = IntDefaultHandler +#pragma weak SVCallIntHandler = IntDefaultHandler +#pragma weak DebugMonIntHandler = IntDefaultHandler +#pragma weak PendSVIntHandler = IntDefaultHandler +#pragma weak SysTickIntHandler = IntDefaultHandler +#pragma weak GPIOIntHandler = IntDefaultHandler +#pragma weak I2CIntHandler = IntDefaultHandler +#pragma weak RFCCPE1IntHandler = IntDefaultHandler +#pragma weak PKAIntHandler = IntDefaultHandler +#pragma weak AONRTCIntHandler = IntDefaultHandler +#pragma weak UART0IntHandler = IntDefaultHandler +#pragma weak AUXSWEvent0IntHandler = IntDefaultHandler +#pragma weak SSI0IntHandler = IntDefaultHandler +#pragma weak SSI1IntHandler = IntDefaultHandler +#pragma weak RFCCPE0IntHandler = IntDefaultHandler +#pragma weak RFCHardwareIntHandler = IntDefaultHandler +#pragma weak RFCCmdAckIntHandler = IntDefaultHandler +#pragma weak I2SIntHandler = IntDefaultHandler +#pragma weak AUXSWEvent1IntHandler = IntDefaultHandler +#pragma weak WatchdogIntHandler = IntDefaultHandler +#pragma weak Timer0AIntHandler = IntDefaultHandler +#pragma weak Timer0BIntHandler = IntDefaultHandler +#pragma weak Timer1AIntHandler = IntDefaultHandler +#pragma weak Timer1BIntHandler = IntDefaultHandler +#pragma weak Timer2AIntHandler = IntDefaultHandler +#pragma weak Timer2BIntHandler = IntDefaultHandler +#pragma weak Timer3AIntHandler = IntDefaultHandler +#pragma weak Timer3BIntHandler = IntDefaultHandler +#pragma weak CryptoIntHandler = IntDefaultHandler +#pragma weak uDMAIntHandler = IntDefaultHandler +#pragma weak uDMAErrIntHandler = IntDefaultHandler +#pragma weak FlashIntHandler = IntDefaultHandler +#pragma weak SWEvent0IntHandler = IntDefaultHandler +#pragma weak AUXCombEventIntHandler = IntDefaultHandler +#pragma weak AONProgIntHandler = IntDefaultHandler +#pragma weak DynProgIntHandler = IntDefaultHandler +#pragma weak AUXCompAIntHandler = IntDefaultHandler +#pragma weak AUXADCIntHandler = IntDefaultHandler +#pragma weak TRNGIntHandler = IntDefaultHandler +#pragma weak OSCIntHandler = IntDefaultHandler +#pragma weak AUXTimer2IntHandler = IntDefaultHandler +#pragma weak UART1IntHandler = IntDefaultHandler +#pragma weak BatMonIntHandler = IntDefaultHandler + +//***************************************************************************** +// +//! The entry point for the application startup code. +// +//***************************************************************************** +extern void __iar_program_start(void); + +//***************************************************************************** +// +//! Get stack start (highest address) symbol from linker file. +// +//***************************************************************************** +extern const void* STACK_TOP; + +// It is required to place something in the CSTACK segment to get the stack +// check feature in IAR to work as expected +__root static void* dummy_stack @ ".stack"; + + +//***************************************************************************** +// +//! The vector table. Note that the proper constructs must be placed on this to +//! ensure that it ends up at physical address 0x0000.0000 or at the start of +//! the program if located at a start address other than 0. +// +//***************************************************************************** +__root void (* const __vector_table[])(void) @ ".resetVecs" = +{ + (void (*)(void))&STACK_TOP, // 0 The initial stack pointer + ResetISR, // 1 The reset handler + NmiSR, // 2 The NMI handler + FaultISR, // 3 The hard fault handler + MPUFaultIntHandler, // 4 Memory Management (MemManage) Fault + BusFaultIntHandler, // 5 The bus fault handler + UsageFaultIntHandler, // 6 The usage fault handler + 0, // 7 Reserved + 0, // 8 Reserved + 0, // 9 Reserved + 0, // 10 Reserved + SVCallIntHandler, // 11 Supervisor Call (SVCall) + DebugMonIntHandler, // 12 Debug monitor handler + 0, // 13 Reserved + PendSVIntHandler, // 14 The PendSV handler + SysTickIntHandler, // 15 The SysTick handler + //--- External interrupts --- + GPIOIntHandler, // 16 AON edge detect + I2CIntHandler, // 17 I2C + RFCCPE1IntHandler, // 18 RF Core Command & Packet Engine 1 + PKAIntHandler, // 19 PKA Interrupt event + AONRTCIntHandler, // 20 AON RTC + UART0IntHandler, // 21 UART0 Rx and Tx + AUXSWEvent0IntHandler, // 22 AUX software event 0 + SSI0IntHandler, // 23 SSI0 Rx and Tx + SSI1IntHandler, // 24 SSI1 Rx and Tx + RFCCPE0IntHandler, // 25 RF Core Command & Packet Engine 0 + RFCHardwareIntHandler, // 26 RF Core Hardware + RFCCmdAckIntHandler, // 27 RF Core Command Acknowledge + I2SIntHandler, // 28 I2S + AUXSWEvent1IntHandler, // 29 AUX software event 1 + WatchdogIntHandler, // 30 Watchdog timer + Timer0AIntHandler, // 31 Timer 0 subtimer A + Timer0BIntHandler, // 32 Timer 0 subtimer B + Timer1AIntHandler, // 33 Timer 1 subtimer A + Timer1BIntHandler, // 34 Timer 1 subtimer B + Timer2AIntHandler, // 35 Timer 2 subtimer A + Timer2BIntHandler, // 36 Timer 2 subtimer B + Timer3AIntHandler, // 37 Timer 3 subtimer A + Timer3BIntHandler, // 38 Timer 3 subtimer B + CryptoIntHandler, // 39 Crypto Core Result available + uDMAIntHandler, // 40 uDMA Software + uDMAErrIntHandler, // 41 uDMA Error + FlashIntHandler, // 42 Flash controller + SWEvent0IntHandler, // 43 Software Event 0 + AUXCombEventIntHandler, // 44 AUX combined event + AONProgIntHandler, // 45 AON programmable 0 + DynProgIntHandler, // 46 Dynamic Programmable interrupt + // source (Default: PRCM) + AUXCompAIntHandler, // 47 AUX Comparator A + AUXADCIntHandler, // 48 AUX ADC new sample or ADC DMA + // done, ADC underflow, ADC overflow + TRNGIntHandler, // 49 TRNG event + OSCIntHandler, // 50 Combined event from Oscillator control + AUXTimer2IntHandler, // 51 AUX Timer2 event 0 + UART1IntHandler, // 52 UART1 combined interrupt + BatMonIntHandler // 53 Combined event from battery monitor +}; + + +//***************************************************************************** +// +//! This is the code that gets called when the processor first starts execution +//! following a reset event. Only the absolutely necessary set is performed, +//! after which the application supplied entry() routine is called. Any fancy +//! actions (such as making decisions based on the reset cause register, and +//! resetting the bits in that register) are left solely in the hands of the +//! application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Final trim of device + // + SetupTrimDevice(); + + // + // Jump to IAR initialization routine + // + __iar_program_start(); + + // + // If we ever return signal Error + // + FaultISR(); +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a NMI. This +//! simply enters an infinite loop, preserving the system state for examination +//! by a debugger. +// +//***************************************************************************** +static void +NmiSRHandler(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a fault +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +FaultISRHandler(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives an unexpected +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ticlang.c b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ticlang.c new file mode 100644 index 00000000..95e00bf0 --- /dev/null +++ b/simplelink_lpf2/source/ti/devices/cc13x2x7_cc26x2x7/startup_files/startup_ticlang.c @@ -0,0 +1,232 @@ +/****************************************************************************** +* Filename: startup_ticlang.c +* +* Description: Startup code for CC13x2x7, CC26x2x7 device family for use with CCS. +* +* Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +//***************************************************************************** +// +// Check if compiler is TICLANG +// +//***************************************************************************** +#if !(defined(__clang__)) +#error "startup_ticlang.c: Unsupported compiler!" +#endif + +#include "../inc/hw_types.h" +#include "../driverlib/setup.h" + + +//***************************************************************************** +// +//! Forward declaration of the reset ISR and the default fault handlers. +// +//***************************************************************************** +void ResetISR( void ); +static void NmiSR( void ); +static void FaultISR( void ); +static void IntDefaultHandler( void ); +extern int main(void); + + +//***************************************************************************** +// +//! The entry point for the application startup code and device trim fxn. +// +//***************************************************************************** +extern void _c_int00(void); + + +//***************************************************************************** +// +// TIClang: Linker variable that marks the top of the stack. +// +//***************************************************************************** +extern unsigned long __STACK_END; + + +//! The vector table. Note that the proper constructs must be placed on this to +//! ensure that it ends up at physical address 0x0000.0000 or at the start of +//! the program if located at a start address other than 0. +// +//***************************************************************************** +__attribute__ ((section(".resetVecs"), retain)) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))((unsigned long)&__STACK_END), + // 0 The initial stack pointer + ResetISR, // 1 The reset handler + NmiSR, // 2 The NMI handler + FaultISR, // 3 The hard fault handler + IntDefaultHandler, // 4 Memory Management (MemManage) Fault + IntDefaultHandler, // 5 The bus fault handler + IntDefaultHandler, // 6 The usage fault handler + 0, // 7 Reserved + 0, // 8 Reserved + 0, // 9 Reserved + 0, // 10 Reserved + IntDefaultHandler, // 11 Supervisor Call (SVCall) + IntDefaultHandler, // 12 Debug monitor handler + 0, // 13 Reserved + IntDefaultHandler, // 14 The PendSV handler + IntDefaultHandler, // 15 The SysTick handler + //--- External interrupts --- + IntDefaultHandler, // 16 AON edge detect + IntDefaultHandler, // 17 Interrupt event from I2C + IntDefaultHandler, // 18 RF Core Command & Packet Engine 1 + IntDefaultHandler, // 19 PKA Interrupt event + IntDefaultHandler, // 20 AON RTC + IntDefaultHandler, // 21 UART0 Rx and Tx + IntDefaultHandler, // 22 AUX software event 0 + IntDefaultHandler, // 23 SSI0 Rx and Tx + IntDefaultHandler, // 24 SSI1 Rx and Tx + IntDefaultHandler, // 25 RF Core Command & Packet Engine 0 + IntDefaultHandler, // 26 RF Core Hardware + IntDefaultHandler, // 27 RF Core Command Acknowledge + IntDefaultHandler, // 28 I2S + IntDefaultHandler, // 29 AUX software event 1 + IntDefaultHandler, // 30 Watchdog timer + IntDefaultHandler, // 31 Timer 0 subtimer A + IntDefaultHandler, // 32 Timer 0 subtimer B + IntDefaultHandler, // 33 Timer 1 subtimer A + IntDefaultHandler, // 34 Timer 1 subtimer B + IntDefaultHandler, // 35 Timer 2 subtimer A + IntDefaultHandler, // 36 Timer 2 subtimer B + IntDefaultHandler, // 37 Timer 3 subtimer A + IntDefaultHandler, // 38 Timer 3 subtimer B + IntDefaultHandler, // 39 Crypto Core Result available + IntDefaultHandler, // 40 uDMA Software + IntDefaultHandler, // 41 uDMA Error + IntDefaultHandler, // 42 Flash controller + IntDefaultHandler, // 43 Software Event 0 + IntDefaultHandler, // 44 AUX combined event + IntDefaultHandler, // 45 AON programmable 0 + IntDefaultHandler, // 46 Dynamic Programmable interrupt + // source (Default: PRCM) + IntDefaultHandler, // 47 AUX Comparator A + IntDefaultHandler, // 48 AUX ADC new sample or ADC DMA + // done, ADC underflow, ADC overflow + IntDefaultHandler, // 49 TRNG event + IntDefaultHandler, // 50 Combined event from Oscillator control + IntDefaultHandler, // 51 AUX Timer2 event 0 + IntDefaultHandler, // 52 UART1 combined interrupt + IntDefaultHandler // 53 Combined event from battery monitor +}; + + +//***************************************************************************** +// +//! This is the code that gets called when the processor first starts execution +//! following a reset event. Only the absolutely necessary set is performed, +//! after which the application supplied entry() routine is called. Any fancy +//! actions (such as making decisions based on the reset cause register, and +//! resetting the bits in that register) are left solely in the hands of the +//! application. +// +//***************************************************************************** +void +ResetISR(void) +{ + // + // Final trim of device + // + SetupTrimDevice(); + + // + // Jump to the CCS C Initialization Routine. + // + __asm(" .global _c_int00\n" + " b.w _c_int00"); + + // + // If we ever return signal Error + // + FaultISR(); +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a NMI. This +//! simply enters an infinite loop, preserving the system state for examination +//! by a debugger. +// +//***************************************************************************** +static void +NmiSR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives a fault +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +FaultISR(void) +{ + // + // Enter an infinite loop. + // + while(1) + { + } +} + + +//***************************************************************************** +// +//! This is the code that gets called when the processor receives an unexpected +//! interrupt. This simply enters an infinite loop, preserving the system state +//! for examination by a debugger. +// +//***************************************************************************** +static void +IntDefaultHandler(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} diff --git a/simplelink_lpf2/source/ti/drivers/ADC.c b/simplelink_lpf2/source/ti/drivers/ADC.c new file mode 100644 index 00000000..9920cd94 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ADC.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ADC.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const ADC_Config ADC_config[]; +extern const uint_least8_t ADC_count; + +/* Default ADC parameters structure */ +const ADC_Params ADC_defaultParams = {.custom = NULL, .isProtected = true}; + +static bool isInitialized = false; + +/* + * ======== ADC_close ======== + */ +void ADC_close(ADC_Handle handle) +{ + ((ADC_FxnTable *)handle->fxnTablePtr)->closeFxn(handle); +} + +/* + * ======== ADC_control ======== + */ +int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (((ADC_FxnTable *)handle->fxnTablePtr)->controlFxn(handle, cmd, arg)); +} + +/* + * ======== ADC_convert ======== + */ +int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value) +{ + return (handle->fxnTablePtr->convertFxn(handle, value)); +} + +/* + * ======== ADC_convertChain ======== + */ +int_fast16_t ADC_convertChain(ADC_Handle *handleList, uint16_t *dataBuffer, uint8_t channelCount) +{ + return (handleList[0]->fxnTablePtr->convertChainFxn(handleList, dataBuffer, channelCount)); +} + +/* + * ======== ADC_convertToMicroVolts ======== + */ +uint32_t ADC_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue) +{ + return (handle->fxnTablePtr->convertToMicroVolts(handle, adcValue)); +} + +/* + * ======== ADC_init ======== + */ +void ADC_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < ADC_count; i++) + { + ADC_config[i].fxnTablePtr->initFxn((ADC_Handle) & (ADC_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== ADC_open ======== + */ +ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params) +{ + ADC_Handle handle = NULL; + + if (isInitialized && (index < ADC_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (ADC_Params *)&ADC_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (ADC_Handle) & (ADC_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== ADC_Params_init ======== + */ +void ADC_Params_init(ADC_Params *params) +{ + *params = ADC_defaultParams; +} diff --git a/simplelink_lpf2/source/ti/drivers/ADC.h b/simplelink_lpf2/source/ti/drivers/ADC.h new file mode 100644 index 00000000..388e3788 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ADC.h @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2016-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADC.h + * @brief Analog to Digital Conversion (ADC) Input Driver + * + * @anchor ti_drivers_ADC_Overview + * # Overview + * + * The ADC driver allows you to manage an Analog to Digital peripheral via + * simple and portable APIs. This driver supports sampling and converting + * raw values into microvolts. + * + *
+ * @anchor ti_drivers_ADC_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_ADC_Synopsis + * "usage summary" and a set of @ref ti_drivers_ADC_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_ADC_Synopsis + * ## Synopsis + * @anchor ti_drivers_ADC_Synopsis_Code + * @code + * // Import ADC Driver definitions + * #include + * + * // Define name for ADC channel index + * #define THERMOCOUPLE_OUT 0 + * + * // One-time init of ADC driver + * ADC_init(); + * + * // initialize optional ADC parameters + * ADC_Params params; + * ADC_Params_init(¶ms); + * params.isProtected = true; + * + * // Open ADC channels for usage + * ADC_Handle adcHandle = ADC_open(THERMOCOUPLE_OUT, ¶ms); + * + * // Sample the analog output from the Thermocouple + * ADC_convert(adcHandle, &result); + * + * // Convert the sample to microvolts + * resultUv = ADC_convertToMicroVolts(adcHandle, result); + * + * ADC_close(adcHandle); + * @endcode + * + *
+ * @anchor ti_drivers_ADC_Examples + * # Examples + * + * @li @ref ti_drivers_ADC_Examples_open "Opening an ADC instance" + * @li @ref ti_drivers_ADC_Examples_convert "Taking an ADC sample" + * @li @ref ti_drivers_ADC_Examples_convert_microvolts "Converting a sample to microvolts" + * @li @ref ti_drivers_ADC_Examples_convert_chain "Executing multi-channel sampling" + * + * @anchor ti_drivers_ADC_Examples_open + * ## Opening an ADC instance + * + * @code + * ADC_Handle adc; + * ADC_Params params; + * + * ADC_Params_init(¶ms); + * + * adc = ADC_open(0, ¶ms); + * if (adc == NULL) { + * // ADC_open() failed + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_ADC_Examples_convert + * ## Taking an ADC sample + * + * An ADC conversion with an ADC peripheral is started by calling + * ADC_convert(). The result value is returned by ADC_convert() + * once the conversion is finished. + * + * @code + * int_fast16_t res; + * uint_fast16_t adcValue; + * + * res = ADC_convert(adc, &adcValue); + * if (res == ADC_STATUS_SUCCESS) + * { + * print(adcValue); + * } + * @endcode + * + * @anchor ti_drivers_ADC_Examples_convert_microvolts + * ## Converting a sample to microvolts + * + * The result value returned by ADC_convert() is a raw value. The + * following uses ADC_convertToMicroVolts() to convert the raw value + * into microvolts. + * @code + * int_fast16_t res; + * uint_fast16_t adcValue; + * uint32_t adcValueUv; + * + * res = ADC_convert(adc, &adcValue); + * if (res == ADC_STATUS_SUCCESS) + * { + * adcValueUv = ADC_convertToMicroVolts(adc, adcValue); + * } + * @endcode + * + * @anchor ti_drivers_ADC_Examples_convert_chain + * ## Executing multi-channel sampling + * + * ADC_convertChain() provides an optimized way to perform + * ADC conversions for several ADC instances (multi-channel sampling). + * It takes a list of identically configured ADC instances and returns + * a buffer with the corresponding result values once the conversion + * is finished. One typical use-case would be reading a group of sensors + * that share the sampling duration. + * + * Should the configuration of the ADC instances differ, the configuration + * of the first instance in the list is used to set the parameters of the + * entire conversion chain. + * @code + * ADC_Handle adc[ADC_COUNT]; + * int_fast16_t res; + * uint16_t retValues[ADC_COUNT]; + * uint8_t i; + * + * res = ADC_convertChain(adc, retValues, ADC_COUNT); + * if (res == ADC_STATUS_SUCCESS) + * { + * for (i = 0; i < ADC_COUNT; i++) { + * print(retValues[i]); + * } + * } + * @endcode + * + *
+ * @anchor ti_drivers_ADC_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_ADC__include +#define ti_drivers_ADC__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @deprecated ADC_convertRawToMicroVolts() is succeeded by + * ADC_convertToMicroVolts(). + */ +#define ADC_convertRawToMicroVolts ADC_convertToMicroVolts + +/*! + * @defgroup ADC_CONTROL ADC_control command and status codes + * These ADC macros are reservations for ADC.h + * @{ + */ + +/*! + * @hideinitializer + * Common ADC_control command code reservation offset. + * ADC driver implementations should offset command codes with ADC_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0 + * #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1 + * @endcode + */ +#define ADC_CMD_RESERVED (32) + +/*! + * @hideinitializer + * Common ADC_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2 + * @endcode + */ +#define ADC_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed + * successfully. + * @{ + * @ingroup ADC_CONTROL + */ +#define ADC_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by ADC_control(). + * + * ADC_control() returns ADC_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ADC_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by ADC_control() for undefined + * command codes. + * + * ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define ADC_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup ADC_CMD Command Codes + * ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC + * driver implementations support these command codes. + * @{ + * @ingroup ADC_CONTROL + */ + +/* Add ADC_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from an ADC_open() call. + */ +typedef struct ADC_Config_ *ADC_Handle; + +/*! + * @brief ADC Parameters used with ADC_open(). + * + * ADC_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa ADC_Params_init() + */ +typedef struct +{ + void *custom; /*!< Custom argument used by driver + implementation */ + bool isProtected; /*!< By default ADC uses a semaphore + to guarantee thread safety. Setting + this parameter to 'false' will eliminate + the usage of a semaphore for thread + safety. The user is then responsible + for ensuring that parallel invocations + of ADC_convert() are thread safe. */ +} ADC_Params; + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_close(). + */ +typedef void (*ADC_CloseFxn)(ADC_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_control(). + */ +typedef int_fast16_t (*ADC_ControlFxn)(ADC_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_ConvertFxn(). + */ +typedef int_fast16_t (*ADC_ConvertFxn)(ADC_Handle handle, uint16_t *value); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_ConvertChainFxn(). + */ +typedef int_fast16_t (*ADC_ConvertChainFxn)(ADC_Handle *handleList, uint16_t *dataBuffer, uint8_t channelCount); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_convertToMicroVolts(). + */ +typedef uint32_t (*ADC_ConvertToMicroVoltsFxn)(ADC_Handle handle, uint16_t adcValue); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_init(). + */ +typedef void (*ADC_InitFxn)(ADC_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADC_open(). + */ +typedef ADC_Handle (*ADC_OpenFxn)(ADC_Handle handle, ADC_Params *params); + +/*! + * @brief The definition of an ADC function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified peripheral */ + ADC_CloseFxn closeFxn; + + /*! Function to perform implementation specific features */ + ADC_ControlFxn controlFxn; + + /*! Function to initiate an ADC single channel conversion */ + ADC_ConvertFxn convertFxn; + + /*! Function to initiate an ADC multi-channel conversion */ + ADC_ConvertChainFxn convertChainFxn; + + /*! Function to convert ADC result to microvolts */ + ADC_ConvertToMicroVoltsFxn convertToMicroVolts; + + /*! Function to initialize the given data object */ + ADC_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + ADC_OpenFxn openFxn; +} ADC_FxnTable; + +/*! + * @brief ADC driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa ADC_init() + * @sa ADC_open() + */ +typedef struct ADC_Config_ +{ + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + ADC_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} ADC_Config; + +/*! + * @brief Function to close an ADC driver instance + * + * @pre ADC_open() has to be called first. + * + * @warning This function must not be called while a conversion is in + * progress, meaning any call to #ADC_convert() and + * #ADC_convertChain() must have returned before calling + * #ADC_close() + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + */ +extern void ADC_close(ADC_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre ADC_open() has to be called first. + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] arg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #ADC_STATUS_SUCCESS The call was successful. + * @retval #ADC_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Function to perform an ADC conversion + * + * Function to perform a single channel sample conversion. + * + * @pre ADC_open() has been called + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * @param[in,out] value A pointer to a uint16_t to store the conversion + * result + * + * @retval #ADC_STATUS_SUCCESS The conversion was successful. + * @retval #ADC_STATUS_ERROR The conversion failed and @p value is + * invalid. + * + * @sa ADC_convertToMicroVolts() + */ +extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value); + +/*! + * @brief Function to perform a multi-channel ADC conversion + * + * Function to perform a multi-channel sample conversion. + * + * @pre ADC_open() has been called + * + * @param[in] handleList A list of #ADC_Handle which have returned + * from ADC_open() + * @param[in,out] dataBuffer A pointer to a uint16_t data buffer to store + * the conversion result + * @param[in] channelCount The number of channels that make up the list + * of #ADC_Handle + * + * @retval #ADC_STATUS_SUCCESS The conversion was successful. + * @retval #ADC_STATUS_ERROR The conversion failed and the data in + * @p dataBuffer is invalid. + * + * @sa ADC_convert() + */ +extern int_fast16_t ADC_convertChain(ADC_Handle *handleList, uint16_t *dataBuffer, uint8_t channelCount); + +/*! + * @brief Function to convert a raw ADC sample into microvolts. + * + * @pre ADC_convert() has to be called first. + * + * @param[in] handle An #ADC_Handle returned from ADC_open() + * + * @param[in] adcValue A sampling result return from ADC_convert() + * + * @return @p adcValue converted into microvolts + * + * @sa ADC_convert() + */ +extern uint32_t ADC_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue); + +/*! + * @brief Function to initialize the ADC driver. + * + * This function must also be called before any other ADC driver APIs. + */ +extern void ADC_init(void); + +/*! + * @brief Function to initialize the ADC peripheral + * + * Function to initialize the ADC peripheral specified by the + * particular index value. + * + * @pre ADC_init() has been called + * + * @param[in] index Index in the @p ADC_Config[] array. + * @param[in] params Pointer to an initialized #ADC_Params structure. + * If NULL, the default #ADC_Params values are used. + * + * @return An #ADC_Handle on success or NULL on error. + * + * @sa ADC_init() + * @sa ADC_close() + */ +extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params); + +/*! + * @brief Initialize an #ADC_Params structure to its default values. + * + * @param[in] params A pointer to an #ADC_Params structure. + * + * Default values are: + * @arg #ADC_Params.custom = NULL + * @arg #ADC_Params.isProtected = true + */ +extern void ADC_Params_init(ADC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ADC__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ADCBuf.c b/simplelink_lpf2/source/ti/drivers/ADCBuf.c new file mode 100644 index 00000000..748f59d2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ADCBuf.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ADCBuf.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const ADCBuf_Config ADCBuf_config[]; +extern const uint_least8_t ADCBuf_count; + +/* Default ADC parameters structure */ +const ADCBuf_Params ADCBuf_defaultParams = {.returnMode = ADCBuf_RETURN_MODE_BLOCKING, /*!< Blocking mode */ + .blockingTimeout = 25000, /*!< Timeout of 25000 RTOS ticks */ + .callbackFxn = NULL, /*!< No callback function */ + .recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT, /*!< One-shot measurement + */ + .samplingFrequency = 10000, /*!< Take samples at 10kHz */ + .custom = NULL}; + +static bool isInitialized = false; + +/* + * ======== ADCBuf_close ======== + */ +void ADCBuf_close(ADCBuf_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== ADCBuf_control ======== + */ +int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg) +{ + return handle->fxnTablePtr->controlFxn(handle, cmd, cmdArg); +} + +/* + * ======== ADCBuf_init ======== + */ +void ADCBuf_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < ADCBuf_count; i++) + { + ADCBuf_config[i].fxnTablePtr->initFxn((ADCBuf_Handle) & (ADCBuf_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== ADCBuf_open ======== + */ +ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params) +{ + ADCBuf_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < ADCBuf_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (ADCBuf_Params *)&ADCBuf_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (ADCBuf_Handle) & (ADCBuf_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== ADCBuf_Params_init ======== + */ +void ADCBuf_Params_init(ADCBuf_Params *params) +{ + *params = ADCBuf_defaultParams; +} + +/* + * ======== ADCBuf_convert ======== + */ +int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) +{ + return (handle->fxnTablePtr->convertFxn(handle, conversions, channelCount)); +} + +/* + * ======== ADCBuf_convertCancel ======== + */ +int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle) +{ + return (handle->fxnTablePtr->convertCancelFxn(handle)); +} + +/* + * ======== ADCBuf_getResolution ======== + */ +uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle) +{ + return (handle->fxnTablePtr->getResolutionFxn(handle)); +} + +/* + * ======== ADCBuf_adjustRawValues ======== + */ +int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan) +{ + return (handle->fxnTablePtr->adjustRawValuesFxn(handle, sampleBuf, sampleCount, adcChan)); +} + +/* + * ======== ADCBuf_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChan, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount) +{ + return (handle->fxnTablePtr->convertAdjustedToMicroVoltsFxn(handle, + adcChan, + adjustedSampleBuffer, + outputMicroVoltBuffer, + sampleCount)); +} diff --git a/simplelink_lpf2/source/ti/drivers/ADCBuf.h b/simplelink_lpf2/source/ti/drivers/ADCBuf.h new file mode 100644 index 00000000..28964731 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ADCBuf.h @@ -0,0 +1,828 @@ +/* + * Copyright (c) 2016-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file ADCBuf.h + * @brief Analog to Digital Conversion Buffer (ADCBuf) Input Driver + * + * @anchor ti_drivers_ADCBuf_Overview + * # Overview + * + * The ADCBuf driver allows you to sample and convert analog signals + * at a specified frequency. The resulting samples are placed in + * a buffer provided by the application. The driver can either take @p N + * samples once or continuously sample by double-buffering and providing a + * callback to process each finished buffer. + * + *
+ * @anchor ti_drivers_ADCBuf_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_ADCBuf_Synopsis + * "usage summary" and a set of @ref ti_drivers_ADCBuf_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_ADCBuf_Synopsis + * ## Synopsis + * @anchor ti_drivers_ADCBuf_Synopsis_Code + * @code + * // Import ADCBuf Driver definitions + * #include + * + * // Define name for ADCBuf channel index + * #define PIEZOMETER_OUT 0 + * + * // Create buffer for samples + * #define ADCBUFFERSIZE 10 + * uint16_t buffer[ADCBUFFERSIZE]; + * uint32_t microvoltBuffer[ADCBUFFERSIZE]; + * + * // One time init of ADCBuf driver + * ADCBuf_init(); + * + * // Initialize optional ADCBuf parameters + * ADCBuf_Params params; + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_BLOCKING; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * + * // Open ADCBuf driver + * adcBuf = ADCBuf_open(CONFIG_ADCBUF0, ¶ms); + * + * // Setup conversion structure + * ADCBuf_Conversion conversion = {0}; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * conversion.sampleBuffer = buffer; + * conversion.adcChannel = PIEZOMETER_OUT; + * + * // Start ADCBuf conversion + * ADCBuf_convert(adcBuf, &conversion, 1) + * + * // Adjust raw ADC values and convert them to microvolts + * ADCBuf_adjustRawValues(handle, buffer, ADCBUFFERSIZE, PIEZOMETER_OUT); + * ADCBuf_convertAdjustedToMicroVolts(handle, PIEZOMETER_OUT, buffer, + * microvoltBuffer, ADCBUFFERSIZE); + * + * // Close ADCBuf driver + * ADCBuf_close(adcbuf); + * @endcode + * + *
+ * @anchor ti_drivers_ADCBuf_Examples + * # Examples + * + * @li @ref ti_drivers_ADCBuf_Examples_open "Opening an ADCBuf instance" + * @li @ref ti_drivers_ADCBuf_Examples_blocking "Using a blocking conversion" + * @li @ref ti_drivers_ADCBuf_Examples_callback "Using a callback conversion" + * + * @anchor ti_drivers_ADCBuf_Examples_open + * ## Opening an ADCBuf instance + * + * @code + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(&adcBufParams); + * + * adcBufHandle = ADCBuf_open(0, &adcBufParams); + * if (adcBufHandle == NULL) + * { + * //ADCBuf_open() failed. + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_ADCBuf_Examples_blocking + * ## Using a blocking conversion + * + * @code + * ADCBuf_Handle adcbuf; + * ADCBuf_Params params; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_BLOCKING; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * adcbuf = ADCBuf_open(0, ¶ms); + * if (adcbuf != NULL) + * { + * ADCBuf_Conversion conversion = {0}; + * conversion.adcChannel = PIEZOMETER_OUT; + * conversion.sampleBuffer = buffer; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcbuf, &conversion, 1) != ADCBuf_STATUS_SUCCESS) + * { + * // ADCBuf_conver() failed + * } + * } + * @endcode + * + * @anchor ti_drivers_ADCBuf_Examples_callback + * ## Using a callback conversion + * + * @code + * // ADCBuf callback function + * void adcBufCallbackFxn(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, + * void *buffer, uint32_t channel, int_fast16_t status); + * + * main() + * { + * ADCBuf_Handle adcbuf; + * ADCBuf_Params params; + * + * ADCBuf_init(); + * + * ADCBuf_Params_init(¶ms); + * params.returnMode = ADCBuf_RETURN_MODE_CALLBACK; + * params.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT; + * params.callbackFxn = adcBufCallbackFxn; + * adcbuf = ADCBuf_open(0, ¶ms); + * + * ADCBuf_Conversion conversion = {0}; + * conversion.adcChannel = PIEZOMETER_OUT; + * conversion.sampleBuffer = buffer; + * conversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcbuf, &conversion, 1) != ADCBuf_STATUS_SUCCESS) + * { + * // ADCBuf_convert() failed + * } + * + * // Pend on a semaphore + * } + * + * void adcBufCallbackFxn(ADCBuf_Handle handle, ADCBuf_Conversion *conversion, + * void *buffer, uint32_t channel, int_fast16_t status) + * { + * // Adjust raw ADC values and convert them to microvolts + * ADCBuf_adjustRawValues(handle, buffer, ADCBUFFERSIZE, + * channel); + * ADCBuf_convertAdjustedToMicroVolts(handle, channel, + * buffer, microvoltBuffer, ADCBUFFERSIZE); + * + * // Post a semaphore + * } + * + * @endcode + * + *
+ * @anchor ti_drivers_ADCBuf_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_adcbuf__include +#define ti_drivers_adcbuf__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @defgroup ADCBuf_CONTROL ADCBuf_control command and status codes + * These ADCBuf macros are reservations for ADCBuf.h + * @{ + */ + +/*! + * Common ADCBuf_control command code reservation offset. + * ADC driver implementations should offset command codes with + * ADCBuf_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0 + * #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1 + * @endcode + */ +#define ADCBuf_CMD_RESERVED (32) + +/*! + * Common ADCBuf_control status code reservation offset. + * ADC driver implementations should offset status codes with + * ADCBuf_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0 + * #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1 + * #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2 + * @endcode + */ +#define ADCBuf_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * ADCBuf_control() + * + * Functions return ADCBuf_STATUS_SUCCESS if the call was executed + * successfully. + * @{ + * @ingroup ADCBuf_CONTROL + */ +#define ADCBuf_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by ADCBuf_control(). + * + * ADCBuf_control() returns #ADCBuf_STATUS_ERROR if the control code was + * not executed successfully. + */ +#define ADCBuf_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by ADCBuf_control() for undefined + * command codes. + * + * ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is + * not recognized by the driver implementation. + */ +#define ADCBuf_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned if the function is not supported + * by a particular driver implementation. + */ +#define ADCBuf_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup ADCBuf_CMD Command Codes + * ADCBuf_CMD_* macros are general command codes for I2C_control(). Not all + * ADCBuf driver implementations support these command codes. + * @{ + * @ingroup ADCBuf_CONTROL + */ + +/* Add ADCBuf_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief A handle that is returned from an ADCBuf_open() call. + */ +typedef struct ADCBuf_Config_ *ADCBuf_Handle; + +/*! + * @brief Defines a conversion to be used with ADCBuf_convert(). + * + * @sa ADCBuf_convert() + * @sa #ADCBuf_Recurrence_Mode + * @sa #ADCBuf_Return_Mode + */ +typedef struct +{ + /*! + * Defines the number of samples to be performed on the + * ADCBuf_Conversion.channel. The application buffers provided by + * #ADCBuf_Conversion.sampleBuffer and #ADCBuf_Conversion.sampleBufferTwo + * must be large enough to hold @p samplesRequestedCount samples. + */ + uint16_t samplesRequestedCount; + + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, only this buffer is used. + */ + void *sampleBuffer; + + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, this buffer is not used. When + * using #ADCBuf_RECURRENCE_MODE_CONTINUOUS, this must point to + * a valid buffer. + * + * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + void *sampleBufferTwo; + + /*! + * Pointer to a custom argument to be passed to the #ADCBuf_Callback + * function via the #ADCBuf_Conversion structure. + * + * @note The #ADCBuf_Callback function is only called when operating in + * #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RETURN_MODE_CALLBACK + * @sa #ADCBuf_Callback + */ + void *arg; + + /*! + * ADCBuf channel to perform conversions on. Mapping of channel to pin or + * internal signal is device specific. Refer to the device specific + * implementation. + */ + uint32_t adcChannel; +} ADCBuf_Conversion; + +/*! + * @brief The definition of a callback function. + * + * When operating in #ADCBuf_RETURN_MODE_CALLBACK, the callback function + * is called when an #ADCBuf_Conversion completes. The application is + * responsible for declaring a #ADCBuf_Callback and providing a pointer + * in #ADCBuf_Params.callbackFxn. + * + * @warning The callback function is called from an interrupt context. + * + * @param[out] handle #ADCBuf_Handle used with the initial call to + * ADCBuf_convert() + * + * @param[out] conversion Pointer to the #ADCBuf_Conversion structure used + * with the initial call to ADCBuf_convert(). This structure also contains + * the custom argument specified by @p conversion.arg. + * + * @param[out] completedADCBuffer Pointer to a buffer containing + * @p conversion.samplesRequestedCount ADC samples. + * + * @param[out] completedChannel ADCBuf channel the samples were + * performed on. + * + * @param[out] status Status of the ADCBuf driver during an interrupt. + * + * @sa ADCBuf_convert() + * @sa ADCBuf_Conversion + * @sa ADCBuf_Recurrence_Mode + * @sa ADCBuf_RETURN_MODE_CALLBACK + */ +typedef void (*ADCBuf_Callback)(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel, + int_fast16_t status); + +/*! + * @brief Recurrence behavior of a #ADCBuf_Conversion specified in the + * #ADCBuf_Params. + * + * This enumeration defines the recurrence mode of a #ADCBuf_Conversion. + * After a call to ADCBuf_convert(), #ADCBuf_Conversion may either be done + * once or reoccur. + */ +typedef enum +{ + /*! + * When operating in #ADCBuf_RECURRENCE_MODE_ONE_SHOT, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RECURRENCE_MODE_ONE_SHOT, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RECURRENCE_MODE_ONE_SHOT + * can only be used in combination with #ADCBuf_RETURN_MODE_BLOCKING. + */ + ADCBuf_RECURRENCE_MODE_ONE_SHOT, + + /*! + * When operating in #ADCBuf_RECURRENCE_MODE_CONTINUOUS, calls to + * ADCBuf_convert() will return immediately. The driver will continuously + * perform #ADCBuf_Conversion.samplesRequestedCount samples and call the + * #ADCBuf_Callback function when completed. The driver + * will automatically alternate between #ADCBuf_Conversion.sampleBuffer + * and #ADCBuf_Conversion.sampleBufferTwo. A + * #ADCBuf_RECURRENCE_MODE_CONTINUOUS conversion can only be terminated + * using ADCBuf_convertCancel(). + * + * @note #ADCBuf_RECURRENCE_MODE_CONTINUOUS can only be used in + * combination with #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RETURN_MODE_CALLBACK + * @sa ADCBuf_convertCancel() + */ + ADCBuf_RECURRENCE_MODE_CONTINUOUS +} ADCBuf_Recurrence_Mode; + +/*! + * @brief Return behavior for ADCBuf_convert() specified in the + * #ADCBuf_Params + * + * This enumeration defines the return behavior for ADCBuf_convert(). + * A call to ADCBuf_convert() may either block or return immediately. + * + * @sa ADCBuf_convert + */ +typedef enum +{ + /*! + * When operating in #ADCBuf_RETURN_MODE_BLOCKING, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RETURN_MODE_BLOCKING, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RETURN_MODE_BLOCKING + * can only be used in combination with #ADCBuf_RECURRENCE_MODE_ONE_SHOT. + */ + ADCBuf_RETURN_MODE_BLOCKING, + + /*! + * When operating in #ADCBuf_RETURN_MODE_CALLBACK, calls to + * ADCBuf_convert() will return immediately. When + * #ADCBuf_Conversion.samplesRequestedCount samples are completed, + * the #ADCBuf_Params.callbackFxn function is called. + * + * @note #ADCBuf_RECURRENCE_MODE_CONTINUOUS can only be used in + * combination with #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + ADCBuf_RETURN_MODE_CALLBACK +} ADCBuf_Return_Mode; + +/*! + * @brief ADCBuf parameters used with ADCBuf_open(). + * + * #ADCBuf_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa ADCBuf_Params_init() + */ +typedef struct +{ + /*! + * Timeout in system clock ticks. This value is only valid when using + * #ADCBuf_RETURN_MODE_BLOCKING. A call to ADCBuf_convert() will block + * for a duration up to @p blockingTimeout ticks. The call to + * ADCBuf_convert() will return prior if the requested number of samples + * in #ADCBuf_Conversion.samplesRequestedCount are completed. The + * @p blockingTimeout should be large enough to allow for + * #ADCBuf_Conversion.samplesRequestedCount samples to be collected + * given the #ADCBuf_Params.samplingFrequency. + * + * @sa #ADCBuf_RETURN_MODE_BLOCKING + */ + uint32_t blockingTimeout; + + /*! + * The frequency at which the ADC will sample in Hertz (Hz). After a + * call to ADCBuf_convert(), the ADC will perform @p samplingFrequency + * samples per second. + */ + uint32_t samplingFrequency; + + /*! #ADCBuf_Return_Mode for all conversions. */ + ADCBuf_Return_Mode returnMode; + + /*! + * Pointer to a #ADCBuf_Callback function to be invoked after a + * conversion completes when operating in #ADCBuf_RETURN_MODE_CALLBACK. + */ + ADCBuf_Callback callbackFxn; + + /*! #ADCBuf_Recurrence_Mode for all conversions. */ + ADCBuf_Recurrence_Mode recurrenceMode; + + /*! Pointer to a device specific extension of the #ADCBuf_Params */ + void *custom; +} ADCBuf_Params; + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_close(). + */ +typedef void (*ADCBuf_CloseFxn)(ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_open(). + */ +typedef ADCBuf_Handle (*ADCBuf_OpenFxn)(ADCBuf_Handle handle, const ADCBuf_Params *params); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_control(). + */ +typedef int_fast16_t (*ADCBuf_ControlFxn)(ADCBuf_Handle handle, uint_fast8_t cmd, void *arg); +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_init(). + */ +typedef void (*ADCBuf_InitFxn)(ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convert(). + */ +typedef int_fast16_t (*ADCBuf_ConvertFxn)(ADCBuf_Handle handle, + ADCBuf_Conversion conversions[], + uint_fast8_t channelCount); +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertCancel(). + */ +typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_GetResolution(); + */ +typedef uint_fast8_t (*ADCBuf_GetResolutionFxn)(ADCBuf_Handle handle); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_adjustRawValues(); + */ +typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); + +/*! + * @private + * @brief A function pointer to a driver specific implementation of + * ADCBuf_convertAdjustedToMicroVolts(); + */ +typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn)(ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); + +/*! + * @brief The definition of an ADCBuf function table that contains the + * required set of functions to control a specific ADC driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified peripheral */ + ADCBuf_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + ADCBuf_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + ADCBuf_InitFxn initFxn; + /*! Function to open the specified peripheral */ + ADCBuf_OpenFxn openFxn; + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBuf_ConvertFxn convertFxn; + /*! Function to abort a conversion being carried out by the specified + peripheral */ + ADCBuf_ConvertCancelFxn convertCancelFxn; + /*! Function to get the resolution in bits of the ADC */ + ADCBuf_GetResolutionFxn getResolutionFxn; + /*! Function to adjust raw ADC return bit values to values comparable + between devices of the same type */ + ADCBuf_adjustRawValuesFxn adjustRawValuesFxn; + /*! Function to convert adjusted ADC values to microvolts */ + ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn; +} ADCBuf_FxnTable; + +/*! + * @brief ADC driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa ADCBuf_init() + * @sa ADCBuf_open() + */ +typedef struct ADCBuf_Config_ +{ + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + const ADCBuf_FxnTable *fxnTablePtr; + + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} ADCBuf_Config; + +/*! + * @brief Function to close an ADCBuf driver instance + * + * @pre ADCBuf_open() has to be called first. + * + * @pre In #ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call + * ADCBuf_convertCancel() first. + * + * @warning This function must not be called while a conversion is being + * started, meaning all calls to #ADC_convert() must have returned + * before calling #ADCBuf_close() + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + */ +extern void ADCBuf_close(ADCBuf_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre ADCBuf_open() has to be called first. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] cmdArg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #ADCBuf_STATUS_SUCCESS The call was successful. + * + * @retval #ADCBuf_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg); + +/*! + * @brief Function to initialize the ADCBuf driver. + * + * This function must also be called before any other ADCBuf driver APIs. + */ +extern void ADCBuf_init(void); + +/*! + * @brief Initialize an #ADCBuf_Params structure to its default values. + * + * @param[in] params A pointer to #ADCBuf_Params structure for + * initialization + * + * Default values are: + * @arg #ADCBuf_Params.returnMode = #ADCBuf_RETURN_MODE_BLOCKING, + * @arg #ADCBuf_Params.blockingTimeout = 25000, + * @arg #ADCBuf_Params.callbackFxn = NULL, + * @arg #ADCBuf_Params.recurrenceMode = #ADCBuf_RECURRENCE_MODE_ONE_SHOT, + * @arg #ADCBuf_Params.samplingFrequency = 10000, + * @arg #ADCBuf_Params.custom = NULL + */ +extern void ADCBuf_Params_init(ADCBuf_Params *params); + +/*! + * @brief This function opens a given ADCBuf peripheral. + * + * @param[in] index Index in the @p ADCBuf_Config[] array. + * + * @param[in] params Pointer to an initialized #ADCBuf_Params structure. + * If NULL, the default #ADCBuf_Params values are used. + * + * @return An #ADCBuf_Handle on success or NULL on error. + * + * @sa ADCBuf_close() + */ +extern ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params); + +/*! + * @brief Starts ADCBuf conversions on one or more channels. + * + * @note When using #ADCBuf_RETURN_MODE_BLOCKING, this must be called from a + * thread context. + * + * @param[in] handle An ADCBuf handle returned from ADCBuf_open() + * + * @param[in] conversions A pointer to an array of #ADCBuf_Conversion + * structures. + * + * @param[in] channelCount The number of channels to convert on in this + * call. Should be the length of the @p conversions array. Depending on the + * device, multiple simultaneous conversions may not be supported. See device + * specific implementation. + * + * @retval #ADCBuf_STATUS_SUCCESS The conversion was successful. + * @retval #ADCBuf_STATUS_ERROR The conversion failed. + * + * @pre ADCBuf_open() must have been called. + * + * @sa ADCBuf_convertCancel() + * @sa ADCBuf_Return_Mode + * @sa ADCBuf_Recurrence_Mode + * @sa ADCBuf_Conversion + */ +extern int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); + +/*! + * @brief Cancels all ADCBuf conversions in progress. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open() + * + * @retval #ADCBuf_STATUS_SUCCESS The cancel was successful. + * @retval #ADCBuf_STATUS_ERROR The cancel failed. + * + * @sa ADCBuf_convert() + */ +extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle); + +/*! + * @brief Returns the resolution in bits of the specified ADCBuf instance. + * + * @param[in] handle An #ADCBuf_Handle returned from ADCBuf_open(). + * + * @return The resolution in bits of the specified ADC. + * + * @pre ADCBuf_open() must have been called prior. + */ +extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle); + +/*! + * @brief Adjust a raw ADC output buffer. The function does + * the adjustment in-place. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open(). + * + * @param[in,out] sampleBuf A buffer full of raw sample values. + * + * @param[in] sampleCount The number of samples to adjust. + * + * @param[in] adcChan The channel the buffer was sampled on. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p sampleBuf contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR if an error occurred. + * + * @retval #ADCBuf_STATUS_UNSUPPORTED The function is not supported by the + * device specific implementation. + * + * @pre ADCBuf_convert() must have returned a valid buffer with samples. + */ +extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuf, + uint_fast16_t sampleCount, + uint32_t adcChan); + +/*! + * @brief Convert an adjusted ADC output buffer to microvolts. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open() + * + * @param[in] adcChan The ADC channel the samples were performed on. + * + * @param[in] adjustedSampleBuffer A buffer full of adjusted samples. + * + * @param[in,out] outputMicroVoltBuffer The output buffer. + * + * @param[in] sampleCount The number of samples to convert. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p outputMicroVoltBuffer contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR The operation failed. + * + * @pre ADCBuf_adjustRawValues() must be called on @p adjustedSampleBuffer. + */ +extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChan, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_adcbuf__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCBC.c b/simplelink_lpf2/source/ti/drivers/AESCBC.c new file mode 100644 index 00000000..7f08019a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCBC.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCBC.c ======== + * + * This file contains default values for the AESCBC_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESCBC_Config AESCBC_config[]; +extern const uint_least8_t AESCBC_count; + +const AESCBC_Params AESCBC_defaultParams = { + .returnBehavior = AESCBC_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCBC_Params_init ======== + */ +void AESCBC_Params_init(AESCBC_Params *params) +{ + *params = AESCBC_defaultParams; +} + +/* + * ======== AESCBC_Operation_init ======== + */ +void AESCBC_Operation_init(AESCBC_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCBC_Operation)); +} + +/* + * ======== AESCBC_OneStepOperation_init ======== + */ +void AESCBC_OneStepOperation_init(AESCBC_OneStepOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCBC_OneStepOperation)); +} + +/* + * ======== AESCBC_SegmentedOperation_init ======== + */ +void AESCBC_SegmentedOperation_init(AESCBC_SegmentedOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCBC_SegmentedOperation)); +} + +/* + * ======== AESCBC_open ======== + */ +__attribute__((weak)) AESCBC_Handle AESCBC_open(uint_least8_t index, const AESCBC_Params *params) +{ + DebugP_assert(index < AESCBC_count); + + AESCBC_Config *config = (AESCBC_Config *)&AESCBC_config[index]; + return AESCBC_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESCBC.h b/simplelink_lpf2/source/ti/drivers/AESCBC.h new file mode 100644 index 00000000..a88cc131 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCBC.h @@ -0,0 +1,1257 @@ +/* + * Copyright (c) 2018-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!*************************************************************************** + * @file AESCBC.h + * + * @brief AESCBC driver header + * + * @anchor ti_drivers_AESCBC_Overview + * # Overview # + * The Cipher Block Chaining (CBC) mode of operation is a generic + * block cipher mode of operation. It can be used with any block cipher + * including AES. + * + * CBC mode encrypts messages of any practical length that have a length + * evenly divisible by the block size. Unlike ECB, it guarantees + * confidentiality of the entire message when the message is larger than + * one block. + * + * ## Operation # + * In CBC encryption, the initialization vector (IV) is XOR'd with a block of + * plaintext and then encrypted. The output ciphertext block is then XOR'd with + * the next plaintext block and the result is encrypted. This process is repeated + * until the final block of plaintext has been encrypted. + * + * To decrypt the message, decrypt the first block of ciphertext and XOR the result + * with the IV. The result is the first plaintext block. For subsequent ciphertext + * blocks, decrypt each block and XOR the previous block of the encrypted message + * into the result. + * + * ## Padding # + * CBC operates on entire blocks of ciphertext and plaintext at a time. This + * means that message lengths must be a multiple of the block cipher block size. + * AES has a block size of 16 bytes no matter the key size. Since messages do + * not necessarily always have a length that is a multiple of 16 bytes, it may + * be necessary to pad the message to a 16-byte boundary. Padding requires + * the sender and receiver to implicitly agree on the padding convention. + * Improperly designed or implemented padding schemes may leak information + * to an attacker through a padding oracle attack for example. + * + * ## Initialization Vectors # + * The IV is generated by the party performing the encryption operation. + * Within the scope of any encryption key, the IV value must be unique. + * The IV does not need to be kept secret and is usually transmitted together + * with the ciphertext to the decrypting party. + * In CBC mode, the IVs must not be predictable. Two recommended ways to + * generate IVs is to either: + * + * - Apply the block cipher (AESCBC), using the same key used with CBC, + * to a nonce. This nonce must be unique for each key-message pair. + * A counter will usually suffice. If the same symmetric key is used + * by both parties to encrypt messages, they should agree to use a + * nonce scheme that avoids generating the same nonce and thus IV twice. + * Incrementing the counter by two and making one party use even numbers + * and the other odd numbers is a common method to avoid such collisions. + * - Use a TRNG (True Random Number Generator) or PRNG + * (Pseudo-Random Number Generator) to generate a random number for use + * as IV. + * + * ## Drawbacks # + * CBC mode has several drawbacks. Unless interfacing with legacy devices, + * it is recommended to use an AEAD (Authenticated Encryption with Associated Data) + * mode such as CCM or GCM. Below is a non-exhaustive list of reasons to use + * a different block cipher mode of operation. + * + * - CBC mode does not offer authentication or integrity guarantees. In practice, + * this means that attackers can intercept the encrypted message and manipulate + * the ciphertext before sending the message on to the receiver. While this + * does not break confidentiality and reveal the plaintext, it has enabled several + * attacks in the past. This is especially problematic given that changing the + * ciphertext of a block will only corrupt the block itself and the subsequent + * block of resultant plaintext. This property may be used to manipulate only + * certain parts of the message. + * + * - CBC mode requires message lengths to be evenly divisible by the block size. + * This necessitates a padding scheme. Improperly implemented padding schemes + * may lead to vulnerabilities that can be exploited by attackers. It often + * makes more sense to use a dedicated stream cipher such as CTR (Counter) that + * does not have this restriction. CCM and GCM both use CTR for encryption. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, CBC operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Output buffer address must be 32-bit aligned. + * + * @anchor ti_drivers_AESCBC_Usage + * # Usage # + * ## Before starting a CBC operation # + * + * Before starting a CBC operation, the application must do the following: + * - Call #AESCBC_init() to initialize the driver + * - Call #AESCBC_Params_init() to initialize the #AESCBC_Params to default values. + * - Modify the #AESCBC_Params as desired + * - Call #AESCBC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESCBC API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the appropriate AESCBC operation struct using the relevant + * operation init functions and set all fields. For example, one-step (one-shot + * or single call) operations should initialize AESCBC_Operation or + * AESCBC_OneStepOperation using AESCBC_Operation_init() or + * AESCBC_OneStepOperation_init(). For multi-step (segmented or multiple call) + * operations, AESCBC_SegmentedOperation must be initialized and set. + * + * ## Starting a CBC operation # + * + * The #AESCBC_oneStepEncrypt and #AESCBC_oneStepDecrypt functions perform a CBC operation + * in a single call. They will always be the most highly optimized routines with the + * least overhead and the fastest runtime. However, they require all plaintext + * or ciphertext to be available to the function at the start of the call. + * All devices support single call operations. + * + * ## After the CBC operation completes # + * + * After the CBC operation completes, the application should either start + * another operation or close the driver by calling #AESCBC_close(). + * + * @anchor ti_drivers_AESCBC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCBC_Synopsis_Code + * @code + * // Import AESCBC Driver definitions + * #include + * + * // Define name for AESCBC channel index + * #define AESCBC_INSTANCE 0 + * + * AESCBC_init(); + * + * handle = AESCBC_open(AESCBC_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCBC_Operation + * AESCBC_OneStepOperation operation; + * AESCBC_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCBC_oneStepEncrypt(handle, &operation); + * + * AESCBC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCBC_Examples + * ## Examples + * + * ### Single call CBC encryption with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCBC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector 0 from NIST CAPV set CBCMMT128 + * uint8_t iv[16] = {0x2f, 0xe2, 0xb3, 0x33, 0xce, 0xda, 0x8f, 0x98, + * 0xf4, 0xa9, 0x9b, 0x40, 0xd2, 0xcd, 0x34, 0xa8}; + * uint8_t plaintext[16] = {0x45, 0xcf, 0x12, 0x96, 0x4f, 0xc8, 0x24, 0xab, + * 0x76, 0x61, 0x6a, 0xe2, 0xf4, 0xbf, 0x08, 0x22}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * + * // The ciphertext should be the following after the encryption operation: + * // 0x0f, 0x61, 0xc4, 0xd4, 0x4c, 0x51, 0x47, 0xc0 + * // 0x3c, 0x19, 0x5a, 0xd7, 0xe2, 0xcc, 0x12, 0xb2 + * + * + * handle = AESCBC_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_OneStepOperation operation; + * AESCBC_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCBC_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCBC_close(handle); + * + * @endcode + * + *

The following code snippet is for CC27XX devices only and leverages the HSM which is a seperate Hardware + * Accelerator

+ * + * ### Single call CBC encryption with plaintext CryptoKey in blocking return mode using the HSM accelerator # + * @code + * + * #include + * #include + * + * ... + * + * AESCBC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector 0 from NIST CAPV set CBCMMT128 + * uint8_t iv[16] = {0x2f, 0xe2, 0xb3, 0x33, 0xce, 0xda, 0x8f, 0x98, + * 0xf4, 0xa9, 0x9b, 0x40, 0xd2, 0xcd, 0x34, 0xa8}; + * uint8_t plaintext[16] = {0x45, 0xcf, 0x12, 0x96, 0x4f, 0xc8, 0x24, 0xab, + * 0x76, 0x61, 0x6a, 0xe2, 0xf4, 0xbf, 0x08, 0x22}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * + * // The ciphertext should be the following after the encryption operation: + * // 0x0f, 0x61, 0xc4, 0xd4, 0x4c, 0x51, 0x47, 0xc0 + * // 0x3c, 0x19, 0x5a, 0xd7, 0xe2, 0xcc, 0x12, 0xb2 + * + * + * handle = AESCBC_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_OneStepOperation operation; + * AESCBC_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * + * encryptionResult = AESCBC_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCBC_close(handle); + * + * @endcode + * + * ### Single call CBC decryption with plaintext CryptoKey in callback return mode # + * + * @note The following code example presented uses a 256-bit key. However, + * CC13x1/CC26x1 and CC23x0 only support a maximum key size of 128-bits, + * so reduction of keyingMaterial would be required. + * + * @code + * + * #include + * #include + * + * ... + * + * // Test vector 0 from NIST CAPV set CBCMMT256 + * + * uint8_t iv[16] = {0xdd, 0xbb, 0xb0, 0x17, 0x3f, 0x1e, 0x2d, 0xeb, + * 0x23, 0x94, 0xa6, 0x2a, 0xa2, 0xa0, 0x24, 0x0e}; + * uint8_t ciphertext[16] = {0xd5, 0x1d, 0x19, 0xde, 0xd5, 0xca, 0x4a, 0xe1, + * 0x4b, 0x2b, 0x20, 0xb0, 0x27, 0xff, 0xb0, 0x20}; + * uint8_t keyingMaterial[32] = {0x43, 0xe9, 0x53, 0xb2, 0xae, 0xa0, 0x8a, 0x3a, + * 0xd5, 0x2d, 0x18, 0x2f, 0x58, 0xc7, 0x2b, 0x9c, + * 0x60, 0xfb, 0xe4, 0xa9, 0xca, 0x46, 0xa3, 0xcb, + * 0x89, 0xe3, 0x86, 0x38, 0x45, 0xe2, 0x2c, 0x9e}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x07, 0x27, 0x0d, 0x0e, 0x63, 0xaa, 0x36, 0xda + * // 0xed, 0x8c, 0x6a, 0xde, 0x13, 0xac, 0x1a, 0xf1 + * + * + * void cbcCallback(AESCBC_Handle handle, + * int_fast16_t returnValue, + * AESCBC_OperationUnion *operation, + * AESCBC_OperationType operationType) { + * + * if (returnValue != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * if (operationType == AESCBC_OPERATION_TYPE_DECRYPT || + * operationType == AESCBC_OPERATION_TYPE_ENCRYPT) { + * // do something with operation->oneStepOperation + * } else { + * // do something with operation->segmentedOperation + * } + * } + * + * AESCBC_OneStepOperation operation; + * + * void cbcStartFunction(void) { + * AESCBC_Handle handle; + * AESCBC_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCBC_Params_init(¶ms); + * params.returnBehavior = AESCBC_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = cbcCallback; + * + * handle = AESCBC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.iv = iv; + * + * decryptionResult = AESCBC_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CBC operation completes in the background + * } + * + * @endcode + * + * ### Multi-step CBC encryption with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * AESCBC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector 0 from NIST CAPV set CBCMMT128 + * uint8_t iv[16] = {0x2f, 0xe2, 0xb3, 0x33, 0xce, 0xda, 0x8f, 0x98, + * 0xf4, 0xa9, 0x9b, 0x40, 0xd2, 0xcd, 0x34, 0xa8}; + * uint8_t plaintext[16] = {0x45, 0xcf, 0x12, 0x96, 0x4f, 0xc8, 0x24, 0xab, + * 0x76, 0x61, 0x6a, 0xe2, 0xf4, 0xbf, 0x08, 0x22}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * + * // The ciphertext should be the following after the encryption operation: + * // 0x0f, 0x61, 0xc4, 0xd4, 0x4c, 0x51, 0x47, 0xc0 + * // 0x3c, 0x19, 0x5a, 0xd7, 0xe2, 0xcc, 0x12, 0xb2 + * + * + * handle = AESCBC_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_SegmentedOperation operation; + * AESCBC_SegmentedOperation_init(&operation); + * + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESCBC_setupEncrypt(handle, &cryptoKey); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCBC_setIV(handle, iv, AES_BLOCK_SIZE); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCBC_addData(handle, &operation); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.inputLength = 0; + * encryptionResult = AESCBC_finalize(handle, &operation); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCBC_close(handle); + * + * @endcode + * + * ### Multi-step CBC decryption with plaintext CryptoKey in callback return mode # + * + * @note The following code example presented uses a 256-bit key. However, + * CC13x1/CC26x1 and CC23x0 only support a maximum key size of 128-bits, + * so reduction of keyingMaterial would be required. + * + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * // Test vector 0 from NIST CAPV set CBCMMT256 + * + * uint8_t iv[16] = {0xdd, 0xbb, 0xb0, 0x17, 0x3f, 0x1e, 0x2d, 0xeb, + * 0x23, 0x94, 0xa6, 0x2a, 0xa2, 0xa0, 0x24, 0x0e}; + * uint8_t ciphertext[16] = {0xd5, 0x1d, 0x19, 0xde, 0xd5, 0xca, 0x4a, 0xe1, + * 0x4b, 0x2b, 0x20, 0xb0, 0x27, 0xff, 0xb0, 0x20}; + * uint8_t keyingMaterial[32] = {0x43, 0xe9, 0x53, 0xb2, 0xae, 0xa0, 0x8a, 0x3a, + * 0xd5, 0x2d, 0x18, 0x2f, 0x58, 0xc7, 0x2b, 0x9c, + * 0x60, 0xfb, 0xe4, 0xa9, 0xca, 0x46, 0xa3, 0xcb, + * 0x89, 0xe3, 0x86, 0x38, 0x45, 0xe2, 0x2c, 0x9e}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x07, 0x27, 0x0d, 0x0e, 0x63, 0xaa, 0x36, 0xda + * // 0xed, 0x8c, 0x6a, 0xde, 0x13, 0xac, 0x1a, 0xf1 + * + * + * void cbcCallback(AESCBC_Handle handle, + * int_fast16_t returnValue, + * AESCBC_OperationUnion *operation, + * AESCBC_OperationType operationType) { + * + * if (returnValue != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * if (operationType == AESCBC_OPERATION_TYPE_DECRYPT || + * operationType == AESCBC_OPERATION_TYPE_ENCRYPT) { + * // do something with operation->oneStepOperation + * } else { + * // do something with operation->segmentedOperation + * } + * } + * + * AESCBC_SegmentedOperation operation; + * + * void cbcStartFunction(void) { + * AESCBC_Handle handle; + * AESCBC_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCBC_Params_init(¶ms); + * params.returnBehavior = AESCBC_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = cbcCallback; + * + * handle = AESCBC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_SegmentedOperation_init(&operation); + * + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * + * decryptionResult = AESCBC_setupDecrypt(handle, &cryptoKey); + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCBC_setIV(handle, iv, AES_BLOCK_SIZE); + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCBC_addData(handle, &operation); + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CBC operation completes in the background + * + * operation.inputLength = 0; + * decryptionResult = AESCBC_finalize(handle, &operation); + * if (decryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * } + * + * @endcode + * + * ### Multi-step CBC encryption with plaintext CryptoKey and non-empty finalize in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * AESCBC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector 1 from NIST CAPV set CBCMMT128 + * uint8_t iv[16] = {0xaa, 0xd1, 0x58, 0x3c, 0xd9, 0x13, 0x65, 0xe3, + * 0xbb, 0x2f, 0x0c, 0x34, 0x30, 0xd0, 0x65, 0xbb}; + * uint8_t plaintext[32] = {0x06, 0x8b, 0x25, 0xc7, 0xbf, 0xb1, 0xf8, 0xbd, + * 0xd4, 0xcf, 0xc9, 0x08, 0xf6, 0x9d, 0xff, 0xc5, + * 0xdd, 0xc7, 0x26, 0xa1, 0x97, 0xf0, 0xe5, 0xf7, + * 0x20, 0xf7, 0x30, 0x39, 0x32, 0x79, 0xbe, 0x91}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x07, 0x00, 0xd6, 0x03, 0xa1, 0xc5, 0x14, 0xe4, + * 0x6b, 0x61, 0x91, 0xba, 0x43, 0x0a, 0x3a, 0x0c}; + * + * // The ciphertext should be the following after the encryption operation: + * // 0xc4, 0xdc, 0x61, 0xd9, 0x72, 0x59, 0x67, 0xa3 + * // 0x02, 0x01, 0x04, 0xa9, 0x73, 0x8f, 0x23, 0x86 + * // 0x85, 0x27, 0xce, 0x83, 0x9a, 0xab, 0x17, 0x52 + * // 0xfd, 0x8b, 0xdb, 0x95, 0xa8, 0x2c, 0x4d, 0x00 + * + * + * handle = AESCBC_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCBC_SegmentedOperation operation; + * AESCBC_SegmentedOperation_init(&operation); + * + * operation.input = plaintext; + * operation.output = ciphertext; + * // One should pass in data that is a block-sized multiple length (16 bytes) + * operation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESCBC_setupEncrypt(handle, &cryptoKey); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCBC_setIV(handle, iv, AES_BLOCK_SIZE); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCBC_addData(handle, &operation); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.output = ciphertext + AES_BLOCK_SIZE; + * + * // You can also finalize with more data (non-zero inputLength) + * operation.inputLength = sizeof(plaintext) - AES_BLOCK_SIZE; + * encryptionResult = AESCBC_finalize(handle, &operation); + * if (encryptionResult != AESCBC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCBC_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_AESCBC__include +#define ti_drivers_AESCBC__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCBC status code reservation offset. + * AESCBC driver implementations should offset status codes with + * #AESCBC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCBCXYZ_STATUS_ERROR0 AESCBC_STATUS_RESERVED - 0 + * #define AESCBCXYZ_STATUS_ERROR1 AESCBC_STATUS_RESERVED - 1 + * #define AESCBCXYZ_STATUS_ERROR2 AESCBC_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCBC_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCBC_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCBC_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCBC_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCBC_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCBC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCBC_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCBC_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported for now. + * + * This code is returned by AESCBC_generateIV(), and internal + * generation of IVs isn't supported for now. Eventually, this + * function will make the TRNG generate the IV. + */ +#define AESCBC_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCBC_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCBC_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCBC driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESCBC_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESCBC Global configuration + * + * The #AESCBC_Config structure contains a set of pointers used to characterize + * the AESCBC driver implementation. + * + * This structure needs to be defined before calling #AESCBC_init() and it must + * not be changed thereafter. + * + * @sa #AESCBC_init() + */ +typedef AESCommon_Config AESCBC_Config; + +/*! + * @brief A handle that is returned from an #AESCBC_open() call. + */ +typedef AESCBC_Config *AESCBC_Handle; + +/*! + * @brief The way in which CBC function calls return after performing an + * encryption or decryption operation. + * + * Not all CBC operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCBC functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCBC_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCBC_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCBC_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCBC_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * CBC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCBC_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the CBC operation goes + * on in the background. CBC operation results are available + * after the function returns. + */ + AESCBC_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while CBC + * operation goes on in the background. CBC operation results + * are available after the function returns. + */ +} AESCBC_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CBC operation. + */ +typedef enum +{ + AESCBC_MODE_ENCRYPT = 1, + AESCBC_MODE_DECRYPT = 2 +} AESCBC_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message in a single-step operation. + */ +typedef struct +{ + CryptoKey *key; /*!< Pointer to a previously initialized CryptoKey. */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CBC operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the output buffer needs to be 32-bit aligned. + */ + uint8_t *iv; /*!< A buffer containing an IV. IVs must be unique to + * each CBC operation and may not be reused. If + * ivInternallyGenerated is set, the IV will be + * generated by #AESCBC_oneStepEncrypt() and copied to + * this buffer. + */ + size_t inputLength; /*!< Length of the input buffer in bytes for one-step + * AES CBC operations. Must be a multiple + * of the AES block size (16 bytes). Also, the + * output buffer must be large enough to receive + * the same number of bytes. The user or application + * should take care of necessary padding. + * Max length supported may be limited depending on the return behavior. + */ + + bool ivInternallyGenerated; /*!< When true, the IV buffer passed into #AESCBC_oneStepEncrypt() + * will be overwritten with a randomly generated IV. + * Not supported by all implementations. + */ +} AESCBC_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message in a segmented operation. Must be updated for steps of a segmented + * operation where data is processed (addData() and finalize()). + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CBC operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the output buffer needs to be 32-bit aligned. + */ + size_t inputLength; /*!< Length of the input buffer in bytes for segmented + * AES CBC operations. Must be a multiple + * of the AES block size (16 bytes) unless finalizing + * without new data. In that case, this value can be 0. + * Also, the output buffer must be large enough to receive + * the same number of bytes. + * Max length supported may be limited depending on the return behavior. + */ +} AESCBC_SegmentedOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESCBC_Operation. + * Existing code should be refactored to use AESCBC_OneStepOperation. + * This reference may be removed at some point in the future + * + */ +typedef AESCBC_OneStepOperation AESCBC_Operation; + +/*! + * @brief Union containing a reference to a one step or + * segmented operation + */ +typedef union AESCBC_OperationUnion +{ + AESCBC_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESCBC_SegmentedOperation segmentedOperation; /* Segmented operation element of the operation union */ +} AESCBC_OperationUnion; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCBC_OPERATION_TYPE_ENCRYPT = 1, /* Fields 1 and 2 are for backward compatibility */ + AESCBC_OPERATION_TYPE_DECRYPT = 2, + AESCBC_OP_TYPE_ONESTEP_ENCRYPT = 1, /* Names changed to _OP_TYPE_ to avoid MISRA deviation from first 31 chars not + being unique */ + AESCBC_OP_TYPE_ONESTEP_DECRYPT = 2, + AESCBC_OP_TYPE_ENCRYPT_SEGMENTED = 3, + AESCBC_OP_TYPE_DECRYPT_SEGMENTED = 4, + AESCBC_OP_TYPE_FINALIZE_ENCRYPT_SEGMENTED = 5, + AESCBC_OP_TYPE_FINALIZE_DECRYPT_SEGMENTED = 6 +} AESCBC_OperationType; + +/*! + * @brief The definition of a callback function used by the AESCBC driver + * when used in ::AESCBC_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CBC operation. + * + * @param returnValue The result of the CBC operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation union. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCBC_CallbackFxn)(AESCBC_Handle handle, + int_fast16_t returnValue, + AESCBC_OperationUnion *operation, + AESCBC_OperationType operationType); + +/*! + * @brief CBC Parameters + * + * CBC Parameters used with the #AESCBC_open() call. Default values for + * these parameters are set using #AESCBC_Params_init(). + * + * @sa #AESCBC_Params_init() + */ +typedef struct +{ + AESCBC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCBC_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCBC_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCBC_Params; + +/*! + * @brief Default #AESCBC_Params structure + * + * @sa #AESCBC_Params_init() + */ +extern const AESCBC_Params AESCBC_defaultParams; + +/*! + * @brief This function initializes the CBC module. + * + * @pre The AESCBC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CBC driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCBC_init(void); + +/*! + * @brief Function to initialize the #AESCBC_Params struct to its defaults + * + * @param params An pointer to #AESCBC_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCBC_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCBC_Params_init(AESCBC_Params *params); + +/*! + * @brief This function opens a given CBC peripheral. + * + * @pre CBC controller has been initialized using #AESCBC_init() + * + * @param [in] index Logical peripheral number for the CBC indexed into + * the AESCBC_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESCBC_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCBC_init() + * @sa #AESCBC_close() + */ +AESCBC_Handle AESCBC_open(uint_least8_t index, const AESCBC_Params *params); + +/*! + * @brief Function to close a CBC peripheral specified by the CBC handle + * + * @pre #AESCBC_open() or #AESCBC_construct() + * + * @param [in] handle A CBC handle + * + * @sa #AESCBC_open() + */ +void AESCBC_close(AESCBC_Handle handle); + +/*! + * @brief Function to initialize an #AESCBC_Operation struct to its defaults + * + * @deprecated This function should be replaced by calls to operation-specific init + * functions. + * + * @param [in] operationStruct A pointer to an #AESCBC_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCBC_Operation_init(AESCBC_Operation *operationStruct); + +/*! + * @brief Function to initialize an #AESCBC_OneStepOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCBC_OneStepOperation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCBC_OneStepOperation_init(AESCBC_OneStepOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCBC_SegmentedOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCBC_SegmentedOperation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCBC_SegmentedOperation_init(AESCBC_SegmentedOperation *operationStruct); + +/*! + * @brief Function to perform an AESCBC encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext. + * + * @pre #AESCBC_open() or #AESCBC_construct(), and #AESCBC_OneStepOperation_init() must be called first. + * + * @param [in] handle A CBC handle returned from #AESCBC_open() or #AESCBC_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCBC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa #AESCBC_oneStepDecrypt() + */ +int_fast16_t AESCBC_oneStepEncrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct); + +/*! + * @brief Function to perform an AESCBC decryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext. + * + * @pre #AESCBC_open() or #AESCBC_construct(), and #AESCBC_OneStepOperation_init() must be called first. + * + * @param [in] handle A CBC handle returned from #AESCBC_open() or #AESCBC_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCBC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCBC_oneStepEncrypt() + */ +int_fast16_t AESCBC_oneStepDecrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct); + +/*! + * @brief Function to prepare a segmented AESCBC encryption operation. + * + * This function sets up a segmented AESCBC encryption operation. + * + * @pre #AESCBC_open() or #AESCBC_construct() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() + * or #AESCBC_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * + * @post #AESCBC_setIV() or #AESCBC_generateIV() + */ +int_fast16_t AESCBC_setupEncrypt(AESCBC_Handle handle, const CryptoKey *key); + +/*! + * @brief Function to prepare a segmented AESCBC decryption operation. + * + * This function sets up a segmented AESCBC decryption operation. + * + * @pre #AESCBC_open() or #AESCBC_construct() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() + * or #AESCBC_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * + * @post #AESCBC_setIV() + */ +int_fast16_t AESCBC_setupDecrypt(AESCBC_Handle handle, const CryptoKey *key); + +/*! + * @brief Function to set an initialization vector for an AES CBC + * segmented operation. + * + * This function sets up a segmented AESCBC encryption or decryption operation. + * + * @pre #AESCBC_setupEncrypt() or #AESCBC_setupDecrypt() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() + * or #AESCBC_construct() + * + * @param [in] iv Pointer to the buffer containing the initialization vector + * + * @param [in] ivLength The length of the initialization vector. The length of the + * IV buffer must be 16 bytes. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * + * @post #AESCBC_addData() + */ +int_fast16_t AESCBC_setIV(AESCBC_Handle handle, const uint8_t *iv, size_t ivLength); + +/*! + * @brief Function to generate an initialization vector for an AES CBC + * segmented encryption operation. + * + * This function sets up a segmented AESCBC encryption operation. + * + * @pre #AESCBC_setupEncrypt() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() + * or #AESCBC_construct() + * + * @param [in] iv Pointer to a buffer to write the generated initialization vector to + * + * @param [in] ivSize Size of the buffer pointed to by iv. This buffer must be + * 16 bytes long for AES CBC mode. + * + * @param [out] ivLength The length of the initialization vector actually written if + * the operation was successful. + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported + * in this device. + * + * @post #AESCBC_addData() + */ +int_fast16_t AESCBC_generateIV(AESCBC_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength); + +/*! + * @brief Encrypts or decrypts a segment of data defined by the AESCBC_SegmentedOperation struct + * + * #AESCBC_addData() may be called an arbitrary number times before finishing the operation with + * #AESCBC_finalize(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @pre #AESCBC_setupEncrypt() or #AESCBC_setupDecrypt() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() or #AESCBC_construct() + * + * @param [in] operation Pointer to a segmented CBC operation structure + * + * @retval #AESCBC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCBC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESCBC_addData() or #AESCBC_finalize() + */ +int_fast16_t AESCBC_addData(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation); + +/*! + * @brief Finalize the AES operation. If new data needs to be added, + * @c inputLength will be used to govern how many bytes will be written. + * New data must be a multiple of a block length, 16 bytes, or 0 if no + * new data needs to be added. + * + * @pre #AESCBC_addData() + * + * @param [in] handle A CBC handle returned from #AESCBC_open() or #AESCBC_construct() + * + * @param [in] operation Pointer to a segmented CBC operation structure + * + * @retval #AESCBC_STATUS_SUCCESS In ::AESCBC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCBC_RETURN_BEHAVIOR_POLLING, this means the CBC + * was generated successfully. In ::AESCBC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCBC_STATUS_ERROR The operation failed. + * @retval #AESCBC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCBC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCBC_finalize(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation); + +/*! + * @brief Cancels an ongoing AESCBC operation. + * + * Asynchronously cancels an AESCBC operation. Only available when using + * AESCBC_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCBC_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCBC_STATUS_SUCCESS The operation was canceled or the operation had already completed. + * @retval #AESCBC_STATUS_ERROR The IV buffer was not properly cleared. + */ +int_fast16_t AESCBC_cancelOperation(AESCBC_Handle handle); + +/** + * @brief Constructs a new AESCBC object + * + * Unlike #AESCBC_open(), #AESCBC_construct() does not require the hwAttrs and + * object to be allocated in a #AESCBC_Config array that is indexed into. + * Instead, the #AESCBC_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param [in] config #AESCBC_Config describing the location of the object and hwAttrs. + * + * @param [in] params #AESCBC_Params to configure the driver instance. + * + * @return Returns a #AESCBC_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESCBC_Handle AESCBC_construct(AESCBC_Config *config, const AESCBC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCBC__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCCM.c b/simplelink_lpf2/source/ti/drivers/AESCCM.c new file mode 100644 index 00000000..f62cf5cb --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCCM.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCCM.c ======== + * + * This file contains default values for the AESCCM_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCCM_Config AESCCM_config[]; +extern const uint_least8_t AESCCM_count; + +const AESCCM_Params AESCCM_defaultParams = { + .returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCCM_Params_init ======== + */ +void AESCCM_Params_init(AESCCM_Params *params) +{ + *params = AESCCM_defaultParams; +} + +/* + * ======== AESCCM_open ======== + */ +__attribute__((weak)) AESCCM_Handle AESCCM_open(uint_least8_t index, const AESCCM_Params *params) +{ + DebugP_assert(index < AESCCM_count); + + AESCCM_Config *config = (AESCCM_Config *)&AESCCM_config[index]; + return AESCCM_construct(config, params); +} + +/* + * ======== AESCCM_Operation_init ======== + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_Operation)); +} + +/* + * ======== AESCCM_OneStepOperation_init ======== + */ +void AESCCM_OneStepOperation_init(AESCCM_OneStepOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_OneStepOperation)); +} + +/* + * ======== AESCCM_SegmentedAADOperation_init ======== + */ +void AESCCM_SegmentedAADOperation_init(AESCCM_SegmentedAADOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedAADOperation)); +} + +/* + * ======== AESCCM_SegmentedDataOperation_init ======== + */ +void AESCCM_SegmentedDataOperation_init(AESCCM_SegmentedDataOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedDataOperation)); +} + +/* + * ======== AESCCM_SegmentedFinalizeOperation_init ======== + */ +void AESCCM_SegmentedFinalizeOperation_init(AESCCM_SegmentedFinalizeOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESCCM_SegmentedFinalizeOperation)); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESCCM.h b/simplelink_lpf2/source/ti/drivers/AESCCM.h new file mode 100644 index 00000000..af2c32d0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCCM.h @@ -0,0 +1,1673 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCCM.h + * + * @brief AESCCM driver header + * + * @anchor ti_drivers_AESCCM_Overview + * # Overview # + * The Counter with CBC-MAC (CCM) mode of operation is a generic + * authenticated encryption block cipher mode. It can be used with + * any block cipher. + * AESCCM combines CBC-MAC with an AES block cipher in CTR mode of operation. + * + * This combination of block cipher modes enables CCM to encrypt messages of any + * length and not only multiples of the block cipher block size. + * + * CTR provides confidentiality. The defined application of CBC-MAC provides + * message integrity and authentication. + * + * AESCCM has the following inputs and outputs: + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AES-CCM input and output parameters
EncryptionDecryption
Input
Shared AES key Shared AES key
NonceNonce
CleartextCiphertext
MAC
AAD (optional)AAD (optional)
Output
CiphertextCleartext
MAC
+ * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * The nonce is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the nonce value must be unique. That is, the set of + * nonce values used with any given key must not contain any duplicate + * values. Using the same nonce for two different messages encrypted + * with the same key destroys the security properties. + * + * The length of the nonce determines the maximum number of messages that may + * be encrypted and authenticated before you must regenerate the key. + * Reasonable session key rotation schemes will regenerate the key before reaching + * this limit. + * There is a trade-off between the nonce-length and the maximum length of + * the plaintext to encrypt and authenticate per nonce. This is because + * CTR concatenates the nonce and an internal counter into one 16-byte + * IV. The counter is incremented after generating an AES-block-sized + * pseudo-random bitstream. This bitstream is XOR'd with the plaintext. + * The counter would eventually roll over for a sufficiently long message. + * This is must not happen. Hence, the longer the nonce and the more messages + * you can send before needing to rotate the key, the shorter the + * lengths of individual messages sent may be. The minimum and maximum + * nonce length defined by the CCM standard provide for both a reasonable + * number of messages before key rotation and a reasonable maximum message length. + * Check NIST SP 800-38C for details. + * + * The optional additional authentication data (AAD) is authenticated + * but not encrypted. Thus, the AAD is not included in the AES-CCM output. + * It can be used to authenticate packet headers. + * + * After the encryption operation, the ciphertext contains the encrypted + * data. The message authentication code (MAC) is also provided. + * + * # CCM Variations # + * The AESCCM driver supports both classic CCM as defined by NIST SP 800-38C and + * the CCM* variant used in IEEE 802.15.4. + * CCM* allows for unauthenticated encryption using CCM by permitting a MAC length + * of 0. It also imposes the requirement that the MAC length be embedded in + * the nonce used for each message if the MAC length varies within the protocol + * using CCM*. + * + * @anchor ti_drivers_AESCCM_Usage + * # Usage # + * + * ## Before starting a CCM operation # + * + * Before starting a CCM operation, the application must do the following: + * - Call AESCCM_init() to initialize the driver + * - Call AESCCM_Params_init() to initialize the AESCCM_Params to default values. + * - Modify the AESCCM_Params as desired + * - Call AESCCM_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESCCM API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the appropriate AESCCM operation struct using the relevant + * operation init functions and set all fields. For example, one-step (one-shot + * or single call) operations should initialize AESCCM_Operation or + * AESCCM_OneStepOperation using AESCCM_Operation_init() or + * AESCCM_OneStepOperation_init(). For multi-step (segmented or multiple call) + * operations, AESCCM_SegmentedAADOperation must be initialized and set when + * processing AAD. AESCCM_SegmentedDataOperation must be initialized and set when + * dealing with payload data (plaintext or ciphertext). AESCCM_SegmentedFinalizeOperation + * must be initialized and set when finalizing the segmented operation. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, CCM operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Output buffer address must be 32-bit aligned. + * - Input length must be a block-size (16-byte) multiple. + * + * ## Starting a CCM operation # + * + * The AESCCM_oneStepEncrypt and AESCCM_oneStepDecrypt functions do a CCM operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. However, they require all AAD and plaintext or ciphertext data to be + * available to the function at the start of the call. + * All devices support single call operations. + * + * When performing a decryption operation with AESCCM_oneStepDecrypt(), the MAC is + * automatically verified. + * + * ## After the CCM operation completes # + * + * After the CCM operation completes, the application should either start another operation + * or close the driver by calling AESCCM_close() + * + * @anchor ti_drivers_AESCCM_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCCM_Synopsis_Code + * @code + * + * // Import AESCCM Driver definitions + * #include + * + * // Define name for AESCCM channel index + * #define AESCCM_INSTANCE 0 + * + * AESCCM_init(); + * + * handle = AESCCM_open(AESCCM_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCCM_OneStepOperation + * AESCCM_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * AESCCM_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCCM_Examples + * ## Examples + * + * ### Single call CCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t nonce[] = "Thisisanonce"; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * handle = AESCCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation operation; + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * ### The following code snippet is for CC27XX devices only and leverages the HSM + * which is a seperate Hardware Accelerator ### + * ### Single call CCM encryption + authentication with plaintext HSM CryptoKey in Polling Mode ### + * + * @code + * + * #include + * #include + * + * ... + * + * AESCCM_Params params; + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t nonce[] = "Thisisanonce"; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * AESCCM_Params_init(¶ms) + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_POLLING; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation operation; + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESCCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * + * ### Single call CCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0}; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESCCM_OneStepOperation operation; + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.nonce = nonce; + * operation.nonceLength = sizeof(nonce); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * decryptionResult = AESCCM_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * + * @endcode + * + * ### Multi-step CCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * AESCCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t keyingMaterial[16] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t aad[8] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t plaintext[23] = {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}; + * uint8_t nonce[13] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t mac[8]; + * uint8_t ciphertext[sizeof(plaintext)]; + * + * // The ciphertext should be the following after the encryption operation: + * // {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * // 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * // 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84} + * + * handle = AESCCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * + * encryptionResult = AESCCM_setupEncrypt(handle, &cryptoKey, sizeof(aad), sizeof(plaintext), sizeof(mac)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) // and the HSM is the engine of choice + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // You will also need to populate the mac in handle->object->mac because HSM needs the mac to construct each + * // segmented token. + * encryptionResult = AESCCMLPF3HSM_setMac(handle, &mac[0], 8); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * #endif + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * encryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = plaintext; + * segmentedDataOperation.output = ciphertext; + * // One should pass in data that is a block-sized multiple length + * // until passing in the last segment of data. + * // In that case, the input length simply needs to be a non-zero value. + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * segmentedDataOperation.input = plaintext + AES_BLOCK_SIZE; + * segmentedDataOperation.output = ciphertext + AES_BLOCK_SIZE; + * segmentedDataOperation.inputLength = sizeof(plaintext) - AES_BLOCK_SIZE; + * + * encryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&segmentedFinalizeOperation); + * segmentedFinalizeOperation.input = plaintext; + * segmentedFinalizeOperation.output = ciphertext; + * + * // You can finalize with no new data + * segmentedFinalizeOperation.inputLength = 0; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * encryptionResult = AESCCM_finalizeEncrypt(handle, &segmentedFinalizeOperation); + * + * if (encryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_close(handle); + * + * @endcode + * + * ### Multi-step CCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0}; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * if(operationType == AESCCM_OPERATION_TYPE_DECRYPT || + * operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + * { + * // Callback fxn only used for one-shot operations + * // Use operation->oneStepOperation + * } + * else if(operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + * operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) + * { + * // Callback fxn only used for segmented AAD operations + * // Use operation->segmentedAADOperation + * } + * else if(operationType == AESCCM_OP_TYPE_DATA_DECRYPT || + * operationType == AESCCM_OP_TYPE_DATA_ENCRYPT) + * { + * // Callback fxn only used for segmented data operations + * // Use operation->segmentedDataOperation + * } + * else + * { + * // Callback fxn only used for segmented finalize operations + * // Use operation->segmentedFinalizeOperation + * } + * } + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * decryptionResult = AESCCM_setupDecrypt(handle, &cryptoKey, 0, 0, 0); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // setLengths must be called if the AAD, input, and MAC lengths aren't provided in setupXXXX. + * decryptionResult = AESCCM_setLengths(handle, sizeof(aad), sizeof(ciphertext), sizeof(mac)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * decryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = ciphertext; + * segmentedDataOperation.output = plaintext; + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&segmentedFinalizeOperation); + * segmentedFinalizeOperation.input = ciphertext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.output = plaintext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.inputLength = sizeof(ciphertext) - AES_BLOCK_SIZE; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * + * decryptionResult = AESCCM_finalizeDecrypt(handle, &segmentedFinalizeOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * @endcode + * + * ### Multi-step CCM* decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0, + * 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}; + * uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; + * uint8_t mac[] = {0}; + * + * // CCM* allows for unauthenticated encryption using CCM by allowing a MAC length of 0 + * uint8_t macLength = 0; + * uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2, + * 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80, + * 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84}; + * uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + * 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E} + * + * + * void ccmCallback(AESCCM_Handle handle, + * int_fast16_t returnValue, + * AESCCM_OperationUnion *operation, + * AESCCM_OperationType operationType) { + * + * if (returnValue != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * if(operationType == AESCCM_OPERATION_TYPE_DECRYPT || + * operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + * { + * // Callback fxn only used for one-shot operations + * // Use operation->oneStepOperation + * } + * else if(operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + * operationType == AESCCM_OP_TYPE_AAD_ENCRYPT) + * { + * // Callback fxn only used for segmented AAD operations + * // Use operation->segmentedAADOperation + * } + * else if(operationType == AESCCM_OP_TYPE_DATA_DECRYPT || + * operationType == AESCCM_OP_TYPE_DATA_ENCRYPT) + * { + * // Callback fxn only used for segmented data operations + * // Use operation->segmentedDataOperation + * } + * else + * { + * // Callback fxn only used for segmented finalize operations + * // Use operation->segmentedFinalizeOperation + * } + * } + * + * void ccmStartFunction(void) { + * AESCCM_Handle handle; + * AESCCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCCM_Params_init(¶ms); + * params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ccmCallback; + * + * handle = AESCCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * decryptionResult = AESCCM_setupDecrypt(handle, &cryptoKey, 0, 0, 0); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // setLengths must be called if the AAD, input, and MAC lengths aren't provided in setupXXXX. + * decryptionResult = AESCCM_setLengths(handle, sizeof(aad), sizeof(ciphertext), macLength); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESCCM_setNonce(handle, nonce, sizeof(nonce)); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedAADOperation segmentedAADOperation; + * AESCCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * decryptionResult = AESCCM_addAAD(handle, &segmentedAADOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedDataOperation segmentedDataOperation; + * AESCCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = ciphertext; + * segmentedDataOperation.output = plaintext; + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESCCM_addData(handle, &segmentedDataOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESCCM_SegmentedFinalizeOperation_init(&segmentedFinalizeOperation); + * segmentedFinalizeOperation.input = ciphertext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.output = plaintext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.inputLength = sizeof(ciphertext) - AES_BLOCK_SIZE; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = macLength; + * + * decryptionResult = AESCCM_finalizeDecrypt(handle, &segmentedFinalizeOperation); + * if (decryptionResult != AESCCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while CCM operation completes in the background + * + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESCCM__include +#define ti_drivers_AESCCM__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCCM status code reservation offset. + * AESCCM driver implementations should offset status codes with + * AESCCM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCCMXYZ_STATUS_ERROR0 AESCCM_STATUS_RESERVED - 0 + * #define AESCCMXYZ_STATUS_ERROR1 AESCCM_STATUS_RESERVED - 1 + * #define AESCCMXYZ_STATUS_ERROR2 AESCCM_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCCM_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return AESCCM_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCCM_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return AESCCM_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCCM_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCCM driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCCM_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCCM_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief An error status code returned if the MAC provided by the application for + * a decryption operation does not match the one calculated during the operation. + * + * This code is returned by AESCCM_oneStepDecrypt() or AESCCM_finalizeDecrypt() + * if the verification of the MAC fails. + */ +#define AESCCM_STATUS_MAC_INVALID AES_STATUS_MAC_INVALID + +/*! + * @brief The operation requested is not supported either by the target hardware + * or the driver implementation. + */ +#define AESCCM_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCCM_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCCM_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCCM driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESCCM Global configuration + * + * The AESCCM_Config structure contains a set of pointers used to characterize + * the AESCCM driver implementation. + * + * This structure needs to be defined before calling AESCCM_init() and it must + * not be changed thereafter. + * + * @sa AESCCM_init() + */ +typedef AESCommon_Config AESCCM_Config; + +/*! + * @brief A handle that is returned from an AESCCM_open() call. + */ +typedef AESCCM_Config *AESCCM_Handle; + +/*! + * @brief The way in which CCM function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all CCM operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCCM functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCCM_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCCM_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCCM_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCCM_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * CCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCCM_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the CCM operation goes + * on in the background. CCM operation results are available + * after the function returns. + */ + AESCCM_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while CCM + * operation goes on in the background. CCM operation results + * are available after the function returns. + */ +} AESCCM_ReturnBehavior; + +/*! + * @brief Enum for the direction of the CCM operation. + */ +typedef enum +{ + AESCCM_MODE_ENCRYPT = 1, + AESCCM_MODE_DECRYPT = 2, +} AESCCM_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and authenticating/verifying a message for one-step operations. + */ +typedef struct +{ + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + uint8_t *nonce; /*!< A buffer containing a nonce. Nonces must be unique to + * each CCM operation and may not be reused. If + * nonceInternallyGenerated is set, the nonce will be + * generated by #AESCCM_oneStepEncrypt() and copied to this buffer. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of the total \c aad in bytes. Either \c aadLength or + * \c inputLength must be non-zero. Unlike this field in + * AESCCM_SegmentedAADOperation, the length doesn't need to be + * block-aligned. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the aadLength must be block-size aligned. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Either \c aadLength or + * \c inputLength must be non-zero. Unlike this field in + * AESCCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * Max length supported may be limited depending on the return behavior. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ + uint8_t nonceLength; /*!< Length of \c nonce in bytes. + * Valid nonce lengths are [7, 8, ... 13]. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ + bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into #AESCCM_oneStepEncrypt() + * will be overwritten with a randomly generated nonce. + * Not supported by all implementations. + */ +} AESCCM_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for + * authenticating/verifying additional data in a segmented operation. + * Must be updated for each add AAD step of a segmented operation. + */ +typedef struct +{ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + size_t aadLength; /*!< Length of the \c aad in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of + * AAD is being passed in. In that case, this value doesn't + * need to be an AES block-sized multiple. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the aadLength must be block-size aligned. + */ +} AESCCM_SegmentedAADOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message in a segmented operation. Must be updated between each + * add data step of a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of data is being + * passed in. In that case, this value doesn't need to a block size multiple. + * Max length supported may be limited depending on the return behavior. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ +} AESCCM_SegmentedDataOperation; + +/*! + * @brief Struct containing the parameters required for finalizing an + * encryption/decryption and authentication/verification of a message + * in a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Can be 0 if finalizing + * without new payload data. Unlike this field in + * AESCCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * Max length supported may be limited depending on the return behavior. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ +} AESCCM_SegmentedFinalizeOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESCCM_Operation. + * Existing code should be refactored to use AESCCM_OneStepOperation. + * This reference may be removed at some point in the future + * + */ +typedef AESCCM_OneStepOperation AESCCM_Operation; + +/*! + * @brief Union containing a reference to a one step, + * segmented AAD, segmented data, or segmented finalize operation. + */ +typedef union AESCCM_OperationUnion +{ + AESCCM_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESCCM_SegmentedAADOperation segmentedAADOperation; /* Segmented AAD operation element of the operation union */ + AESCCM_SegmentedDataOperation segmentedDataOperation; /* Segmented data operation element of the operation union */ + AESCCM_SegmentedFinalizeOperation segmentedFinalizeOperation; /* Segmented finalize operation element of the + operation union */ +} AESCCM_OperationUnion; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCCM_OPERATION_TYPE_ENCRYPT = 1, /* Fields 1 and 2 are for backward compatibility */ + AESCCM_OPERATION_TYPE_DECRYPT = 2, + AESCCM_OP_TYPE_ONESTEP_ENCRYPT = 1, /* Names changed to _OP_TYPE_ to avoid MISRA deviation from first 31 chars not + being unique */ + AESCCM_OP_TYPE_ONESTEP_DECRYPT = 2, + AESCCM_OP_TYPE_AAD_ENCRYPT = 3, + AESCCM_OP_TYPE_AAD_DECRYPT = 4, + AESCCM_OP_TYPE_DATA_ENCRYPT = 5, + AESCCM_OP_TYPE_DATA_DECRYPT = 6, + AESCCM_OP_TYPE_FINALIZE_ENCRYPT = 7, + AESCCM_OP_TYPE_FINALIZE_DECRYPT = 8, +} AESCCM_OperationType; + +/*! + * @brief The definition of a callback function used by the AESCCM driver + * when used in ::AESCCM_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CCM operation. + * + * @param returnValue The result of the CCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operationUnion A pointer to an operation union. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCCM_CallbackFxn)(AESCCM_Handle handle, + int_fast16_t returnValue, + AESCCM_OperationUnion *operation, + AESCCM_OperationType operationType); + +/*! + * @brief CCM Parameters + * + * CCM Parameters used with the AESCCM_open() call. Default values for + * these parameters are set using AESCCM_Params_init(). + * + * @sa AESCCM_Params_init() + */ +typedef struct +{ + AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCCM_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCCM_Params; + +/*! + * @brief Default AESCCM_Params structure + * + * @sa #AESCCM_Params_init() + */ +extern const AESCCM_Params AESCCM_defaultParams; + +/*! + * @brief This function initializes the CCM module. + * + * @pre The AESCCM_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CCM driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCCM_init(void); + +/*! + * @brief Function to initialize the #AESCCM_Params struct to its defaults + * + * @param params An pointer to #AESCCM_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCCM_Params_init(AESCCM_Params *params); + +/*! + * @brief This function opens a given CCM peripheral. + * + * @pre CCM controller has been initialized using #AESCCM_init() + * + * @param [in] index Logical peripheral number for the CCM indexed into + * the AESCCM_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESCCM_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #AESCCM_init() + * @sa #AESCCM_close() + */ +AESCCM_Handle AESCCM_open(uint_least8_t index, const AESCCM_Params *params); + +/*! + * @brief Function to close a CCM peripheral specified by the CCM handle + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle + * + * @sa #AESCCM_open() + */ +void AESCCM_close(AESCCM_Handle handle); + +/*! + * @brief Function to prepare a segmented AESCCM encryption operation. + * + * This function sets up a segmented AESCCM encryption operation. + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] macLength Size of the MAC in bytes. This value + * can be 0 and later provided by + * #AESCCM_setLengths(). + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); + +/*! + * @brief Function to prepare a segmented AESCCM decryption operation. + * + * This function sets up a segmented AESCCM decryption operation. + * + * @pre #AESCCM_open() or #AESCCM_construct() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes + * This value can be 0 and later provided + * by #AESCCM_setLengths(). + * + * @param [in] macLength Size of the MAC in bytes. This value + * can be 0 and later provided by + * #AESCCM_setLengths(). + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength); + +/*! + * @brief Function to set the lengths of the message, additional data, and MAC. + * + * This function declares the lengths of the message, + * additional authenticated data (AAD), and MAC. + * + * @note This function doesn't have to be called if the lengths above were + * specified in #AESCCM_setupEncrypt() or #AESCCM_setupDecrypt(). + * + * @pre #AESCCM_setupEncrypt() or #AESCCM_setupDecrypt() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] aadLength Size of the non-encrypted AAD in bytes + * + * @param [in] plaintextLength Size of the plaintext or ciphertext to encrypt or decrypt in bytes + * + * @param [in] macLength Size of the MAC in bytes + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESCCM_setNonce() + * @post #AESCCM_generateNonce() + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength); + +/*! + * @brief Function to set the nonce for an AES CCM segmented operation. + * + * @pre #AESCCM_setupEncrypt(), #AESCCM_setupDecrypt(), or #AESCCM_setLengths() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] nonce Pointer to the buffer containing the nonce + * + * @param [in] nonceLength The length of the nonce in bytes + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength); + +/*! + * @brief Function to generate a nonce for an AES CCM segmented encryption operation. + * + * @pre #AESCCM_setupEncrypt() or #AESCCM_setLengths() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() + * or #AESCCM_construct() + * + * @param [in] nonce Pointer to the buffer where the generated nonce + * is to be written to + * + * @param [in] nonceSize The length of the nonce buffer in bytes + * + * @param [out] nonceLength The length of the nonce actually written if the + * operation was successful + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength); + +/*! + * @brief Adds a segment of @a aad with a @a length in bytes to the generated MAC. + * The length must be a multiple of a block size, 16 bytes, unless passing in the last + * chunk of AAD. + * + * #AESCCM_addAAD() may be called an arbitrary number of times before continuing the operation with + * #AESCCM_addData(), #AESCCM_finalizeEncrypt() or #AESCCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @note This function must not be called after passing data to encrypt or + * decrypt with #AESCCM_addData(). + * + * @warning When decrypting, do not use the output until + * #AESCCM_finalizeDecrypt() succeeds. + * + * @pre #AESCCM_setNonce() or #AESCCM_generateNonce() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented AAD CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * + * @post #AESCCM_addAAD() + * @post #AESCCM_addData() + * @post #AESCCM_finalizeEncrypt() + * @post #AESCCM_finalizeDecrypt() + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation); + +/*! + * @brief Adds a segment of @a data with a @a length in bytes to the plaintext/ciphertext + * output and generated MAC. The length must be a multiple of a block size, 16 bytes, unless + * passing in the last chunk of payload data. + * + * #AESCCM_addData() may be called an arbitrary number of times before finishing the operation + * with #AESCCM_finalizeEncrypt() or #AESCCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @warning When decrypting, do not use the output until + * #AESCCM_finalizeDecrypt() succeeds. + * + * @pre #AESCCM_setNonce() or #AESCCM_generateNonce() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented data CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESCCM_addData() + * @post #AESCCM_finalizeEncrypt() + * @post #AESCCM_finalizeDecrypt() + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation); + +/*! + * @brief Finalize the MAC and ciphertext. + * + * This function finalizes the encryption of a dataset earlier provided + * by calls to #AESCCM_addAAD() and #AESCCM_addData() and creates a message + * authentication code. If additional data needs to be encrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * The resulting output is a message authentication code and ciphertext. + * + * @pre #AESCCM_addAAD() or #AESCCM_addData() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented finalize CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS In ::AESCCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESCCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Finalize the MAC and plaintext and verify it. + * + * This function finalizes the decryption of a dataset earlier provided + * by calls to AESCCM_addAAD() and AESCCM_addData() and verifies a provided message + * authentication code. If additional data needs to be decrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield a corrupted MAC comparison. + * + * The resulting output is a verification return code and plaintext. + * + * @pre #AESCCM_addAAD() or #AESCCM_addData() + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operation Pointer to segmented finalize CCM operation structure + * + * @retval #AESCCM_STATUS_SUCCESS In ::AESCCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESCCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was verified successfully. In ::AESCCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_MAC_INVALID The provided MAC did not match the recomputed one. + * @retval #AESCCM_STATUS_CANCELED The operation was canceled. + * @retval #AESCCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Function to initialize an #AESCCM_Operation struct to its defaults + * + * @deprecated This function should be replaced by calls to operation-specific + * init functions. + * + * @param [in] operationStruct A pointer to an #AESCCM_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCCM_Operation_init(AESCCM_Operation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_OneStepOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_OneStepOperation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCCM_OneStepOperation_init(AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedAADOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedAADOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedAADOperation_init(AESCCM_SegmentedAADOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedDataOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedDataOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedDataOperation_init(AESCCM_SegmentedDataOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESCCM_SegmentedFinalizeOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESCCM_SegmentedFinalizeOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESCCM_SegmentedFinalizeOperation_init(AESCCM_SegmentedFinalizeOperation *operationStruct); + +/*! + * @brief Function to perform an AESCCM encryption + authentication operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre #AESCCM_open() or #AESCCM_construct() and #AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCCM_oneStepDecrypt() + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to perform an AESCCM decryption + verification operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre #AESCCM_open() or #AESCCM_construct() and #AESCCM_Operation_init() have to be called first. + * + * @param [in] handle A CCM handle returned from #AESCCM_open() or #AESCCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESCCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESCCM_STATUS_ERROR The operation failed. + * @retval #AESCCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCCM_STATUS_MAC_INVALID The provided MAC did not match the recomputed one. + * @retval #AESCCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCCM_oneStepEncrypt() + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct); + +/*! + * @brief Cancels an ongoing AESCCM operation. + * + * Asynchronously cancels an AESCCM operation. Only available when using + * AESCCM_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCCM_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCCM_STATUS_SUCCESS The operation was canceled, or the operation had already completed. + * @retval #AESCCM_STATUS_ERROR The driver was not in callback mode, or the operation's output + * and generated MAC weren't properly cleared. + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle); + +/** + * @brief Constructs a new AESCCM object + * + * Unlike #AESCCM_open(), #AESCCM_construct() does not require the hwAttrs and + * object to be allocated in a #AESCCM_Config array that is indexed into. + * Instead, the #AESCCM_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESCCM_Config describing the location of the object and hwAttrs. + * + * @param params #AESCCM_Params to configure the driver instance. + * + * @return Returns a #AESCCM_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCCM__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCMAC.c b/simplelink_lpf2/source/ti/drivers/AESCMAC.c new file mode 100644 index 00000000..f9df7fd2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCMAC.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCMAC.c ======== + * + * This file contains default values for the AESCMAC_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCMAC_Config AESCMAC_config[]; +extern const uint_least8_t AESCMAC_count; + +const AESCMAC_Params AESCMAC_defaultParams = { + .returnBehavior = AESCMAC_RETURN_BEHAVIOR_BLOCKING, + .operationalMode = AESCMAC_OPMODE_CMAC, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCMAC_Params_init ======== + */ +void AESCMAC_Params_init(AESCMAC_Params *params) +{ + *params = AESCMAC_defaultParams; +} + +/* + * ======== AESCMAC_open ======== + */ +__attribute__((weak)) AESCMAC_Handle AESCMAC_open(uint_least8_t index, const AESCMAC_Params *params) +{ + DebugP_assert(index < AESCMAC_count); + + AESCMAC_Config *config = (AESCMAC_Config *)&AESCMAC_config[index]; + return AESCMAC_construct(config, params); +} + +/* + * ======== AESCMAC_Operation_init ======== + */ +void AESCMAC_Operation_init(AESCMAC_Operation *operation) +{ + memset(operation, 0x00, sizeof(AESCMAC_Operation)); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESCMAC.h b/simplelink_lpf2/source/ti/drivers/AESCMAC.h new file mode 100644 index 00000000..485b4806 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCMAC.h @@ -0,0 +1,1137 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! + * @file AESCMAC.h + * + * @brief AESCMAC (CMAC and CBC-MAC) driver header + * + * @anchor ti_drivers_AESCMAC_Overview + * # Overview # + * The Cipher-based Message Authentication Code (CMAC) and Cipher Block Chaining + * Message Authentication Code (CBC-MAC) are generic block cipher modes of + * operation. They can be used with any block cipher but this driver + * implementation uses AES. + * + * Both CMAC and CBC-MAC create a message authentication code from a message of + * any practical length to provide authenticity and integrity assurances. + * CMAC is recommended over CBC-MAC because CBC-MAC is not secure for variable + * length messages. + * + * ## CBC-MAC Drawbacks # + * CBC-MAC is only secure for fixed-length messages. Any single key must only be + * used for messages of a fixed and known length. The CMAC algorithm, which + * is based on a variation of CBC-MAC at its core, was developed to address that + * security deficiency and is the MAC algorithm recommended by NIST. + * + * @anchor ti_drivers_AESCMAC_Usage + * # CMAC Usage # + * ## Before starting a CMAC operation # + * + * Before starting a CMAC operation, the application must do the following: + * - Call #AESCMAC_init() to initialize the driver + * - Call #AESCMAC_Params_init() to initialize the #AESCMAC_Params to default values. + * - Modify the #AESCMAC_Params as desired + * - Call #AESCMAC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The CMAC API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, CMAC operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Input length must be a block-size (16-byte) multiple. + * + * ## Starting a CMAC operation # + * + * The #AESCMAC_oneStepSign and #AESCMAC_oneStepVerify functions perform a CMAC operation + * in a single call. They will always be the most highly optimized routines with the + * least overhead and the fastest runtime. However, they require all plaintext + * or ciphertext to be available to the function at the start of the call. + * All devices support single call operations. + * + * ## After the CMAC operation completes # + * + * After the CMAC operation completes, the application should either start + * another operation or close the driver by calling #AESCMAC_close(). + * + * @anchor ti_drivers_AESCMAC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCMAC_Synopsis_Code + * @code + * // Import CMAC Driver definitions + * #include + * + * // Define name for CMAC channel index + * #define AESCMAC_INSTANCE 0 + * + * AESCMAC_init(); + * + * handle = AESCMAC_open(AESCMAC_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Initialize the operation + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * AESCMAC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCMAC_Examples + * ## Examples + * + * ### Single call CMAC authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t mac[16]; + * + * ... + * + * CryptoKey cryptoKey; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * AESCMAC_Handle handle = AESCMAC_open(0, NULL); + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * int_fast16_t result = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * // 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C + * + * AESCMAC_close(handle); + * + * @endcode + * + * ### Single call CMAC authentication with plaintext CryptoKey in polling return mode and using HSM engine # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t mac[16]; + * + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * AESCMAC_Params_init(¶ms) + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_POLLING; + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * handle = AESCMAC_open(0, ¶ms); + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * int_fast16_t result = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * // 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C + * + * AESCMAC_close(handle); + * + * @endcode + * + * ### Single call CMAC verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * uint8_t message[16] = {0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + * 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A}; + * uint8_t keyingMaterial[16] = {0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + * 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; + * uint8_t expectedMac[16] = {0x07, 0x0A, 0x16, 0xB4, 0x6B, 0x4D, 0x41, 0x44, + * 0xF7, 0x9B, 0xDD, 0x9D, 0xD0, 0x4A, 0x28, 0x7C}; + * + * void cmacCallback(AESCMAC_Handle handle, + * int_fast16_t returnValue) { + * if (returnValue != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * void cmacStartFunction(void) { + * AESCMAC_Handle handle; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * CryptoKey cryptoKey; + * int_fast16_t verificationResult; + * + * AESCMAC_Params_init(¶ms); + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = cmacCallback; + * handle = AESCMAC_open(0, ¶ms); + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * operation.input = input; + * operation.inputLength = sizeof(input); + * operation.mac = expectedMac; + * operation.macLength = sizeof(expectedMac); + * verificationResult = AESCMAC_oneStepVerify(handle, &operation, &cryptoKey); + * + * if (verificationResult != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * // do other things while CMAC operation completes in the background + * } + * @endcode + * + * ### Multi-step CMAC signature with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t message[40] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11}; + * uint8_t mac[16]; + * + * CryptoKey cryptoKey; + * AESCMAC_Params params; + * AESCMAC_Operation operation; + * + * AESCMAC_init(); + * + * AESCMAC_Handle handle = AESCMAC_open(0, NULL); + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation_init(&operation); + * + * // Set up multi-step sign. + * int_fast16_t result = AESCMAC_setupSign(handle, &cryptoKey); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * size_t initialSegmentSize = AES_BLOCK_SIZE; + * + * // Add first segment of data. + * operation.input = input; + * operation.inputLength = initialSegmentSize; // Must be a non-zero multiple of the block size (16-bytes) unless + * finalizing. result = AESCMAC_addData(handle, &operation); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // Finalize with the last segment of data. + * operation.input = &input[initialSegmentSize]; + * operation.inputLength = sizeof(input) - initialSegmentSize; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * result = AESCMAC_finalize(handle, &operation); + * + * if (result != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resulting MAC should equal the following after the operation: + * // 0xaa, 0xf3, 0xd8, 0xf1, 0xde, 0x56, 0x40, 0xc2, + * // 0x32, 0xf5, 0xb1, 0x69, 0xb9, 0xc9, 0x11, 0xe6 + * ... + * + * AESCMAC_close(handle); + * + * @endcode + * + * @anchor ti_drivers_AESCBCMAC_Usage + * # CBC-MAC Usage # + * ## Before starting a CBC-MAC operation # + * + * Before starting a CBC-MAC operation, the application must do the following: + * - Call #AESCMAC_init() to initialize the driver + * - Call #AESCMAC_Params_init() to initialize the #AESCMAC_Params to + * default values. + * - Set #AESCMAC_Params.operationalMode to #AESCMAC_OPMODE_CBCMAC. + * - Modify the #AESCMAC_Params as desired + * - Call #AESCMAC_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store, key blob), the CryptoKey must be + * initialized differently. The AESCMAC API can handle all types of + * CryptoKey. However, not all device-specific implementations support all + * types of CryptoKey. Devices without a key store will not support + * CryptoKeys with keying material stored in a key store for example. All + * devices support plaintext CryptoKeys. + * - Initialize the #AESCMAC_Operation using #AESCMAC_Operation_init() + * and set all length, key, and buffer fields. + * + * ## Starting a CBC-MAC operation # + * + * The #AESCMAC_oneStepSign and #AESCMAC_oneStepVerify functions perform a + * CBC-MAC operation in a single call. They will always be the most highly + * optimized routines with the least overhead and the fastest runtime. However, + * they require all plaintext or ciphertext to be available to the function at + * the start of the call. All devices support single call operations. + * + * ## After the CBC-MAC operation completes # + * + * After the CBC-MAC operation completes, the application should either start + * another operation or close the driver by calling #AESCMAC_close(). + * + * @anchor ti_drivers_AESCBCMAC_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESCBCMAC_Synopsis_Code + * @code + * // Import AESCMAC Driver definitions + * #include + * + * // Define name for AESCMAC channel index + * #define AESCMAC_INSTANCE 0 + * + * AESCMAC_init(); + * + * AESCMAC_Params params; + * + * AESCMAC_Params_init(¶ms); + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(AESCMAC_INSTANCE, ¶ms); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCMAC_Operation + * AESCMAC_Operation_init(&operation); + * operation.input = plaintext; + * operation.inputLength = sizeof(plaintext); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation); + * + * AESCMAC_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCBCMAC_Examples + * ## Examples + * + * ### One step AES CBC-MAC signature with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t signResult; + * + * // For example purposes only. + * // Test vector derived from RFC 3602 Case #2 + * uint8_t plaintext[32] = {0x56, 0x2F, 0x15, 0x9A, 0x69, 0x0C, 0x3B, 0x2F, + * 0xD5, 0xBA, 0xB0, 0x62, 0x56, 0x23, 0x61, 0x57, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * uint8_t mac[16]; + * uint8_t keyingMaterial[16] = {0xC2, 0x86, 0x69, 0x6D, 0x88, 0x7C, 0x9A, 0xA0, + * 0x61, 0x1B, 0xBB, 0x3E, 0x20, 0x25, 0xA4, 0x5A}; + * + * // The MAC should equal the following after the operation: + * // 0x75, 0x86, 0x60, 0x2D, 0x25, 0x3C, 0xFF, 0xF9, + * // 0x1B, 0x82, 0x66, 0xBE, 0xA6, 0xD6, 0x1A, 0xB1 + * + * AESCMAC_Params_init(¶ms); + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation operation; + * AESCMAC_Operation_init(&operation); // Optional as all struct members will be set before use. + * + * operation.input = plaintext; + * operation.inputLength = sizeof(plaintext); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * signResult = AESCMAC_oneStepSign(handle, &operation, &cryptoKey); + * + * if (signResult == AESCMAC_STATUS_SUCCESS) { + * // signature is available in mac[] buffer. + * } + * else { + * // handle error + * } + * + * AESCMAC_close(handle); + * + * @endcode + * + * + * ### Multi-step AES CBC-MAC verify with plaintext CryptoKey in polling return mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * AESCMAC_Params params; + * AESCMAC_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t retVal; + * + * // For example purposes only. + * // Test vector derived from RFC 3602 Case #2 + * uint8_t plaintext[32] = {0x56, 0x2F, 0x15, 0x9A, 0x69, 0x0C, 0x3B, 0x2F, + * 0xD5, 0xBA, 0xB0, 0x62, 0x56, 0x23, 0x61, 0x57, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * uint8_t mac[16] = {0x75, 0x86, 0x60, 0x2D, 0x25, 0x3C, 0xFF, 0xF9, + * 0x1B, 0x82, 0x66, 0xBE, 0xA6, 0xD6, 0x1A, 0xB1} + * uint8_t keyingMaterial[16] = {0xC2, 0x86, 0x69, 0x6D, 0x88, 0x7C, 0x9A, 0xA0, + * 0x61, 0x1B, 0xBB, 0x3E, 0x20, 0x25, 0xA4, 0x5A}; + * + * AESCMAC_Params_init(¶ms) + * params.returnBehavior = AESCMAC_RETURN_BEHAVIOR_POLLING; + * params.operationalMode = AESCMAC_OPMODE_CBCMAC; + * + * handle = AESCMAC_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCMAC_Operation operation; + * AESCMAC_Operation_init(&operation); // Optional as all struct members will be set before use. + * + * retVal = AESCMAC_setupVerify(handle, &cryptoKey); + * + * if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext; + * operation.inputLength = AES_BLOCK_SIZE; // Must be a non-zero multiple of the block size (16-bytes) unless + * finalizing. + * // Note: MAC pointer only needs to be set when finalizing operation. + * + * retVal = AESCMAC_addData(handle, &operation); + * + * if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.inputLength = AES_BLOCK_SIZE; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * retVal = AESCMAC_finalize(handle, &operation); + * + * // retVal should be AESCMAC_STATUS_SUCCESS to indicate that the signature + * // verification passed. + * + * if (retVal == AESCMAC_STATUS_MAC_INVALID) { + * // handle invalid MAC + * } + * else if (retVal != AESCMAC_STATUS_SUCCESS) { + * // handle error + * } + * + * AESCMAC_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_AESCMAC__include +#define ti_drivers_AESCMAC__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common CMAC status code reservation offset. + * CMAC driver implementations should offset status codes with + * #AESCMAC_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCMACXYZ_STATUS_ERROR0 AESCMAC_STATUS_RESERVED - 0 + * #define AESCMACXYZ_STATUS_ERROR1 AESCMAC_STATUS_RESERVED - 1 + * #define AESCMACXYZ_STATUS_ERROR2 AESCMAC_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCMAC_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCMAC_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCMAC_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCMAC_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCMAC_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * CMAC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCMAC_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The MAC verification failed. + * + * Functions return #AESCMAC_STATUS_MAC_INVALID if the MAC computed + * for the provided (key, message) pair did not match the MAC provided. + */ +#define AESCMAC_STATUS_MAC_INVALID AES_STATUS_MAC_INVALID + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCMAC_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported either by the target hardware + * or the driver implementation. + */ +#define AESCMAC_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCMAC_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCMAC_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input. + * + * AESCMAC driver implementations may have restrictions on the alignment of + * input data due to performance limitations of the hardware. + */ +#define AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief CMAC Global configuration + * + * The #AESCMAC_Config structure contains a set of pointers used to characterize + * the CMAC driver implementation. + * + * This structure needs to be defined before calling #AESCMAC_init() and it must + * not be changed thereafter. + * + * @sa #AESCMAC_init() + */ +typedef AESCommon_Config AESCMAC_Config; + +/*! + * @brief A handle that is returned from an #AESCMAC_open() call. + */ +typedef AESCMAC_Config *AESCMAC_Handle; + +/*! + * @brief The return behavior of AESCMAC functions + * + * Not all AESCMAC operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCMAC functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |---------------------------------|-------|-------|-------| + * |AESCMAC_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCMAC_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCMAC_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCMAC_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * MAC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCMAC_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the MAC operation goes + * on in the background. MAC operation results are available + * after the function returns. + */ + AESCMAC_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while MAC + * operation goes on in the background. MAC operation results + * are available after the function returns. + */ +} AESCMAC_ReturnBehavior; + +/*! + * @brief Defines the operation modes for the AESCMAC driver. + * + * By default, the driver will use CMAC to sign and verify messages. + * To use CBC-MAC instead of CMAC, set the operationalMode in + * #AESCMAC_Params accordingly before calling #AESCMAC_open or + * #AESCMAC_construct. The operational mode persists throughout + * the existance of the driver instance. + */ +typedef enum +{ + AESCMAC_OPMODE_CMAC = 1, /*!< CMAC operational mode */ + AESCMAC_OPMODE_CBCMAC = 2, /*!< CBC-MAC operational mode */ +} AESCMAC_OperationalMode; + +/*! + * @brief Struct containing the parameters required for signing or verifying a message. + */ +typedef struct +{ + uint8_t *input; /*!< - Sign: Pointer to the input message to + * be authenticated. + * - Verify: Pointer to the input message to be + * verified. + */ + uint8_t *mac; /*!< - Sign: Pointer to the output buffer to write + * the generated MAC. Buffer size must be + * at least equal to @a macLength. + * - Verify: Pointer to the input MAC to be + * used for verification. + */ + size_t inputLength; /*!< Length of the input message in bytes. + * May be zero for CMAC but must be non-zero for CBC-MAC. + * See function descriptions for further restrictions. + * Max length supported may be limited depending on the return behavior. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ + size_t macLength; /*!< Length of the MAC in bytes. + * Must be <= 16. A length of < 8 is not recommended and + * should severely restrict MAC recomputation attempts. + * See appendix A of NIST SP800-38b for more information. + */ +} AESCMAC_Operation; + +/*! + * @brief Mask for the operation code. + */ +#define AESCMAC_OP_CODE_MASK 0x0F /* bits 0-3 */ + +/*! + * @brief Enum for the operation codes supported by the driver. + */ +typedef enum +{ + AESCMAC_OP_CODE_ONE_STEP = 0, + AESCMAC_OP_CODE_SEGMENTED, + AESCMAC_OP_CODE_FINALIZE +} AESCMAC_OperationCode; + +/*! + * @brief Flag indicating a sign operation. If this bit is not set, then it + * is a verify operation. + */ +#define AESCMAC_OP_FLAG_SIGN 0x10 /* bit 4 */ + +/*! + * @brief Mask for all valid operation flags. + */ +#define AESCMAC_OP_FLAGS_MASK (AESCMAC_OP_FLAG_SIGN | AESCMAC_OP_FLAG_VERIFY) + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCMAC_OP_TYPE_SIGN = AESCMAC_OP_CODE_ONE_STEP | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_VERIFY = AESCMAC_OP_CODE_ONE_STEP, + AESCMAC_OP_TYPE_SEGMENTED_SIGN = AESCMAC_OP_CODE_SEGMENTED | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_SEGMENTED_VERIFY = AESCMAC_OP_CODE_SEGMENTED, + AESCMAC_OP_TYPE_FINALIZE_SIGN = AESCMAC_OP_CODE_FINALIZE | AESCMAC_OP_FLAG_SIGN, + AESCMAC_OP_TYPE_FINALIZE_VERIFY = AESCMAC_OP_CODE_FINALIZE +} AESCMAC_OperationType; + +/*! + * @brief The definition of a callback function used by the AESCMAC driver + * when used in ::AESCMAC_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the AESCMAC operation. + * + * @param returnValue The result of the AESCMAC operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation Pointer to an operation struct. + * + * @param operationType Indicates which operation the callback refers to. + */ +typedef void (*AESCMAC_CallbackFxn)(AESCMAC_Handle handle, + int_fast16_t returnValue, + AESCMAC_Operation *operation, + AESCMAC_OperationType operationType); + +/*! + * @brief AESCMAC Parameters + * + * CMAC Parameters are used to with the #AESCMAC_open() or #AESCMAC_construct() call. + * Default values for these parameters are set using #AESCMAC_Params_init(). + * + * @sa #AESCMAC_Params_init() + */ +typedef struct +{ + AESCMAC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCMAC_OperationalMode operationalMode; /*!< CMAC or CBC-MAC operational mode */ + AESCMAC_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCMAC_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCMAC_Params; + +/*! + * @brief Default #AESCMAC_Params structure + * + * @sa #AESCMAC_Params_init() + */ +extern const AESCMAC_Params AESCMAC_defaultParams; + +/*! + * @brief Initializes the CMAC module. + * + * @pre The AESCMAC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CMAC driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCMAC_init(void); + +/*! + * @brief Initializes the #AESCMAC_Params struct to its defaults + * + * @param [in] params Pointer to #AESCMAC_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCMAC_RETURN_BEHAVIOR_BLOCKING + * operationalMode = AESCMAC_OPMODE_CMAC + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCMAC_Params_init(AESCMAC_Params *params); + +/*! + * @brief Initializes an #AESCMAC_Operation struct to its defaults + * + * @param [in] operation Pointer to an #AESCMAC_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESCMAC_Operation_init(AESCMAC_Operation *operation); + +/*! + * @brief Opens a given AESCMAC peripheral. + * + * @note #AESCMAC_Params @a operationalMode may be set to enable CBC-MAC + * mode but the default is CMAC mode + * + * @pre AESCMAC driver has been initialized using #AESCMAC_init() + * + * @param [in] index Logical peripheral number for the CMAC indexed into + * the AESCMAC_config table + * + * @param [in] params Pointer to a parameter block, if NULL it will use + * default values + * + * @return An #AESCMAC_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCMAC_init() + * @sa #AESCMAC_close() + */ +AESCMAC_Handle AESCMAC_open(uint_least8_t index, const AESCMAC_Params *params); + +/*! + * @brief Closes a AESCMAC peripheral specified by the CMAC handle + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param handle AESCMAC handle + * + * @sa #AESCMAC_open() + * @sa #AESCMAC_construct() + */ +void AESCMAC_close(AESCMAC_Handle handle); + +/*! + * @brief Prepares a segmented AESCMAC sign operation + * + * This function sets up a segmented AESCMAC sign operation. + * After a segmented operation is setup, it must be completed + * with #AESCMAC_finalize or cancelled with #AESCMAC_cancelOperation + * before another operation can be started. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. Segmented + * data may now be added. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + * + * @sa #AESCMAC_setupVerify() + */ +int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key); + +/*! + * @brief Prepares a segmented AESCMAC verify operation + * + * This function sets up a segmented AESCMAC verify operation. + * After a segmented operation is setup, it must be completed + * with #AESCMAC_finalize or cancelled with #AESCMAC_cancelOperation + * before another operation can be started. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. Segmented + * data may now be added. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + * + * @sa #AESCMAC_setupSign() + */ +int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key); + +/*! + * @brief Adds data to the current segmented operation + * + * The @a inputLength must be a non-zero multiple of the block size (16-bytes). + * #AESCMAC_addData() may be called an arbitrary number of times before + * finishing the operation with #AESCMAC_finalize(). + * + * This function blocks until the final MAC been computed. + * It returns immediately when ::AESCMAC_RETURN_BEHAVIOR_CALLBACK is set. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_setupSign() or #AESCMAC_setupVerify() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to CMAC operation structure() + * + * @retval #AESCMAC_STATUS_SUCCESS The operation succeeded. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @post #AESCMAC_addData() or #AESCMAC_finalize() + */ +int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +/*! + * @brief Finalizes the current segmented operation + * + * For sign operations: + * This function computes and writes back the final MAC @a mac of length + * @a macLength. + * + * For verify operations: + * This function uses the provided MAC @a mac to authenticate an input message. + * The return value indicates whether the authentication was successful. + * + * @note Finalizing without additional input data is not supported. + * If finalization is attempted with @a inputLength of zero, + * #AESCMAC_STATUS_ERROR will be returned and the caller must either + * retry finalization with data or terminate the segmented operation + * by calling #AESCMAC_cancelOperation. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_addData() or #AESCMAC_setupSign() or #AESCMAC_setupVerify() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to CMAC operation structure() + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_MAC_INVALID The provided MAC did not match the generated MAC. + * This return value is only valid for verify operations. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + */ +int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation); + +/*! + * @brief Performs a AESCMAC signature in one call + * + * This function uses the provided key to authenticate an input message. + * The resulting output is a message authentication code. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to AESCMAC operation structure + * + * @param [in] key Pointer to a previously initialized CryptoKey + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @sa #AESCMAC_oneStepVerify() + */ +int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key); + +/*! + * @brief Performs a AESCMAC verification in one call + * + * This function verifies that the provided message authentication code + * matches the one generated by the provided key and input message. + * + * @note None of the buffers provided as arguments may be altered by the application + * during an ongoing operation. Doing so can yield corrupted plaintext. + * + * @pre #AESCMAC_open() or #AESCMAC_construct() + * + * @param [in] handle AESCMAC handle + * + * @param [in] operation Pointer to AESCMAC operation structure + * + * @param [in] key Pointer to a previously initialized CryptoKey + * + * @retval #AESCMAC_STATUS_SUCCESS In ::AESCMAC_RETURN_BEHAVIOR_BLOCKING and + * ::AESCMAC_RETURN_BEHAVIOR_POLLING, this means the MAC + * was verified successfully. In ::AESCMAC_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCMAC_STATUS_ERROR The operation failed. + * @retval #AESCMAC_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCMAC_STATUS_MAC_INVALID The provided MAC did not match the generated MAC. + * This return value is only valid for verify operations. + * @retval #AESCMAC_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input buffer was not word-aligned. + * + * @sa AESCMAC_oneStepSign() + */ +int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key); + +/*! + * @brief Cancels an ongoing AESCMAC operation. + * + * Asynchronously cancels an AESCMAC operation. Only available when using + * AESCMAC_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCMAC_STATUS_CANCELED. + * + * @note Only the same thread that started an operation is permitted to cancel it. + * This function cannot be be called from an interrupt context or callback. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESCMAC_STATUS_SUCCESS The operation was canceled or the operation had already completed. + */ +int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle); + +/** + * @brief Constructs a new AESCMAC object + * + * Unlike #AESCMAC_open(), #AESCMAC_construct() does not require the hwAttrs and + * object to be allocated in a #AESCMAC_Config array that is indexed into. + * Instead, the #AESCMAC_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @note #AESCMAC_Params @a operationalMode may be set to + * enable CBC-MAC mode but the default is CMAC mode + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + * + * @param [in] config #AESCMAC_Config describing the location of the object and hwAttrs. + * + * @param [in] params #AESCMAC_Params to configure the driver instance. + * + * @return Returns a #AESCMAC_Handle on success or NULL on failure. + */ +AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCMAC__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCTR.c b/simplelink_lpf2/source/ti/drivers/AESCTR.c new file mode 100644 index 00000000..c5cd8dc9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCTR.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTR.c ======== + * + * This file contains default values for the AESCTR_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESCTR_Config AESCTR_config[]; +extern const uint_least8_t AESCTR_count; + +const AESCTR_Params AESCTR_defaultParams = { + .returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESCTR_Params_init ======== + */ +void AESCTR_Params_init(AESCTR_Params *params) +{ + *params = AESCTR_defaultParams; +} + +/* + * ======== AESCTR_open ======== + */ +__attribute__((weak)) AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params) +{ + DebugP_assert(index < AESCTR_count); + + AESCTR_Config *config = (AESCTR_Config *)&AESCTR_config[index]; + return AESCTR_construct(config, params); +} + +/* + * ======== AESCTR_Operation_init ======== + */ +void AESCTR_Operation_init(AESCTR_Operation *operation) +{ + AESCTR_OneStepOperation_init(operation); +} + +/* + * ======== AESCTR_Operation_init ======== + */ +void AESCTR_OneStepOperation_init(AESCTR_OneStepOperation *operation) +{ + memset(operation, 0x00, sizeof(AESCTR_OneStepOperation)); +} + +/* + * ======== AESCTR_SegmentedOperation_init ======== + */ +void AESCTR_SegmentedOperation_init(AESCTR_SegmentedOperation *operation) +{ + memset(operation, 0x00, sizeof(AESCTR_SegmentedOperation)); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESCTR.h b/simplelink_lpf2/source/ti/drivers/AESCTR.h new file mode 100644 index 00000000..9a77b730 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCTR.h @@ -0,0 +1,1051 @@ +/* + * Copyright (c) 2018-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTR.h + * + * @brief AESCTR driver header + * + * @anchor ti_drivers_AESCTR_Overview + *

Overview

+ * The Counter (CTR) mode of operation is a generic block cipher mode of operation + * that can be used with any block cipher including AES which is used in this + * implementation. + * + * CTR mode encrypts and decrypts messages. It is not required for the message + * length to be evenly divisible by the cipher block size. This also means + * that padding the message is not required. + * + *

Operation

+ * CTR encryption and decryption perform the following steps: + * -# Set the counter value to the initial counter value + * -# Encrypt the counter value under the symmetric key + * -# XOR the encrypted counter value with the input block (plaintext or ciphertext) + * -# Increment the counter value. Interpret the byte array as a big-endian number. + * -# Repeat steps 2 to 4 until the input is completely processed. If the + * input is not evenly divisible by the block size, XOR the last + * (u = input length % block size) input bytes with the most significant + * u bytes of the last encrypted counter value. + * + * CTR performs the same steps regardless of whether it is used to + * encrypt or decrypt a message. The input merely changes. + * + *

Choosing Initial Counter Values

+ * CTR requires that each counter value used to encrypt a block of a message + * is unique for each key used. If this requirement is not kept, the + * confidentiality of that message block may be compromised. + * + * There are two general strategies when choosing the initial counter value + * of a CTR operation to ensure this requirement holds. + * + * The first is to choose an initial counter value for the first message + * and increment the initial counter value for a subsequent message by + * by message length % block length (16-bytes for AES). This effectively + * turns a sequence of messages into one long message. If 0 is chosen + * as the initial counter value, up to 2^128 - 1 blocks may be encrypted before + * key rotation is mandatory. + * + * The second is to split the initial counter value into a nonce and + * counter section. The nonce of length n bits must be unique per message. + * This allows for up to 2^n - 1 messages to be encrypted before + * key rotation is required. The counter section of length c is incremented + * as usual. This limits messages to a length of at most 2^c - 1 blocks. + * n and c must be chosen such that n + c = block length in bits + * (128 bits for AES) holds. + * + * @anchor ti_drivers_AESCTR_Usage + *

Usage

+ *

Before starting a CTR operation

+ * + * Before starting a CTR operation, the application must do the following: + * - Call #AESCTR_init() to initialize the driver + * - Call #AESCTR_Params_init() to initialize the #AESCTR_Params to default values. + * - Modify the #AESCTR_Params as desired + * - Call #AESCTR_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESCTR API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a single-step AESCTR operation using #AESCTR_OneStepOperation_init() + * which is equivalent to the deprecated #AESCTR_Operation_init(). If it's + * a segmented AESCTR operation, use #AESCTR_SegmentedOperation_init() instead. + * Then set all the fields of the one-step or segmented operation struct accordingly. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, CTR operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Output buffer address must be 32-bit aligned. + * - Input length must be a block-size (16-byte) multiple. + * + *

Starting a CTR operation

+ * + * The AESCTR_oneStepEncrypt() and AESCTR_oneStepDecrypt() functions perform a CTR operation + * in a single call. + * + *

After the CTR operation completes

+ * + * After the CTR operation completes, the application should either start + * another operation or close the driver by calling #AESCTR_close(). + * + * @anchor ti_drivers_AESCTR_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESCTR_Synopsis_Code + * @code + * + * // Import AESCTR Driver definitions + * #include + * + * // Define name for AESCTR channel index + * #define AESCTR_INSTANCE 0 + * + * AESCTR_init(); + * + * handle = AESCTR_open(AESCTR_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESCTR_Operation + * AESCTR_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * AESCTR_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTR_Examples + *

Examples

+ * + *
One step CTR encryption with plaintext CryptoKey in blocking return mode
+ * @code + * + * #include + * #include + * + * ... + * + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector from NIST SP 800-38A + * uint8_t initialCounter[16] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + * 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}; + * uint8_t plaintext[64] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, + * 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + * 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, + * 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + * + * handle = AESCTR_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation operation; + * AESCTR_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // The ciphertext should be the following after the encryption operation: + * // 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, + * // 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce, + * // 0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, + * // 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff, + * // 0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, + * // 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab, + * // 0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, + * // 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee + * + * AESCTR_close(handle); + * + * @endcode + * + *

The following code snippet is for CC27XX devices only and leverages the HSM which is a seperate Hardware + * Accelerator

+ * + *
One step CTR encryption with plaintext CryptoKey in blocking return mode using the HSM accelerator
+ * @code + * + * #include + * #include + * + * ... + * + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * // For example purposes only. Generate IVs in a non-static way in practice. + * // Test vector from NIST SP 800-38A + * uint8_t initialCounter[16] = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + * 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}; + * uint8_t plaintext[64] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + * 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, + * 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + * 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, + * 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + * + * handle = AESCTR_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation operation; + * AESCTR_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.initialCounter = initialCounter; + * + * encryptionResult = AESCTR_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // The ciphertext should be the following after the encryption operation: + * // 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, + * // 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce, + * // 0x98, 0x06, 0xf6, 0x6b, 0x79, 0x70, 0xfd, 0xff, + * // 0x86, 0x17, 0x18, 0x7b, 0xb9, 0xff, 0xfd, 0xff, + * // 0x5a, 0xe4, 0xdf, 0x3e, 0xdb, 0xd5, 0xd3, 0x5e, + * // 0x5b, 0x4f, 0x09, 0x02, 0x0d, 0xb0, 0x3e, 0xab, + * // 0x1e, 0x03, 0x1d, 0xda, 0x2f, 0xbe, 0x03, 0xd1, + * // 0x79, 0x21, 0x70, 0xa0, 0xf3, 0x00, 0x9c, 0xee + * + * AESCTR_close(handle); + * + * @endcode + * + *
One step CTR decryption with plaintext CryptoKey in callback return mode
+ * @code + * + * #include + * #include + * + * ... + * + * + * void ctrCallback(AESCTR_Handle handle, + * int_fast16_t returnValue, + * AESCTR_OperationUnion *operation, + * AESCTR_OperationType operationType) { + * + * if (returnValue != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * } + * AESCTR_Operation operation; + * + * void ctrStartFunction(void) { + * uint8_t initialCounter[16] = {0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + * 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01}; + * uint8_t ciphertext[] = {0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + * 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + * 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + * 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + * 0x25, 0xB2, 0x07, 0x2F}; + * uint8_t keyingMaterial[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + * 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * AESCTR_Handle handle; + * AESCTR_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESCTR_OneStepOperation operation; + * + * AESCTR_Params_init(¶ms); + * params.returnBehavior = AESCTR_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ctrCallback; + * + * handle = AESCTR_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_OneStepOperation_init(&operation); // Optional as all struct members will be set before use. + * + * operation.key = &cryptoKey; + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.initialCounter = initialCounter; + * + * decryptionResult = AESCTR_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESCTR_STATUS_SUCCESS) { + * // handle error + * while(1); + * } + * + * // do other things while CTR operation completes in the background + * + * // After the operation completes and the callback is invoked, the resultant + * // plaintext should be: + * // 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * // 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + * // 0x20, 0x21, 0x22, 0x23 + * + * AESCTR_close(handle); + * } + * + * @endcode + * + *
Multi-step AES CTR encrypt with plaintext CryptoKey in polling return mode
+ * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * ... + * + * AESCTR_Params params; + * AESCTR_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t retVal; + * + * // For example purposes only. + * uint8_t plaintext[36] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + * 0x20, 0x21, 0x22, 0x23}; + * uint8_t initialCounter[] = {0x00, 0xE0, 0x01, 0x7B, 0x27, 0x77, 0x7F, 0x3F, + * 0x4A, 0x17, 0x86, 0xF0, 0x00, 0x00, 0x00, 0x01}; + * uint8_t keyingMaterial[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + * 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + * uint8_t ciphertext[sizeof(plaintext)]; + * + * AESCTR_Params_init(¶ms) + * params.returnBehavior = AESCTR_RETURN_BEHAVIOR_POLLING; + * + * handle = AESCTR_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESCTR_SegmentedOperation operation; + * AESCTR_SegmentedOperation_init(&operation); // Optional as all struct members will be set before use. + * + * retVal = AESCTR_setupEncrypt(handle, &cryptoKey, initialCounter); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext; + * operation.inputLength = AES_BLOCK_SIZE; // Only block multiple lengths are permitted when adding data. + * operation.output = ciphertext; + * + * retVal = AESCTR_addData(handle, &operation); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.inputLength = sizeof(plaintext) - AES_BLOCK_SIZE; // Non-block multiple length permitted during + * finalization. operation.output = ciphertext + AES_BLOCK_SIZE; + * + * retVal = AESCTR_finalize(handle, &operation); + * + * if (retVal != AESCTR_STATUS_SUCCESS) { + * // handle error + * } + * + * // Upon successful return, the resulting ciphertext should be: + * // 0xC1, 0xCF, 0x48, 0xA8, 0x9F, 0x2F, 0xFD, 0xD9, + * // 0xCF, 0x46, 0x52, 0xE9, 0xEF, 0xDB, 0x72, 0xD7, + * // 0x45, 0x40, 0xA4, 0x2B, 0xDE, 0x6D, 0x78, 0x36, + * // 0xD5, 0x9A, 0x5C, 0xEA, 0xAE, 0xF3, 0x10, 0x53, + * // 0x25, 0xB2, 0x07, 0x2F + * + * AESCTR_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_AESCTR__include +#define ti_drivers_AESCTR__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCTR status code reservation offset. + * AESCTR driver implementations should offset status codes with + * #AESCTR_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRXYZ_STATUS_ERROR0 AESCTR_STATUS_RESERVED - 0 + * #define AESCTRXYZ_STATUS_ERROR1 AESCTR_STATUS_RESERVED - 1 + * #define AESCTRXYZ_STATUS_ERROR2 AESCTR_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTR_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCTR_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTR_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTR_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTR_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTR driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTR_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESCTR_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported. + */ +#define AESCTR_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESCTR_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESCTR_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCTR driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief The way in which CTR function calls return after performing an + * encryption or decryption operation. + * + * Not all CTR operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTR functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESCTR_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESCTR_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESCTR_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESCTR_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * CTR operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCTR_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the CTR operation goes + * on in the background. CTR operation results are available + * after the function returns. + */ + AESCTR_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while CTR + * operation goes on in the background. CTR operation results + * are available after the function returns. + */ +} AESCTR_ReturnBehavior; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message using a one-step operation. + * + * The driver may access it at any point during the operation. It must remain + * in scope for the entire duration of the operation. + */ +typedef struct +{ + const CryptoKey *key; /*!< Pointer to a previously initialized CryptoKey. */ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * Size of the output buffer must be greater than + * or equal to the inputLength. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + const uint8_t *initialCounter; /*!< A buffer containing an initial counter. Under + * the same key, each counter value may only be + * used to encrypt or decrypt a single input + * block. If NULL, zero will be used for the + * initial counter value. The buffer's size must + * be at least 16-bytes. + */ + size_t inputLength; /*!< Length of the input in bytes. An equal number + * of bytes will be output by the operation. + * Max length supported may be limited depending on + * the return behavior. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ +} AESCTR_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message using a segmented operation. This struct must be updated + * for each "add data" and "finalize" step. Modifying the structure and any buffers that + * it points to while an operation is in progress is prohibited. + * + * The driver may access it at any point during the operation. It must remain + * in scope for the entire duration of the operation. + */ +typedef struct +{ + const uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + * + * Size of the output buffer must be greater than + * or equal to the inputLength. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the output buffer needs to + * be 32-bit aligned. + */ + size_t inputLength; /*!< Length of the input in bytes. An equal number + * of bytes will be output by the operation. Must + * be a non-zero multiple of block size (16-bytes) when + * calling #AESCTR_addData(). May be zero when calling + * #AESCTR_finalize() to finalize a segmented + * operation without additional data. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ +} AESCTR_SegmentedOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESCTR_Operation. + * Existing code should be refactored to use AESCTR_OneStepOperation. + * This reference may be removed at some point in the future. + */ +typedef AESCTR_OneStepOperation AESCTR_Operation; + +/*! + * @brief Union containing a reference to a one-step and segmented operation + * structure. + */ +typedef union +{ + AESCTR_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESCTR_SegmentedOperation segmentedOperation; /* Segmented operation element of the operation union */ +} AESCTR_OperationUnion; + +/*! + * @brief Enum for the direction of the CTR operation. + */ +typedef enum +{ + AESCTR_MODE_ENCRYPT = 1, + AESCTR_MODE_DECRYPT = 2, +} AESCTR_Mode; + +/*! + * @brief Mask for the operation mode. + */ +#define AESCTR_OP_MODE_MASK 0x0F + +/*! + * @brief Flag indicating a segmented operation. + */ +#define AESCTR_OP_FLAG_SEGMENTED 0x10 /* bit 4 */ + +/*! + * @brief Flag indicating a finalize operation. + */ +#define AESCTR_OP_FLAG_FINALIZE 0x20 /* bit 5 */ + +/*! + * @brief Mask for all valid operation flags. + */ +#define AESCTR_OP_FLAGS_MASK (AESCTR_OP_FLAG_SEGMENTED | AESCTR_OP_FLAG_FINALIZE) + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESCTR_OPERATION_TYPE_ENCRYPT = AESCTR_MODE_ENCRYPT, + AESCTR_OPERATION_TYPE_DECRYPT = AESCTR_MODE_DECRYPT, + AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED = (AESCTR_MODE_ENCRYPT | AESCTR_OP_FLAG_SEGMENTED), + AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED = (AESCTR_MODE_DECRYPT | AESCTR_OP_FLAG_SEGMENTED), + AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE = (AESCTR_MODE_ENCRYPT | AESCTR_OP_FLAG_FINALIZE), + AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE = (AESCTR_MODE_DECRYPT | AESCTR_OP_FLAG_FINALIZE), +} AESCTR_OperationType; + +/*! + * @brief AESCTR Global configuration + * + * The #AESCTR_Config structure contains a set of pointers used to characterize + * the AESCTR driver implementation. + * + * This structure needs to be defined before calling #AESCTR_init() and it must + * not be changed thereafter. + * + * @sa #AESCTR_init() + */ +typedef AESCommon_Config AESCTR_Config; + +/*! + * @brief A handle that is returned from an #AESCTR_open() call. + */ +typedef AESCTR_Config *AESCTR_Handle; + +/*! + * @brief The definition of a callback function used by the AESCTR driver + * when used in ::AESCTR_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the CTR operation. + * + * @param returnValue The result of the CTR operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation Pointer to the operation union struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESCTR_CallbackFxn)(AESCTR_Handle handle, + int_fast16_t returnValue, + AESCTR_OperationUnion *operation, + AESCTR_OperationType operationType); + +/*! + * @brief CTR Parameters + * + * CTR Parameters are for #AESCTR_open() and #AESCTR_construct() calls. + * Default values for these parameters are set using #AESCTR_Params_init(). + * + * @sa #AESCTR_Params_init() + */ +typedef struct +{ + AESCTR_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCTR_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCTR_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTR_Params; + +/*! + * @brief Default #AESCTR_Params structure + * + * @sa #AESCTR_Params_init() + */ +extern const AESCTR_Params AESCTR_defaultParams; + +/*! + * @brief This function initializes the CTR module. + * + * @pre The AESCTR_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CTR driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTR_init(void); + +/*! + * @brief Function to initialize the #AESCTR_Params struct to its defaults + * + * @param [in] params Pointer to #AESCTR_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESCTR_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESCTR_Params_init(AESCTR_Params *params); + +/*! + * @brief This function opens a given AESCTR peripheral. + * + * @pre AESCTR driver has been initialized using #AESCTR_init() + * + * @param [in] index Logical peripheral number for the CTR indexed into + * the AESCTR_config table + * + * @param [in] params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #AESCTR_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTR_init() + * @sa #AESCTR_close() + */ +AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params); + +/*! + * @brief Function to close a CTR peripheral specified by the AESCTR handle + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * + * @sa #AESCTR_open() + */ +void AESCTR_close(AESCTR_Handle handle); + +/*! + * @brief Function to prepare a segmented AESCTR encryption operation. + * + * This function sets up a segmented AESCTR encryption operation. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] key Pointer to a previously initialized CryptoKey + * @param [in] initialCounter Pointer to initial counter value. + * The buffer size must be at least 16-bytes. + * If NULL, zero will be used for the initial counter value. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * + * @post #AESCTR_addData() + */ +int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter); + +/*! + * @brief Function to prepare a segmented AESCTR decryption operation. + * + * This function sets up a segmented AESCTR decryption operation. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] key Pointer to a previously initialized CryptoKey. + * @param [in] initialCounter Pointer to initial counter value. + * The buffer size must be at least 16-bytes. + * If NULL, zero will be used for the initial counter value. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * + * @post #AESCTR_addData() + */ +int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter); + +/*! + * @brief Encrypts or decrypts a segment of @a data with a @a length + * + * The @a inputLength must be a non-zero multiple of the block size (16-bytes). + * #AESCTR_addData() may be called an arbitrary number of times before + * finishing the operation with #AESCTR_finalize(). + * + * This function blocks until the final stream bytes have been computed. + * It returns immediately when ::AESCTR_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre A segmented operation has been setup using #AESCTR_setupEncrypt() or + * #AESCTR_setupDecrypt() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to #AESCTR_SegmentedOperation structure + * containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESCTR_addData() or #AESCTR_finalize() + */ +int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); + +/*! + * @brief Finalize the AES operation. If new data needs to be added, + * @c inputLength will be used to govern how many bytes will be written. + * + * @note To finalize an operation without any additional data, + * set @c inputLength to zero. The input and output buffers + * will not be used in this scenario. + * + * @pre #AESCTR_setupEncrypt() or #AESCTR_setupDecrypt() + * @pre #AESCTR_addData() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to #AESCTR_SegmentedOperation structure + * containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS In ::AESCTR_RETURN_BEHAVIOR_BLOCKING and + * ::AESCTR_RETURN_BEHAVIOR_POLLING, this means the CTR + * was generated successfully. In ::AESCTR_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware + * resource was not available. + * Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation); + +/*! + * @brief Function to initialize an #AESCTR_Operation struct to its defaults (all zeroes) + * + * @deprecated Use #AESCTR_OneStepOperation_init() or #AESCTR_SegmentedOperation_init() + * based on whether it is a one-step or a segmented AESCTR operation. + * + * @param operation Pointer to an #AESCTR_Operation structure for + * initialization + */ +void AESCTR_Operation_init(AESCTR_Operation *operation); + +/*! + * @brief Function to initialize an #AESCTR_OneStepOperation struct to its defaults (all zeroes) + * + * @param [in] operation Pointer to an #AESCTR_OneStepOperation structure for + * initialization + */ +void AESCTR_OneStepOperation_init(AESCTR_OneStepOperation *operation); + +/*! + * @brief Function to initialize an #AESCTR_SegmentedOperation struct to its defaults (all zeroes) + * + * @param [in] operation Pointer to an #AESCTR_SegmentedOperation structure for + * initialization + */ +void AESCTR_SegmentedOperation_init(AESCTR_SegmentedOperation *operation); + +/*! + * @brief Function to perform an AESCTR encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa #AESCTR_oneStepDecrypt() + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation); + +/*! + * @brief Function to perform an AESCTR decryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext. + * + * @pre #AESCTR_open() or #AESCTR_construct() + * + * @param [in] handle AESCTR handle + * @param [in] operation Pointer to a struct containing the parameters required to perform the operation. + * + * @retval #AESCTR_STATUS_SUCCESS The operation succeeded. + * @retval #AESCTR_STATUS_ERROR The operation failed. + * @retval #AESCTR_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESCTR_oneStepEncrypt() + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation); + +/*! + * @brief Cancels an ongoing AESCTR operation. + * + * Asynchronously cancels an AESCTR operation. Only available when using + * AESCTR_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESCTR_STATUS_CANCELED. + * + * @param [in] handle AESCTR handle + * + * @retval #AESCTR_STATUS_SUCCESS The operation was canceled or the operation had already completed. + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle); + +/** + * @brief Constructs a new AESCTR object + * + * Unlike #AESCTR_open(), #AESCTR_construct() does not require the hwAttrs and + * object to be allocated in a #AESCTR_Config array that is indexed into. + * Instead, the #AESCTR_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may occur. + * + * @param [in] config #AESCTR_Config describing the location of the object and hwAttrs. + * + * @param [in] params #AESCTR_Params to configure the driver instance. + * + * @return Returns a #AESCTR_Handle on success or NULL on failure. + * + + */ +AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTR__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.c b/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.c new file mode 100644 index 00000000..a7273e41 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2019-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESCTRDRBG.c ======== + * + * This file contains default values for the AESCTRDRBG_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const AESCTRDRBG_Config AESCTRDRBG_config[]; +extern const uint_least8_t AESCTRDRBG_count; + +const AESCTRDRBG_Params AESCTRDRBG_defaultParams = { + .keyLength = AESCTRDRBG_AES_KEY_LENGTH_128, + .reseedInterval = 10000, + .seed = NULL, + .personalizationData = NULL, + .personalizationDataLength = 0, + .returnBehavior = AESCTRDRBG_RETURN_BEHAVIOR_POLLING, + .custom = NULL, +}; + +/* + * ======== AESCTRDRBG_open ======== + */ +__attribute__((weak)) AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params) +{ + DebugP_assert(index < AESCTRDRBG_count); + + AESCTRDRBG_Config *config = (AESCTRDRBG_Config *)&AESCTRDRBG_config[index]; + return AESCTRDRBG_construct(config, params); +} + +/* + * ======== AESCTRDRBG_Params_init ======== + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params) +{ + *params = AESCTRDRBG_defaultParams; +} diff --git a/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.h b/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.h new file mode 100644 index 00000000..fcb9e3de --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCTRDRBG.h @@ -0,0 +1,724 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBG.h + * + * @brief AESCTRDRBG driver header + * + * @anchor ti_drivers_AESCTRDRBG_Overview + *

Overview

+ * AESCTRDRBG is a cryptographically secure deterministic random bit generator + * that is used to efficiently generate random numbers for use in keying material + * or other security related purposes. It is based on the AES block cipher + * operating in Counter (CTR) mode and is defined by NIST SP 800-90A. + * + * AESCTRDRBG derives a sequence of pseudo-random numbers based on an initial + * secret seed and additional, non-secret personalization data provided during + * instantiation. A sequence of random bits generated by AESCTRDRBG will have + * an equivalent entropy content of MIN(sequenceLength, security strength). + * The security strength is based on the seed length and the AES key length used + * in the AESCTRDRBG instance. + * + * | | AES-128 | AES-192 | AES-256 | + * |---------------------------------------|---------|---------|---------| + * | Security Strength (bits) | 128 | 192 | 256 | + * | Seed Length (bits) | 192 | 320 | 384 | + * | Personalization String Length (bits) | <= 192 | <= 320 | <= 384 | + * | Max Requests Between Reseeds | 2^48 | 2^48 | 2^48 | + * | Max Request Length (bits) | 2^19 | 2^19 | 2^19 | + * + *

Security Strength

+ * The seed must be sourced from a cryptographically secure source such as + * a True Random Number Generator and contain seed length bits of entropy. + * Since the seed length is always larger than the security strength for + * any one AES key length, the output of one AESCTRDRBG instance may not + * be used to seed another instance of the same or higher security strength. + * + *

Reseeding

+ * Because of the way AES CTR operates, there are a limited number of output + * bitstreams that may be generated before the AESCTRDRBG instance must be + * reseeded. The reseeding interval is set by the number of random bit + * sequences generated and not by their individual or combined lengths. Each time + * random bits are requested of the AESCTRDRBG instance by the application, + * the reseed counter is incremented by one regardless of how many bits at a + * time are requested. When this counter reaches the configured reseed limit, + * the AESCTRDRBG instance will return #AESCTRDRBG_STATUS_RESEED_REQUIRED + * until it is reseeded. + * + * The maximum permitted number of requests between reseeds is 2^48. + * The default counter is only 2^32 long for ease of implementation. + * A more conservative reseed limit may be configured by the application + * for increased security. + * + * A previously used seed may never be reused to reseed an AESCTRDRBG instance. + * The seed used to instantiate or reseed an instance must be generated by + * an approved entropy source. + * + *

Derivation Function

+ * NIST specifies the the use of an optional derivation function to reduced + * entropy and personalization string lengths longer than the seed + * length down to the seed length. This feature is not presently supported. + * + * @anchor ti_drivers_AESCTRDRBG_Usage + *

Usage

+ * + * This documentation provides a basic @ref ti_drivers_AESCTRDRBG_Synopsis + * "usage summary" and a set of @ref ti_drivers_AESCTRDRBG_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_AESCTRDRBG_Synopsis + *

Synopsis

+ * @anchor ti_drivers_AESCTRDRBG_Synopsis_Code + * @code + * #include + * + * AESCTRDRBG_init(); + * + * // Instantiate the AESCTRDRBG instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * + * result = AESCTRDRBG_generateKey(handle, &resultKey); + * + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * + * AESCTRDRBG_close(handle); + * @endcode + * + * @anchor ti_drivers_AESCTRDRBG_Examples + *

Examples

+ * + *

Instantiating an AESCTRDRBG Instance with TRNG

+ * @code + * + * #include + * #include + * #include + * + * ... + * + * AESCTRDRBG_Handle handle; + * AESCTRDRBG_Params params; + * TRNG_Handle trngHandle; + * int_fast16_t result; + * + * uint8_t seedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * // Open a TRNG driver instance + * trngHandle = TRNG_open(0, NULL); + * if (trngHandle == NULL) { + * // Failed to open TRNG instance + * while(1); + * } + * + * // Generate entropy for the seed + * result = TRNG_getRandomBytes(trngHandle, seedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * if (result != TRNG_STATUS_SUCCESS) { + * // Failed to generate entropy + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * // Instantiate the AESCTRDRBG parameters and the driver instance + * AESCTRDRBG_Params_init(¶ms); + * params.keyLength = AESCTRDRBG_AES_KEY_LENGTH_128; + * params.reseedInterval = 0xFFFFFFFF; + * params.seed = seedBuffer; + * + * handle = AESCTRDRBG_open(0, ¶ms); + * if (handle == NULL) { + * // Failed to open AESCTRDRBG instance + * while(1); + * } + * @endcode + * + *

Generating random key with Reseeding

+ * + * @code + * + * #include + * #include + * #include + * + * ... + * + * #define RANDOM_KEY_LENGTH_BYTES 32 + * + * AESCTRDRBG_Handle handle; + * TRNG_Handle trngHandle; + * CryptoKey randomKey; + * int_fast16_t result; + * + * uint8_t randomKeyBuffer[RANDOM_KEY_LENGTH_BYTES]; + * + * // Initialise the AESCTRDRBG params and driver instance here + * ... + * + * // Initialize a blank CryptoKey + * CryptoKeyPlaintext_initBlankKey(&randomKey, randomKeyBuffer, RANDOM_KEY_LENGTH_BYTES); + * + * // Generate key-material for the CryptoKey + * result = AESCTRDRBG_generateKey(handle, &randomKey); + * + * // Check return value and reseed if needed. This should happen only after many invocations + * // of AESCTRDRBG_generateKey(). + * if (result == AESCTRDRBG_STATUS_RESEED_REQUIRED) { + * TRNG_Handle trngHandle; + * int_fast16_t reseedResult; + * uint8_t reseedBuffer[AESCTRDRBG_SEED_LENGTH_AES_128]; + * + * reseedResult = TRNG_getRandomBytes(trngHandle, reseedBuffer, AESCTRDRBG_SEED_LENGTH_AES_128); + * if (reseedResult != TRNG_STATUS_SUCCESS) { + * // Failed to generate entropy + * while(1); + * } + * + * TRNG_close(trngHandle); + * + * // Reseed the DRBG instance + * reseedResult = AESCTRDRBG_reseed(handle, reseedBuffer, NULL, 0); + * if (reseedResult != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to reseed the DRBG instance + * while(1); + * } + * + * // If AESCTRDRBG_STATUS_RESEED_REQUIRED was returned from the previous call to + * // AESCTRDRBG_generateKey(), the random key was never generated by that call. + * // So the user must invoke that call again (after reseeding) to get a random key. + * result = AESCTRDRBG_generateKey(handle, &randomKey); + * if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate key-material + * while(1); + * } + * } + * else if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate key-material + * while(1); + * } + * + * @endcode + * + *

Generating random bytes output to an array

+ * + * @code + * + * #include + * #include + * + * ... + * + * #define RANDOM_BYTES_SIZE 16 + * + * AESCTRDRBG_Handle handle; + * TRNG_Handle trngHandle; + * int_fast16_t result; + * uint8_t randomBytesBuffer[RANDOM_BYTES_SIZE]; + * + * // Initialise the AESCTRDRBG params and driver instance here + * ... + * + * // Get random bytes output to the buffer/array + * result = AESCTRDRBG_getRandomBytes(handle, &randomBytesBuffer, RANDOM_BYTES_SIZE); + * + * // Check and reseed if required. This should happen only after many invocations + * // of AESCTRDRBG_getRandomBytes(). + * if (result == AESCTRDRBG_STATUS_RESEED_REQUIRED) { + * // Reseed the DRBG instance using AESCTRDRBG_reseed() + * // and invoke AESCTRDRBG_getRandomBytes() similar to the previous example. + * } + * else if (result != AESCTRDRBG_STATUS_SUCCESS) { + * // Failed to generate random bytes + * while(1); + * } + * + * @endcode + * + */ + +#ifndef ti_drivers_AESCTRDRBG__include +#define ti_drivers_AESCTRDRBG__include + +#include +#include +#include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESCTRDRBG status code reservation offset. + * AESCTRDRBG driver implementations should offset status codes with + * #AESCTRDRBG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESCTRDRBGXYZ_STATUS_ERROR0 AESCTRDRBG_STATUS_RESERVED - 0 + * #define AESCTRDRBGXYZ_STATUS_ERROR1 AESCTRDRBG_STATUS_RESERVED - 1 + * #define AESCTRDRBGXYZ_STATUS_ERROR2 AESCTRDRBG_STATUS_RESERVED - 2 + * @endcode + */ +#define AESCTRDRBG_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return #AESCTRDRBG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESCTRDRBG_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return #AESCTRDRBG_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESCTRDRBG_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESCTRDRBG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The AESCTRDRBG instance must be reseeded. + * + * An AESCTRDRBG instance may only service a limited number of bit + * generation requests before reseeding with more entropy is required. + */ +#define AESCTRDRBG_STATUS_RESEED_REQUIRED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 0) + +/*! + * @brief The AESCTRDRBG instance is uninstantiated. Close and reopen + * the instance. + */ +#define AESCTRDRBG_STATUS_UNINSTANTIATED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 1) + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESCTR driver implementations used by AESCTRDRBG may have restrictions on the + * alignment of input/output data due to performance limitations of the + * hardware. + */ +#define AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED (AES_STATUS_DRIVER_SPECIFIC_ERROR - 2) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return AESCTRDRBG_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define AESCTRDRBG_STATUS_KEYSTORE_ERROR (AES_STATUS_KEYSTORE_GENERIC_ERROR) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /*! + * @brief Requesting entropy from HSM operation failed due to the input length. + * + * Input length has to be less than 64KB. + */ + #define AESCTRDRBG_STATUS_INPUT_LENGTH_INVALID (AES_STATUS_KEYSTORE_GENERIC_ERROR - 1) +#endif + +/*! + * @brief The AES block size in bytes. + */ +#define AESCTRDRBG_AES_BLOCK_SIZE_BYTES 16 + +/*! + * @brief Length in bytes of the internal AES key used by an instance + */ +typedef enum +{ + AESCTRDRBG_AES_KEY_LENGTH_128 = 16, + AESCTRDRBG_AES_KEY_LENGTH_256 = 32, +} AESCTRDRBG_AES_KEY_LENGTH; + +/*! + * @brief Length in bytes of seed used to instantiate or reseed instance + */ +typedef enum +{ + AESCTRDRBG_SEED_LENGTH_AES_128 = AESCTRDRBG_AES_KEY_LENGTH_128 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, + AESCTRDRBG_SEED_LENGTH_AES_256 = AESCTRDRBG_AES_KEY_LENGTH_256 + AESCTRDRBG_AES_BLOCK_SIZE_BYTES, +} AESCTRDRBG_SEED_LENGTH; + +/*! + * @brief The way in which AESCTRDRBG function calls return after generating + * the requested entropy. + * + * Not all AESCTRDRBG operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESCTRDRBG functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |-------------------------------------|-------|-------|-------| + * |#AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING | X | | | + * |#AESCTRDRBG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + /*!< The function call will block while AESCTRDRBG operation goes + * on in the background. AESCTRDRBG operation results are available + * after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING = AESCTR_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will continuously poll a flag while AESCTRDRBG + * operation goes on in the background. AESCTRDRBG operation results + * are available after the function returns. + */ + AESCTRDRBG_RETURN_BEHAVIOR_POLLING = AESCTR_RETURN_BEHAVIOR_POLLING, +} AESCTRDRBG_ReturnBehavior; + +/*! + * @brief AESCTRDRBG Global configuration + * + * The #AESCTRDRBG_Config structure contains a set of pointers used to characterize + * the AESCTRDRBG driver implementation. + * + * This structure needs to be defined before calling #AESCTRDRBG_init() and it must + * not be changed thereafter. + * + * @sa #AESCTRDRBG_init() + */ +typedef AESCommon_Config AESCTRDRBG_Config; + +/*! + * @brief A handle that is returned from an #AESCTRDRBG_open() call. + */ +typedef AESCTRDRBG_Config *AESCTRDRBG_Handle; + +/*! + * @brief AESCTRDRBG Parameters + * + * AESCTRDRBG Parameters are used to with the #AESCTRDRBG_open() call. Default values for + * these parameters are set using #AESCTRDRBG_Params_init(). + * + * @sa #AESCTRDRBG_Params_init() + */ +typedef struct +{ + AESCTRDRBG_AES_KEY_LENGTH keyLength; /*!< Length of the internal AES key + * of the driver instance. + */ + uint32_t reseedInterval; /*!< Number of random number generation + * requests before the application is + * required to reseed the driver. + */ + const void *seed; /*!< Entropy used to seed the internal + * state of the driver. Must be one of + * #AESCTRDRBG_SEED_LENGTH long depending + * on \c keyLength. + */ + const void *personalizationData; /*!< Optional non-secret personalization + * data to mix into the driver's internal + * state. + */ + size_t personalizationDataLength; /*!< Length of the optional + * \c personalizationData. Must satisfy + * 0 <= \c personalizationDataLength <= seed length. + */ + AESCTRDRBG_ReturnBehavior returnBehavior; /*!< Return behavior of the driver instance. + * #AESCTRDRBG_RETURN_BEHAVIOR_POLLING is + * strongly recommended unless requests + * for > 500 bytes with AES-256 or + * 1250 bytes for AES-128 will be common + * use cases for this driver instance. + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESCTRDRBG_Params; + +/*! + * @brief Default #AESCTRDRBG_Params structure + * + * @sa #AESCTRDRBG_Params_init() + */ +extern const AESCTRDRBG_Params AESCTRDRBG_defaultParams; + +/*! + * @brief This function initializes the AESCTRDRBG driver. + * + * @pre The #AESCTRDRBG_Config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other AESCTRDRBG driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESCTRDRBG_init(void); + +/*! + * @brief Function to initialize the #AESCTRDRBG_Params struct to its defaults + * + * @param [out] params Pointer to #AESCTRDRBG_Params structure for + * initialization + */ +void AESCTRDRBG_Params_init(AESCTRDRBG_Params *params); + +/*! + * @brief This function opens a given AESCTRDRBG instance. + * + * @pre AESCTRDRBG controller has been initialized using #AESCTRDRBG_init() + * + * @param [in] index Logical peripheral number for the AESCTRDRBG indexed into + * the #AESCTRDRBG_Config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESCTRDRBG_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa #AESCTRDRBG_init() + * @sa #AESCTRDRBG_close() + */ +AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params); + +/*! + * @brief Function to close an AESCTRDRBG instance specified by the #AESCTRDRBG_Handle + * + * @pre #AESCTRDRBG_open() has to be called first. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @sa #AESCTRDRBG_open() + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle); + +/*! + * @brief Generates the requested number of random bytes. + * + * @deprecated This function has been replaced by a pair of new functions. + * See #AESCTRDRBG_generateKey() and #AESCTRDRBG_getRandomBytes(). + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in,out] randomBytes Pointer to a \c CryptoKey object that should be already initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated random bytes will + * be populated. Some implementations may require key-material to be + * word-aligned. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Random bytes not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomBytes key material must be word-aligned. + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes); + +/*! + * @brief Populates the provided \c CryptoKey object's plaintext key-material with random bytes. + * + * @note This function replaces #AESCTRDRBG_getBytes(). + * See #AESCTRDRBG_getRandomBytes() to output random bytes to an array instead. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in,out] randomKey Pointer to a \c CryptoKey object that should be already initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated random bytes will + * be populated. Some implementations may require key-material to be + * word-aligned. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Key-material generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Key-material not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Key-material not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Key-material not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Key-material not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomKey key material must be word-aligned. + */ +int_fast16_t AESCTRDRBG_generateKey(AESCTRDRBG_Handle handle, CryptoKey *randomKey); + +/*! + * @brief Generates the requested number of random bytes and outputs to the given array. + * + * @attention This function should not be confused with the deprecated #AESCTRDRBG_getBytes(). + * #AESCTRDRBG_getBytes() output random bytes to a \c CryptoKey while this new + * function outputs random bytes to an array. + * + * @note See #AESCTRDRBG_generateKey() to output random bytes to a \c CryptoKey instead. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [out] randomBytes A pointer to an array that stores the random bytes + * output by this function. Some implementations may + * require this array to be word-aligned. + * + * @param [in] randomBytesSize The size in bytes of the random data required. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_RESEED_REQUIRED Reseed counter >= reseed limit. Reseed required. Random bytes not + * generated. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh seed. + * Random bytes not generated. + * @retval #AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED Pointer to \c randomBytes array must be word-aligned. + */ +int_fast16_t AESCTRDRBG_getRandomBytes(AESCTRDRBG_Handle handle, void *randomBytes, size_t randomBytesSize); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/*! + * @brief Generates the requested number of random bytes and outputs to the given array. + * + * This operation bypasses the existing AESCTRDRBG design by fetching random bytes directly from the HSM. + * + * @attention This function leverages the HSM DRBG IP directly. + * Limitations: + * 1. An upper limit of 64KB per request. + * 2. All request amounts have to be 32-bit aligned (multiple of 4). + * + * This API does not utilize the provided seed or the counter but rather relies on the HSM to generate deterministic + * data. + * + * This API operates in a synchronous polling mode. + * + * @param [out] randomBytes A pointer to an array that stores the random bytes + * output by this function. This array has to be word-aligned. + * + * @param [in] randomBytesSize The size in bytes of the random data required. + * The size must be a multiple of 4 bytes. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Random bytes generated. + * @retval #AESCTRDRBG_STATUS_ERROR Generic driver error. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. + * @retval #AESCTRDRBG_STATUS_INPUT_LENGTH_INVALID Length has to be less than 64KB. + */ +int_fast16_t AESCTRDRBG_getRandomBytesFromHSM(void *randomBytes, size_t randomBytesSize); + +/*! + * @brief Reseed the HSM IP DRBG engine + * + * @attention This function makes a direct call to the HSM engine to force a reseed to the HSM IP. + * + * Although the HSM IP auto-reseeds internally after a pre-defined level set in the OTP (256 * 64KB) entropy + * have been fetched, this API is provided to the user to call whenever they want to force a reseed. + * + * This operation is done asynchronously which means the call returns as soon as the request is deposited to the HSM + * engine and does not notify the user when the operation is complete. + * + * Whilst the operation is running, the underlying HSM access semaphore is taken and no other operations or threads can + * leverage the HSM IP. The #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE error code will be returned. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Reseeding was successful. + * @retval #AESCTRDRBG_STATUS_ERROR Reseeding was not successful. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The required hardware was unavailable. + */ +int_fast16_t AESCTRDRBG_reseedHSM(void); +#endif + +/*! + * @brief Reseed an AESCTRDRBG instance. + * + * @param [in] handle An #AESCTRDRBG_Handle returned from #AESCTRDRBG_open() + * + * @param [in] seed Entropy to mix into the AESCTRDRBG instance state + * + * @param [in] additionalData Optional non-secret additional data to mix into the + * instance state. + * + * @param [in] additionalDataLength Length of the optional additional data. + * 0 <= \c additionalDataLength <= seed length of the + * instance. + * + * @retval #AESCTRDRBG_STATUS_SUCCESS Reseed successful. Reseed counter reset. + * @retval #AESCTRDRBG_STATUS_ERROR Reseed not successful. Reseed counter not reset. + * @retval #AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE The requires hardware was unavailable. + * @retval #AESCTRDRBG_STATUS_UNINSTANTIATED DRBG uninstantiated. Close and reopen the instance with fresh + * seed. + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength); + +/** + * @brief Constructs a new AESCTRDRBG object + * + * Unlike #AESCTRDRBG_open(), #AESCTRDRBG_construct() does not require the hwAttrs and + * object to be allocated in a #AESCTRDRBG_Config array that is indexed into. + * Instead, the #AESCTRDRBG_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESCTRDRBG_Config describing the location of the object and hwAttrs. + * + * @param params #AESCTRDRBG_Params to configure the driver instance. + * + * @return Returns an #AESCTRDRBG_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESCTRDRBG_Handle AESCTRDRBG_construct(AESCTRDRBG_Config *config, const AESCTRDRBG_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCTRDRBG__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESCommon.h b/simplelink_lpf2/source/ti/drivers/AESCommon.h new file mode 100644 index 00000000..0bb4fb87 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESCommon.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!*************************************************************************** + * @file AESCommon.h + * + * @brief AES common module header for all devices + *****************************************************************************/ + +#ifndef ti_drivers_AESCommon_include +#define ti_drivers_AESCommon_include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Successful status code. + * + * Functions return #AES_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AES_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return #AES_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AES_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AES driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ +#define AES_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define AES_STATUS_CANCELED ((int_fast16_t)-3) + +/*! + * @brief The MAC verification failed. + * + * Functions return #AES_STATUS_MAC_INVALID if the MAC computed + * for the provided (key, message) pair did not match the MAC provided. + */ +#define AES_STATUS_MAC_INVALID ((int_fast16_t)-4) + +/*! + * @brief The operation tried to load a key from the keystore using + * an invalid key ID. + * + * This code is returned if the provided CryptoKey reference + * is returned as invalid by the key store module. + */ +#define AES_STATUS_KEYSTORE_INVALID_ID ((int_fast16_t)-5) + +/*! + * @brief The key store module returned a generic error. See key store + * documentation for additional details. + */ +#define AES_STATUS_KEYSTORE_GENERIC_ERROR ((int_fast16_t)-6) + +/*! + * @brief The operation requested is not supported. + */ +#define AES_STATUS_FEATURE_NOT_SUPPORTED ((int_fast16_t)-7) + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + */ +#define AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED ((int_fast16_t)-8) + +/*! + * @brief A driver shall use this error code and grow negatively until + * (AES_STATUS_RESERVED + 1) if more driver specific error codes + * are needed beyond the common codes listed above. + * + * @note Not to be confused with #AES_STATUS_RESERVED which is for defining + * device specific codes if needed for a given driver, while + * #AES_STATUS_DRIVER_SPECIFIC_ERROR is for a driver but common across + * all devices for which that driver is implemented. + * + * Example implementation specific status codes: + * @code + * #define AESXYZ_STATUS_ERROR0 AES_STATUS_DRIVER_SPECIFIC_ERROR - 0 + * #define AESXYZ_STATUS_ERROR1 AES_STATUS_DRIVER_SPECIFIC_ERROR - 1 + * #define AESXYZ_STATUS_ERROR2 AES_STATUS_DRIVER_SPECIFIC_ERROR - 2 + * @endcode + */ +#define AES_STATUS_DRIVER_SPECIFIC_ERROR ((int_fast16_t)-16) + +/*! + * Common AES status code reservation offset. + * AES driver implementations should offset status codes with + * #AES_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESXYZCCXXXX_STATUS_ERROR0 AES_STATUS_RESERVED - 0 + * #define AESXYZCCXXXX_STATUS_ERROR1 AES_STATUS_RESERVED - 1 + * #define AESXYZCCXXXX_STATUS_ERROR2 AES_STATUS_RESERVED - 2 + * @endcode + */ +#define AES_STATUS_RESERVED ((int_fast16_t)-32) + +/*! + * @brief AES Global configuration + * + * The #AESCommon_Config structure contains a set of pointers used to + * characterize the AES driver implementation. + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} AESCommon_Config; + +/*! + * @brief The return behavior of AES functions + * + * Not all AES operations exhibit the specified return behavior. Functions + * that do not require significant computation and cannot offload that + * computation to a background thread behave like regular functions. + * Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation + * run on the same CPU as the application will emulate the return behavior + * while not actually offloading the computation to the background thread. + * + * AES functions exhibiting the specified return behavior have restrictions + * on the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |-----------------------------|-------|-------|-------| + * |AES_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AES_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AES_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AES_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AES_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the operation goes + * on in the background. Operation results are available + * after the function returns. + */ + AES_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while + * operation goes on in the background. Operation results + * are available after the function returns. + */ +} AES_ReturnBehavior; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESCommon__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESECB.c b/simplelink_lpf2/source/ti/drivers/AESECB.c new file mode 100644 index 00000000..b02ee5b9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESECB.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESECB.c ======== + * + * This file contains default values for the AESECB_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESECB_Config AESECB_config[]; +extern const uint_least8_t AESECB_count; + +const AESECB_Params AESECB_defaultParams = { + .returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESECB_Params_init ======== + */ +void AESECB_Params_init(AESECB_Params *params) +{ + *params = AESECB_defaultParams; +} + +/* + * ======== AESECB_Operation_init ======== + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESECB_Operation)); +} + +/* + * ======== AESECB_open ======== + */ +__attribute__((weak)) AESECB_Handle AESECB_open(uint_least8_t index, const AESECB_Params *params) +{ + DebugP_assert(index < AESECB_count); + + AESECB_Config *config = (AESECB_Config *)&AESECB_config[index]; + return AESECB_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESECB.h b/simplelink_lpf2/source/ti/drivers/AESECB.h new file mode 100644 index 00000000..c4562295 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESECB.h @@ -0,0 +1,928 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESECB.h + * + * @brief AESECB driver header + * + * @anchor ti_drivers_AESECB_Overview + * # Overview # + * The Electronic Code Book (ECB) mode of operation is a generic + * encryption block cipher mode. It can be used with any block cipher. + * AESECB encrypts or decrypts one or multiple blocks of plaintext or ciphertext + * using the Advanced Encryption Standard (AES) block cipher. + * Each input block is individually encrypted or decrypted. This means that + * blocks of ciphertext can be decrypted individually and out of order. + * Encrypting the same plaintext using the same key yields identical ciphertext. + * This raises several security issues. For this reason, ECB is not recommended + * unless interfacing with legacy systems which cannot be updated + * or where a standard specifies its use. Better alternatives would be an + * authenticated encryption with associated data (AEAD) mode such as + * CCM or GCM. + * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * @anchor ti_drivers_AESECB_Usage + * # Usage # + * + * ## Before starting an ECB operation # + * + * Before starting an ECB operation, the application must do the following: + * - Call AESECB_init() to initialize the driver + * - Call AESECB_Params_init() to initialize the AESECB_Params to default values. + * - Modify the AESECB_Params as desired + * - Call AESECB_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESECB API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the AESECB_Operation using AESECB_Operation_init() and set all + * length, key, and buffer fields. + * + * ## Starting an ECB operation # + * + * The AESECB_oneStepEncrypt and AESECB_oneStepDecrypt functions do an ECB operation in a single call. + * They will always be the most highly optimized routines with the least overhead and the fastest + * runtime. Since ECB plaintext blocks are simply encrypted with the block cipher block by block, + * there is no difference in the ciphertext between encrypting two blocks in one go or encrypting + * each block individually. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, ECB operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Output buffer address must be 32-bit aligned. + * + * ## After the ECB operation completes # + * + * After the ECB operation completes, the application should either start another operation + * or close the driver by calling AESECB_close() + * + * @anchor ti_drivers_AESECB_Synopsis + * ## Synopsis + * @anchor ti_drivers_AESECB_Synopsis_Code + * @code + * // Import AESECB Driver definitions + * #include + * + * AESECB_init(); + * + * // Define name for AESECB channel index + * #define AESECB_INSTANCE 0 + * + * handle = AESECB_open(AESECB_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESECB_Operation + * AESECB_Operation_init(&operation); + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * AESECB_close(handle); + * @endcode + * + * @anchor ti_drivers_AESECB_Examples + * + * ## Examples + * + * ### Encryption of multiple plaintext blocks in blocking mode # + * @code + * + * #include + * #include + * + * ... + * + * AESECB_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t plaintext[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c} + * + * handle = AESECB_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation operation; + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * encryptionResult = AESECB_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resultant ciphertext should be: + * // 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, + * // 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97, + * // 0xf5, 0xd3, 0xd5, 0x85, 0x03, 0xb9, 0x69, 0x9d, + * // 0xe7, 0x85, 0x89, 0x5a, 0x96, 0xfd, 0xba, 0xaf + * + * + * AESECB_close(handle); + * + * @endcode + * + * ### One step ECB decryption in callback mode # + * @code + * + * #include + * #include + * + * ... + * + * uint8_t ciphertext[] = {0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, + * 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8}; + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * // 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * + * + * void ecbCallback(AESECB_Handle handle, + * int_fast16_t returnValue, + * AESECB_Operation *operation, + * AESECB_OperationType operationType) { + * + * if (returnValue != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESECB_Operation operation; + * + * void ecbStartFunction(void) { + * AESECB_Handle handle; + * AESECB_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESECB_Params_init(¶ms); + * params.returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ecbCallback; + * + * handle = AESECB_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESECB_Operation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) + * // for one-step operations. The user or application should take care of + * // necessary padding. + * operation.inputLength = sizeof(plaintext); + * + * decryptionResult = AESECB_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while ECB operation completes in the background + * + * } + * + * @endcode + * + * ### Multi-step ECB encryption in blocking mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * ... + * + * AESECB_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * int_fast16_t setupEncryptionResult; + * int_fast16_t finalizeEncryptionResult; + * uint8_t plaintext[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + * 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51}; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, + * 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c} + * + * handle = AESECB_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * setupEncryptionResult = AESECB_setupEncrypt(handle, &cryptoKey); + * if (setupEncryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * AESECB_Operation operation; + * AESECB_Operation_init(&operation); + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) for calling + * // #AESECB_addData(). The user or application should take care of necessary padding + * // if the final block of data is being added for the entire segmented operation. + * operation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESECB_addData(handle, &operation); + * if (encryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext + AES_BLOCK_SIZE; + * operation.output = ciphertext + AES_BLOCK_SIZE; + * // Input length must either be a non-zero multiple of block-size (16 bytes) + * // for calling #AESECB_finalize(), or it could be zero in case of finalizing without + * // any more data. The user or application should take care of necessary padding + * // for the last block of data. + * operation.inputLength = AES_BLOCK_SIZE; + * + * finalizeEncryptionResult = AESECB_finalize(handle, &operation); + * if (finalizeEncryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // The resultant ciphertext should be: + * // 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, + * // 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97, + * // 0xf5, 0xd3, 0xd5, 0x85, 0x03, 0xb9, 0x69, 0x9d, + * // 0xe7, 0x85, 0x89, 0x5a, 0x96, 0xfd, 0xba, 0xaf + * + * + * AESECB_close(handle); + * + * } + * + * @endcode + * + * ### Multi-step ECB decryption in callback mode # + * @code + * + * #include + * #include + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * ... + * uint8_t ciphertext[] = {0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, + * 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8}; + * uint8_t keyingMaterial[32] = {0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, + * 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, + * 0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, + * 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + * // 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + * + * + * void ecbCallback(AESECB_Handle handle, + * int_fast16_t returnValue, + * AESECB_Operation *operation, + * AESECB_OperationType operationType) { + * + * if (returnValue != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESECB_Operation operation; + * + * void ecbStartFunction(void) { + * AESECB_Handle handle; + * AESECB_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * int_fast16_t setupDecryptionResult; + * int_fast16_t finalizeDecryptionResult; + * + * AESECB_Params_init(¶ms); + * params.returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = ecbCallback; + * + * handle = AESECB_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * setupDecryptionResult = AESECB_setupDecrypt(handle, &cryptoKey); + * if (setupDecryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * AESECB_Operation_init(&operation); + * + * // No need to set operation.key for multi-step operations. + * operation.input = plaintext; + * operation.output = ciphertext; + * // Input length must be a non-zero multiple of block-size (16 bytes) for calling + * // #AESECB_addData(). The user or application should take care of necessary padding + * // if the final block of data is being added for the entire segmented operation. + * operation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESECB_addData(handle, &operation); + * if (decryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while ECB operation completes in the background + * + * // Input length must either be a non-zero multiple of block-size (16 bytes) + * // for calling #AESECB_finalize(), or it could be zero in case of finalizing without + * // any more data as shown in this example. There's no more data involved and padding + * // is not applicable for this finalization operation. + * operation.inputLength = 0; + * + * finalizeDecryptionResult = AESECB_finalize(handle, &operation); + * if (finalizeDecryptionResult != AESECB_STATUS_SUCCESS) { + * // handle error + * } + * + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESECB__include +#define ti_drivers_AESECB__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common AESECB status code reservation offset. + * AESECB driver implementations should offset status codes with + * AESECB_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESECBXYZ_STATUS_ERROR0 AESECB_STATUS_RESERVED - 0 + * #define AESECBXYZ_STATUS_ERROR1 AESECB_STATUS_RESERVED - 1 + * #define AESECBXYZ_STATUS_ERROR2 AESECB_STATUS_RESERVED - 2 + * @endcode + */ +#define AESECB_STATUS_RESERVED AES_STATUS_RESERVED + +/*! + * @brief Successful status code. + * + * Functions return AESECB_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESECB_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return AESECB_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESECB_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESECB driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESECB_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESECB_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief The operation requested is not supported on the target hardware + * or by the current state of the SW implementation. + */ +#define AESECB_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESECB_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESECB_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESECB driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESECB Global configuration + * + * The AESECB_Config structure contains a set of pointers used to characterize + * the AESECB driver implementation. + * + * This structure needs to be defined before calling AESECB_init() and it must + * not be changed thereafter. + * + * @sa AESECB_init() + */ +typedef AESCommon_Config AESECB_Config; + +/*! + * @brief A handle that is returned from an AESECB_open() call. + */ +typedef AESECB_Config *AESECB_Handle; + +/*! + * @brief The way in which ECB function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECB operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESECB functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESECB_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESECB_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESECB_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESECB_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * ECB operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESECB_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while ECB operation goes + * on in the background. ECB operation results are available + * after the function returns. + */ + AESECB_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while ECB + * operation goes on in the background. ECB operation results + * are available after the function returns. + */ +} AESECB_ReturnBehavior; + +/*! + * @brief Enum for the direction of the ECB operation. + */ +typedef enum +{ + AESECB_MODE_ENCRYPT = 1, + AESECB_MODE_DECRYPT = 2, +} AESECB_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and a message. + */ +typedef struct +{ + CryptoKey *key; /*!< A previously initialized CryptoKey. + * @note: Required for one-step operations only. + * For segmented operations, this pointer is not used + * and may be left uninitialized or set to NULL. + */ + uint8_t *input; /*!< + * - Encryption: A pointer to the plaintext buffer. + * - Decryption: A pointer to the ciphertext buffer. + * + * Both input and output buffers should be of the size + * \c inputLength in bytes each. + */ + uint8_t *output; /*!< + * - Encryption: A pointer to the buffer to store the + * resulting ciphertext. + * - Decryption: A pointer to the buffer to store the + * resulting plaintext. + * + * Both input and output buffers should be of the size + * \c inputLength in bytes each. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the output buffer needs to be 32-bit aligned. + */ + size_t inputLength; /*!< + * - One-step operation: Total length of the input in + * bytes. + * - Multi-step / Segmented operation: Length of the + * input in bytes for that #AESECB_addData() + * or #AESECB_finalize() call. + * + * The output will be the same length as the input. + * Max length supported may be limited depending on the + * return behavior. + * + * Must be a non-zero multiple of AES block size (16 bytes). + * May be 0 only when calling #AESECB_finalize() to + * finalize a multi-step operation without additional + * data. + * The user or application should take care of any + * necessary padding. + */ +} AESECB_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESECB_OPERATION_TYPE_ENCRYPT = 1, + AESECB_OPERATION_TYPE_DECRYPT = 2, + AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED = 3, + AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED = 4, + AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED = 5, + AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED = 6 +} AESECB_OperationType; + +/*! + * @brief The definition of a callback function used by the AESECB driver + * when used in ::AESECB_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECB operation. + * + * @param returnValue The result of the ECB operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operation A pointer to an operation struct. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESECB_CallbackFxn)(AESECB_Handle handle, + int_fast16_t returnValue, + AESECB_Operation *operation, + AESECB_OperationType operationType); + +/*! + * @brief ECB Parameters + * + * ECB Parameters are used with the #AESECB_open() call. Default values for + * these parameters are set using #AESECB_Params_init(). + * + * @sa #AESECB_Params_init() + */ +typedef struct +{ + AESECB_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESECB_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESECB_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESECB_Params; + +/*! + * @brief Default #AESECB_Params structure + * + * @sa #AESECB_Params_init() + */ +extern const AESECB_Params AESECB_defaultParams; + +/*! + * @brief This function initializes the ECB module. + * + * @pre The AESECB_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECB driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESECB_init(void); + +/*! + * @brief Function to initialize the #AESECB_Params struct to its defaults + * + * @param params An pointer to #AESECB_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESECB_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESECB_Params_init(AESECB_Params *params); + +/*! + * @brief This function opens a given ECB peripheral. + * + * @pre ECB controller has been initialized using #AESECB_init() + * + * @param [in] index Logical peripheral number for the ECB indexed into + * the AESECB_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An #AESECB_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #AESECB_init() + * @sa #AESECB_close() + */ +AESECB_Handle AESECB_open(uint_least8_t index, const AESECB_Params *params); + +/*! + * @brief Function to close an ECB peripheral specified by the ECB handle + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @sa AESECB_open() + */ +void AESECB_close(AESECB_Handle handle); + +/*! + * @brief Function to initialize an #AESECB_Operation struct to its defaults + * + * @param [in] operationStruct An pointer to #AESECB_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESECB_Operation_init(AESECB_Operation *operationStruct); + +/*! + * @brief Function to perform an AESECB encryption operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre #AESECB_open() or #AESECB_construct(), and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESECB_oneStepDecrypt() + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Function to perform an AESECB decryption in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre #AESECB_open() or #AESECB_construct(), and AESECB_Operation_init() have to be called first. + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESECB_oneStepEncrypt() + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Function to prepare a segmented AESECB encryption operation. + * + * This functions sets up a segmented AESECB encryption operation. + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() + * or #AESECB_construct() + * + * @param [in] key A previously initialized CryptoKey. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * + * @post #AESECB_addData() + */ +int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key); + +/*! + * @brief Function to prepare a segmented AESECB decryption operation. + * + * This functions sets up a segmented AESECB decryption operation. + * + * @pre #AESECB_open() or #AESECB_construct() + * + * @param [in] handle An ECB handle returned from #AESECB_open() + * or #AESECB_construct() + * + * @param [in] key A previously initialized CryptoKey. + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * + * @post #AESECB_addData() + */ +int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key); + +/*! + * @brief Encrypts or decrypts segment of @a data with a @a length + * + * #AESECB_addData() may be called an arbitrary number times before finishing the operation with + * #AESECB_finalize(). Note that this function is called for use with segmented operations. For + * segmented operations, @c inputLength will govern the input/output lengths and + * must be a AES block size multiple (16-bytes). + * + * @pre #AESECB_setupEncrypt() or #AESECB_setupDecrypt() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation Pointer to ECB operation structure() + * + * @retval #AESECB_STATUS_SUCCESS The operation succeeded. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @post #AESECB_addData() or #AESECB_finalize() + */ +int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Finalize the AES transaction. If new data needs to be added, + * @c inputLength will be used to govern how many bytes will be written. + * + * @pre #AESECB_addData() + * + * @param [in] handle An ECB handle returned from #AESECB_open() or #AESECB_construct() + * + * @param [in] operation Pointer to ECB operation structure() + * + * @retval #AESECB_STATUS_SUCCESS In ::AESECB_RETURN_BEHAVIOR_BLOCKING and + * ::AESECB_RETURN_BEHAVIOR_POLLING, this means the ECB output + * was generated successfully. In ::AESECB_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESECB_STATUS_ERROR The operation failed. + * @retval #AESECB_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESECB_STATUS_CANCELED The operation was canceled. + * @retval #AESECB_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + */ +int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation); + +/*! + * @brief Cancels an ongoing AESECB operation. + * + * Asynchronously cancels an AESECB operation. Only available when using + * AESECB_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESECB_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESECB_STATUS_SUCCESS The operation was canceled, or the requested operation had already + * completed. + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle); + +/** + * @brief Constructs a new AESECB object + * + * Unlike #AESECB_open(), #AESECB_construct() does not require the hwAttrs and + * object to be allocated in a #AESECB_Config array that is indexed into. + * Instead, the #AESECB_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESECB_Config describing the location of the object and hwAttrs. + * + * @param params #AESECB_Params to configure the driver instance. + * + * @return Returns a #AESECB_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESECB__include */ diff --git a/simplelink_lpf2/source/ti/drivers/AESGCM.c b/simplelink_lpf2/source/ti/drivers/AESGCM.c new file mode 100644 index 00000000..0b07430c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESGCM.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== AESGCM.c ======== + * + * This file contains default values for the AESGCM_Params struct. + * + */ + +#include +#include +#include + +#include +#include +#include + +/* Extern globals (board file) */ +extern const AESGCM_Config AESGCM_config[]; +extern const uint_least8_t AESGCM_count; + +const AESGCM_Params AESGCM_defaultParams = { + .returnBehavior = AESGCM_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== AESGCM_Params_init ======== + */ +void AESGCM_Params_init(AESGCM_Params *params) +{ + *params = AESGCM_defaultParams; +} + +/* + * ======== AESGCM_open ======== + */ +__attribute__((weak)) AESGCM_Handle AESGCM_open(uint_least8_t index, const AESGCM_Params *params) +{ + DebugP_assert(index < AESGCM_count); + + AESGCM_Config *config = (AESGCM_Config *)&AESGCM_config[index]; + return AESGCM_construct(config, params); +} + +/* + * ======== AESGCM_Operation_init ======== + */ +void AESGCM_Operation_init(AESGCM_Operation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESGCM_Operation)); + + /* The only supported ivLength is 12 for now */ + operationStruct->ivLength = 12; +} + +/* + * ======== AESGCM_OneStepOperation_init ======== + */ +void AESGCM_OneStepOperation_init(AESGCM_OneStepOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESGCM_OneStepOperation)); +} + +/* + * ======== AESGCM_SegmentedAADOperation_init ======== + */ +void AESGCM_SegmentedAADOperation_init(AESGCM_SegmentedAADOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESGCM_SegmentedAADOperation)); +} + +/* + * ======== AESGCM_SegmentedDataOperation_init ======== + */ +void AESGCM_SegmentedDataOperation_init(AESGCM_SegmentedDataOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESGCM_SegmentedDataOperation)); +} + +/* + * ======== AESGCM_SegmentedFinalizeOperation_init ======== + */ +void AESGCM_SegmentedFinalizeOperation_init(AESGCM_SegmentedFinalizeOperation *operationStruct) +{ + memset(operationStruct, 0x00, sizeof(AESGCM_SegmentedFinalizeOperation)); +} diff --git a/simplelink_lpf2/source/ti/drivers/AESGCM.h b/simplelink_lpf2/source/ti/drivers/AESGCM.h new file mode 100644 index 00000000..5441cbff --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/AESGCM.h @@ -0,0 +1,1481 @@ +/* + * Copyright (c) 2018-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * + * @file AESGCM.h + * + * @brief AESGCM driver header + * + * @anchor ti_drivers_AESGCM_Overview + * ### Overview # + * + * The Galois Counter Mode (GCM) mode of operation is a generic + * authenticated encryption with associated data (AEAD) block cipher mode. + * It can be implemented with any block cipher. + * AESGCM combines GHASH with the AES block cipher in CTR mode of operation. + * + * This combination of block cipher modes enables GCM to encrypt messages of any + * length and not only multiples of the block cipher block size. + * + * CTR provides confidentiality. The using GHASH and encrypting the result provides + * message integrity and authentication. + * + * The AES key is a shared secret between the two parties and has a length + * of 128, 192, or 256 bits. + * + * The IV is generated by the party performing the authenticated + * encryption operation. Within the scope of any authenticated + * encryption key, the IV value must be unique. That is, the set of + * IV values used with any given key must not contain any duplicate + * values. Using the same IV for two different messages encrypted + * with the same key destroys the security properties of GCM. + * + * The optional additional authentication data (AAD) is authenticated + * but not encrypted. Thus, the AAD is not included in the AES-GCM output. + * It can be used to authenticate packet headers, timestamps and other + * metadata. + * + * After the encryption operation, the ciphertext contains the encrypted + * data and the message authentication code (MAC). + * + * GCM is highly performant for an AEAD mode. Counter with CBC-MAC requires + * one invocation per block of AAD and two invocations of the block cipher + * per proccessed block of input; one to compute the CBC-MAC and one to + * perform CTR. GCM substitutes the block cipher invocation during CBC-MAC + * computation with computing GHASH over the same input. GHASH is significantly + * faster per block than AES. In turn, this gives GCM a performance edge + * over CCM. + * + * ### Security Considerations + * + * In each operation, GCM limits the length of the input and AAD to guarantee + * its security properties: + * - inputLength <= 2^36 - 32 bytes + * - aadLength <= 2^61 - 1 bytes + * + * The security properties of GCM rely on the MAC size. While MAC lengths of + * [4, 8, 12, 13, 14, 15, 16] bytes are permitted, it is recommended to + * use the full 16-byte MAC. + * + * See NIST SP 800-38D for more a more detailed discussion of security + * considerations. + * + * @anchor ti_drivers_AESGCM_Usage + * ### Usage # + * + * #### Before starting a GCM operation # + * + * Before starting a GCM operation, the application must do the following: + * - Call AESGCM_init() to initialize the driver + * - Call AESGCM_Params_init() to initialize the #AESGCM_Params to default values. + * - Modify the #AESGCM_Params as desired + * - Call AESGCM_open() to open an instance of the driver + * - Initialize a CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The AESGCM API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the appropriate AESGCM operation struct using the relevant + * operation init functions and set all fields. For example, one-step (one-shot + * or single call) operations should initialize AESGCM_Operation or + * AESGCM_OneStepOperation using AESGCM_Operation_init() or + * AESGCM_OneStepOperation_init(). For multi-step (segmented or multiple call) + * operations, AESGCM_SegmentedAADOperation must be initialized and set when + * processing AAD. AESGCM_SegmentedDataOperation must be initialized and set when + * dealing with payload data (plaintext or ciphertext). AESGCM_SegmentedFinalizeOperation + * must be initialized and set when finalizing the segmented operation. + * + * ## Device-Specific Requirements # + * + * For CC27XX devices, GCM operations leveraging the HSM engine + * (key encoding suffixed with _HSM) have the following requirements: + * - Output buffer address must be 32-bit aligned. + * - Input length must be a block-size (16-byte) multiple. + * + * #### Starting a GCM operation # + * + * The AESGCM_oneStepEncrypt() and AESGCM_oneStepDecrypt() functions perform a GCM operation in a single call. + * + * When performing a decryption operation with AESGCM_oneStepDecrypt(), the MAC is + * automatically verified. + * + * #### After the GCM operation completes # + * + * After the GCM operation completes, the application should either start another operation + * or close the driver by calling AESGCM_close() + * + * @anchor ti_drivers_AESGCM_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_AESGCM_Synopsis_Code + * @code + * + * // Import AESGCM Driver definitions + * #include + * + * // Define name for AESGCM channel index + * #define AESGCM_INSTANCE 0 + * + * AESGCM_init(); + * + * handle = AESGCM_open(AESGCM_INSTANCE, NULL); + * + * // Initialize symmetric key + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Set up AESGCM_OneStepOperation + * AESGCM_OneStepOperation_init(&operation); + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * operation.ivLength = sizeof(iv); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESGCM_oneStepEncrypt(handle, &operation); + * + * AESGCM_close(handle); + * @endcode + * + * @anchor ti_drivers_AESGCM_Examples + * #### Examples + * + * ##### Single call GCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * + * @code + * + * #include + * #include + * + * ... + * + * AESGCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t iv[12] = "12-byte IV "; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * handle = AESGCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESGCM_OneStepOperation operation; + * AESGCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * operation.ivLength = 12; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESGCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_close(handle); + * + * @endcode + * + *

The following code snippet is for CC27XX devices only and leverages the HSM which is a seperate Hardware + * Accelerator

+ * + * ##### Single call GCM encryption + authentication with plaintext CryptoKey in blocking return mode + * for the HSM accelerator # + * + * @code + * + * #include + * #include + * + * ... + * + * AESGCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * uint8_t iv[12] = "12-byte IV "; + * uint8_t aad[] = "This string will be authenticated but not encrypted."; + * uint8_t plaintext[] = "This string will be encrypted and authenticated."; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + * 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + * 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + * 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; + * + * handle = AESGCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintextHSM_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESGCM_OneStepOperation operation; + * AESGCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = plaintext; + * operation.output = ciphertext; + * operation.inputLength = sizeof(plaintext); + * operation.iv = iv; + * operation.ivLength = 12; + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * encryptionResult = AESGCM_oneStepEncrypt(handle, &operation); + * + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_close(handle); + * + * @endcode + * + * ##### Single call GCM decryption + verification with plaintext CryptoKey in callback return mode # + * + * @code + * + * #include + * #include + * + * ... + * + * // The following test vector is Packet Vector 1 from RFC 3610 of the IETF. + * + * uint8_t iv[] = {0x1f, 0x80, 0x3c, 0x52, 0xca, 0xc4, 0x97, 0xe1, + * 0x55, 0xaa, 0x55, 0x2d}; + * uint8_t aad[] = {0x3b, 0xba, 0x31, 0x28, 0x9d, 0x05, 0xf5, 0x0f, + * 0xed, 0x6c, 0x53, 0x35, 0x3c, 0x1f, 0x74, 0xd8, + * 0x28, 0xa9, 0x96, 0xb8, 0xd6, 0x84, 0xfe, 0x64, + * 0x7f, 0x7c, 0x40, 0xc0, 0xd5, 0x68, 0x8c, 0x89, + * 0x68, 0x1a, 0x33, 0xb1, 0x0c, 0xb7, 0x14, 0xb6, + * 0x49, 0x0b, 0xdf, 0x1f, 0x16, 0x60, 0x60, 0xa7}; + * uint8_t mac[] = {0x39, 0x03, 0xe4, 0xdc, 0xa4, 0xe7, 0xc8, 0x21, + * 0x62, 0x1a, 0xbb, 0xb2, 0x37, 0x2c, 0x97}; + * uint8_t ciphertext[] = {0xf8, 0x7e, 0xf7, 0x99, 0x4a, 0x86, 0xf3, 0xe9, + * 0xa3, 0xab, 0x6a, 0x6f, 0x2d, 0x34, 0x3b, 0xbd}; + * uint8_t keyingMaterial[] = {0x4f, 0xd7, 0xf2, 0x09, 0xdf, 0xb0, 0xdf, 0xbd, + * 0xd9, 0x8d, 0x2d, 0xb4, 0x98, 0x66, 0x4c, 0x88}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // 0x17, 0x9d, 0xcb, 0x79, 0x5c, 0x09, 0x8f, 0xc5, 0x31, 0x4b, 0xde, 0x0d, 0x39, 0x9d, 0x7a, 0x10 + * + * + * void gcmCallback(AESGCM_Handle handle, + * int_fast16_t returnValue, + * AESGCM_OperationUnion *operation, + * AESGCM_OperationType operationType) { + * + * if (returnValue != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * } + * + * AESGCM_OneStepOperation operation; + * CryptoKey cryptoKey; + * + * void gcmStartFunction(void) { + * AESGCM_Handle handle; + * AESGCM_Params params; + * int_fast16_t decryptionResult; + * + * AESGCM_Params_init(¶ms); + * params.returnBehavior = AESGCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = gcmCallback; + * + * handle = AESGCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * AESGCM_OneStepOperation_init(&operation); + * + * operation.key = &cryptoKey; + * operation.aad = aad; + * operation.aadLength = sizeof(aad); + * operation.input = ciphertext; + * operation.output = plaintext; + * operation.inputLength = sizeof(ciphertext); + * operation.iv = iv; + * operation.ivLength = sizeof(iv); + * operation.mac = mac; + * operation.macLength = sizeof(mac); + * + * decryptionResult = AESGCM_oneStepDecrypt(handle, &operation); + * + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while GCM operation completes in the background + * + * } + * + * @endcode + * + * ### Multi-step GCM encryption + authentication with plaintext CryptoKey in blocking return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * AESGCM_Handle handle; + * CryptoKey cryptoKey; + * int_fast16_t encryptionResult; + * + * uint8_t keyingMaterial[32] = {0x58, 0x53, 0xc0, 0x20, 0x94, 0x6b, 0x35, 0xf2, + * 0xc5, 0x8e, 0xc4, 0x27, 0x15, 0x2b, 0x84, 0x04, + * 0x20, 0xc4, 0x00, 0x29, 0x63, 0x6a, 0xdc, 0xbb, + * 0x02, 0x74, 0x71, 0x37, 0x8c, 0xfd, 0xde, 0x0f}; + * uint8_t aad[20] = {0x13, 0x89, 0xb5, 0x22, 0xc2, 0x4a, 0x77, 0x41, + * 0x81, 0x70, 0x05, 0x53, 0xf0, 0x24, 0x6b, 0xba, + * 0xbd, 0xd3, 0x8d, 0x6f}; + * uint8_t plaintext[32] = {0xce, 0x74, 0x58, 0xe5, 0x6a, 0xef, 0x90, 0x61, + * 0xcb, 0x0c, 0x42, 0xec, 0x23, 0x15, 0x56, 0x5e, + * 0x61, 0x68, 0xf5, 0xa6, 0x24, 0x9f, 0xfd, 0x31, + * 0x61, 0x0b, 0x6d, 0x17, 0xab, 0x64, 0x93, 0x5e}; + * uint8_t iv[12] = {0xee, 0xc3, 0x13, 0xdd, 0x07, 0xcc, 0x1b, 0x3e, + * 0x6b, 0x06, 0x8a, 0x47}; + * uint8_t mac[16]; + * uint8_t ciphertext[sizeof(plaintext)]; + * + * // The ciphertext should be the following after the encryption operation: + * // {0xea, 0xdc, 0x3b, 0x87, 0x66, 0xa7, 0x7d, 0xed, + * // 0x1a, 0x58, 0xcb, 0x72, 0x7e, 0xca, 0x2a, 0x97, + * // 0x90, 0x49, 0x6c, 0x29, 0x86, 0x54, 0xcd, 0xa7, + * // 0x8f, 0xeb, 0xf0, 0xda, 0x16, 0xb6, 0x90, 0x3b} + * + * handle = AESGCM_open(0, NULL); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * encryptionResult = AESGCM_setupEncrypt(handle, &cryptoKey, sizeof(aad), sizeof(plaintext)); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * encryptionResult = AESGCM_setIV(handle, iv, sizeof(iv)); + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedAADOperation segmentedAADOperation; + * AESGCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * // One should pass in data that is a block-sized multiple length + * // until passing in the last segment of data. + * // In that case, the input length simply needs to be a non-zero value. + * segmentedAADOperation.aadLength = sizeof(aad); + * + * encryptionResult = AESGCM_addAAD(handle, &segmentedAADOperation); + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedDataOperation segmentedDataOperation; + * AESGCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = plaintext; + * segmentedDataOperation.output = ciphertext; + * // One should pass in data that is a block-sized multiple length + * // until passing in the last segment of data. + * // In that case, the input length simply needs to be a non-zero value. + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * encryptionResult = AESGCM_addData(handle, &segmentedDataOperation); + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESGCM_SegmentedFinalizeOperation_init(&egmentedFinalizeOperation); + * segmentedFinalizeOperation.input = plaintext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.output = ciphertext + AES_BLOCK_SIZE; + * segmentedFinalizeOperation.inputLength = AES_BLOCK_SIZE; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * encryptionResult = AESGCM_finalizeEncrypt(handle, &segmentedFinalizeOperation); + * + * if (encryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_close(handle); + * + * @endcode + * + * ### Multi-step GCM decryption + verification with plaintext CryptoKey in callback return mode # + * @code + * + * #include + * #include + * + * ... + * + * #define AES_BLOCK_SIZE 16 // bytes + * + * uint8_t iv[] = {0x7f, 0xc2, 0x5c, 0x0c, 0x7a, 0x65, 0xb9, 0x50, + * 0x00, 0x23, 0xd0, 0x58}; + * uint8_t aad[] = {0x9e, 0xca, 0x27, 0x10, 0xbc, 0x1c, 0xaa, 0x99, + * 0x50, 0x2d, 0xe3, 0x0f, 0x08, 0x94, 0x30, 0x69, + * 0x7a, 0xee, 0xfc, 0x03}; + * uint8_t mac[] = {0x77, 0xb6, 0x4e, 0x40}; + * uint8_t ciphertext[] = {0xbd, 0xb4, 0x3f, 0x90, 0xf1, 0x6e, 0x26, 0xdc, + * 0xff, 0x60, 0xdb, 0x92, 0xb9, 0x6c, 0x4a, 0x2f}; + * uint8_t keyingMaterial[] = {0xfb, 0x96, 0x31, 0x2b, 0xdb, 0x8a, 0x22, 0xf1, + * 0x6f, 0xad, 0xc4, 0x23, 0x69, 0x4f, 0x45, 0x70}; + * uint8_t plaintext[sizeof(ciphertext)]; + * + * // The plaintext should be the following after the decryption operation: + * // {0xae, 0xe4, 0x16, 0xa2, 0x1f, 0x0e, 0x98, 0x3f, + * // 0xd7, 0x05, 0x20, 0xb8, 0xce, 0xdb, 0x24, 0xe5} + * + * void gcmCallback(AESGCM_Handle handle, + * int_fast16_t returnValue, + * AESGCM_OperationUnion *operation, + * AESGCM_OperationType operationType) { + * + * if (returnValue != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * if(operationType == AESGCM_OPERATION_TYPE_DECRYPT || + * operationType == AESGCM_OPERATION_TYPE_ENCRYPT) + * { + * // Callback fxn only used for one-shot operations + * // Use operation->oneStepOperation + * } + * else if(operationType == AESGCM_OP_TYPE_AAD_DECRYPT || + * operationType == AESGCM_OP_TYPE_AAD_ENCRYPT) + * { + * // Callback fxn only used for segmented AAD operations + * // Use operation->segmentedAADOperation + * } + * else if(operationType == AESGCM_OP_TYPE_DATA_DECRYPT || + * operationType == AESGCM_OP_TYPE_DATA_ENCRYPT) + * { + * // Callback fxn only used for segmented data operations + * // Use operation->segmentedDataOperation + * } + * else + * { + * // Callback fxn only used for segmented finalize operations + * // Use operation->segmentedFinalizeOperation + * } + * } + * + * void gcmStartFunction(void) { + * AESGCM_Handle handle; + * AESGCM_Params params; + * CryptoKey cryptoKey; + * int_fast16_t decryptionResult; + * + * AESGCM_Params_init(¶ms); + * params.returnBehavior = AESGCM_RETURN_BEHAVIOR_CALLBACK; + * params.callbackFxn = gcmCallback; + * + * handle = AESGCM_open(0, ¶ms); + * + * if (handle == NULL) { + * // handle error + * } + * + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * decryptionResult = AESGCM_setupDecrypt(handle, &cryptoKey, 0, 0); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // setLengths must be called if the AAD and input lengths aren't provided in setupXXXX. + * decryptionResult = AESGCM_setLengths(handle, sizeof(aad), sizeof(ciphertext)); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * decryptionResult = AESGCM_setIV(handle, iv, sizeof(iv)); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedAADOperation segmentedAADOperation; + * AESGCM_SegmentedAADOperation_init(&segmentedAADOperation); + * segmentedAADOperation.aad = aad; + * segmentedAADOperation.aadLength = sizeof(aad); + * + * decryptionResult = AESGCM_addAAD(handle, &segmentedAADOperation); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedDataOperation segmentedDataOperation; + * AESGCM_SegmentedDataOperation_init(&segmentedDataOperation); + * segmentedDataOperation.input = ciphertext; + * segmentedDataOperation.output = plaintext; + * segmentedDataOperation.inputLength = AES_BLOCK_SIZE; + * + * decryptionResult = AESGCM_addData(handle, &segmentedDataOperation); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * AESGCM_SegmentedFinalizeOperation segmentedFinalizeOperation; + * AESGCM_SegmentedFinalizeOperation_init(&egmentedFinalizeOperation); + * segmentedFinalizeOperation.input = ciphertext; + * segmentedFinalizeOperation.output = plaintext; + * + * // You can finalize with no new data + * segmentedFinalizeOperation.inputLength = 0; + * segmentedFinalizeOperation.mac = mac; + * segmentedFinalizeOperation.macLength = sizeof(mac); + * + * decryptionResult = AESGCM_finalizeDecrypt(handle, &segmentedFinalizeOperation); + * if (decryptionResult != AESGCM_STATUS_SUCCESS) { + * // handle error + * } + * + * // do other things while GCM operation completes in the background + * + * } + * + * @endcode + */ + +#ifndef ti_drivers_AESGCM__include +#define ti_drivers_AESGCM__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Only IVs with a length of 12 bytes are supported for now */ +#define AESGCM_IV_LENGTH_BYTES 12 + +/*! + * Common AESGCM status code reservation offset. + * AESGCM driver implementations should offset status codes with + * AESGCM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define AESGCMXYZ_STATUS_ERROR0 AESGCM_STATUS_RESERVED - 0 + * #define AESGCMXYZ_STATUS_ERROR1 AESGCM_STATUS_RESERVED - 1 + * #define AESGCMXYZ_STATUS_ERROR2 AESGCM_STATUS_RESERVED - 2 + * @endcode + */ +#define AESGCM_STATUS_RESERVED AES_STATUS_RESERVED +/*! + * @brief Successful status code. + * + * Functions return AESGCM_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define AESGCM_STATUS_SUCCESS AES_STATUS_SUCCESS + +/*! + * @brief Generic error status code. + * + * Functions return AESGCM_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define AESGCM_STATUS_ERROR AES_STATUS_ERROR + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * AESGCM driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define AESGCM_STATUS_RESOURCE_UNAVAILABLE AES_STATUS_RESOURCE_UNAVAILABLE + +/*! + * @brief The ongoing operation was canceled. + */ +#define AESGCM_STATUS_CANCELED AES_STATUS_CANCELED + +/*! + * @brief An error status code returned if the MAC provided by the application for + * a decryption operation does not match the one calculated during the operation. + * + * This code is returned by AESGCM_oneStepDecrypt() or AESGCM_finalizeDecrypt() if the + * verification of the MAC fails. + */ +#define AESGCM_STATUS_MAC_INVALID AES_STATUS_MAC_INVALID + +/*! + * @brief The operation requested is not supported on the target hardware. + * + * This code is returned by AES GCM segmented data operations when attempting to + * use them on device families that do not support segmented operations. + */ +#define AESGCM_STATUS_FEATURE_NOT_SUPPORTED AES_STATUS_FEATURE_NOT_SUPPORTED + +/*! + * @brief The operation tried to load a key from the keystore using an invalid key ID. + */ +#define AESGCM_STATUS_KEYSTORE_INVALID_ID AES_STATUS_KEYSTORE_INVALID_ID + +/*! + * @brief The key store module returned a generic error. See key store documentation + * for additional details. + */ +#define AESGCM_STATUS_KEYSTORE_GENERIC_ERROR AES_STATUS_KEYSTORE_GENERIC_ERROR + +/*! + * @brief The operation does not support non-word-aligned input and/or output. + * + * AESGCM driver implementations may have restrictions on the alignment of + * input/output data due to performance limitations of the hardware. + */ +#define AESGCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED AES_STATUS_UNALIGNED_IO_NOT_SUPPORTED + +/*! + * @brief AESGCM Global configuration + * + * The AESGCM_Config structure contains a set of pointers used to characterize + * the AESGCM driver implementation. + * + * This structure needs to be defined before calling AESGCM_init() and it must + * not be changed thereafter. + * + * @sa AESGCM_init() + */ +typedef AESCommon_Config AESGCM_Config; +/*! + * @brief A handle that is returned from an AESGCM_open() call. + */ +typedef AESGCM_Config *AESGCM_Handle; + +/*! + * @brief The way in which GCM function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all GCM operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * AESGCM functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |AESGCM_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |AESGCM_RETURN_BEHAVIOR_BLOCKING | X | | | + * |AESGCM_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + AESGCM_RETURN_BEHAVIOR_CALLBACK = AES_RETURN_BEHAVIOR_CALLBACK, + /*!< The function call will return immediately while the + * GCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESGCM_RETURN_BEHAVIOR_BLOCKING = AES_RETURN_BEHAVIOR_BLOCKING, + /*!< The function call will block while the GCM operation goes + * on in the background. GCM operation results are available + * after the function returns. + */ + AESGCM_RETURN_BEHAVIOR_POLLING = AES_RETURN_BEHAVIOR_POLLING, + /*!< The function call will continuously poll a flag while GCM + * operation goes on in the background. GCM operation results + * are available after the function returns. + */ +} AESGCM_ReturnBehavior; + +/*! + * @brief Enum for the direction of the GCM operation. + */ +typedef enum +{ + AESGCM_MODE_ENCRYPT = 1, + AESGCM_MODE_DECRYPT = 2, +} AESGCM_Mode; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * and authenticating/verifying a message for one-step operations. + */ +typedef struct +{ + CryptoKey *key; /*!< A previously initialized CryptoKey */ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the GCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + uint8_t *iv; /*!< A buffer containing an IV. IVs must be unique to + * each GCM operation and may not be reused. If + * ivInternallyGenerated is set, the IV will be + * generated by #AESGCM_oneStepEncrypt() and copied to + * this buffer. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of the total \c aad in bytes. Either \c aadLength or + * \c inputLength must be non-zero. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the aadLength must be block-size aligned. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Either \c aadLength or + * \c inputLength must be non-zero. Unlike this field in + * AESGCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ + uint8_t ivLength; /*!< Length of \c IV in bytes. + * See implementation-specific header for IV length support. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [4, 8, 12, 13, 14, 15, 16]. + */ + bool ivInternallyGenerated; /*!< When true, the IV buffer passed into AESGCM_oneStepEncrypt() + * will be overwritten with a randomly generated IV. + * Not supported by all implementations. + */ +} AESGCM_OneStepOperation; + +/*! + * @brief Struct containing the parameters required for + * authenticating/verifying additional data in a segmented operation. + * Must be updated for each add AAD step of a segmented operation. + */ +typedef struct +{ + uint8_t *aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + size_t aadLength; /*!< Length of the \c aad in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of + * AAD is being passed in. In that case, this value doesn't + * need to be an AES block-sized multiple. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the aadLength must be block-size aligned. + */ +} AESGCM_SegmentedAADOperation; + +/*! + * @brief Struct containing the parameters required for encrypting/decrypting + * a message in a segmented operation. Must be updated between each + * add data step of a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the GCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Must be non-zero, multiple + * of the AES block size (16 bytes) unless the last chunk of + * payload data is being passed in. In that case, this value doesn't + * need to be an AES block-sized multiple. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ +} AESGCM_SegmentedDataOperation; + +/*! + * @brief Struct containing the parameters required for finalizing an + * encryption/decryption and authentication/verification of a message + * in a segmented operation. + */ +typedef struct +{ + uint8_t *input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the GCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t *output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + * + * For cc27XX devices, when key encoding is + * _HSM suffixed, the output buffer needs to + * be 32-bit aligned. + */ + uint8_t *mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t inputLength; /*!< Length of the input/output data in bytes. Can be 0 if finalizing + * without new payload data. Unlike this field in + * AESGCM_SegmentedDataOperation, the length doesn't need to be + * block-aligned. + * + * For CC27XX devices with _HSM-suffixed key encoding, + * the inputLength must be block-size aligned. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [4, 8, 12, 13, 14, 15, 16]. + */ +} AESGCM_SegmentedFinalizeOperation; + +/** + * @deprecated + * Define a typedef for deprecated operation AESGCM_Operation. + * Existing code should be refactored to use AESGCM_OneStepOperation. + * This reference may be removed at some point in the future + * + */ +typedef AESGCM_OneStepOperation AESGCM_Operation; + +/*! + * @brief Union containing a reference to a one step, + * segmented AAD, segmented data, or segmented finalize operation. + */ +typedef union AESGCM_OperationUnion +{ + AESGCM_OneStepOperation oneStepOperation; /* One-step operation element of the operation union */ + AESGCM_SegmentedAADOperation segmentedAADOperation; /* Segmented AAD operation element of the operation union */ + AESGCM_SegmentedDataOperation segmentedDataOperation; /* Segmented data operation element of the operation union */ + AESGCM_SegmentedFinalizeOperation segmentedFinalizeOperation; /* Segmented finalize operation element of the + operation union */ +} AESGCM_OperationUnion; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + AESGCM_OPERATION_TYPE_ENCRYPT = 1, /* Fields 1 and 2 are for backward compatibility */ + AESGCM_OPERATION_TYPE_DECRYPT = 2, + AESGCM_OP_TYPE_ONESTEP_ENCRYPT = 1, /* Names changed to _OP_TYPE_ to avoid MISRA deviation from first 31 chars not + being unique */ + AESGCM_OP_TYPE_ONESTEP_DECRYPT = 2, + AESGCM_OP_TYPE_AAD_ENCRYPT = 3, + AESGCM_OP_TYPE_AAD_DECRYPT = 4, + AESGCM_OP_TYPE_DATA_ENCRYPT = 5, + AESGCM_OP_TYPE_DATA_DECRYPT = 6, + AESGCM_OP_TYPE_FINALIZE_ENCRYPT = 7, + AESGCM_OP_TYPE_FINALIZE_DECRYPT = 8, +} AESGCM_OperationType; + +/*! + * @brief The definition of a callback function used by the AESGCM driver + * when used in ::AESGCM_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the GCM operation. + * + * @param returnValue The result of the GCM operation. May contain an error code. + * Informs the application of why the callback function was + * called. + * + * @param operationUnion A pointer to an operation union. + * + * @param operationType This parameter determines which operation the + * callback refers to. + */ +typedef void (*AESGCM_CallbackFxn)(AESGCM_Handle handle, + int_fast16_t returnValue, + AESGCM_OperationUnion *operation, + AESGCM_OperationType operationType); + +/*! + * @brief GCM Parameters + * + * GCM Parameters used with the AESGCM_open() call. Default values for + * these parameters are set using AESGCM_Params_init(). + * + * @sa AESGCM_Params_init() + */ +typedef struct +{ + AESGCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESGCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESGCM_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} AESGCM_Params; + +/*! + * @brief Default AESGCM_Params structure + * + * @sa #AESGCM_Params_init() + */ +extern const AESGCM_Params AESGCM_defaultParams; + +/*! + * @brief This function initializes the GCM module. + * + * @pre The AESGCM_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GCM driver APIs. This function call does not modify any + * peripheral registers. + */ +void AESGCM_init(void); + +/*! + * @brief Function to initialize the #AESGCM_Params struct to its defaults + * + * @param params An pointer to #AESGCM_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = AESGCM_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void AESGCM_Params_init(AESGCM_Params *params); + +/*! + * @brief This function opens a given GCM peripheral. + * + * @pre GCM controller has been initialized using #AESGCM_init() + * + * @param [in] index Logical peripheral number for the GCM indexed into + * the AESGCM_config table + * + * @param [in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An AESGCM_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #AESGCM_init() + * @sa #AESGCM_close() + */ +AESGCM_Handle AESGCM_open(uint_least8_t index, const AESGCM_Params *params); + +/*! + * @brief Function to close a GCM peripheral specified by the GCM handle + * + * @pre #AESGCM_open() or #AESGCM_construct() + * + * @param [in] handle A GCM handle + * + * @sa #AESGCM_open() + */ +void AESGCM_close(AESGCM_Handle handle); + +/*! + * @brief Function to prepare a segmented AESGCM encryption operation. + * + * This function sets up a segmented AESGCM encryption operation. + * + * @pre #AESGCM_open() or #AESGCM_construct() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() + * or #AESGCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESGCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes. + * This value can be 0 and later provided + * by #AESGCM_setLengths(). + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESGCM_addAAD() + * @post #AESGCM_addData() + */ +int_fast16_t AESGCM_setupEncrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength); + +/*! + * @brief Function to prepare a segmented AESGCM decryption operation. + * + * This function sets up a segmented AESGCM decryption operation. + * + * @pre #AESGCM_open() or #AESGCM_construct() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() + * or #AESGCM_construct() + * + * @param [in] key Pointer to a previously initialized CryptoKey. + * + * @param [in] totalAADLength Total size of the AAD in bytes. + * This value can be 0 and later provided + * by #AESGCM_setLengths(). + * + * @param [in] totalPlaintextLength Total size of the plaintext in bytes + * This value can be 0 and later provided + * by #AESGCM_setLengths(). + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESGCM_addAAD() + * @post #AESGCM_addData() + */ +int_fast16_t AESGCM_setupDecrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength); + +/*! + * @brief Function to set the lengths of the message and additional data. + * + * This function declares the lengths of the message and + * additional authenticated data (AAD). + * + * @note This function doesn't have to be called if the lengths above were + * specified in #AESGCM_setupEncrypt() or #AESGCM_setupDecrypt(). + * + * @pre #AESGCM_setupEncrypt() or #AESGCM_setupDecrypt() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() + * or #AESGCM_construct() + * + * @param [in] aadLength Size of the non-encrypted AAD in bytes + * + * @param [in] plaintextLength Size of the plaintext to encrypt or the + * ciphertext to decrypt in bytes + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESGCM_setIV() + * @post #AESGCM_generateIV() + */ +int_fast16_t AESGCM_setLengths(AESGCM_Handle handle, size_t aadLength, size_t plaintextLength); + +/*! + * @brief Function to set the initialization vector (IV) for an AES GCM segmented operation. + * + * @pre #AESGCM_setupEncrypt(), #AESGCM_setupDecrypt(), or #AESGCM_setLengths() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() + * or #AESGCM_construct() + * + * @param [in] iv Pointer to the buffer containing the IV + * + * @param [in] ivLength The length of the IV in bytes + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESGCM_addAAD() + * @post #AESGCM_addData() + */ +int_fast16_t AESGCM_setIV(AESGCM_Handle handle, const uint8_t *iv, size_t ivLength); + +/*! + * @brief Function to generate an IV for an AES GCM segmented encryption operation. + * + * @pre #AESGCM_setupEncrypt() or #AESGCM_setLengths() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() + * or #AESGCM_construct() + * + * @param [in] iv Pointer to the buffer where the generated IV + * is to be written to + * + * @param [in] ivSize The length of the IV buffer in bytes + * + * @param [out] ivLength The length of the IV actually written if the + * operation was successful + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not + * supported in this device. + * + * @post #AESGCM_addAAD() + * @post #AESGCM_addData() + */ +int_fast16_t AESGCM_generateIV(AESGCM_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength); + +/*! + * @brief Adds a segment of @a aad with a @a length in bytes to the generated MAC. + * + * #AESGCM_addAAD() may be called an arbitrary number of times before continuing the operation with + * #AESGCM_addData(), #AESGCM_finalizeEncrypt() or #AESGCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @note This function must not be called after passing data to encrypt or + * decrypt with #AESGCM_addData(). + * + * @warning When decrypting, do not use the output until + * #AESGCM_finalizeDecrypt() succeeds. + * + * @pre #AESGCM_setIV() or #AESGCM_generateIV() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operation Pointer to segmented AAD GCM operation structure + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESGCM_addAAD() + * @post #AESGCM_addData() + * @post #AESGCM_finalizeEncrypt() + * @post #AESGCM_finalizeDecrypt() + */ +int_fast16_t AESGCM_addAAD(AESGCM_Handle handle, AESGCM_SegmentedAADOperation *operation); + +/*! + * @brief Adds a segment of @a data with a @a length that is a multiple of an AES block-size (16 bytes) + * to the plaintext/ciphertext output and generated MAC. The @a length does not have to be a block-size + * multiple if passing in the last chunk of @a data. + * + * #AESGCM_addData() may be called an arbitrary number of times before finishing the operation + * with #AESGCM_finalizeEncrypt() or #AESGCM_finalizeDecrypt(). + * + * This function returns according to the return behavior set when opening the driver. + * + * @warning When decrypting, do not use the output until + * #AESGCM_finalizeDecrypt() succeeds. + * + * @pre #AESGCM_setIV() or #AESGCM_generateIV() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operation Pointer to segmented data GCM operation structure + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + * + * @post #AESGCM_addData() + * @post #AESGCM_finalizeEncrypt() + * @post #AESGCM_finalizeDecrypt() + */ +int_fast16_t AESGCM_addData(AESGCM_Handle handle, AESGCM_SegmentedDataOperation *operation); + +/*! + * @brief Finalize the MAC and ciphertext. + * + * This function finalizes the encryption of a dataset earlier provided + * by calls to #AESGCM_addAAD() and #AESGCM_addData() and creates a message + * authentication code. If additional data needs to be encrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * The resulting output is a message authentication code and ciphertext. + * + * @pre #AESGCM_addAAD() or #AESGCM_addData() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operation Pointer to segmented finalize GCM operation structure + * + * @retval #AESGCM_STATUS_SUCCESS In ::AESGCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESGCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was generated successfully. In ::AESGCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + */ +int_fast16_t AESGCM_finalizeEncrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Finalize the MAC and plaintext and verify it. + * + * This function finalizes the decryption of a dataset earlier provided + * by calls to AESGCM_addAAD() and AESGCM_addData() and verifies a provided message + * authentication code. If additional data needs to be decrypted and verified + * as part of this call, set the operation structure @a inputLength accordingly. + * + * The resulting output is a verification return code and plaintext. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield a corrupted MAC comparison. + * + * @pre #AESGCM_addAAD() or #AESGCM_addData() + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operation Pointer to segmented finalize GCM operation structure + * + * @retval #AESGCM_STATUS_SUCCESS In ::AESGCM_RETURN_BEHAVIOR_BLOCKING and + * ::AESGCM_RETURN_BEHAVIOR_POLLING, this means the MAC + * was verified successfully. In ::AESGCM_RETURN_BEHAVIOR_CALLBACK, + * this means the operation started successfully. + * @retval #AESGCM_STATUS_ERROR The operation failed. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #AESGCM_STATUS_MAC_INVALID The provided MAC did not match the recomputed one. + * @retval #AESGCM_STATUS_FEATURE_NOT_SUPPORTED The operation is not supported in this device. + */ +int_fast16_t AESGCM_finalizeDecrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation); + +/*! + * @brief Function to initialize an #AESGCM_Operation struct to its defaults + * + * @deprecated This function should be replaced by calls to operation-specific + * init functions. + * + * @param [in] operationStruct A pointer to an #AESGCM_Operation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESGCM_Operation_init(AESGCM_Operation *operationStruct); + +/*! + * @brief Function to initialize an #AESGCM_OneStepOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESGCM_OneStepOperation structure for + * initialization + * + * Defaults values are all zeros. + */ +void AESGCM_OneStepOperation_init(AESGCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESGCM_SegmentedAADOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESGCM_SegmentedAADOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESGCM_SegmentedAADOperation_init(AESGCM_SegmentedAADOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESGCM_SegmentedDataOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESGCM_SegmentedDataOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESGCM_SegmentedDataOperation_init(AESGCM_SegmentedDataOperation *operationStruct); + +/*! + * @brief Function to initialize an #AESGCM_SegmentedFinalizeOperation struct to its defaults + * + * @param [in] operationStruct A pointer to an #AESGCM_SegmentedFinalizeOperation structure + * for initialization + * + * Defaults values are all zeros. + */ +void AESGCM_SegmentedFinalizeOperation_init(AESGCM_SegmentedFinalizeOperation *operationStruct); + +/*! + * @brief Function to perform an AESGCM encryption + authentication operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted ciphertext or incorrect authentication. + * + * @pre #AESGCM_open() or #AESGCM_construct() and #AESGCM_Operation_init() have to be called first. + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed or the IV length is not supported. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESGCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESGCM_oneStepDecrypt() + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct); + +/*! + * @brief Function to perform an AESGCM decryption + verification operation in one call. + * + * @note None of the buffers provided as arguments may be altered by the application during an ongoing operation. + * Doing so can yield corrupted plaintext or incorrectly failed verification. + * + * @pre #AESGCM_open() or #AESGCM_construct() and #AESGCM_Operation_init() have to be called first. + * + * @param [in] handle A GCM handle returned from #AESGCM_open() or #AESGCM_construct() + * + * @param [in] operationStruct A pointer to a struct containing the parameters required to perform the + * operation. + * + * @retval #AESGCM_STATUS_SUCCESS The operation succeeded. + * @retval #AESGCM_STATUS_ERROR The operation failed or the IV length is not supported. + * @retval #AESGCM_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #AESGCM_STATUS_MAC_INVALID The provided MAC did no match the recomputed one. + * @retval #AESGCM_STATUS_UNALIGNED_IO_NOT_SUPPORTED The input and/or output buffer were not word-aligned. + * + * @sa AESGCM_oneStepEncrypt() + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct); + +/*! + * @brief Cancels an ongoing AESGCM operation. + * + * Asynchronously cancels an AESGCM operation. Only available when using + * AESGCM_RETURN_BEHAVIOR_CALLBACK. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be AESGCM_STATUS_CANCELED. + * + * @param [in] handle Handle of the operation to cancel + * + * @retval #AESGCM_STATUS_SUCCESS The operation was canceled, or the operation had already completed. + * @retval #AESGCM_STATUS_ERROR The driver was not in callback mode, or the operation's output + * and generated MAC weren't properly cleared. + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle); + +/** + * @brief Constructs a new AESGCM object + * + * Unlike #AESGCM_open(), #AESGCM_construct() does not require the hwAttrs and + * object to be allocated in a #AESGCM_Config array that is indexed into. + * Instead, the #AESGCM_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #AESGCM_Config describing the location of the object and hwAttrs. + * + * @param params #AESGCM_Params to configure the driver instance. + * + * @return Returns a #AESGCM_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +AESGCM_Handle AESGCM_construct(AESGCM_Config *config, const AESGCM_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_AESGCM__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.c b/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.c new file mode 100644 index 00000000..1512f1bc --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ANSIX936KDF.c ======== + * + * This file contains default values for the ANSIX936KDF_Params struct. + * + */ + +#include +#include + +#include +#include +#include + +const ANSIX936KDF_Params ANSIX936KDF_defaultParams = { + .returnBehavior = ANSIX936KDF_RETURN_BEHAVIOR_BLOCKING, + .timeout = (uint32_t)SemaphoreP_WAIT_FOREVER, +}; + +/* + * ======== ANSIX936KDF_Params_init ======== + */ +void ANSIX936KDF_Params_init(ANSIX936KDF_Params *params) +{ + *params = ANSIX936KDF_defaultParams; +} + +/* + * ======== ANSIX936KDF_open ======== + */ +__attribute__((weak)) ANSIX936KDF_Handle ANSIX936KDF_open(uint_least8_t index, const ANSIX936KDF_Params *params) +{ + DebugP_assert(index < ANSIX936KDF_count); + + ANSIX936KDF_Config *config = (ANSIX936KDF_Config *)&ANSIX936KDF_config[index]; + return ANSIX936KDF_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.h b/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.h new file mode 100644 index 00000000..1112e52d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ANSIX936KDF.h @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ANSIX936KDF.h + * + * @brief ANSIX936KDF driver header + * + * @anchor ti_drivers_ANSIX936KDF_Overview + * # Overview # + * + * The ANSI X9.63 Key Derivation Function (KDF) driver utilizes the SHA-256 hash + * function to derive a key from a shared secret value and optional shared + * info. See ANSI X9.63-2011 or SEC-1 v2.0 standard for more information. + * + * @anchor ti_drivers_ANSIX936KDF_Usage + * # Usage # + * + * Before starting a ANSIX936KDF operation, the application must do the following: + * - Call #ANSIX936KDF_init() to initialize the driver. + * - Call #ANSIX936KDF_Params_init() to initialize the ANSIX936KDF_Params to default values. + * - Modify the #ANSIX936KDF_Params as desired. + * - Call #ANSIX936KDF_open() to open an instance of the driver. + * + * @anchor ti_drivers_ANSIX936KDF_Synopsis + * # Synopsis + * + * @anchor ti_drivers_ANSIX936KDF_Synopsis_Code + * @code + * + * // Import ANSIX936KDF Driver definitions + * #include + * + * // Import driver configuration + * #include "ti_drivers_config.h" + * + * // Initialize driver + * ANSIX936KDF_init(); + * + * // Open driver instance + * handle = ANSIX936KDF_open(CONFIG_ANSIX936KDF_0, NULL); + * + * // Perform key derivation + * result = ANSIX936KDF_deriveKey(handle, input, sizeof(input), sharedInfo, + * sizeof(sharedInfo), output, sizeof(output)); + * + * // Close driver instance + * ANSIX936KDF_close(handle); + * @endcode + * + * @anchor ti_drivers_ANSIX936KDF_Example + * # Example # + * + * The #ANSIX936KDF_deriveKey() function performs a key derivation operation in + * a single call. + * + * After a ANSIX936KDF operation completes, the application may either start + * another operation or close the driver by calling #ANSIX936KDF_close(). + * + * @code + * ANSIX936KDF_Params params; + * ANSIX936KDF_Handle handle; + * int_fast16_t result; + * uint8_t sharedInfo[] = {0x75, 0xee, 0xf8, 0x1a, 0xa3, 0x04, 0x1e, 0x33, + * 0xb8, 0x09, 0x71, 0x20, 0x3d, 0x2c, 0x0c, 0x52}; + * uint8_t input[] = {0x22, 0x51, 0x8b, 0x10, 0xe7, 0x0f, 0x2a, 0x3f, 0x24, 0x38, 0x10, 0xae, + * 0x32, 0x54, 0x13, 0x9e, 0xfb, 0xee, 0x04, 0xaa, 0x57, 0xc7, 0xaf, 0x7d}; + * uint8_t output[32] = {0}; + * + * ANSIX936KDF_init(); + * + * ANSIX936KDF_Params_init(¶ms); + * params.returnBehavior = ANSIX936KDF_RETURN_BEHAVIOR_POLLING; + * + * handle = ANSIX936KDF_open(CONFIG_ANSIX936KDF_0, ¶ms); + * assert(handle != NULL); + * + * result = ANSIX936KDF_deriveKey(handle, input, sizeof(input), sharedInfo, + * sizeof(sharedInfo), output, sizeof(output)); + * assert(result == ANSIX936KDF_STATUS_SUCCESS); + * + * ANSIX936KDF_close(handle); + * @endcode + */ + +#ifndef ti_drivers_ANSIX936KDF__include +#define ti_drivers_ANSIX936KDF__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common ANSIX936KDF status code reservation offset. + * ANSIX936KDF driver implementations should offset status codes with + * ANSIX936KDF_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ANSIX936KDFXYZ_STATUS_ERROR0 ANSIX936KDF_STATUS_RESERVED - 0 + * #define ANSIX936KDFXYZ_STATUS_ERROR1 ANSIX936KDF_STATUS_RESERVED - 1 + * #define ANSIX936KDFXYZ_STATUS_ERROR2 ANSIX936KDF_STATUS_RESERVED - 2 + * @endcode + */ +#define ANSIX936KDF_STATUS_RESERVED ((int_fast16_t)-32) + +/*! + * @brief Successful status code. + * + * Functions return ANSIX936KDF_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ANSIX936KDF_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return ANSIX936KDF_STATUS_ERROR if the function was not executed + * successfully and no more specific error is applicable. + */ +#define ANSIX936KDF_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource is + * currently unavailable. + * + * ANSIX936KDF driver implementations may have hardware or software limitations + * on how many clients can simultaneously perform operations. This status code + * is returned if the mutual exclusion mechanism signals that an operation + * cannot currently be performed. + */ +#define ANSIX936KDF_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief The way in which ANSIX936KDF function calls return after performing + * an operation. + * + * Not all ANSIX936KDF operations exhibit the specified return behavior. + * Functions that do not require significant computation and cannot offload that + * computation to a background thread behave like regular functions. Which + * functions exhibit the specified return behavior is not implementation + * dependent. Specifically, a software-backed implementation run on the same CPU + * as the application will emulate the return behavior while not actually + * offloading the computation to the background thread. + * + * ANSIX936KDF functions exhibiting the specified return behavior have + * restrictions on the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |---------------------------------------|-------|-------|-------| + * |ANSIX936KDF_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ANSIX936KDF_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + /*! The function call will block while the ANSIX936KDF operation goes + * on in the background. ANSIX936KDF operation results are available + * after the function returns. + */ + ANSIX936KDF_RETURN_BEHAVIOR_BLOCKING = SHA2_RETURN_BEHAVIOR_BLOCKING, + + /*! The function call will continuously poll a flag while the ANSIX936KDF + * operation goes on in the background. ANSIX936KDF operation results + * are available after the function returns. + */ + ANSIX936KDF_RETURN_BEHAVIOR_POLLING = SHA2_RETURN_BEHAVIOR_POLLING, +} ANSIX936KDF_ReturnBehavior; + +/*! + * @brief ANSIX936KDF Global configuration + * + * The %ANSIX936KDF_Config structure contains a set of pointers used to characterize + * the ANSIX936KDF driver implementation. + * + * This structure needs to be defined before calling #ANSIX936KDF_init() and it must + * not be changed thereafter. + * + * @sa ANSIX936KDF_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ANSIX936KDF_Config; + +/*! + * @brief A handle that is returned from an ANSIX936KDF_open() call. + */ +typedef ANSIX936KDF_Config *ANSIX936KDF_Handle; + +/*! + * @brief ANSIX936KDF Parameters + * + * ANSIX936KDF Parameters are used to with the ANSIX936KDF_open() call. Default values for + * these parameters are set using ANSIX936KDF_Params_init(). + * + * @sa ANSIX936KDF_Params_init() + */ +typedef struct +{ + ANSIX936KDF_ReturnBehavior returnBehavior; /*!< Blocking or polling return behavior */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::ANSIX936KDF_RETURN_BEHAVIOR_BLOCKING + */ +} ANSIX936KDF_Params; + +/*! + * @brief Global ANSIX936KDF configuration struct. + * + * Specifies context objects and hardware attributes for every + * driver instance. + * + * This variable is supposed to be defined in the board file. + */ +extern const ANSIX936KDF_Config ANSIX936KDF_config[]; + +/*! + * @brief Global ANSIX936KDF configuration count. + * + * Specifies the number of available ANSIX936KDF driver instances. + * + * This variable is supposed to be defined in the board file. + */ +extern const uint_least8_t ANSIX936KDF_count; + +/*! + * @brief Default ANSIX936KDF_Params structure + * + * @sa #ANSIX936KDF_Params_init() + */ +extern const ANSIX936KDF_Params ANSIX936KDF_defaultParams; + +/*! + * @brief Initializes the ANSIX936KDF driver module. + * + * @pre The #ANSIX936KDF_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ANSIX936KDF driver APIs. This function call does not modify any + * peripheral registers. + */ +void ANSIX936KDF_init(void); + +/*! + * @brief Initializes @c params with default values. + * + * @param params A pointer to #ANSIX936KDF_Params structure for + * initialization + * + * Default values:
+ * returnBehavior = ANSIX936KDF_RETURN_BEHAVIOR_BLOCKING
+ * timeout = SemaphoreP_WAIT_FOREVER
+ */ +void ANSIX936KDF_Params_init(ANSIX936KDF_Params *params); + +/*! + * @brief Initializes a ANSIX936KDF driver instance and returns a handle. + * + * @pre ANSIX936KDF controller has been initialized using #ANSIX936KDF_init() + * + * @param index Logical peripheral number for the ANSIX936KDF indexed into + * the #ANSIX936KDF_config table + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #ANSIX936KDF_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #ANSIX936KDF_init() + * @sa #ANSIX936KDF_close() + */ +ANSIX936KDF_Handle ANSIX936KDF_open(uint_least8_t index, const ANSIX936KDF_Params *params); + +/*! + * @brief Closes a ANSIX936KDF peripheral specified by @c handle. + * + * @pre #ANSIX936KDF_open() has to be called first. + * + * @param handle A #ANSIX936KDF_Handle returned from ANSIX936KDF_open() + * + * @sa #ANSIX936KDF_open() + */ +void ANSIX936KDF_close(ANSIX936KDF_Handle handle); + +/*! + * @brief Derives a key with the SHA-256 hash function. + * + * Uses the SHA-256 hash function to derives a key from a shared secret value + * and optional shared information. + * + * @pre #ANSIX936KDF_open() has to be called first. + * + * @param handle A #ANSIX936KDF_Handle returned from #ANSIX936KDF_open() + * + * @param input A pointer to the input (i.e. shared secret value) + * + * @param inputLen The length of @c input in bytes. + * + * @param sharedInfo A pointer to the shared info. May be NULL if there is no + * shared info. + * + * @param sharedInfoLen The length of the @c sharedInfo in bytes. + * Set to zero if @c sharedInfo is NULL. + * + * @param output A pointer to the location to write the output (i.e. derived key). + * + * @param outputLen Output length in bytes. + * + * @retval #ANSIX936KDF_STATUS_SUCCESS The operation succeeded. + * @retval #ANSIX936KDF_STATUS_ERROR The operation failed. + * @retval #ANSIX936KDF_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * + * @sa #ANSIX936KDF_open() + */ +int_fast16_t ANSIX936KDF_deriveKey(ANSIX936KDF_Handle handle, + const void *input, + size_t inputLen, + const void *sharedInfo, + size_t sharedInfoLen, + void *output, + size_t outputLen); + +/*! + * @brief Constructs a new ANSIX936KDF object + * + * Unlike #ANSIX936KDF_open(), #ANSIX936KDF_construct() does not require the hwAttrs and + * object to be allocated in a #ANSIX936KDF_Config array that is indexed into. + * Instead, the #ANSIX936KDF_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #ANSIX936KDF_Config describing the location of the object and hwAttrs. + * + * @param params #ANSIX936KDF_Params to configure the driver instance. + * + * @return Returns a #ANSIX936KDF_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +ANSIX936KDF_Handle ANSIX936KDF_construct(ANSIX936KDF_Config *config, const ANSIX936KDF_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ANSIX936KDF__include */ diff --git a/simplelink_lpf2/source/ti/drivers/Board.h b/simplelink_lpf2/source/ti/drivers/Board.h new file mode 100644 index 00000000..de868865 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Board.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!**************************************************************************** + * @file Board.h + * @brief Portable board-specific symbols + * + * The Board header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * This header serves as device-independent interface for applications using + * peripherals connected to the device via standard digital interfaces; e.g, + * GPIO, SPI, I2C, UART, etc. Its purpose is to enable application code that + * references a peripheral to be portable to any device and board that + * supports the peripheral. + * + * ## Usage ## + * + * @anchor ti_drivers_Board_Synopsis + * ### Synopsis # + * @anchor ti_drivers_Board_Synopsis_Code + * @code + * #include + * + * void main(void) + * { + * Board_init(); + * : + * } + * @endcode + * + * ## Initializing the hardware ## + * + * \p Board_init() must be called before any other driver API. This function + * is owned by the user (typically generated by SysConfig), and is + * responsible for device specific initialization; e.g., initializing clocks + * and power management functionality. + ****************************************************************************** + */ + +#ifndef ti_drivers_Board__include +#define ti_drivers_Board__include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Performs "early" board-level initialization required by TI-DRIVERS + * + * Board_init() must be called before any other TI-DRIVER API. This function + * calls all device and board specific initialization functions needed by + * TI-DRIVERS; e.g., to initialize clocks and power management functionality. + * + * This function should only be called once and as early in the application's + * startup as possible. In most applications, a call to Board_init() is the + * first statement in \p main(). + * + * @pre \p Board_init must be called after every CPU reset and _prior_ to + * enabling any interrupts. + */ +extern void Board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Board_include */ diff --git a/simplelink_lpf2/source/ti/drivers/CAN.c b/simplelink_lpf2/source/ti/drivers/CAN.c new file mode 100644 index 00000000..db2a9f7d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/CAN.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CAN.c ======== + */ +#include +#include + +#include +#include + +#include + +/* Externally defined device-specific functions */ +extern int_fast16_t CAN_initDevice(uint_least8_t index, CAN_Params *params); +extern int_fast16_t CAN_deinitDevice(void); + +/* Default CAN parameters structure */ +static const CAN_Params CAN_defaultParams = { + .msgRamConfig = NULL, + .bitTiming = NULL, + .tsPrescaler = 24U, + .eventCbk = NULL, + .eventMask = 0U, + .userArg = NULL, +}; + +/* + * ======== CAN_Params_init ======== + */ +void CAN_Params_init(CAN_Params *params) +{ + *params = CAN_defaultParams; +} + +/* + * ======== CAN_init ======== + */ +__attribute__((weak)) void CAN_init(void) +{ + /* Do nothing */ +} + +/* + * ======== CAN_open ======== + */ +CAN_Handle CAN_open(uint_least8_t index, CAN_Params *params) +{ + const CAN_Config *config = &CAN_config[index]; + CAN_Handle handle = NULL; + const CAN_HWAttrs *hwAttrs = config->hwAttrs; + CAN_Object *object = config->object; + uintptr_t interruptKey = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(interruptKey); + + return NULL; + } + + object->isOpen = true; + + HwiP_restore(interruptKey); + + object->eventCbk = params->eventCbk; + if (params->eventCbk == NULL) + { + /* Set the event mask to 0 if the callback is NULL to simplify checks */ + object->eventMask = 0U; + } + else + { + object->eventMask = params->eventMask; + object->userArg = params->userArg; + } + + StructRingBuf_construct(&object->rxStructRingBuf, + hwAttrs->rxRingBufPtr, + hwAttrs->rxRingBufSize, + sizeof(MCAN_RxBufElement)); + StructRingBuf_construct(&object->txStructRingBuf, + hwAttrs->txRingBufPtr, + hwAttrs->txRingBufSize, + sizeof(MCAN_TxBufElement)); + + if (CAN_initDevice(index, params) == CAN_STATUS_SUCCESS) + { + handle = (CAN_Handle)config; + } + else + { + object->isOpen = false; + } + + return handle; +} + +/* + * ======== CAN_close ======== + */ +__attribute__((weak)) void CAN_close(CAN_Handle handle) +{ + CAN_Object *object = handle->object; + + object->isOpen = false; +} + +/* + * ======== CAN_read ======== + */ +int_fast16_t CAN_read(CAN_Handle handle, MCAN_RxBufElement *buf) +{ + CAN_Object *object = handle->object; + int_fast16_t status = CAN_STATUS_NO_RX_MSG_AVAIL; + + if (StructRingBuf_get(&object->rxStructRingBuf, buf) >= 0) + { + status = CAN_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== CAN_write ======== + */ +int_fast16_t CAN_write(CAN_Handle handle, const MCAN_TxBufElement *elem) +{ + CAN_Object *object = handle->object; + int_fast16_t status = CAN_STATUS_ERROR; + MCAN_TxFifoQStatus fifoQStatus = {0}; + uintptr_t hwiKey; + + if (object->txFifoQNum != 0U) + { + /* Disable interrupts as the ISR may call CAN_write */ + hwiKey = HwiP_disable(); + + MCAN_getTxFifoQStatus(&fifoQStatus); + + if (fifoQStatus.fifoFull == 0U) + { + MCAN_writeTxMsg(fifoQStatus.putIdx, elem); + + MCAN_setTxBufAddReq(fifoQStatus.putIdx); + status = CAN_STATUS_SUCCESS; + } + else + { + if (StructRingBuf_put(&object->txStructRingBuf, elem) < 0) + { + status = CAN_STATUS_TX_BUF_FULL; + } + else + { + status = CAN_STATUS_SUCCESS; + } + } + + HwiP_restore(hwiKey); + } + + return status; +} + +/* + * ======== CAN_writeBuffer ======== + */ +int_fast16_t CAN_writeBuffer(CAN_Handle handle, uint32_t bufIdx, const MCAN_TxBufElement *elem) +{ + CAN_Object *object = handle->object; + int_fast16_t status = CAN_STATUS_ERROR; + uint32_t pendingTx; + + if (bufIdx < object->txBufNum) + { + pendingTx = MCAN_getTxBufReqPend(); + + if ((((uint32_t)1U << bufIdx) & pendingTx) == 0U) + { + MCAN_writeTxMsg(bufIdx, elem); + + MCAN_setTxBufAddReq(bufIdx); + + status = CAN_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== CAN_readTxEvent ======== + */ +int_fast16_t CAN_readTxEvent(CAN_Handle handle, CAN_TxEventElement *elem) +{ + CAN_Object *object = handle->object; + int_fast16_t status = CAN_STATUS_ERROR; + + if (object->txEventFifoNum != 0U) + { + if (MCAN_readTxEventFifo(elem) == MCAN_STATUS_SUCCESS) + { + status = CAN_STATUS_SUCCESS; + } + else + { + status = CAN_STATUS_NO_TX_EVENT_AVAIL; + } + } + + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/CAN.h b/simplelink_lpf2/source/ti/drivers/CAN.h new file mode 100644 index 00000000..4794ba9a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/CAN.h @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file CAN.h + * + * @brief Controller Area Network (CAN) Driver Interface + * + * @anchor ti_drivers_CAN_Overview + * # Overview + * The Controller Area Network (CAN) driver is a single instance driver + * that provides a simple interface to transmit and receive messages on a CAN bus. + * Messages are broadcast to the entire CAN network and each device is responsible + * for filtering and handling the received messages as necessary. + * The application is responsible for interpreting the received data. + * + * # Power Management + * For devices with an integrated CAN controller, the CAN driver sets a power + * constraint when the driver is opened to prevent the device from entering + * standby when all tasks are blocked. This is required to allow the CAN + * controller and its clock source to remain powered to receive CAN messages + * from the external CAN transceiver. When the driver is closed, the power + * constraint is released. The application should close the CAN driver whenever + * the CAN transceiver enters sleep mode and re-open the CAN driver when the CAN + * transceiver wakes from sleep mode. + * + *
+ * @anchor ti_drivers_CAN_Usage + * # Usage + * + * To use the CAN driver to send and receive messages over the CAN bus, the + * application calls the following APIs: + * - CAN_open(): Open the CAN driver instance and configure the CAN + * controller, placing it in normal operational mode. + * - CAN_write(): Transmit a message using the Tx FIFO/Queue. This is the + * typical method of transmission. + * - CAN_writeBuffer(): Transmit a message using a dedicated Tx Buffer. This + * method of transmission requires a custom message RAM configuration and + * should only be used if there is an application-specific need that cannot + * be met by using the Tx FIFO/Queue. + * - CAN_read(): Receive a message. This should be called in a task context + * and triggered by the event callback when CAN_EVENT_RX_DATA_AVAIL occurs. + * - CAN_close(): Close the CAN driver instance and reset the CAN controller, + * placing it in standby operational mode. + * + * @anchor ti_drivers_CAN_Synopsis + * ## Synopsis + * The following code example initializes the CAN driver with the default + * configuration, transmits a CAN FD message, and waits to read any received + * messages. + * + * @code + * // Payload data size indexed by Data Length Code (DLC) field. + * static const uint32_t dlcToDataSize[16] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + * + * // Rx semaphore. + * static SemaphoreP_Handle rxSemHandle; + * + * void eventCallback(CAN_Handle handle, uint32_t event, uint32_t data, void *userArg) + * { + * if (event == CAN_EVENT_RX_DATA_AVAIL) + * { + * SemaphoreP_post(rxSemHandle); + * } + * // Handle more events here if enabled via the event mask... + * } + * + * void thread(arg0, arg1) + * { + * int_fast16_t status; + * CAN_RxBufElement rxElem; + * CAN_TxBufElement txElem; + * + * // Initialize driver(s). + * CAN_init(); + * + * // Create callback semaphore. + * SemaphoreP_Params semParams; + * SemaphoreP_Params_init(&semParams); + * semParams.mode = SemaphoreP_Mode_BINARY; + * callbackSemHandle = SemaphoreP_create(0, &(semParams)); + * + * if (callbackSemHandle == NULL) + * { + * // SemaphoreP_create() failed. + * while (1) {} + * } + * + * // Open CAN driver with default configuration. + * CAN_Params_init(&canParams); + * canParams.eventCbk = eventCallback; + * // Setup event mask for events the application is interested in receiving + * // the callback for. Typically, only the CAN_EVENT_RX_DATA_AVAIL is required. + * canParams.eventMask = CAN_EVENT_RX_DATA_AVAIL; + * + * canHandle = CAN_open(CONFIG_CAN_0, &canParams); + * if (canHandle == NULL) + * { + * // CAN_open() failed. + * while (1) {} + * } + * + * // Setup Tx buffer element: + * // CAN FD without Bit Rate Switching + * // Extended Message ID = 0x12345678 + * // Data Length of 64-bytes + * // Message marker = 5 + * txElem.id = 0x12345678U; + * txElem.rtr = 0U; + * txElem.xtd = 1U; + * txElem.esi = 0U; + * txElem.brs = 1U; + * txElem.dlc = CAN_DLC_64B; + * txElem.fdf = 1U; + * txElem.efc = 0U; + * txElem.mm = 5U; + * + * // Fill data payload with incrementing values. + * for (i = 0; i < dlcToDataSize[txElem.dlc]; i++) + * { + * txElem.data[i] = i; + * } + * + * // Transmit message. + * CAN_write(canHandle, &txElem); + * + * while (1) + * { + * // Wait for Rx data available event. + * SemaphoreP_pend(rxSemHandle, (uint32_t)SemaphoreP_WAIT_FOREVER); + * + * // Read all available messages. + * while (CAN_read(canHandle, &rxElem) == CAN_STATUS_SUCCESS) + * { + * // Process received message. + * } + * } + * } + * + * @endcode + * + * More details on usage are provided in the following subsections. + * + * @anchor ti_drivers_CAN_Examples + * ## Examples # + * * @ref ti_drivers_CAN_Synopsis "Usage Synopsis" + * * @ref ti_drivers_CAN_Example_initMsgRam "Initialize with custom message RAM configuration" + * * @ref ti_drivers_CAN_Example_initRawBitRate "Initialize with raw bit rate timing" + * + * ## Initializing the CAN Driver + * + * CAN_init() must be called before any other CAN APIs. This function + * initializes common driver resources and calls the device-specific + * initialization function to configure the bit rate and message RAM. + * + * ## Opening the CAN Driver + * After initializing the CAN driver by calling CAN_init(), the application + * can open a CAN instance by calling CAN_open(). This function + * takes an index into the @p CAN_config[] array, and a CAN parameters data + * structure. The CAN instance is specified by the index of the CAN in + * @p CAN_config[]. Calling CAN_open() a second time with the same index + * previously passed to CAN_open() will result in an error. You can, + * though, re-use the index if the instance is closed via CAN_close(). + * + * If no #CAN_Params structure is passed to CAN_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * The CAN driver APIs are non-blocking; there is no configurable return behavior. + * + * @anchor ti_drivers_CAN_Example_initMsgRam + * Example initializing the CAN driver with a custom message RAM configuration + * to receive only filtered message IDs: + * + * @note CAN driver SysConfig must be setup with 'Reject Non-Matching Messages' enabled. + * + * @code + * #define STD_MSG_FILTER_NUM 2U + * #define EXT_MSG_FILTER_NUM 1U + * + * static MCAN_StdMsgIDFilterElement stdMsgIDFilter[STD_MSG_FILTER_NUM] = + * {{.sfid1 = 0x555, .sfid2 = 0x444, .sfec = CAN_FEC_STORE_RXFIFO0, .sft = CAN_FILTER_DUAL_ID}, + * {.sfid1 = 0x123, .sfid2 = 0U, .sfec = CAN_FEC_STORE_RXBUF, .sft = 0U}}; + * + * static MCAN_ExtMsgIDFilterElement extMsgIDFilter[EXT_MSG_FILTER_NUM] = + * {{.efid1 = 0x1234578, .efid2 = 0x1234600, .efec = CAN_FEC_STORE_RXFIFO1, .eft = CAN_FILTER_RANGE}}; + * + * const CAN_MsgRamConfig msgRamConfig = { + * .stdFilterNum = STD_MSG_FILTER_NUM, + * .extFilterNum = EXT_MSG_FILTER_NUM, + * .stdMsgIDFilterList = &stdMsgIDFilter[0], + * .extMsgIDFilterList = &extMsgIDFilter[0], + * + * .rxFifoNum[0] = 10U, + * .rxFifoNum[1] = 2U, + * .rxBufNum = 1U, + * .txBufNum = 1U, + * .txFifoQNum = 5U, + * .txFifoQMode = 1U, + * }; + * + * int_fast16_t status; + * + * // Initialize driver(s). + * CAN_init(); + * + * // Open CAN driver with custom message filters. + * CAN_Params_init(&canParams); + * canParams.msgRamConfig = &msgRamConfig; + * canParams.eventCbk = eventCallback; + * // Setup event mask for events the application is interested in receiving + * // the callback for. Typically, only the CAN_EVENT_RX_DATA_AVAIL is required. + * canParams.eventMask = CAN_EVENT_RX_DATA_AVAIL; + * + * canHandle = CAN_open(CONFIG_CAN_0, &canParams); + * if (canHandle == NULL) + * { + * // CAN_open() failed. + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_CAN_Example_initRawBitRate + * Example initializing the CAN driver with a specific raw bit rate timing: + * @note For this example, CAN driver SysConfig should be setup with 'CAN FD + * Operation' and 'Bit Rate Switching' enabled. The nominal and data bit rates + * selected in SysConfig will be ignored since raw bit rate timing parameters + * are provided to CAN_open(). + * + * @code + * const CAN_DataBitRateTimingRaw rawDataBitRateTiming = { + * // 1Mbps with 40MHz clk and 80% sample point ((40E6 / 2) / (15 + 4 + 1) = 1E6) + * // Add 1 to each programmed bit time to get functional value and +1 for for prop segment + * .dbrp = 1U, + * .dtSeg1 = 14U, + * .dtSeg2 = 3U, + * .dsjw = 3U, + * .tdcOffset = 14U, + * .tdcFilterWinLen = 0U + * }; + * + * const CAN_BitRateTimingRaw rawBitTiming = { + * // 500kbps nominal with 40MHz clk and 87.5% sample point ((40E6 / 1) / (69 + 10 + 1) = 500E3) + * // Add 1 to each programmed bit time to get functional value and +1 for for prop segment + * .nbrp = 0U, + * .ntSeg1 = 68U, + * .ntSeg2 = 9U, + * .nsjw = 9U, + * .dataTiming = &rawDataBitRateTiming + * }; + * + * int_fast16_t status; + * + * // Initialize driver(s). + * CAN_init(); + * + * // Open CAN with specific raw bit timing. + * CAN_Params_init(&canParams); + * canParams.bitTiming = &rawBitTiming; + * canParams.eventCbk = eventCallback; + * // Setup event mask for events the application is interested in receiving + * // the callback for. Typically, only the CAN_EVENT_RX_DATA_AVAIL is required. + * canParams.eventMask = CAN_EVENT_RX_DATA_AVAIL; + * + * canHandle = CAN_open(CONFIG_CAN_0, &canParams); + * if (canHandle == NULL) + * { + * // CAN_open() failed. + * while (1) {} + * } + * @endcode + * + * ## CAN Message RAM Configuration + * + * The default message RAM configuration is as follows: + * - No Rx filters. + * - Tx Queue (message with lowest ID in the queue will be transmitted first) + * with a fixed device-specific number of Tx buffers. + * - No Tx event FIFO. + * - Fixed device-specific number of Rx FIFO0 buffers. + * - No Rx FIFO1 buffers. + * - No dedicated Rx buffers. + * + * The number of default Tx and Rx buffers varies depending on the size of the + * device's message RAM. Check the doxygen for the device-specific CAN + * implementation to find the message RAM size. If using a custom message RAM + * configuration, utilize the entire space by maximizing the number of Rx/Tx + * buffers for optimal performance. + * + * ## CAN Write Behavior + * CAN_write() will return immediately after the message is loaded into the CAN + * controller's message RAM and pending transfer; it does not wait for the CAN + * message to be transmitted on the bus before returning. The CAN controller will + * automatically handle transmission retries in the event of a failure. + * + * ## CAN Read Behavior + * When a message is received in Rx FIFO0/1 or a dedicated Rx buffer, the CAN + * driver's IRQ handler automatically reads the Rx buffer element from the CAN + * controller's message RAM and stores it in a ring buffer whose size is + * configurable in SysConfig. When CAN_read() is called, the Rx buffer element + * is copied from the ring buffer to the application. If the ring buffer becomes + * full, any new messages received will be lost until the application frees + * space in the ring buffer by calling CAN_read(). + ******************************************************************************* + */ +#ifndef ti_drivers_can__include +#define ti_drivers_can__include + +#include +#include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @addtogroup CAN_STATUS CAN status codes + * @{ + */ + +/*! + * @brief Successful status code. + * + * Functions return CAN_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define CAN_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return CAN_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define CAN_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief Not supported status code. + * + * Functions return CAN_STATUS_NOT_SUPPORTED if the function is not supported + * either by the target hardware or the driver implementation. + */ +#define CAN_STATUS_NOT_SUPPORTED ((int_fast16_t)-2) + +/*! + * @brief Tx buffer full status code. + * + * Functions return CAN_STATUS_TXBUF_FULL if the Tx buffers are full. + */ +#define CAN_STATUS_TX_BUF_FULL ((int_fast16_t)-3) + +/*! + * @brief No received message available status code. + * + * Functions return CAN_STATUS_NO_RX_MSG_AVAIL if there are no messages + * available in the Rx message ring buffer. + */ +#define CAN_STATUS_NO_RX_MSG_AVAIL ((int_fast16_t)-4) + +/*! + * @brief No Tx event available status code. + * + * Functions return CAN_STATUS_NO_TX_EVENT_AVAIL if there are no Tx events + * available in the Tx Event FIFO. + */ +#define CAN_STATUS_NO_TX_EVENT_AVAIL ((int_fast16_t)-5) + +/*! @}*/ + +/*! @addtogroup CAN_EVENT CAN events + * @{ + */ + +/*! + * @brief A SPI transfer error occurred. + * + * @note This error is only relevant for SPI-backed external CAN controllers. + * + * If a SPI transfer error occurs, the CAN driver behavior is undefined and + * message transmit and receive may be unreliable. This error is an indication + * that further debug of the system HW & SW is required. + */ +#define CAN_EVENT_SPI_XFER_ERROR (0x800U) + +/*! + * @brief An uncorrected bit error occurred. + * + * If an uncorrected bit error occurs, the driver should be closed and + * re-opened to attempt recovery. + */ +#define CAN_EVENT_BIT_ERR_UNCORRECTED (0x400U) + +/*! + * @brief The driver's Rx ring buffer was full. + * + * The driver's Rx ring buffer was full resulting in a message being discarded. + * The application must call #CAN_read() in a more timely manner in response + * to CAN_EVENT_RX_DATA_AVAIL or the size of the Rx ring buffer should be + * increased. + */ +#define CAN_EVENT_RX_RING_BUFFER_FULL (0x200U) + +/*! + * @brief A message was lost for hardware Rx FIFO. + * + * See event data for FIFO number. + */ +#define CAN_EVENT_RX_FIFO_MSG_LOST (0x100U) + +/*! + * @brief State change to error passive. + */ +#define CAN_EVENT_ERR_PASSIVE (0x80U) + +/*! + * @brief State change to error active. + */ +#define CAN_EVENT_ERR_ACTIVE (0x40U) + +/*! + * @brief State change to bus off. + */ +#define CAN_EVENT_BUS_OFF (0x20U) + +/*! + * @brief State change to bus on. + */ +#define CAN_EVENT_BUS_ON (0x10U) + +/*! + * @brief A CAN message transmission event was lost. + * + * This event is used as an indication that the Tx Event was lost due to the + * Tx Event FIFO being full. + */ +#define CAN_EVENT_TX_EVENT_LOST (0x08U) + +/*! + * @brief A CAN message transmission event is available. + * + * This event is used as an indication that a new entry to the Tx Event FIFO + * occurred due to the transmission of a message with Event FIFO Control (EFC) + * bit set. + */ +#define CAN_EVENT_TX_EVENT_AVAIL (0x04U) + +/*! + * @brief A CAN message transmission was completed. + */ +#define CAN_EVENT_TX_FINISHED (0x02U) + +/*! + * @brief Received CAN message data is available. + * + * This event is used as an indication that #CAN_read() can be called to read + * the received message(s). + */ +#define CAN_EVENT_RX_DATA_AVAIL (0x01U) + +/*! @}*/ + +/** + * @defgroup CAN_DLC CAN Data Length Codes + * Data Length Code for use with CAN_RxBufElement & CAN_TxBufElement + * @{ + */ +#define CAN_DLC_0B ((uint32_t)0U) +#define CAN_DLC_1B ((uint32_t)1U) +#define CAN_DLC_2B ((uint32_t)2U) +#define CAN_DLC_3B ((uint32_t)3U) +#define CAN_DLC_4B ((uint32_t)4U) +#define CAN_DLC_5B ((uint32_t)5U) +#define CAN_DLC_6B ((uint32_t)6U) +#define CAN_DLC_7B ((uint32_t)7U) +#define CAN_DLC_8B ((uint32_t)8U) +#define CAN_DLC_12B ((uint32_t)9U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_16B ((uint32_t)10U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_20B ((uint32_t)11U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_24B ((uint32_t)12U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_32B ((uint32_t)13U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_48B ((uint32_t)14U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +#define CAN_DLC_64B ((uint32_t)15U) /*!< Equivalent to CAN_DLC_8B for classic CAN */ +/** @}*/ + +/** + * @defgroup CAN_FEC CAN Filter Element Configurations + * Filter Element Configuration for use with CAN_MsgRamConfig + *
0 = Disable filter element + *
1 = Store in Rx FIFO 0 if filter matches + *
2 = Store in Rx FIFO 1 if filter matches + *
3 = Reject ID if filter matches + *
4 = Set priority if filter matches + *
5 = Set priority and store in FIFO 0 if filter matches + *
6 = Set priority and store in FIFO 1 if filter matches + *
7 = Store into Rx Buffer or as debug message, + * configuration of filter type is ignored. + *
If FEC = 4-6, a match sets high priority message status and generates + * an interrupt. + * @{ + */ +#define CAN_FEC_DISABLE_FILTER ((uint32_t)0U) +#define CAN_FEC_STORE_RXFIFO0 ((uint32_t)1U) +#define CAN_FEC_STORE_RXFIFO1 ((uint32_t)2U) +#define CAN_FEC_REJECT_ID ((uint32_t)3U) +#define CAN_FEC_SET_PRIO ((uint32_t)4U) +#define CAN_FEC_SET_PRIO_STORE_RXFIFO0 ((uint32_t)5U) +#define CAN_FEC_SET_PRIO_STORE_RXFIFO1 ((uint32_t)6U) +#define CAN_FEC_STORE_RXBUF ((uint32_t)7U) +/** @}*/ + +/** + * @defgroup CAN_FILTER_TYPE CAN Filter Types + * Filter Type for use with CAN_MsgRamConfig + *
0 = Range filter from SFID1 to SFID2 (SFID2 >= SFID1) + *
1 = Dual ID filter for SFID1 or SFID2 + *
2 = Classic filter: SFID1 = filter, SFID2 = mask + *
3 = Filter element disabled + * @{ + */ +#define CAN_FILTER_RANGE ((uint32_t)0U) +#define CAN_FILTER_DUAL_ID ((uint32_t)1U) +#define CAN_FILTER_WITH_MASK ((uint32_t)2U) +#define CAN_FILTER_DISABLE ((uint32_t)3U) +/** @}*/ + +/*! + * @brief A CAN Rx buffer element struct for #CAN_read(). + */ +typedef MCAN_RxBufElement CAN_RxBufElement; + +/*! + * @brief A CAN Tx buffer element struct for #CAN_write() and #CAN_writeBuffer(). + */ +typedef MCAN_TxBufElement CAN_TxBufElement; + +/*! + * @brief A CAN Tx Event element struct for #CAN_readTxEvent(). + */ +typedef MCAN_TxEventFifoElement CAN_TxEventElement; + +/*! + * @brief A CAN bit timing struct for #CAN_getBitTiming(). + */ +typedef MCAN_BitTimingParams CAN_BitTimingParams; + +/*! + * @brief A handle that is returned from a #CAN_open() call. + */ +typedef struct CAN_Config_ *CAN_Handle; + +/*! + * @brief The definition of a callback function used by the CAN driver. + * + * @note The callback can occur in task or interrupt context. + * + * @param[in] handle A #CAN_Handle returned from #CAN_open(). + * @param[in] event @ref CAN_EVENT that has occurred. + * @param[in] data Data is event dependent: + * - #CAN_EVENT_RX_DATA_AVAIL: number of Rx buffers + * available to read. + * - #CAN_EVENT_RX_FIFO_MSG_LOST: FIFO number. + * - #CAN_EVENT_RX_RING_BUFFER_FULL: number of times + * the Rx ring buffer became full resulting in message + * loss. + * - CAN_EVENT_TX_FINISHED: mask of buffers for which + * transmission has occurred. Bits remain set until + * a new transmission is requested for the corresponding + * Tx buffer. + * - CAN_EVENT_TX_EVENT_AVAIL: the number of Tx Event + * elements currently available in the Tx Event FIFO. + * - CAN_EVENT_SPI_XFER_ERROR: SPI transfer status code. + * - other: unused + * @param[in] userArg A user supplied argument specified + * in CAN_Params. + */ +typedef void (*CAN_EventCbk)(CAN_Handle handle, uint32_t event, uint32_t data, void *userArg); + +/*! + * @brief CAN Message RAM configuration + * + * The #CAN_MsgRamConfig structure contains information used to configure + * the message RAM. + * + * This structure needs to be defined before calling CAN_init() and it must + * not be changed thereafter. + * + * @sa CAN_init() + */ +typedef struct +{ + uint32_t stdFilterNum; + /*!< Number of Standard ID filter elements [0-128] */ + uint32_t extFilterNum; + /*!< Number of Extended ID filter elements [0-64] */ + MCAN_StdMsgIDFilterElement *stdMsgIDFilterList; + /*!< Points to Standard ID filter elements. Set to NULL if zero elements. */ + MCAN_ExtMsgIDFilterElement *extMsgIDFilterList; + /*!< Points to Extended ID filter elements. Set to NULL if zero elements. */ + + /* + * Note: All Rx and Tx buffer elements include a 64-byte payload if CAN FD + * is enabled. Otherwise, they include an 8-byte payload. + */ + + uint32_t rxFifoNum[2]; + /*!< Number of Rx FIFO elements [0-64] for FIFO0 and FIFO1 respectively */ + uint32_t rxBufNum; + /*!< Number of dedicated Rx Buffer elements [0-64] */ + + uint32_t txBufNum; + /*!< Number of dedicated Tx Buffer elements [0-64] */ + uint32_t txFifoQNum; + /*!< Number of Tx buffer elements [0-64] for Tx FIFO or Queue */ + uint32_t txFifoQMode; + /*!< Tx FIFO/Queue Mode: 0 = Tx FIFO mode, 1 = Tx Queue mode */ + + uint32_t txEventFifoNum; + /*!< Number of Tx Event FIFO elements [0-32] */ +} CAN_MsgRamConfig; + +/*! + * @brief Structure defining the raw MCAN CAN FD data phase bit rate configuration + * + * The length of the bit time is [dtSeg1 + dtSeg2 + 3] tq. + * Bit Rate = (MCAN system clock / (dbrp + 1)) / (length of bit time) + */ +typedef struct +{ + uint32_t dbrp; + /*!< DBRP: Data Bit Rate Prescaler value for the MCAN system clock. + * Interpreted by MCAN as the value is this field + 1. If Transmitter Delay + * Compensation is used, valid range: 0 to 1. Otherwise, valid range: 0 to + * 31. + */ + uint32_t dtSeg1; + /*!< DTSEG1: Data time segment 1 + prop segment. Interpreted by MCAN as the + * value in this field + 1. Valid range: 0 to 31. + */ + uint32_t dtSeg2; + /*!< DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this + * field + 1. Valid range: 0 to 15. + */ + uint32_t dsjw; + /*!< DSJW: Data Resynchronization Jump Width. Interpreted by MCAN as the + * value is this field + 1. Valid range: 0 to 15. Typically set equal to tSeg2. + */ + uint32_t tdcOffset; + /*!< Transmitter Delay Compensation Offset. Defines the offset from the + * measured Tx to Rx delay to the secondary sample point. Set to zero to + * disable Transmitter Delay Compensation. + * Valid range: 0 to 127 mtq. + */ + uint32_t tdcFilterWinLen; + /*!< Transmitter Delay Compensation Filter Window Length. Defines the + * minimum value for the Secondary Sample Point (SSP) position; dominant + * edges on Rx that would result in an earlier SSP position are ignored + * for transmitter delay measurement. The feature is enabled when \c + * tdcFilterWinLen is set to a value greater than \c tdcOffset. + * Valid range: 0 to 127 mtq. + */ +} CAN_DataBitRateTimingRaw; + +/*! + * @brief Structure defining the raw MCAN bit rate configuration + * + * The length of the bit time is [ntSeg1 + ntSeg2 + 3] tq. + * Bit Rate = (MCAN system clock / (nbrp + 1)) / (length of bit time) + */ +typedef struct +{ + uint32_t nbrp; + /*!< NBRP: Nominal Bit Rate Prescaler value for the MCAN system clock. + * Interpreted by MCAN as the value is this field + 1. Valid range: 0 to + * 511. + */ + uint32_t ntSeg1; + /*!< NTSEG1: Nominal time segment 1 + prop segment. Interpreted by MCAN as the + * value in this field + 1. Valid range: 1 to 255. + */ + uint32_t ntSeg2; + /*!< NTSEG2: Nominal time segment 2. Interpreted by MCAN as the value is this + * field + 1. Valid range: 1 to 127. + */ + uint32_t nsjw; + /*!< NSJW: Nominal Resynchronization Jump Width. Interpreted by MCAN as the + * value is this field + 1. Valid range: 0 to 127. Typically set equal to + * tSeg2. + */ + + const CAN_DataBitRateTimingRaw *dataTiming; + /*!< CAN FD data phase bit rate configuration. May be set to NULL if CAN FD + * bit rate switching is not enabled. + */ +} CAN_BitRateTimingRaw; + +/*! + * @brief CAN Parameters + * + * CAN parameters are used with the CAN_open() call. Default values for + * these parameters are set using CAN_Params_init(). + * + * @sa #CAN_Params_init() + */ +typedef struct +{ + const CAN_MsgRamConfig *msgRamConfig; /*!< Pointer to message RAM configuration */ + const CAN_BitRateTimingRaw *bitTiming; /*!< Pointer to raw bit timing values */ + uint32_t tsPrescaler; /*!< Timestamp prescaler */ + CAN_EventCbk eventCbk; /*!< Pointer to event callback function */ + uint32_t eventMask; /*!< Mask of events to call event callback function for */ + void *userArg; /*!< User supplied arg for callback */ +} CAN_Params; + +/*! + * @brief CAN Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + CAN_EventCbk eventCbk; /*!< User supplied event callback */ + uint32_t eventMask; /*!< User supplied event mask */ + void *userArg; /*!< User supplied arg for callback */ + uint32_t intMask; /*!< MCAN interrupt mask */ + + uint32_t txBufNum; /*!< Copy of the number of dedicated Tx Buffer elements */ + uint32_t txFifoQNum; /*!< Copy of the number of Tx buffer elements to use for Tx FIFO or Queue */ + uint32_t txEventFifoNum; /*!< Copy of the number of Tx Event buffer elements */ + uint32_t rxBufNum; /*!< Copy of the number of dedicated Rx Buffer elements */ + uint32_t rxFifoNum[2]; /*!< Copy of the number of Rx FIFO elements [0-64] for FIFO 0 and FIFO 1 respectively */ + + StructRingBuf_Object rxStructRingBuf; /*!< Receive ring buffer */ + StructRingBuf_Object txStructRingBuf; /*!< Transmit ring buffer */ + + bool isOpen; +} CAN_Object; + +/*! + * @brief CAN hardware attributes + * + * CAN hardware attributes provides constant HW-specific configuration and + * should be included in the board file or SysConfig generated file and pointed + * to by the #CAN_config struct. + */ +typedef struct +{ + bool enableCANFD; /*!< Set to true to enable CAN FD */ + bool enableBRS; /*!< Set to true to enable CAN FD bit rate switching */ + bool rejectNonMatchingMsgs; /*!< Set to true to reject incoming messages that do not match a filter */ + uint32_t nominalBitRate; /*!< Bit rate for arbitration */ + uint32_t dataBitRate; /*!< Bit rate for CAN-FD data phase */ + + void *rxRingBufPtr; /*!< Pointer to Rx ring buffer */ + void *txRingBufPtr; /*!< Pointer to Tx ring buffer */ + size_t rxRingBufSize; /*!< Number of Rx ring buffer elements */ + size_t txRingBufSize; /*!< Number of Tx ring buffer elements */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + uint32_t intPriority; /*!< Interrupt priority */ + uint32_t rxPinMux; /*!< Receive pin mux */ + uint32_t txPinMux; /*!< Transmit pin mux */ + uint_least8_t rxPin; /*!< Receive pin */ + uint_least8_t txPin; /*!< Transmit pin */ +#endif +} CAN_HWAttrs; + +/*! + * @brief CAN Global configuration + * + * The CAN_Config structure contains a set of pointers used to characterize + * the CAN driver implementation. + * + */ +typedef struct CAN_Config_ +{ + /*! Pointer to a driver specific data object */ + CAN_Object *object; + + /*! Pointer to a driver specific hardware attributes structure */ + const CAN_HWAttrs *hwAttrs; +} CAN_Config; + +extern const CAN_Config CAN_config[]; +extern const uint_least8_t CAN_count; + +/*! + * @brief This function initializes the CAN module. + * + * @pre The CAN_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other CAN driver APIs. This function call does not modify any + * peripheral registers. + * + * @sa #CAN_open() + */ +void CAN_init(void); + +/*! + * @brief Initializes the #CAN_Params struct to its default values + * + * @param params An pointer to #CAN_Params structure for + * initialization + * + * Defaults values are: + * msgRamConfig = NULL + * bitTiming = NULL + * tsPrescaler = 24U + * eventCbk = NULL + * eventMask = 0U + * userArg = NULL + * + * @sa #CAN_open() + */ +void CAN_Params_init(CAN_Params *params); + +/*! + * @brief Initializes a CAN driver instance and returns a handle. + * + * Initializes a CAN driver instance, configures the CAN device in normal + * operational mode, and returns a handle. Since the MCAN IP is highly + * configurable, the message RAM configuration and raw bit timings may be + * provided in the parameter block. Raw bit timings are required to use + * transmitter delay compensation. Invalid message RAM configuration or + * bit timing parameters will cause this function to fail. + * + * @note For devices with an integrated CAN controller, a power contraint + * to prohibit standby will be set to allow the controller and its + * clock source to remain powered to receive CAN messages from the + * external transceiver. The power constrain will be released when + * #CAN_close() is called. + * + * @pre CAN controller has been initialized using #CAN_init() + * + * @param index Logical peripheral number for the CAN indexed into + * the #CAN_config table + * @param params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #CAN_Handle on success, otherwise, NULL upon error or if it has been + * opened already. + * + * @pre #CAN_init() + * + * @sa #CAN_close() + */ +CAN_Handle CAN_open(uint_least8_t index, CAN_Params *params); + +/*! + * @brief Closes a CAN peripheral specified by \a handle. + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * + * @return None. + */ +void CAN_close(CAN_Handle handle); + +/*! + * @brief Reads a received CAN message + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * @param elem A pointer to a #CAN_RxBufElement. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_NO_RX_MSG_AVAIL if no messages are available. + */ +int_fast16_t CAN_read(CAN_Handle handle, CAN_RxBufElement *elem); + +/*! + * @brief Sends CAN message using the Tx FIFO/Queue + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * @param elem A pointer to a #CAN_TxBufElement. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_ERROR if no Tx FIFO/Queue is configured. + * @retval CAN_STATUS_TX_BUF_FULL if the Tx buffer is full. + */ +int_fast16_t CAN_write(CAN_Handle handle, const CAN_TxBufElement *elem); + +/*! + * @brief Sends CAN message using a dedicated Tx Buffer + * + * Dedicated Tx buffers are intended for message transmission under complete + * control of the application. A custom message RAM config with dedicated Tx + * buffer(s) must be provided during #CAN_init in order to utilize this + * function. + * + * @note The default message RAM configuration uses a Tx Queue in which the + * message with the highest priority in the queue is transmitted first. + * If a custom message RAM configuration with Tx FIFO is used, messages + * are transmitted out in the order they are placed in the FIFO. Adding + * a dedicated Tx buffer to the custom configuration and calling this + * function can allow a new higher priority message to be transmitted + * before the Tx FIFO is empty. + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * @param bufIdx Index of the dedicated Tx buffer. + * @param elem A pointer to a #CAN_TxBufElement. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_ERROR if the Tx buffer index is invalid or + * the buffer already has a Tx request pending. + */ +int_fast16_t CAN_writeBuffer(CAN_Handle handle, uint32_t bufIdx, const CAN_TxBufElement *elem); + +/*! + * @brief Reads the next available CAN Tx Event FIFO element + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * @param elem A pointer to a #CAN_TxEventElement. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_ERROR if no Tx Event FIFO is configured. + * @retval CAN_STATUS_NO_TX_EVENT_AVAIL if no Tx Event is available. + */ +int_fast16_t CAN_readTxEvent(CAN_Handle handle, CAN_TxEventElement *elem); + +/*! + * @brief Get the CAN bit timings and functional clock frequency. + * + * @pre #CAN_open() has to be called first. + * + * @note Add 1 to the bit timing values to obtain the functional values. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * @param bitTiming A pointer to a #CAN_BitTimingParams struct. + * @param clkFreq A pointer to the CAN functional clock frequency in kHz. + */ +void CAN_getBitTiming(CAN_Handle handle, CAN_BitTimingParams *bitTiming, uint32_t *clkFreq); + +/*! + * @brief Enables external loopback test mode + * + * + * @pre #CAN_open() has to be called first. + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_NOT_SUPPORTED if this feature is not supported. + * + * @sa #CAN_enableLoopbackInt() + * @sa #CAN_disableLoopback() + */ +int_fast16_t CAN_enableLoopbackExt(CAN_Handle handle); + +/*! + * @brief Enables internal loopback test mode + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * + * @pre #CAN_open() + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_NOT_SUPPORTED if this feature is not supported. + * + * @sa #CAN_enableLoopbackExt() + * @sa #CAN_disableLoopback() + */ +int_fast16_t CAN_enableLoopbackInt(CAN_Handle handle); + +/*! + * @brief Disables loopback test mode + * + * @pre #CAN_open() has to be called first. + * @pre #CAN_enableLoopbackExt() or #CAN_enableLoopbackInt() + * + * @param handle A #CAN_Handle returned from #CAN_open(). + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_NOT_SUPPORTED if this feature is not supported. + */ +int_fast16_t CAN_disableLoopback(CAN_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_can__include */ diff --git a/simplelink_lpf2/source/ti/drivers/DAC.c b/simplelink_lpf2/source/ti/drivers/DAC.c new file mode 100644 index 00000000..8305866d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/DAC.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== DAC.c ======== + */ + +#include + +/* Default DAC parameters structure */ +const DAC_Params DAC_defaultParams = { + .initCode = 0, /* initial DAC code */ + .custom = NULL, /* customParams */ +}; + +/* + * ======== DAC_Params_init ======== + */ +void DAC_Params_init(DAC_Params *params) +{ + *params = DAC_defaultParams; +} diff --git a/simplelink_lpf2/source/ti/drivers/DAC.h b/simplelink_lpf2/source/ti/drivers/DAC.h new file mode 100644 index 00000000..2fbff88b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/DAC.h @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file DAC.h + * @brief Digital to Analog Conversion (DAC) Output Driver + * + * @anchor ti_drivers_DAC_Overview + * # Overview + * + * The DAC driver allows you to manage a Digital to Analog peripheral via + * simple and portable APIs. This driver supports converting DAC codes + * into an analog voltage with varying degrees of precision (microvolts + * or millivolts) depending on the resolution of the DAC. + * + *
+ * @anchor ti_drivers_DAC_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_DAC_Synopsis + * "usage summary" and a set of @ref ti_drivers_DAC_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_DAC_Synopsis + * ## Synopsis + * @anchor ti_drivers_DAC_Synopsis_Code + * @code + * // Import DAC Driver definitions + * #include + * + * // Define name for DAC channel index + * #define VREFERENCE_OUT 0 + * + * // One-time init of DAC driver + * DAC_init(); + * + * // Initialize optional DAC parameters + * DAC_Params params; + * DAC_Params_init(¶ms); + * + * // Open DAC channels for usage + * DAC_Handle dacHandle = DAC_open(VREFERENCE_OUT, ¶ms); + + * // Enable the DAC channel + * DAC_enable(dacHandle); + * + * // Output 800mV using the DAC + * DAC_setVoltage(dacHandle, 800000); + * + * // Output a voltage using DAC codes + * DAC_setCode(dacHandle, 125); + * + * // Disable the DAC channel + * DAC_disable(dacHandle); + * + * // Close the DAC channel + * DAC_close(dacHandle); + * + * @endcode + * + *
+ * @anchor ti_drivers_DAC_Examples + * # Examples + * + * @li @ref ti_drivers_DAC_Examples_open "Opening a DAC instance" + * @li @ref ti_drivers_DAC_Examples_reference "Using DAC to set a reference voltage" + * @li @ref ti_drivers_DAC_Examples_code "Using DAC to set a code" + * + * @anchor ti_drivers_DAC_Examples_open + * ## Opening a DAC instance + * + * @code + * DAC_Handle dac; + * DAC_Params params; + * + * DAC_Params_init(¶ms); + * + * dac = DAC_open(0, ¶ms); + * if (dac == NULL) { + * // DAC_open() failed + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_DAC_Examples_reference + * ## Using DAC to set a reference voltage + * + * To set a reference voltage first enable the DAC with DAC_enable() + * and then set the desired output voltage with DAC_setVoltage(). + * The returned value can be used to check if the call was successful. + * + * @code + * int_fast16_t res; + * uint32_t outputMicroVolts = 1500000; + * + * DAC_enable(dac); + * res = DAC_setVoltage(dac, outputMicroVolts); + * if (res == DAC_STATUS_SUCCESS) + * { + * printf(outputMicroVolts); + * } + * @endcode + * + * @anchor ti_drivers_DAC_Examples_code + * ## Using DAC to set a code + * + * The following example shows how to set a DAC code. The use of DAC_setCode() + * instead of DAC_setVoltage() comes handy in scenarios such as outputting a + * data buffer at a particular time rate (e.g. waveform generation). Nevertheless, + * it's important to remember that DAC codes produce different output voltages + * depending on the selected voltage reference source. + * + * @code + * int_fast16_t res; + * uint32_t outputCode = 127; + * DAC_enable(dac); + * res = DAC_setCode(dac, outputCode); + * if (res == DAC_STATUS_SUCCESS) + * { + * printf(outputCode); + * } + * @endcode + * + *
+ * @anchor ti_drivers_DAC_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_DAC__include +#define ti_drivers_DAC__include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_dac.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Successful status code returned by DAC API. + */ +#define DAC_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by DAC API. + */ +#define DAC_STATUS_ERROR (-1) + +/*! + * @brief The DAC is currently in use by another handle or by the sensor controller. + */ +#define DAC_STATUS_INUSE (-2) + +/*! + * @brief The desired output value is outside the DAC's output range. + */ +#define DAC_STATUS_INVALID (-3) + +/*! @brief DAC Global configuration + * + * The DAC_Config structure contains a set of pointers used to characterize + * the DAC driver implementation. + * + * This structure needs to be defined before calling DAC_init() and it must + * not be changed thereafter. + * + * @sa DAC_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} DAC_Config; + +/*! + * @brief A handle that is returned from a DAC_open() call. + */ +typedef DAC_Config *DAC_Handle; + +/*! + * @brief Basic DAC Parameters + * + * DAC parameters used with the DAC_open() call. Default values for these + * parameters are set using DAC_Params_init(). + * + * @sa DAC_Params_init() + */ +typedef struct +{ + /*! Initial DAC code */ + uint32_t initCode; + /*! Pointer to device specific custom params */ + void *custom; +} DAC_Params; + +/*! + * @brief Default DAC_Params structure + * + * @sa DAC_Params_init() + */ +extern const DAC_Params DAC_defaultParams; + +/*! + * @brief Function to initialize the DAC module. + * + * @pre The DAC_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other DAC driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void DAC_init(void); + +/*! + * @brief Function to initialize a given DAC peripheral specified by the + * particular index value. + * + * @pre DAC controller has been initialized + * + * @param [inout] index Logical peripheral number for the DAC indexed into + * the DAC_config table + * + * @param [in] params Pointer to a parameter block. + * All the fields in this structure are RO (read-only). + * Providing a NULL pointer cannot open the module. + * + * @return A DAC_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa DAC_init() + * @sa DAC_close() + */ +extern DAC_Handle DAC_open(uint_least8_t index, DAC_Params *params); + +/*! + * @brief Function to close a given DAC peripheral specified by the DAC + * handle. + * + * @pre DAC_open() had to be called first. + * + * @param [in] handle A DAC_Handle returned from DAC_open + * + * @sa DAC_open() + */ +extern void DAC_close(DAC_Handle handle); + +/*! + * @brief Function to set the DAC voltage value in microvolts. + * + * @warning This function takes a value in microvolts, but the actual + * output is limited by the DAC's resolution. + * + * @pre DAC_enable() has to be called first. + * + * @param [in] handle A DAC_Handle returned from DAC_open. + * + * @param [in] uVoltOutput Desired output voltage in uV. + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #DAC_STATUS_SUCCESS The call was successful. + * @retval #DAC_STATUS_ERROR The call was unsuccessful. + * @retval #DAC_STATUS_INVALID The desired output voltage was out of bounds + * for the DAC. + * + * @sa DAC_setCode() + */ +extern int_fast16_t DAC_setVoltage(DAC_Handle handle, uint32_t uVoltOutput); + +/*! + * @brief Function to set the DAC voltage in terms of a DAC code. + * + * @warning The appropriate DAC code is device-specific and admissible values + * depend on the DAC's resolution. + * + * @pre DAC_open() has to be called first. + * + * @param [in] handle A DAC_Handle returned from DAC_open. + * + * @param [in] code Desired output in terms of a DAC code. + * + * @retval #DAC_STATUS_SUCCESS The call was successful. + * @retval #DAC_STATUS_ERROR The call was unsuccessful. + * + * + * @sa DAC_open() + */ +extern int_fast16_t DAC_setCode(DAC_Handle handle, uint32_t code); + +/*! + * @brief Function to enable the DAC's output. + * + * This function claims ownership of the DAC peripheral, and depending on + * the selected voltage reference source, it calculates the output voltage + * range. + * + * Furthermore, the function configures and enables the DAC. + * + * @pre DAC_open() has to be called first. + * + * @param [in] handle A DAC_Handle returned from DAC_open. + * + * @retval #DAC_STATUS_SUCCESS The call was successful. + * @retval #DAC_STATUS_ERROR The call was unsuccessful. + * @retval #DAC_STATUS_INUSE The call was unsuccessful because the DAC is in + * use by the Sensor Controller or by another + * handle. + * + * @sa DAC_disable() + */ +extern int_fast16_t DAC_enable(DAC_Handle handle); + +/*! + * @brief Function to disable the DAC's output. + * + * @pre DAC_enable() has to be called first. + * + * @param [in] handle A DAC_Handle returned from DAC_open. + * + * @retval #DAC_STATUS_SUCCESS The call was successful. + * @retval #DAC_STATUS_ERROR The call was unsuccessful. + * + * @sa DAC_enable() + */ +extern int_fast16_t DAC_disable(DAC_Handle handle); + +/*! + * @brief Function to initialize the DAC_Params struct to its defaults. + * + * @param [out] params A pointer to DAC_Params structure for + * initialization + * + * Defaults values are: + * @code + * params.initCode = 0, + * params.custom = NULL; + * @endcode + * + * @param params Parameter structure to initialize + */ +extern void DAC_Params_init(DAC_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_DAC__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ECDH.c b/simplelink_lpf2/source/ti/drivers/ECDH.c new file mode 100644 index 00000000..8350efcd --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECDH.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECDH.c ======== + * + * This file contains default values for the ECDH_Params struct + * + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const ECDH_Config ECDH_config[]; +extern const uint_least8_t ECDH_count; + +const ECDH_Params ECDH_defaultParams = { + .returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECDH_open ======== + */ +__attribute__((weak)) ECDH_Handle ECDH_open(uint_least8_t index, const ECDH_Params *params) +{ + DebugP_assert(index < ECDH_count); + + ECDH_Config *config = (ECDH_Config *)&ECDH_config[index]; + return ECDH_construct(config, params); +} + +/* + * ======== ECDH_OperationGeneratePublicKey_init ======== + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation) +{ + operation->curve = NULL; + operation->myPrivateKey = NULL; + operation->myPublicKey = NULL; + /* Default key material endianness is big endian*/ + operation->keyMaterialEndianness = ECDH_BIG_ENDIAN_KEY; +} +/* + * ======== ECDH_OperationComputeSharedSecret_init ======== + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation) +{ + operation->curve = NULL; + operation->myPrivateKey = NULL; + operation->theirPublicKey = NULL; + operation->sharedSecret = NULL; + /* Default key material endianness is big endian*/ + operation->keyMaterialEndianness = ECDH_BIG_ENDIAN_KEY; +} diff --git a/simplelink_lpf2/source/ti/drivers/ECDH.h b/simplelink_lpf2/source/ti/drivers/ECDH.h new file mode 100644 index 00000000..426759f1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECDH.h @@ -0,0 +1,915 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECDH.h + * + * @brief TI Driver for Elliptic Curve Diffie-Hellman key agreement scheme. + * + * @anchor ti_drivers_ECDH_Overview + * # Overview # + * + * Elliptic Curve Diffie-Hellman (ECDH) is a key agreement scheme between + * two parties based on the Diffie-Hellman key exchange protocol. + * + * It provides a means of generating a shared secret and derived symmetric key + * between the two parties over an insecure channel. + * + * It does not provide authentication. As such, it does not guarantee that the + * party you are exchanging keys with is truly the party you wish to establish a + * secured channel with. + * + * The two parties each generate a private key and a public key. The private key + * is a random integer in the interval [1, n - 1], where n is the order of a + * previously agreed upon curve. The public key is generated + * by multiplying the private key by the generator point of a previously agreed + * upon elliptic curve such as NISTP256 or Curve 25519. The public key is itself + * a point upon the elliptic curve. Each public key is then transmitted to the + * other party over a potentially insecure channel. The other party's public key + * is then multiplied with the private key, generating a shared secret. This + * shared secret is also a point on the curve. However, the entropy in the secret + * is not spread evenly throughout the shared secret. In order to generate one or more + * shared symmetric keys, the shared secret must be run through a key derivation + * function (KDF) that was previously agreed upon. Usually, only the X coordinate + * is processed in this way as it contains all the entropy of the shared secret and + * some curve implementations only provide the X coordinate. The key derivation function + * can take many forms, from simply hashing the X coordinate of the shared secret + * with SHA2 and truncating the result to generating multiple symmetric keys with + * HKDF, an HMAC based KDF. + * + * Key derivation functions in the context of symmetric key generation after + * elliptic curve based key exchange differ from KDFs used to generate keys from + * passwords a user provides in a login. Those KDFs such as bcrypt purposefully + * add additional computation to increase a system's resistance against brute + * force or dictionary attacks. + * + * @anchor ti_drivers_ECDH_Usage + * # Usage # + * + * ## Before starting an ECDH operation # + * + * Before starting an ECDH operation, the application must do the following: + * - Call ECDH_init() to initialize the driver + * - Call ECDH_Params_init() to initialize the ECDH_Params to default values. + * - Modify the ECDH_Params as desired + * - Call ECDH_open() to open an instance of the driver + * + * ## Generating your public-private key pair # + * To generate a public-private key pair for an agreed upon curve, the application + * must do the following: + * - Generate the keying material for the private key. This keying material must + * be an integer in the interval [1, n - 1], where n is the order of the curve. + * It can be stored in big-endian or little-endian format. + * The array should be the same length as the curve parameters of the curve used. + * The driver validates private keys against the provided curve by default. + * - Initialize the private key CryptoKey. CryptoKeys are opaque data structures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The ECDH API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a blank CryptoKey for the public key. The CryptoKey will keep track + * of where the keying material for the public key should be copied and how + * long it is. SEC 1-based big-endian format public keys should have key material twice the length + * of the private key plus one. Little-endian format public keys should have key material the + * length of the private key for Montgomery curve X-only public keys or have key material twice + * the length of the private for other curves + * - Initialize the ECDH_OperationGeneratePublicKey struct and then populate it. By + * default, big-endian public keys will be generated. + * - If using RFC 7748-style public keys, initialize the operation's public key + * data format to be ECDH_LITTLE_ENDIAN_KEY. + * - Call ECDH_generatePublicKey(). The generated keying material will be copied + * according the the CryptoKey passed in as the public key parameter. The CryptoKey + * will no longer be considered 'blank' after the operation. + * + * ## Calculating a shared secret # + * After trading public keys with the other party, the application should do the following + * to calculate the shared secret: + * - Initialize a CryptoKey as public key with the keying material received from the other + * party. + * - Initialize the private key CryptoKey with the key used to generate your + * public key. CryptoKeys are opaque data structures and representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The ECDH API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize a blank CryptoKey with the same size as the previously initialized + * public key. + * - Initialize the ECDH_OperationComputeSharedSecret struct and then populate it. By + * default, big-endian input keys will be assumed and big-endian shared secrets + * will be generated. + * - If importing RFC 7748-style public keys, initialize the operation's key material + * endianess to be ECDH_LITTLE_ENDIAN_KEY. + * - Call ECDH_computeSharedSecret(). The shared secret will be copied to a location + * according to the shared secret CryptoKey passed to the function call. The driver + * will validate the supplied public key and reject invalid ones. + * + * ## Creating one or more symmetric keys from the shared secret # + * After calculating the shared secret between the application and the other party, + * the entropy in the shared secret must be evened out and stretched as needed. There are + * uncountable methods and algorithms to stretch an original seed entropy (the share secret) + * to generate symmetric keys. + * - Run the X coordinate of the resulting entropy through a key derivation function (KDF) + * + * ## After a key exchange # + * After the ECDH key exchange completes, the application should either start another operation + * or close the driver by calling ECDH_close() + * + * ## General usage # + * The API expects elliptic curves as defined in ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECDH documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your device. + * ECDH support for a curve type on a device does not imply curve-type support for + * other ECC schemes. + * + * ## Key Formatting + * By default, the ECDH API expects the private and public keys to be formatted in + * big-endian format. The details of octet string formatting can be found in + * SEC 1: Elliptic Curve Cryptography. + * + * ## Limitations # + * For CC27XX devices, the ECDH driver cannot accept private keys with a + * value of 0x01 (entire value is 0x01). + * + * Private keys can be formatted as big-endian or little-endian integers of the same + * length as the curve length. + * + * Public keys and shared secrets are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as an + * X,Y pair. + * This API uses points expressed in uncompressed affine coordinates by default. + * The big-endian format requires a formatting byte in the first byte of the + * public key. When using uncompressed affine coordinates, this is the value + * 0x04. + * The point itself is stored as a concatenated array of X followed by Y. + * X and Y maybe in big-endian or little-endian. Some implementations do not require or + * yield the Y coordinate for ECDH on certain curves. It is recommended that the full + * keying material buffer of twice the curve param length is used to facilitate + * code-reuse. Implementations that do not use the Y coordinate will zero-out + * the Y-coordinate whenever they write a point to the CryptoKey. + * + * If device-supported, Montgomery curves can be stored as their X-only format + * based on the RFC-7748 specification. Here, only the X coordinate is packed + * in little-endian integers of the same length as the curve length. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|----------------------------| + * | Short Weierstrass | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [X] | Curve Param Length | + * | Edwards | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * + * Note: This driver will automatically prune the private key according to + * RFC 7748 for the following curve: + * X25519 + * + * @anchor ti_drivers_ECDH_Synopsis + * ## Synopsis + * @anchor ti_drivers_ECDH_Synopsis_Code + * @code + * // Import ECDH Driver definitions + * #include + * + * ECDH_init(); + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialize their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * // Close the driver + * ECDH_close(ecdhHandle); + * + * @endcode + * + * ## Synopsis for X25519 X-only key exchange + * @anchor ti_drivers_ECDH_X25519_Code + * @code + * // Import ECDH Driver definitions + * #include + * + * ECDH_init(); + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * // For CC27XX devices only, + * // Since the ECDH driver for CC27XX relies on one HW engine (the HSM) for all of its operations + * // If the HSM boot up sequence fails, ECDH_open() will return NULL. + * if (!ecdhHandle) { + * // Handle error + * } + * + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * // Note that the public key size is only 32 bytes + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_Curve25519; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * // If generating public key in little-endian format, we use the following format: + * operationGeneratePublicKey.keyMaterialEndianness = ECDH_LITTLE_ENDIAN_KEY; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material to theirPublicKeyingMaterial + * + * // Initialize their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_Curve25519; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * // If receiving and generating keys in little-endian format, we use the following format: + * operationComputeSharedSecret.keyMaterialEndianness = ECDH_LITTLE_ENDIAN_KEY; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * // Close the driver + * ECDH_close(ecdhHandle); + * + * @endcode + * + * @anchor ti_drivers_ECDH_Examples + * # Examples # + * + * ## ECDH exchange with plaintext CryptoKeys # + * + * @code + * + * #include + * #include + * + * #define CURVE_LENGTH 32 + * + * ... + * + * // Our private key is 0x0000000000000000000000000000000000000000000000000000000000000001 + * // In practice, this value should come from a TRNG, PRNG, PUF, or device-specific pre-seeded key + * uint8_t myPrivateKeyingMaterial[CURVE_LENGTH] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + * 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}; + * uint8_t myPublicKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t theirPublicKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t sharedSecretKeyingMaterial[2 * CURVE_LENGTH + 1] = {0}; + * uint8_t symmetricKeyingMaterial[16] = {0}; + * + * CryptoKey myPrivateKey; + * CryptoKey myPublicKey; + * CryptoKey theirPublicKey; + * CryptoKey sharedSecret; + * CryptoKey symmetricKey; + * + * ECDH_Handle ecdhHandle; + * + * int_fast16_t operationResult; + * + * ECDH_OperationGeneratePublicKey operationGeneratePublicKey; + * + * // Since we are using default ECDH_Params, we just pass in NULL for that parameter. + * ecdhHandle = ECDH_open(0, NULL); + * + * if (!ecdhHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey and myPublicKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial)); + * + * ECDH_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_NISTP256; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial + * operationResult = ECDH_generatePublicKey(ecdhHandle, &operationGeneratePublicKey); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Now send the content of myPublicKeyingMaterial to the other party, + * // receive their public key, and copy their public keying material and the + * // 0x04 byte to theirPublicKeyingMaterial + * + * // Initialise their public CryptoKey and the shared secret CryptoKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial)); + * CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial)); + * + * // The ECC_NISTP256 struct is provided in ti/drivers/types/EccParams.h and the corresponding device-specific + * implementation ECDH_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myPrivateKey = &myPrivateKey; + * operationComputeSharedSecret.theirPublicKey = &theirPublicKey; + * operationComputeSharedSecret.sharedSecret = &sharedSecret; + * + * // Compute the shared secret and copy it to sharedSecretKeyingMaterial + * operationResult = ECDH_computeSharedSecret(ecdhHandle, &operationComputeSharedSecret); + * + * if (operationResult != ECDH_STATUS_SUCCESS) { + * // Handle error + * } + * + * CryptoKeyPlaintext_initBlankKey(&symmetricKey, symmetricKeyingMaterial, sizeof(symmetricKeyingMaterial)); + * + * // Set up a KDF such as HKDF and open the requisite cryptographic primitive driver to implement it + * // HKDF and SHA2 were chosen as an example and may not be available directly + * + * // At this point, you and the other party have both created the content within symmetricKeyingMaterial without + * // someone else listening to your communication channel being able to do so + * + * @endcode + * + * + */ + +#ifndef ti_drivers_ECDH__include +#define ti_drivers_ECDH__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common ECDH status code reservation offset. + * ECC driver implementations should offset status codes with + * ECDH_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECCXYZ_STATUS_ERROR0 ECDH_STATUS_RESERVED - 0 + * #define ECCXYZ_STATUS_ERROR1 ECDH_STATUS_RESERVED - 1 + * #define ECCXYZ_STATUS_ERROR2 ECDH_STATUS_RESERVED - 2 + * @endcode + */ +#define ECDH_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECDH_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECDH_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECDH_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECDH_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECC driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECDH_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The result of the operation is the point at infinity. + * + * The operation yielded the point at infinity on this curve. This point is + * not permitted for further use in ECC operations. + */ +#define ECDH_STATUS_POINT_AT_INFINITY (-3) + +/*! + * @brief The private key passed in is larger or equal to the order of the curve. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER (-4) + +/*! + * @brief The private key passed in is zero. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECDH_STATUS_PRIVATE_KEY_ZERO (-5) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-6) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-7) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECDH_STATUS_CANCELED (-8) + +/*! + * @brief The provided CryptoKey does not match the expected size + * + * The driver expects the private key to have the same length as other curve + * parameters and the public key to have a length of twice that plus one. + * If the provided CryptoKeys for the public and private keys do not match this + * scheme, this error will be returned. + */ +#define ECDH_STATUS_INVALID_KEY_SIZE (-9) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return ECDH_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define ECDH_STATUS_KEYSTORE_ERROR (-10) + +/*! + * @brief ECC Global configuration + * + * The ECDH_Config structure contains a set of pointers used to characterize + * the ECC driver implementation. + * + * This structure needs to be defined before calling ECDH_init() and it must + * not be changed thereafter. + * + * @sa ECDH_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECDH_Config; + +/*! + * @brief A handle that is returned from an ECDH_open() call. + */ +typedef ECDH_Config *ECDH_Handle; + +/*! + * @brief The way in which ECDH function calls return after performing a + * public key generation or shared secret compution operation. + * + * Callback return behavior is not supported by software-backed implementations. + * A NULL handle will be returned when attempting to open or construct a driver + * instance with an unsupported return behavior. + * + * Not all ECDH operations exhibit the specified return behavior. Functions that + * do not require significant computation and cannot offload that computation to + * a background thread behave like regular functions. Which functions exhibit + * the specfied return behavior is not implementation dependent. Specifically, a + * software-backed implementation run on the same CPU as the application will + * emulate the return behavior while not actually offloading the computation to + * the background thread. + * + * ECDH functions exhibiting the specified return behavior have restrictions on + * the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |ECDH_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECDH_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECDH_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes + * on in the background. ECC operation results are available + * after the function returns. + */ + ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC + * operation goes on in the background. ECC operation results + * are available after the function returns. + */ +} ECDH_ReturnBehavior; + +typedef enum +{ + ECDH_BIG_ENDIAN_KEY = 0, /*!< All ECDH key material (private key, public key, and shared secret (when used)) + * are in big-endian format + */ + ECDH_LITTLE_ENDIAN_KEY = 1, /*!< All ECDH key material (private key, public key, and shared secret (when used)) + * are in little-endian format + */ +} ECDH_KeyMaterialEndianness; + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/*! + * @brief Enum for the curve types supported by the driver. + */ +typedef enum +{ + ECDH_TYPE_SEC_P_224_R1 = 1, + ECDH_TYPE_SEC_P_256_R1 = 2, + ECDH_TYPE_SEC_P_384_R1 = 3, + ECDH_TYPE_SEC_P_521_R1 = 4, + ECDH_TYPE_BRP_P_256_R1 = 5, + ECDH_TYPE_BRP_P_384_R1 = 6, + ECDH_TYPE_BRP_P_512_R1 = 7, + ECDH_TYPE_CURVE_25519 = 8, +} ECDH_CurveType; + +/*! + * @brief Enum for signature sizes in bits supported by the driver. + */ +typedef enum +{ + ECDH_CURVE_LENGTH_192 = 192, + ECDH_CURVE_LENGTH_224 = 224, + ECDH_CURVE_LENGTH_255 = 255, + ECDH_CURVE_LENGTH_256 = 256, + ECDH_CURVE_LENGTH_384 = 384, + ECDH_CURVE_LENGTH_512 = 512, + ECDH_CURVE_LENGTH_521 = 521, +} ECDH_CurveLength; +#endif + +/*! + * @brief Struct containing the parameters required to generate a public key. + */ +typedef struct +{ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + ECDH_CurveType curveType; /*!< An ECDSA_CurveType value indicating which EC curve to use for the operation*/ +#endif + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key from which the new public + * key will be generated. (maybe your static key) + */ + CryptoKey *myPublicKey; /*!< A pointer to a public ECC key which has been initialized blank. + * Newly generated key will be placed in this location. + * The formatting byte will be filled in by the driver if the + * keyMaterialEndianness requires it. + */ + ECDH_KeyMaterialEndianness keyMaterialEndianness; /*!< All keyMaterials, including myPrivate and myPublicKey, + * are either in big-endian (default) or little-endian format + */ +} ECDH_OperationGeneratePublicKey; + +/*! + * @brief Struct containing the parameters required to compute the shared secret. + */ +typedef struct +{ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + ECDH_CurveType curveType; /*!< An ECDSA_CurveType value indicating which EC curve to use for the operation*/ +#endif + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey. + * If ECDH_generateKey() was used, this should be the same private key. + */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key which will be used in to + * compute the shared secret. + */ + const CryptoKey *theirPublicKey; /*!< A pointer to the public key of the party with whom the + * shared secret will be generated. + */ + CryptoKey *sharedSecret; /*!< A pointer to a CryptoKey which has been initialized blank. + * The shared secret will be placed here. + * The formatting byte will be filled in by the driver if the + * keyMaterialEndianness requires it. + */ + ECDH_KeyMaterialEndianness keyMaterialEndianness; /*!< All keyMaterials, including myPrivate, theirPublicKey, and + * sharedSecret are either in big-endian (default) or little- + * endian format + */ +} ECDH_OperationComputeSharedSecret; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union +{ + ECDH_OperationGeneratePublicKey *generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ + ECDH_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECDH_OperationComputeSharedSecret + * struct + */ +} ECDH_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY = 1, + ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET = 2, +} ECDH_OperationType; + +/*! + * @brief The definition of a callback function used by the ECDH driver + * when used in ::ECDH_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECDH operation. + * + * @param returnStatus The result of the ECDH operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECDH_CallbackFxn)(ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); + +/*! + * @brief ECC Parameters + * + * ECC Parameters are used to with the ECDH_open() call. Default values for + * these parameters are set using ECDH_Params_init(). + * + * @sa ECDH_Params_init() + */ +typedef struct +{ + ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout of the operation */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECDH_Params; + +/*! + * @brief Default ECDH_Params structure + * + * @sa ECDH_Params_init() + */ +extern const ECDH_Params ECDH_defaultParams; + +/*! + * @brief This function initializes the ECC module. + * + * @pre The ECDH_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECC driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECDH_init(void); + +/*! + * @brief Function to initialize the ECDH_Params struct to its defaults + * + * @param params An pointer to ECDH_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECDH_Params_init(ECDH_Params *params); + +/*! + * @brief This function opens a given ECC peripheral. + * + * @pre ECC controller has been initialized using ECDH_init() + * + * @param index Logical peripheral number for the ECC indexed into + * the ECDH_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECDH_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ECDH_init() + * @sa ECDH_close() + */ +ECDH_Handle ECDH_open(uint_least8_t index, const ECDH_Params *params); + +/*! + * @brief Function to close an ECC peripheral specified by the ECC handle + * + * @pre ECDH_open() has to be called first. + * + * @param handle An ECC handle returned from ECDH_open() + * + * @sa ECDH_open() + */ +void ECDH_close(ECDH_Handle handle); + +/*! + * @brief Function to initialize an ECDH_OperationGeneratePublicKey struct to its defaults + * + * @param operation A pointer to ECDH_OperationGeneratePublicKey structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationGeneratePublicKey_init(ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Function to initialize an ECDH_OperationComputeSharedSecret struct to its defaults + * + * @param operation A pointer to ECDH_OperationComputeSharedSecret structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDH_OperationComputeSharedSecret_init(ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Generates a public key for use in key agreement. + * + * This function can be used to generate a public key from a private key. + * + * @param handle A ECDH handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECDH_OperationGeneratePublicKey_init() on @c operation. + * + * @post ECDH_computeSharedSecret() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_POINT_AT_INFINITY The computed public key is the point at infinity. + * @retval #ECDH_STATUS_PRIVATE_KEY_ZERO The provided private key is zero. + * @retval #ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER The provided private key is larger than or equal to the order + * of the curve. + * + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation); + +/*! + * @brief Computes a shared secret + * + * This secret can be used to generate shared keys for encryption and authentication. + * + * @param handle A ECDH handle returned from ECDH_open() + * + * @param operation A pointer to a struct containing the requisite + * + * @pre Call ECDH_OperationComputeSharedSecret_init() on \c operation. + * Generate a shared secret off-chip or using ECDH_generatePublicKey() + * + * @retval #ECDH_STATUS_SUCCESS The operation succeeded. + * @retval #ECDH_STATUS_ERROR The operation failed. + * @retval #ECDH_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECDH_STATUS_CANCELED The operation was canceled. + * @retval #ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE The foreign public key is not a point on the specified curve. + * @retval #ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME One of the public key coordinates is larger the the curve's + * prime. + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation); + +/*! + * @brief Cancels an ongoing ECDH operation. + * + * Asynchronously cancels an ECDH operation. Only available when using + * ECDH_RETURN_BEHAVIOR_CALLBACK or ECDH_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be ECDH_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECDH_STATUS_SUCCESS The operation was canceled. + * @retval #ECDH_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle); + +/** + * @brief Constructs a new ECDH object + * + * Unlike #ECDH_open(), #ECDH_construct() does not require the hwAttrs and + * object to be allocated in a #ECDH_Config array that is indexed into. + * Instead, the #ECDH_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #ECDH_Config describing the location of the object and hwAttrs. + * + * @param params #ECDH_Params to configure the driver instance. + * + * @return Returns a #ECDH_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +ECDH_Handle ECDH_construct(ECDH_Config *config, const ECDH_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECDH__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ECDSA.c b/simplelink_lpf2/source/ti/drivers/ECDSA.c new file mode 100644 index 00000000..669a94a0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECDSA.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECDSA.c ======== + * + * This file contains default values for the ECDSA_Params struct + * + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const ECDSA_Config ECDSA_config[]; +extern const uint_least8_t ECDSA_count; + +const ECDSA_Params ECDSA_defaultParams = { + .returnBehavior = ECDSA_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECDSA_Params_init ======== + */ +void ECDSA_Params_init(ECDSA_Params *params) +{ + *params = ECDSA_defaultParams; +} + +/* + * ======== ECDSA_open ======== + */ +__attribute__((weak)) ECDSA_Handle ECDSA_open(uint_least8_t index, const ECDSA_Params *params) +{ + DebugP_assert(index < ECDSA_count); + + ECDSA_Config *config = (ECDSA_Config *)&ECDSA_config[index]; + return ECDSA_construct(config, params); +} + +/* + * ======== ECDSA_OperationSign_init ======== + */ +void ECDSA_OperationSign_init(ECDSA_OperationSign *operation) +{ + memset(operation, 0x00, sizeof(ECDSA_OperationSign)); +} + +/* + * ======== ECDSA_OperationVerify_init ======== + */ +void ECDSA_OperationVerify_init(ECDSA_OperationVerify *operation) +{ + memset(operation, 0x00, sizeof(ECDSA_OperationVerify)); +} diff --git a/simplelink_lpf2/source/ti/drivers/ECDSA.h b/simplelink_lpf2/source/ti/drivers/ECDSA.h new file mode 100644 index 00000000..cf512be5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECDSA.h @@ -0,0 +1,975 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! + * @file ECDSA.h + * + * @brief TI Driver for Elliptic Curve Digital Signature Algorithm. + * + * + * @anchor ti_drivers_ECDSA_Overview + * # Overview # + * + * The Elliptic Curve Digital Signature Algorithm (ECDSA) is a message + * authentication scheme between two parties based on operation on elliptic + * curves over finite fields. + * + * Signing a message with ECDSA proves to the recipient that the sender of + * the message is in possession of the private key corresponding to the + * transmitted public key used during verification. + * For most practical systems, this ensures message authentication and + * integrity. + * + * # Steps involved # + * - The sender hashes the message they wish to authenticate and + * truncates it to the length of the curve parameters of the + * elliptic curve used by both parties. + * - The sender generates r and s where 0 < r, s < N. These two integers + * constitute the actual signature of the message. + * - The sender transmits the message, r, s, and the public key to the + * recipient. + * - The recipient calculates the hash of the message using an agreed + * upon hash function and truncates it to the length of the curve + * parameters of the elliptic curve used by both parties + * - The recipient uses the hash, s, and the sender's public key to + * recalculate r. + * - The recipient accepts the signature if the received and calculated r + * match. Otherwise, they reject the signature. + * + * @anchor ti_drivers_ECDSA_Usage + * # Usage # + * + * ## Before starting an ECDSA operation # + * + * Before starting an ECDSA operation, the application must do the following: + * - Call ECDSA_init() to initialize the driver + * - Call ECDSA_Params_init() to initialize the ECDSA_Params to default + * values. + * - Modify the ECDSA_Params as desired + * - Call ECDSA_open() to open an instance of the driver + * + * ## Signing a message # + * To sign a message using an agreed upon hash function and elliptic curve, the + * application must do the following: + * - Initialize an ECDSA_OperationSign struct by calling + * ECDSA_OperationSign_init(). + * - Generate the keying material for the private key. This keying material + * must be an integer in the interval [1, n - 1], where n is the order of the + * curve. It should be stored in an array with the least significant byte of + * the integer hex representation stored in the highest address of the array + * (big-endian). + * The array should be the same length as the curve parameters of the curve + * used. The driver validates public and private keys against the provided + * curve. + * - Initialize the private key CryptoKey. CryptoKeys are opaque datastructures + * and representations of keying material and its storage. + * Depending on how the keying material is stored (RAM or flash, key store), + * the CryptoKey must be initialized differently. + * The ECDSA API can handle all types of CryptoKey. + * However, not all device-specific implementions support all types of + * CryptoKey. + * Devices without a key store will not support CryptoKeys with keying + * material stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Hash the message using a previously agreed upon hash function and truncate + * the hash to the length of the curve parameters of the agreed upon curve. + * - Call ECDSA_sign(). The r and s vectors will be written to the buffers + * provided in the function call. Ensure the return value is + * ECDSA_STATUS_SUCCESS. + * + * ## Verifying a message # + * After receiving the message, public key, r, and s, the application should + * do the following to verify the signature: + * - Initialize an ECDSA_OperationVerify struct by calling + * ECDSA_OperationVerify_init(). + * - Hash the message using a previously agreed upon hash function and truncate + * the hash to the length of the curve parameters of the agreed upon curve. + * - Initialize a CryptoKey as public key with the keying material received + * from the other party. + * - Call ECDSA_verify(). Ensure the return value is ECDSA_STATUS_SUCCESS. The + * driver will validate the received public key against the provided curve. + * + * ## General usage # + * The API expects elliptic curves as defined in + * ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific ECDSA + * documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your + * device. + * ECDSA support for a curve type on a device does not imply curve-type support + * for other ECC schemes. + * + * ## Parameter formatting # + * Public keys are points on an elliptic curve. These points can + * be expressed in several ways. The most common one is in affine coordinates as + * an X,Y pair. + * This API uses points expressed in uncompressed affine coordinates by default + * and formatted in octet string format. + * The octet string format requires a formatting byte in the first byte of the + * public key. When using uncompressed coordinates, this is the value + * 0x04. + * The point itself is stored as a concatenated array of X followed by Y. + * X and Y are big-endian. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | PublicKeying Material Array | Array Length | + * |--------------------|-----------------------|----------------------------| + * | Short Weierstrass | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Edwards | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * + * The signature components r and s as well as the hash must be formatted in + * octet string format. For the hash, this simply means passing the digest of + * the hash function such as SHA-256 directly into #ECDSA_sign() or + * #ECDSA_verify(). r and s will be interpreted as big-endian integers. + * + * @anchor ti_drivers_ECDSA_Synopsis + * ## Synopsis + * @anchor ti_drivers_ECDSA_Synopsis_Code + * @code + * // Import ECDSA Driver definitions + * #include + * + * // Since we are using default ECDSA_Params, + * // we just pass in NULL for that parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, + * myPrivateKeyingMaterial, + * sizeof(myPrivateKeyingMaterial)); + * + * // Initialize the operation + * ECDSA_OperationSign_init(&operationSign); + * operationSign.curve = &ECCParams_NISTP256; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.hash = messageHash; + * operationSign.r = r; + * operationSign.s = s; + * + * // Generate the signature + * operationResult = ECDSA_sign(ecdsaHandle, &operationSign); + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, + * theirPublicKeyingMaterial, + * sizeof(theirPublicKeyingMaterial)); + * + * ECDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_NISTP256; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.hash = messageHash; + * operationVerify.r = r; + * operationVerify.s = s; + * + * // Generate the keying material for myPublicKey and store it in + * // myPublicKeyingMaterial + * operationResult = ECDSA_verify(ecdsaHandle, &operationVerify); + * + * // Close the driver + * ECDSA_close(ecdsaHandle); + * @endcode + * + * @anchor ti_drivers_ECDSA_Examples + * # Examples # + * + * ## ECDSA sign with plaintext CryptoKeys for CC27XX and CC35XX devices ## + * + * @code + * + * #include + * #include + * + * ... + * + * // This vector is taken from the NIST ST toolkit examples from ECDSA_Prime.pdf + * uint8_t myPrivateKeyingMaterial[32] = {0x96, 0xBF, 0x85, 0x49, 0xC3, 0x79, 0xE4, 0x04, + * 0xED, 0xA1, 0x08, 0xA5, 0x51, 0xF8, 0x36, 0x23, + * 0x12, 0xD8, 0xD1, 0xB2, 0xA5, 0xFA, 0x57, 0x06, + * 0xE2, 0xCC, 0x22, 0x5C, 0xF6, 0xF9, 0x77, 0xC4}; + * uint8_t messageHash[32] = {0xA4,0x1A,0x41,0xA1,0x2A,0x79,0x95,0x48, + * 0x21,0x1C,0x41,0x0C,0x65,0xD8,0x13,0x3A, + * 0xFD,0xE3,0x4D,0x28,0xBD,0xD5,0x42,0xE4, + * 0xB6,0x80,0xCF,0x28,0x99,0xC8,0xA8,0xC4}; + * uint8_t r[32] = {0}; + * uint8_t s[32] = {0}; + * + * + * CryptoKey myPrivateKey; + * + * ECDSA_Handle ecdsaHandle; + * + * int_fast16_t operationResult; + * + * // Since we are using default ECDSA_Params, we just pass in NULL for that parameter. + * + * ecdsaHandle = ECDSA_open(0, NULL); + * + * // Since the ECDSA driver for CC27XX and CC35XX relies on one HW engine (the HSM) for all of its operations + * // If the HSM boot up sequence fails, ECDSA_open() will return NULL. + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey + * CryptoKeyPlaintextHSM_initKey(&myPrivateKey, + * myPrivateKeyingMaterial, + * sizeof(myPrivateKeyingMaterial)); + * + * // Initialize the operation + * // For CC27XX and CC35XX devices, you must specify the curveType instead of providing a pointer to the curve like + * // the case with other devices. + * ECDSA_OperationSign_init(&operationSign); + * operationSign.curveType = ECDSA_TYPE_SEC_P_256_R1; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.hash = messageHash; + * operationSign.r = r; + * operationSign.s = s; + * + * // Generate the signature + * operationResult = ECDSA_sign(ecdsaHandle, &operationSign); + * + * if (operationResult != ECDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * ## ECDSA sign with plaintext CryptoKeys # + * + * @code + * + * #include + * #include + * + * ... + * + * // This vector is taken from the NIST ST toolkit examples from ECDSA_Prime.pdf + * uint8_t myPrivateKeyingMaterial[32] = {0x96, 0xBF, 0x85, 0x49, 0xC3, 0x79, 0xE4, 0x04, + * 0xED, 0xA1, 0x08, 0xA5, 0x51, 0xF8, 0x36, 0x23, + * 0x12, 0xD8, 0xD1, 0xB2, 0xA5, 0xFA, 0x57, 0x06, + * 0xE2, 0xCC, 0x22, 0x5C, 0xF6, 0xF9, 0x77, 0xC4}; + * uint8_t messageHash[32] = {0xA4,0x1A,0x41,0xA1,0x2A,0x79,0x95,0x48, + * 0x21,0x1C,0x41,0x0C,0x65,0xD8,0x13,0x3A, + * 0xFD,0xE3,0x4D,0x28,0xBD,0xD5,0x42,0xE4, + * 0xB6,0x80,0xCF,0x28,0x99,0xC8,0xA8,0xC4}; + * uint8_t r[32] = {0}; + * uint8_t s[32] = {0}; + * + * + * CryptoKey myPrivateKey; + * + * ECDSA_Handle ecdsaHandle; + * + * int_fast16_t operationResult; + * + * // Since we are using default ECDSA_Params, + * // we just pass in NULL for that parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize myPrivateKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, + * myPrivateKeyingMaterial, + * sizeof(myPrivateKeyingMaterial)); + * + * // Initialize the operation + * ECDSA_OperationSign_init(&operationSign); + * operationSign.curve = &ECCParams_NISTP256; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.hash = messageHash; + * operationSign.r = r; + * operationSign.s = s; + * + * // Generate the signature + * operationResult = ECDSA_sign(ecdsaHandle, &operationSign); + * + * if (operationResult != ECDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * + * ## ECDSA verify with plaintext CryotoKeys # + * + * @code + * + * #include + * #include + * + * ... + * + * // This vector is taken from the NIST ST toolkit examples from + * // ECDSA_Prime.pdf + * // messageHash is the direct result of using SHA-256 on the string + * // 'Example of ECDSA with P-256' without the terminating zero. + * uint8_t theirPublicKeyingMaterial[65] = {0x04, + * // X + * 0xB7,0xE0,0x8A,0xFD,0xFE,0x94,0xBA,0xD3, + * 0xF1,0xDC,0x8C,0x73,0x47,0x98,0xBA,0x1C, + * 0x62,0xB3,0xA0,0xAD,0x1E,0x9E,0xA2,0xA3, + * 0x82,0x01,0xCD,0x08,0x89,0xBC,0x7A,0x19, + * //Y + * 0x36,0x03,0xF7,0x47,0x95,0x9D,0xBF,0x7A, + * 0x4B,0xB2,0x26,0xE4,0x19,0x28,0x72,0x90, + * 0x63,0xAD,0xC7,0xAE,0x43,0x52,0x9E,0x61, + * 0xB5,0x63,0xBB,0xC6,0x06,0xCC,0x5E,0x09}; + * uint8_t messageHash[32] = {0xA4,0x1A,0x41,0xA1,0x2A,0x79,0x95,0x48, + * 0x21,0x1C,0x41,0x0C,0x65,0xD8,0x13,0x3A, + * 0xFD,0xE3,0x4D,0x28,0xBD,0xD5,0x42,0xE4, + * 0xB6,0x80,0xCF,0x28,0x99,0xC8,0xA8,0xC4}; + * uint8_t r[32] = {0x2B,0x42,0xF5,0x76,0xD0,0x7F,0x41,0x65, + * 0xFF,0x65,0xD1,0xF3,0xB1,0x50,0x0F,0x81, + * 0xE4,0x4C,0x31,0x6F,0x1F,0x0B,0x3E,0xF5, + * 0x73,0x25,0xB6,0x9A,0xCA,0x46,0x10,0x4F}; + * uint8_t s[32] = {0xDC,0x42,0xC2,0x12,0x2D,0x63,0x92,0xCD, + * 0x3E,0x3A,0x99,0x3A,0x89,0x50,0x2A,0x81, + * 0x98,0xC1,0x88,0x6F,0xE6,0x9D,0x26,0x2C, + * 0x4B,0x32,0x9B,0xDB,0x6B,0x63,0xFA,0xF1}; + * + * + * CryptoKey theirPublicKey; + * + * ECDSA_Handle ecdsaHandle; + * + * int_fast16_t operationResult; + * + * ECDSA_OperationVerify operationVerify; + * + * // Since we are using default ECDSA_Params, we just pass in NULL for that + * // parameter. + * ecdsaHandle = ECDSA_open(0, NULL); + * + * if (!ecdsaHandle) { + * // Handle error + * } + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, + * theirPublicKeyingMaterial, + * sizeof(theirPublicKeyingMaterial)); + * + * ECDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_NISTP256; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.hash = messageHash; + * operationVerify.r = r; + * operationVerify.s = s; + * + * // Generate the keying material for myPublicKey and store it in + * // myPublicKeyingMaterial + * operationResult = ECDSA_verify(ecdsaHandle, &operationVerify); + * + * if (operationResult != ECDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * ## Using KeyStore for ECDSA Keys # + * + * @code + * + * // This example shows how to import persistent public key into KeyStore key and + * // how to use KeyStore public key to verify ECDSA signature + * KeyStore_PSA_KeyFileId publicKeyID; + * KeyStore_PSA_KeyAttributes pubKeyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * KeyStore_PSA_KeyType keyType = KEYSTORE_PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE; + * int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + * + * // Public key + * KeyStore_PSA_setKeyAlgorithm(&pubKeyAttributes, KEYSTORE_PSA_ALG_ECDSA); + * KeyStore_PSA_setKeyUsageFlags(&pubKeyAttributes, KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH); + * // Set key ID for persistent keys + * GET_KEY_ID(publicKeyID, KEYSTORE_PSA_KEY_ID_USER_MIN); + * KeyStore_PSA_setKeyLifetime(&pubKeyAttributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); + * // In this example, we assume public key to be stored is for NIST-P256 + * KeyStore_PSA_setKeyType(attributes, keyType | KEYSTORE_PSA_ECC_CURVE_SECP256R1); + * status = KeyStore_PSA_importKey(&pubKeyAttributes, + * theirPublicKeyingMaterial, + * sizeof(theirPublicKeyingMaterial), + * &publicKeyID); + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * while(1); // handle error + * } + * KeyStore_PSA_initKey(&theirPublicKey, publicKeyID, sizeof(theirPublicKeyingMaterial), NULL); + * + * + * // The application can continue to use the theirPublicKey as they would use + * // plaintext keys with ECDSA driver + * @endcode + * + */ + +#ifndef ti_drivers_ECDSA__include +#define ti_drivers_ECDSA__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common ECDSA status code reservation offset. + * ECDSA driver implementations should offset status codes with + * ECDSA_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECDSAXYZ_STATUS_ERROR0 ECDSA_STATUS_RESERVED - 0 + * #define ECDSAXYZ_STATUS_ERROR1 ECDSA_STATUS_RESERVED - 1 + * #define ECDSAXYZ_STATUS_ERROR2 ECDSA_STATUS_RESERVED - 2 + * @endcode + */ +#define ECDSA_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECDSA_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECDSA_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECDSA_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECDSA_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECDSA driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ +#define ECDSA_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The r value passed in is larger than the order of the curve. + * + * Signature components (r and s) must be integers in the interval [1, n - 1], + * where n is the order of the curve. + */ +#define ECDSA_STATUS_R_LARGER_THAN_ORDER (-3) + +/*! + * @brief The s value passed in is larger than the order of the curve. + * + * Signature components (r and s) must be integers in the interval [1, n - 1], + * where n is the order of the curve. + */ +#define ECDSA_STATUS_S_LARGER_THAN_ORDER (-4) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed + * upon curve. + */ +#define ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-5) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-6) + +/*! + * @brief The public key to verify against is the point at infinity. + * + * The point at infinity is not a valid input. + */ +#define ECDSA_STATUS_POINT_AT_INFINITY (-7) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECDSA_STATUS_CANCELED (-8) + +/*! + * @brief The provided CryptoKey does not match the expected size + * + * The driver expects the private key to have the same length as other curve + * parameters and the public key to have a length of twice that plus one. + * If the provided CryptoKeys for the public and private keys do not match this + * scheme, this error will be returned. + */ +#define ECDSA_STATUS_INVALID_KEY_SIZE (-10) + +/*! + * @brief The KeyStore module returned an error while importing/exporting key + * + * Functions return EDDSA_STATUS_KEYSTORE_ERROR if any KeyStore operation + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define ECDSA_STATUS_KEYSTORE_ERROR (-11) + +/*! + * @brief ECDSA Global configuration + * + * The ECDSA_Config structure contains a set of pointers used to characterize + * the ECDSA driver implementation. + * + * This structure needs to be defined before calling ECDSA_init() and it must + * not be changed thereafter. + * + * @sa ECDSA_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECDSA_Config; + +/*! + * @brief A handle that is returned from an ECDSA_open() call. + */ +typedef ECDSA_Config *ECDSA_Handle; + +/*! + * @brief The way in which ECDSA function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECDSA operations exhibit the specified return behavor. Functions that + * do not require significant computation and cannot offload that computation to + * a background threadbehave like regular functions. Which functions exhibit the + * specfied return behavior is implementation dependent. Specifically, a + * software-backed implementation run on the same CPU as the application will + * emulate the return behavior while not actually offloading the computation to + * the background thread. + * + * ECDSA functions exhibiting the specified return behavior have restrictions on + * the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |ECDSA_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECDSA_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECDSA_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + ECDSA_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECDSA operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDSA_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECDSA operation goes + * on in the background. ECDSA operation results are available + * after the function returns. + */ + ECDSA_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECDSA + * operation goes on in the background. ECDSA operation results + * are available after the function returns. + */ +} ECDSA_ReturnBehavior; + +#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX)) +/*! + * @brief Enum for the curve types supported by the driver. + */ +typedef enum +{ + ECDSA_TYPE_SEC_P_224_R1 = 1, + ECDSA_TYPE_SEC_P_256_R1 = 2, + ECDSA_TYPE_SEC_P_384_R1 = 3, + ECDSA_TYPE_SEC_P_521_R1 = 4, + ECDSA_TYPE_BRP_P_256_R1 = 5, + ECDSA_TYPE_BRP_P_384_R1 = 6, + ECDSA_TYPE_BRP_P_512_R1 = 7, +} ECDSA_CurveType; + +/*! + * @brief Enum for signature sizes in bits supported by the driver. + */ +typedef enum +{ + ECDSA_CURVE_LENGTH_192 = 192, + ECDSA_CURVE_LENGTH_224 = 224, + ECDSA_CURVE_LENGTH_256 = 256, + ECDSA_CURVE_LENGTH_384 = 384, + ECDSA_CURVE_LENGTH_512 = 512, + ECDSA_CURVE_LENGTH_521 = 521, +} ECDSA_CurveLength; + +/*! + * @brief Enum for the hash digest lengths in bits supported by the driver. + */ +typedef enum +{ + ECDSA_DIGEST_LENGTH_224 = 224, + ECDSA_DIGEST_LENGTH_256 = 256, + ECDSA_DIGEST_LENGTH_384 = 384, + ECDSA_DIGEST_LENGTH_512 = 512, +} ECDSA_DigestLength; +#endif + +/*! + * @brief Struct containing the parameters required for signing a message. + */ +typedef struct +{ +#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX)) + ECDSA_CurveType curveType; /*!< An ECDSA_CurveType value indicating which EC curve to use for the operation*/ +#endif + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters */ + const CryptoKey *myPrivateKey; /*!< A pointer to the private ECC key that will + * sign the hash of the message + */ + const uint8_t *hash; /*!< A pointer to the hash of the message in + * octet string format. + * Must be the same length as the other curve parameters. + */ + uint8_t *r; /*!< A pointer to the buffer the r component of + * the signature will be written to. + * Formatted in octet string format. + * Must be of the same length as other + * params of the curve used. + */ + uint8_t *s; /*!< A pointer to the buffer the s component of + * the signature will be written to. + * Must be of the same length as other + * params of the curve used. + */ +} ECDSA_OperationSign; + +/*! + * @brief Struct containing the parameters required for verifying a message. + */ +typedef struct +{ +#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX)) + ECDSA_CurveType curveType; +#else + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters */ +#endif + const CryptoKey *theirPublicKey; /*!< A pointer to the public key of the party + * that signed the hash of the message + */ + const uint8_t *hash; /*!< A pointer to the hash of the message in + * octet string format. + * Must be the same length as the other curve parameters. + */ + const uint8_t *r; /*!< A pointer to the r component of the received + * signature. + * Formatted in octet string format. + * Must be of the same length + * as other params of the curve used. + */ + const uint8_t *s; /*!< A pointer to the s component of the received + * signature. + * Formatted in octet string format. + * Must be of the same length + * as other params of the curve used. + */ +} ECDSA_OperationVerify; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union +{ + ECDSA_OperationSign *sign; /*!< A pointer to an ECDSA_OperationSign struct */ + ECDSA_OperationVerify *verify; /*!< A pointer to an ECDSA_OperationVerify struct */ +} ECDSA_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + ECDSA_OPERATION_TYPE_SIGN = 1, + ECDSA_OPERATION_TYPE_VERIFY = 2, +} ECDSA_OperationType; + +/*! + * @brief The definition of a callback function used by the ECDSA driver + * when used in ::ECDSA_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECDSA operation. + * + * @param returnStatus The result of the ECDSA operation. May contain an error + * code if the result is the point at infinity for + * example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECDSA_CallbackFxn)(ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType); + +/*! + * @brief ECDSA Parameters + * + * ECDSA Parameters are used to with the ECDSA_open() call. Default values for + * these parameters are set using ECDSA_Params_init(). + * + * @sa ECDSA_Params_init() + */ +typedef struct +{ + ECDSA_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling + * return behavior + */ + ECDSA_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before + * the operation fails and returns + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECDSA_Params; + +/*! + * @brief Default ECDSA_Params structure + * + * @sa ECDSA_Params_init() + */ +extern const ECDSA_Params ECDSA_defaultParams; + +/*! + * @brief This function initializes the ECDSA module. + * + * @pre The ECDSA_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECDSA driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECDSA_init(void); + +/*! + * @brief Function to close an ECDSA peripheral specified by the ECDSA handle + * + * @pre ECDSA_open() has to be called first. + * + * @param handle An ECDSA handle returned from ECDSA_open() + * + * @sa ECDSA_open() + */ +void ECDSA_close(ECDSA_Handle handle); + +/*! + * @brief This function opens a given ECDSA peripheral. + * + * @pre ECDSA controller has been initialized using ECDSA_init() + * + * @param index Logical peripheral number for the ECDSA indexed into + * the ECDSA_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECDSA_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa ECDSA_init() + * @sa ECDSA_close() + */ +ECDSA_Handle ECDSA_open(uint_least8_t index, const ECDSA_Params *params); + +/*! + * @brief Function to initialize the ECDSA_Params struct to its defaults + * + * @param params An pointer to ECDSA_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECDSA_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECDSA_Params_init(ECDSA_Params *params); + +/*! + * @brief Function to initialize an ECDSA_OperationSign struct to its defaults + * + * @param operation A pointer to ECDSA_OperationSign structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDSA_OperationSign_init(ECDSA_OperationSign *operation); + +/*! + * @brief Function to initialize an ECDSA_OperationSign struct to its defaults + * + * @param operation An pointer to ECDSA_OperationSign structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECDSA_OperationVerify_init(ECDSA_OperationVerify *operation); + +/*! + * @brief Signs a hashed message. + * + * ECDSA_sign() generates a signature (\c r, \c s) of a \c hash of a message. + * + * @pre ECDSA_OperationSign_init() must be called on \c operation first. + * The driver must have been opened by calling ECDSA_open() first. + * For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps, before using ECDSA_sign() and prior to the use of the Radio. + * 1. Read radio noise using RCL_AdcNoise_get_samples_blocking(). This RCL function must + * be called from a task context with interrupts enabled and therefore cannot be called + * by startup code. This must be executed prior to the use of the radio. + * 2. Condition the noise to seed the RNG using RNGLPF3RF_conditionNoiseToGenerateSeed(). + * 3. Initialize the RNG from the application with RNG_init() + * + * + * @param [in] handle An ECDSA handle returned from ECDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * @sa ECDSA_verify() + * + * @retval #ECDSA_STATUS_SUCCESS The operation succeeded. + * @retval #ECDSA_STATUS_ERROR The operation failed. + * @retval #ECDSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECDSA_STATUS_CANCELED The operation was canceled. + * @retval #ECDSA_STATUS_KEYSTORE_ERROR The keystore module returned an error. + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation); + +/*! + * @brief Verifies a received signature matches a hash and public key + * + * @pre ECDSA_OperationVerify_init() must be called on \c operation first. + * The driver must have been opened by calling ECDSA_open() first. + * + * @param [in] handle An ECDSA handle returned from ECDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * + * @sa ECDSA_sign() + * + * @retval #ECDSA_STATUS_SUCCESS The operation succeeded. + * @retval #ECDSA_STATUS_ERROR The operation failed. This is the return status if the signature + * did not match. + * @retval #ECDSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECDSA_STATUS_CANCELED The operation was canceled. + * @retval #ECDSA_STATUS_R_LARGER_THAN_ORDER The r value passed in is larger than the order of the curve. + * @retval #ECDSA_STATUS_S_LARGER_THAN_ORDER The s value passed in is larger than the order of the curve. + * @retval #ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the curve. + * @retval #ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME One of the public key coordinates is larger the the curve's + * prime. + * @retval #ECDSA_STATUS_POINT_AT_INFINITY The public key to verify against is the point at infinity. + * @retval #ECDSA_STATUS_KEYSTORE_ERROR The keystore module returned an error. + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation); + +/*! + * @brief Cancels an ongoing ECDSA operation. + * + * Asynchronously cancels an ECDSA operation. Only available when using + * ECDSA_RETURN_BEHAVIOR_CALLBACK or ECDSA_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be ECDSA_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECDSA_STATUS_SUCCESS The operation was canceled. + * @retval #ECDSA_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECDSA_cancelOperation(ECDSA_Handle handle); + +/** + * @brief Constructs a new ECDSA object + * + * Unlike #ECDSA_open(), #ECDSA_construct() does not require the hwAttrs and + * object to be allocated in a #ECDSA_Config array that is indexed into. + * Instead, the #ECDSA_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #ECDSA_Config describing the location of the object + * and hwAttrs. + * + * @param params #ECDSA_Params to configure the driver instance. + * + * @return Returns a #ECDSA_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +ECDSA_Handle ECDSA_construct(ECDSA_Config *config, const ECDSA_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECDSA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ECJPAKE.c b/simplelink_lpf2/source/ti/drivers/ECJPAKE.c new file mode 100644 index 00000000..d84e3bc1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECJPAKE.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECJPAKE.c ======== + * + * This file contains default values for the ECJPAKE_Params struct + * + */ + +#include +#include + +#include +#include +#include + +extern const ECJPAKE_Config ECJPAKE_config[]; +extern const uint_least8_t ECJPAKE_count; + +const ECJPAKE_Params ECJPAKE_defaultParams = { + .returnBehavior = ECJPAKE_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== ECJPAKE_Params_init ======== + */ +void ECJPAKE_Params_init(ECJPAKE_Params *params) +{ + *params = ECJPAKE_defaultParams; +} + +/* + * ======== ECJPAKE_open ======== + */ +__attribute__((weak)) ECJPAKE_Handle ECJPAKE_open(uint_least8_t index, const ECJPAKE_Params *params) +{ + DebugP_assert(index < ECJPAKE_count); + + ECJPAKE_Config *config = (ECJPAKE_Config *)&ECJPAKE_config[index]; + return ECJPAKE_construct(config, params); +} + +/* + * ======== ECJPAKE_OperationRoundOneGenerateKeys_init ======== + */ +void ECJPAKE_OperationRoundOneGenerateKeys_init(ECJPAKE_OperationRoundOneGenerateKeys *operation) +{ + memset(operation, 0x00, sizeof(ECJPAKE_OperationRoundOneGenerateKeys)); +} + +/* + * ======== ECJPAKE_OperationGenerateZKP_init ======== + */ +void ECJPAKE_OperationGenerateZKP_init(ECJPAKE_OperationGenerateZKP *operation) +{ + memset(operation, 0x00, sizeof(ECJPAKE_OperationGenerateZKP)); +} + +/* + * ======== ECJPAKE_OperationVerifyZKP_init ======== + */ +void ECJPAKE_OperationVerifyZKP_init(ECJPAKE_OperationVerifyZKP *operation) +{ + memset(operation, 0x00, sizeof(ECJPAKE_OperationVerifyZKP)); +} + +/* + * ======== ECJPAKE_OperationRoundTwoGenerateKeys_init ======== + */ +void ECJPAKE_OperationRoundTwoGenerateKeys_init(ECJPAKE_OperationRoundTwoGenerateKeys *operation) +{ + memset(operation, 0x00, sizeof(ECJPAKE_OperationRoundTwoGenerateKeys)); +} + +/* + * ======== ECJPAKE_OperationComputeSharedSecret_init ======== + */ +void ECJPAKE_OperationComputeSharedSecret_init(ECJPAKE_OperationComputeSharedSecret *operation) +{ + memset(operation, 0x00, sizeof(ECJPAKE_OperationComputeSharedSecret)); +} diff --git a/simplelink_lpf2/source/ti/drivers/ECJPAKE.h b/simplelink_lpf2/source/ti/drivers/ECJPAKE.h new file mode 100644 index 00000000..9120f9c5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ECJPAKE.h @@ -0,0 +1,1467 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ECJPAKE.h + * + * @brief TI Driver for Elliptic Curve Password Authenticated Key Exchange + * by Juggling. + * + * @anchor ti_drivers_ECJPAKE_Overview + * # Overview # + * Elliptic Curve Password Authenticated Key Exchange by Juggling (EC-JPAKE) + * is a key agreement scheme that establishes a secure channel over an insecure + * network. It only requires sharing a password offline and does not require + * public key infrastructure or trusted third parties such as certificate + * authorities. + * + * At the end of the EC-JPAKE scheme, both parties derive a shared secret + * from which a session key is derived. + * + * The scheme is symmetric. Both parties perform the exact same operations + * to end up with the shared secret. + * + * # Steps involved # + * Since the scheme is symmetric, the steps involved will be illustrated + * using Alice and Bob as relevant parties. + * + * -# Alice and Bob decide on some pre-shared secret, the password, and + * negotiate this through some offline means such as during commissioning. + * + * -# Alice generates private keys x1, x2, v1, and v2 uniformly at random from [1, n - 1], + * where n is the order of the curve. + * -# Alice generates public keys X1 = x1 * G, X2 = x2 * G, V1 = v1 * G, and V2 = v2 * G. + * -# Alice generates Zero-Knowledge Proofs (ZKPs) for (X1, x1) and (X2, x2). + * The required hash is computed by concatenating G, V, the public key + * the ZKP authenticates, and the UserID of the authenticator and hashing + * the new bitstring. The exact order and formatting of all parameters and + * any extra information such as length words must be agreed upon by both + * parties to yield the same result. + * -# Alice sends X1, X2, V1, V2, r1, r2, and her UserID to Bob. + * + * -# Bob generates private keys x3, x4, v3, and v4 uniformly at random from [1, n - 1], + * where n is the order of the curve. + * -# Bob generates public keys X3 = x3 * G, X4 = x4 * G, V3 = v3 * G, and V4 = v4 * G. + * -# Bob generates Zero-Knowledge Proofs (ZKPs) for (X3, x3) and (X4, x4). + * -# Bob sends X3, X4, V3, V4, r3, r4, and his UserID to Bob. + * + * -# Alice and Bob verify the other parties ZKPs and break off the scheme if they + * do not check out. + * + * -# Alice computes the new generator point G2 = (X1 + X3 + X4). + * -# Alice computes the combined private key x5 = x2 * s, where s is the pre-shared + * secret. + * -# Alice computes the combined public key X5 = x5 * G2. + * -# Alice computes a ZKP for (X5, x5) using G2 as the generator point of the ZKP. + * -# Alice sends X5, V5, r5, and her UserID to Bob. + * + * -# Bob computes the new generator point G3 = (X3 + X1 + X2). + * -# Bob computes the combined private key x6 = x4 * s, where s is the pre-shared + * secret. + * -# Bob computes the combined public key X6 = x6 * G3. + * -# Bob computes a ZKP for (X6, x6) using G3 as the generator point of the ZKP. + * -# Bob sends X6, V6, r6, and his UserID to Alice. + * + * -# Alice and Bob verify the other parties ZKPs and break off the scheme if they + * do not check out. This involves computing the other parties generator point. + * + * -# Alice computes shared secret K = (X6 - (X4 * x5)) * x2. + * + * -# Bob computes shared secret K = (X5 - (X2 * x6)) * x4. + * + * -# Alice and Bob each run K through a mutually agreed upon key derivation + * function to compute the symmetric session key. + * + * @anchor ti_drivers_ECJPAKE_Usage + * # Usage # + * + * ## Before starting an ECJPAKE operation # + * + * Before starting an ECJPAKE operation, the application must do the following: + * -# Call ECJPAKE_init() to initialize the driver + * -# Call ECJPAKE_Params_init() to initialize the ECJPAKE_Params to default values. + * -# Modify the ECJPAKE_Params as desired + * -# Call ECJPAKE_open() to open an instance of the driver + * + * ## Round one # + * -# Initialize the following private key CryptoKeys. + * Seed them with keying material uniformly drawn from [1, n - 1] + * - myPrivateKey1 + * - myPrivateKey2 + * - myPrivateV1 + * - myPrivateV2 + * -# Initialize the following blank public key CryptoKeys: + * - myPublicKey1 + * - myPublicKey2 + * - myPublicV1 + * - myPublicV2 + * - theirPublicKey1 + * - theirPublicKey2 + * - theirPublicV1 + * - theirPublicV2 + * -# Call ECJPAKE_roundOneGenerateKeys() to generate all round one keys as needed. + * -# Generate the hashes for the ZKPs using previously agreed upon formatting. + * Use the default generator point of the curve in the first round. + * -# Generate your two ZKPs by calling ECJPAKE_generateZKP() once per ZKP. + * -# Exchange public keys, UserIDs, and ZKP signatures. Write the received keying + * material into the relevant buffers or load them into key stores as specified + * by the CryptoKeys initialised earlier. + * -# Verify the other party's ZKPs after computing their ZKP hash by calling + * ECJPAKE_verifyZKP() once per ZKP. + * -# You can now let all V keys, myPrivateKey1, and all ZKP signatures go out of scope + * and re-use their memory. + * + * ## Round two # + * -# Initialize the following private key CryptoKeys. + * Seed myPrivateV with keying material uniformly drawn from [1, n - 1]. + * Initialise the preSharedSecret with the common keying material previously + * shared between you and the other party. + * - preSharedSecret + * - myCombinedPrivateKey + * -# Initialize the following blank public key CryptoKeys: + * - theirNewGenerator + * - myNewGenerator + * - myCombinedPublicKey + * - myPublicV + * -# Call ECJPAKE_roundTwoGenerateKeys() to generate the remaining round two keys. + * -# Generate the hash for your ZKP use myNewGenerator as your generator point. + * -# Exchange public keys, UserIDs, and ZKP signatures. Write the received keying + * material into the relevant buffers or load them into key stores as specified + * by the CryptoKeys initialised earlier. + * -# Verify the other party's ZKP after computing their ZKP hash by calling + * ECJPAKE_verifyZKP(). Use theirNewGenerator as the generator point for this + * ZKP. + * -# You can now let all keys and keying material but myCombinedPrivateKey, + * theirCombinedPublicKey, theirPublicKey2, and myPrivateKey2 go out of scope. + * + * ## Computing the shared secret # + * -# Initialize the following blank public key CryptoKey: + * - sharedSecret + * -# Call ECJPAKE_computeSharedSecret(). + * -# Run sharedSecret through a key derivation function to compute the shared + * symmetric session key. + * + * ## Key Formatting + * The ECJPAKE API expects the private and public keys to be formatted in octet + * string format. The details of octet string formatting can be found in + * SEC 1: Elliptic Curve Cryptography. + * + * Private keys and V's are formatted as big-endian integers of the same length + * as the curve length. + * + * Public keys, public V's, generator points, and shared secrets are points on + * an elliptic curve. These points can be expressed in several ways. + * This API uses points expressed in uncompressed affine coordinates by default. + * The octet string format requires a formatting byte in the first byte of the + * public key. When using uncompressed affine coordinates, this is the value + * 0x04. + * The point itself is stored as a concatenated array of X followed by Y. + * X and Y are big-endian. Some implementations do not require or yield + * the Y coordinate for ECJPAKE on certain curves. It is recommended that the full + * keying material buffer of twice the curve param length is used to facilitate + * code-reuse. Implementations that do not use the Y coordinate will zero-out + * the Y-coordinate whenever they write a point to the CryptoKey. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | Keying Material Array | Array Length | + * |--------------------|-----------------------|----------------------------| + * | Short Weierstrass | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Montgomery | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * | Edwards | [0x04, X, Y] | 1 + 2 * Curve Param Length | + * + * The r component of the ZKP signature, hash, and preSharedSecret also all + * use the octet string format. They are interpreted as big-endian integers. + * + * @anchor ti_drivers_ECJPAKE_Synopsis + * ## Synopsis + * + * @anchor ti_drivers_ECJPAKE_Synopsis_Code + * @code + * // Import ECJPAKE Driver definitions + * #include + * + * ECJPAKE_init(); + * + * // Since we are using default ECJPAKE_Params, we just pass in NULL for that parameter. + * ecjpakeHandle = ECJPAKE_open(0, NULL); + + * ECJPAKE_Handle handle = ECJPAKE_open(0, ¶ms); + * + * ECJPAKE_OperationRoundOneGenerateKeys operationRoundOneGenerateKeys; + * ECJPAKE_OperationRoundTwoGenerateKeys operationRoundTwoGenerateKeys; + * ECJPAKE_OperationGenerateZKP operationGenerateZKP; + * ECJPAKE_OperationVerifyZKP operationVerifyZKP; + * ECJPAKE_OperationComputeSharedSecret operationComputeSharedSecret; + * + * // Generate my round one keys + * ECJPAKE_OperationRoundOneGenerateKeys_init(&operationRoundOneGenerateKeys); + * operationRoundOneGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundOneGenerateKeys.myPrivateKey1 = &myPrivateCryptoKey1; + * operationRoundOneGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundOneGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundOneGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundOneGenerateKeys.myPrivateV1 = &myPrivateCryptoV1; + * operationRoundOneGenerateKeys.myPrivateV2 = &myPrivateCryptoV2; + * operationRoundOneGenerateKeys.myPublicV1 = &myPublicCryptoV1; + * operationRoundOneGenerateKeys.myPublicV2 = &myPublicCryptoV2; + * + * result = ECJPAKE_roundOneGenerateKeys(handle, &operationRoundOneGenerateKeys); + * + * // Generate hashes here + * + * // generate my round one ZKPs + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey1; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV1; + * operationGenerateZKP.hash = myHash1; + * operationGenerateZKP.r = myR1; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey2; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV2; + * operationGenerateZKP.hash = myHash2; + * operationGenerateZKP.r = myR2; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * // Do ZKP and key transmission here + * + * // Verify their round one ZKPs + * // Generate their hashes here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = NULL; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey1; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV1; + * operationVerifyZKP.hash = theirHash1; + * operationVerifyZKP.r = theirR1; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = NULL; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey2; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV2; + * operationVerifyZKP.hash = theirHash2; + * operationVerifyZKP.r = theirR2; + * + * result = ECJPAKE_verifyZKP(handle,&operationVerifyZKP); + * + * // Round two starts now + * + * // Generate my round two keys + * ECJPAKE_OperationRoundTwoGenerateKeys_init(&operationRoundTwoGenerateKeys); + * operationRoundTwoGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundTwoGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundTwoGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundTwoGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundTwoGenerateKeys.theirPublicKey1 = &theirPublicCryptoKey1; + * operationRoundTwoGenerateKeys.theirPublicKey2 = &theirPublicCryptoKey2; + * operationRoundTwoGenerateKeys.preSharedSecret = &preSharedSecretCryptoKey; + * operationRoundTwoGenerateKeys.theirNewGenerator = &theirGeneratorKey; + * operationRoundTwoGenerateKeys.myNewGenerator = &myGeneratorKey; + * operationRoundTwoGenerateKeys.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationRoundTwoGenerateKeys.myCombinedPublicKey = &myCombinedPublicKey; + * operationRoundTwoGenerateKeys.myPrivateV = &myPrivateCryptoV3; + * operationRoundTwoGenerateKeys.myPublicV = &myPublicCryptoV3; + * + * result = ECJPAKE_roundTwoGenerateKeys(handle, &operationRoundTwoGenerateKeys); + * + * // Generate my round two ZKP + * // Generate the round two hash here + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myCombinedPrivateKey; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV3; + * operationGenerateZKP.hash = myHash3; + * operationGenerateZKP.r = myR3; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * // Exchange keys and ZKPs again + * + * // Verify their second round ZKP + * // Generate their round two hash here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &theirGeneratorKey; + * operationVerifyZKP.theirPublicKey = &theirCombinedPublicKey; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV3; + * operationVerifyZKP.hash = theirHash3; + * operationVerifyZKP.r = theirR3; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * // Generate shared secret + * ECJPAKE_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationComputeSharedSecret.theirCombinedPublicKey = &theirCombinedPublicKey; + * operationComputeSharedSecret.theirPublicKey2 = &theirPublicCryptoKey2; + * operationComputeSharedSecret.myPrivateKey2 = &myPrivateCryptoKey2; + * operationComputeSharedSecret.sharedSecret = &sharedSecretCryptoKey; + * + * result = ECJPAKE_computeSharedSecret(handle, &operationComputeSharedSecret); + * + * // Close the driver + * ECJPAKE_close(handle); + * @endcode + * + * @anchor ti_drivers_ECJPAKE_Examples + * # Examples # + * + * ## Basic ECJPAKE exchange # + * + * @code + * + * #define NISTP256_CURVE_LENGTH_BYTES 32 + * #define OCTET_STRING_OFFSET 1 + * #define NISTP256_PRIVATE_KEY_LENGTH_BYTES NISTP256_CURVE_LENGTH_BYTES + * #define NISTP256_PUBLIC_KEY_LENGTH_BYTES (NISTP256_CURVE_LENGTH_BYTES * 2 + OCTET_STRING_OFFSET) + * + * // My fixed keying material + * uint8_t myPrivateKeyMaterial1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myPrivateKeyMaterial2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myPrivateVMaterial1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myPrivateVMaterial2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myPrivateVMaterial3[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myHash1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myHash2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myHash3[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * // My derived keying material + * uint8_t myR1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myR2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myR3[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myPublicKeyMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myPublicKeyMaterial2[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myPublicVMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myPublicVMaterial2[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myPublicVMaterial3[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myCombinedPublicKeyMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t myCombinedPrivateKeyMaterial1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t myGenerator[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * + * // Their fixed keying material + * uint8_t theirHash1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t theirHash2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t theirHash3[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * + * // Their derived keying material + * uint8_t theirR1[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t theirR2[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t theirR3[NISTP256_PRIVATE_KEY_LENGTH_BYTES]; + * uint8_t theirPublicKeyMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirPublicKeyMaterial2[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirPublicVMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirPublicVMaterial2[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirPublicVMaterial3[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirCombinedPublicKeyMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * uint8_t theirGenerator[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * + * // Shared secrets + * uint8_t preSharedSecretKeyingMaterial[NISTP256_PRIVATE_KEY_LENGTH_BYTES] = "This is our password"; + * uint8_t sharedSecretKeyingMaterial1[NISTP256_PUBLIC_KEY_LENGTH_BYTES]; + * + * // Pre-Shared Secret Key + * CryptoKey preSharedSecretCryptoKey; + * + * // Final shared secret keys + * CryptoKey sharedSecretCryptoKey; + * + * // My's keys + * CryptoKey myPrivateCryptoKey1; + * CryptoKey myPrivateCryptoKey2; + * CryptoKey myPrivateCryptoV1; + * CryptoKey myPrivateCryptoV2; + * CryptoKey myPrivateCryptoV3; + * CryptoKey myCombinedPrivateKey; + * + * CryptoKey myPublicCryptoKey1; + * CryptoKey myPublicCryptoKey2; + * CryptoKey myPublicCryptoV1; + * CryptoKey myPublicCryptoV2; + * CryptoKey myPublicCryptoV3; + * CryptoKey myCombinedPublicKey; + * CryptoKey myGeneratorKey; + * + * // Their's Keys + * CryptoKey theirPublicCryptoKey1; + * CryptoKey theirPublicCryptoKey2; + * CryptoKey theirPublicCryptoV1; + * CryptoKey theirPublicCryptoV2; + * CryptoKey theirPublicCryptoV3; + * CryptoKey theirCombinedPublicKey; + * CryptoKey theirGeneratorKey; + * + * // NISTP256 generator + * CryptoKeyPlaintext_initKey(NULL, ECCParams_NISTP256.generatorX, sizeof(ECCParams_NISTP256.length * 2)); + * + * // Pre-shared secret + * CryptoKeyPlaintext_initKey(&preSharedSecretCryptoKey, preSharedSecretKeyingMaterial, + sizeof(preSharedSecretKeyingMaterial)); + * + * // Final shared secret key + * CryptoKeyPlaintext_initKey(&sharedSecretCryptoKey, sharedSecretKeyingMaterial1, sizeof(sharedSecretKeyingMaterial1)); + * CryptoKeyPlaintext_initKey(&sharedSecretCryptoKey2, sharedSecretKeyingMaterial2, + sizeof(sharedSecretKeyingMaterial2)); + * + * + * // My keys + * + * // This example assumes that the private keying material buffers already + * // contains random bytes. Otherwise, we need to use a TRNG or DRBG to fill + * // them after initialising the CryptoKeys. + * CryptoKeyPlaintext_initKey(&myPrivateCryptoKey1, myPrivateKeyMaterial1, sizeof(myPrivateKeyMaterial1)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoKey2, myPrivateKeyMaterial2, sizeof(myPrivateKeyMaterial2)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV1, myPrivateVMaterial1, sizeof(myPrivateVMaterial1)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV2, myPrivateVMaterial2, sizeof(myPrivateVMaterial2)); + * CryptoKeyPlaintext_initKey(&myPrivateCryptoV3, myPrivateVMaterial3, sizeof(myPrivateVMaterial3)); + * + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoKey1, myPublicKeyMaterial1, sizeof(myPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoKey2, myPublicKeyMaterial2, sizeof(myPublicKeyMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV1, myPublicVMaterial1, sizeof(myPublicVMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV2, myPublicVMaterial2, sizeof(myPublicVMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&myPublicCryptoV3, myPublicVMaterial3, sizeof(myPublicVMaterial3)); + * CryptoKeyPlaintext_initBlankKey(&myCombinedPrivateKey, myCombinedPrivateKeyMaterial1, + sizeof(myCombinedPrivateKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myCombinedPublicKey, myCombinedPublicKeyMaterial1, + sizeof(myCombinedPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&myGeneratorKey, myGenerator, sizeof(myGenerator)); + * + * // Their keys + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoKey1, theirPublicKeyMaterial1, sizeof(theirPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoKey2, theirPublicKeyMaterial2, sizeof(theirPublicKeyMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV1, theirPublicVMaterial1, sizeof(theirPublicVMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV2, theirPublicVMaterial2, sizeof(theirPublicVMaterial2)); + * CryptoKeyPlaintext_initBlankKey(&theirPublicCryptoV3, theirPublicVMaterial3, sizeof(theirPublicVMaterial3)); + * CryptoKeyPlaintext_initBlankKey(&theirCombinedPublicKey, theirCombinedPublicKeyMaterial1, + sizeof(theirCombinedPublicKeyMaterial1)); + * CryptoKeyPlaintext_initBlankKey(&theirGeneratorKey, theirGenerator, sizeof(theirGenerator)); + * + * // Initial driver setup + * ECJPAKE_Params params; + * ECJPAKE_Params_init(¶ms); + * + * + * ECJPAKE_Handle handle = ECJPAKE_open(0, ¶ms); + * + * ECJPAKE_OperationRoundOneGenerateKeys operationRoundOneGenerateKeys; + * ECJPAKE_OperationRoundTwoGenerateKeys operationRoundTwoGenerateKeys; + * ECJPAKE_OperationGenerateZKP operationGenerateZKP; + * ECJPAKE_OperationVerifyZKP operationVerifyZKP; + * ECJPAKE_OperationComputeSharedSecret operationComputeSharedSecret; + * + * // Generate my round one keys + * ECJPAKE_OperationRoundOneGenerateKeys_init(&operationRoundOneGenerateKeys); + * operationRoundOneGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundOneGenerateKeys.myPrivateKey1 = &myPrivateCryptoKey1; + * operationRoundOneGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundOneGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundOneGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundOneGenerateKeys.myPrivateV1 = &myPrivateCryptoV1; + * operationRoundOneGenerateKeys.myPrivateV2 = &myPrivateCryptoV2; + * operationRoundOneGenerateKeys.myPublicV1 = &myPublicCryptoV1; + * operationRoundOneGenerateKeys.myPublicV2 = &myPublicCryptoV2; + * + * int_fast16_t result = ECJPAKE_roundOneGenerateKeys(handle, &operationRoundOneGenerateKeys); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Generate hashes here + * + * // generate my round one ZKPs + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey1; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV1; + * operationGenerateZKP.hash = myHash1; + * operationGenerateZKP.r = myR1; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myPrivateCryptoKey2; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV2; + * operationGenerateZKP.hash = myHash2; + * operationGenerateZKP.r = myR2; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Do ZKP and key transmission here + * + * // Verify their round one ZKPs + * // Generate their hashes here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = NULL; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey1; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV1; + * operationVerifyZKP.hash = theirHash1; + * operationVerifyZKP.r = theirR1; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = NULL; + * operationVerifyZKP.theirPublicKey = &theirPublicCryptoKey2; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV2; + * operationVerifyZKP.hash = theirHash2; + * operationVerifyZKP.r = theirR2; + * + * result = ECJPAKE_verifyZKP(handle,&operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Round two starts now + * + * // Generate my round two keys + * ECJPAKE_OperationRoundTwoGenerateKeys_init(&operationRoundTwoGenerateKeys); + * operationRoundTwoGenerateKeys.curve = &ECCParams_NISTP256; + * operationRoundTwoGenerateKeys.myPrivateKey2 = &myPrivateCryptoKey2; + * operationRoundTwoGenerateKeys.myPublicKey1 = &myPublicCryptoKey1; + * operationRoundTwoGenerateKeys.myPublicKey2 = &myPublicCryptoKey2; + * operationRoundTwoGenerateKeys.theirPublicKey1 = &theirPublicCryptoKey1; + * operationRoundTwoGenerateKeys.theirPublicKey2 = &theirPublicCryptoKey2; + * operationRoundTwoGenerateKeys.preSharedSecret = &preSharedSecretCryptoKey; + * operationRoundTwoGenerateKeys.theirNewGenerator = &theirGeneratorKey; + * operationRoundTwoGenerateKeys.myNewGenerator = &myGeneratorKey; + * operationRoundTwoGenerateKeys.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationRoundTwoGenerateKeys.myCombinedPublicKey = &myCombinedPublicKey; + * operationRoundTwoGenerateKeys.myPrivateV = &myPrivateCryptoV3; + * operationRoundTwoGenerateKeys.myPublicV = &myPublicCryptoV3; + * + * result = ECJPAKE_roundTwoGenerateKeys(handle, &operationRoundTwoGenerateKeys); + * + * // Generate my round two ZKP + * // Generate the round two hash here + * + * ECJPAKE_OperationGenerateZKP_init(&operationGenerateZKP); + * operationGenerateZKP.curve = &ECCParams_NISTP256; + * operationGenerateZKP.myPrivateKey = &myCombinedPrivateKey; + * operationGenerateZKP.myPrivateV = &myPrivateCryptoV3; + * operationGenerateZKP.hash = myHash3; + * operationGenerateZKP.r = myR3; + * + * result = ECJPAKE_generateZKP(handle, &operationGenerateZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Exchange keys and ZKPs again + * + * // Verify their second round ZKP + * // Generate their round two hash here + * + * ECJPAKE_OperationVerifyZKP_init(&operationVerifyZKP); + * operationVerifyZKP.curve = &ECCParams_NISTP256; + * operationVerifyZKP.theirGenerator = &theirGeneratorKey; + * operationVerifyZKP.theirPublicKey = &theirCombinedPublicKey; + * operationVerifyZKP.theirPublicV = &theirPublicCryptoV3; + * operationVerifyZKP.hash = theirHash3; + * operationVerifyZKP.r = theirR3; + * + * result = ECJPAKE_verifyZKP(handle, &operationVerifyZKP); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * + * // Generate shared secret + * ECJPAKE_OperationComputeSharedSecret_init(&operationComputeSharedSecret); + * operationComputeSharedSecret.curve = &ECCParams_NISTP256; + * operationComputeSharedSecret.myCombinedPrivateKey = &myCombinedPrivateKey; + * operationComputeSharedSecret.theirCombinedPublicKey = &theirCombinedPublicKey; + * operationComputeSharedSecret.theirPublicKey2 = &theirPublicCryptoKey2; + * operationComputeSharedSecret.myPrivateKey2 = &myPrivateCryptoKey2; + * operationComputeSharedSecret.sharedSecret = &sharedSecretCryptoKey; + * + * result = ECJPAKE_computeSharedSecret(handle, &operationComputeSharedSecret); + * + * if (result != ECJPAKE_STATUS_SUCCESS) { + * while(1); + * } + * + * // Run sharedSecretCryptoKey through a key derivation function and + * // confirm to the other party that we have derived the same key + * + * + * @endcode + * + * ## Using KeyStore for ECJPAKE Keys # + * + * @code + * + * // This example shows how to import presharedsecret as a KeyStore key and + * // how to use KeyStore to store the newly generated sharedsecrets from ECJPAKE + * KeyStore_PSA_KeyAttributes presharedsecretKeyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * KeyStore_PSA_KeyFileId presharedsecretKeyID; + * KeyStore_PSA_KeyAttributes sharedsecretKeyAttributes1 = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * KeyStore_PSA_KeyAttributes sharedsecretKeyAttributes2 = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * KeyStore_PSA_KeyFileId privateKeyID; + * KeyStore_PSA_KeyFileId sharedsecretKeyID1; + * int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + * + * // Pre-shared secret + * KeyStore_PSA_setKeyUsageFlags(&presharedsecretKeyAttributes, KEYSTORE_PSA_KEY_USAGE_DERIVE); + * KeyStore_PSA_setKeyAlgorithm(&presharedsecretKeyAttributes, KEYSTORE_PSA_ALG_PAKE); + * KeyStore_PSA_setKeyLifetime(&priKeyAttributes, KEYSTORE_PSA_KEY_LIFETIME_VOLATILE); + * GET_KEY_ID(presharedsecretKeyID, 0); + * status = KeyStore_PSA_importKey(&presharedsecretKeyAttributes, + * preSharedSecretKeyingMaterial, + * sizeof(preSharedSecretKeyingMaterial), + * &presharedsecretKeyID); + * if (status == KEYSTORE_PSA_STATUS_SUCCESS) + * { + * while(1); // handle error + * } + * KeyStore_PSA_initKey(&preSharedSecretCryptoKey, presharedsecretKeyID, preSharedSecretLength, NULL); + * + * // Final computed shared secrets + * KeyStore_PSA_setKeyUsageFlags(&sharedsecretKeyAttributes1, KEYSTORE_PSA_KEY_USAGE_DERIVE); + * KeyStore_PSA_setKeyAlgorithm(&sharedsecretKeyAttributes1, KEYSTORE_PSA_ALG_PAKE); + * KeyStore_PSA_setKeyLifetime(&sharedsecretKeyAttributes1, KEYSTORE_PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE | + * KEYSTORE_PSA_ECC_CURVE_SECP256R1); + * GET_KEY_ID(sharedsecretKeyID1, 0); + * KeyStore_PSA_initBlankKey(&sharedSecretCryptoKey, sharedsecretKeyID1, preSharedSecretLength, + * sharedsecretKeyAttributes1); + * + * // The application can continue to use the sharedSecretCryptoKey and preSharedSecretCryptoKey as they would + * // use with plaintext keys with ECJPAKE driver + * @endcode + * + */ + +#ifndef ti_drivers_ECJPAKE__include +#define ti_drivers_ECJPAKE__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common ECJPAKE status code reservation offset. + * ECJPAKE driver implementations should offset status codes with + * ECJPAKE_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define ECJPAKEXYZ_STATUS_ERROR0 ECJPAKE_STATUS_RESERVED - 0 + * #define ECJPAKEXYZ_STATUS_ERROR1 ECJPAKE_STATUS_RESERVED - 1 + * #define ECJPAKEXYZ_STATUS_ERROR2 ECJPAKE_STATUS_RESERVED - 2 + * @endcode + */ +#define ECJPAKE_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return ECJPAKE_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ECJPAKE_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECJPAKE_STATUS_ERROR if the function was not executed + * successfully. + */ +#define ECJPAKE_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * ECJPAKE driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ECJPAKE_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief The public key of the other party is not valid. + * + * The public key received from the other party is not valid. + */ +#define ECJPAKE_STATUS_INVALID_PUBLIC_KEY (-3) + +/*! + * @brief The public key of the other party does not lie upon the curve. + * + * The public key received from the other party does not lie upon the agreed upon + * curve. + */ +#define ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-4) + +/*! + * @brief A coordinate of the public key of the other party is too large. + * + * A coordinate of the public key received from the other party is larger than + * the prime of the curve. This implies that the point was not correctly + * generated on that curve. + */ +#define ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME (-5) + +/*! + * @brief The result of the operation is the point at infinity. + * + * The operation yielded the point at infinity on this curve. This point is + * not permitted for further use in ECC operations. + */ +#define ECJPAKE_STATUS_POINT_AT_INFINITY (-6) + +/*! + * @brief The private key passed into the the call is invalid. + * + * Private keys must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECJPAKE_STATUS_INVALID_PRIVATE_KEY (-7) + +/*! + * @brief The private v passed into the the call is invalid. + * + * Private v must be integers in the interval [1, n - 1], where n is the + * order of the curve. + */ +#define ECJPAKE_STATUS_INVALID_PRIVATE_V (-8) + +/*! + * @brief The ongoing operation was canceled. + */ +#define ECJPAKE_STATUS_CANCELED (-9) + +/*! + * @brief A provided output key was not initialized as blank. + */ +#define ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK (-10) + +/*! + * @brief KeyStore operation within ECJPAKE failed + */ +#define ECJPAKE_STATUS_KEYSTORE_ERROR (-11) + +/*! + * @brief ECJPAKE operation not supported + */ +#define ECJPAKE_STATUS_NOT_SUPPORTED (-12) + +/*! + * @brief ECJPAKE Global configuration + * + * The ECJPAKE_Config structure contains a set of pointers used to characterize + * the ECJPAKE driver implementation. + * + * This structure needs to be defined before calling ECJPAKE_init() and it must + * not be changed thereafter. + * + * @sa ECJPAKE_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} ECJPAKE_Config; + +/*! + * @brief A handle that is returned from an ECJPAKE_open() call. + */ +typedef ECJPAKE_Config *ECJPAKE_Handle; + +/*! + * @brief The way in which ECJPAKE function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all ECJPAKE operations exhibit the specified return behavor. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specfied return behavior is + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * ECJPAKE functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |----------------------------------|-------|-------|-------| + * |ECJPAKE_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |ECJPAKE_RETURN_BEHAVIOR_BLOCKING | X | | | + * |ECJPAKE_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + ECJPAKE_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECJPAKE operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECJPAKE_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECJPAKE operation goes + * on in the background. ECJPAKE operation results are available + * after the function returns. + */ + ECJPAKE_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECJPAKE + * operation goes on in the background. ECJPAKE operation results + * are available after the function returns. + */ +} ECJPAKE_ReturnBehavior; + +/*! + * @brief Struct containing the parameters required to generate the first round of keys. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myPrivateKey1; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + const CryptoKey *myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + CryptoKey *myPublicKey1; /*!< A pointer to the blank public key of \c + * myPrivateKey1. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + CryptoKey *myPublicKey2; /*!< A pointer to the blank public key of \c + * myPrivateKey2. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + const CryptoKey *myPrivateV1; /*!< A pointer to a private ECC key used in the + * first Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + const CryptoKey *myPrivateV2; /*!< A pointer to a private ECC key used in the + * second Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey *myPublicV1; /*!< A pointer to the blank public key of \c + * myPrivateV1. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ + CryptoKey *myPublicV2; /*!< A pointer to the blank public key of \c + * myPrivateV2. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ +} ECJPAKE_OperationRoundOneGenerateKeys; + +/*! + * @brief Struct containing the parameters required to generate a ZKP. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myPrivateKey; /*!< A pointer to a private ECC key to be signed. Must + * be of the same length as other params + * of the curve used. + */ + const CryptoKey *myPrivateV; /*!< A pointer to a private ECC key that will be + * used only to generate a ZKP signature. + * Must be of the same length as other params + * of the curve used. + */ + const uint8_t *hash; /*!< A pointer to the hash of the message. + * Must be of the same length as other params + * of the curve used. + */ + uint8_t *r; /*!< A pointer to where the r component of the + * ZKP will be written to. + */ +} ECJPAKE_OperationGenerateZKP; + +/*! + * @brief Struct containing the parameters required to verify a ZKP. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *theirGenerator; /*!< A pointer to a CryptoKey describing the generator point + * to be used. In the first round, this will + * be the default generator of the curve. + * In the second round, this parameter is + * computed by ECJPAKE_roundTwoGenerateKeys(). + * + * Formatted as a public key. If NULL, default + * generator point from @c curve is used. + */ + const CryptoKey *theirPublicKey; /*!< A pointer to a CryptoKey describing the public key + * received from the other party that the + * ZKP to be verified supposedly signed. + */ + const CryptoKey *theirPublicV; /*!< A pointer to a CryptoKey describing the public V of the + * ZKP. Received from the other party. + */ + const uint8_t *hash; /*!< A pointer to the hash of the ZKP generated as the + * other party generated it to compute r. + */ + const uint8_t *r; /*!< A pointer to a R component of the ZKP signature. Received + * from the other party. + */ +} ECJPAKE_OperationVerifyZKP; + +/*! + * @brief Struct containing the parameters required to generate the second round keys. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey *myPublicKey1; /*!< A pointer to the public key of + * myPrivateKey1. Generated in round one. + */ + const CryptoKey *myPublicKey2; /*!< A pointer to the second public key. + * Generated in round one. + */ + const CryptoKey *theirPublicKey1; /*!< A pointer to a CryptoKey describing the first public key + * received from the other party. + */ + const CryptoKey *theirPublicKey2; /*!< A pointer to a CryptoKey describing the second public key + * received from the other party. + */ + const CryptoKey *preSharedSecret; /*!< A pointer to a CryptoKey describing the secret shared between + * the two parties prior to starting the scheme. + * This exchange would have happened through some + * offline commissioning scheme most likely. + * The driver expects an integer of the same length + * as the curve parameters of the curve in use as + * keying material even if the original pre-shared + * secret is shorter than this length. + */ + CryptoKey *theirNewGenerator; /*!< A pointer to a blank CryptoKey describing the generator point + * used by the other party in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + * Formatted as a public key. + */ + CryptoKey *myNewGenerator; /*!< A pointer to a blank CryptoKey describing the generator point + * used by the application in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + * Formatted as a public key. + */ + CryptoKey *myCombinedPrivateKey; /*!< A pointer to a blank private ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myPrivateKey2 by \c preSharedSecret. + */ + CryptoKey *myCombinedPublicKey; /*!< A pointer to a blank public ECC key. Result of multiplying + * \c myCombinedPrivateKey by \c myNewGenerator. + */ + const CryptoKey *myPrivateV; /*!< A pointer to a private ECC key used in the + * only second-round Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey *myPublicV; /*!< A pointer to the blank public key of \c + * myPrivateV. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ +} ECJPAKE_OperationRoundTwoGenerateKeys; + +/*! + * @brief Struct containing the parameters required to compute the shared secret. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey *myCombinedPrivateKey; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey *theirCombinedPublicKey; /*!< A pointer to a the second public key + * received from the other party. + */ + const CryptoKey *theirPublicKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myPrivateKey2 by \c preSharedSecret. + */ + const CryptoKey *myPrivateKey2; /*!< A pointer to a combined public key received in the second + * round and verified by the application against + * the second round ZKP signature. + */ + CryptoKey *sharedSecret; /*!< A pointer to a blank CryptoKey used to store + the shared secret that is identical between both + * parties. Formatted as a public key. + */ +} ECJPAKE_OperationComputeSharedSecret; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union +{ + ECJPAKE_OperationRoundOneGenerateKeys *generateRoundOneKeys; /*!< A pointer to an + ECJPAKE_OperationRoundOneGenerateKeys struct */ + ECJPAKE_OperationGenerateZKP *generateZKP; /*!< A pointer to an ECJPAKE_OperationGenerateZKP struct */ + ECJPAKE_OperationVerifyZKP *verifyZKP; /*!< A pointer to an ECJPAKE_OperationVerifyZKP struct */ + ECJPAKE_OperationRoundTwoGenerateKeys *generateRoundTwoKeys; /*!< A pointer to an + ECJPAKE_OperationRoundTwoGenerateKeys struct */ + ECJPAKE_OperationComputeSharedSecret *computeSharedSecret; /*!< A pointer to an ECJPAKE_OperationComputeSharedSecret + struct */ +} ECJPAKE_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + ECJPAKE_OPERATION_TYPE_ROUND_ONE_GENERATE_KEYS = 1, + ECJPAKE_OPERATION_TYPE_GENERATE_ZKP = 2, + ECJPAKE_OPERATION_TYPE_VERIFY_ZKP = 3, + ECJPAKE_OPERATION_TYPE_ROUND_TWO_GENERATE_KEYS = 4, + ECJPAKE_OPERATION_TYPE_COMPUTE_SHARED_SECRET = 5, +} ECJPAKE_OperationType; + +/*! + * @brief The definition of a callback function used by the ECJPAKE driver + * when used in ::ECJPAKE_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the ECJPAKE operation. + * + * @param returnStatus The result of the ECJPAKE operation. May contain an error code + * if the result is the point at infinity for example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through /c operation. + */ +typedef void (*ECJPAKE_CallbackFxn)(ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType); + +/*! + * @brief ECJPAKE Parameters + * + * ECJPAKE Parameters are used to with the ECJPAKE_open() call. Default values for + * these parameters are set using ECJPAKE_Params_init(). + * + * @sa ECJPAKE_Params_init() + */ +typedef struct +{ + ECJPAKE_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECJPAKE_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before the operation fails + * and returns + */ + void *custom; /*!< Custom argument used by driver + * implementation + */ +} ECJPAKE_Params; + +/*! + * @brief This function initializes the ECJPAKE module. + * + * @pre The ECJPAKE_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other ECJPAKE driver APIs. This function call does not modify any + * peripheral registers. + */ +void ECJPAKE_init(void); + +/*! + * @brief Function to initialize an ECJPAKE_OperationRoundOneGenerateKeys struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationRoundOneGenerateKeys structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationRoundOneGenerateKeys_init(ECJPAKE_OperationRoundOneGenerateKeys *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationGenerateZKP struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationGenerateZKP structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationGenerateZKP_init(ECJPAKE_OperationGenerateZKP *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationVerifyZKP struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationVerifyZKP structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationVerifyZKP_init(ECJPAKE_OperationVerifyZKP *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationRoundTwoGenerateKeys struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationRoundTwoGenerateKeys structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationRoundTwoGenerateKeys_init(ECJPAKE_OperationRoundTwoGenerateKeys *operation); + +/*! + * @brief Function to initialize an ECJPAKE_OperationComputeSharedSecret struct to its defaults + * + * @param operation A pointer to ECJPAKE_OperationComputeSharedSecret structure for + * initialization + * + * Defaults values are all zeros. + */ +void ECJPAKE_OperationComputeSharedSecret_init(ECJPAKE_OperationComputeSharedSecret *operation); + +/*! + * @brief Function to close an ECJPAKE peripheral specified by the ECJPAKE handle + * + * @pre ECJPAKE_open() has to be called first. + * + * @param handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @sa ECJPAKE_open() + */ +void ECJPAKE_close(ECJPAKE_Handle handle); + +/*! + * @brief This function opens a given ECJPAKE peripheral. + * + * @pre ECJPAKE controller has been initialized using ECJPAKE_init() + * + * @param index Logical peripheral number for the ECJPAKE indexed into + * the ECJPAKE_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An ECJPAKE_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa ECJPAKE_init() + * @sa ECJPAKE_close() + */ +ECJPAKE_Handle ECJPAKE_open(uint_least8_t index, const ECJPAKE_Params *params); + +/*! + * @brief Function to initialize the ECJPAKE_Params struct to its defaults + * + * @param params An pointer to ECJPAKE_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = ECJPAKE_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void ECJPAKE_Params_init(ECJPAKE_Params *params); + +/*! + * @brief Generates all public and private keying material for the first round of + * the EC-JPAKE scheme. + * + * This function generates all public and private keying material required for + * the first round of the EC-JPAKE scheme. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationRoundOneGenerateKeys_init() on /c operation. + * + * @post Generate the two sets of hashes and ZKPs for the two public/private key pairs. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_POINT_AT_INFINITY The computed public key is the point at infinity. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_KEY The private key passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_V The private v passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_KEYSTORE_ERROR The keystore operation to retrieve or store the keys failed. + * @retval #ECJPAKE_STATUS_NOT_SUPPORTED The driver does not support persistent keystore keys. + * + */ +int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundOneGenerateKeys *operation); + +/*! + * @brief Generates the \c r component of a Schnorr Zero-Knowledge Proof (ZKP) signature. + * + * This function generates the \c r component of a ZKP using the hash and private + * keys. The hash must be computed prior. + * This function does not compute the hash for the application. There is no strictly + * defined bit-level implementation guideline for generating the hash in the EC-JPAKE + * scheme. Hence, interoperability could not be guaranteed between different EC-JPAKE + * implementations. Usually, the hash will be a concatenation of the public V, public + * key, generator point, and user ID. There may be other components such as length + * fields mixed in. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre If in round one, ECJPAKE_roundOneGenerateKeys() must be called prior. + * Else, ECJPAKE_roundTwoGenerateKeys() must be called prior. The hash + * must also have been computed prior to calling this function. + * Call ECJPAKE_OperationGenerateZKP_init() on /c operation. + * + * + * @post Send all ZKP signatures (\c r, public V, user ID) together with the + * public keys to the other party. + * + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_KEYSTORE_ERROR The keystore operation to retrieve or store the keys failed. + */ +int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP *operation); + +/*! + * @brief Verifies a Schnorr Zero-Knowledge Proof (ZKP) signature. + * + * This function computes if a received Schnorr ZKP correctly verifies + * a received public key. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Receive the relevant ZKP signature parameters. Compute the hash. + * If in the second round, compute the generator first by calling + * ECJPAKE_roundTwoGenerateKeys(). + * Call ECJPAKE_OperationVerifyZKP_init() on /c operation. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. Signature did not verify correctly. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again + * later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the + * curve. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME A coordinate of the public key of the other party is too + * large. + * @retval #ECJPAKE_STATUS_KEYSTORE_ERROR The keystore operation to retrieve or store the keys failed. + */ +int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP *operation); + +/*! + * @brief Generates all public and private keying material for the first round of + * the EC-JPAKE scheme. + * + * This function generates all public and private keying material required for + * the first round of the EC-JPAKE scheme. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationRoundTwoGenerateKeys_init() on /c operation. + * + * @post Generate the hash and ZKP signature for the second round public/private key. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_KEY The private key passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_INVALID_PRIVATE_V The private v passed into the the call is invalid. + * @retval #ECJPAKE_STATUS_KEYSTORE_ERROR The keystore operation to retrieve or store the keys failed. + * @retval #ECJPAKE_STATUS_NOT_SUPPORTED The driver does not support persistent keystore keys. + */ +int_fast16_t ECJPAKE_roundTwoGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundTwoGenerateKeys *operation); + +/*! + * @brief Computes the shared secret. + * + * This function computes the shared secret between both parties. The shared + * secret is a point on the elliptic curve and is used to further derive the + * symmetric session key via a key derivation function. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Call ECJPAKE_OperationComputeSharedSecret_init() on /c operation. + * + * @post The shared secret must be processed by a key derivation function to + * compute the symmetric session key. It is recommended that the two parties + * prove to each other that they are in posession of the symmetric session + * key. While this should be implied by the successful verification of + * the three ZKPs in the scheme, it is nonetheless good practice. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_KEYSTORE_ERROR The keystore operation to retrieve or store the keys failed. + * @retval #ECJPAKE_STATUS_NOT_SUPPORTED The driver does not support persistent keystore keys. + */ +int_fast16_t ECJPAKE_computeSharedSecret(ECJPAKE_Handle handle, ECJPAKE_OperationComputeSharedSecret *operation); + +/*! + * @brief Cancels an ongoing ECJPAKE operation. + * + * Asynchronously cancels an ECJPAKE operation. Only available when using + * ECJPAKE_RETURN_BEHAVIOR_CALLBACK or ECJPAKE_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occured. The + * return status code of the operation will be ECJPAKE_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation was canceled. + * @retval #ECJPAKE_STATUS_ERROR The operation was not canceled. There may be no operation to cancel. + */ +int_fast16_t ECJPAKE_cancelOperation(ECJPAKE_Handle handle); + +/** + * @brief Constructs a new ECJPAKE object + * + * Unlike #ECJPAKE_open(), #ECJPAKE_construct() does not require the hwAttrs and + * object to be allocated in a #ECJPAKE_Config array that is indexed into. + * Instead, the #ECJPAKE_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #ECJPAKE_Config describing the location of the object and hwAttrs. + * + * @param params #ECJPAKE_Params to configure the driver instance. + * + * @return Returns a #ECJPAKE_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +ECJPAKE_Handle ECJPAKE_construct(ECJPAKE_Config *config, const ECJPAKE_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ECJPAKE__include */ diff --git a/simplelink_lpf2/source/ti/drivers/EDDSA.c b/simplelink_lpf2/source/ti/drivers/EDDSA.c new file mode 100644 index 00000000..f2691a19 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/EDDSA.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== EDDSA.c ======== + * + * This file contains default values for the EDDSA_Params struct + * + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const EDDSA_Config EDDSA_config[]; +extern const uint_least8_t EDDSA_count; + +const EDDSA_Params EDDSA_defaultParams = { + .returnBehavior = EDDSA_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== EDDSA_Params_init ======== + */ +void EDDSA_Params_init(EDDSA_Params *params) +{ + *params = EDDSA_defaultParams; +} + +/* + * ======== EDDSA_open ======== + */ +__attribute__((weak)) EDDSA_Handle EDDSA_open(uint_least8_t index, const EDDSA_Params *params) +{ + DebugP_assert(index < EDDSA_count); + + EDDSA_Config *config = (EDDSA_Config *)&EDDSA_config[index]; + return (EDDSA_construct(config, params)); +} + +/* + * ======== EDDSA_OperationGeneratePublicKey_init ======== + */ +void EDDSA_OperationGeneratePublicKey_init(EDDSA_OperationGeneratePublicKey *operation) +{ + memset(operation, 0x00, sizeof(EDDSA_OperationGeneratePublicKey)); +} + +/* + * ======== EDDSA_OperationSign_init ======== + */ +void EDDSA_OperationSign_init(EDDSA_OperationSign *operation) +{ + memset(operation, 0x00, sizeof(EDDSA_OperationSign)); +} + +/* + * ======== EDDSA_OperationVerify_init ======== + */ +void EDDSA_OperationVerify_init(EDDSA_OperationVerify *operation) +{ + memset(operation, 0x00, sizeof(EDDSA_OperationVerify)); +} diff --git a/simplelink_lpf2/source/ti/drivers/EDDSA.h b/simplelink_lpf2/source/ti/drivers/EDDSA.h new file mode 100644 index 00000000..236cd44e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/EDDSA.h @@ -0,0 +1,1021 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! + * @file EDDSA.h + * + * @brief TI Driver for Edwards Curve Digital Signature Algorithm. + * + * + * @anchor ti_drivers_EDDSA_Overview + * # Overview # + * + * The Edwards Curve Digital Signature Algorithm (EdDSA) is a message + * authentication scheme between two parties based on operation on Edwards + * curves over finite fields. This driver supports the PureEdDSA scheme + * for Edwards curve Ed25519 as is described in RFC 8032: + * https://tools.ietf.org/html/rfc8032 . EdDSA variants, such as + * Ed25519ph or Ed25519ctx are currently not supported. + * + * Signing a message with EdDSA proves to the recipient that the sender of + * the message is in possession of the private key corresponding to the + * transmitted public key used during verification. + * For most practical systems, this ensures message authentication and + * integrity. + * + * # Steps involved # + * - Public Key Generation. The sender generates an EdDSA private-public + * keypair with private key k and public key A. For Ed25519, these are + * 32 bytes in little endian. The private key k comes from the DRBG. + * This private key is hashed, pruned (clear bits 0,1,2,255 and set bit + * 254), and used as a scalar to generate public key A. + * - Signature Generation. The sender hashes part of the private key + * k and message to be signed M. This result is used as a scalar to + * generate EdDSA signature component R which is a point on Ed25519. + * The signature component R, public key A, and message M are hashed + * to find a value that is used to generate the EdDSA signature + * component S which is a scalar. The signature for message M is {R,S}. + * - Signature Verification. The recipient receives signature {R,S}. The + * scalar S value is checked to be less than the order of the Edwards curve. + * The signature component R, public key A, and message M are hashed to + * find a scalar to recalculate R. The recipient accepts the signature + * if the received and calculated R match. Otherwise, they reject the + * signature. + * + * @note From here, we use EDDSA rather than EdDSA to be consistent with + * driver naming conventions. + * + * @anchor ti_drivers_EDDSA_Usage + * # Usage # + * + * ## Before starting an EDDSA operation # + * + * Before starting an EDDSA operation, the application must do the following: + * - Call EDDSA_init() to initialize the driver + * - Call EDDSA_Params_init() to initialize the EDDSA_Params to default + * values. + * - Modify the EDDSA_Params as desired + * - Call EDDSA_open() to open an instance of the driver + * + * ## Generating an Ed25519 Public Key # + * To generate an Ed25519 public key, the application must do the following: + * - Initialize an EDDSA_OperationGeneratePublicKey struct by calling + * EDDSA_OperationGeneratePublicKey_init(). + * - Initialize the public key CryptoKey. + * CryptoKeys are opaque data structures and representations of keying + * material and its storage. + * Depending on how the keying material is stored (RAM or flash, key store), + * the CryptoKey must be initialized differently. + * The EDDSA API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of + * CryptoKey. + * Devices without a key store will not support CryptoKeys with keying + * material stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Initialize the private key CryptoKey and set its value as a random or + * selected 32-byte value + * - Call EDDSA_operationGeneratePublicKey(). The public key + * information will be written to the buffers provided in the function call. + * myPublicKey is the public key A generated from part of a hash of the + * private key. + * Ensure the return value is EDDSA_STATUS_SUCCESS. + * + * + * ## Signing a message # + * To sign a message using Ed25519, the application must do the following: + * - Initialize an EDDSA_OperationSign struct by calling + * EDDSA_OperationSign_init(). + * - Initialize and set the preHashedMessage buffer and corresponding + * preHashedMessageLength. Note that this function accepts any length. This + * is the message to sign. + * - Initialize the signature components R and S as 32 byte arrays. + * - Use the CryptoKeys myPrivateKey and myPublicKey generated from + * EDDSA_OperationGeneratePublicKey(). + * - Call EDDSA_sign(). The R and S vectors will be written to the buffers + * provided in the function call. Ensure the return value is + * EDDSA_STATUS_SUCCESS. + * + * ## Verifying a message # + * After receiving the message, public key, R, and S, the application should + * do the following to verify the signature: + * - Initialize an EDDSA_OperationVerify struct by calling + * EDDSA_OperationVerify_init(). + * - Initialize and set the preHashedMessage buffer and corresponding + * preHashedMessageLength. Note that this function accepts any length. This + * is the message to verify. + * - Initialize a CryptoKey as public key with the keying material received + * from the other party. + * - Call EDDSA_verify(). Ensure the return value is EDDSA_STATUS_SUCCESS. The + * driver will validate the received public key against the provided curve. + * + * ## General usage # + * The API expects Edwards elliptic curves as defined in + * ti/drivers/cryptoutils/ecc/ECCParams.h. + * Several commonly used curves are provided. Check the device-specific EDDSA + * documentation + * for curve type (short Weierstrass, Montgomery, Edwards) support for your + * device. + * EDDSA support for a curve type on a device does not imply curve-type support + * for other ECC schemes. + * + * ## Parameter formatting # + * Public keys are points on an elliptic curve. For EDDSA, these points are + * represented in their compressed form. + * This API uses points expressed in compressed affine coordinates by default + * and formatted in little endian. + * The point itself is stored as Y in little endian. If the X-coordinate is + * odd, the most significant bit of the public key is set (that is 0x80 || y). + * Otherwise, the public key is simply y and the even choice of x-coordinate + * is selected. + * + * This API accepts and returns the keying material of public keys according + * to the following table: + * + * | Curve Type | PublicKeying Material Array | Array Length | + * |--------------------|-----------------------------|--------------------| + * | Ed25519 | [{0x80 or 0x00} || Y] | Curve Param Length | + * + * The signature components R and S as well as the hash must be formatted in + * little endian format. For the hash, this simply means passing the digest of + * the hash function SHA-512 directly into #EDDSA_sign() or #EDDSA_verify(). + * R and S will be interpreted as little-endian integers. + * + * @anchor ti_drivers_EDDSA_Synopsis + * ## Synopsis + * @anchor ti_drivers_EDDSA_Synopsis_Code + * @code + * // Import EdDSA Driver definitions + * #include + * + * // Create default parameters + * EDDSA_Handle eddsaHandle; + * EDDSA_Params params; + * + * EDDSA_init(); + * + * EDDSA_Params_init(¶ms); + * params.returnBehavior = EDDSA_RETURN_BEHAVIOR_BLOCKING; + * + * eddsaHandle = EDDSA_open(0, ¶ms); + * + * if (!eddsaHandle) { + * // Handle error + * } + * + * CryptoKey myPrivateKey; + * CryptoKey myPublicKey; + * CryptoKey theirPublicKey; + * + * // Initialize myPrivateKey + * CryptoKeyPlaintext_initKey(&myPrivateKey, + * myPrivateKeyingMaterial, + * sizeof(myPrivateKeyingMaterial)); + * + * // Initialize myPublicKey + * CryptoKeyPlaintext_initKey(&myPublicKey, + * myPublicKeyMaterial, + * sizeof(myPublicKeyMaterial)); + * + * // Initialize the operation + * EDDSA_OperationGeneratePublicKey_init(&operationGeneratePublicKey); + * operationGeneratePublicKey.curve = &ECCParams_Ed25519; + * operationGeneratePublicKey.myPrivateKey = &myPrivateKey; + * operationGeneratePublicKey.myPublicKey = &myPublicKey; + * + * operationResult = EDDSA_generatePublicKey(eddsaHandle, + * &operationGeneratePublicKey); + * + * if (operationResult != EDDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Initialize the operation + * EDDSA_OperationSign_init(&operationSign); + * operationSign.curve = &ECCParams_Ed25519; + * operationSign.myPrivateKey = &myPrivateKey; + * operationSign.myPublicKey = &myPublicKey; + * operationSign.preHashedMessage = preHashedMessage; + * operationSign.preHashedMessageLength = preHashedMessageLength; + * operationSign.R = sigR; + * operationSign.S = sigS; + * + * // Generate the signature + * operationResult = EDDSA_sign(eddsaHandle, &operationSign); + * + * if (operationResult != EDDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, + * theirPublicKeyingMaterial, + * sizeof(theirPublicKeyingMaterial)); + * + * EDDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_Ed25519; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.preHashedMessage = preHashedMessage; + * operationVerify.preHashedMessageLength = preHashedMessageLength; + * operationVerify.R = sigR; + * operationVerify.S = sigS; + * + * // Verify the EdDSA signature + * operationResult = EDDSA_verify(eddsaHandle, &operationVerify); + * + * if (operationResult != EDDSA_STATUS_SUCCESS) { + * // Handle error + * } + * + * // Close the driver + * EDDSA_close(eddsaHandle); + * @endcode + * + * @anchor ti_drivers_EDDSA_Examples + * # Examples # + * @code + * + * #include + * #include + * + * EDDSA_Handle eddsaHandle; + * EDDSA_Params params; + * CryptoKey theirPublicKey; + * int_fast16_t operationResult; + * EDDSA_OperationVerify operationVerify; + * + * // This vector is test vector 2 from Section 7.1 of RFC 8032. + * uint8_t publicKey[32] = {0x3D,0x40,0x17,0xC3,0xE8,0x43,0x89,0x5A, + * 0x92,0xB7,0x0A,0xA7,0x4D,0x1B,0x7E,0xBC, + * 0x9C,0x98,0x2C,0xCF,0x2E,0xC4,0x96,0x8C, + * 0xC0,0xCD,0x55,0xF1,0x2A,0xF4,0x66,0x0C}; + * uint8_t sigR[32] = {0x92,0xA0,0x09,0xA9,0xF0,0xD4,0xCA,0xB8, + * 0x72,0x0E,0x82,0x0B,0x5F,0x64,0x25,0x40, + * 0xA2,0xB2,0x7B,0x54,0x16,0x50,0x3F,0x8F, + * 0xB3,0x76,0x22,0x23,0xEB,0xDB,0x69,0xDA}; + * uint8_t sigS[32] = {0x08,0x5A,0xC1,0xE4,0x3E,0x15,0x99,0x6E, + * 0x45,0x8F,0x36,0x13,0xD0,0xF1,0x1D,0x8C, + * 0x38,0x7B,0x2E,0xAE,0xB4,0x30,0x2A,0xEE, + * 0xB0,0x0D,0x29,0x16,0x12,0xBB,0x0C,0x00}; + * uint8_t preHashedMessage[1] = {0x72}; + * uint32_t preHashedMessageLength = 1; + * + * // Initialize EDDSA driver + * EDDSA_init(); + * + * EDDSA_Params_init(¶ms); + * params.returnBehavior = EDDSA_RETURN_BEHAVIOR_BLOCKING; + * + * eddsaHandle = EDDSA_open(0, ¶ms); + * + * if (!eddsaHandle) { + * // Handle error + * } + * + * // Initialize theirPublicKey + * CryptoKeyPlaintext_initKey(&theirPublicKey, + * publicKey, + * sizeof(publicKey)); + * + * EDDSA_OperationVerify_init(&operationVerify); + * operationVerify.curve = &ECCParams_Ed25519; + * operationVerify.theirPublicKey = &theirPublicKey; + * operationVerify.preHashedMessage = preHashedMessage; + * operationVerify.preHashedMessageLength = preHashedMessageLength; + * operationVerify.R = sigR; + * operationVerify.S = sigS; + * + * // Verify the EdDSA signature + * operationResult = EDDSA_verify(eddsaHandle, &operationVerify); + * + * if (operationResult != EDDSA_STATUS_SUCCESS) { + * // Handle error + * } + * @endcode + * + * + * ## Using KeyStore for EDDSA Keys # + * + * @code + * + * // This example shows how to import persistent public key into KeyStore and + * // how to use KeyStore public key to verify EDDSA signature + * KeyStore_PSA_KeyFileId publicKeyID; + * KeyStore_PSA_KeyAttributes pubKeyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + * + * // Public Key + * KeyStore_PSA_setKeyAlgorithm(&pubKeyAttributes, KEYSTORE_PSA_ALG_PURE_EDDSA); + * KeyStore_PSA_setKeyUsageFlags(&pubKeyAttributes, KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE); + * // In this example, we assume public key to be stored is for Curve25519 + * KeyStore_PSA_setKeyType(&priKeyAttributes, + * KEYSTORE_PSA_KEY_TYPE_ECC_KEY_PAIR_BASE | KEYSTORE_PSA_ECC_CURVE_CURVE25519); + * // Set key ID for persistent keys + * GET_KEY_ID(publicKeyID, KEYSTORE_PSA_KEY_ID_USER_MIN); + * KeyStore_PSA_setKeyLifetime(&pubKeyAttributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); + * status = KeyStore_PSA_importKey(&pubKeyAttributes, + * publicKey, + * sizeof(publicKey), + * &publicKeyID); + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * while(1); // handle error + * } + * KeyStore_PSA_initKey(&theirPublicKey, publicKeyID, sizeof(theirPublicKeyingMaterial), NULL); + * + * + * // The application can continue to use the theirPublicKey as they would use + * // plaintext keys with EDDSA driver + * @endcode + * + * + */ + +#ifndef ti_drivers_EDDSA__include +#define ti_drivers_EDDSA__include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common EDDSA status code reservation offset. + * EDDSA driver implementations should offset status codes with + * EDDSA_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define EDDSAXYZ_STATUS_ERROR0 EDDSA_STATUS_RESERVED - 0 + * #define EDDSAXYZ_STATUS_ERROR1 EDDSA_STATUS_RESERVED - 1 + * #define EDDSAXYZ_STATUS_ERROR2 EDDSA_STATUS_RESERVED - 2 + * @endcode + */ +#define EDDSA_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return EDDSA_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define EDDSA_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return EDDSA_STATUS_ERROR if the function was not executed + * successfully. + */ +#define EDDSA_STATUS_ERROR (-1) + +/*! + * @brief The ongoing operation was canceled. + */ +#define EDDSA_STATUS_CANCELED (-2) + +/*! + * @brief An error status code returned if the hash hardware or software + * resource is currently unavailable. + * + * EDDSA driver implementations may have hardware or software limitations on + * how many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed because the hash module is unavailable. + */ +#define EDDSA_STATUS_HASH_UNAVAILABLE (-3) + +/*! + * @brief An error status code returned if the public-key accelerator + * hardware or software resource is currently unavailable. + * + * EDDSA driver implementations may have hardware or software limitations on + * how many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed because the PKA module is unavailable. + */ +#define EDDSA_STATUS_PKA_UNAVAILABLE (-4) + +/*! + * @brief The generated public key was the point at infinity. + * + * The point at infinity is not a valid public key, try + * EDDSA_generatePublicKey again. + */ +#define EDDSA_STATUS_POINT_AT_INFINITY (-5) + +/*! + * @brief The private key was not 32 bytes long. + * + * Ed25519 expects a 32 byte private key. + */ +#define EDDSA_STATUS_INVALID_PRIVATE_KEY_SIZE (-6) + +/*! + * @brief The public key was not 32 bytes long. + * + * Ed25519 expects a 32 byte public key. This is the compressed representation + * of a point on curve Ed25519. + */ +#define EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE (-7) + +/*! + * @brief The public key was not a valid point on curve Ed25519. + * + * Ed25519 expects a valid public key. This is the compressed representation + * of a point on curve Ed25519. + */ +#define EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE (-8) + +/*! + * @brief The Ed25519 signature component R was not 32 bytes long. + * + * Signature component R must be 32 bytes long, representing a point on + * Ed25519. + */ +#define EDDSA_STATUS_INVALID_R_SIZE (-9) + +/*! + * @brief The Ed25519 signature component S was not 32 bytes long. + * + * Signature component S must be 32 bytes long, representing a scalar. + */ +#define EDDSA_STATUS_INVALID_S_SIZE (-10) + +/*! + * @brief The Ed25519 signature component S was larger than the order of + * Ed25519. + * + * The signature component S must be less than the order of the elliptic curve + * Ed25519. + */ +#define EDDSA_STATUS_S_LARGER_THAN_ORDER (-11) + +/*! + * @brief The Ed25519 operation was called with conflicting private and + * public key ID parameters. + * + * The private and public key params have different ECC parameters. + */ +#define EDDSA_STATUS_KEY_ID_PARAM_MISMATCH (-12) + +/*! + * @brief The KeyStore module could not find a key with the given ID. + * + * The KeyStore was provided an invalid ID#. + */ +#define EDDSA_STATUS_KEYSTORE_INVALID_ID (-13) + +/*! + * @brief The KeyStore module entered a failure state when retrieving the key + * ID. + * + * A KeyStore operation failed as a result of an invalid key type, invalid key + * policy, not enough buffer space, hardware failure, and so on. + */ +#define EDDSA_STATUS_KEYSTORE_GENERIC_FAILURE (-14) + +/*! + * @brief The SHA2 module returned an error while hashing. + * + * The SHA2 module did not successfully hash a required value. + */ +#define EDDSA_STATUS_SHA2_HASH_FAILURE (-15) + +/*! + * @brief The KeyStore module returned an error while importing/exporting key + * + * Functions return EDDSA_STATUS_KEYSTORE_ERROR if any KeyStore operation + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define EDDSA_STATUS_KEYSTORE_ERROR (-16) + +/*! + * @brief EDDSA Global configuration + * + * The EDDSA_Config structure contains a set of pointers used to characterize + * the EDDSA driver implementation. + * + * This structure needs to be defined before calling EDDSA_init() and it must + * not be changed thereafter. + * + * @sa EDDSA_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} EDDSA_Config; + +/*! + * @brief A handle that is returned from an EDDSA_open() call. + */ +typedef EDDSA_Config *EDDSA_Handle; + +/*! + * @brief The way in which EDDSA function calls return after performing an + * encryption + authentication or decryption + verification operation. + * + * Not all EDDSA operations exhibit the specified return behavior. Functions + * that do not require significant computation and cannot offload that + * computation to a background thread behave like regular functions. Which + * functions exhibit the specified return behavior is implementation dependent. + * Specifically, a software-backed implementation run on the same CPU as the + * application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * EDDSA functions exhibiting the specified return behavior have restrictions + * on the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |EDDSA_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |EDDSA_RETURN_BEHAVIOR_BLOCKING | X | | | + * |EDDSA_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + EDDSA_RETURN_BEHAVIOR_CALLBACK = 1, + /*!< The function call will return immediately while the EDDSA operation + * goes on in the background. The registered callback function is called + * after the operation completes. The context the callback function is + * called (task, HWI, SWI) is implementation-dependent. + */ + + EDDSA_RETURN_BEHAVIOR_BLOCKING = 2, + /*!< The function call will block while EDDSA operation goes on in the + * background. EDDSA operation results are available after the function + * returns. + */ + + EDDSA_RETURN_BEHAVIOR_POLLING = 4, + /*!< The function call will continuously poll a flag while EDDSA operation + * goes on in the background. EDDSA operation results are available after + * the function returns. + */ + +} EDDSA_ReturnBehavior; + +/*! + * @brief Struct containing the parameters required for generating an EdDSA + * private-public keypair. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; + /*!< A pointer to the elliptic curve parameters */ + + const CryptoKey *myPrivateKey; + /*!< A pointer to the randomly generated randomly private key "k" in little + * endian. Must be 32 bytes for Ed25519. + */ + + CryptoKey *myPublicKey; + /*!< A pointer public EdDSA key A = s*B in compressed public key format. + * Must be 32 bytes for Ed25519. + */ + +} EDDSA_OperationGeneratePublicKey; + +/*! + * @brief Struct containing the parameters required for generating an EdDSA + * digital signature. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; + /*!< A pointer to the elliptic curve parameters */ + + const CryptoKey *myPrivateKey; + /*!< A pointer to the randomly generated private key "k" in little endian. + * Must be 32 bytes for Ed25519. + */ + + const CryptoKey *myPublicKey; + /*!< A pointer public EdDSA key A = s*B in compressed public key format. + * Must be 32 bytes for Ed25519. + */ + + const uint8_t *preHashedMessage; + /*!< A pointer to the (prehashed) message in little endian. In the + * PureEdDSA scheme, the prehash function is the identity, PH(M) = M. + */ + + size_t preHashedMessageLength; + /*!< Length of the message buffer in bytes. */ + + uint8_t *R; + /*!< Signature component R = r*B in little endian. + * Must be 32 bytes for Ed25519. + */ + + uint8_t *S; + /*!< Signature component S = r + x*s mod n in little endian. + * Must be 32 bytes for Ed25519. + */ + +} EDDSA_OperationSign; + +/*! + * @brief Struct containing the parameters required for verifying an EdDSA + * digital signature. + */ +typedef struct +{ + const ECCParams_CurveParams *curve; + /*!< A pointer to the elliptic curve parameters */ + + const CryptoKey *theirPublicKey; + /*!< A pointer to the signer's public EdDSA key A = s*B in compressed + * public key format. Must be 32 bytes for Ed25519 and a valid point on + * Ed25519. + */ + + const uint8_t *preHashedMessage; + /*!< A pointer to the (prehashed) message in little endian. In the + * PureEdDSA scheme, the prehash function is the identity, PH(M) = M. + */ + + size_t preHashedMessageLength; + /*!< Length of the message buffer in bytes. */ + + const uint8_t *R; + /*!< Signature component R to verify in little endian. + * Must be 32 bytes for Ed25519. + */ + + const uint8_t *S; + /*!< Signature component S to verify in little endian. + * Must be 32 bytes for Ed25519. + */ + +} EDDSA_OperationVerify; + +/*! + * @brief Union containing pointers to all supported operation structs. + */ +typedef union +{ + /*!< A pointer to an EDDSA_OperationGeneratePublicKey struct */ + EDDSA_OperationGeneratePublicKey *generatePublicKey; + /*!< A pointer to an EDDSA_OperationSign struct */ + EDDSA_OperationSign *sign; + /*!< A pointer to an EDDSA_OperationVerify struct */ + EDDSA_OperationVerify *verify; +} EDDSA_Operation; + +/*! + * @brief Enum for the operation types supported by the driver. + */ +typedef enum +{ + EDDSA_OPERATION_TYPE_GENERATE_PUBLIC_KEY = 1, + EDDSA_OPERATION_TYPE_SIGN = 2, + EDDSA_OPERATION_TYPE_VERIFY = 3, +} EDDSA_OperationType; + +/*! + * @brief The definition of a callback function used by the EDDSA driver + * when used in ::EDDSA_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the EDDSA operation. + * + * @param returnStatus The result of the EDDSA operation. May contain an + * error code if the result is the point at infinity for + * example. + * + * @param operation A union of pointers to operation structs. Only one type + * of pointer is valid per call to the callback function. Which type + * is currently valid is determined by /c operationType. The union + * allows easier access to the struct's fields without the need to + * typecase the result. + * + * @param operationType This parameter determined which operation the + * callback refers to and which type to access through \c operation. + */ +typedef void (*EDDSA_CallbackFxn)(EDDSA_Handle handle, + int_fast16_t returnStatus, + EDDSA_Operation operation, + EDDSA_OperationType operationType); + +/*! + * @brief EDDSA Parameters + * + * EDDSA Parameters are used to with the EDDSA_open() call. Default values for + * these parameters are set using EDDSA_Params_init(). + * + * @sa EDDSA_Params_init() + */ +typedef struct +{ + EDDSA_ReturnBehavior returnBehavior; + /*!< Blocking, callback, or polling return behavior */ + + EDDSA_CallbackFxn callbackFxn; + /*!< Callback function pointer */ + + uint32_t timeout; + /*!< Timeout in system ticks before the operation fails and returns */ + + void *custom; + /*!< Custom argument used by driver implementation */ + +} EDDSA_Params; + +/*! + * @brief This function initializes the EDDSA module. + * + * @pre The EDDSA_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other EDDSA driver APIs. This function call does not modify any + * peripheral registers. + */ +void EDDSA_init(void); + +/*! + * @brief Function to close an EDDSA peripheral specified by the EDDSA handle + * + * @pre EDDSA_open() has to be called first. + * + * @param handle An EDDSA handle returned from EDDSA_open() + * + * @sa EDDSA_open() + */ +void EDDSA_close(EDDSA_Handle handle); + +/*! + * @brief This function opens a given EDDSA peripheral. + * + * @pre EDDSA controller has been initialized using EDDSA_init() + * + * @param index Logical peripheral number for the EDDSA indexed into + * the EDDSA_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return An EDDSA_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa EDDSA_init() + * @sa EDDSA_close() + */ +EDDSA_Handle EDDSA_open(uint_least8_t index, const EDDSA_Params *params); + +/*! + * @brief Function to initialize the EDDSA_Params struct to its defaults + * + * @param params An pointer to EDDSA_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = EDDSA_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void EDDSA_Params_init(EDDSA_Params *params); + +/*! + * @brief Function to initialize an EDDSA_OperationGeneratePublicKey struct + * to its defaults + * + * @param operation A pointer to EDDSA_OperationGeneratePublicKey structure + * for initialization + * + * Defaults to all zeros. + */ +void EDDSA_OperationGeneratePublicKey_init(EDDSA_OperationGeneratePublicKey *operation); + +/*! + * @brief Function to initialize an EDDSA_OperationSign struct to its + * defaults + * + * @param operation A pointer to EDDSA_OperationSign structure for + * initialization + * + * Defaults to all zeros. + */ +void EDDSA_OperationSign_init(EDDSA_OperationSign *operation); + +/*! + * @brief Function to initialize an EDDSA_OperationSign struct to its + * defaults + * + * @param operation An pointer to EDDSA_OperationSign structure for + * initialization + * + * Defaults to all zeros. + */ +void EDDSA_OperationVerify_init(EDDSA_OperationVerify *operation); + +/*! + * @brief Generates an EdDSA private-public keypair. + * + * EDDSA_generatePublicKey() generates a private-public keypair (\c k, \c A) + * to generate EdDSA signatures with. + * + * @pre EDDSA_OperationSign_init() must be called on \c operation first. + * The driver must have been opened by calling EDDSA_open() first. + * + * @param [in] handle An EDDSA handle returned from EDDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * @sa EDDSA_sign() + * @sa EDDSA_verify() + * + * @retval #EDDSA_STATUS_SUCCESS The operation succeeded. + * @retval #EDDSA_STATUS_ERROR The operation failed. + * @retval #EDDSA_STATUS_CANCELED The operation was canceled. + * @retval #EDDSA_STATUS_HASH_UNAVAILABLE The required hash hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_PKA_UNAVAILABLE The required PKA hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_POINT_AT_INFINITY The computed public key is + * the point at infinity. + * Try again. + * @retval #EDDSA_STATUS_KEY_ID_PARAM_MISMATCH The ID for the private and + * public key parameters do + * not match. + * @retval #EDDSA_STATUS_KEYSTORE_INVALID_ID KeyStore could not find a + * key with the given key ID#. + * @retval #EDDSA_STATUS_KEYSTORE_GENERIC_FAILURE The KeyStore entered some + * error state when storing + * the public or private key. + * @retval #EDDSA_STATUS_KEYSTORE_ERROR The keystore module returned an error. + */ +int_fast16_t EDDSA_generatePublicKey(EDDSA_Handle handle, EDDSA_OperationGeneratePublicKey *operation); + +/*! + * @brief Generates an EdDSA signature. + * + * EDDSA_sign() generates a signature (\c R, \c S) of a message. + * + * @pre EDDSA_OperationSign_init() must be called on \c operation first. + * The driver must have been opened by calling EDDSA_open() first. + * + * @param [in] handle An EDDSA handle returned from EDDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * @sa EDDSA_generatePublicKey() + * @sa EDDSA_verify() + * + * @retval #EDDSA_STATUS_SUCCESS The operation succeeded. + * @retval #EDDSA_STATUS_ERROR The operation failed. + * @retval #EDDSA_STATUS_CANCELED The operation was canceled. + * @retval #EDDSA_STATUS_HASH_UNAVAILABLE The required hash hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_PKA_UNAVAILABLE The required PKA hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_INVALID_PRIVATE_KEY_SIZE The private key size is an + * invalid size. + * @retval #EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE The public key size is an + * invalid size. + * @retval #EDDSA_STATUS_KEY_ID_PARAM_MISMATCH The ID for the private and + * public key parameters do + * not match. + * @retval #EDDSA_STATUS_KEYSTORE_INVALID_ID KeyStore could not find a + * key with the given key ID#. + * @retval #EDDSA_STATUS_KEYSTORE_GENERIC_FAILURE The KeyStore entered some + * error state when retrieving + * the public or private key. + * @retval #EDDSA_STATUS_KEYSTORE_ERROR The keystore module returned an error. + */ +int_fast16_t EDDSA_sign(EDDSA_Handle handle, EDDSA_OperationSign *operation); + +/*! + * @brief Verifies a received EdDSA signature matches a hash and public key + * + * @pre EDDSA_OperationVerify_init() must be called on \c operation first. + * The driver must have been opened by calling EDDSA_open() first. + * + * @param [in] handle An EDDSA handle returned from EDDSA_open() + * + * @param [in] operation A struct containing the pointers to the + * buffers necessary to perform the operation + * + * @sa EDDSA_sign() + * + * @retval #EDDSA_STATUS_SUCCESS The operation succeeded. + * @retval #EDDSA_STATUS_ERROR The operation failed. + * @retval #EDDSA_STATUS_CANCELED The operation was canceled. + * @retval #EDDSA_STATUS_HASH_UNAVAILABLE The required hash hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_PKA_UNAVAILABLE The required PKA hardware + * resource was not available. + * Try again later. + * @retval #EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE The public key size is an + * invalid size. + * @retval #EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key is not a + * valid point. + * @retval #EDDSA_STATUS_INVALID_R_SIZE The signature component R + * is an invalid size. + * @retval #EDDSA_STATUS_INVALID_S_SIZE The signature component S + * is an invalid size. + * @retval #EDDSA_STATUS_S_LARGER_THAN_ORDER The signature component S + * is larger than the Edwards + * curve order. + * @retval #EDDSA_STATUS_KEYSTORE_INVALID_ID KeyStore could not find a + * key with the given key ID#. + * @retval #EDDSA_STATUS_KEYSTORE_GENERIC_FAILURE The KeyStore entered some + * error state when retrieving + * the public or private key. + * @retval #EDDSA_STATUS_KEYSTORE_ERROR The keystore module returned an error. + */ +int_fast16_t EDDSA_verify(EDDSA_Handle handle, EDDSA_OperationVerify *operation); + +/*! + * @deprecated This function will be deprecated in the 3Q20 SDK release. The + * asynchronicity of the function can not be handled by all accelerators. + * + * @brief Cancels an ongoing EDDSA operation. + * + * Asynchronously cancels an EDDSA operation. Only available when using + * EDDSA_RETURN_BEHAVIOR_CALLBACK or EDDSA_RETURN_BEHAVIOR_BLOCKING. + * The operation will terminate as though an error occurred. The + * return status code of the operation will be EDDSA_STATUS_CANCELED. + * + * @param handle Handle of the operation to cancel + * + * @retval #EDDSA_STATUS_SUCCESS The operation was canceled. + * @retval #EDDSA_STATUS_ERROR The operation was not canceled. + * There may be no operation to + * cancel. + */ +int_fast16_t EDDSA_cancelOperation(EDDSA_Handle handle); + +/** + * @brief Constructs a new EDDSA object + * + * Unlike #EDDSA_open(), #EDDSA_construct() does not require the hwAttrs and + * object to be allocated in a #EDDSA_Config array that is indexed into. + * Instead, the #EDDSA_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of + * temporary driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #EDDSA_Config describing the location of the object + * and hwAttrs. + * + * @param params #EDDSA_Params to configure the driver instance. + * + * @return Returns a #EDDSA_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +EDDSA_Handle EDDSA_construct(EDDSA_Config *config, const EDDSA_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_EDDSA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/GPIO.c b/simplelink_lpf2/source/ti/drivers/GPIO.c new file mode 100644 index 00000000..d1a66138 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/GPIO.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== GPIO.c ======== + */ +#include +#include + +#include + +extern GPIO_Config GPIO_config; + +/* + * ======== GPIO_setCallback ======== + */ +void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback) +{ + /* + * Only update callbacks entry if different. + * This allows the callbacks array to be in flash for static systems. + */ + if (index != GPIO_INVALID_INDEX && GPIO_config.callbacks[index] != callback) + { + GPIO_config.callbacks[index] = callback; + } +} + +/* + * ======== GPIO_getCallback ======== + */ +GPIO_CallbackFxn GPIO_getCallback(uint_least8_t index) +{ + return GPIO_config.callbacks[index]; +} + +/* + * ======== GPIO_setUserArg ======== + */ +void GPIO_setUserArg(uint_least8_t index, void *arg) +{ + if (index != GPIO_INVALID_INDEX) + { + GPIO_config.userArgs[index] = arg; + } +} + +/* + * ======== GPIO_getUserArg ======== + */ +void *GPIO_getUserArg(uint_least8_t index) +{ + return GPIO_config.userArgs[index]; +} + +/* + * ======== GPIO_resetConfig ======== + */ +void GPIO_resetConfig(uint_least8_t index) +{ + if (index != GPIO_INVALID_INDEX) + { + GPIO_disableInt(index); + GPIO_setConfig(index, GPIO_config.configs[index]); + GPIO_setCallback(index, NULL); + GPIO_setUserArg(index, NULL); + } +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/GPIO.h b/simplelink_lpf2/source/ti/drivers/GPIO.h new file mode 100644 index 00000000..142dedc9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/GPIO.h @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file GPIO.h + * + * @brief General Purpose I/O driver interface. + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The GPIO module allows you to manage General Purpose I/O pins via simple + * and portable APIs. GPIO pin behavior is usually configured statically, + * but can also be configured or reconfigured at runtime. + * + * Because of its simplicity, the GPIO driver does not follow the model of + * other TI-RTOS drivers in which a driver application interface has + * separate device-specific implementations. This difference is most + * apparent in the GPIOxxx_Config structure, which does not require you to + * specify a particular function table or object. + * + * # Usage # + * This section provides a basic \ref ti_drivers_GPIO_Synopsis + * "usage summary" and a set of \ref ti_drivers_GPIO_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * GPIO APIs and their effect are provided in subsequent sections. + * + * @anchor ti_drivers_GPIO_Synopsis + * ### Synopsis # + * @anchor ti_drivers_GPIO_Synopsis_Code + * @code + * // Import GPIO Driver definitions + * #include + * + * // Define names for GPIO pin indexes + * #define BUTTON 0 + * #define LED 1 + * + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Read GPIO pin + * unsigned int state = GPIO_read(BUTTON); + * + * // Write to GPIO pin + * GPIO_write(LED, state); + * @endcode + * + * @anchor ti_drivers_GPIO_Examples + * ### Examples # + * * @ref ti_drivers_GPIO_Example_callback "Creating an input callback" + * * @ref ti_drivers_GPIO_Example_reconfigure "Runtime pin configuration" + * + * @anchor ti_drivers_GPIO_Example_callback + * **Creating an input callback**: The following example demonstrates how + * to configure a GPIO pin to generate an interrupt and how to toggle an + * an LED on and off within the registered interrupt callback function. Pin + * configuration is handled within Sysconfig for this example. + * @code + * // Driver header file + * #include + * + * // TI Drivers Configuration + * #include "ti_drivers_config.h" + * + * // GPIO button call back function + * void gpioButton0Fxn(uint_least8_t index); + * + * main() + * { + * // Turn on user LED + * GPIO_write(CONFIG_GPIO_LED0, CONFIG_GPIO_LED_ON); + * + * // install Button callback and enable interrupts + * GPIO_setCallback(CONFIG_GPIO_BUTTON0, gpioButton0Fxn); + * GPIO_enableInt(CONFIG_GPIO_BUTTON0); + * } + * + * // + * // ======== gpioButton0Fxn ======== + * // Callback function for the GPIO interrupt on CONFIG_GPIO_BUTTON0 + * // + * // Note: index is the GPIO id for the button which is not used here + * // + * void gpioButton0Fxn(uint_least8_t index) + * { + * // Toggle the LED + * GPIO_toggle(CONFIG_GPIO_LED0); + * } + * @endcode + * + * @anchor ti_drivers_GPIO_Example_reconfigure + * **Runtime pin configuration**: The following example demonstrates how + * to (re)configure GPIO pins. + * @code + * // Driver header file + * #include + * + * // TI Driver configuration + * #include "ti_drivers_config.h" + * + * void main() + * { + * // One-time init of GPIO driver + * GPIO_init(); + * + * // Configure a button pin as input and configure its interrupt + * // Passing INT_ENABLE means you do not need to also call GPIO_enableInt() + * GPIO_setConfig( + * CONFIG_GPIO_BUTTON0, + * GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING | GPIO_CFG_INT_ENABLE + * ); + * + * // Configure an LED output pin + * GPIO_setConfig(CONFIG_GPIO_LED0, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + * } + * @endcode + * + * ### GPIO Driver Configuration # + * + * In order to use the GPIO APIs, the application is required + * to provide 3 structures in the ti_drivers_config.c file: + * 1. An array of @ref GPIO_PinConfig elements that defines the + * initial configuration of each pin on the device. A pin is then + * referenced in the application by its corresponding index in this + * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is + * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and + * device specific pin identification are configured in each element + * of this array (see @ref GPIO_PinConfigSettings). + * Below is a device specific example of the GPIO_PinConfig array: + * @code + * // + * // Array of Pin configurations + * // + * GPIO_PinConfig gpioPinConfigs[31] = { + * GPIO_CFG_INPUT, // DIO_0 + * GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_NONE, // CONFIG_GPIO_LP19 + * GPIO_CFG_INPUT, // DIO_2 + * GPIO_CFG_INPUT, // DIO_3 + * ... + * }; + * @endcode + * + * 2. An array of @ref GPIO_CallbackFxn elements that is used to store + * callback function pointers for GPIO pins. The indexes for these array + * elements correspond to the pins defined in the GPIO_pinConfig array. + * These function pointers can be defined statically by referencing the + * callback function name in the array element, or dynamically, by setting + * the array element to NULL and using GPIO_setCallback() at runtime to + * plug the callback entry. The callback function syntax should match the + * following: + * @code + * void (*GPIO_CallbackFxn)(uint_least8_t index); + * @endcode + * The index parameter is the same index that was passed to + * GPIO_setCallback(). This allows the same callback function to be used + * for multiple GPIO interrupts, by using the index to identify the GPIO + * that caused the interrupt. + * @remark Callback functions are called in the context of an interrupt + * service routine and should be designed accordingly. + * + * When an interrupt is triggered, the interrupt status of all + * (interrupt enabled) pins on a port will be read, cleared, and the + * respective callbacks will be executed. Callbacks will be called in order + * from least significant bit to most significant bit. + * Below is a device specific example of the GPIO_CallbackFxn array: + * @code + * // + * // Array of callback function pointers + * // + * GPIO_CallbackFxn gpioCallbackFunctions[31] = { + * NULL, // DIO_0 + * NULL, // DIO_1 + * myGpioCallback, // CONFIG_GPIO_LP19 + * NULL, // DIO_3 + * ... + * }; + * @endcode + * + * 3. A device specific GPIO_Config structure that tells the GPIO + * driver where the two aforementioned arrays are and the number of elements + * in each. The interrupt priority of all pins configured to generate + * interrupts is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + * Below is a device specific example of a GPIO_Config structure: + * @code + * // + * // ======== GPIO_config ======== + * // + * const GPIO_Config GPIO_config = { + * .configs = (GPIO_PinConfig *)gpioPinConfigs, + * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + * .intPriority = (~0) + * }; + * @endcode + * + * ### Initializing the GPIO Driver # + * + * GPIO_init() must be called before any other GPIO APIs. This function + * configures each GPIO pin in the user-provided @ref GPIO_PinConfig + * array according to the defined settings. The user can also reconfigure + * a pin dynamically after GPIO_init() is called by using the + * GPIO_setConfig(), and GPIO_setCallback() APIs. + * + * GPIO_init() is called from Board_init() by default. Calling GPIO_init() + * multiple times is safe. + * + * # Implementation # + * + * Unlike most other TI-RTOS drivers, there is no notion of an instance + * 'handle' with the GPIO driver. This allows lightweight pin control with + * minimal runtime and memory overhead. + * + * GPIO pins are always referenced by device DIO index. + * + ****************************************************************************** + */ + +#ifndef ti_drivers_GPIO__include +#define ti_drivers_GPIO__include + +#include + +#include + +/* The device-specific header is used to map GPIO_CFG_X_INTERNAL definitions + * directly to device-specific configuration values, allowing efficient runtime + * reconfiguration without the need for bit twiddling. + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0 || DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + #include +#endif + +/* Generic functions for converting pin indexes to and from masks. Internal use + * only. CLZ is an ARM instruction for `count leading zeroes`, so if multiple + * bits in the pinmask are set MASK_TO_PIN will only return the highest set + * bit. PIN_TO_MASK is used for setting registers. + */ +#if defined(__IAR_SYSTEMS_ICC__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __CLZ(pinmask)) +#elif defined(__TI_COMPILER_VERSION__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __clz(pinmask)) +#elif defined(__GNUC__) && !defined(__TI_COMPILER_VERSION__) + #include + #define GPIO_MASK_TO_PIN(pinmask) (31 - __builtin_clz(pinmask)) +#endif + +#define GPIO_PIN_TO_MASK(pin) (1 << (pin)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs. + * @{ + */ + +/*! + * @brief Successful status code returned by GPIO_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define GPIO_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by GPIO_setConfig(). + * + * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed + * successfully. + */ +#define GPIO_STATUS_ERROR (-1) +/** @}*/ + +/*! + * @brief GPIO pin configuration settings + * + * The meaning of the bits within PinConfig are entirely device-specific + * and are typically one-to-one with the hardware register controlling pin + * configuration. + * + * Only create and manipulate these values using GPIO_CFG_* defines. + */ +typedef uint32_t GPIO_PinConfig; + +/*! + * @brief Dummy value for "this pin is not assigned to a GPIO". + * + * Not for use in customer software. Some drivers use this value to manage the + * behaviour of optional pins (e.g. UART flow control, SPI chip select). If you + * pass this value to any GPIO methods, it will return immediately and no + * register writes will be performed. + */ +#define GPIO_INVALID_INDEX 0xFF + +/*! + * \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins + * @{ + */ +/** @name GPIO_PinConfig output pin configuration macros + * @{ + */ +/*! @hideinitializer Pin is an output. Equivalent to OUT_STD. */ +#define GPIO_CFG_OUTPUT GPIO_CFG_OUTPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is actively driven high and low */ +#define GPIO_CFG_OUT_STD GPIO_CFG_OUTPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is Open Drain */ +#define GPIO_CFG_OUT_OD_NOPULL GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Output pin is Open Drain w/ pull up */ +#define GPIO_CFG_OUT_OD_PU GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_UP_INTERNAL +/*! @hideinitializer Output pin is Open Drain w/ pull dn */ +#define GPIO_CFG_OUT_OD_PD GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL | GPIO_CFG_PULL_DOWN_INTERNAL + +/*! @hideinitializer Set output pin strength to low */ +#define GPIO_CFG_OUT_STR_LOW GPIO_CFG_DRVSTR_LOW_INTERNAL +/*! @hideinitializer Set output pin strength to medium */ +#define GPIO_CFG_OUT_STR_MED GPIO_CFG_DRVSTR_MED_INTERNAL +/*! @hideinitializer Set output pin strength to high */ +#define GPIO_CFG_OUT_STR_HIGH GPIO_CFG_DRVSTR_HIGH_INTERNAL + +/*! @hideinitializer Set pin's output to 1. */ +#define GPIO_CFG_OUT_HIGH GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL +/*! @hideinitializer Set pin's output to 0. */ +#define GPIO_CFG_OUT_LOW GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig input pin configuration macros + * @{ + */ +/*! @hideinitializer Pin is an input. */ +#define GPIO_CFG_INPUT GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Input pin with no internal PU/PD */ +#define GPIO_CFG_IN_NOPULL GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/*! @hideinitializer Input pin with internal PU */ +#define GPIO_CFG_IN_PU GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_UP_INTERNAL +/*! @hideinitializer Input pin with internal PD */ +#define GPIO_CFG_IN_PD GPIO_CFG_INPUT_INTERNAL | GPIO_CFG_PULL_DOWN_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig nondirectional pin configuration macros + * @{ + */ +/*! @hideinitializer Input and output are both disabled. Primarily useful for disabling muxed pins. */ +#define GPIO_CFG_NO_DIR GPIO_CFG_NO_DIR_INTERNAL | GPIO_CFG_PULL_NONE_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig pin inversion configuration macros + * @{ + */ +/*! @hideinitializer Input/output values are normal (default) */ +#define GPIO_CFG_INVERT_OFF GPIO_CFG_INVERT_OFF_INTERNAL +/*! @hideinitializer Input/output values are inverted */ +#define GPIO_CFG_INVERT_ON GPIO_CFG_INVERT_ON_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig pin hysteresis configuration macros + * @{ + */ +/*! @hideinitializer Input hysteresis is disabled (default) */ +#define GPIO_CFG_HYSTERESIS_OFF GPIO_CFG_HYSTERESIS_OFF_INTERNAL +/*! @hideinitializer Input hysteresis is enabled */ +#define GPIO_CFG_HYSTERESIS_ON GPIO_CFG_HYSTERESIS_ON_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig slew rate configuration macros + * @{ + */ +/*! @hideinitializer Output slew rate is unchanged (default) */ +#define GPIO_CFG_SLEW_NORMAL GPIO_CFG_SLEW_NORMAL_INTERNAL +/*! @hideinitializer Output slew rate is reduced */ +#define GPIO_CFG_SLEW_REDUCED GPIO_CFG_SLEW_REDUCED_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig interrupt configuration macros + * @{ + */ +/*! @hideinitializer No Interrupt (default) */ +#define GPIO_CFG_IN_INT_NONE GPIO_CFG_INT_NONE_INTERNAL +/*! @hideinitializer Interrupt on falling edge */ +#define GPIO_CFG_IN_INT_FALLING GPIO_CFG_INT_FALLING_INTERNAL +/*! @hideinitializer Interrupt on rising edge */ +#define GPIO_CFG_IN_INT_RISING GPIO_CFG_INT_RISING_INTERNAL +/*! @hideinitializer Interrupt on both edges */ +#define GPIO_CFG_IN_INT_BOTH_EDGES GPIO_CFG_INT_BOTH_EDGES_INTERNAL +/*! @hideinitializer Interrupt on low level */ +#define GPIO_CFG_IN_INT_LOW GPIO_CFG_INT_LOW_INTERNAL +/*! @hideinitializer Interrupt on high level */ +#define GPIO_CFG_IN_INT_HIGH GPIO_CFG_INT_HIGH_INTERNAL + +/*! @hideinitializer Interrupt disabled (default) */ +#define GPIO_CFG_INT_DISABLE GPIO_CFG_INT_DISABLE_INTERNAL +/*! @hideinitializer Interrupt enabled */ +#define GPIO_CFG_INT_ENABLE GPIO_CFG_INT_ENABLE_INTERNAL +/** @} */ + +/** @name GPIO_PinConfig power mode configuration macros + * @brief For devices that support low power modes, standard GPIO interrupts + * may be disabled in some modes. These defines allow configuring individual + * pins as wake-up sources. The GPIO module's wake up configuration is always + * enabled if it exists, so there is no module-level configuration. + * See the device-specific header files for details. + * @{ + */ +/*! @hideinitializer This pin will not wake the device up */ +#define GPIO_CFG_SHUTDOWN_WAKE_OFF GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL +/*! @hideinitializer A high value will wake the device from shutdown */ +#define GPIO_CFG_SHUTDOWN_WAKE_HIGH GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL +/*! @hideinitializer A low value will wake the device from shutdown */ +#define GPIO_CFG_SHUTDOWN_WAKE_LOW GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL +/** @} */ + +/** @name GPIO_pinconfig macro preventing configuration + * @brief Should be used if a pin is configured before the first GPIO_init() + * call, and should not be overwritten + * @{ + */ +/*! @hideinitializer Prevent this GPIO from being configured + * by the GPIO driver */ +#define GPIO_CFG_DO_NOT_CONFIG GPIO_CFG_DO_NOT_CONFIG_INTERNAL +/** @} */ + +/** @name GPIO_Mux configuration macros + * @brief For additional muxing options, see the directions in the + * device-specific GPIO driver. + * @{ + */ +/*! @hideinitializer Set this pin to be a GPIO (the default) */ +#define GPIO_MUX_GPIO GPIO_MUX_GPIO_INTERNAL +/** @} */ +/** @} end of GPIO_PinConfigSettings group */ + +/*! + * @brief GPIO callback function type + * + * @param index GPIO index. This is the same index that + * was passed to GPIO_setCallback(). This allows + * you to use the same callback function for multiple + * GPIO interrupts, by using the index to identify + * the GPIO that caused the interrupt. + */ +typedef void (*GPIO_CallbackFxn)(uint_least8_t index); + +/*! + * @brief GPIO driver configuration structure + * + * The GPIO_Config struct contains the defaults for pin configuration. + * + * The interrupt priority of all pins configured to generate interrupts + * is also specified here. Values for the interrupt priority are + * device-specific. You should be well-acquainted with the interrupt + * controller used in your device before setting this parameter to a + * non-default value. The sentinel value of (~0) (the default value) is + * used to indicate that the lowest possible priority should be used. + */ +typedef struct +{ + GPIO_PinConfig *configs; + GPIO_CallbackFxn *callbacks; + void **userArgs; + uint32_t intPriority; +} GPIO_Config; + +/*! + * @brief Clear a GPIO pin interrupt flag + * + * Clears the GPIO interrupt for the specified index. + * + * Note: It is not necessary to call this API within a callback assigned + * to a pin. The driver clears interrupt flags before dispatching callbacks. + * + * @param index GPIO index + */ +extern void GPIO_clearInt(uint_least8_t index); + +/*! + * @brief Disable a GPIO pin interrupt + * + * Disables interrupts for the specified GPIO index. + * + * @param index GPIO index + */ +extern void GPIO_disableInt(uint_least8_t index); + +/*! + * @brief Enable a GPIO pin interrupt + * + * Enables GPIO interrupts for the selected index to occur. + * + * Note: Prior to enabling a GPIO pin interrupt, make sure + * that a corresponding callback function has been provided. + * Use the GPIO_setCallback() API for this purpose at runtime. + * Alternatively, the callback function can be statically + * configured in the GPIO_CallbackFxn array provided. + * + * @param index GPIO index + */ +extern void GPIO_enableInt(uint_least8_t index); + +/*! + * @brief Initializes the GPIO module + * + * The pins defined in the application-provided *GPIO_config* structure + * are initialized accordingly. + * + * @pre The GPIO_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other GPIO driver APIs. + */ +extern void GPIO_init(void); + +/*! + * @brief Reads the value of a GPIO pin + * + * The value returned will either be zero or one depending on the + * state of the pin. + * + * @param index GPIO index + * + * @return 0 or 1, depending on the state of the pin. + */ +extern uint_fast8_t GPIO_read(uint_least8_t index); + +/*! + * @brief Toggles the current state of a GPIO + * + * @param index GPIO index + */ +extern void GPIO_toggle(uint_least8_t index); + +/*! + * @brief Writes the value to a GPIO pin + * + * @param index GPIO index + * @param value must be either 0 or 1 + */ +extern void GPIO_write(uint_least8_t index, unsigned int value); + +/*! + * @brief Bind a callback function to a GPIO pin interrupt + * + * Associate a callback function with a particular GPIO pin interrupt. + * + * Callbacks can be changed at any time, making it easy to switch between + * efficient, state-specific interrupt handlers. + * + * Note: The callback function is called within the context of an interrupt + * handler. + * + * Note: This API does not enable the GPIO pin interrupt. + * Use GPIO_enableInt() and GPIO_disableInt() to enable and disable the pin + * interrupt as necessary, or use GPIO_CFG_INT_ENABLE when calling setConfig. + * + * Note: it is not necessary to call GPIO_clearInt() within a callback. + * That operation is performed internally before the callback is invoked. + * + * @param index GPIO index + * @param callback address of the callback function + */ +extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback); + +/*! + * @brief Gets the callback associated with a GPIO pin. + * + * @param index GPIO index + * + * @return The callback function for the pin or NULL. + */ +extern GPIO_CallbackFxn GPIO_getCallback(uint_least8_t index); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For input pins with interrupt configurations, a corresponding interrupt + * object will be created as needed. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + * + * @return GPIO_STATUS_SUCCESS or an error if the pin cannot be configured + */ +extern int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig); + +/*! + * @brief Configure the gpio pin + * + * Dynamically configure a gpio pin to a device specific setting. + * This variant only allows configuring the interrupt settings (rising edge, + * falling edge, etc.) and enabling or disabling interrupts. + * + * Only GPIO_CFG_IN_INT_XXX macros and GPIO_CFG_INT_ENABLE/DISABLE may be + * passed to the config parameter for this function. If you do not pass + * GPIO_CFG_INT_ENABLE, this function will disable interrupts. + * + * @param index GPIO index + * @param config pin configuration settings + */ +extern void GPIO_setInterruptConfig(uint_least8_t index, GPIO_PinConfig config); + +/*! + * @brief Get the current configuration for a gpio pin + * + * GPIO_getConfig() gets the current pin configuration. + * + * This value may not be identical to the value used in setConfig, as some + * configuration options are applied directly to hardware on some devices and + * not saved in order to save memory. + * + * @param index GPIO index + * @param pinConfig Location to store device specific pin + * configuration settings + */ +extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig); + +/*! + * @brief Resets the configuration for a gpio pin to the default value + * + * The default pin configuration is provided in the static GPIO_PinConfig + * array, defined by sysconfig or the board file at compile time. Also clears + * the callback and user argument. + * + * @param index GPIO index + */ +extern void GPIO_resetConfig(uint_least8_t index); + +/*! + * @brief Get the current mux for a gpio pin + * + * For details and valid mux options, see the device-specific header file. + * + * @param index GPIO index + * + * @return A device-specific mux value or GPIO_MUX_GPIO. + */ +extern uint32_t GPIO_getMux(uint_least8_t index); + +/*! + * @brief Configure the gpio pin's config and mux in a single write + * + * Dynamically configure a gpio pin to a device specific setting. + * For many applications, the pin configurations provided in the static + * GPIO_PinConfig array is sufficient. + * + * For some devices, configuring the pin and then muxing it can create a small + * drop on the line, which is enough to trigger some communication protocols. + * This helper function sets the pin configuration and the mux in a single access. + * + * @param index GPIO index + * @param pinConfig device specific pin configuration settings + * @param mux Device-specific mux value to use a special mode, + * or GPIO_MUX_GPIO to reset the pin to standard IO. + * + * @return GPIO_STATUS_SUCCESS or an error if the pin cannot be configured + */ +extern int_fast16_t GPIO_setConfigAndMux(uint_least8_t index, GPIO_PinConfig pinConfig, uint32_t mux); + +/*! + * @brief Set the user argument for a gpio pin + * + * This can be retrieved using GPIO_getUserArg() and can be helpful to share + * callback logic across different pins. + * + * @param index GPIO index + * @param arg Pointer to a user object + */ +void GPIO_setUserArg(uint_least8_t index, void *arg); + +/*! + * @brief Get the user argument for a gpio pin + * + * @param index GPIO index + * + * @return Pointer to a user object set by GPIO_setUserArg() + */ +void *GPIO_getUserArg(uint_least8_t index); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIO__include */ diff --git a/simplelink_lpf2/source/ti/drivers/I2C.c b/simplelink_lpf2/source/ti/drivers/I2C.c new file mode 100644 index 00000000..af26191b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/I2C.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== I2C.c ======== + */ + +#include +#include +#include + +#include +#include + +#include +#include + +/* Default I2C parameters structure */ +const I2C_Params I2C_defaultParams = { + I2C_MODE_BLOCKING, /* transferMode */ + NULL, /* transferCallbackFxn */ + I2C_100kHz, /* bitRate */ + I2C_ADDRESS_MODE_7_BIT, /* addressMode */ + NULL /* custom */ +}; + +/* + * ======== I2C_cancel ======== + */ +void I2C_cancel(I2C_Handle handle) +{ + I2C_Object *object = handle->object; + I2C_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + key = HwiP_disable(); + + /* Return if no transfer in progress */ + if (!object->headPtr) + { + HwiP_restore(key); + return; + } + + I2CSupport_controllerFinish(hwAttrs); + + /* Set current transaction as canceled */ + object->currentTransaction->status = I2C_STATUS_CANCEL; + + HwiP_restore(key); +} + +/* + * ======== I2C_init ======== + */ +void I2C_init(void) +{ + /* Do nothing */ +} + +/* + * ======== I2C_Params_init ======= + */ +void I2C_Params_init(I2C_Params *params) +{ + *params = I2C_defaultParams; +} + +/* + * ======== I2C_transfer ======== + */ +bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction) +{ + int_fast16_t result = (I2C_transferTimeout(handle, transaction, I2C_WAIT_FOREVER)); + + if (result == I2C_STATUS_SUCCESS) + { + return (true); + } + else + { + return (false); + } +} + +/* + * ======== I2C_transferTimeout ======== + */ +int_fast16_t I2C_transferTimeout(I2C_Handle handle, I2C_Transaction *transaction, uint32_t timeout) +{ + I2C_Object *object = handle->object; + I2C_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + int_fast16_t ret; + + /* Check if anything needs to be written or read */ + if ((!transaction->writeCount) && (!transaction->readCount)) + { + transaction->status = I2C_STATUS_INVALID_TRANS; + /* Nothing to write or read */ + return (transaction->status); + } + + key = HwiP_disable(); + + /* If callback mode, determine if transfer in progress */ + if (object->transferMode == I2C_MODE_CALLBACK && object->headPtr) + { + /* + * Queued transactions are being canceled. Can't allow additional + * transactions to be queued. + */ + if (object->headPtr->status == I2C_STATUS_CANCEL) + { + transaction->status = I2C_STATUS_INVALID_TRANS; + ret = transaction->status; + } + /* Transfer in progress */ + else + { + /* + * Update the message pointed by the tailPtr to point to the next + * message in the queue + */ + object->tailPtr->nextPtr = transaction; + + /* Update the tailPtr to point to the last message */ + object->tailPtr = transaction; + + /* Set queued status */ + transaction->status = I2C_STATUS_QUEUED; + + ret = I2C_STATUS_SUCCESS; + } + + HwiP_restore(key); + return (ret); + } + + /* Store the headPtr indicating I2C is in use */ + object->headPtr = transaction; + object->tailPtr = transaction; + + /* In blocking mode, transactions can queue on the I2C mutex */ + transaction->status = I2C_STATUS_QUEUED; + + HwiP_restore(key); + + /* Get the lock for this I2C handle */ + if (SemaphoreP_pend(&(object->mutex), SemaphoreP_NO_WAIT) == SemaphoreP_TIMEOUT) + { + + /* We were unable to get the mutex in CALLBACK mode */ + if (object->transferMode == I2C_MODE_CALLBACK) + { + /* + * Recursively call transfer() and attempt to place transaction + * on the queue. This may only occur if a thread is preempted + * after restoring interrupts and attempting to grab this mutex. + */ + return (I2C_transferTimeout(handle, transaction, timeout)); + } + + /* Wait for the I2C lock. If it times-out before we retrieve it, then + * return false to cancel the transaction. */ + if (SemaphoreP_pend(&(object->mutex), timeout) == SemaphoreP_TIMEOUT) + { + transaction->status = I2C_STATUS_TIMEOUT; + return (I2C_STATUS_TIMEOUT); + } + } + + if (object->transferMode == I2C_MODE_BLOCKING) + { + /* + * In the case of a timeout, It is possible for the timed-out transaction + * to call the hwi function and post the object->transferComplete Semaphore + * To clear this, we simply do a NO_WAIT pend on (binary) + * object->transferComplete, so that it resets the Semaphore count. + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_NO_WAIT); + } + + I2CSupport_powerSetConstraint(); + + /* + * I2CSupport_primeTransfer is a longer process and + * protection is needed from the I2C interrupt + */ + HwiP_disableInterrupt(hwAttrs->intNum); + ret = I2CSupport_primeTransfer(handle, transaction); + HwiP_enableInterrupt(hwAttrs->intNum); + + if (ret != I2C_STATUS_SUCCESS) + { + /* Release disallow constraint. */ + I2CSupport_powerRelConstraint(); + } + else if (object->transferMode == I2C_MODE_BLOCKING) + { + /* Wait for the primed transfer to complete */ + if (SemaphoreP_pend(&(object->transferComplete), timeout) == SemaphoreP_TIMEOUT) + { + + key = HwiP_disable(); + + /* + * Protect against a race condition in which the transfer may + * finish immediately after the timeout. If this occurs, we + * will preemptively consume the semaphore on the next initiated + * transfer. + */ + if (object->headPtr) + { + /* + * It's okay to call cancel here since this is blocking mode. + * Cancel will generate a STOP condition and immediately + * return. + */ + I2C_cancel(handle); + + HwiP_restore(key); + + /* + * We must wait until the STOP interrupt occurs. When this + * occurs, the semaphore will be posted. Since the STOP + * condition will finish the current burst, we can't + * unblock the object->mutex until this occurs. + * + * This may block forever if the target holds the clock line-- + * rendering the I2C bus un-usable. + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_WAIT_FOREVER); + + transaction->status = I2C_STATUS_TIMEOUT; + } + else + { + HwiP_restore(key); + } + } + + ret = transaction->status; + } + + /* Release the lock for this particular I2C handle */ + SemaphoreP_post(&(object->mutex)); + + /* Return status */ + return (ret); +} diff --git a/simplelink_lpf2/source/ti/drivers/I2C.h b/simplelink_lpf2/source/ti/drivers/I2C.h new file mode 100644 index 00000000..bbe3cc45 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/I2C.h @@ -0,0 +1,966 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2C.h + * @brief Inter-Integrated Circuit (I2C) Controller Driver + * + * @anchor ti_drivers_I2C_Overview + * # Overview + * + * The I2C driver is designed to operate as an I2C controller and will not + * function as an I2C target. Multi-controller arbitration is not supported; + * therefore, this driver assumes it is the only I2C controller on the bus. + * This I2C driver's API set provides the ability to transmit and receive + * data over an I2C bus between the I2C controller and I2C target(s). The + * application is responsible for manipulating and interpreting the data. + * + * + *
+ * @anchor ti_drivers_I2C_Usage + * # Usage + * + * This section provides a basic @ref ti_drivers_I2C_Synopsis + * "usage summary" and a set of @ref ti_drivers_I2C_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * I2C APIs and their effect are provided in subsequent sections. + * + * @anchor ti_drivers_I2C_Synopsis + * ## Synopsis # + * @anchor ti_drivers_I2C_Synopsis_Code + * @code + * // Import I2C Driver definitions + * #include + * + * // Define name for an index of an I2C bus + * #define SENSORS 0 + * + * // Define the target address of device on the SENSORS bus + * #define OPT_ADDR 0x47 + * + * // One-time init of I2C driver + * I2C_init(); + * + * // initialize optional I2C bus parameters + * I2C_Params params; + * I2C_Params_init(¶ms); + * params.bitRate = I2C_400kHz; + * + * // Open I2C bus for usage + * I2C_Handle i2cHandle = I2C_open(SENSORS, ¶ms); + * + * // Initialize target address of transaction + * I2C_Transaction transaction = {0}; + * transaction.targetAddress = OPT_ADDR; + * + * // Read from I2C target device + * transaction.readBuf = data; + * transaction.readCount = sizeof(data); + * transaction.writeCount = 0; + * I2C_transfer(i2cHandle, &transaction); + * + * // Write to I2C target device + * transaction.writeBuf = command; + * transaction.writeCount = sizeof(command); + * transaction.readCount = 0; + * I2C_transferTimeout(i2cHandle, &transaction, 5000); + * + * // Close I2C + * I2C_close(i2cHandle); + * @endcode + * + * @anchor ti_drivers_I2C_Examples + * ## Examples + * + * @li @ref ti_drivers_I2C_Example_open "Getting an I2C bus handle" + * @li @ref ti_drivers_I2C_Example_write3bytes "Sending 3 bytes" + * @li @ref ti_drivers_I2C_Example_read5bytes "Reading 5 bytes" + * @li @ref ti_drivers_I2C_Example_writeread "Writing then reading in a single transaction" + * @li @ref ti_drivers_I2C_Example_callback "Using Callback mode" + * + * @anchor ti_drivers_I2C_Example_open + * ## Opening the I2C Driver + * + * After calling I2C_init(), the application can open an I2C instance by + * calling I2C_open().The following code example opens an I2C instance with + * default parameters by passing @p NULL for the #I2C_Params argument. + * + * @code + * I2C_Handle i2cHandle; + * + * i2cHandle = I2C_open(0, NULL); + * + * if (i2cHandle == NULL) { + * // Error opening I2C + * while (1) {} + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_write3bytes + * ## Sending three bytes of data. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t writeBuffer[3]; + * + * writeBuffer[0] = 0xAB; + * writeBuffer[1] = 0xCD; + * writeBuffer[2] = 0xEF; + * + * i2cTransaction.targetAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 3; + * i2cTransaction.readBuf = NULL; + * i2cTransaction.readCount = 0; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * // Unsuccessful I2C transfer + * if (i2cTransaction.status == I2C_STATUS_ADDR_NACK) { + * // I2C target address not acknowledged + * } + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_read5bytes + * ## Reading five bytes of data. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t readBuffer[5]; + * + * i2cTransaction.targetAddress = 0x50; + * i2cTransaction.writeBuf = NULL; + * i2cTransaction.writeCount = 0; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 5; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * if (i2cTransaction.status == I2C_STATUS_ADDR_NACK) { + * // I2C target address not acknowledged + * } + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_writeread + * ## Writing two bytes and reading four bytes in a single transaction. + * + * @code + * I2C_Transaction i2cTransaction = {0}; + * uint8_t readBuffer[4]; + * uint8_t writeBuffer[2]; + * + * writeBuffer[0] = 0xAB; + * writeBuffer[1] = 0xCD; + * + * i2cTransaction.targetAddress = 0x50; + * i2cTransaction.writeBuf = writeBuffer; + * i2cTransaction.writeCount = 2; + * i2cTransaction.readBuf = readBuffer; + * i2cTransaction.readCount = 4; + * + * status = I2C_transfer(i2cHandle, &i2cTransaction); + * + * if (status == false) { + * if (i2cTransaction->status == I2C_STATUS_ADDR_NACK) { + * // target address not acknowledged + * } + * } + * @endcode + * + * @anchor ti_drivers_I2C_Example_callback + * ## Using callback mode + * This final example shows usage of #I2C_MODE_CALLBACK, with queuing + * of multiple transactions. Because multiple transactions are simultaneously + * queued, separate #I2C_Transaction structures must be used. Each + * #I2C_Transaction will contain a custom application argument of a + * semaphore handle. The #I2C_Transaction.arg will point to the semaphore + * handle. When the callback function is called, the #I2C_Transaction.arg is + * checked for @p NULL. If this value is not @p NULL, then it can be assumed + * the @p arg is pointing to a valid semaphore handle. The semaphore handle + * is then used to call @p sem_post(). Hypothetically, this can be used to + * signal transaction completion to the task(s) that queued the + * transaction(s). + * + * @code + * void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, bool status) + * { + * // if transaction failed + * if (status == false) { + * if (msg->status == I2C_STATUS_ADDR_NACK) { + * // target address not acknowledged + * } + * else if (msg->status == I2C_STATUS_CANCEL) { + * // transaction canceled by I2C_cancel() + * } + * } + * + * // Check for a custom argument + * if (msg->arg != NULL) { + * + * // In this example, the custom argument is a semaphore handle + * // Perform a semaphore post + * sem_post((sem_t *) (msg->arg)); + * } + * } + * @endcode + * + * Snippets of the thread code that initiates the transactions are shown below. + * Note the use of multiple #I2C_Transaction structures. The handle of the + * semaphore to be posted is specified via @p i2cTransaction2.arg. + * I2C_transfer() is called three times to initiate each transaction. + * Since callback mode is used, these functions return immediately. After + * the transactions have been queued, other work can be done. Eventually, + * @p sem_wait() is called causing the thread to block until the transaction + * completes. When the transaction completes, the application's callback + * function, @p callbackFxn will be called. Once #I2C_CallbackFxn posts the + * semaphore, the thread will be unblocked and can resume execution. + * + * @code + * void thread(arg0, arg1) + * { + * + * I2C_Transaction i2cTransaction0 = {0}; + * I2C_Transaction i2cTransaction1 = {0}; + * I2C_Transaction i2cTransaction2 = {0}; + * + * // ... + * + * i2cTransaction0.arg = NULL; + * i2cTransaction1.arg = NULL; + * i2cTransaction2.arg = semaphoreHandle; + * + * // ... + * + * I2C_transfer(i2c, &i2cTransaction0); + * I2C_transfer(i2c, &i2cTransaction1); + * I2C_transfer(i2c, &i2cTransaction2); + * + * // ... + * + * sem_wait(semaphoreHandle); + * } + * @endcode + * + *
+ * @anchor ti_drivers_I2C_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_I2C__include +#define ti_drivers_I2C__include + +/*! @cond */ +#include +#include +#include + +#include +#include +/*! @endcond */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup I2C_STATUS I2C Status codes + * These macros are reservations for I2C.h + * @{ + */ + +/*! @cond */ +/*! + * @private + * Common I2C_control status code reservation offset. + * I2C driver implementations should offset status codes with + * #I2C_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0 + * #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1 + * #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2 + * @endcode + */ +#define I2C_STATUS_RESERVED (-32) +/*! @endcond */ + +/*! + * @brief I2C transaction is queued but has not started + */ +#define I2C_STATUS_QUEUED (1) + +/*! + * @brief Successful status code returned by I2C API. + */ +#define I2C_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by I2C API. + */ +#define I2C_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by I2C_control() for undefined + * command codes. + */ +#define I2C_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief I2C operation timed-out + */ +#define I2C_STATUS_TIMEOUT (-3) + +/*! + * @brief I2C serial clock line timeout + */ +#define I2C_STATUS_CLOCK_TIMEOUT (-4) + +/*! + * @brief I2C target address not acknowledged + */ +#define I2C_STATUS_ADDR_NACK (-5) + +/*! + * @brief I2C data byte not acknowledged + */ +#define I2C_STATUS_DATA_NACK (-6) + +/*! + * @brief I2C multi-controller arbitration lost + */ +#define I2C_STATUS_ARB_LOST (-7) + +/*! + * @brief I2C transaction is in progress or returned without completing + */ +#define I2C_STATUS_INCOMPLETE (-8) + +/*! + * @brief I2C bus already in use by another controller. The I2C transaction + * was therefore unable to start. + */ +#define I2C_STATUS_BUS_BUSY (-9) + +/*! + * @brief I2C transaction canceled by I2C_cancel() + */ +#define I2C_STATUS_CANCEL (-10) + +/*! + * @brief I2C transaction is invalid. This may occur if: + * 1. The #I2C_Transaction.readCount and #I2C_Transaction.writeCount are + * both set to 0. + * 2. A call to I2C_transfer() is made from a #I2C_CallbackFxn while queued + * transactions are being canceled. See also: I2C_cancel() + */ +#define I2C_STATUS_INVALID_TRANS (-11) +/** @} */ + +/*! + * @brief Wait forever define used to specify timeouts. + */ +#define I2C_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from an I2C_open() call. + */ +typedef struct I2C_Config_ *I2C_Handle; + +/*! + * @brief Defines a transaction to be used with I2C_transfer() or + * I2C_transferTimeout() + * + * After a call to I2C_transfer(), the #I2C_Transaction.status reflects + * the current transfer status. + * + * @sa I2C_transfer(), I2C_transferTimeout() + */ +typedef struct +{ + /*! + * Pointer to a buffer of at least #I2C_Transaction.writeCount bytes. + * If #I2C_Transaction.writeCount is 0, this pointer is not used. + */ + void *writeBuf; + + /*! + * Number of bytes to write to the I2C target device. A value of 0 + * indicates no data will be written to the target device and only a read + * will occur. If this value + * is not 0, the driver will always perform the write transfer first. + * The data written to the I2C bus is preceded by the + * #I2C_Transaction.targetAddress with the write bit set. If + * @p writeCount bytes are successfully sent and + * acknowledged, the transfer will complete or perform a read--depending + * on #I2C_Transaction.readCount. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t writeCount; + + /*! + * Pointer to a buffer of at least #I2C_Transaction.readCount bytes. + * If #I2C_Transaction.readCount is 0, this pointer is not used. + */ + void *readBuf; + + /*! + * Number of bytes to read from the I2C target device. A value of 0 + * indicates no data will be read and only a write will occur. If + * #I2C_Transaction.writeCount is not 0, this driver will perform the + * write first, followed by the read. The data read from the bus is + * preceded by the #I2C_Transaction.targetAddress with the read bit set. + * After @p readCount bytes are successfully read, the transfer will + * complete. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t readCount; + + /*! + * Pointer to a custom argument to be passed to the #I2C_CallbackFxn + * function via the #I2C_Transaction structure. + * + * @note The #I2C_CallbackFxn function is only called when operating in + * #I2C_MODE_CALLBACK. + * + * @sa #I2C_MODE_CALLBACK + * @sa #I2C_CallbackFxn + */ + void *arg; + + /*! + * I2C status of the current transaction. The status may be used to + * determine why a transaction failed. Potential codes are: + * @li #I2C_STATUS_SUCCESS + * @li #I2C_STATUS_ERROR + * @li #I2C_STATUS_TIMEOUT + * @li #I2C_STATUS_CLOCK_TIMEOUT + * @li #I2C_STATUS_ADDR_NACK + * @li #I2C_STATUS_DATA_NACK + * @li #I2C_STATUS_ARB_LOST + * @li #I2C_STATUS_INCOMPLETE + * @li #I2C_STATUS_BUS_BUSY + * @li #I2C_STATUS_CANCEL + * @li #I2C_STATUS_INVALID_TRANS + * + * This status may also be used to determine if a transaction is queued + * (#I2C_STATUS_QUEUED) or in progress (#I2C_STATUS_INCOMPLETE). + */ + volatile int_fast16_t status; + + /*! + * I2C target address used for the transaction. The target address is + * the first byte transmitted during an I2C transfer. The read/write bit + * is automatically set based upon the #I2C_Transaction.writeCount and + * #I2C_Transaction.readCount. + */ + uint_least16_t targetAddress; + + /*! + * @private This is reserved for use by the driver and must never be + * modified by the application. + */ + void *nextPtr; +} I2C_Transaction; + +/*! + * @brief Return behavior of I2C_Transfer() specified in the #I2C_Params. + * + * This enumeration defines the return behaviors for a call to I2C_transfer(). + * + * @sa #I2C_Params + */ +typedef enum +{ + /*! + * In #I2C_MODE_BLOCKING, calls to I2C_transfer() block until the + * #I2C_Transaction completes. Other threads calling I2C_transfer() + * while a transaction is in progress are also placed into a blocked + * state. If multiple threads are blocked, the thread with the highest + * priority will be unblocked first. This implies that arbitration + * will not be executed in chronological order. + * + * @note When using #I2C_MODE_BLOCKING, I2C_transfer() must be called + * from a thread context. + */ + I2C_MODE_BLOCKING, + + /*! + * In #I2C_MODE_CALLBACK, calls to I2C_transfer() return immediately. The + * application's callback function, #I2C_Params.transferCallbackFxn, is + * called when the transaction is complete. Sequential calls to + * I2C_transfer() will place #I2C_Transaction structures into an + * internal queue. Queued transactions are automatically started after the + * previous transaction has completed. This queuing occurs regardless of + * any error state from previous transactions. The transactions are + * always executed in chronological order. The + * #I2C_Params.transferCallbackFxn function will be called asynchronously + * as each transaction is completed. + */ + I2C_MODE_CALLBACK +} I2C_TransferMode; + +/*! + * @brief The definition of a callback function. + * + * When operating in #I2C_MODE_CALLBACK, the callback function is called + * when an I2C_transfer() completes. The application is responsible for + * declaring an #I2C_CallbackFxn function and providing a pointer + * in #I2C_Params.transferCallbackFxn. + * + * @warning The callback function is called from an interrupt context. + * + * @param[out] handle #I2C_Handle used with the initial call to + * I2C_transfer() + * + * @param[out] transaction Pointer to the #I2C_Transaction structure used + * with the initial call to I2C_transfer(). This structure contains the + * custom argument specified by @p transaction.arg and the transaction status. + * + * @param[out] transferStatus Boolean indicating if the I2C transaction + * was successful. If @p true, the transaction was successful. If @p false, + * the transaction failed. + */ +typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus); + +/*! + * @brief Bit rate for an I2C driver instance specified in the #I2C_Params. + * + * This enumeration defines the bit rates used with an I2C_transfer(). + * + * @note You must check that the device specific implementation supports the + * desired #I2C_BitRate. + */ +typedef enum +{ + I2C_100kHz = 0, /*!< I2C Standard-mode. Up to 100 kbit/s. */ + I2C_400kHz = 1, /*!< I2C Fast-mode. Up to 400 kbit/s. */ + I2C_1000kHz = 2, /*!< I2C Fast-mode Plus. Up to 1Mbit/s. */ + I2C_3330kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ + I2C_3400kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ +} I2C_BitRate; + +/*! + * @brief Address mode for an I2C driver instance specified selected by + * #I2C_setAddressMode() + * + * This enumeration defines the address modes selected by #I2C_setAddressMode(). + * + * @note You must check that the device specific implementation supports the + * desired #I2C_AddressMode. + */ +typedef enum +{ + I2C_ADDRESS_MODE_7_BIT = 0, /*!< 7-bit address mode */ + I2C_ADDRESS_MODE_10_BIT = 1, /*!< 10-bit address mode */ +} I2C_AddressMode; + +/*! + * @brief I2C parameters used with I2C_open(). + * + * I2C_Params_init() must be called prior to setting fields in + * this structure. + * + * @sa I2C_Params_init() + */ +typedef struct +{ + /*! #I2C_TransferMode for all I2C transfers. */ + I2C_TransferMode transferMode; + + /*! + * Pointer to a #I2C_CallbackFxn to be invoked after a + * I2C_transfer() completes when operating in #I2C_MODE_CALLBACK. + */ + I2C_CallbackFxn transferCallbackFxn; + + /*! + * A #I2C_BitRate specifying the frequency at which the I2C peripheral + * will transmit data during a I2C_transfer(). + */ + I2C_BitRate bitRate; + + /*! + * A #I2C_AddressMode specifying the address mode to configure the I2C + * peripheral to use. This will be the address mode used after calling + * #I2C_open(). + * The address mode can later be changed using #I2C_setAddressMode(). + * + * @note Not all address modes are supported for by devices. Please refer to + * the device-specific documentation for a list of supported address modes. + */ + I2C_AddressMode addressMode; + + /*! Pointer to a device specific extension of the #I2C_Params */ + void *custom; +} I2C_Params; + +/*! @cond NODOC */ +#define I2C_BASE_OBJECT \ + /* I2C control variables */ \ + I2C_TransferMode transferMode; /* Blocking or Callback mode */ \ + I2C_CallbackFxn transferCallbackFxn; /* Callback function pointer */ \ + I2C_Transaction *currentTransaction; /* Ptr to current I2C transaction */ \ + \ + /* I2C transaction pointers for I2C_MODE_CALLBACK */ \ + I2C_Transaction *volatile headPtr; /* Head ptr for queued transactions */ \ + I2C_Transaction *tailPtr; /* Tail ptr for queued transactions */ \ + \ + /* I2C RTOS objects */ \ + HwiP_Struct hwi; /* Hwi object handle */ \ + SemaphoreP_Struct mutex; /* Grants exclusive access to I2C */ \ + SemaphoreP_Struct transferComplete; /* Signal I2C transfer complete */ \ + \ + /* Read and write variables */ \ + const uint8_t *writeBuf; /* Internal inc. writeBuf index */ \ + size_t writeCount; /* Internal dec. writeCounter */ \ + uint8_t *readBuf; /* Internal inc. readBuf index */ \ + size_t readCount; /* Internal dec. readCounter */ \ + \ + bool isOpen; /* Flag to show module is open */ \ +/*! @endcond */ + +/*! + * @cond NODOC + * I2C Object. Applications must not access any member variables of + * this structure! + */ +typedef struct +{ + I2C_BASE_OBJECT +} I2C_Object; +/*! @endcond */ + +/*! @cond NODOC */ +#define I2C_BASE_HWATTRS \ + /*! I2C Peripheral's base address */ \ + uint32_t baseAddr; \ + /*! I2C Peripheral's interrupt vector */ \ + uint32_t intNum; \ + /*! I2C Peripheral's interrupt priority. \ + * \ + * Note for CC26XX: The CC26XX uses three of the priority bits, \ + * meaning ~0 has the same effect as (7 << 5). \ + * \ + * (7 << 5) will apply the lowest priority. \ + * (1 << 5) will apply the highest priority. \ + * \ + * Setting the priority to 0 is not supported by the I2CCC26XX driver. \ + * \ + * Hwi's with priority 0 ignore the Hwi dispatcher to support zero-latency \ + * interrupts, thus invalidating the critical sections in this driver. \ + */ \ + uint32_t intPriority; +/*! @endcond */ + +/*! + * @cond NODOC + * I2C HWAttrs. + */ +typedef struct +{ + I2C_BASE_HWATTRS +} I2C_HWAttrs; +/*! @endcond */ + +/*! + * @brief I2C driver's custom @ref driver_configuration "configuration" + * structure. + * + * @sa I2C_init() + * @sa I2C_open() + */ +typedef struct I2C_Config_ +{ + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void *object; + + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const *hwAttrs; +} I2C_Config; + +extern const I2C_Config I2C_config[]; +extern const uint_least8_t I2C_count; + +/*! + * @brief Cancels all I2C transfers + * + * This function will cancel asynchronous I2C_transfer() operations by + * generating a STOP condition on the I2C bus. + * + * Calls to I2C_cancel() return immediately; however, the transaction + * may not yet be canceled. + * + * For #I2C_MODE_BLOCKING, the current transaction is canceled. + * + * For #I2C_MODE_CALLBACK mode, the in progress transfer, as + * well as any queued transfers, will be canceled. The individual callback + * functions for each transfer will be called in chronological order. The + * callback functions are called in an interrupt context. Additional calls + * to I2C_transfer() invoked from the callback function of a canceled + * transaction will always fail. In such cases, the #I2C_Transaction.status + * will indicate #I2C_STATUS_INVALID_TRANS. + * + * A canceled transaction may be identified when the #I2C_Transaction.status + * is set to #I2C_STATUS_CANCEL. + * + * @note This API may not handle cases where the I2C target holds the clock + * line indefinitely. + * + * @pre I2C_Transfer() has been called. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @note Different I2C target devices will behave differently when an + * in-progress transfer fails and needs to be canceled. The target + * may need to be reset, or there may be other target-specific + * steps that can be used to successfully resume communication. + * + * @sa I2C_transfer() + * @sa #I2C_MODE_CALLBACK + */ +extern void I2C_cancel(I2C_Handle handle); + +/*! + * @brief Function to close an I2C driver instance + * + * @pre I2C_open() has been called. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + */ +extern void I2C_close(I2C_Handle handle); + +/*! + * @brief Function performs implementation specific features on a + * driver instance. + * + * @pre I2C_open() has to be called first. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] cmd A command value defined by the device specific + * implementation + * + * @param[in] controlArg An optional R/W (read/write) argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @retval #I2C_STATUS_SUCCESS The call was successful. + * @retval #I2C_STATUS_UNDEFINEDCMD The @p cmd value is not supported by + * the device specific implementation. + */ +extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, void *controlArg); + +/*! + * @brief Function to initialize the I2C driver. + * + * This function must also be called before any otherI2C driver APIs. + */ +extern void I2C_init(void); + +/*! + * @brief Open an I2C driver instance. + * + * @pre I2C_init() has been called. + * + * @param[in] index Index in the @p I2C_Config[] array. + * + * @param[in] params Pointer to an initialized #I2C_Params structure. + * If NULL, the default #I2C_Params values are used. + * + * @return An #I2C_Handle on success, or @p NULL on an error. + * + * @sa I2C_init() + * @sa I2C_close() + */ +extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params); + +/*! + * @brief Initialize an #I2C_Params structure to its default values. + * + * @param[in] params A pointer to #I2C_Params structure for + * initialization. + * + * Defaults values are: + * @arg #I2C_Params.transferMode = #I2C_MODE_BLOCKING + * @arg #I2C_Params.transferCallbackFxn = @p NULL + * @arg #I2C_Params.bitRate = #I2C_100kHz + * @arg #I2C_Params.addressMode = #I2C_ADDRESS_MODE_7_BIT + * @arg #I2C_Params.custom = @p NULL + */ +extern void I2C_Params_init(I2C_Params *params); + +/*! + * @brief Set the I2C address mode + * + * @note Not all I2C driver implementations implement this function. + * + * @param[in] handle An #I2C_Handle returned from #I2C_open() + * + * @param[in] addressMode The address mode the I2C instance should use. + * + */ +extern void I2C_setAddressMode(I2C_Handle handle, I2C_AddressMode addressMode); + +/*! + * @brief Set the I2C SCL clock timeout. + * + * An I2C target can extend a I2C transaction by periodically pulling the + * clock low to create a slow bit transfer rate. The application can use this + * API to program a counter in the I2C module. The count is used to force a + * timeout if an I2C target holds the clock line low for longer than the + * @p timeout duration. An #I2C_STATUS_CLOCK_TIMEOUT status indicates a + * timeout event occured. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] timeout Timeout in units of I2C clock cycles. Refer to + * the device specifc reference manual to determine + * how to calculate the timeout value. + * + * @return Possible return values include: + * @li #I2C_STATUS_SUCCESS + * @li #I2C_STATUS_ERROR + * + * @sa I2C_transfer() + */ +extern int_fast16_t I2C_setClockTimeout(I2C_Handle handle, uint32_t timeout); + +/*! + * @brief Perform an I2C transaction with an I2C target peripheral. + * + * This function will perform an I2C transfer, as specified by an + * #I2C_Transaction structure. + * + * @note When using #I2C_MODE_BLOCKING, this must be called from a thread + * context. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] transaction A pointer to an #I2C_Transaction. The application + * is responsible for allocating and initializing an #I2C_Transaction + * structure prior to passing it to I2C_Transfer(). This + * structure must persist in memory unmodified until the transfer is complete. + * + * @note #I2C_Transaction structures cannot be re-used until the previous + * transaction has completed. Upon the completion of a transaction, the + * #I2C_Transaction.status may be used for error handling. + * + * @return In #I2C_MODE_BLOCKING: @p true for a successful transfer; @p false + * for an error (for example, an I2C bus fault (NACK)). + * + * @return In #I2C_MODE_CALLBACK: always @p true. The #I2C_CallbackFxn @p bool + * argument will be @p true to indicate success, and @p false to + * indicate an error. + * + * @pre I2C_open() has been called. + * + * @sa I2C_open(), I2C_transferTimeout() + * @sa I2C_Transaction + */ +extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction); + +/*! + * @brief Perform an I2C transaction with an I2C target peripheral. + * + * This function will perform an I2C transfer, as specified by an + * #I2C_Transaction structure. If the timeout is exceeded, then the + * I2C transaction is canceled. + * + * @note When using #I2C_MODE_BLOCKING, this must be called from a thread + * context. + * + * @note The timeout restriction is only applied when using + * #I2C_MODE_BLOCKING. If using #I2C_MODE_CALLBACK, the application should + * manage timeouts using I2C_cancel(). Additionally, this timeout may not + * handle cases where the I2C target holds the clock line indefinitely. + * + * @param[in] handle An #I2C_Handle returned from I2C_open() + * + * @param[in] transaction A pointer to an #I2C_Transaction. The application + * is responsible for allocating and initializing an #I2C_Transaction + * structure prior to passing it to I2C_TransferTimeout(). This + * structure must persist in memory unmodified until the transfer is complete. + * + * @param[in] timeout The time in system ticks to wait for the transaction + * to complete. Passing I2C_WAIT_FOREVER into this parameter will cause + * I2C_transferTimeout() to behave the same as I2C_transfer() but with a + * more detailed return status. + * + * @note #I2C_Transaction structures cannot be re-used until the previous + * transaction has completed. Upon the completion of a transaction, the + * #I2C_Transaction.status may be used for error handling. + * + * @return In #I2C_MODE_CALLBACK: always @p I2C_STATUS_SUCCESS. + * The #I2C_CallbackFxn @p transferStatus argument will be @p true + * to indicate success, and @p false to indicate an error. + * + * @return In #I2C_MODE_BLOCKING: Possible return values include: + * @li #I2C_STATUS_SUCCESS + * @li #I2C_STATUS_ERROR + * @li #I2C_STATUS_TIMEOUT + * @li #I2C_STATUS_CLOCK_TIMEOUT + * @li #I2C_STATUS_ADDR_NACK + * @li #I2C_STATUS_DATA_NACK + * @li #I2C_STATUS_ARB_LOST + * @li #I2C_STATUS_INCOMPLETE + * @li #I2C_STATUS_BUS_BUSY + * @li #I2C_STATUS_CANCEL + * @li #I2C_STATUS_INVALID_TRANS + * + * @pre I2C_open() has been called. + * + * @sa I2C_open(), I2C_transfer() + * @sa I2C_Transaction + */ +extern int_fast16_t I2C_transferTimeout(I2C_Handle handle, I2C_Transaction *transaction, uint32_t timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2C__include */ diff --git a/simplelink_lpf2/source/ti/drivers/I2S.c b/simplelink_lpf2/source/ti/drivers/I2S.c new file mode 100644 index 00000000..f084e5a5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/I2S.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== I2S.c ======== + */ + +#include + +extern const I2S_Config I2S_config[]; +extern const uint_least8_t I2S_count; + +/* Default I2S parameters structure */ +const I2S_Params I2S_defaultParams = { + .samplingFrequency = 8000, /* Sampling Freq */ + .memorySlotLength = I2S_MEMORY_LENGTH_16BITS, /* Memory slot length */ + .moduleRole = I2S_CONTROLLER, /* Controller / Target selection */ + .trueI2sFormat = (bool)true, /* Activate true I2S format */ + .invertWS = (bool)true, /* WS inversion */ + .isMSBFirst = (bool)true, /* Endianness selection */ + .isDMAUnused = (bool)false, /* Selection between DMA and CPU transmissions */ + .samplingEdge = I2S_SAMPLING_EDGE_RISING, /* Sampling edge */ + .beforeWordPadding = 0, /* Before sample padding */ + .bitsPerWord = 16, /* Bits/Sample */ + .afterWordPadding = 0, /* After sample padding */ + .fixedBufferLength = 1, /* Fixed Buffer Length */ + .SD0Use = I2S_SD0_OUTPUT, /* SD0Use */ + .SD1Use = I2S_SD1_INPUT, /* SD1Use */ + .SD0Channels = I2S_CHANNELS_STEREO, /* Channels activated on SD0 */ + .SD1Channels = I2S_CHANNELS_STEREO, /* Channels activated on SD1 */ + .phaseType = I2S_PHASE_TYPE_DUAL, /* Phase type */ + .startUpDelay = 2, /* Start up delay in number of WS periods */ + .CCLKDivider = 40, /* CCLK divider */ + .readCallback = NULL, /* Read callback */ + .writeCallback = NULL, /* Write callback */ + .errorCallback = NULL, /* Error callback */ + .custom = NULL, /* customParams */ +}; + +/* + * ======== I2S_Params_init ======== + */ +void I2S_Params_init(I2S_Params *params) +{ + *params = I2S_defaultParams; +} + +/* + * ======== I2S_Transaction_init ======== + */ +void I2S_Transaction_init(I2S_Transaction *transaction) +{ + transaction->bufPtr = NULL; + transaction->bufSize = 0; + transaction->bytesTransferred = 0; + transaction->untransferredBytes = 0; + transaction->numberOfCompletions = 0; + transaction->arg = (uintptr_t)NULL; +} diff --git a/simplelink_lpf2/source/ti/drivers/I2S.h b/simplelink_lpf2/source/ti/drivers/I2S.h new file mode 100644 index 00000000..e390aec9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/I2S.h @@ -0,0 +1,1349 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2S.h + * @brief Inter-Integrated Circuit Sound (I2S) Bus Driver + * + * The I2S header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * @anchor ti_drivers_I2S_Overview + * # Overview # + * + * The I2S driver facilitates the use of Inter-IC Sound (I2S), which is + * used to connect digital audio devices so that audio signals can be + * communicated between devices. The I2S driver simplifies reading and + * writing to any of the Multichannel Audio Serial Port (McASP) peripherals + * on the board with Receive and Transmit support. These include read and + * write characters on the McASP peripheral. + * + * I2S interfaces typically consist of 4 or 5 signals. The 5th signal is not + * systematically used. + * @li Serial Clock (SCK) also called Bit Clock (BCLK) or Multichannel + * Audio Frame Synchronization (McAFSX) + * @li Word Select (WS) also called Word Clock (WCLK), Left Right + * Clock (LRCLK) or Multichannel Audio Clock (McACLK) + * @li Serial Data (SD0) also called AD0, AD1, McAXR0, or possibly SDI + * @li Serial Data (SD1) also called AD1, ADI, McAXR1, or possibly SDI + * @li Controller Clock (CCLK) + * + *
+ * @anchor ti_drivers_I2S_Usage + * # Usage # + * + * The I2S driver provides the following APIs: + * @li I2S_init(): @copybrief I2S_init + * @li I2S_open(): @copybrief I2S_open + * @li I2S_Params_init(): @copybrief I2S_Params_init + * @li I2S_Transaction_init(): @copybrief I2S_Transaction_init + * @li I2S_setReadQueueHead(): @copybrief I2S_setReadQueueHead + * @li I2S_setWriteQueueHead(): @copybrief I2S_setWriteQueueHead + * @li I2S_startClocks(): @copybrief I2S_startClocks + * @li I2S_startRead(): @copybrief I2S_startRead + * @li I2S_startWrite(): @copybrief I2S_startWrite + * @li I2S_stopRead(): @copybrief I2S_stopRead + * @li I2S_stopWrite(): @copybrief I2S_stopWrite + * @li I2S_stopClocks(): @copybrief I2S_stopClocks + * @li I2S_close(): @copybrief I2S_close + * + *
+ * @anchor ti_drivers_I2S_Driver_Transactions + * ### Transactions # + * + * Data transfers are achieved through #I2S_Transaction structures. Application is + * responsible to maintain the transactions queues. The I2S driver completes the + * transactions one by one. When a transaction is over, the I2S driver takes in + * consideration the next transaction (if the next transaction is NULL, the I2S + * drivers signals this to the user). + * The I2S driver relies on the following fields of the #I2S_Transaction to + * complete it: + * - the buffer + * - the length of the buffer + * - a pointer on the next transaction to achieve (kept in a List_Elem structure) + * . + * The I2S driver provides the following elements (fields of the #I2S_Transaction): + * - the number of untransferred bytes: the driver is designed to avoid memory corruption and will + * not complete an incomplete transaction (meaning a transaction where the buffer size would not + * permit to send or receive a whole number of samples). In this case, the system considers the + * samples of the beginning of the buffer and read/write as much as possible samples and ignore the + * end of the buffer. The number of untransafered bytes is the number of bytes left at the end of + * the buffer) + * - the number of completions of the transaction. This value is basically incremented by one + * every time the transaction is completed. + * + * Please note that these two fields are valid only when the transaction has been completed. + * Consult examples to get more details on the transaction usage. + * + * The sample buffer structure and content is different between devices. Please + * refer to the device-specific documentation for details. + * + *
+ * @anchor ti_drivers_I2S_Driver_ProvidingData + * ### Providing data to the I2S driver # + * Application is responsible to handle the queues of transactions. + * Application is also responsible to provide to the driver a pointer on + * the first transaction to consider (considering that all the following + * transactions are correctly queued). + * #I2S_setReadQueueHead() and #I2S_setWriteQueueHead() allow the user to + * set the first transaction to consider. These functions should be used only + * when no transaction is running on the considered interface. + * + *
+ * @anchor ti_drivers_I2S_Driver_StartStopClocks + * ### Start and stop clocks and transactions # + * Clocks can be started and stopped by the application. + * Read and write can be started and stopped independently. + * To start a transfer, clocks must be running. + * To stop the clocks no transfer must be running. + * Refer to the following functions for more details: + * @li I2S_startClocks() @li I2S_startRead() @li I2S_startWrite() + * @li I2S_stopRead() @li I2S_stopWrite() @li I2S_stopClocks() + * + * @note + * @li In #I2S_TARGET mode, clocks must be started and stopped exactly like + * it is done in #I2S_CONTROLLER mode. + * @li If the queue of transaction is not empty, the calls to #I2S_stopRead() + * and #I2S_stopWrite() are blocking and potentially long. + * + *
+ * @anchor ti_drivers_I2S_Examples + * ## Examples # + * + * @li @ref ti_drivers_I2S_Example_PlayAndStop "Play and Stop" + * @li @ref ti_drivers_I2S_Example_Streaming "Streaming" + * @li @ref ti_drivers_I2S_Example_RepeatMode "Repeat" + * + *
+ * @anchor ti_drivers_I2S_Example_PlayAndStop + * ### Mode Play and Stop # + * The following example shows how to simultaneously receive and send out a given amount of data. + * + *
+ * @anchor ti_drivers_I2S_Example_PlayAndStop_Code + * @code + * static I2S_Handle i2sHandle; + * + * static uint16_t readBuf1[500]; // the data read will end up in this buffer + * static uint16_t readBuf2[500]; // the data read will end up in this buffer + * static uint16_t readBuf3[500]; // the data read will end up in this buffer + * static uint16_t writeBuf1[250] = {...some data...}; // this buffer will be sent out + * static uint16_t writeBuf2[250] = {...some data...}; // this buffer will be sent out + * static uint16_t writeBuf3[250] = {...some data...}; // this buffer will be sent out + * + * static I2S_Transaction i2sRead1; + * static I2S_Transaction i2sRead2; + * static I2S_Transaction i2sRead3; + * static I2S_Transaction i2sWrite1; + * static I2S_Transaction i2sWrite2; + * static I2S_Transaction i2sWrite3; + * + * List_List i2sReadList; + * List_List i2sWriteList; + * + * static volatile bool readStopped = (bool)true; + * static volatile bool writeStopped = (bool)true; + * + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * if(status & I2S_ALL_TRANSACTIONS_SUCCESS){ + * + * // Note: Here we do not queue new transfers or set a new queue-head. + * // The driver will stop sending out data on its own. + * writeStopped = (bool)true; + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * if(status & I2S_ALL_TRANSACTIONS_SUCCESS){ + * + * // Note: Here we do not queue new transfers or set a new queue-head. + * // The driver will stop receiving data on its own. + * readStopped = (bool)true; + * } + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // Handle the I2S error + * } + * + * void *modePlayAndStopThread(void *arg0) + * { + * I2S_Params i2sParams; + * + * I2S_init(); + * + * // Initialize I2S opening parameters + * I2S_Params_init(&i2sParams); + * i2sParams.fixedBufferLength = 500; // fixedBufferLength is the greatest common + * // divisor of all the different buffers + * // (here buffers' size are 500 and 1000 bytes) + * i2sParams.writeCallback = writeCallbackFxn ; + * i2sParams.readCallback = readCallbackFxn ; + * i2sParams.errorCallback = errCallbackFxn; + * + * i2sHandle = I2S_open(CONFIG_I2S0, &i2sParams); + * + * // Initialize the read-transactions + * I2S_Transaction_init(&i2sRead1); + * I2S_Transaction_init(&i2sRead2); + * I2S_Transaction_init(&i2sRead3); + * i2sRead1.bufPtr = readBuf1; + * i2sRead2.bufPtr = readBuf2; + * i2sRead3.bufPtr = readBuf3; + * i2sRead1.bufSize = sizeof(readBuf1); + * i2sRead2.bufSize = sizeof(readBuf2); + * i2sRead3.bufSize = sizeof(readBuf3); + * List_put(&i2sReadList, (List_Elem*)&i2sRead1); + * List_put(&i2sReadList, (List_Elem*)&i2sRead2); + * List_put(&i2sReadList, (List_Elem*)&i2sRead3); + * + * I2S_setReadQueueHead(i2sHandle, &i2sRead1); + * + * // Initialize the write-transactions + * I2S_Transaction_init(&i2sWrite1); + * I2S_Transaction_init(&i2sWrite2); + * I2S_Transaction_init(&i2sWrite3); + * i2sWrite1.bufPtr = writeBuf1; + * i2sWrite2.bufPtr = writeBuf2; + * i2sWrite3.bufPtr = writeBuf3; + * i2sWrite1.bufSize = sizeof(writeBuf1); + * i2sWrite2.bufSize = sizeof(writeBuf2); + * i2sWrite3.bufSize = sizeof(writeBuf3); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite1); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite2); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite3); + * + * I2S_setWriteQueueHead(i2sHandle, &i2sWrite1); + * + * I2S_startClocks(i2sHandle); + * I2S_startWrite(i2sHandle); + * I2S_startRead(i2sHandle); + * + * readStopped = (bool)false; + * writeStopped = (bool)false; + * + * while (1) { + * + * if(readStopped && writeStopped) { + * I2S_stopClocks(i2sHandle); + * I2S_close(i2sHandle); + * while (1); + * } + * } + * } + * @endcode + * + * \note If you desire to put only one transaction in the queue, fixedBufferLength must be inferior to half the length + *(in bytes) of the buffer to transfer. + * + *
+ * @anchor ti_drivers_I2S_Example_Streaming + * ### Writing Data in Continuous Streaming Mode # + * The following example shows how to read and write data in streaming mode. + * A dummy treatment of the data is also done. + * This example is not complete (semaphore and tasks creation are not shown) + * + *
+ * @anchor ti_drivers_I2S_Example_Streaming_Code + * @code + * static I2S_Handle i2sHandle; + * static sem_t semDataReadyForTreatment; + * + * // These buffers will successively be written, treated and sent out + * static uint16_t readBuf1[500]; + * static uint16_t readBuf2[500]; + * static uint16_t readBuf3[500]; + * static uint16_t readBuf4[500]; + * static uint16_t writeBuf1[500]={0}; + * static uint16_t writeBuf2[500]={0}; + * static uint16_t writeBuf3[500]={0}; + * static uint16_t writeBuf4[500]={0}; + * + * // These transactions will successively be part of the + * // i2sReadList, the treatmentList and the i2sWriteList + * static I2S_Transaction i2sRead1; + * static I2S_Transaction i2sRead2; + * static I2S_Transaction i2sRead3; + * static I2S_Transaction i2sRead4; + * static I2S_Transaction i2sWrite1; + * static I2S_Transaction i2sWrite2; + * static I2S_Transaction i2sWrite3; + * static I2S_Transaction i2sWrite4; + * + * List_List i2sReadList; + * List_List treatmentList; + * List_List i2sWriteList; + * + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // We must remove the previous transaction (the current one is not over) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // Remove the finished transaction from the write queue + * List_remove(&i2sWriteList, (List_Elem*)transactionFinished); + * + * // This transaction must now feed the read queue (we do not need anymore the data of this transaction) + * transactionFinished->queueElement.next = NULL; + * List_put(&i2sReadList, (List_Elem*)transactionFinished); + * + * // We need to queue a new transaction: let's take one in the treatment queue + * I2S_Transaction *newTransaction = (I2S_Transaction*)List_head(&treatmentList); + * if(newTransaction != NULL){ + * List_remove(&treatmentList, (List_Elem*)newTransaction); + * newTransaction->queueElement.next = NULL; + * List_put(&i2sWriteList, (List_Elem*)newTransaction); + * } + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // We must remove the previous transaction (the current one is not over) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // The finished transaction contains data that must be treated + * List_remove(&i2sReadList, (List_Elem*)transactionFinished); + * transactionFinished->queueElement.next = NULL; + * List_put(&treatmentList, (List_Elem*)transactionFinished); + * + * // Start the treatment of the data + * sem_post(&semDataReadyForTreatment); + * + * // We do not need to queue transaction here: writeCallbackFxn takes care of this :) + * } + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // Handle the I2S error + * } + * + * void *echoExampleThread(void *arg0) + * { + * I2S_Params i2sParams; + * + * I2S_init(); + * + * int retc = sem_init(&semDataReadyForTreatment, 0, 0); + * if (retc == -1) { + * while (1); + * } + * + * // Initialize the treatmentList (this list is initially empty) + * List_clearList(&treatmentList); + * + * //Initialize I2S opening parameters + * I2S_Params_init(&i2sParams); + * i2sParams.fixedBufferLength = 1000; + * i2sParams.writeCallback = writeCallbackFxn ; + * i2sParams.readCallback = readCallbackFxn ; + * i2sParams.errorCallback = errCallbackFxn; + * + * i2sHandle = I2S_open(CONFIG_I2S0, &i2sParams); + * + * // Initialize the read-transactions + * I2S_Transaction_init(&i2sRead1); + * I2S_Transaction_init(&i2sRead2); + * I2S_Transaction_init(&i2sRead3); + * I2S_Transaction_init(&i2sRead4); + * i2sRead1.bufPtr = readBuf1; + * i2sRead2.bufPtr = readBuf2; + * i2sRead3.bufPtr = readBuf3; + * i2sRead4.bufPtr = readBuf4; + * i2sRead1.bufSize = sizeof(readBuf1); + * i2sRead2.bufSize = sizeof(readBuf2); + * i2sRead3.bufSize = sizeof(readBuf3); + * i2sRead4.bufSize = sizeof(readBuf4); + * List_clearList(&i2sReadList); + * List_put(&i2sReadList, (List_Elem*)&i2sRead1); + * List_put(&i2sReadList, (List_Elem*)&i2sRead2); + * List_put(&i2sReadList, (List_Elem*)&i2sRead3); + * List_put(&i2sReadList, (List_Elem*)&i2sRead4); + * + * I2S_setReadQueueHead(i2sHandle, &i2sRead1); + * + * // Initialize the write-transactions + * I2S_Transaction_init(&i2sWrite1); + * I2S_Transaction_init(&i2sWrite2); + * I2S_Transaction_init(&i2sWrite3); + * I2S_Transaction_init(&i2sWrite4); + * i2sWrite1.bufPtr = writeBuf1; + * i2sWrite2.bufPtr = writeBuf2; + * i2sWrite3.bufPtr = writeBuf3; + * i2sWrite4.bufPtr = writeBuf4; + * i2sWrite1.bufSize = sizeof(writeBuf1); + * i2sWrite2.bufSize = sizeof(writeBuf2); + * i2sWrite3.bufSize = sizeof(writeBuf3); + * i2sWrite4.bufSize = sizeof(writeBuf4); + * List_clearList(&i2sWriteList); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite1); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite2); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite3); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite4); + * + * I2S_setWriteQueueHead(i2sHandle, &i2sWrite1); + * + * I2S_startClocks(i2sHandle); + * I2S_startWrite(i2sHandle); + * I2S_startRead(i2sHandle); + * + * while (1) { + * uint8_t k = 0; + * I2S_Transaction* lastAchievedReadTransaction = NULL; + * + * retc = sem_wait(&semDataReadyForTreatment); + * if (retc == -1) { + * while (1); + * } + * + * lastAchievedReadTransaction = (I2S_Transaction*) List_head(&treatmentList); + * + * if(lastAchievedReadTransaction != NULL) { + * + * // Need a critical section to be sure to have corresponding bufPtr and bufSize + * uintptr_t key = HwiP_disable(); + * uint16_t *buf = lastAchievedReadTransaction->bufPtr; + * uint16_t bufLength = lastAchievedReadTransaction->bufSize / sizeof(uint16_t); + * HwiP_restore(key); + * + * // My dummy data treatment... + * for(k=0; k + * @anchor ti_drivers_I2S_Example_RepeatMode + * ### Writing Data in repeat Mode # + * The following example shows how to read and write data in repeat mode. + * The same buffers are continuously written and send out while the driver is not stopped. + * Here, we decide to only stop sending out after an arbitrary number of sending. + * + *
+ * @anchor ti_drivers_I2S_Example_RepeatMode_Code + * @code + * static I2S_Handle i2sHandle; + * + * // This buffer will be continuously re-written + * static uint16_t readBuf[500]; + * // This data will be continuously sent out + * static uint16_t writeBuf[500] = {...some cool data...}; + * + * static I2S_Transaction i2sRead; + * static I2S_Transaction i2sWrite; + * + * List_List i2sReadList; + * List_List i2sWriteList; + * + * static volatile bool writeFinished = (bool)false; + * static void writeCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // Nothing to do here: the buffer(s) are queued in a ring list, the transfers are + * // executed without any action from the application. + * + * // We must consider the previous transaction (ok, when you have only one transaction it's the same) + * I2S_Transaction *transactionFinished = (I2S_Transaction*)List_prev(&transactionPtr->queueElement); + * + * if(transactionFinished != NULL){ + * // After an arbitrary number of completion of the transaction, we will stop writting + * if(transactionFinished->numberOfCompletions >= 10) { + * + * // Note: You cannot use I2S_stopRead() / I2S_stopWrite() in the callback. + * // The execution of these functions is potentially blocking and can mess up the + * // system. + * + * writeFinished = (bool)true; + * } + * } + * } + * + * static void readCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * // Nothing to do here: the buffer(s) are queued in a ring list, the transfers are + * // executed without any action from the application. + * } + * + * static void errCallbackFxn(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr) { + * + * // Handle the I2S error + * } + * + * void *modeRepeat(void *arg0) + * { + * I2S_Params i2sParams; + * + * // Initialize I2S opening parameters + * I2S_Params_init(&i2sParams); + * i2sParams.fixedBufferLength = 1000; // No problem here: the driver consider + * // the list as an infinite list. + * i2sParams.writeCallback = writeCallbackFxn ; + * i2sParams.readCallback = readCallbackFxn ; + * i2sParams.errorCallback = errCallbackFxn; + * + * i2sHandle = I2S_open(CONFIG_I2S0, &i2sParams); + * + * // Initialize the read-transactions + * I2S_Transaction_init(&i2sRead); + * i2sRead.bufPtr = readBuf; + * i2sRead.bufSize = sizeof(readBuf); + * List_put(&i2sReadList, (List_Elem*)&i2sRead); + * List_tail(&i2sReadList)->next = List_head(&i2sReadList);// Read buffers are queued in a ring-list + * List_head(&i2sReadList)->prev = List_tail(&i2sReadList); + * + * I2S_setReadQueueHead(i2sHandle, &i2sRead); + * + * // Initialize the write-transactions + * I2S_Transaction_init(&i2sWrite); + * i2sWrite.bufPtr = writeBuf; + * i2sWrite.bufSize = sizeof(writeBuf); + * List_put(&i2sWriteList, (List_Elem*)&i2sWrite); + * List_tail(&i2sWriteList)->next = List_head(&i2sWriteList); // Write buffers are queued in a ring-list + * List_head(&i2sWriteList)->prev = List_tail(&i2sWriteList); + * + * I2S_setWriteQueueHead(i2sHandle, &i2sWrite); + * + * I2S_startClocks(i2sHandle); + * I2S_startWrite(i2sHandle); + * I2S_startRead(i2sHandle); + * + * while (1) { + * + * if(writeFinished){ + * writeFinished = (bool)false; + * I2S_stopWrite(i2sHandle); + * } + * } + * } + * @endcode + * + * @note In the case of circular lists, there is no problem to put only + * one buffer in the queue. + * + *
+ * @anchor ti_drivers_I2S_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_I2S__include +#define ti_drivers_I2S__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup I2S_STATUS Status Codes + * I2S_STATUS_* macros are general status codes used when user callback is called + * @{ + * @ingroup I2S_CONTROL + */ + +/*! + * @brief Successful status code returned by I2S driver functions. + * + * I2S driver functions return I2S_ALL_TRANSACTION_SUCCESS if ALL the queued transactions + * were executed successfully. + */ +#define I2S_ALL_TRANSACTIONS_SUCCESS (0x0001U) + +/*! + * @brief Successful status code returned by I2S driver functions. + * + * I2S driver functions return I2S_TRANSACTION_SUCCESS if ONE queued transaction + * was executed successfully. + */ +#define I2S_TRANSACTION_SUCCESS (0x0002U) + +/*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_TIMEOUT_ERROR if I2S module lost the audio clock. + * If this error has been raised, I2S module must be reseted and restarted. + */ +#define I2S_TIMEOUT_ERROR (0x0100U) + +/*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_BUS_ERROR if I2S module faced problem with the DMA + * bus (DMA transfer not completed in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ +#define I2S_BUS_ERROR (0x0200U) + +/*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_WS_ERROR if I2S module detect noise on the WS signal. + * If this error has been raised, I2S module must be reseted and restarted. + */ +#define I2S_WS_ERROR (0x0400U) + +/*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_PTR_READ_ERROR if I2S module ran out of data + * on the read interface (DMA pointer not loaded in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ +#define I2S_PTR_READ_ERROR (0x0800U) + +/*! + * @brief Error status code returned by I2S driver functions. + * + * I2S driver functions return I2S_PTR_WRITE_ERROR if I2S module ran out of data + * on the write interface (DMA pointer not loaded in time). + * If this error has been raised, I2S module must be reseted and restarted. + */ +#define I2S_PTR_WRITE_ERROR (0x1000U) +/** @}*/ + +/*! @brief I2S Global configuration + * + * The I2S_Config structure contains a set of pointers used to characterize + * the I2S driver implementation. + * + * This structure needs to be defined before calling I2S_init() and it must + * not be changed thereafter. + * + * @sa I2S_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} I2S_Config; + +/*! + * @brief A handle that is returned from a I2S_open() call. + */ +typedef I2S_Config *I2S_Handle; + +/*! + * @brief I2S transaction descriptor. + */ +typedef struct +{ + /*! Used internally to link descriptors together */ + List_Elem queueElement; + /*! Pointer to the buffer */ + void *bufPtr; + /*! Size of the buffer. */ + size_t bufSize; + /*! Internal use only. Number of bytes written to or read from the buffer. */ + size_t bytesTransferred; + /*! Number of non-transfered bytes at transaction's end. */ + size_t untransferredBytes; + /*! Parameter incremented each time the transaction is completed. */ + uint16_t numberOfCompletions; + /*! Internal argument. Application must not modify this element. */ + uintptr_t arg; +} I2S_Transaction; + +/*! + * @brief The definition of a user-callback function used by the I2S driver + * + * @param I2S_Handle I2S_Handle + * + * @param status Status of the operation (possible values are : + * :I2S_STATUS_SUCCESS, :I2S_STATUS_ERROR, + * :I2S_STATUS_BUFFER_UNAVAILABLE, :I2S_STATUS_TIMEOUT) + * + * @param I2S_Transaction *transactionPtr: Pointer on the transaction that has just started. + * For error callbacks, transactionPtr points on NULL. + * + */ +typedef void (*I2S_Callback)(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr); + +/*! + * @brief The definition of a function used to set the I2S register + * + * @param uint32_t ui32Base: base address of the I2S module. + * + * @param uint32_t ui32NextPointer: pointer on an I2S buffer. + * + */ +typedef void (*I2S_RegUpdate)(uint32_t ui32Base, uint32_t ui32NextPointer); + +/*! + * @brief The definition of a function used to stop an I2S interface + * + * @param I2S_Handle I2S_Handle + * + */ +typedef void (*I2S_StopInterface)(I2S_Handle handle); + +/*! + * @brief I2S slot memory length setting + * + * The enum defines if the module uses a 16 bits or a 24 bits buffer in memory. + * This value has no influence on the number of bits transmitted, but it should + * be consistent with the chosen word length. + * + * @warning Not all devices support all of the listed memory lengths. Please + * refer to the device-specific documentation for possible limitations. + */ +typedef enum +{ + + I2S_MEMORY_LENGTH_8BITS = 8U, /*!< Buffer used is 8 bits length. */ + I2S_MEMORY_LENGTH_16BITS = 16U, /*!< Buffer used is 16 bits length. */ + I2S_MEMORY_LENGTH_24BITS = 24U, /*!< Buffer used is 24 bits length. */ + I2S_MEMORY_LENGTH_32BITS = 32U /*!< Buffer used is 32 bits length. */ + +} I2S_MemoryLength; + +/*! + * @brief I2S controller / target selection + * + * The enum defines if the module acts like a controller (clocks are internally generated) + * or a target (the clocks are externally generated). + */ +typedef enum +{ + + I2S_TARGET = 0, /*!< Module is a target, clocks are externally generated. */ + I2S_CONTROLLER = 1 /*!< Module is a controller, clocks are internally generated. */ + +} I2S_Role; + +/*! + * @brief I2S sampling setting + * + * The enum defines if sampling is done on BLCK rising or falling edges. + */ +typedef enum +{ + + /*! + * @brief Sampling on falling edges. + * + * For DSP data format. + */ + I2S_SAMPLING_EDGE_FALLING = 0, + + /*! + * @brief Sampling on rising edges. + * + * For Inter-IC Sound (I2S), Left Justified (LJF) and Right Justified (RJF) + * data formats. + */ + I2S_SAMPLING_EDGE_RISING = 1, +} I2S_SamplingEdge; + +/*! + * @brief I2S phase setting + * + * The enum defines if the I2S if set with single or dual phase. + * + * @warning Not all devices support all of the listed phase types. Please + * refer to the device-specific documentation for possible limitations. + */ +typedef enum +{ + /*! + * @brief Single phase + * + * For DSP format. + * Up to eight channels are usable. + */ + I2S_PHASE_TYPE_SINGLE = 0U, + + /*! + * @brief Dual phase + * + * For Inter-IC Sound (I2S), Left Justified (LJF) and Right Justified (RJF) + * data formats. + * Up to two channels are usable. + */ + I2S_PHASE_TYPE_DUAL = 1U, + +} I2S_PhaseType; + +/*! + * @brief I2S data interface configuration + * + * The enum defines the different settings for the data interfaces (SD0 and SD1). + */ +typedef enum +{ + + I2S_SD0_DISABLED = 0x00U, /*!< SD0 is disabled */ + I2S_SD0_INPUT = 0x01U, /*!< SD0 is an input */ + I2S_SD0_OUTPUT = 0x02U, /*!< SD0 is an output */ + I2S_SD1_DISABLED = 0x00U, /*!< SD1 is disabled */ + I2S_SD1_INPUT = 0x10U, /*!< SD1 is an input */ + I2S_SD1_OUTPUT = 0x20U /*!< SD1 is an output */ + +} I2S_DataInterfaceUse; + +/*! + * @brief Channels used selection + * + * The enum defines different settings to activate the expected channels. + + * For dual phase mode, the following can be used: + * - #I2S_CHANNELS_NONE + * - #I2S_CHANNELS_MONO + * - #I2S_CHANNELS_MONO_INV + * - #I2S_CHANNELS_STEREO + * . + * For single phase mode, the following can be used: + * - #I2S_1_CHANNEL + * - #I2S_2_CHANNELS + * - #I2S_3_CHANNELS + * - #I2S_4_CHANNELS + * - #I2S_5_CHANNELS + * - #I2S_6_CHANNELS + * - #I2S_7_CHANNELS + * - #I2S_8_CHANNELS + * - #I2S_CHANNELS_ALL + */ +typedef enum +{ + + /*! + * @brief No channel activated + * + * - read: I2S does not receive anything (no buffer consumption) + * - write: I2S does not send anything (no buffer consumption) + */ + I2S_CHANNELS_NONE = 0x00U, + + /*! + * @brief Only channel 1 is activated + * + * - read: I2S only reads channel 1 + * - write: I2S transmits the data on channel 1 and duplicates it on + * channel 2 + */ + I2S_CHANNELS_MONO = 0x01U, + + /*! + * @brief Only channel 2 is activated + * + * - read: I2S only reads channel 2 + * - write: I2S transmits the data on channel 2 and duplicates it on + * the channel 1 of the next word + */ + I2S_CHANNELS_MONO_INV = 0x02U, + + /*! + * @brief Channels 1 and 2 are activated + * + * - read: I2S reads both channel 1 and channel 2 + * - write: I2S transmits data both on channel 1 and channel 2 + */ + I2S_CHANNELS_STEREO = 0x03U, + + I2S_1_CHANNEL = 0x01U, /*!< 1 channel is activated */ + I2S_2_CHANNELS = 0x03U, /*!< 2 channels are activated */ + I2S_3_CHANNELS = 0x07U, /*!< 3 channels are activated */ + I2S_4_CHANNELS = 0x0FU, /*!< 4 channels are activated */ + I2S_5_CHANNELS = 0x1FU, /*!< 5 channels are activated */ + I2S_6_CHANNELS = 0x3FU, /*!< 6 channels are activated */ + I2S_7_CHANNELS = 0x7FU, /*!< 7 channels are activated */ + I2S_8_CHANNELS = 0xFFU, /*!< 8 channels are activated */ + I2S_CHANNELS_ALL = 0xFFU /*!< All the eight channels are activated */ + +} I2S_ChannelConfig; + +/*! + * @brief Basic I2S Parameters + * + * I2S parameters are used to with the I2S_open() call. Default values for + * these parameters are set using I2S_Params_init(). + * + * @sa I2S_Params_init() + */ +typedef struct +{ + + /*! + * Activate "true I2S format". + * - false: Data are read/write on the data lines from the first SCK + * period of the WS half-period to the last SCK edge of the WS + * half-period. + * - true: Data are read/write on the data lines from the second SCK + * period of the WS half-period to the first SCK edge of the next + * WS half-period. If no padding is activated, this corresponds + * to the I2S standard. + */ + bool trueI2sFormat; + + /*! + * WS must be internally inverted when using I2S data format. + * - false: The WS signal is not internally inverted. + * - true: The WS signal is internally inverted. + */ + bool invertWS; + + /*! + * Endianness selection. + * - false: The samples are transmitted LSB first. + * - true: The samples are transmitted MSB first. + * + * @warning Not all devices support selecting endianness. Please refer to + * the device-specific documentation for possible limitations. + */ + bool isMSBFirst; + + /*! + * Selection between DMA transmissions and CPU transmissions. + * - false: Transmission are performed by DMA. + * - true: Transmission are performed by CPU. + * + * @warning Not all devices support selecting between DMA and CPU + * transmissions. Please refer to the device-specific documentation for + * possible limitations. + */ + bool isDMAUnused; + + /*! + * Width of stored samples. It should be consistent with the word length. + */ + I2S_MemoryLength memorySlotLength; + + /*! + * Number of SCK periods between the first WS edge and the MSB of the first + * audio channel data transferred during the phase. + */ + uint8_t beforeWordPadding; + + /*! + * Number of SCK periods between the LSB of the an audio channel and the + * MSB of the next audio channel. + */ + uint8_t afterWordPadding; + + /*! Bits per sample (Word length): must be between 8 and 24 bits. */ + uint8_t bitsPerWord; + + /*! + * Select if the I2S module is a Target or a Controller. + */ + I2S_Role moduleRole; + + /*! + * Select edge sampling type. + */ + I2S_SamplingEdge samplingEdge; + + /*! + * Select if SD0 is an input, an output or disabled. + * - #I2S_SD0_DISABLED: Disabled. + * - #I2S_SD0_INPUT: Input. + * - #I2S_SD0_OUTPUT: Output. + */ + I2S_DataInterfaceUse SD0Use; + + /*! + * Select if SD1 is an input, an output or disabled. + * - #I2S_SD1_DISABLED: Disabled. + * - #I2S_SD1_INPUT: Input. + * - #I2S_SD1_OUTPUT: Output. + */ + I2S_DataInterfaceUse SD1Use; + + /*! + * This parameter is indicating which channels are valid on SD0. + * Valid channels on SD1 and SD0 can be different. + * + * Refer to #I2S_ChannelConfig for a list of possible values, and for which + * phase types they can be used. + */ + I2S_ChannelConfig SD0Channels; + + /*! + * This parameter is indicating which channels are valid on SD1. + * Valid channels on SD1 and SD0 can be different. + * + * Refer to #I2S_ChannelConfig for a list of possible values, and for which + * phase types they can be used. + */ + I2S_ChannelConfig SD1Channels; + + /*! + * Select phase type. + */ + I2S_PhaseType phaseType; + + /*! + * Number of consecutive bytes of the samples buffers. This field must be + * set to a value x different from 0. All the data buffers used (both for + * input and output) must contain N*x bytes (with N an integer satisfying + * N>0). + */ + uint16_t fixedBufferLength; + + /*! Number of WS periods to wait before the first transfer. */ + uint16_t startUpDelay; + + /*! + * Select the frequency divider for CCLK signal. Final value of CCLK is + * 48MHz/CCLKDivider. Value must be selected + * between 2 and 1024. + */ + uint16_t CCLKDivider; + + /*! + * I2S sampling frequency configuration in samples/second. + * + * The selected sampling frequency must ensure that the SCK frequency will + * be inside of its device-specific limits. Please refer to the device-specific + * documentation for the lower and upper limits of the SCK frequency. + */ + uint32_t samplingFrequency; + + /*! + * Pointer to read callback. Cannot be NULL if a read interface is + * activated. + */ + I2S_Callback readCallback; + + /*! + * Pointer to write callback. Cannot be NULL if a write interface is + * activated. + */ + I2S_Callback writeCallback; + + /*! Pointer to error callback. Cannot be NULL. */ + I2S_Callback errorCallback; + + /*! Pointer to device specific custom params */ + void *custom; +} I2S_Params; + +/*! + * @brief Default I2S_Params structure + * + * @sa I2S_Params_init() + */ +extern const I2S_Params I2S_defaultParams; + +/*! + * @brief Function to close a given I2S peripheral specified by the I2S + * handle. + * + * @pre I2S_open() had to be called first. + * + * @param [in] handle An I2S_Handle returned from I2S_open + * + * @sa I2S_open() + */ +extern void I2S_close(I2S_Handle handle); + +/*! + * @brief Function to initializes the I2S module + * + * @pre The I2S_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other I2S driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void I2S_init(void); + +/*! + * @brief Function to initialize a given I2S peripheral specified by the + * particular index value. The parameter specifies which mode the I2S + * will operate. + * + * @pre I2S controller has been initialized + * + * @param [inout] index Logical peripheral number for the I2S indexed into + * the I2S_config table + * + * @param [in] params Pointer to an parameter block. + * All the fields in this structure are RO (read-only). + * Provide a NULL pointer cannot open the module. + * + * @return An I2S_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa I2S_init() + * @sa I2S_close() + */ +extern I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params); + +/*! + * @brief Function to initialize the I2S_Params struct to its defaults + * + * @param [out] params An pointer to I2S_Params structure for + * initialization + * + * Defaults values are: + * @code + * params.samplingFrequency = 8000; + * params.memorySlotLength = I2S_MEMORY_LENGTH_16BITS; + * params.moduleRole = I2S_CONTROLLER; + * params.trueI2sFormat = (bool)true; + * params.invertWS = (bool)true; + * params.isMSBFirst = (bool)true; + * params.isDMAUnused = (bool)false; + * params.samplingEdge = I2S_SAMPLING_EDGE_RISING; + * params.beforeWordPadding = 0; + * params.bitsPerWord = 16; + * params.afterWordPadding = 0; + * params.fixedBufferLength = 1; + * params.SD0Use = I2S_SD0_OUTPUT; + * params.SD1Use = I2S_SD1_INPUT; + * params.SD0Channels = I2S_CHANNELS_STEREO; + * params.SD1Channels = I2S_CHANNELS_STEREO; + * params.phaseType = I2S_PHASE_TYPE_DUAL; + * params.startUpDelay = 0; + * params.CCLKDivider = 40; + * params.readCallback = NULL; + * params.writeCallback = NULL; + * params.errorCallback = NULL; + * params.custom = NULL; + * @endcode + * + * @param params Parameter structure to initialize + */ +extern void I2S_Params_init(I2S_Params *params); + +/*! + * @brief Initialize an I2S_Transaction struct to known state. + * + * The I2S_Transaction struct is put in a known state. The application is + * still responsible for populating some of the fields. + * For example, the user is responsible to provide the buffer containing the + * data and the size of it. + * User provided buffer's size must matche with the I2S settings. + * If the buffer size is not adapted, the I2S module will truncate it. + * Authorized buffer sizes depend on the number of activated outputs, the number + * of channels activated, the memory slots length (16 or 24 bits), and the + * fixed-buffer-size eventually provided. + * Authorized buffer sizes are all the multiple values of the value of + * handle->object->memoryStepOut. + * + * @param [out] transaction Transaction struct to initialize. + */ +extern void I2S_Transaction_init(I2S_Transaction *transaction); + +/*! + * @brief Function to set the first read-transaction to consider + * + * At the end of each transaction, I2S driver takes in consideration the next + * transaction. Application is responsible to handle the queue. + * + * @param [in] handle An I2S_Handle. + * + * @param [in] transaction A pointer to an I2S_Transaction object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * + * @return void + * + * @sa I2S_setWriteQueueHead() + */ +extern void I2S_setReadQueueHead(I2S_Handle handle, I2S_Transaction *transaction); + +/*! + * @brief Function to set the first write-transaction to consider + * + * At the end of each transaction, I2S driver takes in consideration the next + * transaction. Application is responsible to handle the queue. + * + * @param [in] handle An I2S_Handle. + * + * @param [in] transaction A pointer to an I2S_Transaction object. The bufPtr + * and bufSize fields must be set to a buffer and the + * size of the buffer before passing to this function. + * + * @return void + * + * @sa I2S_setReadQueueHead() + */ +extern void I2S_setWriteQueueHead(I2S_Handle handle, I2S_Transaction *transaction); + +/*! + * @brief Start the WS, SCK and CCLK clocks. + * + * This function enable WS, SCK and CCLK (if activated) clocks. This is required before starting + * any reading or a writing transaction. + * This function is supposed to be executed both in target and controller mode. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_stopClocks() + */ +extern void I2S_startClocks(I2S_Handle handle); + +/*! + * @brief Stops the WS, SCK and CCLK clocks. + * + * This function disable WS, SCK and CCLK clocks. + * This function must be executed only if no transaction is in progress. + * This function is supposed to be executed in a Task context (NOT in a HWI or Callback context). + * This function is supposed to be executed both in target and controller mode. + * + * @warning This function is supposed to be executed in a Task context + * (NOT in a HWI or Callback context). + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_stopRead() + * @sa I2S_stopWrite() + */ +extern void I2S_stopClocks(I2S_Handle handle); + +/*! + * @brief Start read transactions. + * + * This function starts reception of the transactions stored in the read-queue. + * and returns immediately. At the completion of each transaction the readCallback + * provided is executed. + * + * If the queue for read transactions becomes empty (i.e. the read Callback is + * triggered with status #I2S_ALL_TRANSACTIONS_SUCCESS and the application has + * not queued new transactions or defined a new first read-transaction to consider + * using #I2S_setReadQueueHead()), the driver will stop the read interface on its + * own in order to avoid the occurrence of errors (such as #I2S_PTR_READ_ERROR). + * + * @pre First read-transaction to consider must be set and clocks must be running + * before calling this function. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_startClocks() + * @sa I2S_setReadQueueHead() + */ +extern void I2S_startRead(I2S_Handle handle); + +/*! + * @brief Start write transactions. + * + * This function starts transmission of the transactions stored in the write-queue + * and returns immediately. At the completion of each transaction the write Callback + * provided is executed. + * + * If the queue for write transactions becomes empty (i.e. the write Callback is + * triggered with status #I2S_ALL_TRANSACTIONS_SUCCESS and the application has not + * queued new transactions or defined a new first write-transaction to consider using + * #I2S_setWriteQueueHead()), the driver will stop the write interface on its own in + * order to avoid the occurrence of errors (such as #I2S_PTR_WRITE_ERROR). + * + * @pre First write-transaction to consider must be set and clocks must be running + * before calling this function. + * + * @param [in] handle An I2S_Handle. + * + * @return void + * + * @sa I2S_startClocks() + * @sa I2S_setWriteQueueHead() + */ +extern void I2S_startWrite(I2S_Handle handle); + +/*! + * @brief Stop read transactions. + * + * This function stops the reception of read transactions correctly so that + * read operations can be safely restarted later. + * + * The application can decide at any time to suspend the reception of data by calling + * this function. In this case (and because the transaction queue is not empty) the + * execution of #I2S_stopRead() is blocked until the current transaction is completed + * (this ensures that the I2S read interface is correctly stopped). Therefore, this + * function must be executed in a Task context (not in a HWI or Callback context). + * + * After the transfers have been stopped (either by calling #I2S_stopRead() or because + * the queue has been empty), the application can resume the transfers using the + * function #I2S_startRead(). If the read-queue was empty application must beforehand + * set the first read-transaction using #I2S_setReadQueueHead(). + * + * @param [in] handle An I2S_Handle. + * + * @return void + */ +extern void I2S_stopRead(I2S_Handle handle); + +/*! + * @brief Stop write transactions. + * + * This function stops the transmission of write transactions correctly so that + * writing operations can be safely restarted later. + * + * The application can decide at any time to suspend the sending of data by calling + * this function. In this case (and because the transaction queue is not empty) the + * execution of #I2S_stopWrite() is blocked until the current transaction is completed + * (this ensures that the I2S write interface is correctly stopped). Therefore, this + * function must be executed in a Task context (not in a HWI or Callback context). + * + * After the transfers have been stopped (either by calling #I2S_stopWrite() or because + * the queue has been empty), the application can resume the transfers using the + * function #I2S_startWrite(). If the write-queue was empty application must beforehand + * set the first write-transaction using #I2S_setWriteQueueHead(). + * + * @param [in] handle An I2S_Handle. + * + * @return void + */ +extern void I2S_stopWrite(I2S_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2S__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ITM.c b/simplelink_lpf2/source/ti/drivers/ITM.c new file mode 100644 index 00000000..8dc12bd1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ITM.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Standard Includes */ +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#include +#include +#include + +/* Declare the ITM_Object type */ +typedef struct +{ + uint8_t numberOfClients; /* Number of ITM_open calls */ + uint8_t numDwtComparators; /* Number of DWT comparators available */ + uint32_t dwtCtrlRegister; /* Shadow of the DWT CTRL register */ + uint32_t fullFIFOInCycles; /* Number of cycles needed to drain TPIU FIFO */ +} ITM_Object; + +/* Create an instance of the object and initialize it */ +static ITM_Object object = { + .numberOfClients = 0, + .numDwtComparators = 0, + .dwtCtrlRegister = 0, + .fullFIFOInCycles = 0, +}; + +/* This enables the device specific hwAttrs to be case as the generic ones + * The hwAttrs will be generated by syscfg + */ +extern void *itmHwAttrs; + +/** + * This function initializes the ITM hardware. + */ +static void ITM_initHw(void); + +/** + * This function will setup the mux to route the TPIU output to the pin(s) that + * the user has selected in the hwAttrs. + * + */ +extern bool ITM_applyPinMux(void); +/** + * This function will remove any pin mux settings applied by ITM_applyPinMux. + */ +extern void ITM_clearPinMux(void); + +/* + * ======== ITM_open ======== + */ +bool ITM_open(void) +{ + ITM_HWAttrs *hwAttrs = (ITM_HWAttrs *)itmHwAttrs; + uint32_t tpiuFifoSize = 0; + bool pinMuxStatus = false; + uintptr_t hwiKey; + + hwiKey = HwiP_disable(); + + if (object.numberOfClients == 0) + { + /* Mux out the pins that will be used by the TPIU */ + pinMuxStatus = ITM_applyPinMux(); + + /* If we couldn't acquire the pins, give up now */ + if (pinMuxStatus == false) + { + HwiP_restore(hwiKey); + return (bool)false; + } + + /* Initialize ITM Hardware */ + ITM_initHw(); + + /* Store the number of DWT comparators */ + object.numDwtComparators = (HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) & CPU_DWT_CTRL_NUMCOMP_M) >> + CPU_DWT_CTRL_NUMCOMP_S; + + /* Store the FIFO size of the TPIU, this will be used for flush */ + tpiuFifoSize = (HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_DEVID) & CPU_TPIU_DEVID_FIFO_SIZE_M) >> + CPU_TPIU_DEVID_FIFO_SIZE_S; + + /* FIFO size stored in the register as 2^FIFO_SIZE in bytes + * 1. Calculate the power of 2 using left shifts. + * 2. Subtract 2 from the number of positions to shift to convert bytes + * into 32-bit words + */ + tpiuFifoSize = (1 << (tpiuFifoSize - 2)); + + /* Then multiply this by the length of the FIFO */ + object.fullFIFOInCycles = tpiuFifoSize * (hwAttrs->fullPacketInCycles); + } + + /* Increment is open counter to allow multiple open calls */ + object.numberOfClients++; + + HwiP_restore(hwiKey); + + return (bool)true; +} +/* + * ======== ITM_close ======== + */ +void ITM_close(void) +{ + uintptr_t hwiKey; + hwiKey = HwiP_disable(); + + /* Protect against unbalanced number of open/close calls */ + if (object.numberOfClients <= 0) + { + HwiP_restore(hwiKey); + return; + } + + /* If this is the last close call, clean up */ + if (object.numberOfClients == 1) + { + ITM_disableExceptionTrace(); + ITM_disablePCAndEventSampling(); + + /* Disable DWT stimulus. This routes DWT packets to the TPIU */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) &= ~(CPU_ITM_TCR_DWTENA_M); + + /* Disable cycle counter, required to ensure proper flush */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) &= ~CPU_DWT_CTRL_CYCCNTENA_M; + HWREG(ITM_SCS_BASE_ADDR + CPU_SCS_O_DEMCR) &= (~CPU_SCS_DEMCR_TRCENA_M); + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) &= ~((CPU_DWT_CTRL_PCSAMPLEENA_M) | (CPU_DWT_CTRL_EXCTRCENA_M)); + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) &= ~CPU_ITM_TCR_ITMENA; + + /* Flush out any remaining packets to be sent */ + ITM_flush(); + + /* Unmux pins that were in use by the TPIU. This is device specific + * and will reside in the device specific file + */ + ITM_clearPinMux(); + } + + /* Decrement is open counter */ + object.numberOfClients--; + + HwiP_restore(hwiKey); +} + +/* + * ======== ITM_send32Atomic ======== + */ +void ITM_send32Atomic(uint8_t port, uint32_t value) +{ + uint32_t key; + key = HwiP_disable(); + ITM_send32Polling(port, value); + HwiP_restore(key); +} + +/* + * ======== ITM_send16Atomic ======== + */ +void ITM_send16Atomic(uint8_t port, uint16_t value) +{ + uint32_t key; + key = HwiP_disable(); + ITM_send16Polling(port, value); + HwiP_restore(key); +} + +/* + * ======== ITM_send8Atomic ======== + */ +void ITM_send8Atomic(uint8_t port, uint8_t value) +{ + uint32_t key; + key = HwiP_disable(); + ITM_send8Polling(port, value); + HwiP_restore(key); +} + +/* + * ======== ITM_sendBufferAtomic ======== + */ +void ITM_sendBufferAtomic(const uint8_t port, const char *msg, size_t length) +{ + uint32_t key; + key = HwiP_disable(); + /* Unroll the sending of the data to use the optimal port size + * This has a slightly higher flash footprint, but has better performance + * for large buffers. Users who are concerned about flash can consider + * replacing this with a single for loop. Ensure msg is word-aligned before + * proceeding. + */ + while ((length > 0) && ((uint32_t)msg & 0x03)) + { + ITM_send8Polling(port, *msg++); + length--; + } + while (length > 3) + { + /* The cast from uint8_t* to uint32_t* below is safe, due to the loop above */ + ITM_send32Polling(port, *((uint32_t *)msg)); + length -= 4; + msg += 4; + } + while (length > 1) + { + /* The cast from uint8_t* to uint16_t* below is safe, due to the loop above */ + ITM_send16Polling(port, *((uint16_t *)msg)); + length -= 2; + msg += 2; + } + if (length > 0) + { + ITM_send8Polling(port, *msg); + } + + HwiP_restore(key); +} + +/* + * ======== ITM_enableExceptionTrace ======== + */ +void ITM_enableExceptionTrace(void) +{ + /* Enable interrupt event tracing by the DWT */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_EXCTRCENA_M; +} + +/* + * ======== ITM_disableExceptionTrace ======== + */ +void ITM_disableExceptionTrace(void) +{ + /* Disable interrupt event tracing by the DWT */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) &= ~(CPU_DWT_CTRL_EXCTRCENA_M); +} + +/* + * ======== ITM_enablePCSampling ======== + */ +void ITM_enablePCSampling(bool prescale1024, uint8_t postReset) +{ + /* Disable before setup */ + ITM_disablePCAndEventSampling(); + + /* Setup sampling interval by setting reload down counter value */ + if (prescale1024 == (bool)true) + { + /* Tap at bit 10 of system clock, this results in a prescale by 1024 */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_CYCTAP_BIT10; + } + + /* The postreset value is the reload value for the counter */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= ((postReset & 0x0F) << CPU_DWT_CTRL_POSTPRESET_S); + + /* Enable DWT packets in the ITM and cycle counting */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_DWTENA_M; + + /* Enable PC sampling event */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_PCSAMPLEENA_M; +} + +/* + * ======== ITM_enableEventCounter ======== + */ +void ITM_enableEventCounter(bool prescale1024, uint8_t postReset) +{ + /* Clear the PC Sampling and Cycle Event bits */ + ITM_disablePCAndEventSampling(); + /* Setup sampling interval by setting reload down counter value */ + if (prescale1024 == (bool)true) + { + /* Tap at bit 10 of system clock, this results in a prescale by 1024 */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_CYCTAP_BIT10; + } + + /* The postreset value is the reload value for the counter */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= ((postReset & 0x0F) << CPU_DWT_CTRL_POSTPRESET_S); + + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_DWTENA_M; + + /* Enable Cycle Count event */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_CYCEVTENA_M; +} + +/* + * ======== ITM_disablePCAndEventSampling ======== + */ +void ITM_disablePCAndEventSampling(void) +{ + /* Clear the PC Sampling and Cycle Event bits */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) &= ~(CPU_DWT_CTRL_PCSAMPLEENA_M | CPU_DWT_CTRL_CYCEVTENA_M); +} + +/* + * ======== ITM_enableWatchpoint ======== + */ +bool ITM_enableWatchpoint(ITM_WatchpointAction function, const uintptr_t address) +{ + + uint8_t dwtIndex = 0; + bool dwtAvailable = false; + for (dwtIndex = 0; dwtIndex < object.numDwtComparators; dwtIndex++) + { + uint32_t offset = 16 * dwtIndex; + if (0 == (HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_FUNCTION0 + offset) & 0x7FFFFFF)) + { + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_COMP0 + offset) = address; + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_MASK0 + offset) = 0; + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_FUNCTION0 + offset) = function; + dwtAvailable = true; + } + } + return dwtAvailable; +} + +/* + * ======== ITM_enableTiming ======== + */ +void ITM_enableTimestamps(ITM_TimeStampPrescaler tsPrescale, bool asyncMode) +{ + /* Set timestamp prescale value and enable timestamp packet generation */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= ((tsPrescale << CPU_ITM_TCR_TSPRESCALE_S) & CPU_ITM_TCR_TSPRESCALE_M); + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_TSENA_M; + + if (asyncMode == (bool)true) + { + /* Asynchronous vs synchronous mode is controlled by the SWOENA bit */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_SWOENA_M; + } +} + +/* + * ======== ITM_enableSyncPackets ======== + */ +void ITM_enableSyncPackets(ITM_SyncPacketRate syncPacketRate) +{ + /* Clear the synchronous packet rate field */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) &= ~(CPU_DWT_CTRL_SYNCTAP_M); + /* Set sync packet rate */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= ((syncPacketRate << CPU_DWT_CTRL_SYNCTAP_S) & CPU_DWT_CTRL_SYNCTAP_M); + /* Enable sync packet generation */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_SYNCENA_M; +} + +/* + * ======== ITM_flush ======== + */ +void __attribute__((weak)) ITM_flush(void) +{ + /* This function is intentionally blank to save overhead in the power + * policy. When ITM is enabled, the function will be strongly defined by + * syscfg + */ + + /* When populated by syscfg, this function will execute: + * 1. ITM_commonFlush() - This is the common implementation + * 2. Device specific flush e.g. ITMCC26XX_commonFlush + */ +} + +/* + * ======== ITM_restore ======== + */ +void __attribute__((weak)) ITM_restore(void) +{ + /* This function is intentionally blank to save overhead in the power + * policy. When ITM is enabled, the function will be strongly defined by + * syscfg + */ +} + +/* + * ======== ITM_commonFlush ======== + */ +void ITM_commonFlush(void) +{ + if (object.numberOfClients != 0) + { + /* Cache the DWT CTRL register so it can be restored on wake */ + object.dwtCtrlRegister = HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL); + + /* Disable PC sampling so the buffer doesn't fill up */ + ITM_disablePCAndEventSampling(); + + /* Write dummy value to "flush" the FIFO */ + uint32_t dummy = 0xAAAAAAAA; + ITM_send32Atomic(0, dummy); + + /* Wait until the ITM events has drained */ + while (HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) & (1 << 23)) {} + + /* Flush TPIU FIFO + * Now, the ITM is flushed, but the TPIU also has a FIFO to be empty + * There is no flush bit available in the TPIU register set, + * so here we calculate the time needed to drain the FIFO using + * using its size and baudrate + */ + uint32_t ticksNow = HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CYCCNT); + int32_t numTicks = 0; + do + { + int32_t tmp = HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CYCCNT) - ticksNow; + + /* Consider the case where the DWT timer has wrapped */ + if (tmp < 0) + { + tmp += 0xFFFFFFFF; + } + + /* Increase the accumulated ticks */ + numTicks += tmp; + + /* Update the current time */ + ticksNow = HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CYCCNT); + } while ((numTicks < object.fullFIFOInCycles)); + + /* Disable ITM */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) &= ~CPU_ITM_TCR_ITMENA; + } +} + +/* + * ======== ITM_commonRestore ======== + */ +void ITM_commonRestore(void) +{ + /* Only if currently used ... */ + if (object.numberOfClients != 0) + { + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + /* For CC27XX devices, the CPU sub-system is reset in standby, and the + * ITM must thus be re-initialized. + */ + ITM_initHw(); +#endif + + /* Enable ITM */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_ITMENA; + + /* Restore the DWT CTRL register */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= object.dwtCtrlRegister; + } +} + +/* + * ======== ITM_initHw ======== + */ +static void ITM_initHw(void) +{ + ITM_HWAttrs *hwAttrs = (ITM_HWAttrs *)itmHwAttrs; + + /* Disable ITM and trace hardware as we're about to set it up again */ + HWREG(ITM_SCS_BASE_ADDR + CPU_SCS_O_DEMCR) &= (~CPU_SCS_DEMCR_TRCENA_M); + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) = 0x00000000; + + /* Enable trace */ + HWREG(ITM_SCS_BASE_ADDR + CPU_SCS_O_DEMCR) |= CPU_SCS_DEMCR_TRCENA_M; + + /* Unlock and Setup TPIU for SWO UART mode */ + HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_LAR) = ITM_LAR_UNLOCK; + HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_SPPR) = hwAttrs->format; + HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_CSPSR) = CPU_TPIU_CSPSR_ONE; + + /* Unlock and enable all ITM stimulus ports with default settings */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_LAR) = ITM_LAR_UNLOCK; + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TER) = hwAttrs->traceEnable; + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TPR) = 0x0000000F; + + /* Program prescaler value which is calculated from SysConfig */ + HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_ACPR) = hwAttrs->tpiuPrescaler; + + /* Disable formatter */ + HWREG(ITM_TPIU_BASE_ADDR + CPU_TPIU_O_FFCR) = 0; + + /* Unlock DWT */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_LAR) = ITM_LAR_UNLOCK; + + /* Enable cycle counter, required to ensure proper flush */ + HWREG(ITM_DWT_BASE_ADDR + CPU_DWT_O_CTRL) |= CPU_DWT_CTRL_CYCCNTENA_M; + + /* Enable ITM */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_ITMENA; + + /* Enable DWT stimulus. This routes DWT packets to the TPIU */ + HWREG(ITM_BASE_ADDR + CPU_ITM_O_TCR) |= CPU_ITM_TCR_DWTENA_M; +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/ITM.h b/simplelink_lpf2/source/ti/drivers/ITM.h new file mode 100644 index 00000000..8ce27fb2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ITM.h @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file ITM.h + * @brief ITM driver header + * + * @anchor ti_drivers_ITM_Overview + *

Overview

+ * This driver implements APIs to configure and control the ARM Instrumentation + * Trace Macrocell (ITM), Debug Watchpoint and Trace (DWT), and Trace Port + * Instrumentation Unit (TPIU) IPs to realize non-intrusive software logging + * and runtime trace. + * + * # Overview + * The ITM software module provides application level APIs for the non-invasive + * debug capabilities of the ARM Cortex-M family. This includes the following + * hardware modules: + * + * - Instrumentation Trace Macrocell (ITM) + * - Debug Watchpoint and Trace (DWT) + * - Trace Port Instrumentation Unit (TPIU) + * + * At a high level, the DWT provides watchpoint, data trace, and program + * counter sampling. The ITM provides memory mapped registers for low-intrusion + * software profiling. The TPIU provides an external interface for the ITM and + * DWT. Further details can be found in the + * [ARMv7-M Architecture Reference Manual](https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf) + * + *

Limitations and Constraints

+ * The driver is is designed with the following constraints in mind: + * - ITM is designed as a singleton. This means that a single instance is + * shared across all clients + * - The parallel TracePort mode of the TPIU is not supported, only + * serial protocols are considered + * - The ITM hardware is configured via firmware on the DUT. + * Log records can be read independent of any IDE or debugger configuration. + * This means that if the IDE debug system configures the ITM, it should + * be turned off. + * - In Code Composer Studio, it is not currently possible to disable + * the debugger configuration mentioned above. No ITM output will be visible + * while the IDE's debugger is connected. Please flash your firmware, then + * disconnect and reset the device to see ITM data on the serial port. + * + * @anchor ti_drivers_ITM_Setup + *

Setup

+ * The ITM is configured via hardware attributes stored in the hardware + * attributes structure. This structure contains a common portion that is used + * for all drivers. This structure may be extended for some devices such as + * CC26XX. + * + *

Opening the driver

+ * Unlike other drivers, the ITM is intended to be a singleton. + * This means that @ref ITM_open can be called multiple times. + * The ITM will only be configured the first time open is called. + * + * Furthermore, helper functions for features such as PC sampling must coherent + * across clients. The driver offers no protection against mismatched + * configuration. + * + * The open call will enable ITM as well as the necessary stimulus ports. + * It will setup the TPIU for necessary baudrate and serial format. + * + * @anchor ti_drivers_ITM_PinMux + *

Pin Muxing

+ * As the ITM driver is primarily interfacing to ARM defined IP, it is almost + * entirely common across all supported devices. The only specifics are pin + * muxing of the SWO pin. See the table below for some notes + + * | Device Family | Debug Protocol | Muxing | Configurable? | + * |---------------|----------------|-----------------|---------------| + * | CC13XX/CC26XX | JTAG/cJTAG | Any pin | Y | + * + * Device specific pin muxing is done by the device specific ITM backend + * implementation. + * + * @anchor ti_drivers_ITM_SwMessages + *

Software Messages

+ * The ITM stimulus ports enable serialization of application data with low + * overhead. There are multiple ports available, they are selectable via + * software. + * + * Data written to the software stimulus ports is serialized by the TPIU + * and wrapped in the SWIT packet format. This packet format is standardized + * by ARM and described in [ARMv7-M Architecture Reference + Manual](https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf) + * + * There are three tiers of access to the stimulus ports. In the table below, + * polled access means that the API/macro will poll the port's busy flag + * before writing. This is done to prevent silent data loss that + * occurs when writing to a port that is not ready. Actual serialization of the + * data will occur later inside the TPIU. + * + * - ITM_PortX - Macro to write or read to the port, doesn't poll before + * - ITM_sendXPolling - Macro that polls and writes to the port + * - ITM_sendXAtomic - Function that calls ITM_sendXPolling with interrupts + * disabled + * + * It is up the the application writer to understand the tradeoff associated + * with each of these and select the correct one. + * + *

DWT Features

+ * The Data Watchpoint and Trace (DWT) module is capable of many + * instrumentation features such as + * + * | Feature | ITM API | + * |--------------------------|-------------------------------------| + * | Exception trace | @ref ITM_enableExceptionTrace | + * | Program Counter sampling | @ref ITM_enablePCSampling | + * | Event counting | @ref ITM_enableEventCounter | + * | Synchronization packets | @ref ITM_enableSyncPackets | + * + * + * Data generated by the DWT is serialized via the TPIU. DWT packet formats + * are defined in the ARMv7-M Architecture Reference Manual referenced above + * + *

Flush

+ * The ITM/DWT/TPIU hardware resides in the CPU power domain. This means that + * whenever the CPU domain is powered down, ITM will power down. + * Powering down when data is inside in the TPIU can result in lost data. + * In order to prevent dataloss, the device's power policy will flush the + * ITM before powering down the CPU domain. When returning from sleep, the + * power policy will restore the ITM. This is achieved using the + * @ref ITM_flush and @ref ITM_restore. + * + * These functions are weakly defined as empty functions. This reduces the + * overhead in the power policy when ITM is not enabled. These weak functions + * are overridden by syscfg when ITM is enabled. + * + */ + +#ifndef ti_drivers_ITM__include +#define ti_drivers_ITM__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Base address of the Instrumentation Trace Macrocell (ITM) module + * + */ +#define ITM_BASE_ADDR (0xE0000000) + +/** + * @brief Base address of the Debug Watchpoint and Trace (DWT) module + * + */ +#define ITM_DWT_BASE_ADDR (0xE0001000) + +/** + * @brief Base address of the CPU_SCS module + * + */ +#define ITM_SCS_BASE_ADDR (0xE000E000) + +/** + * @brief Base address of the Trace Port Instrumentation Unit (TPIU) module + * + */ +#define ITM_TPIU_BASE_ADDR (0xE0040000) + +/** + * @brief Value to unlock ARM debug modules. This value should be written to + * the Lock Access Registers (LAR) in order to enable their + * configuration and use + * + */ +#define ITM_LAR_UNLOCK (0xC5ACCE55) + +/** + * @brief Device-specific values that implement the generic ITM-functions + * in ITM_WatchpointAction + * + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #define ITM_FUNCTION_DISABLED (0x00) + #define ITM_FUNCTION_EMIT_PC (0x30 | 0x4) + #define ITM_FUNCTION_EMIT_DATA_ON_READ_WRITE (0x800 | 0x20 | 0xc) + #define ITM_FUNCTION_EMIT_PC_ON_READ_WRITE (0x800 | 0x30 | 0x2) + #define ITM_FUNCTION_EMIT_DATA_ON_READ (0x800 | 0x20 | 0xe) + #define ITM_FUNCTION_EMIT_DATA_ON_WRITE (0x800 | 0x20 | 0xd) + #define ITM_FUNCTION_EMIT_PC_AND_DATA_ON_READ (0x800 | 0x30 | 0xe) + #define ITM_FUNCTION_EMIT_PC_AND_DATA_ON_WRITE (0x800 | 0x30 | 0xd) +#else + #define ITM_FUNCTION_DISABLED 0x00 + #define ITM_FUNCTION_EMIT_PC 0x01 + #define ITM_FUNCTION_EMIT_DATA_ON_READ_WRITE 0x02 + #define ITM_FUNCTION_EMIT_PC_ON_READ_WRITE 0x03 + #define ITM_FUNCTION_EMIT_DATA_ON_READ 0x0C + #define ITM_FUNCTION_EMIT_DATA_ON_WRITE 0x0D + #define ITM_FUNCTION_EMIT_PC_AND_DATA_ON_READ 0x0E + #define ITM_FUNCTION_EMIT_PC_AND_DATA_ON_WRITE 0x0F +#endif + +/** + * @brief Write a 32-bit word to stimulus port n + * + * @warning This does not does not first poll the port for availability. + * + */ +#define ITM_port32(n) (*((volatile unsigned int *)(ITM_BASE_ADDR + 4 * n))) + +/* The do {} while() loops below are to protect the macros so that they're + * evaluated correctly regardless of the call site. They do not have any + * function besides ensuring that the syntax is preserved correctly by the pre + * processor. + */ +/** + * @brief Write a 32-bit word to stimulus port n with polling + * + * @warning This macro does not guarantee atomic access between poll and write + * + */ +#define ITM_send32Polling(n, x) \ + do \ + { \ + while (0 == ITM_port32(n)) \ + ; \ + ITM_port32(n) = x; \ + } while (0) + +/** + * @brief Write a 16-bit half word to stimulus port n + * + * @warning This does not does not first poll the port for availability. + */ +#define ITM_port16(n) (*((volatile unsigned short *)(ITM_BASE_ADDR + 4 * n))) + +/** + * @brief Write a 16-bit word to stimulus port n with polling + * + * @warning This macro does not guarantee atomic access between poll and write + * + */ +#define ITM_send16Polling(n, x) \ + do \ + { \ + while (0 == ITM_port16(n)) \ + ; \ + ITM_port16(n) = x; \ + } while (0) + +/** + * @brief Write a byte to stimulus port n + * + * @warning This does not does not first poll the port for availability. + */ +#define ITM_port8(n) (*((volatile unsigned char *)(ITM_BASE_ADDR + 4 * n))) + +/** + * @brief Write a 8-bit word to stimulus port n with polling + * + * @warning This macro does not guarantee atomic access between poll and write + * + */ +#define ITM_send8Polling(n, x) \ + do \ + { \ + while (0 == ITM_port8(n)) \ + ; \ + ITM_port8(n) = x; \ + } while (0) + +typedef enum +{ + ITM_TPIU_SWO_MANCHESTER = 0x00000001, /*!< Serial format is manchester */ + ITM_TPIU_SWO_UART = 0x00000002, /*!< Serial format is UART */ +} ITM_TPIU_PortFormat; + +/*! @cond NODOC */ +/* This enables a common defintion of the hwAttrs structure that can be easily + * extended by the device specific implementations. This structure defintion + * must be the first line of any device specific structure + */ +#define ITM_BASE_HWATTRS \ + ITM_TPIU_PortFormat format; /* Wire interface used by TPIU */ \ + uint32_t traceEnable; /* Bitmask of enabled stimulus ports */ \ + uint32_t tpiuPrescaler; /* Baudrate to be used by the TPIU */ \ + uint32_t fullPacketInCycles; /* Cycles in a full word */ \ +/*! @endcond */ + +/*! + * @brief ITM Hardware Attributes + * + * ITM hardware attributes should be included in the board file or syscfg + * generated file and provides constant hardware specific configuration. + */ +typedef struct +{ + ITM_BASE_HWATTRS +} ITM_HWAttrs; + +/** + * @brief Control the action taken by the DWT on comparator match + */ +typedef enum +{ + ITM_Disabled = ITM_FUNCTION_DISABLED, /*!< Disabled */ + ITM_EmitPc = ITM_FUNCTION_EMIT_PC, /*!< Emit Program Counter */ + ITM_EmitDataOnReadWrite = ITM_FUNCTION_EMIT_DATA_ON_READ_WRITE, /*!< Emit Data on Read or Write */ + ITM_SamplePcAndEmitDataOnReadWrite = ITM_FUNCTION_EMIT_PC_ON_READ_WRITE, /*!< Emit Program Counter on Read or Write + */ + ITM_SampleDataOnRead = ITM_FUNCTION_EMIT_DATA_ON_READ, /*!< Sample Data on Read */ + ITM_SampleDataOnWrite = ITM_FUNCTION_EMIT_DATA_ON_WRITE, /*!< Sample Data on Write */ + ITM_SamplePcAndDataOnRead = ITM_FUNCTION_EMIT_PC_AND_DATA_ON_READ, /*!< Sample PC and Data on Read */ + ITM_SamplePcAndDataOnWrite = ITM_FUNCTION_EMIT_PC_AND_DATA_ON_WRITE, /*!< Sample PC and Data on Write */ +} ITM_WatchpointAction; + +/** + * @brief Prescaler for ITM timestamp generation based on the trace packet + * reference clock + */ +typedef enum +{ + ITM_TS_DIV_NONE = 0, /*!< No division */ + ITM_TS_DIV_4 = 1, /*!< Divide by 4 */ + ITM_TS_DIV_16 = 2, /*!< Divide by 16 */ + ITM_TS_DIV_64 = 3 /*!< Divide by 64 */ +} ITM_TimeStampPrescaler; +/** + * @brief Synchronous packet generation rate based on cycles of CYCCNT + * This controls how often sync packets will be generated. + * The tap controls which bit transition in the counter triggers a packet + */ +typedef enum +{ + ITM_SYNC_NONE = 0, /*!< Disabled */ + ITM_SYNC_TAP_BIT24 = 1, /*!< Tap the CYCCNT register at bit 24 */ + ITM_SYNC_TAP_BIT26 = 2, /*!< Tap the CYCCNT register at bit 26 */ + ITM_SYNC_TAP_BIT28 = 3 /*!< Tap the CYCCNT register at bit 28 */ +} ITM_SyncPacketRate; + +/** + * @brief Open and configure the ITM, DWT, and TPIU. This includes muxing + * pins as needed + * + * @return true - The ITM was successfully configured and the pins were acquired + * @return false - Pin muxing failed and the ITM was not configured + */ +extern bool ITM_open(void); + +/** + * Disable the ITM, when it is no longer in use, it will be shutdown. + * This will also turn off any additional features that were enabled such as + * PC sampling or interrupt tracing + * + * @sa ITM_open() + */ +extern void ITM_close(void); + +/** + * @brief Write the contents of a buffer to the stimulus port, polling to ensure + * the port is available + * + * @warning This API will disable interrupts for the entire buffer duration + * Use it cautiously to prevent negatively impacting interrupt latency + * + * @param port The stimulus port to use + * @param msg Data to send. + * @param length length of buffer in bytes + */ +extern void ITM_sendBufferAtomic(const uint8_t port, const char *msg, size_t length); + +/** + * @brief Write a 32-bit word to the given stimulus port, polling to ensure the + * port is available + * + * @param port The stimulus port to use + * @param value The 32-bit value to write + */ +extern void ITM_send32Atomic(uint8_t port, uint32_t value); + +/** + * @brief Write a 16-bit short to the given stimulus port, polling to ensure the + * port is available + * + * @param port The stimulus port to use + * @param value The 16-bit value to write + */ +extern void ITM_send16Atomic(uint8_t port, uint16_t value); + +/** + * @brief Write an 8-bit byte to the given stimulus port, polling to ensure the + * port is available + * + * @param port The stimulus port to use + * @param value The 8-bit value to write + */ +extern void ITM_send8Atomic(uint8_t port, uint8_t value); + +/** + * @brief Enable exception tracing + * This will trigger the DWT to generate packets when the device + * enters or leaves an exception. The ITM will forward these packets + * to the TPIU to be sent to the debugger. + * + */ +extern void ITM_enableExceptionTrace(void); + +/** + * @brief Disable exception tracing. + * + * @sa ITM_enableExceptionTrace() + * + */ +extern void ITM_disableExceptionTrace(void); + +/** + * + * @brief Enable periodic sampling of the program counter using the DWT + * POSTCNT timer. + * + * @param prescale1024 true: divide system clock by 1024 to generate POSTCNT + * false: divide system clock by 64 to generate POSTCNT + * @param postReset 4-bit downcounter that is reloaded on POSTCNT expiration + * + * @note PC sampling and event counting are mutally exclusive. + * It is not recommended to call @ref ITM_enableEventCounter() + * after this API has been called + * + */ +extern void ITM_enablePCSampling(bool prescale1024, uint8_t postReset); + +/** + * @brief Enable generation of event counter packets using the DWT + * POSTCNT timer. + * + * @param prescale1024 true: divide system clock by 1024 to generate POSTCNT + * false: divide system clock by 64 to generate POSTCNT + * @param postReset 4-bit downcounter that is reloaded on POSTCNT expiration + * + * @note PC sampling and event counting are mutally exclusive. + * It is not recommended to call @ref ITM_enablePCSampling() + * after this API has been called + */ +extern void ITM_enableEventCounter(bool prescale1024, uint8_t postReset); + +/** + * @brief Disable program counter and event sampling in the DWT + * + * @sa ITM_enablePCSampling(), ITM_enableEventCounter + * + */ +extern void ITM_disablePCAndEventSampling(void); + +/** + * @brief Enable the generation of local timestamp packets from the ITM module + * These are packets sent form the ITM that measure how long it has been + * since the previous timestamp + * + * @param tsPrescale Prescaler value for the timestamp clock. + * @param asyncMode true: Synchronous mode - generate timestamps by dividing + * the system clock. + false: Asynchronous mode - generate timestamps by dividing + * the TPIU clock. + */ +extern void ITM_enableTimestamps(ITM_TimeStampPrescaler tsPrescale, bool asyncMode); + +/** + * @brief Enable the generation of synchronization packets from the ITM + * based on the CYCCNT counter. Synchronization packets can be used + * to recover bit-to-byte alignment information in a serial data stream + * + * @warning When using the TPIU as a asynchronous serial trace port + * ARM recommends disabling these packets to reduce stream bandwith. + * + * @param syncPacketRate Tap for CYCCNT. Controls the frequency of sync packets. + */ +extern void ITM_enableSyncPackets(ITM_SyncPacketRate syncPacketRate); + +/** + * @brief Enable the watchpoint functionality using a DWT comparator + * + * @param function The DWT_FUNCTION field to be programmed. + * This controls what data is emitted on comparator match + * see @ref ITM_WatchpointAction for possible values + * @param address The address for the comparator to match on + * @return true The watchpoint was successfully set + * @return false There was no watchpoint available (all are in use) + */ +extern bool ITM_enableWatchpoint(ITM_WatchpointAction function, const uintptr_t address); + +/** + * @brief Flush the ITM in preparation for power off of CPU domain + * + * This will disable PC sampling, and other DWT features, flush the fifo + * and (if applicable) setup the PIN as a GPIO. + * + * @warning This function should not be called from ISR context + * + * @note This function is invoked by the DPL power policy right before + * entering IDLE/DEEPSLEEP. By default it is an empty stub so that the + * power policy doesn't incur the flush overhead when ITM isn't used. + * When ITM is enabled this function will be strongly defined by SYSCFG. + * + */ +extern void __attribute__((weak)) ITM_flush(void); + +/** + * @brief Prepare the ITM hardware to return from power off of CPU domain + * This will reenable DWT features, re apply the ITM pin mux + * + * @warning This function should not be called from ISR context + * + * @note This function is invoked by the DPL power policy right after + * leaving IDLE/DEEPSLEEP. By default it is an empty stub so that the + * power policy doesn't incur the flush overhead when ITM isn't used. + * When ITM is enabled this function will be strongly defined by SYSCFG. + */ +extern void __attribute__((weak)) ITM_restore(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ITM__include */ diff --git a/simplelink_lpf2/source/ti/drivers/NVS.c b/simplelink_lpf2/source/ti/drivers/NVS.c new file mode 100644 index 00000000..1b68a0e7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/NVS.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVS.c ======== + */ +#include +#include +#include +#include + +#include +#include + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +static bool isInitialized = false; + +/* Default NVS parameters structure */ +const NVS_Params NVS_defaultParams = { + NULL /* custom */ +}; + +/* + * ======== NVS_close ======= + */ +void NVS_close(NVS_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== NVS_control ======== + */ +int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== NVS_erase ======= + */ +int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size) +{ + return (handle->fxnTablePtr->eraseFxn(handle, offset, size)); +} + +/* + * ======== NVS_getAttrs ======= + */ +void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + handle->fxnTablePtr->getAttrsFxn(handle, attrs); +} + +/* + * ======== NVS_init ======= + */ +void NVS_init(void) +{ + uint_least8_t i; + + /* Call each driver's init function */ + for (i = 0; i < NVS_count; i++) + { + NVS_config[i].fxnTablePtr->initFxn(); + } + + isInitialized = true; +} + +/* + * ======== NVS_lock ======= + */ +int_fast16_t NVS_lock(NVS_Handle handle, uint32_t timeout) +{ + return (handle->fxnTablePtr->lockFxn(handle, timeout)); +} + +/* + * ======== NVS_open ======= + */ +NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params) +{ + NVS_Handle handle = NULL; + + /* do init if not done yet */ + if (!isInitialized) + { + NVS_init(); + } + + if (index < NVS_count) + { + if (params == NULL) + { + /* No params passed in, so use the defaults */ + params = (NVS_Params *)&NVS_defaultParams; + } + handle = NVS_config[index].fxnTablePtr->openFxn(index, params); + } + + return (handle); +} + +/* + * ======== NVS_Params_init ======= + */ +void NVS_Params_init(NVS_Params *params) +{ + *params = NVS_defaultParams; +} + +/* + * ======== NVS_read ======= + */ +int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize) +{ + return (handle->fxnTablePtr->readFxn(handle, offset, buffer, bufferSize)); +} + +/* + * ======== NVS_unlock ======= + */ +void NVS_unlock(NVS_Handle handle) +{ + handle->fxnTablePtr->unlockFxn(handle); +} + +/* + * ======== NVS_write ======= + */ +int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags) +{ + return (handle->fxnTablePtr->writeFxn(handle, offset, buffer, bufferSize, flags)); +} diff --git a/simplelink_lpf2/source/ti/drivers/NVS.h b/simplelink_lpf2/source/ti/drivers/NVS.h new file mode 100644 index 00000000..fd407956 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/NVS.h @@ -0,0 +1,847 @@ +/* + * Copyright (c) 2015-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file NVS.h + * @brief Non-Volatile Storage driver interface + * + * @anchor ti_drivers_NVS_Overview + * # Overview # + * + * The NVS module allows you to manage non-volatile memory. Using the + * NVS APIs, you can read and write data from and to persistent storage. + * + * Each NVS object is used to manage a region of non-volatile memory. + * The size of the region is specified in the device specific driver's + * hardware attributes. + * A sector is the smallest unit of non-volatile storage that can be erased + * at one time. The size of the sector, or sector size, is hardware specific + * and may be meaningless for some non-volatile storage hardware. For flash + * memory devices, the region must be aligned with the sector size. That is, + * the region must start on a sector boundary. Additionally, the overall size + * of the region must be an integer multiple of the sector size. + * + *
+ * @anchor ti_drivers_NVS_Usage + * # Usage + * + * This section provides a basic @ref ti_drivers_NVS_Synopsis + * "usage summary" and a set of @ref ti_drivers_NVS_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + + * The NVS driver interface provides device independent APIs, data types, + * and macros. The following code example opens an NVS region instance, + * writes a string into it, then prints the string after reading it back + * into a local buffer, and also prints the string from its directly + * addressable location in flash memory. + * + * @anchor ti_drivers_NVS_Synopsis + * ## Synopsis + * @anchor ti_drivers_NVS_Synopsis_Code + * @code + * // Import NVS Driver definitions + * #include + * + * // One time init of NVS driver + * NVS_init(); + * + * // Initialize optional NVS parameters + * NVS_Params_init(&nvsParams); + * + * // Open NVS driver instance + * nvsRegion = NVS_open(config_NVS0, &nvsParams); + * + * // write "Hello" to the base address of region 0, verify after write + * status = NVS_write(nvsRegion, 0, "Hello", strlen("Hello")+1, NVS_WRITE_POST_VERIFY); + * + * // Close NVS region + * NVS_close(nvsRegion); + * + * @endcode + * + *
+ * @anchor ti_drivers_NVS_Examples + * # Examples + * + * @li @ref ti_drivers_NVS_Examples_open "Opening an NVS region instance" + * @li @ref ti_drivers_NVS_Examples_typical "Typical NVS region operations" + * + * @anchor ti_drivers_NVS_Examples_open + * ## Opening an NVS region instance + * + * @code + * NVS_Handle nvsRegion; + * NVS_Params nvsParams; + * + * NVS_Params_init(&nvsParams); + * nvsRegion = NVS_open(CONFIG_NVS0, &nvsParams); + * @endcode + * + * @anchor ti_drivers_NVS_Examples_typical + * ## Erasing, writing, reading an NVS region + * + * The following code example opens an NVS region instance, erases the first + * sector of that region, writes a string into it, then prints the string + * after reading it back into a local buffer. If the string is directly CPU + * addressable (i.e. not in SPI flash), the string is printed from + * its location in flash memory. + * + * @code + * + * // Import NVS Driver definitions + * #include + * + * NVS_Handle nvsRegion; + * NVS_Attrs regionAttrs; + * + * uint_fast16_t status; + * char buf[32]; + * + * // initialize the NVS driver + * NVS_init(); + * + * // + * // Open the NVS region specified by the 0th element in the NVS_config[] + * // array defined in ti_drivers_config.c. + * // + * // Use default NVS_Params to open this memory region, hence 'NULL' + * // + * nvsRegion = NVS_open(CONFIG_NVS0, NULL); + * + * // Confirm that the NVS region opened properly + * if (nvsRegion == NULL) { + * // Error handling code + * } + * + * // Fetch the generic NVS region attributes for nvsRegion + * NVS_getAttrs(nvsRegion, ®ionAttrs); + * + * // Erase the first sector of nvsRegion + * status = NVS_erase(nvsRegion, 0, regionAttrs.sectorSize); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Write "Hello" to the base address of nvsRegion, verify after write + * status = NVS_write(nvsRegion, 0, "Hello", strlen("Hello")+1, NVS_WRITE_POST_VERIFY); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Copy "Hello" from nvsRegion into local 'buf' + * status = NVS_read(nvsRegion, 0, buf, strlen("Hello")+1); + * if (status != NVS_STATUS_SUCCESS) { + * // Error handling code + * } + * + * // Print the string from fetched NVS storage + * System_printf("%s\n", buf); + * + * // + * // Print the string using direct flash address reference if valid + * // + * // When the NVS driver is managing SPI flash non volatile + * // storage, the regionBase attribute will be `NVS_REGION_NOT_ADDRESSABLE` + * // + * if (regionAttrs.regionBase != NVS_REGION_NOT_ADDRESSABLE) { + * System_printf("%s\n", regionAttrs.regionBase); + * } + * + * // close the region + * NVS_close(nvsRegion); + * + * @endcode + * + *
+ * @anchor ti_drivers_NVS_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ * + * # Example discussion + * + * Details for the @ref ti_drivers_NVS_Examples_typical "Typical NVS region operations" + * example code above are described in the following subsections. + * + * ### NVS Driver Configuration # + * + * In order to use the NVS APIs, the application is required to provide + * device-specific NVS configuration in the ti_drivers_config.c file. + * The NVS driver interface defines a configuration data structure, + * #NVS_Config. + * + * The application must declare an array of #NVS_Config elements, named + * \p NVS_config[]. Each element of \p NVS_config[] is populated with + * pointers to a device specific NVS driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the NVS region's base address and size, + * Each element in \p NVS_config[] corresponds to a NVS instance, and none + * of the elements should have NULL pointers. + * + * You will need to check the device-specific NVS driver implementation's + * header file for example configuration. Please also refer to the + * ti_drivers_config.c file of any of the examples to see the NVS configuration. + * + * ### Initializing the NVS Driver # + * + * NVS_init() must be called before any other NVS APIs. This function + * calls the device implementation's NVS initialization function, for each + * element of \p NVS_config[]. + * + * ### Opening the NVS Driver # + * + * Opening a NVS requires four steps: + * 1. Optionally create and initialize a #NVS_Params structure. + * 2. Fill in the desired parameters. + * 3. Call NVS_open(), passing the index of the NVS region in the #NVS_Config + * structure, and the address of the #NVS_Params structure. + * 4. Check that the #NVS_Handle returned by NVS_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * NVS you just opened. + * + * \note Each NVS index can only be opened exclusively. Calling NVS_open() + * multiple times with the same index will result in an error. The index can + * be re-used if NVS_close() is called first. + * + *
+ * # Thread Safety # + * + * All NVS APIs are globally thread safe. Consequently, only one write, + * erase (or read in the case of SPI flash) operation is allowed to be + * performed at a time, even for distinct NVS regions. Threads initiating + * new NVS writes or erases will block until any current operation completes. + * + * # Interrupt Latency During Flash Operations # + * + * When writing to or erasing internal flash, interrupts must be disabled + * to avoid executing code in flash while the flash is being reprogrammed. + * This constraint is met internally by the driver. User code does not need + * to safeguard against this. + * + * Care must be taken by the user to not perform flash write or erase + * operations during latency critical phases of an application. See the + * NVS_lock() and NVS_unlock() API descriptions for more information. + * + ***************************************************************************** + */ + +#ifndef ti_drivers_NVS__include +#define ti_drivers_NVS__include + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup NVS_CONTROL NVS_control command and status codes + * These NVS macros are reservations for NVS.h + * @{ + */ + +/*! + * Common NVS_control command code reservation offset. + * NVS driver implementations should offset command codes with NVS_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define NVSXYZ_CMD_COMMAND0 NVS_CMD_RESERVED + 0 + * #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1 + * @endcode + */ +#define NVS_CMD_RESERVED (32) + +/*! + * Common NVS_control status code reservation offset. + * NVS driver implementations should offset status codes with + * NVS_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define NVSXYZ_STATUS_ERROR0 NVS_STATUS_RESERVED - 0 + * #define NVSXYZ_STATUS_ERROR1 NVS_STATUS_RESERVED - 1 + * #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2 + * @endcode + */ +#define NVS_STATUS_RESERVED (-32) + +/** + * @defgroup NVS_STATUS Status Codes + * NVS_STATUS_* macros are general status codes returned by NVS_control() + * @{ + * @ingroup NVS_CONTROL + */ + +/*! + * @brief Successful status code returned by: + * NVS_control(), NVS_read(), NVS_write(), NVS_erase(), or + * NVS_lock(). + * + * APIs returns NVS_STATUS_SUCCESS if the API was executed + * successfully. + */ +#define NVS_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by: + * NVS_control(), NVS_erase(), or NVS_write(), + * + * APIs return NVS_STATUS_ERROR if the API was not executed + * successfully. + */ +#define NVS_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by NVS_control() for undefined + * command codes. + * + * NVS_control() returns #NVS_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define NVS_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by NVS_lock() + * + * NVS_lock() will return this value if the @p timeout has expired + */ +#define NVS_STATUS_TIMEOUT (-3) + +/*! + * @brief An error status code returned by NVS_read(), NVS_write(), or + * NVS_erase() + * + * Error status code returned if the @p offset argument is invalid + * (e.g., when offset + bufferSize exceeds the size of the region). + */ +#define NVS_STATUS_INV_OFFSET (-4) + +/*! + * @brief An error status code + * + * Error status code returned by NVS_erase() if the @p offset argument is + * not aligned on a flash sector address. + */ +#define NVS_STATUS_INV_ALIGNMENT (-5) + +/*! + * @brief An error status code returned by NVS_erase() and NVS_write() + * + * Error status code returned by NVS_erase() if the @p size argument is + * not a multiple of the flash sector size, or if @p offset + @p size + * extends past the end of the region. + */ +#define NVS_STATUS_INV_SIZE (-6) + +/*! + * @brief An error status code returned by NVS_write() + * + * NVS_write() will return this value if #NVS_WRITE_PRE_VERIFY is + * requested and a flash location can not be changed to the value + * desired. + */ +#define NVS_STATUS_INV_WRITE (-7) + +/*! + * @brief An error status code returned by NVS_write() + * + * NVS_write() will return this value if #NVS_WRITE_PRE_VERIFY + * or #NVS_WRITE_POST_VERIFY is requested but the verification buffer has not been configured. + */ +#define NVS_STATUS_VERIFYBUFFER (-8) + +/** @}*/ + +/** + * @defgroup NVS_CMD Command Codes + * NVS_CMD_* macros are general command codes for NVS_control(). Not all NVS + * driver implementations support these command codes. + * @{ + * @ingroup NVS_CONTROL + */ + +/* Add NVS_CMD_ here */ + +/** @} end NVS commands */ + +/** @} end NVS_CONTROL group */ + +/*! + * @brief NVS write flags + * + * The following flags can be or'd together and passed as a bit mask + * to NVS_write. + * @{ + */ + +/*! + * @brief Erase write flag. + * + * If #NVS_WRITE_ERASE is set in the flags passed to NVS_write(), the + * affected destination flash sectors will be erased prior to the + * start of the write operation. + */ +#define NVS_WRITE_ERASE (0x1) + +/*! + * @brief Validate write flag. + * + * If #NVS_WRITE_PRE_VERIFY is set in the flags passed to NVS_write(), the + * destination address range will be pre-tested to guarantee that the source + * data can be successfully written. If #NVS_WRITE_ERASE is also requested in + * the write flags, then the #NVS_WRITE_PRE_VERIFY modifier is ignored. + */ +#define NVS_WRITE_PRE_VERIFY (0x2) + +/*! + * @brief Validate write flag. + * + * If #NVS_WRITE_POST_VERIFY is set in the flags passed to NVS_write(), the + * destination address range will be tested after the write is finished to + * verify that the write operation was completed successfully. + */ +#define NVS_WRITE_POST_VERIFY (0x4) + +/** @} */ + +/*! + * @brief Special NVS_lock() timeout values + * @{ + */ + +/*! + * @brief NVS_lock() Wait forever define + */ +#define NVS_LOCK_WAIT_FOREVER (~(0U)) + +/*! + * @brief NVS_lock() No wait define + */ +#define NVS_LOCK_NO_WAIT (0U) + +/** @} */ + +/*! + * @brief Special NVS_Attrs.regionBase value + * @{ + */ + +/*! + * @brief This region is not directly addressable (e.g.,: SPI flash region) + * + * The NVS_Attrs.regionBase field returned by NVS_getAttrs() is set to this + * value by the NVSSPI driver to indicate that the region is not directly + * addressable. + */ +#define NVS_REGION_NOT_ADDRESSABLE ((void *)(~(0U))) + +/** @} */ + +/*! + * @brief NVS Parameters + * + * NVS parameters are used with the NVS_open() call. Default values for + * these parameters are set using NVS_Params_init(). + * + * @sa NVS_Params_init() + */ +typedef struct +{ + void *custom; /*!< Custom argument used by driver implementation */ +} NVS_Params; + +/*! + * @brief NVS attributes + * + * The address of an NVS_Attrs structure is passed to NVS_getAttrs(). + * + * @sa NVS_getAttrs() + */ +typedef struct +{ + void *regionBase; /*!< Base address of the NVS region. If the NVS + region is not directly accessible by the MCU + (such as SPI flash), this field will be set to + #NVS_REGION_NOT_ADDRESSABLE. */ + size_t regionSize; /*!< NVS region size in bytes. */ + size_t sectorSize; /*!< Erase sector size in bytes. This attribute is + device specific. */ +} NVS_Attrs; + +/*! + * @brief A handle that is returned from the NVS_open() call. + */ +typedef struct NVS_Config_ *NVS_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_close(). + */ +typedef void (*NVS_CloseFxn)(NVS_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_control(). + */ +typedef int_fast16_t (*NVS_ControlFxn)(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_erase(). + */ +typedef int_fast16_t (*NVS_EraseFxn)(NVS_Handle handle, size_t offset, size_t size); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_getAttrs(). + */ +typedef void (*NVS_GetAttrsFxn)(NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_init(). + */ +typedef void (*NVS_InitFxn)(void); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_open(). + */ +typedef NVS_Handle (*NVS_OpenFxn)(uint_least8_t index, NVS_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_read(). + */ +typedef int_fast16_t (*NVS_ReadFxn)(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_write(). + */ +typedef int_fast16_t ( + *NVS_WriteFxn)(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_lock(). + */ +typedef int_fast16_t (*NVS_LockFxn)(NVS_Handle handle, uint32_t timeout); + +/*! + * @brief A function pointer to a driver specific implementation of + * NVS_unlock(). + */ +typedef void (*NVS_UnlockFxn)(NVS_Handle handle); + +/*! + * @brief The definition of an NVS function table that contains the + * required set of functions to control a specific NVS driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified NVS region */ + NVS_CloseFxn closeFxn; + + /*! Function to apply control command to the specified NVS region */ + NVS_ControlFxn controlFxn; + + /*! Function to erase a portion of the specified NVS region */ + NVS_EraseFxn eraseFxn; + + /*! Function to get the NVS device-specific attributes */ + NVS_GetAttrsFxn getAttrsFxn; + + /*! Function to initialize the NVS module */ + NVS_InitFxn initFxn; + + /*! Function to lock the specified NVS flash region */ + NVS_LockFxn lockFxn; + + /*! Function to open an NVS region */ + NVS_OpenFxn openFxn; + + /*! Function to read from the specified NVS region */ + NVS_ReadFxn readFxn; + + /*! Function to unlock the specified NVS flash region */ + NVS_UnlockFxn unlockFxn; + + /*! Function to write to the specified NVS region */ + NVS_WriteFxn writeFxn; +} NVS_FxnTable; + +/*! + * @brief NVS Global configuration + * + * The NVS_Config structure contains a set of pointers used to characterize + * the NVS driver implementation. + * + * This structure needs to be defined before calling NVS_init() and it must + * not be changed thereafter. + * + * @sa NVS_init() + */ +typedef struct NVS_Config_ +{ + /*! Pointer to a table of driver-specific implementations of NVS APIs */ + NVS_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} NVS_Config; + +/*! + * @brief Function to close an #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @sa NVS_open() + */ +extern void NVS_close(NVS_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #NVS_Handle. + * + * @pre NVS_open() must be called first. + * + * @param handle An #NVS_Handle returned from NVS_open() + * + * @param cmd A command value defined by the driver specific + * implementation + * + * @param arg An optional read or write argument that is + * accompanied with @p cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa NVS_open() + */ +extern int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); + +/*! + * @brief Erase @p size bytes of the region beginning at @p offset bytes + * from the base of the region referenced by the #NVS_Handle. + * + * @warning Erasing internal flash on most devices can introduce + * significant interrupt latencies while the erase operation is in + * in progress. The user may want to surround certain real-time + * critical code sections with NVS_lock() and NVS_unlock() calls in order + * to prevent uncoordinated flash erase operations from negatively + * impacting performance. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * erasing from (must be erase sector aligned) + * + * @param size The number of bytes to erase (must be integer + * multiple of sector size) + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_INV_ALIGNMENT If @p offset is not aligned on + * a sector boundary + * @retval #NVS_STATUS_INV_OFFSET If @p offset exceeds region size + * @retval #NVS_STATUS_INV_SIZE If @p size or @p offset + @p size + * exceeds region size, or if @p size + * is not an integer multiple of + * the flash sector size. + * @retval #NVS_STATUS_ERROR If an internal error occurred + * erasing the flash. + */ +extern int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size); + +/*! + * @brief Function to get the NVS attributes + * + * This function will populate a #NVS_Attrs structure with attributes + * specific to the memory region associated with the #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @param attrs Location to store attributes. + */ +extern void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); + +/*! + * @brief Function to initialize the NVS module + * + * @pre The NVS_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other NVS APIs. + */ +extern void NVS_init(void); + +/*! + * @brief Function to lock the NVS driver + * + * This function is provided in the event that the user needs to + * perform some flash related operation not provided by the NVS + * driver API set or if the user simply needs to block flash operations + * for a period of time. + * + * For example, the interrupt latency introduced + * by an uncoordinated flash write operation could interfere with some + * critical operation being performed by the application. + * + * NVS_lock() prevents any other thread from initiating + * read, write, or erase operations while the user is performing an + * operation which is incompatible with those functions. + * + * When the application no longer needs to block flash operations by + * other threads, NVS_unlock() must be called to allow NVS write or erase + * APIs to complete. + * + * @param handle A handle returned from NVS_open() + * + * @param timeout Timeout (in milliseconds) to wait, + * or #NVS_LOCK_WAIT_FOREVER, #NVS_LOCK_NO_WAIT + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_TIMEOUT If @p timeout has expired. + */ +extern int_fast16_t NVS_lock(NVS_Handle handle, uint32_t timeout); + +/*! + * @brief Open an NVS region for reading and writing. + * + * @pre NVS_init() was called. + * + * @param index Index in the #NVS_Config table of the region + * to manage. + * + * @param params Pointer to a parameter region. If NULL, default + * parameter values will be used. + * + * @return A non-zero handle on success, else NULL. + */ +extern NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params); + +/*! + * @brief Function to initialize the NVS_Params struct to its defaults + * + * @param params A pointer to NVS_Params structure for + * initialization. + */ +extern void NVS_Params_init(NVS_Params *params); + +/*! + * @brief Read data from the NVS region associated with the #NVS_Handle. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * reading from. + * + * @param buffer A buffer to copy the data to. + * + * @param bufferSize The size of the buffer (number of bytes to read). + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_INV_OFFSET If @p offset + @p size exceed the size + * of the region. + */ +extern int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); + +/*! + * @brief Function to unlock the NVS driver + * + * This function allows NVS write and erase operations to proceed after being + * temporarily inhibited by a call to NVS_lock(). + * + * @param handle A handle returned from NVS_open() + */ +extern void NVS_unlock(NVS_Handle handle); + +/*! + * @brief Write data to the NVS region associated with the #NVS_Handle. + * + * @warning Writing to internal flash on most devices can introduce + * significant interrupt latencies while the write operation is in + * in progress. The user may want to surround certain real-time + * critical code sections with NVS_lock() and NVS_unlock() calls in order + * to prevent uncoordinated flash write operations from negatively + * impacting performance. + * + * @param handle A handle returned from NVS_open() + * + * @param offset The byte offset into the NVS region to start + * writing. + * + * @param buffer A buffer containing data to write to + * the NVS region. + * + * @param bufferSize The size of the buffer (number of bytes to write). + * + * @param flags Write flags (#NVS_WRITE_ERASE, #NVS_WRITE_PRE_VERIFY, + * #NVS_WRITE_POST_VERIFY). + * + * @retval #NVS_STATUS_SUCCESS Success. + * @retval #NVS_STATUS_ERROR If the internal flash write operation + * failed, or if #NVS_WRITE_POST_VERIFY + * was requested and the destination flash + * range does not match the source + * @p buffer data. + * @retval #NVS_STATUS_INV_OFFSET If @p offset + @p size exceed the size + * of the region. + * @retval #NVS_STATUS_INV_WRITE If #NVS_WRITE_PRE_VERIFY is requested + * and the destination flash address range + * cannot be change to the values desired. + * @retval #NVS_STATUS_INV_ALIGNMENT If #NVS_WRITE_ERASE is requested + * and @p offset is not aligned on + * a sector boundary + * @retval #NVS_STATUS_VERIFYBUFFER If #NVS_WRITE_PRE_VERIFY or #NVS_WRITE_POST_VERIFY + * is requested but the verification buffer has not + * been configured. + * + * @remark This call may lock a region to ensure atomic access to the region. + */ +extern int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags); + +#if defined(__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_NVS__include */ diff --git a/simplelink_lpf2/source/ti/drivers/PWM.c b/simplelink_lpf2/source/ti/drivers/PWM.c new file mode 100644 index 00000000..3863c95b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/PWM.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PWM.c ======== + */ + +#include +#include +#include + +#include +#include + +__attribute__((weak)) extern const PWM_Config PWM_config[]; +__attribute__((weak)) extern const uint_least8_t PWM_count; + +/* Default PWM parameters structure */ +const PWM_Params PWM_defaultParams = { + .periodUnits = PWM_PERIOD_HZ, /* Period is defined in Hz */ + .periodValue = 1000000U, /* 1MHz */ + .dutyUnits = PWM_DUTY_FRACTION, /* Duty is fraction of period */ + .dutyValue = 0, /* 0% duty cycle */ + .idleLevel = PWM_IDLE_LOW, /* Low idle level */ + .custom = NULL /* No custom params */ +}; + +static bool isInitialized = false; + +/* + * ======== PWM_close ======== + */ +void PWM_close(PWM_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== PWM_control ======== + */ +int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) +{ + return handle->fxnTablePtr->controlFxn(handle, cmd, arg); +} + +/* + * ======== PWM_init ======== + */ +void PWM_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < PWM_count; i++) + { + PWM_config[i].fxnTablePtr->initFxn((PWM_Handle) & (PWM_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== PWM_open ======== + */ +PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params) +{ + PWM_Handle handle = NULL; + + if (isInitialized && (index < PWM_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (PWM_Params *)&PWM_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (PWM_Handle) & (PWM_config[index]); + + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== PWM_Params_init ======== + */ +void PWM_Params_init(PWM_Params *params) +{ + *params = PWM_defaultParams; +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty) +{ + return (handle->fxnTablePtr->setDutyFxn(handle, duty)); +} + +/* + * ======== PWM_setDuty ======== + */ +int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period) +{ + return (handle->fxnTablePtr->setPeriodFxn(handle, period)); +} +/* + * ======== PWM_setDutyandPeriod ======== + */ +int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period) +{ + return (handle->fxnTablePtr->setDutyAndPeriodFxn(handle, duty, period)); +} + +/* + * ======== PWM_start ======== + */ +void PWM_start(PWM_Handle handle) +{ + handle->fxnTablePtr->startFxn(handle); +} + +/* + * ======== PWM_stop ======== + */ +void PWM_stop(PWM_Handle handle) +{ + handle->fxnTablePtr->stopFxn(handle); +} diff --git a/simplelink_lpf2/source/ti/drivers/PWM.h b/simplelink_lpf2/source/ti/drivers/PWM.h new file mode 100644 index 00000000..aac70e6d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/PWM.h @@ -0,0 +1,629 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file PWM.h + * @brief Pulse Width Modulation (PWM) driver + * + * @anchor ti_drivers_PWM_Overview + * # Overview # + * The PWM driver in TI-RTOS facilitates the generation of Pulse Width + * Modulated signals via simple and portable APIs. + * + * When a PWM instance is opened, the period, duty cycle and idle level are + * configured and the PWM is stopped (waveforms not generated until PWM_start() + * is called). The maximum period and duty supported is device dependent; + * refer to the implementation specific documentation for values. + * + * PWM outputs are active-high, meaning the duty will control the duration of + * high output on the pin (at 0% duty, the output is always low, at 100% duty, + * the output is always high). + * + *
+ * @anchor ti_drivers_PWM_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_PWM_Synopsis + * "usage summary" and a set of @ref ti_drivers_PWM_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_PWM_Synopsis + * ## Synopsis + * @anchor ti_drivers_PWM_Synopsis_Code + * @code + * // Import PWM Driver definitions + * #include + * + * PWM_Handle pwm; + * PWM_Params pwmParams; + * uint32_t dutyValue; + * + * // Initialize the PWM driver. + * PWM_init(); + * + * // Initialize the PWM parameters + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running + * pwmParams.periodUnits = PWM_PERIOD_HZ; // Period is in Hz + * pwmParams.periodValue = 1e6; // 1MHz + * pwmParams.dutyUnits = PWM_DUTY_FRACTION; // Duty is in fractional percentage + * pwmParams.dutyValue = 0; // 0% initial duty cycle + * + * // Open the PWM instance + * pwm = PWM_open(CONFIG_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * + * PWM_start(pwm); // start PWM with 0% duty cycle + * + * dutyValue = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 37) / 100); + * PWM_setDuty(pwm, dutyValue); // set duty cycle to 37% + * @endcode + * + *
+ * @anchor ti_drivers_PWM_Examples + * # Examples + * + * @li @ref ti_drivers_PWM_Examples_open "Opening a PWM instance" + * @li @ref ti_drivers_PWM_Examples_duty "Setting PWM duty" + * @li @ref ti_drivers_PWM_Examples_dutyperiod "Setting PWM Duty and Period" + * + * @anchor ti_drivers_PWM_Examples_open + * # Opening a PWM instance + * + * @code + * + * PWM_Handle pwm; + * PWM_Params pwmParams; + * + * PWM_init(); + * + * PWM_Params_init(&pwmParams); + * pwmParams.idleLevel = PWM_IDLE_LOW; + * pwmParams.periodUnits = PWM_PERIOD_HZ; + * pwmParams.periodValue = 1e6; + * pwmParams.dutyUnits = PWM_DUTY_FRACTION; + * pwmParams.dutyValue = 0; + * + * pwm = PWM_open(CONFIG_PWM0, &pwmParams); + * + * if (pwm == NULL) { + * // PWM_open() failed + * while (1); + * } + * @endcode + * + * @anchor ti_drivers_PWM_Examples_duty + * # Setting PWM duty + * + * Once the PWM instance has been opened and started, the primary API used + * by the application will be #PWM_setDuty() to control the duty cycle of a + * PWM pin: + * + * Below demonstrates setting the duty cycle in units of #PWM_DUTY_FRACTION + * to 45%. + * + * @code + * uint32_t dutyCycle; + * + * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 45) / 100); + * PWM_setDuty(pwm, dutyCycle); + * @endcode + * + * @anchor ti_drivers_PWM_Examples_dutyperiod + * # Setting PWM Duty and Period + * + * If an application needs to modify the duty and period of a running timer, + * an API is available to set both with as little interim time as possible. + * This minimises the possibility that a timeout will occur between one set + * call and the other. For low periods or for instances close to timeout, this + * API will pause the instance output briefly and must only be called when the + * PWM is already running. + * + * Below demonstrates setting the duty cycle to 75% of the new period (100us). + * + * @code + * uint32_t dutyCycle; + * uint32_t periodUs = 100; + * + * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 75) / 100); + * PWM_setDutyAndPeriod(pwm, dutyCycle, periodUs); + * @endcode + * + * ### Modes of Operation # + * + * A PWM instance can be configured to interpret the period as one of three + * units: + * - #PWM_PERIOD_US: The period is in microseconds. + * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. + * - #PWM_PERIOD_COUNTS: The period is in timer counts. + * + * A PWM instance can be configured to interpret the duty as one of three + * units: + * - #PWM_DUTY_US: The duty is in microseconds. + * - #PWM_DUTY_FRACTION: The duty is in a fractional part of + * #PWM_DUTY_FRACTION_MAX where 0 is 0% and + * #PWM_DUTY_FRACTION_MAX is 100%. See + * @ref ti_drivers_PWM_Examples_duty "Setting PWM duty" + * above. + * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than + * the period. + * + * The idle level parameter is used to set the output to high/low when the + * PWM is not running (stopped or not started). The idle level can be + * set to: + * - #PWM_IDLE_LOW + * - #PWM_IDLE_HIGH + * + * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. + * The default period units are in #PWM_PERIOD_HZ and the default duty units + * are in #PWM_DUTY_FRACTION. Finally, the default output idle level is + * #PWM_IDLE_LOW. It is the application's responsibility to set the duty for + * each PWM output used. + * + *
+ * @anchor ti_drivers_PWM_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ ***************************************************************************** + */ + +#ifndef ti_drivers_PWM__include +#define ti_drivers_PWM__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Maximum duty (100%) when configuring duty cycle as a fraction of + * period. + */ +#define PWM_DUTY_FRACTION_MAX ((uint32_t)~0) + +/*! + * Common PWM_control command code reservation offset. + * PWM driver implementations should offset command codes with #PWM_CMD_RESERVED + * growing positively. + * + * Example implementation specific command codes: + * @code + * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) + * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) + * @endcode + */ +#define PWM_CMD_RESERVED (32) + +/*! + * Common PWM_control status code reservation offset. + * PWM driver implementations should offset status codes with + * #PWM_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) + * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) + * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) + * @endcode + */ +#define PWM_STATUS_RESERVED (-32) + +/*! + * @brief Success status code returned by: + * #PWM_control(), #PWM_setDuty(), #PWM_setPeriod(). + * + * Functions return #PWM_STATUS_SUCCESS if the call was executed + * successfully. + */ +#define PWM_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by #PWM_control(). + * + * #PWM_control() returns #PWM_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define PWM_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by #PWM_control() for undefined + * command codes. + * + * #PWM_control() returns #PWM_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define PWM_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by #PWM_setPeriod(). + * + * #PWM_setPeriod() returns #PWM_STATUS_INVALID_PERIOD if the period argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_PERIOD (-3) + +/*! + * @brief An error status code returned by #PWM_setDuty(). + * + * #PWM_setDuty() returns #PWM_STATUS_INVALID_DUTY if the duty cycle argument is + * invalid for the current configuration. + */ +#define PWM_STATUS_INVALID_DUTY (-4) + +/*! + * @brief PWM period unit definitions. Refer to device specific + * implementation if using #PWM_PERIOD_COUNTS (raw PWM/Timer counts). + */ +typedef enum +{ + PWM_PERIOD_US, /*!< Period in microseconds */ + PWM_PERIOD_HZ, /*!< Period in (reciprocal) Hertz + (for example 2MHz = 0.5us period) */ + PWM_PERIOD_COUNTS /*!< Period in timer counts */ +} PWM_Period_Units; + +/*! + * @brief PWM duty cycle unit definitions. Refer to device specific + * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). + */ +typedef enum +{ + PWM_DUTY_US, /*!< Duty cycle in microseconds */ + PWM_DUTY_FRACTION, /*!< Duty as a fractional part of #PWM_DUTY_FRACTION_MAX. + * A duty cycle value of 0 will yield a 0% duty cycle + * while a duty cycle value of #PWM_DUTY_FRACTION_MAX + * will yield a duty cycle value of 100%. See + * @ref ti_drivers_PWM_Examples_duty "Setting PWM duty" + * above. */ + PWM_DUTY_COUNTS /*!< Duty in timer counts */ +} PWM_Duty_Units; + +/*! + * @brief Idle output level when PWM is not running (stopped / not started). + */ +typedef enum +{ + PWM_IDLE_LOW = 0, + PWM_IDLE_HIGH = 1, +} PWM_IdleLevel; + +/*! + * @brief PWM Parameters + * + * PWM Parameters are used to with the PWM_open() call. Default values for + * these parameters are set using PWM_Params_init(). + * + * @sa PWM_Params_init() + */ +typedef struct +{ + PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ + uint32_t periodValue; /*!< PWM initial period */ + PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ + uint32_t dutyValue; /*!< PWM initial duty */ + PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} PWM_Params; + +/*! + * @brief A handle that is returned from a PWM_open() call. + */ +typedef struct PWM_Config_ *PWM_Handle; + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_close(). + */ +typedef void (*PWM_CloseFxn)(PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_control(). + */ +typedef int_fast16_t (*PWM_ControlFxn)(PWM_Handle handle, uint_fast16_t cmd, void *arg); +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_init(). + */ +typedef void (*PWM_InitFxn)(PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_open(). + */ +typedef PWM_Handle (*PWM_OpenFxn)(PWM_Handle handle, PWM_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDuty(). + */ +typedef int_fast16_t (*PWM_SetDutyFxn)(PWM_Handle handle, uint32_t duty); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setPeriod(). + */ +typedef int_fast16_t (*PWM_SetPeriodFxn)(PWM_Handle handle, uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_setDutyAndPeriod(). + */ +typedef int_fast16_t (*PWM_SetDutyAndPeriodFxn)(PWM_Handle handle, uint32_t duty, uint32_t period); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_start(). + */ +typedef void (*PWM_StartFxn)(PWM_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * PWM_stop(). + */ +typedef void (*PWM_StopFxn)(PWM_Handle handle); + +/*! + * @brief The definition of a PWM function table that contains the + * required set of functions to control a specific PWM driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified instance */ + PWM_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + PWM_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + PWM_InitFxn initFxn; + /*! Function to open the specified instance */ + PWM_OpenFxn openFxn; + /*! Function to set the duty cycle for a specific instance */ + PWM_SetDutyFxn setDutyFxn; + /*! Function to set the period for a specific instance */ + PWM_SetPeriodFxn setPeriodFxn; + /*! Function to set the duty and the period for a specific instance */ + PWM_SetDutyAndPeriodFxn setDutyAndPeriodFxn; + /*! Function to start the PWM output for a specific instance */ + PWM_StartFxn startFxn; + /*! Function to stop the PWM output for a specific instance */ + PWM_StopFxn stopFxn; +} PWM_FxnTable; + +/*! + * @brief PWM Global configuration. + * + * The PWM_Config structure contains a set of pointers used to characterize + * the PWM driver implementation. + * + */ +typedef struct PWM_Config_ +{ + /*! Pointer to a table of driver-specific implementations of PWM APIs */ + PWM_FxnTable const *fxnTablePtr; + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PWM_Config; + +/*! + * @brief Function to close a PWM instance specified by the PWM handle. + * + * @pre PWM_open() must have been called first. + * @pre PWM_stop() must have been called first if PWM was started. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + * @sa PWM_stop() + */ +extern void PWM_close(PWM_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * PWM_Handle. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] cmd A command value defined by the driver specific + * implementation. + * + * @param[in] arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @retval #PWM_STATUS_SUCCESS The control call was successful. + * @retval #PWM_STATUS_ERROR The control call failed. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief This function initializes the PWM module. + * + * @pre The PWM_config structure must exist and be persistent before this + * function can be called. This function must be called before any + * other PWM driver APIs. This function does not modify any peripheral + * registers & should only be called once. + */ +extern void PWM_init(void); + +/*! + * @brief This function opens a given PWM instance and sets the period, + * duty and idle level to those specified in the params argument. + * + * @param[in] index Logical instance number for the PWM indexed into + * the PWM_config table. + * + * @param[in] params Pointer to an parameter structure. If NULL default + * values are used. + * + * @return A #PWM_Handle if successful or NULL on an error or if it has been + * opened already. If NULL is returned further PWM API calls will + * result in undefined behavior. + * + * @sa PWM_close() + */ +extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); + +/*! + * @brief Function to initialize the PWM_Params structure to default values. + * + * @param[in] params A pointer to PWM_Params structure for initialization. + * + * Defaults values are: + * Period units: PWM_PERIOD_HZ + * Period: 1e6 (1MHz) + * Duty cycle units: PWM_DUTY_FRACTION + * Duty cycle: 0% + * Idle level: PWM_IDLE_LOW + */ +extern void PWM_Params_init(PWM_Params *params); + +/*! + * @brief Function to set the duty cycle of the specified PWM handle. PWM + * instances run in active high output mode; 0% is always low output, + * 100% is always high output. This API can be called while the PWM + * is running & duty must always be lower than or equal to the period. + * If an error occurs while calling the function the PWM duty cycle + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] duty Duty cycle in the units and format specified by the params + * used in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The duty was set successfully. + * @retval #PWM_STATUS_ERROR The duty was not set and remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); + +/*! + * @brief Function to set the period of the specified PWM handle. This API + * can be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the PWM period + * will remain unchanged. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] period Period in the units specified by the params used + * in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The period was set successfully. + * @retval #PWM_STATUS_ERROR The period was not set and remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); + +/*! + * @brief Function to set both the period and the duty cycle of the specified PWM handle. + * This API must be called while the PWM is running & the period must always be + * larger than the duty cycle. + * If an error occurs while calling the function the period and duty + * will remain unchanged. + * + * @note This API should only be called while the PWM is running. + * + * @note If the period is lower than a certain platform-specific amount, the output of the + * PWM timer may be paused to set these values. Some implementations may also pause + * the PWM if the remaining time before the next timeout is less than this value. This + * is to guard against an edge case where a timeout happens in between setting period + * and duty. + * + * @pre PWM_open() must have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @param[in] duty Duty cycle in the units and format specified by the params used + * in PWM_open(). + * + * @param[in] period Period in the units specified by the params used + * in PWM_open(). + * + * @retval #PWM_STATUS_SUCCESS The duty and period was set successfully. + * @retval #PWM_STATUS_ERROR The duty and period was not set and + remains unchanged. + * + * @sa PWM_open() + */ +extern int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period); + +/*! + * @brief Function to start the specified PWM handle with current settings. + * + * @pre PWM_open() has to have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_stop() + */ +extern void PWM_start(PWM_Handle handle); + +/*! + * @brief Function to stop the specified PWM handle. Output will set to the + * idle level specified by params in PWM_open(). + * + * @pre PWM_open() has to have been called first. + * + * @param[in] handle A PWM handle returned from PWM_open(). + * + * @sa PWM_open() + * @sa PWM_start() + */ +extern void PWM_stop(PWM_Handle handle); + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_PWM__include */ diff --git a/simplelink_lpf2/source/ti/drivers/Power.h b/simplelink_lpf2/source/ti/drivers/Power.h new file mode 100644 index 00000000..9789f81c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Power.h @@ -0,0 +1,952 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file Power.h + * @brief Power Manager + * + * @anchor ti_drivers_Power_Overview + * # Overview + * + * The Power Manager facilitates the transition of the MCU from active states + * to sleep states and vice versa. It provides other drivers the + * ability to set and release dependencies on hardware resources, and keeps + * reference counts on each resource to know when to enable or disable the + * resource. It provides drivers the ability to register callback functions + * to be invoked upon specific power events. In addition, drivers and + * applications can set or release constraints to prevent the MCU from + * transitioning into specific active or sleep states. Refer to the device + * specific power driver header file device specific information. + * + *
+ * @anchor ti_drivers_Power_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_Power_Synopsis + * "usage summary" and a set of @ref ti_drivers_Power_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * @anchor ti_drivers_Power_Synopsis + * ## Synopsis + * @anchor ti_drivers_Power_Synopsis_Code + * + * @note The following example demonstrates usage of some of the Power + * driver APIs.This example is intended for reference only and is not intended + * for application use. You should refer to the device specific Power driver + * header for valid API usage and arguments. + * + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set power dependency on a resource + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * // Other application code + * + * // Release a previously set power constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred + * } + * + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred + * } + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Examples + * # Examples + * + * @note + * The following examples are intended for reference only and are not + * intended for application use. You should refer to the device specific + * Power driver header file for more usage information. + * + * @li @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @li @ref ti_drivers_Power_Examples_disable "Disabling power policy" + * @li @ref ti_drivers_Power_Examples_constraint "Using power constraints" + * @li @ref ti_drivers_Power_Examples_dependency "Using power dependency" + * @li @ref ti_drivers_Power_Examples_notify "Using power notify" + * @li @ref ti_drivers_Power_Examples_transistion "Power transitions" + * + * + * @anchor ti_drivers_Power_Examples_enable + * ## Enabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Enable power policy + * Power_enablePolicy(); + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_disable + * ## Disabling Power Policy + * + * @code + * // Import Power Driver definitions + * #include + * + * bool flag; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Disable power policy + * flag = Power_disablePolicy(); + * if (flag == false) { + * // Power policy was already disabled + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_constraint + * ## Using Power Constraints + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t mask; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power constraint + * status = Power_setConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred setting constraint + * } + * + * // Read mask of currently set power constraints + * mask = Power_getConstraintMask(); + * + * // Release previously set constraint + * status = Power_releaseConstraint(constraintId); + * if (status != Power_SOK) { + * // Error occurred releasing constraint + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_dependency + * ## Using Power Dependency + * + * @code + * // Import Power Driver definitions + * #include + * + * int16_t count; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Set a power dependency + * status = Power_setDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred setting dependency + * } + * + * // Get the dependency count of the resource + * count = Power_getDependencyCount(resourceId); + * if (count == Power_EINVALIDINPUT) { + * // Invalid resourceId used + * } + * + * if (count > 0) { + * // At least 1 dependency exists for the resource. + * // Regardless, we may safely release the dependency when we + * // no longer need the resource. + * } + * + * // Release a power dependency + * status = Power_releaseDependency(resourceId); + * if (status != Power_SOK) { + * // Error occurred releasing dependency + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_notify + * ## Using Power Notify + * + * The application must define a #Power_NotifyFxn function and + * allocate memory for the #Power_NotifyObj object. + * + * @code + * // Import Power Driver definitions + * #include + * + * // Application Power_NotifyObj object + * Power_NotifyObj powerNotifyObj; + * + * // Application Power_NotifyFxn function prototype + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg); + * @endcode + * + * The application must register for the event. Here, we use pseudo event + * names. You should refer to the device specific power driver header file + * for eventTypes. Inside the infinite loop, we wait for a semaphore to be + * post from our notification callback. + * + * @code + * // Application thread + * void thread(void) + * { + * int16_t status; + * unsigned int eventTypes = LOW_POWER_EXIT | LOW_POWER_ENTER; + * uintptr_t clientArg = semaphoreHandle; + * + * status = Power_registerNotify(&powerNotifyObj, eventTypes, + * postNotifyFxn, clientArg); + * + * while (1) + * { + * sem_wait(semaphoreHandle); + * // Do something + * + * // Unregister for the notification. After this call, + * // our postNotifyFxn() will never be called again unless + * // we use Power_registerNotify() again. + * Power_unregisterNotify(&powerNotifyObj); + * + * break; + * } + * } + * @endcode + * + * The application may implement the power notify function to fit their + * needs. The #Power_NotifyFxn should always return #Power_NOTIFYDONE or + * #Power_NOTIFYERROR. + * + * @code + * // Application Power_NotifyFxn function implementation + * static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, + * uintptr_t clientArg) + * { + * sem_t semaphoreHandle = (sem_t) clientArg; + * + * if (eventType == LOW_POWER_EXIT) { + * sem_post(semaphoreHandle); + * return (Power_NOTIFYDONE); + * } + * + * if (eventType == LOW_POWER_ENTER) { + * // Store something in RAM + * return (Power_NOTIFYDONE); + * } + * + * // We received an unexpected event type + * return (Power_NOTIFYERROR); + * } + * @endcode + * + * + * @anchor ti_drivers_Power_Examples_transistion + * ## Power transitions + * + * @code + * // Import Power Driver definitions + * #include + * + * uint32_t totalLatency, resumeLatency; + * int16_t status; + * + * // One-time initialization of Power manager + * Power_init(); + * + * // Get the current power transition state + * status = Power_getTransitionState(); + * + * switch (status) + * { + * case Power_ACTIVE: + * // No transitions in progress + * break; + * case Power_ENTERING_SLEEP: + * // Transition to sleep in progress + * break; + * case Power_EXITING_SLEEP: + * // Transition from sleep in progress + * break; + * } + * + * // Get the Power_TOTAL and Power_RESUME transition latency for a + * // device specific sleepState. Latency is in microseconds. + * totalLatency = Power_getTransitionLatency(sleepState, Power_TOTAL); + * resumeLatency = Power_getTransitionLatency(sleepState, Power_RESUME); + * @endcode + * + * + *
+ * @anchor ti_drivers_Power_Configuration + * # Configuration + * + * @note The Power Manager APIs and configuration parameters are described here. + * For a detailed description of terms and concepts, and usage by different + * types of software components (peripheral drivers, power policies, + * and applications) please see the + * SimpleLink SDK Power Management User's Guide. + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_Power__include +#define ti_drivers_Power__include + +/* @cond */ +#include +#include +/* @endcond */ + +#include +#include + +/* Note: Device specific Power include files are included in the bottom of this file. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @addtogroup Power_Latency_Type + * @{ + */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ +/*! @}*/ + +/*! @addtogroup Power_Notify_Response + * @{ + */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ +/*! @}*/ + +/*! @addtogroup Power_Status + * @{ + */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ +/*! @}*/ + +/*! @addtogroup Power_Transition_State + * @{ + */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +/*! @}*/ + +/*! + * @brief Power policy initialization function pointer + */ +typedef void (*Power_PolicyInitFxn)(void); + +/*! + * @brief Power policy function pointer + */ +typedef void (*Power_PolicyFxn)(void); + +/*! + * @brief Power notify callback function used with the + * Power_registerNotify() + * + * @param[in] eventType The eventTypes parameter identifies the type of + * power event for which the notify callback function was called. + * + * @param[in] eventArg An optional @p eventType specific argument. + * + * @param[in] clientArg Pointer to a custom argument. + * + * @retval #Power_NOTIFYDONE if the client processed the notification + * successfully + * + * @retval #Power_NOTIFYERROR if an error occurred during notification. + * + * @sa Power_registerNotify() + * @sa Power_unregisterNotify() + * @sa Power_NotifyObj + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, uintptr_t eventArg, uintptr_t clientArg); + +/*! + * @brief Power notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * Power_registerNotify() will take care initializing the internal elements + * appropriately. + * + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +typedef struct +{ + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ +} Power_NotifyObj; + +/*! + * @brief Power resource identifier + */ +typedef uint32_t Power_Resource; + +/*! + * @brief Disable the configured power policy from running when the CPU is + * idle + * + * Calling this function clears the flag that controls whether the configured + * power policy function is invoked on each pass through the Idle loop. + * This function call will override both a 'true' setting of the + * "enablePolicy" setting in the Power Manager configuration object, as well + * as a previous runtime call to the Power_enablePolicy() function. + * + * @return The old value of "enablePolicy". + * + * @sa Power_enablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +bool Power_disablePolicy(void); + +/*! + * @brief Enable the configured power policy to run when the CPU is idle + * + * Calling this function sets a flag that will cause the configured power + * policy function to be invoked on each pass through the Idle loop. This + * function call will override both a 'false' setting of the "enablePolicy" + * setting in the Power Manager configuration object, as well as a previous + * runtime call to the Power_disablePolicy() function. + * + * For some processor families, automatic power transitions can make initial + * application development more difficult, as well as being at odds with + * basic debugger operation. This convenience function allows an application + * to be initially configured, built, and debugged, without automatic power + * transitions during idle time. When the application is found to be working, + * this function can be called (typically in main()) to enable the policy + * to run, without having to change the application configuration. + * + * @sa Power_disablePolicy() + * @sa @ref ti_drivers_Power_Examples_enable "Enabling power policy" + * @sa @ref ti_drivers_Power_Examples_disable "Disabling power policy" + */ +void Power_enablePolicy(void); + +/*! + * @brief Get the constraints that have been declared with Power + * + * This function returns a bitmask indicating the constraints that are + * currently declared to the Power Manager (via previous calls to + * Power_setConstraint()). For each constraint that is currently declared, + * the corresponding bit in the bitmask will be set. For example, if two + * clients have independently declared two different constraints, the returned + * bitmask will have two bits set. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. The corresponding bit in the + * bitmask returned by this function can be derived by a left-shift using + * the constraint identifier. For example, for CC26XX, for the corresponding + * bit for the PowerCC26XX_DISALLOW_STANDBY constraint, the bit position is + * determined by the operation: (1 << PowerCC26XX_DISALLOW_STANDBY) + * + * @return A bitmask of the currently declared constraints. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +uint_fast32_t Power_getConstraintMask(void); + +/*! + * @brief Get the current dependency count for a resource + * + * This function returns the number of dependencies that are currently + * declared upon a resource. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. + * + * @param[in] resourceId resource id + * + * @return The number of dependencies declared for the resource. + * + * @retval #Power_EINVALIDINPUT if the @p resourceId is invalid or this + * function is not supported by the device specific implementation. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_getDependencyCount(Power_Resource resourceId); + +/*! + * @brief Get the current constraint count for an operational transition + * + * This function returns the current number of constraints that is set on the + * given operational transition. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h, and to see how many constraints there + * currently are on entering standby, call this function with argument + * PowerCC26XX_DISALLOW_STANDBY + * + * @param[in] constraintId constraint identifier + * + * @return The count for the given power constraint identifier + * + * @retval #Power_EINVALIDINPUT if the @p constraintId is invalid or this + * function is not supported by the device specific implementation. + * + * @sa Power_setConstraint() + */ +int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId); + +/*! + * @brief Get the hardware transition latency for a sleep state + * + * This function reports the minimal hardware transition latency for a specific + * sleep state. The reported latency is that for a direct transition, and does + * not include any additional latency that might occur due to software-based + * notifications. + * + * Sleep states are device specific, and defined in the device-specific Power + * include file. + * + * This function is typically called by the power policy function. The latency + * is reported in units of microseconds. + * + * @param[in] sleepState the sleep state + * + * @param[in] type @ref Power_Latency_Type (#Power_TOTAL or #Power_RESUME) + * + * @return The latency value, in units of microseconds. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, uint_fast16_t type); + +/*! + * @brief Get the current transition state of the Power Manager + * + * @return The current @ref Power_Transition_State. + * + * @retval #Power_ACTIVE returned when no transitions are in progress. + * + * @retval #Power_ENTERING_SLEEP returned during the transition to + * sleep, before sleep has occurred. + * + * @retval #Power_EXITING_SLEEP returned after wakeup, as the device is + * being transitioned back to #Power_ACTIVE. + * + * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" + */ +uint_fast16_t Power_getTransitionState(void); + +/*! + * @brief Power function to be added to the application idle loop + * + * This function should be added to the application idle loop. (The method to + * do this depends upon the operating system being used.) This function + * will invoke the configured power policy function when appropriate. The + * specific policy function to be invoked is configured as the 'policyFxn' + * in the application-defined Power configuration object. + * + */ +void Power_idleFunc(void); + +/*! + * @brief Power initialization function + * + * This function initializes Power Manager internal state. + * + * @warning The application is responsible for ensuring this function is + * called prior to any other Power API. Additionally, this function must be + * be called prior to any other TI-Driver's APIs. This function is normally + * called prior to any operating system initialization. + * + * @return #Power_SOK + */ +int_fast16_t Power_init(void); + +/*! + * @brief Register a function to be called upon a specific power event + * + * This function registers a function to be called when a Power event occurs. + * Registrations and the corresponding notifications are processed in + * first-in-first-out (FIFO) order. The function registered must behave as + * described later, below. + * + * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object + * that will be used by Power to support the notification. This object could + * be dynamically allocated, or declared as a global object. This function + * will properly initialized the object's fields as appropriate; the caller + * just needs to provide a pointer to this pre-existing object. + * + * The eventTypes parameter identifies the type of power event(s) for which + * the notify function being registered is to be called. (Event identifiers are + * device specific, and defined in the device-specific Power include file. + * For example, the events for CC26XX are defined in PowerCC26XX.h.) The + * eventTypes parameter for this function call is treated as a bitmask, so + * multiple event types can be registered at once, using a common callback + * function. For example, to call the specified notifyFxn when both + * the entering deepsleep and awake from deepsleep events occur, eventTypes + * should be specified as: PowerCC26XX_ENTERING_STANDBY | + * PowerCC26XX_AWAKE_STANDBY + * + * The notifyFxn parameter specifies a callback function to be called when the + * specified Power event occurs. The notifyFxn must implement the following + * signature: + * status = notifyFxn(eventType, eventArg, clientArg); + * + * Where: eventType identifies the event being signaled, eventArg is an + * optional event-specific argument, and clientArg is an arbitrary argument + * specified by the client at registration. Note that multiple types of events + * can be specified when registering the notification callback function, + * but when the callback function is actually called by Power, only a + * single eventType will be specified for the callback (i.e., the current + * event). The status returned by the client notification function must + * be one of the following constants: Power_NOTIFYDONE if the client processed + * the notification successfully, or Power_NOTIFYERROR if an error occurred + * during notification. + * + * The clientArg parameter is an arbitrary, client-defined argument to be + * passed back to the client upon notification. This argument may allow one + * notify function to be used by multiple instances of a driver (that is, the + * clientArg can be used to identify the instance of the driver that is being + * notified). + * + * @param[in] pNotifyObj #Power_NotifyObj preallocated by caller + * + * @param[in] eventTypes event type or types + * + * @param[in] notifyFxn client's #Power_NotifyFxn function + * + * @param[in] clientArg client-specified argument to pass with + * notification + * + * @retval #Power_SOK on success. + * + * @retval #Power_EINVALIDPOINTER if either @p pNotifyObj or @p notifyFxn + * are NULL. + * + * @sa Power_unregisterNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Release a previously declared constraint + * + * This function releases a constraint that was previously declared with + * Power_setConstraint(). For example, if a device driver is starting an I/O + * transaction and wants to prohibit activation of a sleep state during the + * transaction, it uses Power_setConstraint() to declare the constraint, + * before starting the transaction. When the transaction completes, the + * driver calls this function to release the constraint, to allow the Power + * manager to once again allow transitions to sleep. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. + * + * Only one constraint can be specified with each call to this function; to + * release multiple constraints this function must be called multiple times. + * + * It is critical that clients call Power_releaseConstraint() when operational + * constraints no longer exists. Otherwise, Power may be left unnecessarily + * restricted from activating power savings. + * + * @pre Power_setConstraint() must have been called first. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the constraintId is + * valid,valid, and that the constraint count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid, and + * #Power_EFAIL if the constraint count is already zero. + * + * @sa Power_setConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); + +/*! + * @brief Release a previously declared dependency + * + * This function releases a dependency that had been previously declared upon + * a resource (by a call to Power_setDependency()). + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size + * asserts are used internally to check that the resourceId is valid, + * and that the resource reference count is not already zero; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the resourceId is invalid, and #Power_EFAIL + * if the resource reference count is already zero. + * + * @sa Power_setDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId); + +/*! + * @brief Resets the system and causes it to reboot + * + * This function causes the system to reset and then boot up again. The impact + * this has on the existing system state such as what memory is retained is + * device-specific. Unless otherwise specified in the device-specific + * documentation, this function will trigger the most comprehensive reset of + * the system triggerable from software. + */ +void Power_reset(void); + +/*! + * @brief Declare an operational constraint + * + * Before taking certain actions, the Power Manager checks to see if the + * requested action would conflict with a client-declared constraint. If the + * action does conflict, Power will not proceed with the request. This is the + * function that allows clients to declare their constraints with Power. + * + * Constraint identifiers are device specific, and defined in the + * device-specific Power include file. For example, the constraints for + * CC26XX are defined in PowerCC26XX.h. + * + * Only one constraint can be specified with each call to this function; to + * declare multiple constraints this function must be called multiple times. + * + * @param[in] constraintId constraint id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the constraintId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the constraintId is invalid. + * + * @sa Power_releaseConstraint() + * @sa @ref ti_drivers_Power_Examples_constraint "Using power constraints" + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId); + +/*! + * @brief Declare a dependency upon a resource + * + * This function declares a dependency upon a resource. For example, if a + * UART driver needs a specific UART peripheral, it uses this function to + * declare this to the Power Manager. If the resource had been inactive, + * then Power will activate the peripheral during this function call. + * + * What is needed to make a peripheral resource 'active' will vary by device + * family. For some devices this may be a simple enable of a clock to the + * specified peripheral. For others it may also require a power on of a + * power domain. In either case, the Power Manager will take care of these + * details, and will also implement reference counting for resources and their + * interdependencies. For example, if multiple UART peripherals reside in + * a shared serial power domain, the Power Manager will power up the serial + * domain when it is first needed, and then automatically power the domain off + * later, when all related dependencies for the relevant peripherals are + * released. + * + * Resource identifiers are device specific, and defined in the + * device-specific Power include file. + * + * @param[in] resourceId resource id + * + * @return CC26XX/CC13XX only: #Power_SOK. To minimize code size an + * assert is used internally to check that the resourceId is valid; + * the function always returns #Power_SOK. + * + * @return All other devices: #Power_SOK on success, + * #Power_EINVALIDINPUT if the reseourceId is invalid. + * + * @sa Power_releaseDependency() + * @sa @ref ti_drivers_Power_Examples_dependency "Using power dependency" + */ +int_fast16_t Power_setDependency(Power_Resource resourceId); + +/*! + * @brief Set a new Power policy + * + * This function allows a new #Power_PolicyFxn function to be selected at + * runtime. + * + * @param[in] policy the new #Power_PolicyFxn function + */ +void Power_setPolicy(Power_PolicyFxn policy); + +/*! + * @brief Put the device into a shutdown state + * + * This function will transition the device into a shutdown state. Before the + * actual transition is initiated, notifications will be sent to any clients + * who've registered (with Power_registerNotify()) for an 'entering shutdown' + * event. The event name is device specific, and defined in the + * device-specific Power include file. Once notifications have been completed, + * the device shutdown will commence. + * + * If the device is successfully transitioned to shutdown, this function + * call will never return. Upon wakeup, the device and application will + * be rebooted (through a device reset). If the transition is not + * successful, one of the error codes listed below will be returned. + * + * On some devices a timed wakeup from shutdown can be specified, using + * the shutdownTime parameter. This enables an autonomous application reboot + * at a future time. For example, an application can go to shutdown, and then + * automatically reboot at a future time to do some work. And once that work + * is done, the application can shutdown again, for another timed interval. + * The time interval is specified via the shutdownTime parameter. (On devices + * that do not support this feature, any value specified for shutdownTime will + * be ignored.) If the specified shutdownTime is zero, or otherwise less than + * the total shutdown latency for the device, the shutdownTime parameter will + * be ignored. The shutdown latency for the device can be found in the + * device-specific Power include file. + * + * @param[in] shutdownState the device-specific shutdown state + * + * @param[in] shutdownTime the amount of time (in milliseconds) to keep + * the the device in the shutdown state; this parameter is not supported on + * all device families. + * + * @retval #Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting + * shutdown. + * + * @retval #Power_EFAIL if an error occurred during client notifications. + * + * @retval #Power_EINVALIDINPUT if the shutdownState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, uint_fast32_t shutdownTime); + +/*! + * @brief Transition the device into a sleep state + * + * This function is called from the power policy when it has made a decision + * to put the device in a specific sleep state. This function returns to the + * caller (the policy function) once the device has awoken from sleep. + * + * @warning This function must be called with interrupts disabled, and + * should not be called directly by the application, or by any drivers. + * This function does not check declared constraints; the policy function + * must check constraints before calling this function to initiate sleep. + * + * @param[in] sleepState the sleep state + * + * @retval #Power_SOK on success, the device has slept and is awake again. + * + * @retval #Power_EFAIL if an error occurred during client notifications, or + * if a general failure occurred. + * + * @retval #Power_EINVALIDINPUT if the @p sleepState is invalid. + * + * @retval #Power_EBUSY if another transition is already in progress. + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState); + +/*! + * @brief Unregister previously registered notifications + * + * This function unregisters for event notifications that were previously + * registered with Power_registerNotify(). The caller must specify a pointer + * to the same notification object used during registration. + * + * @param[in] pNotifyObj The #Power_NotifyObj used with the original + * call to Power_registerNotify() + * + * @sa Power_registerNotify() + * @sa @ref ti_drivers_Power_Examples_notify "Using power notify" + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); + +#ifdef __cplusplus +} +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + #include +#endif + +#endif /* ti_drivers_Power__include */ diff --git a/simplelink_lpf2/source/ti/drivers/RNG.c b/simplelink_lpf2/source/ti/drivers/RNG.c new file mode 100644 index 00000000..6f9ca3e6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/RNG.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RNG.c ======== + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const RNG_Config RNG_config[]; +extern const uint_least8_t RNG_count; + +const RNG_Params RNG_defaultParams = {.returnBehavior = RNG_RETURN_BEHAVIOR_BLOCKING, + .cryptoKeyCallbackFxn = NULL, + .randomBitsCallbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER}; + +/* + * ======== RNG_open ======== + */ +RNG_Handle RNG_open(uint_least8_t index, const RNG_Params *params) +{ + DebugP_assert(index <= RNG_count); + + const RNG_Config *config = (const RNG_Config *)&RNG_config[index]; + + return RNG_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/RNG.h b/simplelink_lpf2/source/ti/drivers/RNG.h new file mode 100644 index 00000000..3137b430 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/RNG.h @@ -0,0 +1,1005 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file RNG.h + * + * @brief RNG driver header + * + * @anchor ti_drivers_RNG_Overview + * # Overview # + * The Random Number Generator (RNG) module generates random data of variable + * lengths from a pool of entropy. The pool of entropy is maintained by the + * driver using implementation-specific sources of entropy. + * The output is suitable for applications requiring cryptographically + * random data such as keying material for private or symmetric keys. + * + * The RNG driver for CC27XX devices is strictly a CRNG/HSM implementation only. + * + * CRNG (Cryptographically Secure Pseudo Random Number) a DRBG method alternative to + * True Random Number (TRNG) + * + * HSM (Hardware Security Module) is a HW IP used for RNG operations + * + * For CC27XX devices only, the RNG driver accepts two types of cryptoKey encoding + * - CryptoKey_BLANK_PLAINTEXT + * - CryptoKey_BLANK_PLAINTEXT_HSM + * + * @anchor ti_drivers_RNG_Usage + * # Usage # + * + * ## Initialization ## + * Unlike most drivers, there is a global instance of RNG driver data + * that is always available once #RNG_init() is called. This data will contain + * the entropy pool and any needed state information required to refill the + * pool. #RNG_init() should be called once before using other RNG + * driver APIs. + * + * @note Some implementations restrict when RNG_init() may be called. + * Check the implementation's documentation for more information. + * + * For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps prior to the use of the Radio because CC23X0 uses the ADC samples + * from radio as noise that is conditioned using CBC MAC to generate the seed for RNG driver + * + * ### Step 1: Required header file ### + * + * @code + * + * #include // required for external syscfg variable RNGLPF3RF_noiseInputWordLen + * + * @endcode + * + * ### Step 2: External APIs ### + * + * @code + * + * // Use the function provided by RCL to read noise input // + * extern int_fast16_t RCL_AdcNoise_get_samples_blocking(uint32_t *buffer, uint32_t numWords); + * + * @endcode + * + * ### Step 3: Read noise input from RCL using RCL_AdcNoise_get_samples_blocking() ### + * + * @code + * + * int_fast16_t rclStatus, result; + + * // User's global array for noise input based on size provided in syscfg // + * uint32_t localNoiseInput[]; //Minimum array size 80 words + * + * // Clear noise input // + * memset(localNoiseInput, 0, sizeof(localNoiseInput)); + * + * // Fill noise input from RCL // + * //RNGLPF3RF_noiseInputWordLen is external variable from RNGLPF3RF.h + * rclStatus = RCL_AdcNoise_get_samples_blocking(localNoiseInput, RNGLPF3RF_noiseInputWordLen); + * + * if (rclStatus != 0) + * { + * //Handle error; + * } + * + * // Initialize the RNG driver noise input pointer with global noise input array from user // + * result = RNGLPF3RF_conditionNoiseToGenerateSeed(localNoiseInput); + * if ( rclStatus != 0) + * { + * //Handle error; + * } + * + * @endcode + * + * + * ## Before starting a RNG operation ## + * + * Before starting a RNG operation, the application must do the following: + * - Call RNG_init() to initialize the driver's global instance data. + * - Call RNG_Params_init() to initialize the RNG_Params to default values. + * - Modify the RNG_Params as desired. + * - Call RNG_open() to open an instance of the driver. + * + * @note Some implementations restrict when RNG_init() may be called. + * Check the implementation's documentation for more information. + * + * ## Entropy Pool Management ## + * + * At any time after calling RNG_init(), the application may call + * RNG_fillPoolIfLessThan() to add entropy to the pool which will then make + * future requests for entropy execute faster. Note that the driver never + * automatically refills the pool. However, if the pool is empty, the RNG + * driver will still generate entropy upon request (for example when + * RNG_getRandomBits() is called). + * + * The application is responsible for deciding when it is appropriate to + * spend the time and energy to refill the pool. One suggested location + * to do so is the idle thread. + * + * ## RNG operations ## + * + * Use RNG_getRandomBits() to obtain random bits from the entropy pool and + * copy them to a buffer/array. The caller must allocate memory sufficient + * to hold at least the number of bits of random data requested. + * + * ## After the RNG operation completes ## + * + * After the RNG operation completes, the application should either start + * another operation or close the driver by calling RNG_close(). Note that the + * singleton instance of the driver, along with its associated pool of entropy + * will still exist and will be used by any future RNG_open() calls. Note that + * closing the driver instance may not be strictly required, but is good + * practice. + * + * ## Security ## + * + * ### Data Protection ### + * + * The entropy pool and any required state to generate more entropy is + * maintained in memory, in the driver's global instance data. The entirety of + * this data is stored in two global variables called RNG_instanceData and + * RNG_instancePool. It is up to the system to provide adequate + * protection (primarily confidentiality and integrity) of these in-memory + * assets. + * + * ### Timing Side Channels ### + * + * Functions which provide for generation of a value within a range use + * an algorithm which is timing-constant when the following parameters + * are held constant: lowerLimit, upperLimit, bitLength, + * and endianess. Thus, while the driver may create multiple candidates for the + * value to find one within the range, timing will not leak the final + * value's relation to the limits. However, timing may leak the bitLength, + * the endianess, and the use of #CryptoUtils_limitZero, #CryptoUtils_limitOne, + * or NULL for the limit values. + * + * @anchor ti_drivers_RNG_Synopsis + * ## Synopsis + * @anchor ti_drivers_RNG_Synopsis_Code + * ### Generate random bytes to a user provided buffer # + * + * @code + * + * #include + * #include "ti_drivers_config.h" + * + * // Setup RNG + * RNG_Init(); + * RNG_fillPoolIfLessThan(RNG_POOL_BYTE_SIZE); + * + * // Use RNG + * #define RANDOM_BYTES_SIZE 16u + * RNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * result = RNG_getRandomBits(handle, randomBytesArray, RANDOM_BYTES_SIZE * 8); + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * // Refill RNG Pool when convenient + * RNG_fillPoolIfLessThan(RNG_POOL_BYTE_SIZE); + * @endcode + * + * @anchor ti_drivers_RNG_Examples + * ## Examples + * + * The following examples do not show the process of initializing the RNG + * module and refilling the pool. + * See @ref ti_drivers_RNG_Synopsis RNG Driver Synopsis for an example + * showing those parts of RNG operation. * + * + * ### Generate a number within a range ### + * + * @code + * + * #include + * + * #define RANDOM_BIT_SIZE 15u + * #define RANDOM_BYTE_SIZE ((RANDOM_BIT_SIZE + 7u)/8u) + * + * RNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * uint8_t upperLimit[RANDOM_BYTES_SIZE] = {0xA9, 0x61}; // 25,001, LE format + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * // Generate a number from 1 to 25,000 (inclusive) + * // Note that lowerLimit parameter is inclusive and upperLimit is + * // exclusive. Thus, upperLimit is set to 25,001. + * result = RNG_getLERandomNumberInRange(RNG_Handle handle, RNG_limitOne, + * upperLimit, randomBytesArray, + * RANDOM_BIT_SIZE); + * + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * @endcode + * + * + * ### Generate an ECC private key ### + * + * @code + * + * #include + * #include + * + * // Values are chosen to generate a NIST 256 bit key. + * CryptoKey privateKey; + * uint8_t privateKeyingMaterial[NISTP256_PARAM_SIZE_BYTES]; + * RNG_Handle handle; + * int_fast16_t result; + * + * handle = RNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initBlankKey(&privateKey, privateKeyingMaterial, + * ECCParams_NISTP256.length); + * + * // Generate NIST 256 bit key in BE format. + * result = RNG_generateBEKeyInRange(RNG_Handle handle, RNG_limitOne, + * ECCParams_NISTP256.order, privateKey, + * 256); + * + * + * if (result != RNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * RNG_close(handle); + * + * @endcode + * + */ + +#ifndef ti_drivers_RNG__include +#define ti_drivers_RNG__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common RNG status code reservation offset. + * RNG driver implementations should offset status codes with + * RNG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define RNGXYZ_STATUS_ERROR0 ((int_fast16_t) (RNG_STATUS_RESERVED - 0)) + * #define RNGXYZ_STATUS_ERROR1 ((int_fast16_t) (RNG_STATUS_RESERVED - 1)) + * #define RNGXYZ_STATUS_ERROR2 ((int_fast16_t) (RNG_STATUS_RESERVED - 2)) + * @endcode + */ +#define RNG_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return RNG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define RNG_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return RNG_STATUS_ERROR if the function was not executed + * successfully. + */ +#define RNG_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * RNG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ +#define RNG_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief Operation failed due to invalid inputs. + * + * Functions return RNG_STATUS_INVALID_INPUTS if input validation fails. + */ +#define RNG_STATUS_INVALID_INPUTS ((int_fast16_t)-3) + +/*! + * @brief The ongoing operation was canceled. + */ +#define RNG_STATUS_CANCELED ((int_fast16_t)-4) + +/*! + * @brief The pool of entropy has been exhausted and additional entropy cannot + * be generated. A reset of the system may be required to generate more + * entropy. + */ +#define RNG_ENTROPY_EXHAUSTED ((int_fast16_t)-5) + +/*! + * @brief Some implementations have restrictions on how often or when + * RNG_init may be called. See the documentation for the implementation + * for more information. + */ +#define RNG_STATUS_INIT_NOT_ALLOWED ((int_fast16_t)-6) + +/*! + * @brief Some implementations require a noise input during initialization + * which is conditioned to seed the RNG driver. RNG_init() will return this + * error if the noise input pointer is not initialized with valid information. + * See documentation for the implementation for more information. + */ +#define RNG_STATUS_NOISE_INPUT_INVALID ((int_fast16_t)-7) + +/*! + * @brief RNG driver not initialized. + * + * @note Some implementations restrict when RNG_init() may be called. + * Refer to #RNG_init() for more information. + */ +#define RNG_STATUS_NOT_INITIALIZED ((int_fast16_t)-8) + +/*! + * @brief Maximum number of bits that may be requested in a single call + */ +#define RNG_MAX_BIT_LENGTH ((size_t)1u << 20u) /* 1 MiB */ + +/*! + * @brief RNG Global configuration + * + * The RNG_Config structure contains a set of pointers used to characterize + * the RNG driver implementation. + * + * This structure needs to be defined before calling RNG_init() and it must + * not be changed thereafter. + * + * @sa RNG_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} RNG_Config; + +/*! + * @brief A handle that is returned from a RNG_open() call. + */ +typedef const RNG_Config *RNG_Handle; + +/*! + * @brief The way in which RNG function calls return after generating + * the requested entropy. + * + * Not all RNG implementations support all of the return behavior options. + * + * Not all RNG operations exhibit the specified return behavior. Functions that + * do not require significant computation and cannot offload that computation to + * a background thread behave like regular functions. Which functions exhibit + * the specified return behavior is not implementation dependent. Specifically, + * a software-backed implementation run on the same CPU as the application will + * emulate the return behavior while not actually offloading the computation to + * the background thread. + * + * RNG functions exhibiting the specified return behavior have restrictions on + * the context from which they may be called. + * + * | | Task | Hwi | Swi | + * |------------------------------|-------|-------|-------| + * | RNG_RETURN_BEHAVIOR_CALLBACK | X | | | + * | RNG_RETURN_BEHAVIOR_BLOCKING | X | | | + * | RNG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + RNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * RNG operation goes on in the background. The + * registered callback function is called after the + * operation completes. The context the callback + * function is called (task, HWI, SWI) is + * implementation-dependent. + */ + RNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while RNG operation + * goes on in the background. RNG operation results + * are available after the function returns. + */ + RNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag + * while RNG operation goes on in the background. RNG + * operation results are available after the function + * returns. + */ +} RNG_ReturnBehavior; + +/*! + * @brief The definition of a callback function used by the RNG driver + * when RNG_generateKey(), RNG_generateLEKeyInRange(), or + * RNG_generateBEKeyInRange() is called with ::RNG_RETURN_BEHAVIOR_CALLBACK + * + * @warning Attempting to make calls to the RNG driver from the callback + * may result in deadlock. + * + * @param handle Handle of the client that started the RNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param key The CryptoKey that describes the location the generated + * entropy will be copied to. + */ +typedef void (*RNG_CryptoKeyCallbackFxn)(RNG_Handle handle, int_fast16_t returnValue, CryptoKey *key); + +/*! + * @brief The definition of a callback function used by the RNG driver + * when RNG_getRandomBits(), RNG_getLERandomNumberInRange(), + * or RNG_getBERandomNumberInRange is called with + * ::RNG_RETURN_BEHAVIOR_CALLBACK + * + * @warning Attempting to make calls to the RNG driver from the callback + * may result in deadlock. + * + * @param handle Handle of the client that started the RNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param randomBits Pointer to an array that stores the random bits + * output by this function. + * + * @param randomBitsLength The length of the random data generated, in bits. + */ +typedef void (*RNG_RandomBitsCallbackFxn)(RNG_Handle handle, + int_fast16_t returnValue, + uint8_t *randomBits, + size_t randomBitsLength); + +/*! + * @brief RNG Parameters + * + * RNG Parameters are used with the RNG_open() call. Default values for + * these parameters are set using RNG_Params_init(). + * + * @attention When using the driver in #RNG_RETURN_BEHAVIOR_CALLBACK, + * set the appropriate callback function field to point to a + * valid callback function and set the other one to NULL. + * + * @sa RNG_Params_init() + */ +typedef struct +{ + RNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + RNG_CryptoKeyCallbackFxn cryptoKeyCallbackFxn; /*!< Callback function to use with RNG_generateKey() + * and RNG_generateKeyInRange(). + * Set randomBitsCallbackFxn to NULL if using this. + */ + RNG_RandomBitsCallbackFxn randomBitsCallbackFxn; /*!< Callback function to use with RNG_getRandomBits(), + * RNG_getLERandomNumberInRange(), and + * RNG_getBERandomNumberInRange(). + * Set cryptoKeyCallbackFxn to NULL if using this. + */ + uint32_t timeout; /*!< Timeout (in ClockP ticks) before the driver + * returns an error in ::RNG_RETURN_BEHAVIOR_BLOCKING + */ +} RNG_Params; + +/*! + * @brief Default RNG_Params structure + * + * @sa RNG_Params_init() + */ +extern const RNG_Params RNG_defaultParams; + +/*! + * @brief The byte size of the pool + */ +extern const size_t RNG_poolByteSize; + +/*! + * @brief This function initializes the RNG module. + * + * @pre The RNG_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other RNG driver APIs. This function call does not modify any + * peripheral registers. + * For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps prior to the use of the Radio because CC23X0 uses the ADC samples + * from radio as noise that is conditioned using CBC MAC + * to generate the seed for RNG driver + * 1. Read radio noise using RCL_AdcNoise_get_samples_blocking(). This RCL function must + * be called from a task context with interrupts enabled and therefore cannot be called + * by startup code. This must be executed prior to the use of the radio. + * 2. Condition the noise to seed the RNG using RNGLPF3RF_conditionNoiseToGenerateSeed(). + * 3. Initialize the RNG from the application with RNG_init() + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + */ +int_fast16_t RNG_init(void); + +/*! + * @brief Fills the pool with entropy if the number of bytes with entropy in + * the pool is less than the value specified. + * + * @note This function does not take in a handle and the implementation + * may run in either blocking or polling mode. + * + * @pre RNG_init() has to be called first. + * + * @param bytes Pool will be filled if current level is less than this number. + * Use RNG_POOL_BYTE_SIZE (from ti_drivers_config.h) to always fill. + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_ENTROPY_EXHAUSTED Pool could not be refilled, device + * may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_fillPoolIfLessThan(size_t bytes); + +/*! + * @brief Function to initialize the RNG_Params struct to its defaults + * + * @param params An pointer to RNG_Params structure for + * initialization + * + * Default values are:
+ * returnBehavior = RNG_RETURN_BEHAVIOR_BLOCKING
+ * cryptoKeyCallbackFxn = NULL
+ * randomBitsCallbackFxn = NULL
+ * timeout = SemaphoreP_WAIT_FOREVER
+ * custom = NULL
+ */ +void RNG_Params_init(RNG_Params *params); + +/*! + * @brief This function opens a given RNG peripheral. + * + * @pre RNG controller has been initialized using RNG_init() + * + * @param index Logical peripheral number for the RNG indexed into + * the RNG_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A RNG_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa RNG_init() + * @sa RNG_close() + */ +RNG_Handle RNG_open(uint_least8_t index, const RNG_Params *params); + +/*! + * @brief Function to close a RNG peripheral specified by the RNG handle + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open() + * + * @sa RNG_open() + */ +void RNG_close(RNG_Handle handle); + +/*! + * @brief Generate random bits and output to the given array. + * + * Generates random a random number of bits with length of \c randomBitsLength. + * The output length in bytes will be the minimum number of bytes needed + * to contain \c randomBitsLength. The output will be placed at the address + * pointed to by \c randomBits. The user shall be responsible for allocating + * sufficient memory starting at the address pointed at by \c randomBits to + * hold the number of bytes output. + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a + * callback function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateKey() to output random bytes to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param randomBits Pointer to an array that stores the random bits + * output by this function. + * + * @param randomBitsLength The length of the random data required, in bits. + * A maximum of 1MiB is allowed. + * + * @sa RNG_getLERandomNumberInRange + * @sa RNG_getBERandomNumberInRange + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_getRandomBits(RNG_Handle handle, void *randomBits, size_t randomBitsLength); + +/*! + * @brief Generate random number, stored in little-endian (LE) format, where + * the number is within the specified range. + * + * Generates random a random number within the range [lowerLimit, upperLimit) + * of bit size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed at the address pointed to by \c randomNumber. The user + * shall be responsible for allocating sufficient memory starting at the + * address pointed at by \c randomNumber to hold the number of bytes output. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateLEKeyInRange() to output a ranged number to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in LE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in LE format for the generated number. + * + * @param randomNumber Pointer to an array that stores the random number + * output by this function. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_getLERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength); + +/*! + * @brief Generate random number, stored in big-endian (BE) format, where + * the number is within the specified range. + * + * Generates random a random number within the range [lowerLimit, upperLimit) + * of bit size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed at the address pointed to by \c randomNumber. The user + * shall be responsible for allocating sufficient memory starting at the address + * pointed at by \c randomNumber to hold the number of bytes output. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_RandomBitsCallbackFxn. + * + * @note See #RNG_generateBEKeyInRange() to output a ranged number to a \c CryptoKey instead. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in BE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in BE format for the generated number. + * + * @param randomNumber Pointer to an array that stores the random number + * output by this function. + * + * @param randomNumberBitLength The length, in bits, of both the limit value + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_getBERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength); + +/*! + * @brief Generate random bits and output them to the given \c CryptoKey object. + * + * Generates a random bitstream of the size defined in the \c key + * CryptoKey in the range 0 <= \c key buffer < 2 ^ (entropy length * 8). + * The entropy will be generated and stored according to the storage + * requirements defined in the CryptoKey. The length of the entropy + * generated will be the same as the key length. + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a + * callback function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @sa RNG_generateLEKeyInRange + * @sa RNG_generateBEKeyInRange + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_generateKey(RNG_Handle handle, CryptoKey *key); + +/*! + * @brief Generate random number, in little-endian (LE) format, where the + * number is within the specified range. Store the random number in + * the given \c CryptoKey object. + * + * Generates a random number within the range [lowerLimit, upperLimit) of bit + * size \c randomNumberBitLength. The output length in bytes will be the minimum + * number of bytes needed to contain \c randomNumberBitLength. The output will + * be placed as specified by the members of \c key. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in LE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in LE format for the generated number. + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_generateLEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength); + +/*! + * @brief Generate random number, stored in big-endian (BE) format, where the + * number is within the specified range. Store the random number in + * the given \c CryptoKey object. + * + * Generates a random number within the range [lowerLimit, upperLimit) of bit + * size \c randomNumberBitLength. The output length in bytes will be the + * minimum number of bytes needed to contain \c randomNumberBitLength. The + * output will be placed as specified by the members of \c key. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the \c lowerLimit. + * (These values can also be used for the \c upperLimit but their use for the + * upperLimit has no practical use.) + * + * If \c lowerLimit is NULL then the lower limit is taken as 0. + * If \c upperLimit is NULL then the upper limit is taken as + * 2(\c bitLength + 1). + * + * @attention When called with ::RNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #RNG_CryptoKeyCallbackFxn. + * + * @pre RNG_open() has to be called first. + * + * @param handle A RNG handle returned from RNG_open(). + * + * @param lowerLimit Pointer to an array that stores the lower limit (inclusive) + * in BE format for the generated number. + * + * @param upperLimit Pointer to an array that stores the upper limit (exclusive) + * in BE format for the generated number. + * + * @param key Pointer to a blank CryptoKey, initialized with a length and + * appropriate storage for storing a key of the specified length. + * + * @param randomNumberBitLength The length, in bits, of both the limit values + * and the random number to be generated. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_limitOne + * + * @retval #RNG_STATUS_SUCCESS The operation succeeded. + * @retval #RNG_STATUS_ERROR The operation failed. + * @retval #RNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was + * not available. Try again later. + * @retval #RNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + * @retval #RNG_ENTROPY_EXHAUSTED Requested number of bytes could + * not be obtained. Device may need reset. + * @retval #RNG_STATUS_NOT_INITIALIZED RNG not initialized. + */ +int_fast16_t RNG_generateBEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength); + +/** + * @brief Constructs a new RNG object + * + * Unlike #RNG_open(), #RNG_construct() does not require the hwAttrs and + * object to be allocated in a #RNG_Config array that is indexed into. + * Instead, the #RNG_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #RNG_Config describing the location of the object and hwAttrs. + * + * @param params #RNG_Params to configure the driver instance. + * + * @return Returns a #RNG_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +RNG_Handle RNG_construct(const RNG_Config *config, const RNG_Params *params); + +/*! + * @brief Aborts an ongoing RNG operation and clears internal buffers. + * + * Aborts an operation to generate random bytes/entropy. The operation will + * terminate as though an error occurred and the status code of the operation + * will be #RNG_STATUS_CANCELED in this case. + * + * Any entropy already copied out of the pool will have already been removed + * from the pool and will not be reused for later requests. + * + * Canceling an operation may be delayed if the entropy pool is below its + * minimum fill mark as the driver will refill the pool before finishing + * the cancelled operation. + * + * @param handle A #RNG_Handle returned from #RNG_open() + * + * @retval #RNG_STATUS_SUCCESS The operation was canceled or there was no + * operation in progress to be canceled. + */ +int_fast16_t RNG_cancelOperation(RNG_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_RNG__include */ diff --git a/simplelink_lpf2/source/ti/drivers/SD.c b/simplelink_lpf2/source/ti/drivers/SD.c new file mode 100644 index 00000000..47ec3353 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SD.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +extern const SD_Config SD_config[]; +extern const uint_least8_t SD_count; + +/* Default SD parameters structure */ +const SD_Params SD_defaultParams = { + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== SD_close ======== + */ +void SD_close(SD_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== SD_control ======== + */ +int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); +} + +/* + * ======== SD_getNumSectors ======== + */ +uint_fast32_t SD_getNumSectors(SD_Handle handle) +{ + return (handle->fxnTablePtr->getNumSectorsFxn(handle)); +} + +/* + * ======== SD_getSectorSize ======== + */ +uint_fast32_t SD_getSectorSize(SD_Handle handle) +{ + return (handle->fxnTablePtr->getSectorSizeFxn(handle)); +} + +/* + * ======== SD_init ======== + */ +void SD_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < SD_count; i++) + { + SD_config[i].fxnTablePtr->initFxn((SD_Handle) & (SD_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== SD_initialize ======== + */ +int_fast16_t SD_initialize(SD_Handle handle) +{ + return (handle->fxnTablePtr->initializeFxn(handle)); +} + +/* + * ======== SD_open ======== + */ +SD_Handle SD_open(uint_least8_t index, SD_Params *params) +{ + SD_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < SD_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (SD_Params *)&SD_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (SD_Handle) & (SD_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== SD_Params_init ======== + */ +void SD_Params_init(SD_Params *params) +{ + *params = SD_defaultParams; +} + +/* + * ======== SD_read ======== + */ +int_fast16_t SD_read(SD_Handle handle, void *buf, int_fast32_t sector, uint_fast32_t secCount) +{ + return (handle->fxnTablePtr->readFxn(handle, buf, sector, secCount)); +} + +/* + * ======== SD_write ======== + */ +int_fast16_t SD_write(SD_Handle handle, const void *buf, int_fast32_t sector, uint_fast32_t secCount) +{ + return (handle->fxnTablePtr->writeFxn(handle, buf, sector, secCount)); +} diff --git a/simplelink_lpf2/source/ti/drivers/SD.h b/simplelink_lpf2/source/ti/drivers/SD.h new file mode 100644 index 00000000..44f5bd06 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SD.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!*************************************************************************** + * @file SD.h + * @brief Secure Digital (SD) Driver + * + * @anchor ti_drivers_SD_Overview + * # Overview + * + * The SD driver is designed to serve as an interface to perform basic + * transfers directly to the SD card. + * + *
+ * @anchor ti_drivers_SD_Usage + * # Usage + * This section will cover driver usage. + * + * @anchor ti_drivers_SD_Synopsis + * ## Synopsis + * @anchor ti_drivers_SD_Synopsis_Code + * @code + * SD_Handle handle; + * uint16_t status; + * + * SD_init(); + * + * // Open SD and initialize card + * handle = SD_open(CONFIG_SD0, NULL); + * status = SD_initialize(handle); + * if (handle == NULL || status != SD_STATUS_SUCCESS) { + * //Error opening SD driver + * while (1); + * } + * + * // Write and read back the first sector + * status = SD_write(handle, sendBuffer, 0, 1); + * if (status == SD_STATUS_SUCCESS) { + * status = SD_read(handle, readBuffer, 0 , 1); + * } + * + * SD_close(handle); + * @endcode + * + * @anchor ti_drivers_SD_Examples + * # Examples + * - @ref ti_drivers_SD_Synopsis "Overview" + * - @ref ti_drivers_SD_Example_getCardSpace "Get SD card size" + * + * Get total capacity of an SD card: + * @anchor ti_drivers_SD_Example_getCardSpace + * @code + * SD_Handle handle; + * Display_Handle display; + * uint_fast32_t sectorSize, sectorCount; + * + * // Init, open, etc + * ... + * + * sectorSize = SD_getSectorSize(handle); + * sectorCount = SD_getNumSectors(handle); + * + * Display_printf(display, 0, 0,"SD card total capacity is %lu bytes.", + * sectorSize * sectorCount); + * @endcode + * + *
+ * @anchor ti_drivers_SD_Configuration + * # Configuration + * Refer to the @ref driver_configuration "Driver's Configuration" + * section for driver configuration information. + * + *
+ ****************************************************************************** + */ + +#ifndef ti_drivers_SD__include +#define ti_drivers_SD__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup SD_CONTROL SD_control command and status codes + * @{ + */ + +/*! + * Common SD_control() command code reservation offset. + * SD driver implementations should offset command codes with + * SD_CMD_RESERVED growing positively. + * + * Example implementation specific command codes: + * @code + * #define SDXYZ_CMD_COMMAND0 (SD_CMD_RESERVED + 0) + * #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1) + * @endcode + */ +#define SD_CMD_RESERVED (32) + +/*! + * Common SD_control status code reservation offset. + * SD driver implementations should offset status codes with + * SD_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SDXYZ_STATUS_ERROR0 (SD_STATUS_RESERVED - 0) + * #define SDXYZ_STATUS_ERROR1 (SD_STATUS_RESERVED - 1) + * #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2) + * @endcode + */ +#define SD_STATUS_RESERVED (-32) + +/** + * @defgroup SD_STATUS Status Codes + * SD_STATUS_* macros are general status codes returned by SD_control() + * @{ + * @ingroup SD_CONTROL + */ + +/*! + * @brief Successful status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define SD_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SD_control(). + * + * SD_control() returns SD_STATUS_ERROR if the control code + * was not executed successfully. + */ +#define SD_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SD_control() for + * undefined command codes. + * + * SD_control() returns SD_STATUS_UNDEFINEDCMD if the + * control code is not recognized by the driver implementation. + */ +#define SD_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SD_CMD Command Codes + * SD_CMD_* macros are general command codes for SD_control(). Not all SD + * driver implementations support these command codes. + * @{ + * @ingroup SD_CONTROL + */ + +/* Add SD_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief SD Card type inserted + */ +typedef enum +{ + SD_NOCARD = 0, /*!< Unrecognized Card */ + SD_MMC = 1, /*!< Multi-media Memory Card (MMC) */ + SD_SDSC = 2, /*!< Standard SDCard (SDSC) */ + SD_SDHC = 3 /*!< High Capacity SDCard (SDHC) */ +} SD_CardType; + +/*! + * @brief A handle that is returned from a SD_open() call. + */ +typedef struct SD_Config_ *SD_Handle; + +/*! + * @brief SD Parameters + * + * SD Parameters are used to with the SD_open() call. + * Default values for these parameters are set using SD_Params_init(). + * + * @sa SD_Params_init() + */ + +/* SD Parameters */ +typedef struct +{ + void *custom; /*!< Custom argument used by driver implementation */ +} SD_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_CloseFxn(). + */ +typedef void (*SD_CloseFxn)(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_controlFxn(). + */ +typedef int_fast16_t (*SD_ControlFxn)(SD_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getNumSectorsFxn(). + */ +typedef uint_fast32_t (*SD_getNumSectorsFxn)(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_getSectorSizeFxn(). + */ +typedef uint_fast32_t (*SD_getSectorSizeFxn)(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_InitFxn(). + */ +typedef void (*SD_InitFxn)(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_initializeFxn(). + */ +typedef int_fast16_t (*SD_InitializeFxn)(SD_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_OpenFxn(). + */ +typedef SD_Handle (*SD_OpenFxn)(SD_Handle handle, SD_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_readFxn(). + */ +typedef int_fast16_t (*SD_ReadFxn)(SD_Handle handle, void *buf, int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief A function pointer to a driver specific implementation of + * SD_writeFxn(). + */ +typedef int_fast16_t (*SD_WriteFxn)(SD_Handle handle, const void *buf, int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief The definition of a SD function table that contains the + * required set of functions to control a specific SD driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified peripheral */ + SD_CloseFxn closeFxn; + /*! Function to implementation specific control function */ + SD_ControlFxn controlFxn; + /*! Function to return the total number of sectors on the SD card */ + SD_getNumSectorsFxn getNumSectorsFxn; + /*! Function to return the sector size used to address the SD card */ + SD_getSectorSizeFxn getSectorSizeFxn; + /*! Function to initialize the given data object */ + SD_InitFxn initFxn; + /*! Function to initialize the SD card */ + SD_InitializeFxn initializeFxn; + /*! Function to open the specified peripheral */ + SD_OpenFxn openFxn; + /*! Function to read from the SD card */ + SD_ReadFxn readFxn; + /*! Function to write to the SD card */ + SD_WriteFxn writeFxn; +} SD_FxnTable; + +/*! + * @brief SD Global configuration + * + * The SD_Config structure contains a set of pointers used + * to characterize the SD driver implementation. + * + * This structure needs to be defined before calling SD_init() and it must + * not be changed thereafter. + * + * @sa SD_init() + */ +typedef struct SD_Config_ +{ + /*! Pointer to a table of driver-specific implementations of SD APIs */ + SD_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SD_Config; + +/*! + * @brief Function to close a SD peripheral specified by the SD handle. + * + * @pre SD_open() had to be called first. + * + * @param handle A #SD_Handle returned from SD_open() + * + * @sa SD_open() + */ +extern void SD_close(SD_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #SD_Handle. + * + * Commands for SD_control can originate from SD.h or from implementation + * specific SD*.h files. + * While commands from SD.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SD*.h files add + * unique driver capabilities but are not API portable across all SD driver + * implementations. + * + * Commands supported by SD.h follow a SD*_CMD naming + * convention. + * + * Commands supported by SD*.h follow a SD*_CMD naming + * convention. + * Each control command defines arg differently. The types of arg are + * documented with each command. + * + * See @ref SD_CMD "SD_control command codes" for command codes. + * + * See @ref SD_STATUS "SD_control return status codes" for status codes. + * + * @pre SD_open() has to be called first. + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param cmd SD.h or SD*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd. + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SD_open() + */ +extern int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Function to obtain the total number of sectors on the SD card. + * Note: Total Card capacity is the (NumberOfSectors * SectorSize). + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return The total number of sectors on the SD card, + * or 0 if an error occurred. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getNumSectors(SD_Handle handle); + +/*! + * @brief Function to obtain the sector size used to access the SD card. + * + * @pre SD Card has been initialized using SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return The sector size set for use during SD card read/write operations. + * + * @sa SD_initialize() + */ +extern uint_fast32_t SD_getSectorSize(SD_Handle handle); + +/*! + * @brief This function initializes the SD driver. + * + * @pre The SD_config[] array must exist and be persistent before this + * function can be called. This function must also be called before + * any other SD driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SD_init(void); + +/*! + * @brief Function to initialize the #SD_Params struct to its defaults. + * + * @param params A pointer to #SD_Params structure for initialization. + */ +extern void SD_Params_init(SD_Params *params); + +/*! + * @brief Function to initialize the SD card. + * + * @pre SD controller has been opened by calling SD_open(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the initialization, + * #SD_STATUS_ERROR otherwise. + */ +extern int_fast16_t SD_initialize(SD_Handle handle); + +/*! + * @brief Function to open the SD peripheral with the index and parameters + * specified. + * + * @pre SD controller has been initialized using SD_init(). + * + * @param index Logical peripheral number for the SD indexed into + * the SD_config[] table. + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #SD_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SD_init() + * @sa SD_close() + */ +extern SD_Handle SD_open(uint_least8_t index, SD_Params *params); + +/*! + * @brief Function that reads the specified sectors from the SD card. + * The destination is specified by \a buf. The starting sector + * is specified by \a sector and the total number of sectors to + * read is provided by \a secCount. + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param buf Pointer to a buffer to read data into. + * + * @param sector Starting sector on the disk to read from. + * + * @param secCount Number of sectors to be read. + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the write, + * #SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_read(SD_Handle handle, void *buf, int_fast32_t sector, uint_fast32_t secCount); + +/*! + * @brief Function that writes data to the specified sectors of the SD card. + * The source is specified by \a buf. The starting sector to write + * is specified by \a sector and the total number of sectors to write + * is provided by \a secCount. + * + * @pre SD controller has been opened and initialized by calling SD_open() + * followed by SD_initialize(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @param buf Pointer to a buffer containing data to write to disk. + * + * @param sector Starting sector on the disk to write to. + * + * @param secCount Number of sectors to be written. + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the write, + * #SD_STATUS_ERROR otherwise. + * + * @sa SD_initialize() + */ +extern int_fast16_t SD_write(SD_Handle handle, const void *buf, int_fast32_t sector, uint_fast32_t secCount); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SD__include */ diff --git a/simplelink_lpf2/source/ti/drivers/SDFatFS.c b/simplelink_lpf2/source/ti/drivers/SDFatFS.c new file mode 100644 index 00000000..3c47256d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SDFatFS.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* + * By default disable both asserts and log for this module. + * This must be done before DebugP.h is included. + */ +#ifndef DebugP_ASSERT_ENABLED + #define DebugP_ASSERT_ENABLED 0 +#endif +#ifndef DebugP_LOG_ENABLED + #define DebugP_LOG_ENABLED 0 +#endif + +#include +#include +#include +#include + +#include + +/* SDFatFS Specific Defines */ +#define DRIVE_NOT_MOUNTED (~(0U)) + +extern const SDFatFS_Config SDFatFS_config[]; +extern const uint_least8_t SDFatFS_count; + +static bool isInitialized = false; + +/* + * Array of SDFatFS_Handles to determine the association of the + * FatFs drive number with a SDFatFS_Handle. + * FF_VOLUMES is defined in . + */ +static SDFatFS_Handle sdFatFSHandles[FF_VOLUMES]; + +/* FatFS function prototypes */ +DSTATUS SDFatFS_diskInitialize(BYTE drive); +DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer); +DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, DWORD sector, UINT secCount); +DSTATUS SDFatFS_diskStatus(BYTE drive); +DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, DWORD sector, UINT secCount); + +/* + * ======== SDFatFS_close ======== + */ +void SDFatFS_close(SDFatFS_Handle handle) +{ + TCHAR path[3]; + DRESULT dresult; + FRESULT fresult; + SDFatFS_Object *obj = handle->object; + + /* Construct base directory path */ + path[0] = (TCHAR)'0' + obj->driveNum; + path[1] = (TCHAR)':'; + path[2] = (TCHAR)'\0'; + + /* Close the SD driver */ + SD_close(obj->sdHandle); + + /* Unmount the FatFs drive */ + fresult = f_mount(NULL, path, 0); + if (fresult != FR_OK) + { + DebugP_log1("SDFatFS: Could not unmount FatFs volume @ drive" + " number %d", + obj->driveNum); + } + + /* Unregister the disk_*() functions */ + dresult = disk_unregister(obj->driveNum); + if (dresult != RES_OK) + { + DebugP_log1("SDFatFS: Error unregistering disk" + " functions @ drive number %d", + obj->driveNum); + } + + obj->driveNum = DRIVE_NOT_MOUNTED; + DebugP_log0("SDFatFS closed"); +} + +/* + * ======== SDFatFS_diskInitialize ======== + */ +DSTATUS SDFatFS_diskInitialize(BYTE drive) +{ + int_fast8_t result; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + result = SD_initialize(obj->sdHandle); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) + { + obj->diskState = ((DSTATUS)obj->diskState) & ~((DSTATUS)STA_NOINIT); + } + + return (obj->diskState); +} + +/* + * ======== SDFatFS_diskIOctrl ======== + * Function to perform specified disk operations. This function is called by the + * FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer) +{ + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + DRESULT fatfsRes = RES_ERROR; + + switch (ctrl) + { + case CTRL_SYNC: + fatfsRes = RES_OK; + break; + + case (BYTE)GET_SECTOR_COUNT: + *(uint32_t *)buffer = (uint32_t)SD_getNumSectors(obj->sdHandle); + + DebugP_log1("SDFatFS: Disk IO control: sector count: %d", *(uint32_t *)buffer); + fatfsRes = RES_OK; + break; + + case (BYTE)GET_SECTOR_SIZE: + *(WORD *)buffer = (WORD)SD_getSectorSize(obj->sdHandle); + DebugP_log1("SDFatFS: Disk IO control: sector size: %d", *(WORD *)buffer); + fatfsRes = RES_OK; + break; + + case (BYTE)GET_BLOCK_SIZE: + *(WORD *)buffer = (WORD)SD_getSectorSize(obj->sdHandle); + DebugP_log1("SDFatFS: Disk IO control: block size: %d", *(WORD *)buffer); + fatfsRes = RES_OK; + break; + + default: + DebugP_log0("SDFatFS: Disk IO control parameter error"); + fatfsRes = RES_PARERR; + break; + } + return (fatfsRes); +} + +/* + * ======== SDFatFS_diskRead ======== + * Function to perform a disk read from the SDCard. This function is called by + * the FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, DWORD sector, UINT secCount) +{ + int_fast32_t result; + DRESULT fatfsRes = RES_ERROR; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + /* Return if disk not initialized */ + if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) + { + fatfsRes = RES_PARERR; + } + else + { + result = SD_read(obj->sdHandle, (uint_least8_t *)buffer, (int_least32_t)sector, (uint_least32_t)secCount); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) + { + fatfsRes = RES_OK; + } + } + + return (fatfsRes); +} + +/* + * ======== SDFatFS_diskStatus ======== + * Function to return the current disk status. This function is called by + * the FatFs module and must not be called by the application! + */ +DSTATUS SDFatFS_diskStatus(BYTE drive) +{ + return (((SDFatFS_Object *)sdFatFSHandles[drive]->object)->diskState); +} + +#if (_READONLY == 0) +/* + * ======== SDFatFS_diskWrite ======== + * Function to perform a write to the SDCard. This function is called by + * the FatFs module and must not be called by the application! + */ +DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, DWORD sector, UINT secCount) +{ + int_fast32_t result; + DRESULT fatfsRes = RES_ERROR; + SDFatFS_Object *obj = sdFatFSHandles[drive]->object; + + /* Return if disk not initialized */ + if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) + { + fatfsRes = RES_PARERR; + } + else + { + result = SD_write(obj->sdHandle, + (const uint_least8_t *)buffer, + (int_least32_t)sector, + (uint_least32_t)secCount); + + /* Convert lower level driver status code */ + if (result == SD_STATUS_SUCCESS) + { + fatfsRes = RES_OK; + } + } + + return (fatfsRes); +} +#endif + +/* + * ======== SDFatFS_init ======== + */ +void SDFatFS_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + SDFatFS_Object *obj; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Initialize each SDFatFS object */ + for (i = 0; i < SDFatFS_count; i++) + { + obj = ((SDFatFS_Handle) & (SDFatFS_config[i]))->object; + + obj->diskState = STA_NOINIT; + obj->driveNum = DRIVE_NOT_MOUNTED; + } + + /* Initialize the SD Driver */ + SD_init(); + } + + HwiP_restore(key); +} + +/* + * ======== SDFatFS_open ======== + * Note: The index passed into this function must correspond directly + * to the SD driver index. + */ +SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive) +{ + uintptr_t key; + DRESULT dresult; + FRESULT fresult; + TCHAR path[3]; + SDFatFS_Handle handle = NULL; + SDFatFS_Object *obj; + + /* Verify driver index and state */ + if (isInitialized && (idx < SDFatFS_count)) + { + /* Get handle for this driver instance */ + handle = (SDFatFS_Handle) & (SDFatFS_config[idx]); + obj = handle->object; + + /* Determine if the device was already opened */ + key = HwiP_disable(); + if (obj->driveNum != DRIVE_NOT_MOUNTED) + { + HwiP_restore(key); + DebugP_log1("SDFatFS Drive %d already in use!", obj->driveNum); + handle = NULL; + } + else + { + obj->driveNum = drive; + HwiP_restore(key); + + /* Open SD Driver */ + obj->sdHandle = SD_open(idx, NULL); + + if (obj->sdHandle == NULL) + { + obj->driveNum = DRIVE_NOT_MOUNTED; + /* Error occurred in lower level driver */ + handle = NULL; + } + else + { + + /* Register FATFS Functions */ + dresult = disk_register(obj->driveNum, + SDFatFS_diskInitialize, + SDFatFS_diskStatus, + SDFatFS_diskRead, + SDFatFS_diskWrite, + SDFatFS_diskIOctrl); + + /* Check for drive errors */ + if (dresult != RES_OK) + { + DebugP_log0("SDFatFS: Disk functions not registered"); + SDFatFS_close(handle); + handle = NULL; + } + else + { + + /* Construct base directory path */ + path[0] = (TCHAR)'0' + obj->driveNum; + path[1] = (TCHAR)':'; + path[2] = (TCHAR)'\0'; + + /* + * Register the filesystem with FatFs. This operation does + * not access the SDCard yet. + */ + fresult = f_mount(&(obj->filesystem), path, 0); + if (fresult != FR_OK) + { + DebugP_log1("SDFatFS: Drive %d not mounted", obj->driveNum); + + SDFatFS_close(handle); + handle = NULL; + } + else + { + + /* + * Store the new sdfatfs handle for the input drive + * number + */ + sdFatFSHandles[obj->driveNum] = handle; + + DebugP_log0("SDFatFS: opened"); + } + } + } + } + } + + return (handle); +} diff --git a/simplelink_lpf2/source/ti/drivers/SDFatFS.h b/simplelink_lpf2/source/ti/drivers/SDFatFS.h new file mode 100644 index 00000000..2ec5e852 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SDFatFS.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2016-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file SDFatFS.h + * + * @brief File Allocation Table File System (FATFS) Driver + * + * The SDFatFS header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * @anchor ti_drivers_SDFatFS_Overview + * # Overview # + * + * The SDFatFS driver is designed to hook into FatFs by implementing a + * set of functions that FatFs needs to call to perform basic block data + * transfers. This driver makes use of the SD driver for lower level disk IO + * operations. + * + * The only functions that should be called by the application are the + * standard driver framework functions (_open, _close, etc...). + * + * The application may use the FatFs APIs or the standard C + * runtime file I/O calls (fopen, fclose, etc...) given that SDFatFS_open has + * has been successfully called. After the SDFatFS_close API is called, + * ensure the application does NOT make any file I/O calls. + * + * ## Opening the driver # + * + * @code + * SDFatFS_Handle handle; + * + * handle = SDFatFS_open(CONFIG_SDFatFS0, driveNum, NULL); + * if (handle == NULL) { + * //Error opening SDFatFS driver + * while (1); + * } + * @endcode + * + * # Instrumentation # + * + * The SDFatFS driver interface produces log statements if + * instrumentation is enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic operations performed | + * Diags_USER2 | detailed operations performed | + * ============================================================================ + */ + +#ifndef ti_drivers_SDFatFS__include +#define ti_drivers_SDFatFS__include + +#include + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief SDFatFS Object + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint_fast32_t driveNum; + DSTATUS diskState; + FATFS filesystem; /* FATFS data object */ + SD_Handle sdHandle; +} SDFatFS_Object; + +/*! + * @brief SDFatFS Global configuration + * + * The #SDFatFS_Config structure contains a single pointer used to characterize + * the SDFatFS driver implementation. + * + * This structure needs to be defined before calling SDFatFS_init() and it must + * not be changed thereafter. + * + * @sa SDFatFS_init() + */ +typedef struct +{ + /*! Pointer to a SDFatFS object */ + SDFatFS_Object *object; +} SDFatFS_Config; + +/*! + * @brief A handle that is returned from a SDFatFS_open() call. + */ +typedef SDFatFS_Config *SDFatFS_Handle; + +/*! + * @brief Function to open a SDFatFS instance on the specified drive. + * + * Function to mount the FatFs filesystem and register the SDFatFS disk + * I/O functions with the FatFS module. + * + * @param idx Logical peripheral number indexed into the HWAttrs + * table. + * @param drive Drive Number + */ +extern SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive); + +/*! + * @brief Function to close a SDFatFS instance specified by the SDFatFS + * handle. + * + * This function unmounts the file system mounted by SDFatFS_open() and + * unregisters the SDFatFS driver from the FatFs module. + * + * @pre SDFatFS_open() had to be called first. + * + * @param handle A #SDFatFS_Handle returned from SDFatFS_open() + * + * @sa SDFatFS_open() + */ +extern void SDFatFS_close(SDFatFS_Handle handle); + +/*! + * Function to initialize a SDFatFS instance + */ +extern void SDFatFS_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SDFatFS__include */ diff --git a/simplelink_lpf2/source/ti/drivers/SHA2.c b/simplelink_lpf2/source/ti/drivers/SHA2.c new file mode 100644 index 00000000..512d9707 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SHA2.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SHA2.c ======== + * + * This file contains default values for the SHA2_Params struct. + * + */ + +#include +#include +#include + +const SHA2_Params SHA2_defaultParams = { + .hashType = SHA2_HASH_TYPE_256, + .returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING, + .callbackFxn = NULL, + .timeout = (uint32_t)SemaphoreP_WAIT_FOREVER, +}; + +void SHA2_Params_init(SHA2_Params *params) +{ + *params = SHA2_defaultParams; +} + +/* + * ======== SHA2_open ======== + */ +__attribute__((weak)) SHA2_Handle SHA2_open(uint_least8_t index, const SHA2_Params *params) +{ + DebugP_assert(index < SHA2_count); + + SHA2_Config *config = (SHA2_Config *)&SHA2_config[index]; + return SHA2_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/SHA2.h b/simplelink_lpf2/source/ti/drivers/SHA2.h new file mode 100644 index 00000000..15f68af8 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SHA2.h @@ -0,0 +1,948 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file SHA2.h + * + * @brief SHA2 driver header + * + * @anchor ti_drivers_SHA2_Overview + * # Overview # + * + * SHA2 (Secure Hash Algorithm 2) is a cryptographic hashing algorithm that + * maps an input of arbitrary length to a fixed-length output with negligible + * probability of collision. A collision would occur when two different inputs + * map to the same output. + * + * It is not currently technologically feasible to derive an input from + * the hash digest (output) itself. + * + * Hashes are often used to ensure the integrity of messages. They are also + * used to as constituent parts of more complicated cryptographic schemes. + * HMAC is a message authentication code that is based on hash functions such + * as SHA2 rather than a block cipher. + * Hashes may themselves be used as or form a part of key derivation functions + * used to derive symmetric keys from sources of entropy such as an Elliptic + * Curve Diffie-Helman key exchange (ECDH). + * + * SHA2 is not actually a single algorithm, but a suite of similar algorithms + * that produce hash digests of different lengths. 224, 256, 384, and 512-bit + * outputs are available. + * + * "Hash" may refer to either the process of hashing when used as a verb and + * the output digest when used as a noun. + * + * @anchor ti_drivers_SHA2_Usage + * # Usage # + * + * Before starting a SHA2 operation, the application must do the following: + * - Call #SHA2_init() to initialize the driver + * - Call #SHA2_Params_init() to initialize the SHA2_Params to default values. + * - Modify the #SHA2_Params as desired + * - Call #SHA2_open() to open an instance of the driver + * + * There are two general ways to execute a SHA2 operation: + * + * - one-step (in one operation) + * - multi-step (multiple partial operations) + + * @anchor ti_drivers_SHA2_Synopsis + * # Synopsis + * + * @anchor ti_drivers_SHA2_Synopsis_Code + * @code + * + * // Import SHA2 Driver definitions + * #include + * + * // Define name for SHA2 channel index + * #define SHA2_INSTANCE 0 + * + * SHA2_init(); + * + * handle = SHA2_open(SHA2_INSTANCE, NULL); + * + * // For CC27XX devices only, + * // Since the SHA2 driver for CC27XX relies on one HW engine (the HSM) for all of its operations + * // If the HSM boot up sequence fails, SHA2_open() will return NULL. + * if (!handle) { + * // Handle error + * } + * + * result = SHA2_hashData(handle, message, strlen(message), actualDigest); + * + * SHA2_close(handle); + * @endcode + * + * @anchor ti_drivers_SHA2_Examples + * # Examples # + * + * ## One-step hash operation # + * + * The #SHA2_hashData() function can perform a SHA2 operation in a single call. + * It will always use the most highly optimized routine with the least overhead and + * the fastest runtime. However, it requires that the entire input message is + * available to the function in a contiguous location at the start of the call. + * The single call operation is required when hashing a message with a length smaller + * than or equal to one hash-block length. All devices support single call operations. + * + * After a SHA2 operation completes, the application may either start + * another operation or close the driver by calling #SHA2_close(). + * + * @code + * SHA2_Params params; + * SHA2_Handle handle; + * int_fast16_t result; + * + * char message[] = "A Ferengi without profit is no Ferengi at all."; + * + * uint8_t actualDigest[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedDigest[] = { + * 0x93, 0xD6, 0x5C, 0x07, + * 0xA6, 0x26, 0x88, 0x9C, + * 0x87, 0xCC, 0x82, 0x24, + * 0x47, 0xC6, 0xE4, 0x28, + * 0xC0, 0xBD, 0xC6, 0xED, + * 0xAA, 0x8C, 0xD2, 0x53, + * 0x77, 0xAA, 0x73, 0x14, + * 0xA3, 0xE2, 0xDE, 0x43 + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * assert(handle != NULL); + * + * result = SHA2_hashData(handle, message, strlen(message), actualDigest); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = memcmp(actualDigest, expectedDigest, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + * + * ## Partial hash operation # + * + * When trying to operate on data that is too large to fit into available memory, + * partial processing is more advisable. The segments are processed with + * #SHA2_addData() whereas the final digest is computed by #SHA2_finalize(). + * + * @code + * SHA2_Handle handle; + * int_fast16_t result; + * SHA2_Params params; + * + * const char message[] = + * "Premature optimization is the root of all evil (or at least most of it) in programming."; + * + * uint8_t actualDigest[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedDigest[] = { + * 0xF2, 0x6A, 0xFF, 0x01, + * 0x11, 0x6B, 0xF6, 0x77, + * 0x63, 0x91, 0xFE, 0xD9, + * 0x47, 0x56, 0x99, 0xB2, + * 0xAD, 0x7D, 0x64, 0x16, + * 0xF7, 0x40, 0x1A, 0x5B, + * 0xCC, 0xC7, 0x08, 0x3D, + * 0xE8, 0x6B, 0x35, 0x6D, + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * assert(handle != NULL); + * + * // We can configure the driver even after SHA2_open() + * result = SHA2_setHashType(handle, SHA2_HASH_TYPE_256); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Process data in chunks. The driver buffers incomplete blocks internally. + * result = SHA2_addData(handle, &message[0], 17); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = SHA2_addData(handle, &message[17], strlen(message) - 17); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Compute the resulting digest + * result = SHA2_finalize(handle, actualDigest); + * assert(result == SHA2_STATUS_SUCCESS); + * + * // Verify + * result = memcmp(actualDigest, expectedDigest, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + * + * ## One-step HMAC operation # + * + * The #SHA2_hmac() function can perform a SHA2 operation in a single call. + * It will always use the most highly optimized routine with the least overhead + * and the fastest runtime. It requires that the entire input message is + * available to the function in a contiguous location at the start of the call. + * + * After a SHA2 operation completes, the application may either start + * another operation or close the driver by calling #SHA2_close(). + * + * @code + * SHA2_Params params; + * SHA2_Handle handle; + * int_fast16_t result; + * CryptoKey hmacKey; + * + * uint8_t message[] = { + * 0xb1, 0x68, 0x9c, 0x25, 0x91, 0xea, 0xf3, 0xc9, + * 0xe6, 0x60, 0x70, 0xf8, 0xa7, 0x79, 0x54, 0xff, + * 0xb8, 0x17, 0x49, 0xf1, 0xb0, 0x03, 0x46, 0xf9, + * 0xdf, 0xe0, 0xb2, 0xee, 0x90, 0x5d, 0xcc, 0x28, + * 0x8b, 0xaf, 0x4a, 0x92, 0xde, 0x3f, 0x40, 0x01, + * 0xdd, 0x9f, 0x44, 0xc4, 0x68, 0xc3, 0xd0, 0x7d, + * 0x6c, 0x6e, 0xe8, 0x2f, 0xac, 0xea, 0xfc, 0x97, + * 0xc2, 0xfc, 0x0f, 0xc0, 0x60, 0x17, 0x19, 0xd2, + * 0xdc, 0xd0, 0xaa, 0x2a, 0xec, 0x92, 0xd1, 0xb0, + * 0xae, 0x93, 0x3c, 0x65, 0xeb, 0x06, 0xa0, 0x3c, + * 0x9c, 0x93, 0x5c, 0x2b, 0xad, 0x04, 0x59, 0x81, + * 0x02, 0x41, 0x34, 0x7a, 0xb8, 0x7e, 0x9f, 0x11, + * 0xad, 0xb3, 0x04, 0x15, 0x42, 0x4c, 0x6c, 0x7f, + * 0x5f, 0x22, 0xa0, 0x03, 0xb8, 0xab, 0x8d, 0xe5, + * 0x4f, 0x6d, 0xed, 0x0e, 0x3a, 0xb9, 0x24, 0x5f, + * 0xa7, 0x95, 0x68, 0x45, 0x1d, 0xfa, 0x25, 0x8e}; + * + * // In this case, keyingMaterial is 40 bytes long. It could also be + * // any other length. + * uint8_t keyingMaterial[] = { + * 0x97, 0x79, 0xd9, 0x12, 0x06, 0x42, 0x79, 0x7f, + * 0x17, 0x47, 0x02, 0x5d, 0x5b, 0x22, 0xb7, 0xac, + * 0x60, 0x7c, 0xab, 0x08, 0xe1, 0x75, 0x8f, 0x2f, + * 0x3a, 0x46, 0xc8, 0xbe, 0x1e, 0x25, 0xc5, 0x3b, + * 0x8c, 0x6a, 0x8f, 0x58, 0xff, 0xef, 0xa1, 0x76}; + * + * + * + * uint8_t actualHmac[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedHmac[] = { + * 0x76, 0x9f, 0x00, 0xd3, 0xe6, 0xa6, 0xcc, 0x1f, + * 0xb4, 0x26, 0xa1, 0x4a, 0x4f, 0x76, 0xc6, 0x46, + * 0x2e, 0x61, 0x49, 0x72, 0x6e, 0x0d, 0xee, 0x0e, + * 0xc0, 0xcf, 0x97, 0xa1, 0x66, 0x05, 0xac, 0x8b + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * assert(handle != NULL); + * + * CryptoKeyPlaintext_initKey(&hmacKey, + * keyingMaterial, + * sizeof(keyingMaterial)); + * + * result = SHA2_hmac(handle, + * &hmacKey, + * message, + * sizeof(message), + * actualHmac); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = memcmp(actualHmac, expectedHmac, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + * + * ## One-step HMAC operation for CC27XX # + * + * The #SHA2_hmac() function can perform a SHA2 operation in a single call. + * It will always use the most highly optimized routine with the least overhead + * and the fastest runtime. It requires that the entire input message is + * available to the function in a contiguous location at the start of the call. + * + * After a SHA2 operation completes, the application may either start + * another operation or close the driver by calling #SHA2_close(). + * + * @code + * SHA2_Params params; + * SHA2_Handle handle; + * int_fast16_t result; + * CryptoKey hmacKey; + * + * uint8_t message[] = { + * 0xb1, 0x68, 0x9c, 0x25, 0x91, 0xea, 0xf3, 0xc9, + * 0xe6, 0x60, 0x70, 0xf8, 0xa7, 0x79, 0x54, 0xff, + * 0xb8, 0x17, 0x49, 0xf1, 0xb0, 0x03, 0x46, 0xf9, + * 0xdf, 0xe0, 0xb2, 0xee, 0x90, 0x5d, 0xcc, 0x28, + * 0x8b, 0xaf, 0x4a, 0x92, 0xde, 0x3f, 0x40, 0x01, + * 0xdd, 0x9f, 0x44, 0xc4, 0x68, 0xc3, 0xd0, 0x7d, + * 0x6c, 0x6e, 0xe8, 0x2f, 0xac, 0xea, 0xfc, 0x97, + * 0xc2, 0xfc, 0x0f, 0xc0, 0x60, 0x17, 0x19, 0xd2, + * 0xdc, 0xd0, 0xaa, 0x2a, 0xec, 0x92, 0xd1, 0xb0, + * 0xae, 0x93, 0x3c, 0x65, 0xeb, 0x06, 0xa0, 0x3c, + * 0x9c, 0x93, 0x5c, 0x2b, 0xad, 0x04, 0x59, 0x81, + * 0x02, 0x41, 0x34, 0x7a, 0xb8, 0x7e, 0x9f, 0x11, + * 0xad, 0xb3, 0x04, 0x15, 0x42, 0x4c, 0x6c, 0x7f, + * 0x5f, 0x22, 0xa0, 0x03, 0xb8, 0xab, 0x8d, 0xe5, + * 0x4f, 0x6d, 0xed, 0x0e, 0x3a, 0xb9, 0x24, 0x5f, + * 0xa7, 0x95, 0x68, 0x45, 0x1d, 0xfa, 0x25, 0x8e}; + * + * // In this case, keyingMaterial is 40 bytes long. It could also be + * // any other length. + * uint8_t keyingMaterial[] = { + * 0x97, 0x79, 0xd9, 0x12, 0x06, 0x42, 0x79, 0x7f, + * 0x17, 0x47, 0x02, 0x5d, 0x5b, 0x22, 0xb7, 0xac, + * 0x60, 0x7c, 0xab, 0x08, 0xe1, 0x75, 0x8f, 0x2f, + * 0x3a, 0x46, 0xc8, 0xbe, 0x1e, 0x25, 0xc5, 0x3b, + * 0x8c, 0x6a, 0x8f, 0x58, 0xff, 0xef, 0xa1, 0x76}; + * + * + * + * uint8_t actualHmac[SHA2_DIGEST_LENGTH_BYTES_256]; + * uint8_t expectedHmac[] = { + * 0x76, 0x9f, 0x00, 0xd3, 0xe6, 0xa6, 0xcc, 0x1f, + * 0xb4, 0x26, 0xa1, 0x4a, 0x4f, 0x76, 0xc6, 0x46, + * 0x2e, 0x61, 0x49, 0x72, 0x6e, 0x0d, 0xee, 0x0e, + * 0xc0, 0xcf, 0x97, 0xa1, 0x66, 0x05, 0xac, 0x8b + * }; + * + * SHA2_init(); + * + * SHA2_Params_init(¶ms); + * params.returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING; + * handle = SHA2_open(0, ¶ms); + * + * // For CC27XX devices only, + * // Since the SHA2 driver for CC27XX relies on one HW engine (the HSM) for all of its operations + * // If the HSM boot up sequence fails, SHA2_open() will return NULL. + * assert(handle != NULL); + * + * CryptoKeyPlaintextHSM_initKey(&hmacKey, + * keyingMaterial, + * sizeof(keyingMaterial)); + * + * result = SHA2_hmac(handle, + * &hmacKey, + * message, + * sizeof(message), + * actualHmac); + * assert(result == SHA2_STATUS_SUCCESS); + * + * result = memcmp(actualHmac, expectedHmac, SHA2_DIGEST_LENGTH_BYTES_256); + * assert(result == 0); + * + * SHA2_close(handle); + * @endcode + */ + +#ifndef ti_drivers_SHA2__include +#define ti_drivers_SHA2__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common SHA2 status code reservation offset. + * SHA2 driver implementations should offset status codes with + * SHA2_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SHA2XYZ_STATUS_ERROR0 SHA2_STATUS_RESERVED - 0 + * #define SHA2XYZ_STATUS_ERROR1 SHA2_STATUS_RESERVED - 1 + * #define SHA2XYZ_STATUS_ERROR2 SHA2_STATUS_RESERVED - 2 + * @endcode + */ +#define SHA2_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return SHA2_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define SHA2_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return SHA2_STATUS_ERROR if the function was not executed + * successfully and no more specific error is applicable. + */ +#define SHA2_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * SHA2 driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define SHA2_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief The ongoing operation was canceled. + */ +#define SHA2_STATUS_CANCELED ((int_fast16_t)-3) + +/*! + * @brief The requested operation or configuration is not + * supported by the device specific implementation. + */ +#define SHA2_STATUS_UNSUPPORTED ((int_fast16_t)-4) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return SHA2_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define SHA2_STATUS_KEYSTORE_ERROR ((int_fast16_t)-5) + +/*! + * @brief The requested operation involves a DMA transfer larger than + * the hardware's DMA controller can handle. + * + * Functions return SHA2_STATUS_DMA_ERROR only on CC27XX devices, as + * large DMA transfers will not be automatically segmented into multiple + * token transactions. + */ +#define SHA2_STATUS_DMA_ERROR ((int_fast16_t)-6) + +/*! + * @brief The requested operation contains data that cannot be accessed by + * the HSM Module. + * + * Functions return SHA2_STATUS_DATA_INACCESSIBLE only on CC35XX devices, since + * HSM module on CC35XX cannot access external flash and data must be in RAM. + */ +#define SHA2_STATUS_DATA_INACCESSIBLE ((int_fast16_t)-7) + +/*! + * @brief The way in which SHA2 function calls return after performing an + * operation. + * + * Not all SHA2 operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * SHA2 functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |--------------------------------|-------|-------|-------| + * |SHA2_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |SHA2_RETURN_BEHAVIOR_BLOCKING | X | | | + * |SHA2_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + SHA2_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * SHA2 operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + SHA2_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the SHA2 operation goes + * on in the background. SHA2 operation results are available + * after the function returns. + */ + SHA2_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while the SHA2 + * operation goes on in the background. SHA2 operation results + * are available after the function returns. + */ +} SHA2_ReturnBehavior; + +/*! + * @brief Enum for the hash types supported by the driver. + */ +typedef enum +{ + SHA2_HASH_TYPE_224 = 0, + SHA2_HASH_TYPE_256 = 1, + SHA2_HASH_TYPE_384 = 2, + SHA2_HASH_TYPE_512 = 3, +} SHA2_HashType; + +/*! + * @brief Enum for the hash digest lengths in bytes supported by the driver. + */ +typedef enum +{ + SHA2_DIGEST_LENGTH_BYTES_224 = 28, + SHA2_DIGEST_LENGTH_BYTES_256 = 32, + SHA2_DIGEST_LENGTH_BYTES_384 = 48, + SHA2_DIGEST_LENGTH_BYTES_512 = 64, +} SHA2_DigestLengthBytes; + +/*! + * @brief Enum for the block sizes of the algorithms. + * + * SHA2 iteratively consumes segments of the block + * size and computes intermediate digests which are + * fed back into the algorithm together with the next + * segment to compute the next intermediate or final + * digest. + * The block sizes of the algorithms differ from their + * digest lengths. When performing partial hashes, + * the segment lengths for all but the last segment + * must be multiples of the relevant block size. + */ +typedef enum +{ + SHA2_BLOCK_SIZE_BYTES_224 = 64, + SHA2_BLOCK_SIZE_BYTES_256 = 64, + SHA2_BLOCK_SIZE_BYTES_384 = 128, + SHA2_BLOCK_SIZE_BYTES_512 = 128, +} SHA2_BlockSizeBytes; + +/*! + * @brief SHA2 Global configuration + * + * The %SHA2_Config structure contains a set of pointers used to characterize + * the SHA2 driver implementation. + * + * This structure needs to be defined before calling #SHA2_init() and it must + * not be changed thereafter. + * + * @sa SHA2_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SHA2_Config; + +/*! + * @brief A handle that is returned from an SHA2_open() call. + */ +typedef SHA2_Config *SHA2_Handle; + +/*! + * @brief The definition of a callback function used by the SHA2 driver + * when used in ::SHA2_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the SHA2 operation. + * + * @param returnStatus The result of the SHA2 operation. May contain an error code. + * Informs the application of why the callback function was + * called. + */ +typedef void (*SHA2_CallbackFxn)(SHA2_Handle handle, int_fast16_t returnStatus); + +/*! + * @brief SHA2 Parameters + * + * SHA2 Parameters are used to with the SHA2_open() call. Default values for + * these parameters are set using SHA2_Params_init(). + * + * @sa SHA2_Params_init() + */ +typedef struct +{ + SHA2_HashType hashType; /*!< SHA2 variant to use. This determines the output digest + * length. + */ + SHA2_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + SHA2_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::SHA2_RETURN_BEHAVIOR_BLOCKING + */ +} SHA2_Params; + +/*! + * @brief Global SHA2 configuration struct. + * + * Specifies context objects and hardware attributes for every + * driver instance. + * + * This variable is supposed to be defined in the board file. + */ +extern const SHA2_Config SHA2_config[]; + +/*! + * @brief Global SHA2 configuration count. + * + * Specifies the amount of available SHA2 driver instances. + * + * This variable is supposed to be defined in the board file. + */ +extern const uint_least8_t SHA2_count; + +/*! + * @brief Default SHA2_Params structure + * + * @sa #SHA2_Params_init() + */ +extern const SHA2_Params SHA2_defaultParams; + +/*! + * @brief Initializes the SHA2 driver module. + * + * @pre The #SHA2_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other SHA2 driver APIs. This function call does not modify any + * peripheral registers. + */ +void SHA2_init(void); + +/*! + * @brief Initializes \a params with default values. + * + * @param params A pointer to #SHA2_Params structure for + * initialization + * + * Defaults values are: + * returnBehavior = SHA2_RETURN_BEHAVIOR_BLOCKING + * callbackFxn = NULL + * timeout = SemaphoreP_WAIT_FOREVER + * custom = NULL + */ +void SHA2_Params_init(SHA2_Params *params); + +/*! + * @brief Initializes a SHA2 driver instance and returns a handle. + * + * @pre SHA2 controller has been initialized using #SHA2_init() + * + * @param index Logical peripheral number for the SHA2 indexed into + * the #SHA2_config table + * + * @param params Pointer to a parameter block, if NULL it will use + * default values. + * + * @return A #SHA2_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa #SHA2_init(), #SHA2_close() + */ +SHA2_Handle SHA2_open(uint_least8_t index, const SHA2_Params *params); + +/*! + * @brief Closes a SHA2 peripheral specified by \a handle. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from SHA2_open() + * + * @sa #SHA2_open() + */ +void SHA2_close(SHA2_Handle handle); + +/*! + * @brief Starts an HMAC operation on segmented data + * + * This function uses @c key to compute the all intermediate results involving + * @c key as specified in FIPS 198-1. + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_open() has to be called first. + * + * @post Call #SHA2_addData() and #SHA2_finalizeHmac() + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param key The key with which to sign the message with + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_reset() + */ +int_fast16_t SHA2_setupHmac(SHA2_Handle handle, const CryptoKey *key); + +/*! + * @brief Adds a segment of @c data with a @c length in bytes to the + * cryptographic hash or HMAC. + * + * %SHA2_addData() may be called arbitrary times before finishing the + * operation with #SHA2_finalize(). + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * + * @pre #SHA2_open() has to be called first. + * @pre If computing an HMAC, #SHA2_setupHmac() must be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param data Pointer to the location to read from. + * There might be alignment restrictions on different + * platforms. + * + * @param length Length of the message segment to hash, in bytes. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * @retval #SHA2_STATUS_DMA_ERROR The requested transaction is too + * large for the HSM DMA controller + * to handle. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open(), #SHA2_reset(), #SHA2_finalize() + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void *data, size_t length); + +/*! + * @brief Finishes a hash operation and writes the result to \a digest. + * + * This function finishes a hash operation that has been previously started + * by #SHA2_addData(). + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_addData() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param digest Pointer to the location to write the digest to. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open(), #SHA2_addData() + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest); + +/*! + * @brief Finishes an HMAC operation and writes the result to @c hmac. + * + * This function finishes a an HMAC operation that has been previously started + * by #SHA2_setupHmac() and #SHA2_addData(). + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_setupHmac() must be called prior. + * @pre #SHA2_addData() should be called after #SHA2_setupHmac(). + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param hmac Pointer to the location to write the digest to. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open(), #SHA2_setupHmac() #SHA2_addData() + */ +int_fast16_t SHA2_finalizeHmac(SHA2_Handle handle, void *hmac); + +/*! + * @brief Hashes a segment of \a data with a \a size in bytes and writes the + * resulting hash to \a digest. + * + * The digest content is computed in one step. Intermediate data from a + * previous partial operation started with #SHA2_addData() is discarded. + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param data Pointer to the location to read from. + * There might be alignment restrictions on different + * platforms. + * + * @param dataLength Length of the message @c data, in bytes. + * + * @param digest Pointer to the location to write the digest to. + * There might be alignment restrictions on different + * platforms. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * @retval #SHA2_STATUS_DMA_ERROR The requested transaction is too + * large for the HSM DMA controller + * to handle. + * @retval #SHA2_STATUS_CANCELED The hash operation was canceled. + * + * @sa #SHA2_open() + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void *data, size_t dataLength, void *digest); + +/*! + * @brief Creates a keyed hash of @c data with @c key. + * + * This function signs @c data using @c key using the keyed-hash message + * authentication code (HMAC) algorithm specified in FIPS 198-1. + * + * This function expects all of @c data to be available in contiguous memory. + * + * Intermediate data from a previous + * partial operation started with #SHA2_addData() is discarded. + * + * This function blocks until the final digest hash been computed. + * It returns immediately when ::SHA2_RETURN_BEHAVIOR_CALLBACK is set. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param key The key with which @c data is signed + * + * @param data Pointer to the location to read from. + * There might be alignment restrictions on different platforms. + * + * @param dataLength Length of the message @c data, in bytes. + * + * @param hmac Pointer to the location to write the HMAC to. + * There might be alignment restrictions on different platforms. + * + * @retval #SHA2_STATUS_SUCCESS The hash operation succeeded. + * @retval #SHA2_STATUS_ERROR The hash operation failed. + * @retval #SHA2_STATUS_RESOURCE_UNAVAILABLE The required hardware resource + * was not available. Try again + * later. + * + * @sa #SHA2_open() + */ +int_fast16_t SHA2_hmac(SHA2_Handle handle, const CryptoKey *key, const void *data, size_t dataLength, void *hmac); + +/*! + * @brief Clears internal buffers and aborts an ongoing SHA2 operation. + * + * Clears all internal buffers and the intermediate digest of this driver instance. + * If an asynchronous operation is ongoing, the behavior is the same as for + * #SHA2_cancelOperation(). + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @sa #SHA2_cancelOperation() + */ +void SHA2_reset(SHA2_Handle handle); + +/*! + * @brief Aborts an ongoing SHA2 operation and clears internal buffers. + * + * Aborts an ongoing hash operation of this driver instance. The operation will + * terminate as though an error occurred and the status code of the operation will be + * #SHA2_STATUS_CANCELED in this case. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @retval #SHA2_STATUS_SUCCESS The operation was canceled or there was no + * operation in progress to be canceled. + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle); + +/*! + * @brief Selects a new hash algorithm @a type. + * + * This function changes the hash algorithm type of the hash digest at + * run-time. The hash type is usually specified during #SHA2_open(). + * + * Neither is it allowed to call this function during a running hash operation + * nor during an incomplete multi-step hash operation. In this case + * #SHA2_STATUS_ERROR would be returned. + * + * @pre #SHA2_open() has to be called first. + * + * @param handle A #SHA2_Handle returned from #SHA2_open() + * + * @param type New hash algorithm type + * + * @retval #SHA2_STATUS_SUCCESS Hash type set correctly. + * @retval #SHA2_STATUS_ERROR Error. Platform may not support this hash type. + */ +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type); + +/** + * @brief Constructs a new SHA2 object + * + * Unlike #SHA2_open(), #SHA2_construct() does not require the hwAttrs and + * object to be allocated in a #SHA2_Config array that is indexed into. + * Instead, the #SHA2_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #SHA2_Config describing the location of the object and hwAttrs. + * + * @param params #SHA2_Params to configure the driver instance. + * + * @return Returns a #SHA2_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +SHA2_Handle SHA2_construct(SHA2_Config *config, const SHA2_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SHA2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/SPI.c b/simplelink_lpf2/source/ti/drivers/SPI.c new file mode 100644 index 00000000..72555bad --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SPI.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== SPI.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +extern const SPI_Config SPI_config[]; +extern const uint_least8_t SPI_count; + +/* Default SPI parameters structure */ +const SPI_Params SPI_defaultParams = { + SPI_MODE_BLOCKING, /* transferMode */ + SPI_WAIT_FOREVER, /* transferTimeout */ + NULL, /* transferCallbackFxn */ + SPI_CONTROLLER, /* mode */ + 1000000, /* bitRate */ + 8, /* dataSize */ + SPI_POL0_PHA0, /* frameFormat */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== SPI_close ======== + */ +void SPI_close(SPI_Handle handle) +{ + handle->fxnTablePtr->closeFxn(handle); +} + +/* + * ======== SPI_control ======== + */ +int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg) +{ + return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); +} + +/* + * ======== SPI_init ======== + */ +void SPI_init(void) +{ + uint_least8_t i; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < SPI_count; i++) + { + SPI_config[i].fxnTablePtr->initFxn((SPI_Handle) & (SPI_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== SPI_open ======== + */ +SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params) +{ + SPI_Handle handle = NULL; + + if (isInitialized && (index < SPI_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (SPI_Params *)&SPI_defaultParams; + } + + /* Get handle for this driver instance */ + handle = (SPI_Handle) & (SPI_config[index]); + handle = handle->fxnTablePtr->openFxn(handle, params); + } + + return (handle); +} + +/* + * ======== SPI_Params_init ======== + */ +void SPI_Params_init(SPI_Params *params) +{ + *params = SPI_defaultParams; +} + +/* + * ======== SPI_transfer ======== + */ +bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + return (handle->fxnTablePtr->transferFxn(handle, transaction)); +} + +/* + * ======== SPI_transferCancel ======== + */ +void SPI_transferCancel(SPI_Handle handle) +{ + handle->fxnTablePtr->transferCancelFxn(handle); +} diff --git a/simplelink_lpf2/source/ti/drivers/SPI.h b/simplelink_lpf2/source/ti/drivers/SPI.h new file mode 100644 index 00000000..b96d2561 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/SPI.h @@ -0,0 +1,925 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file SPI.h + * + * @brief Serial Peripheral Interface (SPI) Driver Interface + * + * @anchor ti_drivers_SPI_Overview + * # Overview + * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex + * driver that transmits and receives data on a SPI bus. SPI is sometimes + * called SSI (Synchronous Serial Interface). + * The SPI protocol defines the format of a data transfer over the SPI bus, + * but it leaves flow control, data formatting, and handshaking mechanisms + * to higher-level software layers. + * + * The SPI driver operates on some key definitions and assumptions: + * - The driver operates transparently from the chip select. Some SPI + * controllers feature a hardware chip select to assert SPI peripheral + * peripherals. See the specific device implementations on chip + * select requirements. + * + * - The SPI protocol does not account for a built-in handshaking mechanism + * and neither does this SPI driver. Therefore, when operating in + * #SPI_PERIPHERAL mode, the application must provide such a mechanism to + * ensure that the SPI peripheral is ready for the SPI controller. The SPI + * peripheral must call #SPI_transfer() *before* the SPI controller starts + * transmitting. + * Some example application mechanisms could include: + * - Timed delays on the SPI controller to guarantee the SPI peripheral is + * ready for a SPI transaction. + * - A form of GPIO flow control from the peripheral to the SPI controller to + * notify the controller when ready. + * + *
+ * @anchor ti_drivers_SPI_Usage + * # Usage + * + * To use the SPI driver to send data over the SPI bus, the application + * calls the following APIs: + * - SPI_init(): Initialize the SPI driver. + * - SPI_Params_init(): Initialize a #SPI_Params structure with default + * values. Then change the parameters from non-default values as + * needed. + * - SPI_open(): Open an instance of the SPI driver, passing the + * initialized parameters, or NULL, and an index to the configuration to + * open (detailed later). + * - SPI_transfer(): Transmit/receive data. This function takes a + * #SPI_Transaction argument that describes the transfer that is requested. + * - SPI_close(): De-initialize the SPI instance. + * + * @anchor ti_drivers_SPI_Synopsis + * ## Synopsis + * The following code example opens a SPI instance as a SPI controller, + * and issues a transaction. + * + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[MSGSIZE]; + * uint8_t receiveBuffer[MSGSIZE]; + * bool transferOK; + * + * SPI_init(); // Initialize the SPI driver + * + * SPI_Params_init(&spiParams); // Initialize SPI parameters + * spiParams.dataSize = 8; // 8-bit data size + * + * spi = SPI_open(CONFIG_SPI0, &spiParams); + * if (spi == NULL) { + * while (1); // SPI_open() failed + * } + * + * // Fill in transmitBuffer + * spiTransaction.count = MSGSIZE; + * spiTransaction.txBuf = (void *)transmitBuffer; + * spiTransaction.rxBuf = (void *)receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * while (1); + * } + * @endcode + * + * More details on usage are provided in the following subsections. + * + * @anchor ti_drivers_SPI_Examples + * ## Examples # + * * @ref ti_drivers_SPI_Synopsis "Usage Synopsis" + * * @ref ti_drivers_SPI_Example_openblocking "Open in blocking mode" + * * @ref ti_drivers_SPI_Example_opencallback "Open in callback mode" + * * @ref ti_drivers_SPI_Example_6bitframes "Sending 6 bit frames" + * * @ref ti_drivers_SPI_Example_12bitframes "Sending 12 bit frames" + * * @ref ti_drivers_SPI_Example_callbackarg "Callback function using arg" + * + * ## Initializing the SPI Driver + * + * SPI_init() must be called before any other SPI APIs. This function + * iterates through the elements of the @p SPI_config[] array, calling + * the element's device implementation SPI initialization function. + * + * ## Opening the SPI Driver + * After initializing the SPI driver by calling SPI_init(), the application + * can open a SPI instance by calling SPI_open(). This function + * takes an index into the @p SPI_config[] array, and a SPI parameters data + * structure. The SPI instance is specified by the index of the SPI in + * @p SPI_config[]. Calling SPI_open() a second time with the same index + * previously passed to SPI_open() will result in an error. You can, + * though, re-use the index if the instance is closed via SPI_close(). + * + * If no #SPI_Params structure is passed to SPI_open(), default values are + * used. If the open call is successful, it returns a non-NULL value. + * + * @anchor ti_drivers_SPI_Example_openblocking + * Example opening a SPI driver instance in blocking mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_BLOCKING; + * spi = SPI_open(CONFIG_SPI0, &spiParams); + * + * if (spi == NULL) { + * // Error opening SPI + * while(1); + * } + * @endcode + * + * @anchor ti_drivers_SPI_Example_opencallback + * Example opening a SPI driver instance in callback mode: + * @code + * SPI_Handle spi; + * SPI_Params spiParams; + * + * SPI_Params_init(&spiParams); + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = UserCallbackFxn; + * + * spi = SPI_open(CONFIG_SPI0, &spiParams); + * if (spi == NULL) { + * // Error opening SPI + * while (1); + * } + * @endcode + * + * ## SPI Parameters + * + * The #SPI_Params structure is passed to the SPI_open() call. If NULL + * is passed for the parameters, SPI_open() uses default parameters. + * A #SPI_Params structure is initialized with default values by passing + * it to SPI_Params_init(). + * Some of the SPI parameters are described below. To see brief descriptions + * of all the parameters, see #SPI_Params. + * + * ### SPI Mode + * The SPI driver operates in both SPI controller and SPI peripheral modes. + * Logically, the implementation is identical, however the difference + * between these two modes is driven by hardware. The default mode is + * #SPI_CONTROLLER, but can be set to peripheral mode by setting + * #SPI_Params.mode to #SPI_PERIPHERAL in the parameters passed to SPI_open(). + * See @ref ti_drivers_SPI_ControllerPeripheralModes "Controller/Peripheral Modes" + * for further details. + * + * ### SPI Transfer Mode + * The SPI driver supports two transfer modes of operation: blocking and + * callback. The transfer mode is determined by the transferMode parameter + * in the #SPI_Params data structure. The SPI driver + * defaults to blocking mode, if the application does not set it. + * Once a SPI driver is opened, the only way to change the operation mode + * is to close and re-open the SPI instance with the new transfer mode. + * + * In blocking mode, a task's code execution is blocked until a SPI + * transaction has completed or a timeout has occurred. This ensures + * that only one SPI transfer operates at a given time. Other tasks requesting + * SPI transfers while a transfer is currently taking place will receive + * a FALSE return value. If a timeout occurs the transfer is canceled, the + * task is unblocked & will receive a FALSE return value. The transaction + * count field will have the amount of frames which were transferred + * successfully before the timeout. In blocking mode, transfers cannot be + * performed in software or hardware ISR context. + * + * In callback mode, a SPI transaction functions asynchronously, which + * means that it does not block code execution. After a SPI transaction + * has been completed, the SPI driver calls a user-provided hook function. + * Callback mode is supported in the execution context of tasks and + * hardware interrupt routines. + * + * ### SPI Frame Formats and Data Size + * The SPI driver can configure the device's SPI peripheral to transfer + * data in several SPI format options: SPI (with various polarity and phase + * settings), TI, and Micro-wire. The frame format is set with + * #SPI_Params.frameFormat. Some SPI implementations may not support all frame + * formats & the SPI driver will fail to opened. Refer to the device specific + * implementation documentation for details on which frame formats are + * supported. + * + * The smallest single unit of data transmitted onto the SPI bus is called + * a SPI frame and is of size #SPI_Params.dataSize. A series of SPI frames + * transmitted/received on a SPI bus is referred to as a SPI transaction. + * + * ## SPI Transactions + * + * A SPI transaction consists of a series of SPI frames + * transmitted/received on a SPI bus. A SPI transaction is performed + * using SPI_transfer(). SPI_transfer() accepts a pointer to a + * #SPI_Transaction structure that dictates the quantity of data to be + * sent and received. + * The #SPI_Transaction.txBuf and #SPI_Transaction.rxBuf are both pointers + * to data buffers. If txBuf is NULL, the driver sends SPI frames with all + * data set to the default value specified in the hardware attributes. If + * rxBuf is NULL, the driver discards all SPI frames received. SPI_transfer() + * of a SPI transaction is performed atomically. + * + * @warning The use of NULL as a sentinel txBuf or rxBuf value to determine + * whether the SPI transaction includes a tx or rx component implies + * that it is not possible to perform a transmit or receive transfer + * directly from/to a buffer with a base address of 0x00000000. To support + * this rare use-case, the application will have to manually copy the + * contents of location 0x00000000 to/from a temporary buffer before/after + * the tx/rx SPI transaction. + * + * When the SPI is opened, the dataSize value determines the element types + * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver + * assumes the data buffers are of type uint8_t (unsigned char). If the + * dataSize is from 8 to 16 bits, the driver assumes the data buffers are + * of type uint16_t (unsigned short). If the dataSize is greater than + * 16 bits, the driver assumes the data buffers are uint32_t (unsigned long). + * Some SPI driver implementations may not support all data sizes; refer + * to device specific SPI implementation documentation for details on + * what data sizes are supported. + * + * The optional #SPI_Transaction.arg variable can only be used when the + * SPI driver has been opened in callback mode. This variable is used to + * pass a user-defined value into the user-defined callback function. + * + * SPI_transfer() always performs full-duplex SPI transactions. This means + * the SPI simultaneously receives data as it transmits data. The application + * is responsible for formatting the data to be transmitted as well as + * determining whether the data received is meaningful. + * Specifics about SPI frame formatting and data sizes are provided in + * device-specific data sheets and technical reference manuals. + * + * The following code snippets perform SPI transactions. + * + * @anchor ti_drivers_SPI_Example_6bitframes + * Example transferring 6-bit SPI frames. The transmit and receive + * buffers are of type uint8_t. + * @code + * SPI_Transaction spiTransaction; + * uint8_t transmitBuffer[BUFSIZE]; + * uint8_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 6; + * spi = SPI_open(CONFIG_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * @anchor ti_drivers_SPI_Example_12bitframes + * Example transferring 12-bit SPI frames. The transmit and receive + * buffers are of type uint16_t. + * @code + * SPI_Transaction spiTransaction; + * uint16_t transmitBuffer[BUFSIZE]; + * uint16_t receiveBuffer[BUFSIZE]; + * bool transferOK; + * + * SPI_Params_init(&spiParams); + * spiParams.dataSize = 12; + * spi = SPI_open(CONFIG_SPI0, &spiParams); + * ... + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * + * transferOK = SPI_transfer(spi, &spiTransaction); + * if (!transferOK) { + * // Error in SPI or transfer already in progress. + * } + * @endcode + * + * The following example shows an example of a callback function that + * utilizes the arg parameter. + * @anchor ti_drivers_SPI_Example_callbackarg + * @code + * // SPI is opened with callback function as seen in other examples + * // Our goal is to post a semaphore when transfer with sufficient size + * // completes. + * ... + * // Pass pointer to an initialized semaphore to callback via arg + * spiTransaction.count = someIntegerValue; + * spiTransaction.txBuf = transmitBuffer; + * spiTransaction.rxBuf = receiveBuffer; + * spiTransaction.arg = &mySemaphore; + * + * ... + * + * // Our callback function is defined here + * void spiCallbackFxn(SPI_Handle spi, SPI_Transaction *tran) + * { + * sem_t *semPtr = (sem_t *)(tran->arg); + * + * // Post the semaphore if our transaction was more than LIMIT + * if (tran->status == SPI_STATUS_SUCCESS && + * tran->count > LIMIT) { + * sem_post(semPtr); + * } + * } + * @endcode + * + * ## Canceling a transaction + * SPI_transferCancel() is used to cancel a SPI transaction when the driver is + * used in #SPI_MODE_CALLBACK mode. + * + * Calling this API while no transfer is in progress has no effect. If a + * transfer is in progress, it is canceled and the callback functions is + * called. + * The #SPI_Status status field in the #SPI_Transaction structure + * can be examined within the callback to determine if the transaction + * succeeded. + * + * Example: + * @code + * SPI_transferCancel(spi); + * @endcode + * + * @anchor ti_drivers_SPI_ControllerPeripheralModes + * ## Controller/Peripheral Modes + * This SPI driver functions in both SPI controller and SPI peripheral modes. + * Logically, the implementation is identical, however the difference between + * these two modes is driven by hardware. As a SPI controller, the peripheral is + * in control of the clock signal and therefore will commence communications + * to the SPI peripheral immediately. As a SPI peripheral, the SPI driver + * prepares the peripheral to transmit and receive data in a way such that the + * peripheral is ready to transfer data when the SPI controller initiates a + * transaction. + * + * ## Asserting on Chip Select + * The SPI protocol requires that the SPI controller asserts a SPI peripheral's + * chip select pin prior to starting a SPI transaction. While this protocol is + * generally followed, various types of SPI peripherals have different + * timing requirements as to when and for how long the chip select pin must + * remain asserted for a SPI transaction. + * + * Commonly, the SPI controller uses a hardware chip select to assert and + * de-assert the SPI peripheral for every data frame. In other cases, a SPI + * peripheral imposes the requirement of asserting the chip select over several SPI + * data frames. This is generally accomplished by using a regular, + * general-purpose output pin. Due to the complexity of such SPI peripheral + * implementations, this SPI driver has been designed to operate + * transparently to the SPI chip select. When the hardware chip + * select is used, the peripheral automatically selects/enables the + * peripheral. When using a software chip select, the application needs to + * handle the proper chip select and pin configuration. Chip select support + * will vary per SPI peripheral, refer to the device specific implementation + * documentation for details on chip select support. + * + * - _Hardware chip select_ No additional action by the application is + * required. + * - _Software chip select_ The application needs to handle the chip select + * assertion and de-assertion for the proper SPI peripheral. + * + *
+ * @anchor ti_drivers_SPI_Configuration + * # Configuration + * + * In order to use the SPI APIs, the application is required to provide + * device-specific SPI configuration in the ti_drivers_config.c file. + * The SPI driver interface defines a configuration data structure: + * + * @code + * typedef struct { + * SPI_FxnTable const *fxnTablePtr; + * void *object; + * void const *hwAttrs; + * } SPI_Config; + * @endcode + * + * The application must declare an array of #SPI_Config elements, named + * @p SPI_config[]. Each element of @p SPI_config[] must be populated with + * pointers to a device specific SPI driver implementation's function + * table, driver object, and hardware attributes. The hardware attributes + * define properties such as the SPI peripheral's base address, and + * the PICO and POCI pins. Each element in @p SPI_config[] corresponds to + * a SPI instance, and none of the elements should have NULL pointers. + * There is no correlation between the index and the + * peripheral designation (such as SPI0 or SPI1). For example, it is + * possible to use SPI_config[0] for SPI1. + * + * Because the SPI configuration is very device dependent, you will need to + * check the doxygen for the device specific SPI implementation. There you + * will find a description of the SPI hardware attributes. Please also + * refer to the ti_drivers_config.c file of any of your examples to see the + * SPI configuration. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_SPI__include +#define ti_drivers_SPI__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup SPI_CONTROL SPI_control command and status codes + * These SPI macros are reservations for SPI.h + * @{ + */ + +/*! + * Common SPI_control() command code reservation offset. + * SPI driver implementations should offset command codes with #SPI_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 + * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 + * @endcode + */ +#define SPI_CMD_RESERVED (32) + +/*! + * Common SPI_control status code reservation offset. + * SPI driver implementations should offset status codes with + * #SPI_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 + * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 + * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 + * @endcode + */ +#define SPI_STATUS_RESERVED (-32) + +/** + * @defgroup SPI_STATUS Status Codes + * SPI_STATUS_* macros are general status codes returned by SPI_control() + * @{ + * @ingroup SPI_CONTROL + */ + +/*! + * @brief Successful status code returned by SPI_control(). + * + * This value is returned from SPI_control() if the control code was executed + * successfully. + */ +#define SPI_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by SPI_control(). + * + * This value is returned from SPI_control() if the control code was not + * executed successfully. + */ +#define SPI_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by SPI_control() for undefined + * command codes. + * + * This value is returned from SPI_control() if the control code is not + * recognized by the driver implementation. + */ +#define SPI_STATUS_UNDEFINEDCMD (-2) +/** @}*/ + +/** + * @defgroup SPI_CMD Command Codes + * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI + * driver implementations support these command codes. + * @{ + * @ingroup SPI_CONTROL + */ + +/* Add SPI_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Wait forever define used to specify timeouts. + */ +#define SPI_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a SPI_open() call. + */ +typedef struct SPI_Config_ *SPI_Handle; + +/*! + * @brief Status codes that are set by the SPI driver. + */ +typedef enum +{ + SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ + SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ + SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ + SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ + SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted (only + applicable in return partial mode) */ + SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip + select is asserted */ + SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ +} SPI_Status; + +/*! + * @brief + * A #SPI_Transaction data structure is used with SPI_transfer(). It indicates + * how many #SPI_FrameFormat frames are sent and received from the buffers + * pointed to txBuf and rxBuf. + * The arg variable is an user-definable argument which gets passed to the + * #SPI_CallbackFxn when the SPI driver is in #SPI_MODE_CALLBACK. + */ +typedef struct +{ + /* User input (write-only) fields */ + size_t count; /*!< Number of frames for this transaction */ + void *txBuf; /*!< void * to a buffer with data to be transmitted */ + void *rxBuf; /*!< void * to a buffer to receive data */ + void *arg; /*!< Argument to be passed to the callback function */ + + /* User output (read-only) fields */ + SPI_Status status; /*!< #SPI_Status code set by SPI_transfer */ + + void *nextPtr; /*!< Field used internally by the driver and must + never be accessed by the application. */ +} SPI_Transaction; + +/*! + * @brief The definition of a callback function used by the SPI driver + * when used in #SPI_MODE_CALLBACK + * + * @param SPI_Handle A #SPI_Handle + * @param SPI_Transaction* Pointer to a #SPI_Transaction + */ +typedef void (*SPI_CallbackFxn)(SPI_Handle handle, SPI_Transaction *transaction); +/*! + * @brief + * Definitions for various SPI modes of operation. + */ +typedef enum +{ + SPI_CONTROLLER = 0, /*!< SPI in controller mode */ + SPI_PERIPHERAL = 1 /*!< SPI in peripheral mode */ +} SPI_Mode; + +/*! + * @brief + * Definitions for various SPI data frame formats. + */ +typedef enum +{ + SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ + SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ + SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ + SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ + SPI_TI = 4, /*!< TI mode (not supported on all + implementations) */ + SPI_MW = 5 /*!< Micro-wire mode (not supported on all + implementations) */ +} SPI_FrameFormat; + +/*! + * @brief + * + * SPI transfer mode determines the whether the SPI controller operates + * synchronously or asynchronously. In #SPI_MODE_BLOCKING mode SPI_transfer() + * blocks code execution until the SPI transaction has completed. In + * #SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead + * calls a #SPI_CallbackFxn callback function when the transaction has + * completed (successfully or not). + */ +typedef enum +{ + /*! + * SPI_transfer() blocks execution. This mode can only be used when called + * within a Task context + */ + SPI_MODE_BLOCKING, + /*! + * SPI_transfer() does not block code execution and will call a + * #SPI_CallbackFxn. This mode can be used in a Task, software or hardware + * interrupt context. + */ + SPI_MODE_CALLBACK +} SPI_TransferMode; + +/*! + * @brief SPI Parameters + * + * SPI Parameters are used to with the SPI_open() call. Default values for + * these parameters are set using SPI_Params_init(). + * + * @sa SPI_Params_init() + */ +typedef struct +{ + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + uint32_t transferTimeout; /*!< Transfer timeout in system + ticks */ + SPI_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + SPI_Mode mode; /*!< Controller or Peripheral mode */ + /*! @brief SPI bit rate in Hz + * + * Maximum bit rates supported by hardware: + * Device Family | Peripheral Max (MHz) | Controller Max (MHz) | + * ------------- | -------------------- | -------------------- | + * CC13X2/CC26X2 | 4 MHz | 4 MHz | + * CC13X4/CC26X4 | 8 MHz | 12 MHz | + * CC23XX/CC27XX | 12 MHz | 12 MHz | + * + * Please note that depending on the specific use case, the driver may not + * support the hardware's maximum bit rate. + */ + uint32_t bitRate; + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + void *custom; /*!< Custom argument used by driver + implementation */ +} SPI_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_close(). + */ +typedef void (*SPI_CloseFxn)(SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_control(). + */ +typedef int_fast16_t (*SPI_ControlFxn)(SPI_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_init(). + */ +typedef void (*SPI_InitFxn)(SPI_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_open(). + */ +typedef SPI_Handle (*SPI_OpenFxn)(SPI_Handle handle, SPI_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transfer(). + */ +typedef bool (*SPI_TransferFxn)(SPI_Handle handle, SPI_Transaction *transaction); + +/*! + * @brief A function pointer to a driver specific implementation of + * SPI_transferCancel(). + */ +typedef void (*SPI_TransferCancelFxn)(SPI_Handle handle); + +/*! + * @brief The definition of a SPI function table that contains the + * required set of functions to control a specific SPI driver + * implementation. + */ +typedef struct +{ + /*! Function to close the specified peripheral */ + SPI_CloseFxn closeFxn; + + /*! Function to implementation specific control function */ + SPI_ControlFxn controlFxn; + + /*! Function to initialize the given data object */ + SPI_InitFxn initFxn; + + /*! Function to open the specified peripheral */ + SPI_OpenFxn openFxn; + + /*! Function to initiate a SPI data transfer */ + SPI_TransferFxn transferFxn; + + /*! Function to cancel SPI data transfer */ + SPI_TransferCancelFxn transferCancelFxn; +} SPI_FxnTable; + +/*! + * @brief SPI Global configuration + * + * The #SPI_Config structure contains a set of pointers used to characterize + * the SPI driver implementation. + * + * This structure needs to be defined before calling SPI_init() and it must + * not be changed thereafter. + * + * @sa SPI_init() + */ +typedef struct SPI_Config_ +{ + /*! Pointer to a table of driver-specific implementations of SPI APIs */ + SPI_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} SPI_Config; + +/*! + * @brief Function to close a SPI peripheral specified by the SPI handle + * + * @pre SPI_open() has to be called first. + * + * @param handle A #SPI_Handle returned from SPI_open() + * + * @sa SPI_open() + */ +extern void SPI_close(SPI_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #SPI_Handle. + * + * Commands for SPI_control can originate from SPI.h or from implementation + * specific SPI*.h (SPICC26X2DMA.h, SPIMSP432DMA.h, etc.. ) files. + * While commands from SPI.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific SPI*.h files add + * unique driver capabilities but are not API portable across all SPI driver + * implementations. + * + * Commands supported by SPI.h follow a SPI_CMD_\ naming + * convention.
+ * Commands supported by SPI*.h follow a SPI*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref SPI_CMD "SPI_control command codes" for command codes. + * + * See @ref SPI_STATUS "SPI_control return status codes" for status codes. + * + * @pre SPI_open() has to be called first. + * + * @param handle A #SPI_Handle returned from SPI_open() + * + * @param cmd SPI.h or SPI*.h commands. + * + * @param controlArg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa SPI_open() + */ +extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg); + +/*! + * @brief This function initializes the SPI module. + * + * @pre The SPI_config[] array must exist and be persistent before this + * function can be called. This function must also be called before + * any other SPI driver APIs. This function call does not modify any + * peripheral registers. + */ +extern void SPI_init(void); + +/*! + * @brief This function opens a given SPI peripheral. + * + * @pre SPI controller has been initialized using SPI_init() + * + * @param index Index of config to use in the *SPI_config* array + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #SPI_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa SPI_init() + * @sa SPI_close() + */ +extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); + +/*! + * @brief Function to initialize the #SPI_Params struct to its defaults + * + * @param params An pointer to #SPI_Params structure for + * initialization + * + * Defaults values are: + * * SPI_Params.transferMode = #SPI_MODE_BLOCKING + * * SPI_Params.transferTimeout = #SPI_WAIT_FOREVER + * * SPI_Params.transferCallbackFxn = NULL + * * SPI_Params.mode = #SPI_CONTROLLER + * * SPI_Params.bitRate = 1000000 (Hz) + * * SPI_Params.dataSize = 8 (bits) + * * SPI_Params.frameFormat = #SPI_POL0_PHA0 + */ +extern void SPI_Params_init(SPI_Params *params); + +/*! + * @brief Function to perform SPI transactions + * + * If the SPI is in #SPI_CONTROLLER mode, it will immediately start the + * transaction. If the SPI is in #SPI_PERIPHERAL mode, it prepares the driver for + * a transaction with a SPI controller device. The device will then wait until + * the controller begins the transfer. + * + * In #SPI_MODE_BLOCKING, #SPI_transfer() will block task execution until the + * transaction has completed or a timeout has occurred. + * + * In #SPI_MODE_CALLBACK, %SPI_transfer() does not block task execution, but + * calls a #SPI_CallbackFxn once the transfer has finished. This makes + * %SPI_tranfer() safe to be used within a Task, software or hardware + * interrupt context. If queued transactions are supported SPI_Transfer may + * be called multiple times to queue multiple transactions. If the driver does + * not support this functionality additional calls will return false. Refer to + * device specific SPI driver documentation for support information. + * + * From calling #SPI_transfer() until transfer completion, the #SPI_Transaction + * structure must stay persistent and must not be altered by application code. + * It is also forbidden to modify the content of the #SPI_Transaction.txBuf + * during a transaction, even though the physical transfer might not have + * started yet. Doing this can result in data corruption. This is especially + * important for peripheral operations where SPI_transfer() might be called a long + * time before the actual data transfer begins. + * + * @param handle A #SPI_Handle + * + * @param transaction A pointer to a #SPI_Transaction. All of the fields within + * transaction except #SPI_Transaction.count and + * #SPI_Transaction.status are WO (write-only) unless + * otherwise noted in the driver implementations. If a + * transaction timeout has occurred, #SPI_Transaction.count + * will contain the number of frames that were transferred. + * Neither is it allowed to modify the transaction object nor + * the content of #SPI_Transaction.txBuf until the transfer + * has completed. + * + * @return @p true if started successfully; else @p false + * + * @sa #SPI_open + * @sa #SPI_transferCancel + */ +extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); + +/*! + * @brief Function to cancel SPI transactions + * + * In #SPI_MODE_BLOCKING, SPI_transferCancel has no effect. + * + * In #SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if + * if one is in progress. + * If a transaction was in progress, its callback function will be called + * in context from which this API is called from. The #SPI_CallbackFxn + * function can determine if the transaction was successful or not by reading + * the #SPI_Status status value in the #SPI_Transaction structure. + * + * @pre SPI_init(), SPI_open(), SPI_transfer() are called + * + * @param handle A #SPI_Handle + * + * @sa #SPI_open + * @sa #SPI_transfer + */ +extern void SPI_transferCancel(SPI_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_SPI__include */ diff --git a/simplelink_lpf2/source/ti/drivers/TRNG.c b/simplelink_lpf2/source/ti/drivers/TRNG.c new file mode 100644 index 00000000..65165064 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/TRNG.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== TRNG.c ======== + * + * This file contains default values for the TRNG_Params struct + * + */ + +#include +#include + +#include +#include +#include + +/* Extern globals */ +extern const TRNG_Config TRNG_config[]; +extern const uint_least8_t TRNG_count; + +const TRNG_Params TRNG_defaultParams = { + .returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING, + .cryptoKeyCallbackFxn = NULL, + .randomBytesCallbackFxn = NULL, + .timeout = SemaphoreP_WAIT_FOREVER, + .custom = NULL, +}; + +/* + * ======== TRNG_Params_init ======== + */ +void TRNG_Params_init(TRNG_Params *params) +{ + *params = TRNG_defaultParams; +} + +/* + * ======== TRNG_open ======== + */ +__attribute__((weak)) TRNG_Handle TRNG_open(uint_least8_t index, TRNG_Params *params) +{ + DebugP_assert(index <= TRNG_count); + + TRNG_Config *config = (TRNG_Config *)&TRNG_config[index]; + + return TRNG_construct(config, params); +} diff --git a/simplelink_lpf2/source/ti/drivers/TRNG.h b/simplelink_lpf2/source/ti/drivers/TRNG.h new file mode 100644 index 00000000..5e682d78 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/TRNG.h @@ -0,0 +1,768 @@ +/* + * Copyright (c) 2018-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file TRNG.h + * + * @brief TRNG driver header + * + * @anchor ti_drivers_TRNG_Overview + * # Overview # + * The True Random Number Generator (TRNG) module generates random data of variable + * lengths from a source of entropy. The output is suitable for applications + * requiring cryptographically random data such as keying material for + * private or symmetric keys. + * + * @anchor ti_drivers_TRNG_Usage + * # Usage # + * + * ## Before starting a TRNG operation # + * + * Before starting a TRNG operation, the application must do the following: + * - Call TRNG_init() to initialize the driver. + * - Call TRNG_Params_init() to initialize the TRNG_Params to default values. + * - Modify the TRNG_Params as desired. + * - Call TRNG_open() to open an instance of the driver. + * - Option 1: Use TRNG_generateKey() that writes random bytes to a CryptoKey.
+ * Initialize a blank CryptoKey. These opaque data structures are representations + * of keying material and its storage. Depending on how the keying material + * is stored (RAM or flash, key store), the CryptoKey must be + * initialized differently. The TRNG API can handle all types of CryptoKey. + * However, not all device-specific implementations support all types of CryptoKey. + * Devices without a key store will not support CryptoKeys with keying material + * stored in a key store for example. + * All devices support plaintext CryptoKeys. + * - Option 2: Use TRNG_getRandomBytes() that writes random bytes to a buffer.
+ * Allocate memory sufficient to hold the number of bytes of random data requested. + * + * ## TRNG operations # + * + * TRNG_generateKey() provides the most basic functionality. Use it to + * generate key-material of a specified size. An example use-case would be generating + * a symmetric key for AES encryption and / or authentication. If entropy data is needed + * for anything other than a key-material, use TRNG_getRandomBytes() that + * writes random bytes from the entropy source to a buffer/array. + * + * For CC27XX, the CRNG is the default configuration for the NRBG engine. + * Use TRNGLPF3HSM_switchNrbgMode() to switch between CRNG and TRNG configurations. + * + * For CC27XX devices only, the TRNG driver accepts two types of cryptoKey encoding: + * - CryptoKey_BLANK_PLAINTEXT + * - CryptoKey_BLANK_PLAINTEXT_HSM + * + * To generate an ECC private key, you should use rejection sampling to ensure + * that the keying material is in the interval [1, n - 1]. The ECDH public key + * generation APIs will reject private keys that are outside of this interval. + * This information may be used to generate keying material until a suitable + * key is generated. For most curves, it is improbable to generate a random number + * outside of this interval because n is a large number close to the maximum + * number that would fit in the k-byte keying material array. An example + * of how to do this is given below. + * + * ## TRNG Driver Limitation for CC27XX devices # + * + * For CC27XX devices, the underlying HSM engine for which the driver gets its source of + * entropy and random numbers from, you have the ability to configure the NRBG + * (Non-deterministic Random Bits Generator) engine which is part of the HSM in either + * CRNG or TRNG modes. Please refer to the device specific header file for a + * definition of both methods. + * + * In addition, the size of random data requested must be a 32-bit multiple. The + * appropriate error code, TRNG_STATUS_INVALID_INPUT_SIZE, will be returned to the user in + * the case this rule is not adhered to and the input size is not a multiple of 4 bytes, (32-bits). + * + * For example, in the case you are requesting a 521-bit (66 bytes) key for a + * SEC_P_521 related asymmetric key operations, the user must provide a buffer and a input size + * that rounds up to the next (32-bit) aligned byte (68 Bytes) and therefore, + * adheres to the above limitation. + * + * ## After the TRNG operation completes # + * + * After the TRNG operation completes, the application should either start another operation + * or close the driver by calling TRNG_close(). + * + * @anchor ti_drivers_TRNG_Synopsis + * ## Synopsis + * @anchor ti_drivers_TRNG_Synopsis_Code + * @code + * // Import TRNG Driver definitions + * #include + * #include + * + * // Define name for TRNG channel index + * #define TRNG_INSTANCE 0 + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_init(); + * + * handle = TRNG_open(TRNG_INSTANCE, NULL); + * + * CryptoKeyPlaintext_initBlankKey(&entropyKey, entropyBuffer, KEY_LENGTH_BYTES); + * + * result = TRNG_generateKey(handle, &entropyKey); + * + * TRNG_close(handle); + * + * @endcode + * + * @anchor ti_drivers_TRNG_Examples + * ## Examples + * + * ### TRNG force a reseed (for CC27XX devices only) # + * + * This example code for reseeding the DRBG engine is only applicable for CC27XX + * devices. Other devices and their corresponding SDKs do not have this API. + * + * @code + * + * #include + * #include + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * + * handle = TRNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * result = TRNG_getRandomBytes(handle, randomBytesArray, RANDOM_BYTES_SIZE); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * result = TRNGLPF3HSM_reseedDRBG(handle); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * result = TRNG_getRandomBytes(handle, randomBytesArray, RANDOM_BYTES_SIZE); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(handle); + * + * @endcode + * + * + * ### TRNG switch NRBG engine (for CC27XX devices only) # + * + * !!!!!!!!!!!!! WARNING !!!!!!!!!!!!! + * This example code is only applicable for CC27XX devices. + * Other devices and their corresponding SDKs do not have this API. + * + * @code + * + * #include + * #include + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * + * // The driver is initialized with CRNG configuration by default. + * handle = TRNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * result = TRNG_getRandomBytes(handle, randomBytesArray, RANDOM_BYTES_SIZE); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * result = TRNGLPF3HSM_switchNrbgMode(handle, TRNG_MODE_TRNG); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * result = TRNG_getRandomBytes(handle, randomBytesArray, RANDOM_BYTES_SIZE); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(handle); + * + * @endcode + * + * ### Generate symmetric encryption key # + * + * @code + * + * #include + * #include + * + * #define KEY_LENGTH_BYTES 16 + * + * TRNG_Handle handle; + * int_fast16_t result; + * + * CryptoKey entropyKey; + * uint8_t entropyBuffer[KEY_LENGTH_BYTES] = {0}; + * + * handle = TRNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * CryptoKeyPlaintext_initBlankKey(&entropyKey, entropyBuffer, KEY_LENGTH_BYTES); + * + * result = TRNG_generateKey(handle, &entropyKey); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(handle); + * + * @endcode + * + * ### Generate ECC private and public key using rejection sampling # + * + * @code + * + * #include + * #include + * #include + * #include + * + * TRNG_Handle trngHandle; + * ECDH_Handle ecdhHandle; + * + * CryptoKey privateKey; + * CryptoKey publicKey; + * + * int_fast16_t trngResult; + * int_fast16_t ecdhResult; + * + * uint8_t privateKeyingMaterial[32]; + * uint8_t publicKeyingMaterial[64]; + * + * ECDH_OperationGeneratePublicKey genPubKeyOperation; + * + * trngHandle = TRNG_open(0, NULL); + * if (!trngHandle) { + * while(1); + * } + * + * ecdhHandle = ECDH_open(0, NULL); + * if (!ecdhHandle) { + * while(1); + * } + * + * // Repeatedly generate random numbers until they are in the range [1, n - 1]. + * // Since the NIST-P256 order is so close to 2^256, the probability of needing + * // to generate more than one random number is incredibly low but not non-zero. + * do { + * + * CryptoKeyPlaintext_initBlankKey(&privateKey, privateKeyingMaterial, ECCParams_NISTP256.length); + * CryptoKeyPlaintext_initBlankKey(&publicKey, publicKeyingMaterial, 2 * ECCParams_NISTP256.length); + * + * trngResult = TRNG_generateKey(trngHandle, &privateKey); + * + * if (trngResult != TRNG_STATUS_SUCCESS) { + * while(1); + * } + * + * ECDH_OperationGeneratePublicKey_init(&genPubKeyOperation); + * genPubKeyOperation.curve = &ECCParams_NISTP256; + * genPubKeyOperation.myPrivateKey = &privateKey; + * genPubKeyOperation.myPublicKey = &publicKey; + * + * ecdhResult = ECDH_generatePublicKey(ecdhHandle, &genPubKeyOperation); + * + * } while(ecdhResult == ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER || ecdhResult == ECDH_STATUS_PRIVATE_KEY_ZERO); + * + * TRNG_close(trngHandle); + * ECDH_close(ecdhHandle); + * + * @endcode + * + * ### Generate random bytes to a user provided buffer # + * + * @code + * + * #include + * + * #define RANDOM_BYTES_SIZE 16 + * + * TRNG_Handle handle; + * int_fast16_t result; + * + * uint8_t randomBytesArray[RANDOM_BYTES_SIZE] = {0}; + * + * handle = TRNG_open(0, NULL); + * + * if (!handle) { + * // Handle error + * while(1); + * } + * + * result = TRNG_getRandomBytes(handle, randomBytesArray, RANDOM_BYTES_SIZE); + * + * if (result != TRNG_STATUS_SUCCESS) { + * // Handle error + * while(1); + * } + * + * TRNG_close(handle); + * + * @endcode + */ + +#ifndef ti_drivers_TRNG__include +#define ti_drivers_TRNG__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common TRNG status code reservation offset. + * TRNG driver implementations should offset status codes with + * TRNG_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TRNGXYZ_STATUS_ERROR0 TRNG_STATUS_RESERVED - 0 + * #define TRNGXYZ_STATUS_ERROR1 TRNG_STATUS_RESERVED - 1 + * #define TRNGXYZ_STATUS_ERROR2 TRNG_STATUS_RESERVED - 2 + * @endcode + */ +#define TRNG_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return TRNG_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define TRNG_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return TRNG_STATUS_ERROR if the function was not executed + * successfully. + */ +#define TRNG_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * TRNG driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define TRNG_STATUS_RESOURCE_UNAVAILABLE (-2) + +/*! + * @brief Operation failed due to invalid inputs. + * + * Functions return TRNG_STATUS_INVALID_INPUTS if input validation fails. + */ +#define TRNG_STATUS_INVALID_INPUTS (-3) + +/*! + * @brief The ongoing operation was canceled. + */ +#define TRNG_STATUS_CANCELED (-4) + +/*! + * @brief Importing generated key into KeyStore failed + * + * Functions return TRNG_STATUS_KEYSTORE_ERROR if the KeyStore_PSA_importKey() + * did not return KEYSTORE_PSA_STATUS_SUCCESS + */ +#define TRNG_STATUS_KEYSTORE_ERROR (-5) + +/*! + * @brief TRNG Global configuration + * + * The TRNG_Config structure contains a set of pointers used to characterize + * the TRNG driver implementation. + * + * This structure needs to be defined before calling TRNG_init() and it must + * not be changed thereafter. + * + * @sa TRNG_init() + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} TRNG_Config; + +/*! + * @brief A handle that is returned from a TRNG_open() call. + */ +typedef TRNG_Config *TRNG_Handle; + +/*! + * @brief The way in which TRNG function calls return after generating + * the requested entropy. + * + * Not all TRNG operations exhibit the specified return behavior. Functions that do not + * require significant computation and cannot offload that computation to a background thread + * behave like regular functions. Which functions exhibit the specified return behavior is not + * implementation dependent. Specifically, a software-backed implementation run on the same + * CPU as the application will emulate the return behavior while not actually offloading + * the computation to the background thread. + * + * TRNG functions exhibiting the specified return behavior have restrictions on the + * context from which they may be called. + * + * | | Task | Hwi | Swi | + * |------------------------------|-------|-------|-------| + * |TRNG_RETURN_BEHAVIOR_CALLBACK | X | X | X | + * |TRNG_RETURN_BEHAVIOR_BLOCKING | X | | | + * |TRNG_RETURN_BEHAVIOR_POLLING | X | X | X | + * + */ +typedef enum +{ + TRNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * TRNG operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + TRNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while TRNG operation goes + * on in the background. TRNG operation results are available + * after the function returns. + */ + TRNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while TRNG + * operation goes on in the background. TRNG operation results + * are available after the function returns. + */ +} TRNG_ReturnBehavior; + +/*! + * @brief The definition of a callback function used by the TRNG driver + * when TRNG_generateKey() is called with ::TRNG_RETURN_BEHAVIOR_CALLBACK + * + * @attention This will replace #TRNG_CallbackFxn, which is currently deprecated. + * + * @param handle Handle of the client that started the TRNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param entropy The CryptoKey that describes the location the generated + * entropy will be copied to. + */ +typedef void (*TRNG_CryptoKeyCallbackFxn)(TRNG_Handle handle, int_fast16_t returnValue, CryptoKey *entropy); + +/*! + * @brief The definition of a callback function used by the TRNG driver + * when TRNG_getRandomBytes() is called with ::TRNG_RETURN_BEHAVIOR_CALLBACK + * + * @param handle Handle of the client that started the TRNG operation. + * + * @param returnValue Return status code describing the outcome of the operation. + * + * @param randomBytes Pointer to an array that stores the random bytes + * output by this function. + * + * @param randomBytesSize The size of the random data required. + */ +typedef void (*TRNG_RandomBytesCallbackFxn)(TRNG_Handle handle, + int_fast16_t returnValue, + uint8_t *randomBytes, + size_t randomBytesSize); + +/*! + * @brief The definition of a callback function used by the TRNG driver + * when used in ::TRNG_RETURN_BEHAVIOR_CALLBACK + * + * @deprecated #TRNG_CallbackFxn will be replaced by #TRNG_CryptoKeyCallbackFxn + */ +typedef TRNG_CryptoKeyCallbackFxn TRNG_CallbackFxn; + +/*! + * @brief TRNG Parameters + * + * TRNG Parameters are used to with the TRNG_open() call. Default values for + * these parameters are set using TRNG_Params_init(). + * + * @attention When using the driver in #TRNG_RETURN_BEHAVIOR_CALLBACK, + * set the appropriate callback function field to point to a + * valid callback function and set the other one to NULL. + * + * @sa TRNG_Params_init() + */ +typedef struct +{ + TRNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + TRNG_CryptoKeyCallbackFxn cryptoKeyCallbackFxn; /*!< Callback function to use with TRNG_generateKey(). + * Set randomBytesCallbackFxn to NULL if using this. + */ + TRNG_RandomBytesCallbackFxn randomBytesCallbackFxn; /*!< Callback function to use with TRNG_getRandomBytes() + * Set cryptoKeyCallbackFxn to NULL if using this. + */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::TRNG_RETURN_BEHAVIOR_BLOCKING + */ + void *custom; /*!< Custom argument used by driver implementation */ +} TRNG_Params; + +/*! + * @brief Default TRNG_Params structure + * + * @sa TRNG_Params_init() + */ +extern const TRNG_Params TRNG_defaultParams; + +/*! + * @brief This function initializes the TRNG module. + * + * @pre The TRNG_config structure must exist and be persistent before this + * function can be called. This function must also be called before + * any other TRNG driver APIs. This function call does not modify any + * peripheral registers. + */ +void TRNG_init(void); + +/*! + * @brief Function to initialize the TRNG_Params struct to its defaults + * + * @param params An pointer to TRNG_Params structure for + * initialization + * + * Default values are:
+ * returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING
+ * cryptoKeyCallbackFxn = NULL
+ * randomBytesCallbackFxn = NULL
+ * timeout = SemaphoreP_WAIT_FOREVER
+ * custom = NULL
+ */ +void TRNG_Params_init(TRNG_Params *params); + +/*! + * @brief This function opens a given TRNG peripheral. + * + * @pre TRNG controller has been initialized using TRNG_init() + * + * @param index Logical peripheral number for the TRNG indexed into + * the TRNG_config table + * + * @param params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A TRNG_Handle on success or a NULL on an error or if it has been + * opened already. + * + * @sa TRNG_init() + * @sa TRNG_close() + */ +TRNG_Handle TRNG_open(uint_least8_t index, TRNG_Params *params); + +/*! + * @brief Function to close a TRNG peripheral specified by the TRNG handle + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open() + * + * @sa TRNG_open() + */ +void TRNG_close(TRNG_Handle handle); + +/*! + * @brief Generate random bytes and output to the given \c CryptoKey object. + * + * For devices other than CC27XX, Generates a random bitstream of the size defined in the \c entropy + * CryptoKey in the range 0 <= \c entropy buffer < 2 ^ (entropy length * 8). + * The entropy will be generated and stored according to the storage requirements + * defined in the CryptoKey. + * + * For CC27XX devices, Leverages the HSM to generate raw entropy. + * The requested amount cannot be zero and has to be between 1-256 Bytes. + * For larger amounts, the amount has to be a multiple of 256 bytes and up to 64KB. + * + * @deprecated This function has been replaced by a pair of new functions. + * See #TRNG_generateKey() and #TRNG_getRandomBytes(). + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open(). + * + * @param entropy Pointer to a \c CryptoKey object that should already be initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated entropy will be populated. + * + * @retval #TRNG_STATUS_SUCCESS The operation succeeded. + * @retval #TRNG_STATUS_ERROR The operation failed. + * @retval #TRNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #TRNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + */ +int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey *entropy); + +/*! + * @brief Generate random bytes and output to the given \c CryptoKey object. + * + * Generates a random bitstream of the size defined in the \c entropy + * CryptoKey in the range 0 <= \c entropy buffer < 2 ^ (entropy length * 8). + * The entropy will be generated and stored according to the storage requirements + * defined in the CryptoKey. + * + * @note This function replaces #TRNG_generateEntropy(). + * See #TRNG_getRandomBytes() to output random bytes to an array instead. + * + * @attention When called with ::TRNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #TRNG_CryptoKeyCallbackFxn. + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open(). + * + * @param entropy Pointer to a \c CryptoKey object that should already be initialized + * to hold a plaintext key, provided with the length and the address + * of the plaintext key-material where the generated entropy will be populated. + * + * @retval #TRNG_STATUS_SUCCESS The operation succeeded. + * @retval #TRNG_STATUS_ERROR The operation failed. + * @retval #TRNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #TRNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + */ +int_fast16_t TRNG_generateKey(TRNG_Handle handle, CryptoKey *entropy); + +/*! + * @brief Generate random bytes and output to the given array. + * + * Generates random bytes of size given by \c randomBytesSize and stores it + * in the array pointed at by \c randomBytes. The user shall be responsible for allocating + * \c randomBytesSize long memory starting at the address pointed at by \c randomBytes. + * + * @attention When called with ::TRNG_RETURN_BEHAVIOR_CALLBACK, provide a callback + * function of type #TRNG_RandomBytesCallbackFxn. + * + * @note See #TRNG_generateKey() to output random bytes to a \c CryptoKey instead. + * + * @pre TRNG_open() has to be called first. + * + * @param handle A TRNG handle returned from TRNG_open(). + * + * @param randomBytes Pointer to an array that stores the random bytes + * output by this function. + * For CC27XX devices, randomBytes must be 32-bit aligned. + * + * @param randomBytesSize The size of the random data required. + * For CC27XX devices, randomBytesSize must be 32-bit multiple. + * + * @retval #TRNG_STATUS_SUCCESS The operation succeeded. + * @retval #TRNG_STATUS_ERROR The operation failed. + * @retval #TRNG_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #TRNG_STATUS_INVALID_INPUTS Inputs provided are not valid. + */ +int_fast16_t TRNG_getRandomBytes(TRNG_Handle handle, void *randomBytes, size_t randomBytesSize); + +/** + * @brief Constructs a new TRNG object + * + * Unlike #TRNG_open(), #TRNG_construct() does not require the hwAttrs and + * object to be allocated in a #TRNG_Config array that is indexed into. + * Instead, the #TRNG_Config, hwAttrs, and object can be allocated at any + * location. This allows for relatively simple run-time allocation of temporary + * driver instances on the stack or the heap. + * The drawback is that this makes it more difficult to write device-agnostic + * code. If you use an ifdef with DeviceFamily, you can choose the correct + * object and hwAttrs to allocate. That compilation unit will be tied to the + * device it was compiled for at this point. To change devices, recompilation + * of the application with a different DeviceFamily setting is necessary. + * + * @param config #TRNG_Config describing the location of the object and hwAttrs. + * + * @param params #TRNG_Params to configure the driver instance. + * + * @return Returns a #TRNG_Handle on success or NULL on failure. + * + * @pre The object struct @c config points to must be zeroed out prior to + * calling this function. Otherwise, unexpected behavior may ensue. + */ +TRNG_Handle TRNG_construct(TRNG_Config *config, const TRNG_Params *params); + +/*! + * @brief Aborts an ongoing TRNG operation and clears internal buffers. + * + * Aborts an operation to generate random bytes/entropy. The operation will + * terminate as though an error occurred and the status code of the operation will be + * #TRNG_STATUS_CANCELED in this case. + * + * @param handle A #TRNG_Handle returned from #TRNG_open() + * + * @retval #TRNG_STATUS_SUCCESS The operation was canceled or there was no + * operation in progress to be canceled. + */ +int_fast16_t TRNG_cancelOperation(TRNG_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TRNG__include */ diff --git a/simplelink_lpf2/source/ti/drivers/Temperature.c b/simplelink_lpf2/source/ti/drivers/Temperature.c new file mode 100644 index 00000000..68c73162 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Temperature.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== Temperature.c ======== + * + */ + +#include +#include + +#include + +/* + * ======== Temperature_getThresholdHigh ======== + */ +int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject) +{ + return notifyObject->thresholdHigh; +} + +/* + * ======== Temperature_getThresholdLow ======== + */ +int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject) +{ + return notifyObject->thresholdLow; +} + +/* + * ======== Temperature_getThresholdRange ======== + */ +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, int16_t *thresholdHigh, int16_t *thresholdLow) +{ + *thresholdHigh = notifyObject->thresholdHigh; + *thresholdLow = notifyObject->thresholdLow; +} + +/* + * ======== Temperature_getClientArg ======== + */ +uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject) +{ + return notifyObject->clientArg; +} + +/* + * ======== Temperature_getNotifyFxn ======== + */ +Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject) +{ + return notifyObject->notifyFxn; +} diff --git a/simplelink_lpf2/source/ti/drivers/Temperature.h b/simplelink_lpf2/source/ti/drivers/Temperature.h new file mode 100644 index 00000000..2e60ac55 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Temperature.h @@ -0,0 +1,549 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file Temperature.h + * + * @brief Temperature driver + * + * @anchor ti_drivers_Temperature_Overview + * # Overview # + * The Temperature driver provides services related to measuring and reacting + * to the current temperature of the chip and changes to it. + * + * The two main services provided are: + * - Getting the current temperature + * - Providing notification callbacks when the temperature changes + * + * @anchor ti_drivers_Temperature_Usage + * # Usage # + * + * ## Initialisation # + * Unlike most drivers, there is only a single instance of the temperature + * driver that is always available once #Temperature_init() is called. + * #Temperature_init() should be called once before using other Temperature + * driver APIs. It is not called automatically via SysConfig generated code. + * Subsequent #Temperature_init() calls will have no effect. + * + * ## Getting the Current Temperature # + * The most basic function of the driver is to provide the current temperature + * and return it. It is encoded as a signed integer in degrees C. + * + * ## Notifications # + * The other major function of the Temperature driver is to notify the + * application when the temperature changes and crosses an application-defined + * threshold. + * + * There are three default usecases for this: + * - High threshold. + * The application will receive a notification callback when + * currentTemperature >= thresholdHigh. + * - Low threshold. + * The application will receive a notification callback when + * currentTemperature <= thresholdLow. + * - Range threshold. + * The application will receive a notification callback when + * currentTemperature >= thresholdHigh || currentTemperature <= + * thresholdLow. This setup addresses usecases + * where a notification is required when the temperature changes by a + * certain amount regardless of whether it is up or down. Adjusting + * clock offsets based on temperature is a good example of this. + * + * ### Registering Notifications + * There are three functions that register a notification for the application: + * - #Temperature_registerNotifyHigh() + * - #Temperature_registerNotifyLow() + * - #Temperature_registerNotifyRange() + * + * Multiple notifications may be registered. The different parts of the + * application and drivers that need to respond to a temperature change do not + * need to know of one another. + * Each notification must have its own #Temperature_NotifyObj and must be + * registered individually. + * + * ### Notification Callbacks + * Once the chip temperature crosses the smallest high threshold or largest + * low threshold amongst the registered notifications, the driver will + * iterate over the entire list of registered notification and check which + * ones have triggered. Notifications that have triggered are removed from + * the list of registered notifications and thus are no longer registered. + * Their callback function is then invoked. + * + * If an application wishes to re-register a notification that just triggered + * and was unregistered, it may register it again from within the notification + * callback or another context. + * + * It is possible to determine whether the high or low threshold triggered + * the notification callback as follows: + * - currentTemperature <= thresholdTemperature: Low threshold triggered + * - currentTemperature >= thresholdTemperature: High threshold triggered + * This information is only reasonably useful when registering a notification + * with both a high and low threshold using #Temperature_registerNotifyRange(). + * Even then, the expected basic usecase only cares about the current + * temperature and adding an offset to it when registering the notification + * again. + * + * ### Unregistering Notifications + * Registered notifications are unregistered in two ways: + * - Automatically when a notification triggers + * - By calling #Temperature_unregisterNotify() + * + * Unregistered notifications may be registered again at any time. + * + * # Measured vs True Temperature + * While the driver aims to supply and act on an accurate absolute temperature, + * there will be differences between the measured vs the true temperature due + * to inherent variances in the manufacturing process. The nature of these + * differences varies by device family. + * + * Examples of such differences: + * - A constant per-chip offset between the measured and the true + * temperature + * - An temperature dependent per-chip offset between the measured and the + * true temperature + * - A variance in the measured temperature when measuring multiple times + * at the same chip temperature + * + * It is strongly recommended to read the device-specific Temperature driver + * documentation for details of the temperature sensor characteristics and + * how they might affect choices of threshold values. + * + * @anchor ti_drivers_Temperature_Synopsis + * # Synopsis # + * @anchor ti_drivers_Temperature_Synopsis_Code + * @code + * #include + * + * #define WINDOW_DELTA 10 + * + * Temperature_init(); + * + * currentTemperature = Temperature_getTemperature(); + * + * result = Temperature_registerNotifyRange(¬ifyObject, + * currentTemperature + WINDOW_DELTA, + * currentTemperature - WINDOW_DELTA, + * myNotifyFxn, + * clientArg); + * @endcode + * + * @anchor ti_drivers_Temperature_Examples + * # Examples # + * + * ## Register a High Threshold Notification # + * + * @code + * + * // The notification will trigger when the temperature reaches 40 C + * #define THRESHOLD_CUTOFF 40 + * + * #include + * + * void thresholdNotifyFxn(int16_t currentTemperature, + * int16_t thresholdTemperature, + * uintptr_t clientArg, + * Temperature_NotifyObj *notifyObject) { + * // Post a semaphore, set a flag, or otherwise act upon the temperature + * // change. + * } + * + * ... + * + * // Initialize the Temperature driver and register a notification. + * + * Temperature_init(); + * + * int_fast16_t status = Temperature_registerNotifyHigh(notifyObject, + * THRESHOLD_CUTOFF, + * thresholdNotifyFxn, + * NULL); + * + * if (status != Temperature_STATUS_SUCCESS) { + * // Handle error + * } + * + * @endcode + * + * ## Register a Range Threshold Notification and Re-register in Callback # + * + * @code + * + * #define THRESHOLD_DELTA 5 + * + * #include + * + * + * void deltaNotificationFxn(int16_t currentTemperature, + * int16_t thresholdTemperature, + * uintptr_t clientArg, + * Temperature_NotifyObj *notifyObject) { + * int_fast16_t status; + * + * status = Temperature_registerNotifyRange(notifyObject, + * currentTemperature + THRESHOLD_DELTA, + * currentTemperature - THRESHOLD_DELTA, + * deltaNotificationFxn, + * NULL); + * + * if (status != Temperature_STATUS_SUCCESS) { + * while(1); + * } + * } + * + * ... + * + * // Initialize the Temperature driver and register a notification. + * + * Temperature_init(); + * + * int16_t currentTemperature = Temperature_getTemperature(); + * + * int_fast16_t status = Temperature_registerNotifyRange(notifyObject, + * currentTemperature + THRESHOLD_DELTA, + * currentTemperature - THRESHOLD_DELTA, + * deltaNotificationFxn, + * NULL); + * @endcode + */ + +#ifndef ti_drivers_Temperature__include +#define ti_drivers_Temperature__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common Temperature status code reservation offset. + * Temperature driver implementations should offset status codes with + * Temperature_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TemperatureXYZ_STATUS_ERROR0 Temperature_STATUS_RESERVED - 0 + * #define TemperatureXYZ_STATUS_ERROR1 Temperature_STATUS_RESERVED - 1 + * #define TemperatureXYZ_STATUS_ERROR2 Temperature_STATUS_RESERVED - 2 + * @endcode + */ +#define Temperature_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + * + * Functions return Temperature_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define Temperature_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return Temperature_STATUS_ERROR if the function was not executed + * successfully. + */ +#define Temperature_STATUS_ERROR (-1) + +/* @cond + * + * Type declaration for the notification object made separately from the + * struct definition because of the circular dependency between + * #Temperature_NotifyFxn() and #Temperature_NotifyObj. + */ +typedef struct Temperature_NotifyObj Temperature_NotifyObj; +/* @endcond */ + +/*! + * @brief Function prototype for a notification callback. + * + * @param [in] currentTemperature Current chip temperature + * + * @param [in] thresholdTemperature Temperature threshold that caused + * this notification callback. + * + * @param [in] clientArg Argument provided by the application + * during registration. + * + * @param [in/out] notifyObject The notification object that was + * registered previously. This pointer + * may be used to register the + * notification again with updated + * inputs from within the notification + * callback. + */ +typedef void (*Temperature_NotifyFxn)(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); + +/*! + * @brief Temperature notify object structure. + * + * This structure specification is for internal use. Notification clients must + * pre-allocate a notify object when registering for a notification; + * #Temperature_registerNotifyHigh(), #Temperature_registerNotifyLow(), + * or #Temperature_registerNotifyRange() will take care initializing the + * internal elements appropriately. + */ +struct Temperature_NotifyObj +{ + List_Elem link; /*!< For placing on the notify list */ + Temperature_NotifyFxn notifyFxn; /*!< Application callback function */ + int16_t thresholdHigh; /*!< High threshold in degrees C */ + int16_t thresholdLow; /*!< Low threshold in degrees C */ + uintptr_t clientArg; /*!< Application provided arg */ + bool isRegistered; /*!< Is the notification active */ +}; + +/*! + * @brief This function initializes the Temperature driver. + * + * This function initializes the internal state of the Temperature driver. + * It must be called before calling any other Temperature functions. Calling + * this function multiple times will only have an effect the first time. + * + * @note This function should be called manually before using the temperature API. + * It will not be called automatically via SysConfig generated code. + */ +void Temperature_init(void); + +/*! + * @brief Gets the current temperature in degrees C. + * + * @return Current temperature in degrees C + */ +int16_t Temperature_getTemperature(void); + +/*! + * @brief Registers a notification with a high threshold. + * + * This function registers a Temperature notification with a high threshold. + * Once the chip temperature rises above @c thresholdHigh, @c notifyFxn is + * called and the notification is automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh Threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature rises above + * @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #Temperature_STATUS_ERROR There was an error during registration. + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyHigh(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with a low threshold. + * + * This function registers a Temperature notification with a low threshold. + * Once the chip temperature falls below @c thresholdLow, @c notifyFxn is + * called and the notification is automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdLow Threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature falls below + * @c thresholdLow. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered. + * @retval #Temperature_STATUS_ERROR There was an error during registration. + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyLow(Temperature_NotifyObj *notifyObject, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Registers a notification with both a high and low threshold. + * + * This function registers a Temperature notification with a high and low + * threshold. Once the chip temperature rises above @c thresholdHigh or + * falls below @c thresholdLow, @c notifyFxn is called and the notification is + * automatically unregistered. + * + * @param notifyObject Structure to be initialized. After returning, + * it will contain the data necessary to issue a + * notification callback. The memory of the + * structure must persist while the notification + * is registered. + * + * @param [in] thresholdHigh High threshold temperature in degrees C + * + * @param [in] thresholdLow Low threshold temperature in degrees C + * + * @param [in] notifyFxn Callback function that is called once the + * chip temperature falls below + * @c thresholdLow, or rises above + * @c thresholdHigh. + * + * @param [in] clientArg Application-specified argument + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * registered + * @retval #Temperature_STATUS_ERROR There was an error during registration + * + * @pre Temperature_init() called + */ +int_fast16_t Temperature_registerNotifyRange(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg); + +/*! + * @brief Unregisters a currently registered notification. + * + * This function unregisters a currently registered notification. It should not + * be called on a @c notifyObject that is not currently registered. + * + * @param notifyObject Notification to unregister. + * + * @retval #Temperature_STATUS_SUCCESS The notification was successfully + * unregistered. + * @retval #Temperature_STATUS_ERROR There was an error during + * unregistration. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +int_fast16_t Temperature_unregisterNotify(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the high threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyLow(). The high threshold value returned in + * that case will be a device-specific invalid temperature. + * + * @param notifyObject Notification to get the high threshold of. + * + * @return High threshold in degrees C. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * or #Temperature_registerNotifyRange() + */ +int16_t Temperature_getThresholdHigh(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the low threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyHigh(). The low threshold value returned in + * that case will be a device-specific invalid temperature. + * + * @param notifyObject Notification to get the low threshold of. + * + * @return Low threshold in degrees C. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyLow(), + * or #Temperature_registerNotifyRange() + */ +int16_t Temperature_getThresholdLow(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the high and low threshold of a notification. + * + * This function should not be called on a @c notifyObject registered with + * #Temperature_registerNotifyLow() or #Temperature_registerNotifyHigh(). + * The unconfigured threshold value returned in that case will be a + * device-specific invalid temperature. + * + * @param notifyObject Notification to get the high and low threshold of. + * + * @param [out] thresholdHigh High threshold value in degrees C written back + * by this function. + * + * @param [out] thresholdLow Low threshold value in degrees C written back + * by this function. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyRange() + */ +void Temperature_getThresholdRange(Temperature_NotifyObj *notifyObject, int16_t *thresholdHigh, int16_t *thresholdLow); + +/*! + * @brief Get the application-provided clientArg of a notification. + * + * @param notifyObject Notification to get the clientArg of. + * + * @return The clientArg provided during registration. + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +uintptr_t Temperature_getClientArg(Temperature_NotifyObj *notifyObject); + +/*! + * @brief Get the notifyFxn provided during registration. + * + * @param notifyObject Notification to get the notifyFxn of. + * + * @return The notifyFxn provided during registration + * + * @pre Register @c notifyObject with #Temperature_registerNotifyHigh(), + * #Temperature_registerNotifyLow(), or #Temperature_registerNotifyRange() + */ +Temperature_NotifyFxn Temperature_getNotifyFxn(Temperature_NotifyObj *notifyObject); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Temperature__include */ diff --git a/simplelink_lpf2/source/ti/drivers/Timer.c b/simplelink_lpf2/source/ti/drivers/Timer.c new file mode 100644 index 00000000..ff374417 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Timer.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#include +#include +#include + +#include +#include + +/* Default Parameters */ +static const Timer_Params defaultParams = {.timerMode = Timer_ONESHOT_BLOCKING, + .periodUnits = Timer_PERIOD_COUNTS, + .timerCallback = NULL, + .period = (uint16_t)~0}; + +/* + * ======== Timer_init ======== + */ +void Timer_init(void) +{ + /* Do nothing */ +} + +/* + * ======== Timer_Params_init ======== + */ +void Timer_Params_init(Timer_Params *params) +{ + *params = defaultParams; +} + +/* + * ======== Timer_setPeriod ======== + */ +int32_t Timer_setPeriod(Timer_Handle handle, Timer_PeriodUnits periodUnits, uint32_t period) +{ + Timer_Object *object = handle->object; + ClockP_FreqHz clockFreq; + + ClockP_getCpuFreq(&clockFreq); + + if (periodUnits == Timer_PERIOD_US) + { + /* Checks if the calculated period will fit in 32-bits */ + if (period >= ((uint32_t)~0) / (clockFreq.lo / 1000000)) + { + return (Timer_STATUS_ERROR); + } + period = period * (clockFreq.lo / 1000000); + } + else if (periodUnits == Timer_PERIOD_HZ) + { + /* If period > clockFreq */ + if ((period = clockFreq.lo / period) == 0) + { + return (Timer_STATUS_ERROR); + } + } + + /* If using a half timer */ + if (!TimerSupport_timerFullWidth(handle)) + { + if (period > 0xFFFF) + { + /* 24-bit resolution for the half timer */ + if (period >= (1 << 24)) + { + return (Timer_STATUS_ERROR); + } + } + } + + object->period = period; + + TimerSupport_timerLoad(handle); + + return (Timer_STATUS_SUCCESS); +} + +/* + * ======== Timer_start ======== + */ +int32_t Timer_start(Timer_Handle handle) +{ + Timer_Object *object = handle->object; + uintptr_t key; + + /* Check if timer is already running */ + key = HwiP_disable(); + + if (object->isRunning) + { + HwiP_restore(key); + return (Timer_STATUS_ERROR); + } + + object->isRunning = true; + + TimerSupport_timerEnable(handle); + + HwiP_restore(key); + + if (object->mode == Timer_ONESHOT_BLOCKING) + { + /* Pend forever, ~0 */ + SemaphoreP_pend(object->semHandle, SemaphoreP_WAIT_FOREVER); + } + + return (Timer_STATUS_SUCCESS); +} + +/* + * ======== Timer_stop ======== + */ +void Timer_stop(Timer_Handle handle) +{ + Timer_Object *object = handle->object; + uintptr_t key; + bool flag = false; + + key = HwiP_disable(); + + if (object->isRunning) + { + object->isRunning = false; + /* Post the Semaphore when called from the Hwi */ + if (object->mode == Timer_ONESHOT_BLOCKING) + { + flag = true; + } + TimerSupport_timerDisable(handle); + } + + HwiP_restore(key); + + if (flag) + { + SemaphoreP_post(object->semHandle); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/Timer.h b/simplelink_lpf2/source/ti/drivers/Timer.h new file mode 100644 index 00000000..4fb9c15a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Timer.h @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Timer.h + * @brief Timer driver + * + * @anchor ti_drivers_Timer_Overview + * # Overview + * The timer driver allows you to measure elapsed time with simple and + * portable APIs.This driver does not have PWM or capture functionalities. + * These functionalities are addressed in both the capture and PWM driver. + * + * The timer driver also handles the general purpose timer resource allocation. + * For each driver that requires use of a general purpose timer, it calls + * Timer_open() to occupy the specified timer, and calls Timer_close() to + * release the occupied timer resource. + * + * @anchor ti_drivers_Timer_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_Timer_Synopsis + * "usage summary" and a set of @ref ti_drivers_Timer_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_Timer_Synopsis + * ## Synopsis + * @anchor ti_drivers_Timer_Synopsis_Code + * @code + * // Import Timer Driver definitions + * #include + * + * Timer_Handle handle; + * Timer_Params params; + * + * Timer_Params_init(¶ms); + * params.periodUnits = Timer_PERIOD_HZ; + * params.period = 1000; + * params.timerMode = Timer_CONTINUOUS_CALLBACK; + * params.timerCallback = UserCallbackFunction; + * + * handle = Timer_open(CONFIG_TIMER0, ¶ms); + * + * @code + * // Import Timer Driver definitions + * #include + * + * Timer_Handle handle; + * Timer_Params params; + * + * // Initialize Timer parameters + * Timer_Params_init(¶ms); + * params.periodUnits = Timer_PERIOD_HZ; + * params.period = 1000; + * params.timerMode = Timer_CONTINUOUS_CALLBACK; + * params.timerCallback = UserCallbackFunction; + * + * // Open Timer instance + * handle = Timer_open(CONFIG_TIMER0, ¶ms); + * + * sleep(10000); + * + * Timer_stop(handle); + * @endcode + * + *
+ * @anchor ti_drivers_Timer_Examples + * # Examples + * + * @li @ref ti_drivers_Timer_Examples_open "Opening a Timer Instance" + * @li @ref ti_drivers_Timer_Examples_mode "Configuring Timer mode and period" + * + * @anchor ti_drivers_Timer_Examples_open + * ## Opening a Timer instance + * + * @code + * Timer_Handle handle; + * Timer_Params params; + * + * Timer_Params_init(¶ms); + * handle = Timer_open(CONFIG_TIMER0, ¶ms); + * + * if (handle == NULL) { + * // Timer_open() failed + * while (1); + * } + @endcode + * + * @anchor ti_drivers_Timer_Examples_mode + * ##Configuring Timer mode and period + * + * The following example code opens a timer in continuous callback mode. The + * period is set to 1000 Hz. + * + * @code + * Timer_Handle handle; + * Timer_Params params; + * + * Timer_Params_init(¶ms); + * params.periodUnits = Timer_PERIOD_HZ; + * params.period = 1000; + * params.timerMode = Timer_CONTINUOUS_CALLBACK; + * params.timerCallback = UserCallbackFunction; + * + * handle = Timer_open(CONFIG_TIMER0, ¶ms); + * + * if (handle == NULL) { + * // Timer_open() failed + * while (1); + * } + * + * status = Timer_start(handle); + * + * if (status == Timer_STATUS_ERROR) { + * //Timer_start() failed + * while (1); + * } + * + * sleep(10000); + * + * Timer_stop(handle); + * @endcode + * + * ### Initializing the Timer Driver # + * + * Timer_init() must be called before any other timer APIs. This function + * calls the device implementation's timer initialization function, for each + * element of Timer_config[]. + * + *
+ * @anchor ti_drivers_Timer_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+******************************************************************************* + */ + +#ifndef ti_drivers_Timer__include +#define ti_drivers_Timer__include + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * Common Timer_control command code reservation offset. + * Timer driver implementations should offset command codes with Timer_CMD_RESERVED + * growing positively + * + * Example implementation specific command codes: + * @code + * #define TimerXYZ_CMD_COMMAND0 Timer_CMD_RESERVED + 0 + * #define TimerXYZ_CMD_COMMAND1 Timer_CMD_RESERVED + 1 + * @endcode + */ +#define Timer_CMD_RESERVED (32) + +/*! + * Common Timer_control status code reservation offset. + * Timer driver implementations should offset status codes with + * Timer_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define TimerXYZ_STATUS_ERROR0 Timer_STATUS_RESERVED - 0 + * #define TimerXYZ_STATUS_ERROR1 Timer_STATUS_RESERVED - 1 + * @endcode + */ +#define Timer_STATUS_RESERVED (-32) + +/*! + * @brief Successful status code. + */ +#define Timer_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + */ +#define Timer_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Timer_control() for undefined + * command codes. + * + * Timer_control() returns Timer_STATUS_UNDEFINEDCMD if the control code is not + * recognized by the driver implementation. + */ +#define Timer_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief A handle that is returned from a Timer_open() call. + */ +typedef struct Timer_Config_ *Timer_Handle; + +/*! + * @brief Timer mode settings + * + * This enum defines the timer modes that may be specified in #Timer_Params. + * + * The timer driver supports four modes of operation which may be specified in + * the Timer_Params. The device specific implementation may configure the timer + * peripheral as an up or down counter. In any case, Timer_getCount() will + * return a value characteristic of an up counter. + */ +typedef enum +{ + Timer_ONESHOT_CALLBACK, /*!< Is a non-blocking call. After Timer_start() + is called, the calling thread will continue + execution. When the timer interrupt is + triggered, the specified callback function + will be called. The timer will not generate + another interrupt unless Timer_start() is + called again. Calling Timer_stop() or + Timer_close() after Timer_start() but, + before the timer interrupt, will prevent + the specified callback from ever being invoked. + */ + Timer_ONESHOT_BLOCKING, /*!< Is a blocking call. A semaphore is used to + block the calling thread's execution until + the timer generates an interrupt. If + Timer_stop() is called, the calling thread + will become unblocked immediately. The + behavior of the timer in this mode is similar + to a sleep function. + */ + Timer_CONTINUOUS_CALLBACK, /*!< Is a non-blocking call. After Timer_start() + is called, the calling thread will continue + execution. When the timer interrupt is + triggered, the specified callback function + will be called. The timer is automatically + restarted and will continue to periodically + generate interrupts until Timer_stop() is + called. + */ + Timer_FREE_RUNNING /*!< Is a non-blocking call. After Timer_start() + is called, the calling thread will continue + execution. The timer will not generate an + interrupt in this mode. The timer hardware + will run until Timer_stop() is called. + */ +} Timer_Mode; + +/*! + * @brief Timer period unit enum + * + * This enum defines the units that may be specified for the period + * in #Timer_Params. This unit has no effect with Timer_getCounts. + */ +typedef enum +{ + Timer_PERIOD_US, /*!< Period specified in micro seconds. */ + Timer_PERIOD_HZ, /*!< Period specified in hertz; interrupts per + second. */ + Timer_PERIOD_COUNTS /*!< Period specified in ticks or counts. Varies + from board to board. */ +} Timer_PeriodUnits; + +/*! + * @brief Timer callback function + * + * User definable callback function prototype. The timer driver will call the + * defined function and pass in the timer driver's handle and the status code. + * + * @param[in] handle Timer_Handle + * @param[in] status Status of timer interrupt + */ +typedef void (*Timer_CallBackFxn)(Timer_Handle handle, int_fast16_t status); + +/*! + * @brief Timer Parameters + * + * Timer parameters are used with the Timer_open() call. Default values for + * these parameters are set using Timer_Params_init(). + * + */ +typedef struct +{ + /*! Mode to be used by the timer driver. */ + Timer_Mode timerMode; + + /*! Units used to specify the period. */ + Timer_PeriodUnits periodUnits; + + /*! Callback function called when timerMode is Timer_ONESHOT_CALLBACK or + Timer_CONTINUOUS_CALLBACK. */ + Timer_CallBackFxn timerCallback; + + /*! Period in units of periodUnits. */ + uint32_t period; +} Timer_Params; + +/*! @cond NODOC */ +#define TIMER_BASE_OBJECT \ + /* Timer control variables */ \ + Timer_Mode mode; /* Blocking or Callback mode */ \ + Timer_CallBackFxn callBack; /* Callback function pointer */ \ + Power_NotifyObj notifyObj; /* Ptr to current I2C transaction */ \ + uint32_t timer; \ + uint32_t period; \ + uint32_t prescaler; \ + \ + /* Timer RTOS objects */ \ + HwiP_Handle hwiHandle; /* Hwi object handle */ \ + SemaphoreP_Struct semStruct; /* Grants exclusive access to I2C */ \ + SemaphoreP_Handle semHandle; /* Signal I2C transfer complete */ \ + \ + bool isRunning; /* Flag to show module is open */ \ +/*! @endcond */ + +/*! + * @cond NODOC + * Timer Object. Applications must not access any member variables of + * this structure! + */ +typedef struct +{ + TIMER_BASE_OBJECT +} Timer_Object; +/*! @endcond */ + +/*! @cond NODOC */ +#define TIMER_BASE_HWATTRS \ + /*! Timer Peripheral's base address */ \ + uint32_t baseAddress; \ + /*! Timer Peripheral's interrupt vector */ \ + uint32_t intNum; \ + /*! Timer Peripheral's interrupt priority*/ \ + uint32_t intPriority; +/*! @endcond */ + +/*! + * @cond NODOC + * Timer HWAttrs. + */ +typedef struct +{ + TIMER_BASE_HWATTRS +} Timer_HWAttrs; +/*! @endcond */ + +/*! + * @brief Timer Global configuration + * + * The Timer_Config structure contains a set of pointers used to characterize + * the timer driver implementation. + * + * This structure needs to be defined before calling Timer_init() and it must + * not be changed thereafter. + * + * @sa Timer_init() + */ +typedef struct Timer_Config_ +{ + /*! Pointer to a driver-specific data object. */ + void *object; + + /*! Pointer to a driver-specific hardware attributes structure. */ + void const *hwAttrs; +} Timer_Config; + +/*! + * @cond NODOC + * Timer Config. + */ +extern const Timer_Config Timer_config[]; +/*! @endcond */ + +/*! + * @brief Function to close a timer. The corresponding timer + * becomes an available timer resource. + * + * @pre Timer_open() has been called. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_open() + */ +extern void Timer_close(Timer_Handle handle); + +/*! + * @brief Function performs device-specific features on a given + * timer. + * + * @pre Timer_open() has been called. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @param[in] cmd A command value defined by the driver-specific + * implementation. + * + * @param[in] arg A pointer to an optional R/W (read/write) argument that + * is accompanied with cmd. + * + * @retval #Timer_STATUS_SUCCESS The control call was successful. + * @retval #Timer_STATUS_ERROR The control call failed + * + * @sa Timer_open() + */ +extern int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Function to get the current count of a timer. The value returned + * represents timer counts. The value returned is always + * characteristic of an up counter. This is true even if the timer + * peripheral is counting down. Some device-specific implementations + * may employ a prescaler in addition to this timer count. + * + * @pre Timer_open() has been called. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_open() + * + * @return The current count of the timer in timer ticks. + * + */ +extern uint32_t Timer_getCount(Timer_Handle handle); + +/*! + * @brief Function to initialize a timer. This function will go through + * all available hardware resources and mark them as "available". + * + * @pre The Timer_config structure must exist before this function is + * called, and must be persistent. This function must be called + * before any other timer driver APIs. + * + * @sa Timer_open() + */ +extern void Timer_init(void); + +/*! + * @brief Function to initialize a given timer peripheral specified by the + * index argument. The Timer_Params specifies the mode the timer will + * operate in. The accuracy of the desired period is limited by the + * the clock. For example, a 100 MHz clock will have a tick resolution + * of 10 nanoseconds. This function takes care of timer resource + * allocation. If the particular timer is available to use, the timer + * driver acquires it and returns a Timer_Handle. + * + * @pre Timer_init() has been called. + * + * @param[in] index Logical peripheral number for the timer indexed into + * the Timer_config table. + * + * @param[in] params Pointer to an parameter block, if NULL it will use + * default values. + * + * @return A #Timer_Handle upon success, or NULL. NULL is returned if the + * desired period results in overflow or saturation of the timer, or + * if the timer resource is already in use. + * + * @sa Timer_init() + * @sa Timer_close() + */ +extern Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params); + +/*! + * @brief Function to set the period of a timer after it has been opened. + * + * @pre Timer_open() has been called. It is also recommended Timer_stop() has + * been called on an already running timer before calling this API as the + period is updated asynchronously. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @param[in] periodUnits #Timer_PeriodUnits of the desired period value. + * + * @param[in] period Period value to set. + * + * @retval #Timer_STATUS_SUCCESS The setPeriod call was successful. + * @retval #Timer_STATUS_ERROR The setPeriod call failed. + * + * @sa Timer_open() + * @sa Timer_stop() + */ +extern int32_t Timer_setPeriod(Timer_Handle handle, Timer_PeriodUnits periodUnits, uint32_t period); + +/*! + * @brief Function to initialize the Timer_Params struct to its defaults. + * + * @param[in] params A pointer to Timer_Params structure for + * initialization. + * + * Defaults values are: + * timerMode = Timer_ONESHOT_BLOCKING + * periodUnit = Timer_PERIOD_COUNTS + * timerCallback = NULL + * period = (uint16_t) ~0 + */ +extern void Timer_Params_init(Timer_Params *params); + +/*! + * @brief Function to start a timer. + * + * @pre Timer_open() has been called. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @retval #Timer_STATUS_SUCCESS The start call was successful. + * @retval #Timer_STATUS_ERROR The start call failed + * + * @sa Timer_stop() + */ +extern int32_t Timer_start(Timer_Handle handle); + +/*! + * @brief Function to stop a timer. If the timer is already stopped this + * function has no effect. + * + * @pre Timer_open() has been called. + * + * @param[in] handle A Timer_Handle returned from Timer_open(). + * + * @sa Timer_start() + */ +extern void Timer_stop(Timer_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Timer__include */ diff --git a/simplelink_lpf2/source/ti/drivers/UART2.c b/simplelink_lpf2/source/ti/drivers/UART2.c new file mode 100644 index 00000000..8417d843 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/UART2.c @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== UART2.c ======== + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern const UART2_Config UART2_config[]; +extern const uint_least8_t UART2_count; + +/* Macro for weak definition of the UART2 Log module */ +Log_MODULE_DEFINE_WEAK(LogModule_UART2, {0}); + +/* Default UART parameters structure */ +const UART2_Params UART2_defaultParams = { + UART2_Mode_BLOCKING, /* readMode */ + UART2_Mode_BLOCKING, /* writeMode */ + NULL, /* readCallback */ + NULL, /* writeCallback */ + NULL, /* eventCallback */ + 0, /* eventMask */ + UART2_ReadReturnMode_PARTIAL, /* readReturnMode */ + 115200, /* baudRate */ + UART2_DataLen_8, /* dataLength */ + UART2_StopBits_1, /* stopBits */ + UART2_Parity_NONE, /* parityType */ + NULL /* userArg */ +}; + +/* Functions used internally */ +int_fast16_t UART2_writeTimeoutBlocking(UART2_Handle handle, + const void *buffer, + size_t size, + size_t *bytesWritten, + uint32_t timeout); + +int_fast16_t UART2_writeTimeoutNonblocking(UART2_Handle handle, + const void *buffer, + size_t size, + size_t *bytesWritten, + uint32_t timeout); + +static int_fast16_t UART2_writePolling(UART2_Handle handle, const void *buffer, size_t size, size_t *bytesWritten); + +/* + * ======== UART2_getRxCount ======== + */ +size_t __attribute__((weak)) UART2_getRxCount(UART2_Handle handle) +{ + UART2_Object *object = handle->object; + uintptr_t key; + int count = 0; + + key = HwiP_disable(); + if (object->state.opened) + { + /* Stop and start the DMA transaction. This will update the count in the ring buffer */ + UART2Support_dmaStopRx(handle); + UART2Support_dmaStartRx(handle); + count = RingBuf_getCount(&object->rxBuffer); + } + HwiP_restore(key); + + return count; +} + +/* + * ======== UART2_Params_init ======== + */ +void UART2_Params_init(UART2_Params *params) +{ + *params = UART2_defaultParams; +} + +/* + * ======== UART2_read ======== + */ +int_fast16_t __attribute__((weak)) UART2_read(UART2_Handle handle, void *buffer, size_t size, size_t *bytesRead) +{ + UART2_Object *object = handle->object; + int status = UART2_STATUS_SUCCESS; + + Log_printf(LogModule_UART2, + Log_INFO, + "UART2_read: Start reading %d byte(s) to buffer address 0x%x", + size, + buffer); + + if ((object->state.readMode == UART2_Mode_BLOCKING) && (object->state.readReturnMode == UART2_ReadReturnMode_FULL)) + { + status = UART2_readFull(handle, buffer, size, bytesRead); + } + else + { + status = UART2_readTimeout(handle, buffer, size, bytesRead, UART2_WAIT_FOREVER); + } + + return status; +} + +/* + * ======== UART2_readFull ======== + */ +int_fast16_t __attribute__((weak)) UART2_readFull(UART2_Handle handle, void *buffer, size_t size, size_t *bytesRead) +{ + unsigned char *buf = (unsigned char *)buffer; + int status = UART2_STATUS_SUCCESS; + size_t totalRead = 0; + size_t sizeTemp = size; + size_t nRead; + + while (size > 0) + { + status = UART2_readTimeout(handle, buf + totalRead, size - totalRead, &nRead, UART2_WAIT_FOREVER); + + totalRead += nRead; + size -= nRead; + + if (status != UART2_STATUS_SUCCESS) + { + break; + } + } + + if (bytesRead != NULL) + { + *bytesRead = totalRead; + } + + if (sizeTemp == 0) + { + /* Reading 0 bytes is not valid */ + status = UART2_STATUS_EINVALID; + } + + return status; +} + +/* + * ======== UART2_readTimeout ======== + */ +int_fast16_t UART2_readTimeout(UART2_Handle handle, void *buffer, size_t size, size_t *bytesRead, uint32_t timeout) +{ + UART2_Object *object = handle->object; + int status = UART2_STATUS_SUCCESS; + uintptr_t key; /* Key returned by HwiP_disable, used to restore interrupts */ + int available; /* Number of available bytes in ring buffer */ + unsigned char *srcAddr; /* Address in ring buffer where data can be read from */ + void *readBufCopy; /* Temporarily copy readBuf before clearing it, to pass copy to callback */ + + if (bytesRead != NULL) + { + *bytesRead = 0; + } + + key = HwiP_disable(); + + if (!object->state.opened) + { + /* Instance not yet opened */ + HwiP_restore(key); + return UART2_STATUS_ENOTOPEN; + } + + if (object->readInUse) + { + /* Another read is ongoing */ + HwiP_restore(key); + return UART2_STATUS_EINUSE; + } + + if (size == 0) + { + /* Reading 0 bytes is not valid */ + HwiP_restore(key); + return UART2_STATUS_EINVALID; + } + + /* The driver is now free to start a read transaction. Even though there is no active "user read" ongoing, + * the ring buffer could be receiving data in the background. Stop potentially ongoing transfers before proceeding. + */ + UART2Support_dmaStopRx(handle); + + /* Update driver state variables */ + object->readInUse = true; + object->readBuf = (unsigned char *)buffer; + object->readSize = size; + object->readCount = size; /* Number remaining to be read */ + object->bytesRead = 0; /* Number of bytes read */ + object->rxStatus = 0; /* Clear receive errors */ + object->state.rxCancelled = false; + object->state.readTimedOut = false; + + /* Enable RX. If RX has already been enabled, this function call does nothing */ + UART2_rxEnable(handle); + + /* Start RX. Depending on the number of bytes in the ring buffer, this will either start a DMA transaction + * straight into the user buffer, or continue reading into the ring buffer (if it contains enough data for this + * read) + */ + UART2Support_dmaStartRx(handle); + + /* Read data from the ring buffer */ + do + { + available = RingBuf_getPointer(&object->rxBuffer, &srcAddr); + + if (available > object->readCount) + { + available = object->readCount; + } + memcpy((unsigned char *)buffer + object->bytesRead, srcAddr, available); + + Log_printf(LogModule_UART2, Log_VERBOSE, + "UART2_readTimeout: Read %d byte(s) from the ring buffer.", + available); + RingBuf_getConsume(&object->rxBuffer, available); + + object->readCount -= available; + object->bytesRead += available; + + } while ((available > 0) && (object->readCount > 0)); + + /* If we are in nonblocking mode, the read operation is done. Update state variables */ + if (object->state.readMode == UART2_Mode_NONBLOCKING) + { + object->readCount = 0; + object->readBuf = NULL; + object->readInUse = false; + } + /* If there are no more bytes to read, the read operation is complete */ + if (object->readCount == 0) + { + /* Update driver state variables */ + object->readInUse = false; + /* Set readBuf to NULL, but first make a copy to pass to the callback. We cannot set it to NULL after + * the callback in case another read was issued from the callback. + */ + readBufCopy = object->readBuf; + object->readBuf = NULL; + + if (object->state.readMode == UART2_Mode_CALLBACK) + { + /* Safely call the callback function in case UART2_read() + * is called from within the callback, to avoid recursion. + */ + object->state.readCallbackPending = true; + HwiP_restore(key); + + /* If we're not inside the read callback function... */ + if (object->state.inReadCallback == false) + { + while (object->state.readCallbackPending) + { + key = HwiP_disable(); + object->state.readCallbackPending = false; + object->state.inReadCallback = true; + HwiP_restore(key); + + object->readCallback(handle, readBufCopy, object->bytesRead, object->userArg, UART2_STATUS_SUCCESS); + + object->state.inReadCallback = false; + } + } + key = HwiP_disable(); + } + } + + HwiP_restore(key); + + if (object->state.readMode == UART2_Mode_BLOCKING) + { + /* If the driver still has bytes to read */ + if (object->readCount > 0) + { + /* Wait for more data, with given timeout */ + if (SemaphoreP_pend(&object->readSem, timeout) != SemaphoreP_OK) + { + /* The semaphore-pend returned with a timeout */ + object->state.readTimedOut = true; + } + + key = HwiP_disable(); + + /* Stop RX temporarily*/ + UART2Support_dmaStopRx(handle); + + /* Update state variables */ + object->readCount = 0; + object->readBuf = NULL; + object->readInUse = false; + + /* In case RX was cancelled or timed out, start a new RX. This will start a transaction into the ring buffer + */ + UART2Support_dmaStartRx(handle); + + if (object->state.readTimedOut) + { + status = UART2_STATUS_ETIMEOUT; + } + + if (object->state.rxCancelled) + { + status = UART2_STATUS_ECANCELLED; + } + + HwiP_restore(key); + } + else + { + /* Flush read-semaphore */ + SemaphoreP_pend(&object->readSem, SemaphoreP_NO_WAIT); + } + } + + key = HwiP_disable(); + + /* Set the number of bytes read, but not in callback mode. The number of bytes read here will be 0 in that case, + * and the correct number will be passed to the callback + */ + if ((object->state.readMode != UART2_Mode_CALLBACK) && (bytesRead != NULL)) + { + *bytesRead = object->bytesRead; + } + + HwiP_restore(key); + + return status; +} + +/* + * ======== UART2_readCancel ======== + */ +void __attribute__((weak)) UART2_readCancel(UART2_Handle handle) +{ + UART2_Object *object = handle->object; + uintptr_t key; + + if ((object->state.readMode != UART2_Mode_BLOCKING) && (object->state.readMode != UART2_Mode_CALLBACK)) + { + return; + } + + key = HwiP_disable(); + + if (object->readInUse == false) + { + HwiP_restore(key); + return; + } + + object->readInUse = false; + object->readCount = 0; + + if (object->state.rxCancelled == false) + { + object->state.rxCancelled = true; + SemaphoreP_post(&object->readSem); + + if (object->state.readMode == UART2_Mode_CALLBACK) + { + object->readCallback(handle, object->readBuf, object->bytesRead, object->userArg, UART2_STATUS_ECANCELLED); + } + } + + HwiP_restore(key); +} + +/* + * ======== UART2_rxDisable ======== + */ +void __attribute__((weak)) UART2_rxDisable(UART2_Handle handle) +{ + UART2_Object *object = handle->object; + UART2_HWAttrs const *hwAttrs = handle->hwAttrs; + + uintptr_t key = HwiP_disable(); + if (object->state.rxEnabled) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2_rxDisable: Disable RX"); + + UART2Support_dmaStopRx(handle); + UART2Support_disableRx(hwAttrs); + + /* Release standby-constraint, but not flash-constraint */ + UART2Support_powerRelConstraint(handle, false); + + object->state.rxEnabled = false; + } + HwiP_restore(key); +} + +/* + * ======== UART2_rxEnable ======== + */ +void __attribute__((weak)) UART2_rxEnable(UART2_Handle handle) +{ + UART2_Object *object = handle->object; + + uintptr_t key = HwiP_disable(); + if (!object->state.rxEnabled) + { + object->state.rxEnabled = true; + + /* Enable registered event callbacks/interrupts and receive */ + UART2Support_enableInts(handle); + UART2Support_enableRx(handle->hwAttrs); + + /* Start a DMA RX transaction */ + UART2Support_dmaStartRx(handle); + + /* Set standby constraint to guarantee transaction, but not flash constraint */ + UART2Support_powerSetConstraint(handle, false); + } + HwiP_restore(key); +} + +/* + * ======== UART2_write ======== + */ +int_fast16_t __attribute__((weak)) +UART2_write(UART2_Handle handle, const void *buffer, size_t size, size_t *bytesWritten) +{ + Log_printf(LogModule_UART2, + Log_INFO, + "UART2_write: Start writing %d byte(s) from buffer address 0x%x", + size, + buffer); + + return UART2_writeTimeout(handle, buffer, size, bytesWritten, UART2_WAIT_FOREVER); +} + +/* + * ======== UART2_writeTimeout ======== + */ +int_fast16_t __attribute__((weak)) +UART2_writeTimeout(UART2_Handle handle, const void *buffer, size_t size, size_t *bytesWritten, uint32_t timeout) +{ + UART2_Object *object = handle->object; + + if (object->state.writeMode == UART2_Mode_NONBLOCKING) + { + return UART2_writeTimeoutNonblocking(handle, buffer, size, bytesWritten, timeout); + } + else + { + return UART2_writeTimeoutBlocking(handle, buffer, size, bytesWritten, timeout); + } +} + +int_fast16_t UART2_writePolling(UART2_Handle handle, const void *buffer, size_t size, size_t *bytesWritten) +{ + UART2_Object *object = handle->object; + UART2_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t writeCount; + + if (object->eventMask & UART2_EVENT_TX_BEGIN) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2_writePolling: Entering event callback with event = 0x%x and user argument = 0x%x", + UART2_EVENT_TX_BEGIN, + object->userArg); + + object->eventCallback(handle, UART2_EVENT_TX_BEGIN, 0, object->userArg); + } + + while (size) + { + writeCount = UART2Support_sendData(hwAttrs, size, (unsigned char *)buffer + object->bytesWritten); + object->bytesWritten += writeCount; + size -= writeCount; + } + /* Wait for data to be fully shifted out of TX shift register. This is + * required so that the device does not transition to low-power mode + * prematurely. + */ + while (!UART2Support_txDone(hwAttrs)) {} + + UART2Support_disableTx(hwAttrs); + if (object->eventMask & UART2_EVENT_TX_FINISHED) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2_writePolling: Entering event callback with event = 0x%x and user argument = 0x%x", + UART2_EVENT_TX_FINISHED, + object->userArg); + + object->eventCallback(handle, UART2_EVENT_TX_FINISHED, 0, object->userArg); + } + + object->writeInUse = false; + + /* Set output argument, if supplied */ + if (bytesWritten != NULL) + { + *bytesWritten = object->bytesWritten; + } + + return UART2_STATUS_SUCCESS; +} + +/* + * ======== UART2_writeTimeout ======== + */ +int_fast16_t UART2_writeTimeoutBlocking(UART2_Handle handle, + const void *buffer, + size_t size, + size_t *bytesWritten, + uint32_t timeout) +{ + UART2_Object *object = handle->object; + UART2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + bool globalInterruptsEnabled; + + /* Set output argument, if supplied */ + if (bytesWritten != NULL) + { + *bytesWritten = 0; + } + + /* Return error if size is 0 */ + if (size == 0) + { + return UART2_STATUS_EINVALID; + } + + /* Save state of global interrupts before entering critical section */ + globalInterruptsEnabled = HwiP_interruptsEnabled(); + + /* Enter critical section while checking and modifying state variables */ + key = HwiP_disable(); + + if (!object->state.opened) + { + /* Instance not yet opened */ + HwiP_restore(key); + return UART2_STATUS_ENOTOPEN; + } + + if (object->writeInUse) + { + /* An active write call is already in progress */ + HwiP_restore(key); + return UART2_STATUS_EINUSE; + } + + /* Update state variables */ + object->writeInUse = true; + object->writeBuf = buffer; + object->writeSize = size; + object->writeCount = size; + object->bytesWritten = 0; + object->txStatus = UART2_STATUS_SUCCESS; + object->state.writeTimedOut = false; + object->state.txCancelled = false; + + /* Flush TX semaphore */ + SemaphoreP_pend(&object->writeSem, SemaphoreP_NO_WAIT); + + /* Enable TX - interrupts must be disabled */ + UART2Support_enableTx(hwAttrs); + + if ((globalInterruptsEnabled == false) && (object->state.writeMode == UART2_Mode_BLOCKING)) + { + /* RTOS not started yet, called from main(), use polling mode */ + HwiP_restore(key); + return UART2_writePolling(handle, buffer, size, bytesWritten); + } + + /* Start TX transaction */ + UART2Support_dmaStartTx(handle); + + HwiP_restore(key); + + /* If blocking mode, wait until transfer is complete */ + if (object->state.writeMode == UART2_Mode_BLOCKING) + { + /* Wait until semaphore is posted by either + * - EOT interrupt is received + * - Write is cancelled + * - SemaphoreP_pend times out + */ + if (SemaphoreP_pend(&object->writeSem, timeout) != SemaphoreP_OK) + { + object->state.writeTimedOut = true; + } + + /* If write was cancelled or timed out, stop TX transaction */ + UART2Support_dmaStopTx(handle); + + object->writeInUse = false; + } + + /* Set output argument, if supplied */ + if (bytesWritten != NULL) + { + *bytesWritten = object->bytesWritten; + } + + if (object->state.txCancelled) + { + object->state.txCancelled = false; + return UART2_STATUS_ECANCELLED; + } + + if (object->state.writeTimedOut) + { + return UART2_STATUS_ETIMEOUT; + } + + return UART2_STATUS_SUCCESS; +} + +/* + * ======== UART2_writeTimeout ======== + */ +int_fast16_t UART2_writeTimeoutNonblocking(UART2_Handle handle, + const void *buffer, + size_t size, + size_t *bytesWritten, + uint32_t timeout) +{ + UART2_Object *object = handle->object; + UART2_HWAttrs const *hwAttrs = handle->hwAttrs; + int_fast16_t status = UART2_STATUS_SUCCESS; + uintptr_t key; + unsigned char *dstAddr; + int space; + + /* Set output argument, if supplied */ + if (bytesWritten != NULL) + { + *bytesWritten = 0; + } + + /* Return error if size is 0 */ + if (size == 0) + { + return UART2_STATUS_EINVALID; + } + + key = HwiP_disable(); + + if (!object->state.opened) + { + /* Instance not yet opened */ + HwiP_restore(key); + return UART2_STATUS_ENOTOPEN; + } + + if (object->writeInUse) + { + /* An active write call is already in progress */ + HwiP_restore(key); + return UART2_STATUS_EINUSE; + } + + /* Update state variables */ + object->writeInUse = true; + object->writeBuf = buffer; + object->writeSize = size; + object->writeCount = size; + object->bytesWritten = 0; + object->txStatus = UART2_STATUS_SUCCESS; + object->state.writeTimedOut = false; + object->state.txCancelled = false; + + /* Enable TX - interrupts must be disabled */ + UART2Support_enableTx(hwAttrs); + + HwiP_restore(key); + + /* Copy as much data as we can to the ring buffer */ + do + { + /* Get the number of bytes we can copy to the ring buffer + * and the location where we can start the copy into the + * ring buffer. + */ + key = HwiP_disable(); + + space = RingBuf_putPointer(&object->txBuffer, &dstAddr); + + if (space > object->writeCount) + { + space = object->writeCount; + } + memcpy(dstAddr, (unsigned char *)buffer + object->bytesWritten, space); + + /* Update the ring buffer state with the number of bytes copied */ + Log_printf(LogModule_UART2, Log_VERBOSE, + "UART2_writeTimeoutNonblocking: Write %d byte(s) to the ring buffer.", + space); + RingBuf_putAdvance(&object->txBuffer, space); + + object->writeCount -= space; + object->bytesWritten += space; + + HwiP_restore(key); + } while ((space > 0) && (object->writeCount > 0)); + + key = HwiP_disable(); + + /* If anything was written to the ring buffer, enable and start TX */ + if (object->bytesWritten > 0) + { + /* Try to start the DMA, it may already be started. */ + UART2Support_enableTx(hwAttrs); + UART2Support_dmaStartTx(handle); + } + + /* If there was no space in the ring buffer, set the status to indicate so */ + if (object->bytesWritten == 0) + { + status = UART2_STATUS_EAGAIN; + } + + /* Set output argument, if supplied */ + if (bytesWritten != NULL) + { + *bytesWritten = object->bytesWritten; + } + + object->writeInUse = false; + + HwiP_restore(key); + + return status; +} + +/* + * ======== UART2_writeCancel ======== + */ +void __attribute__((weak)) UART2_writeCancel(UART2_Handle handle) +{ + UART2_Object *object = handle->object; + uintptr_t key; + uint32_t bytesRemaining; + + key = HwiP_disable(); + + if (!object->state.txCancelled) + { + object->state.txCancelled = true; + + /* Stop DMA transaction */ + bytesRemaining = UART2Support_dmaStopTx(handle); + + /* bytesWritten includes bytes commited to DMA transaction. Remove bytes remaining in transaction from count */ + if (object->state.writeMode == UART2_Mode_NONBLOCKING) + { + object->bytesWritten -= bytesRemaining; + RingBuf_flush(&object->txBuffer); + } + + if (object->writeInUse) + { + /* If in blocking mode, wake up the blocked write task */ + if (object->state.writeMode == UART2_Mode_BLOCKING) + { + SemaphoreP_post(&object->writeSem); + } + + /* Invoke callback if in callback mode */ + if (object->state.writeMode == UART2_Mode_CALLBACK) + { + object->writeInUse = false; + object->writeCount = 0; + object->writeCallback(handle, + (void *)object->writeBuf, + object->bytesWritten, + object->userArg, + UART2_STATUS_ECANCELLED); + } + } + } + + if (object->state.txEnabled) + { + /* If the UART peripheral is actively transmitting, wait for it to clear the TX FIFO */ + while (!UART2Support_txDone(handle->hwAttrs)) {} + + /* Disable TX in the peripheral */ + UART2Support_disableTx(handle->hwAttrs); + object->state.txEnabled = false; + /* Disable standby constraint and flash constraint */ + UART2Support_powerRelConstraint(handle, true); + } + + HwiP_restore(key); +} diff --git a/simplelink_lpf2/source/ti/drivers/UART2.h b/simplelink_lpf2/source/ti/drivers/UART2.h new file mode 100644 index 00000000..574b6a2b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/UART2.h @@ -0,0 +1,1204 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file UART2.h + * @brief PRELIMINARY UART driver interface + * + * WARNING These APIs are PRELIMINARY, and subject to + * change in the next few months. + * + * The UART2 driver is an updated version of the UART driver. The name + * UART2 was given due to changes in the API, to support backwards + * compatibility with applications using the existing UART driver. + * Key differences between the UART and UART2 drivers: + * - UART2 has both RX and TX ring buffers for receiving/sending data. + * - UART2 uses DMA to transfer data between the UART FIFOs and the + * RX and TX ring buffers (in nonblocking mode). In blocking mode and + * callback mode, DMA will transfer data straight between the hardware + * FIFO and the source/destination buffer supplied by the application. + * NOTE: If the source-buffer for a TX operation resides in flash, + * the driver will constrain the flash to remain on during idle. + * - The UART2 APIs for reading and writing data have been made more + * posix-like. + * - UART2 provides for event notification, allowing the application + * to receive TX start and completion events, and RX error events. + * @note These events are synchronous to what can be observed on the data + * lines. A UART2_EVENT_TX_FINISHED event will for example only occur + * after all data has been shifted from the hardware FIFO out onto the + * TX-pin. In contrast, read and write-callbacks are invoked when the + * driver has finished writing data into the hardware FIFO. + * + * To use the UART2 driver, ensure that the correct driver library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module serves as the main interface for applications. Its purpose + * is to implement common code between the device specific implementations + * of UART2. Any device specific code that differs from the common code is + * called through functions prefaced with the "UART2_" naming convention. + * These functions are implemented in each device specific implementation. + * + * @anchor ti_drivers_UART2_Overview + * # Overview + * A UART is used to translate data between the chip and a serial port. + * The UART2 driver simplifies reading and writing to any of the UART + * peripherals on the board, with multiple modes of operation and performance. + * These include blocking and nonblocking modes. + * + * The UART2 driver interface provides device independent APIs, data types, + * and macros. The APIs in this driver serve as an interface to a typical RTOS + * application. The specific peripheral implementations are responsible for + * creating all the RTOS specific primitives to allow for thread-safe + * operation. + * + *
+ * @anchor ti_drivers_UART2_Usage + * # Usage + * + * This documentation provides a basic @ref ti_drivers_UART2_Synopsis + * "usage summary" and a set of @ref ti_drivers_UART2_Examples "examples" + * in the form of commented code fragments. Detailed descriptions of the + * APIs are provided in subsequent sections. + * + * @anchor ti_drivers_UART2_Synopsis + * ## Synopsis + * @anchor ti_drivers_UART2_Synopsis_Code + * @code + * // Import the UART2 driver definitions + * #include + * + * // Initialize UART2 parameters + * UART2_Params params; + * UART2_Params_init(¶ms); + * params.baudRate = 9600; + * params.readMode = UART2_Mode_BLOCKING; + * params.writeMode = UART2_Mode_BLOCKING; + * + * // Open the UART + * UART2_Handle uart; + * uart = UART2_open(CONFIG_UART0, ¶ms); + * + * // Enable receiver, inhibit low power mode + * UART2_rxEnable(uart); + * + * // Read from the UART. + * size_t bytesRead; + * uint8_t buffer[BUFSIZE]; + * int32_t status; + * status = UART2_read(uart, buffer, BUFSIZE, &bytesRead); + * + * // Write to the UART + * size_t bytesWritten; + * status = UART2_write(uart, buffer, BUFSIZE, &bytesWritten); + * + * // Close the UART + * UART2_close(uart); + * @endcode + * + *
+ * @anchor ti_drivers_UART2_Examples + * # Examples + * The following code example opens a UART instance, reads + * a byte from the UART, and then writes the byte back to the UART. + * + * @code + * char input; + * UART2_Handle uart; + * UART2_Params uartParams; + * + * // Open an instance of the UART2 driver + * UART2_Params_init(&uartParams); + * uartParams.baudRate = 115200; + * uart = UART2_open(CONFIG_UART0, &uartParams); + * + * if (uart == NULL) { + * // UART2_open() failed + * while (1); + * } + * + * // Enable receiver, inhibit low power mode + * UART2_rxEnable(uart); + * + * // Loop forever echoing + * while (1) { + * status = UART2_read(uart, &input, 1, &bytesRead); + * status = UART2_write(uart, &input, 1, &bytesWritten); + * } + * @endcode + * + * Details for the example code above are described in the following + * subsections. + * + * ### Opening the UART2 Driver # + * + * Opening a UART requires four steps: + * 1. Create and initialize a UART2_Params structure. + * 2. Fill in the desired parameters. + * 3. Call UART2_open(), passing the index of the UART in the UART2_config + * structure, and the address of the UART2_Params structure. The + * UART2 instance is specified by the index in the UART2_config structure. + * 4. Check that the UART2 handle returned by UART2_open() is non-NULL, + * and save it. The handle will be used to read and write to the + * UART you just opened. + * + * Only one UART index can be used at a time; calling UART2_open() a second + * time with the same index previosly passed to UART2_open() will result in + * an error. You can, though, re-use the index if the instance is closed + * via UART2_close(). + * In the previous example code, CONFIG_UART0 is passed to UART2_open(). + * This macro is defined in the example's ti_drivers_config.h file. + * + * + * ### Modes of Operation # + * + * The UART driver can operate in blocking, nonblocking, or callback mode, by + * setting the writeMode and readMode parameters passed to UART2_open(). + * If these parameters are not set, as in the example code, the UART2 + * driver defaults to blocking mode. Options for the writeMode and + * readMode parameters are #UART2_Mode_BLOCKING, #UART2_Mode_NONBLOCKING, and + * #UART2_Mode_CALLBACK: + * + * - #UART2_Mode_BLOCKING uses a semaphore to block while data is being sent, + * or while waiting for some data to be received. The context of calling + * UART2_read() and UART2_write() in blocking mode must always be a Task. + * The UART2_write() call will block until all data has been transmitted + * onto the TX pin. The UART2_read() calls can be configured to + * have two different behaviors, using the #UART2_ReadReturnMode of the + * #UART2_Params. In #UART2_ReadReturnMode_FULL (the default), + * UART2_read() will block until the requested number of bytes has been + * received. In #UART2_ReadReturnMode_PARTIAL, UART2_read() will block + * until either the requested number of bytes has been received, + * or a UART hardware read timeout has occurred. Using + * UART2_ReadReturnMode_PARTIAL is a good choice if the number of + * incoming data bytes is unknown. In UART2_Mode_BLOCKING, + * UART2_read() will always return at least some data. + * UART2_readTimeout() can be used to specify a timeout in system + * clock ticks, to wait for data. + * UART2_readTimeout() will return when all data is received, or + * the specified timeout expires, or, if using the mode + * UART2_ReadReturnMode_PARTIAL, a hardware read timeout occurs, + * whichever happens first. + * + * - #UART2_Mode_NONBLOCKING does not block waiting for data to be sent + * or received. UART2_write() and UART2_read() will return immediately + * having transferred as much data as the driver can immediately accept + * or has available, respectively. If no data can be accepted or + * received, UART2_write() and UART2_read() return UART2_STATUS_EAGAIN. + * + * - #UART2_Mode_CALLBACK is nonblocking and UART2_read() and UART2_write() + * will return while data is being sent in the context of a hardware + * interrupt. When all data has been read from, or written to the hardware + * FIFO, the UART2 driver will call the user's callback function, and the + * driver is ready to accept another read or write operation. + * @note When transmitting, it is therefore not guaranteed that all data has + * been shifted out to the TX pin when the write-callback is invoked. This is + * instead signalled by the UART2_EVENT_TX_FINISHED event. + * In some cases, the UART data transfer may have been cancelled, + * so the number of bytes sent/received are passed to the callback function. + * Your implementation of the callback function can use this information as needed. + * Since the user's callback may be called in the context of a hardware + * interrupt, the callback function must not make any RTOS blocking calls. + * The buffer passed to UART2_write() in UART2_Mode_CALLBACK must remain + * coherent until all the characters have been sent + * (ie until the tx callback has been called with a byte count equal to + * that passed to UART2_write()). + * + * ### Enabling the Receiver # + * + * The example code enables the collection of data into the RX ring buffer + * \a before the first call to UART2_read(): + * + * @code + * UART2_rxEnable(uart); + * @endcode + * + * Note that this call is not necessary if the first UART2_read() is called + * in time to prevent the RX FIFO from overrun, or if flow control is used. + * + * ### Reading and Writing Data # + * + * The example code reads one byte frome the UART instance, and then writes + * one byte back to the same instance: + * + * @code + * status = UART2_read(uart, &input, 1, &bytesRead); + * status = UART2_write(uart, &input, 1, &bytesWritten); + * @endcode + * + * The UART2 driver allows full duplex data transfers. Therefore, it is + * possible to call UART2_read() and UART2_write() at the same time. + * It is not possible, however, + * to issue multiple concurrent operations in the same direction. + * For example, if one thread calls UART2_read(uart0, buffer0...), + * any other thread attempting UART2_read(uart0, buffer1...) will result in + * an error of UART2_STATUS_EINUSE, until all the data from the first + * UART2_read() has been transferred to buffer0. This applies to blocking, + * callback, and nonblocking modes. So applications must either synchronize + * UART2_read() (or UART2_write()) calls that use the same UART handle, or + * check for the UART2_STATUS_EINUSE return code indicating that a transfer is + * still ongoing. + * + *
+ * @anchor ti_drivers_UART2_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for driver configuration information. + *
+ * + * ============================================================================ + */ + +#ifndef ti_drivers_UART2__include +#define ti_drivers_UART2__include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief No hardware flow control + */ +#define UART2_FLOWCTRL_NONE 0 + +/*! + * @brief Hardware flow control + */ +#define UART2_FLOWCTRL_HARDWARE 1 + +/** @addtogroup UART2_STATUS + * @{ + */ +/*! + * @brief Successful status code returned by UART2 APIs. + */ +#define UART2_STATUS_SUCCESS (0) + +/*! + * @brief A read timeout occurred (not an error). + */ +#define UART2_STATUS_SREADTIMEOUT (1) + +/*! + * @brief A framing error occurred. + */ +#define UART2_STATUS_EFRAMING (-1) + +/*! + * @brief A parity error occurred. + */ +#define UART2_STATUS_EPARITY (-2) + +/*! + * @brief A break error occurred. + */ +#define UART2_STATUS_EBREAK (-4) + +/*! + * @brief A FIFO overrun occurred. + */ +#define UART2_STATUS_EOVERRUN (-8) + +/*! + * @brief The UART is currently in use. + */ +#define UART2_STATUS_EINUSE (-9) + +/*! + * @brief An invalid argument or UART2_Params field was passed to UART2 API. + */ +#define UART2_STATUS_EINVALID (-10) + +/*! + * @brief General failure status returned by UART2 API. + */ +#define UART2_STATUS_EFAIL (-11) + +/*! + * @brief A memory allocation failure occurred. + */ +#define UART2_STATUS_EMEMORY (-12) + +/*! + * @brief A timeout occurred for a blocking UART2_read or UART2_write call. + */ +#define UART2_STATUS_ETIMEOUT (-13) + +/*! + * @brief A UART2_write() or UART2_read() operation was cancelled. + */ +#define UART2_STATUS_ECANCELLED (-14) + +/*! + * @brief A UART2_write() or UART2_read() called on a device not opened. + */ +#define UART2_STATUS_ENOTOPEN (-15) + +/*! + * @brief A UART2_write() or UART2_read() in UART2_Mode_NONBLOCKING would + * have blocked. + */ +#define UART2_STATUS_EAGAIN (-16) + +/** @}*/ + +/** @addtogroup UART2_EVENT + * @{ + */ + +/*! + * @brief A receive overrun has occurred. + */ +#define UART2_EVENT_OVERRUN (0x08) + +/*! + * @brief A break has occurred. + */ +#define UART2_EVENT_BREAK (0x04) + +/*! + * @brief A parity error has occurred. + */ +#define UART2_EVENT_PARITY (0x02) + +/*! + * @brief A framing error has occurred. + */ +#define UART2_EVENT_FRAMING (0x01) + +/*! + * @brief The UART will start transmitting data. + * + * This event can be useful in RS-485 half-duplex systems to toggle TX enable high. + */ +#define UART2_EVENT_TX_BEGIN (0x10) + +/*! + * @brief The UART stopped transmitting data. + * + * This event can be useful in RS-485 half-duplex systems to toggle TX enable low. + */ +#define UART2_EVENT_TX_FINISHED (0x20) + +/** @}*/ + +/*! + * @brief Wait forever define + */ +#define UART2_WAIT_FOREVER (~(0U)) + +/*! + * @brief A handle that is returned from a UART2_open() call. + */ +typedef struct UART2_Config_ *UART2_Handle; + +/*! + * @brief The definition of a callback function used by the UART2 driver + * when used in #UART2_Mode_CALLBACK + * The callback can occur in task or interrupt context. + * + * @param[in] UART2_Handle UART2_Handle + * + * @param[in] buf Pointer to read/write buffer + * + * @param[in] count Number of elements read/written + * + * @param[in] userArg A user supplied argument specified + * in UART2_Params. + * + * @param[in] status A UART2_STATUS code indicating + * success or failure of the transfer. + */ +typedef void (*UART2_Callback)(UART2_Handle handle, void *buf, size_t count, void *userArg, int_fast16_t status); + +/*! + * @brief The definition of a callback function used by the UART driver. + * The callback can occur in task or interrupt context. + * + * @param[in] UART2_Handle UART2_Handle + * + * @param[in] event UART2_EVENT that has occurred. + * + * @param[in] data - UART2_EVENT_OVERRUN: accumulated count + * - UART2_EVENT_BREAK: unused + * - UART2_EVENT_PARITY: unused + * - UART2_EVENT_FRAMING: unused + * - UART2_EVENT_TX_BEGIN: unused + * - UART2_EVENT_TX_FINISHED: unused + * + * @param[in] userArg A user supplied argument specified + * in UART2_Params. + * + * @param[in] status A UART2_STATUS code indicating + * success or failure of the transfer. + */ +typedef void (*UART2_EventCallback)(UART2_Handle handle, uint32_t event, uint32_t data, void *userArg); + +/*! + * @brief UART2 mode settings + * + * This enum defines the read and write modes for the configured UART. + */ +typedef enum +{ + /*! + * UART2_write() will block the calling task until all of the data has been + * transmitted onto the TX pin. UART2_read() will block until some data + * becomes available. + */ + UART2_Mode_BLOCKING, + + /*! + * Nonblocking, UART2_write() or UART2_read() will return immediately. + * When all data has been either written to, or read from the hardware FIFO, + * the callback function is called from either the caller's context or from + * an interrupt context, and the driver is ready to accept a new call to + * UART2_write() or UART2_read(). It is not guaranteed that all data has + * been fully transmitted yet when the write-callback is invoked. To be + * notified of this, the application must subscribe to the UART2_EVENT_TX_FINISHED + * event. + */ + UART2_Mode_CALLBACK, + + /*! + * Nonblocking, UART2_write() or UART2_read() will return immediately. + * UART2_write() will copy as much data into the transmit buffer as space + * allows. UART2_read() will copy as much data from the receive buffer + * as is immediately available. + */ + UART2_Mode_NONBLOCKING, + /*! @cond NODOC */ + /* Added for backwards compatibility. */ + UART2_Mode_POLLING = UART2_Mode_NONBLOCKING + /*! @endcond */ +} UART2_Mode; + +/*! + * @brief UART2 return mode settings + * + * This enumeration defines the return modes for UART2_read(). + * + * #UART2_ReadReturnMode_FULL unblocks or performs a callback when the read + * buffer has been filled with the number of bytes passed to #UART2_read(). + * #UART2_ReadReturnMode_PARTIAL unblocks or performs a callback whenever a + * read timeout error occurs on the UART peripheral. This timeout + * error is not the same as the blocking read timeout in the UART2_Params; + * the read timeout occurs if the read FIFO is non-empty and no new + * data has been received for a device/baudrate dependent number of + * clock cycles. This mode can be used when the exact number of bytes to + * be read is not known. + */ +typedef enum +{ + /*! Unblock/callback when buffer is full. */ + UART2_ReadReturnMode_FULL, + + /*! Unblock/callback when no new data comes in. */ + UART2_ReadReturnMode_PARTIAL +} UART2_ReadReturnMode; + +/*! + * @brief UART2 data length settings + * + * This enumeration defines the UART data lengths. + */ +typedef enum +{ + UART2_DataLen_5 = 0, /*!< Data length is 5 bits */ + UART2_DataLen_6 = 1, /*!< Data length is 6 bits */ + UART2_DataLen_7 = 2, /*!< Data length is 7 bits */ + UART2_DataLen_8 = 3 /*!< Data length is 8 bits */ +} UART2_DataLen; + +/*! + * @brief UART2 stop bit settings + * + * This enumeration defines the UART2 stop bits. + */ +typedef enum +{ + UART2_StopBits_1 = 0, /*!< One stop bit */ + UART2_StopBits_2 = 1 /*!< Two stop bits */ +} UART2_StopBits; + +/*! + * @brief UART2 parity type settings + * + * This enumeration defines the UART2 parity types. + */ +typedef enum +{ + UART2_Parity_NONE = 0, /*!< No parity */ + UART2_Parity_EVEN = 1, /*!< Parity bit is even */ + UART2_Parity_ODD = 2, /*!< Parity bit is odd */ + UART2_Parity_ZERO = 3, /*!< Parity bit is always zero */ + UART2_Parity_ONE = 4 /*!< Parity bit is always one */ +} UART2_Parity; + +/*! + * @brief UART2 Parameters + * + * UART2 parameters are used with the UART2_open() call. Default values for + * these parameters are set using UART2_Params_init(). + * + * @sa UART2_Params_init() + */ +typedef struct +{ + UART2_Mode readMode; /*!< Mode for all read calls */ + UART2_Mode writeMode; /*!< Mode for all write calls */ + UART2_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ + UART2_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ + UART2_EventCallback eventCallback; /*!< Pointer to event callback function. */ + uint32_t eventMask; /*!< Mask of events that the application is interested in */ + UART2_ReadReturnMode readReturnMode; /*!< Receive return mode */ + uint32_t baudRate; /*!< Baud rate for UART */ + UART2_DataLen dataLength; /*!< Data length for UART */ + UART2_StopBits stopBits; /*!< Stop bits for UART */ + UART2_Parity parityType; /*!< Parity bit type for UART */ + void *userArg; /*!< User supplied argument for callback functions */ +} UART2_Params; + +/*! @cond NODOC */ +#define UART2_BASE_OBJECT \ + /* UART2 state variable */ \ + struct \ + { \ + uint32_t overrunCount; /*!< Total count of overruns */ \ + UART2_Mode readMode; /*!< Mode for read calls */ \ + UART2_Mode writeMode; /*!< Mode for write calls */ \ + UART2_ReadReturnMode readReturnMode; /*!< RX return mode (partial/full) */ \ + bool opened; /*!< Has the obj been opened */ \ + bool txEnabled; /*!< Flag set if ongoing transmit */ \ + bool rxEnabled; /*!< Flag set if ongoing receive */ \ + bool rxCancelled; /*!< Has the TX been canceled */ \ + bool txCancelled; /*!< Has the TX been canceled */ \ + bool readTimedOut; /*!< Has read timed out */ \ + bool writeTimedOut; /*!< Has write timed out */ \ + bool overrunActive; /*!< Is a RX overrun active */ \ + bool inReadCallback; /*!< To avoid stack overflow */ \ + bool readCallbackPending; /*!< To avoid stack overflow */ \ + bool inWriteCallback; /*!< To avoid stack overflow */ \ + bool writeCallbackPending; /*!< To avoid stack overflow */ \ + bool readToRingbuf; /*!< Read into ring buffer or user-buffer */ \ + } state; \ + \ + HwiP_Struct hwi; /*!< Hwi object for interrupts */ \ + uint32_t baudRate; /*!< Baud rate for UART */ \ + UART2_DataLen dataLength; /*!< Data length for UART */ \ + UART2_StopBits stopBits; /*!< Stop bits for UART */ \ + UART2_Parity parityType; /*!< Parity bit type for UART */ \ + int32_t rxStatus; /*!< RX status */ \ + int32_t txStatus; /*!< TX status */ \ + UART2_EventCallback eventCallback; /*!< User supplied event callback */ \ + uint32_t eventMask; /*!< User supplied event mask */ \ + void *userArg; /*!< User supplied arg for callbacks */ \ + \ + /* UART read variables */ \ + RingBuf_Object rxBuffer; /*!< Receive ring buffer */ \ + bool readInUse; /*!< Is a read() active */ \ + unsigned char *readBuf; /*!< Buffer data pointer */ \ + size_t readSize; /*!< Number of bytes to read */ \ + size_t readCount; /*!< Number of bytes left to read */ \ + size_t rxSize; /*!< # of bytes to read in DMA xfer */ \ + size_t bytesRead; /*!< Number of bytes read */ \ + SemaphoreP_Struct readSem; /*!< UART read semaphore */ \ + UART2_Callback readCallback; /*!< Pointer to read callback */ \ + \ + /* UART write variables */ \ + RingBuf_Object txBuffer; /*!< Transmit ring buffer */ \ + volatile bool writeInUse; /*!< Flag to show ongoing write */ \ + const unsigned char *writeBuf; /*!< Buffer data pointer */ \ + size_t writeSize; /*!< Number of bytes to write*/ \ + size_t writeCount; /*!< Number of bytes left to write */ \ + size_t txSize; /*!< # of bytes to write with DMA */ \ + size_t bytesWritten; /*!< Number of bytes written */ \ + SemaphoreP_Struct writeSem; /*!< UART write semaphore*/ \ + UART2_Callback writeCallback; /*!< Pointer to write callback */ \ + \ + /* For Power management */ \ + Power_Resource powerMgrId; /*!< Determined from base address */ \ +/*! @endcond */ + +/*! + * @cond NODOC + * UART2 Object. Applications must not access any member variables of + * this structure! + */ +typedef struct +{ + UART2_BASE_OBJECT +} UART2_Object; +/*! @endcond */ + +/*! @cond NODOC */ +#define UART2_BASE_HWATTRS \ + /*! UART Peripheral's base address */ \ + uint32_t baseAddr; \ + /*! UART Peripheral's interrupt vector */ \ + int intNum; \ + /*! UART Peripheral's interrupt priority */ \ + uint8_t intPriority; \ + /*! Pointer to an application RX buffer */ \ + unsigned char *rxBufPtr; \ + /*! Size of rxBufPtr */ \ + size_t rxBufSize; \ + /*! Pointer to an application TX buffer */ \ + unsigned char *txBufPtr; \ + /*! Size of txBufPtr */ \ + size_t txBufSize; \ + /*! Hardware flow control setting */ \ + uint32_t flowControl; \ + /*! UART RX pin assignment */ \ + uint32_t rxPin; \ + /*! UART TX pin assignment */ \ + uint32_t txPin; \ + /*! UART clear to send (CTS) pin assignment */ \ + uint32_t ctsPin; \ + /*! UART request to send (RTS) pin assignment */ \ + uint32_t rtsPin; \ +/*! @endcond */ + +/*! + * @cond NODOC + * UART2 HWAttrs. + */ +typedef struct +{ + UART2_BASE_HWATTRS +} UART2_HWAttrs; +/*! @endcond */ + +/*! + * @brief UART2 Global configuration + * + * The UART2_Config structure contains a set of pointers used to characterize + * the UART2 driver implementation. + * + */ +typedef struct UART2_Config_ +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} UART2_Config; + +extern const UART2_Config UART2_config[]; +extern const uint_least8_t UART2_count; + +/*! + * @brief Function to close a UART peripheral specified by the UART2 handle + * + * @pre UART2_open() has been called. + * @pre There are no ongoing read or write calls. Any ongoing read + * or write calls can be cancelled with UART2_readCancel() or + * UART2_writeCancel(). + * + * @param[in] handle A #UART2_Handle returned from UART2_open() + * + * @sa UART2_open() + */ +extern void UART2_close(UART2_Handle handle); + +/*! + * @brief Function to flush data in the UART RX FIFO. + * + * @pre UART2_open() has been called. + * + * This function can be called to remove all data from the RX FIFO, for + * example, after a UART read error has occurred. + * All data in the RX circular buffer will be discarded. + * + * @param[in] handle A #UART2_Handle returned from UART2_open() + */ +extern void UART2_flushRx(UART2_Handle handle); + +/*! + * @brief Get the number of bytes available in the circular buffer. + * + * @pre UART2_open() has been called. + * + * @param[in] handle A #UART2_Handle returned from UART2_open() + * + * @return Returns the number of bytes available in the RX circular + * buffer. + * + * @sa UART2_rxEnable() + */ +extern size_t UART2_getRxCount(UART2_Handle handle); + +/*! + * @brief Function to initialize a given UART peripheral + * + * Function to initialize a given UART peripheral specified by the + * particular index value. + * + * @param[in] index Logical peripheral number for the UART indexed into + * the UART2_config table + * + * @param[in] params Pointer to a parameter block. If NULL, default + * parameter values will be used. All the fields in + * this structure are read-only. + * + * @sa UART2_close() + */ +extern UART2_Handle UART2_open(uint_least8_t index, UART2_Params *params); + +/*! + * @brief Function to initialize the UART2_Params struct to its defaults + * + * @param[in] params A pointer to UART2_Params structure for + * initialization + * + * Defaults values are: + * readMode = UART2_Mode_BLOCKING; + * writeMode = UART2_Mode_BLOCKING; + * eventCallback = NULL; + * eventMask = 0; + * readCallback = NULL; + * writeCallback = NULL; + * readReturnMode = UART2_ReadReturnMode_PARTIAL; + * baudRate = 115200; + * dataLength = UART2_DataLen_8; + * stopBits = UART2_StopBits_1; + * parityType = UART2_Parity_NONE; + * userArg = NULL; + */ +extern void UART2_Params_init(UART2_Params *params); + +/*! + * @brief Function that reads data from a UART. + * + * %UART2_read() reads data from a UART controller. The destination is + * specified by \a buffer and the number of bytes to read is given by + * \a size. + * + * In #UART2_Mode_BLOCKING, %UART2_read() blocks task execution until all + * the data in buffer has been read, if the read return mode is + * #UART2_ReadReturnMode_FULL. + * If the read return mode is #UART2_ReadReturnMode_PARTIAL, %UART2_read() + * returns before all the data has been read, if some data has been received, + * but reception has been inactive sufficiently long for a hardware read + * timeout to occur (e.g., for a 32-bit period). + * If a receive error occurs (e.g., framing, FIFO overrun), %UART2_read() + * will return with the number of bytes read up to the occurance of the + * error. + * + * In #UART2_Mode_CALLBACK, %UART2_read() does not block task execution. + * Instead, a callback function specified by UART2_Params::readCallback + * is called when the transfer is finished (#UART2_ReadReturnMode_FULL), or + * reception has become inactive (#UART2_ReadReturnMode_PARTIAL). + * The callback function can occur in the caller's context or in HWI + * context, depending on the device-specific implementation. + * An unfinished asynchronous read operation must always be cancelled using + * UART2_readCancel() before calling UART2_close(). + * + * In #UART2_Mode_NONBLOCKING, %UART2_read() will return the minimum + * of size bytes and the number of bytes in the RX circular buffer. + * In this mode, the application should check the number of bytes + * returned in the bytesRead parameter. A status of success will be + * returned, even if not all bytes requested were read, unless no + * data is available or an error occured. If no data is available, + * a status of UART2_STATUS_EAGAIN is returned. + * + * @note It is ok to call %UART2_read() from its own callback function when in + * #UART2_Mode_CALLBACK. + * + * @warning By calling this function, RX will be enabled even after the function + * has returned. This is in order to keep collecting data into the RX buffer + * to prevent losing data at high baud-rates. As a consequence, entering low + * power mode will be inhibited. To disable RX and enable entering low power + * mode, UART2_rxDisable must be called. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @param[in] buffer A pointer to an empty buffer to which + * received data should be read + * + * @param[in] size The number of bytes to be read into buffer + * + * @param[out] bytesRead If non-NULL, the location to store the number of + * bytes actually read into the buffer. If NULL, this + * parameter will be ignored. In callback mode, NULL + * could be passed in for this parameter, since the + * callback function will be passed the number of bytes + * read. In blocking mode, NULL can be passed, + * however, status should be checked in case the number + * of bytes requested was not received due to errors. + * In nonblocking mode, it is not recommended to pass + * NULL for this parameter, as it would be impossible to + * determine the number of bytes actually read. + * + * @return Returns a status indicating success or failure of the read. + * + * @retval #UART2_STATUS_SUCCESS The call was successful. + * @retval #UART2_STATUS_EINUSE Another read from the UART is currently + * ongoing. + * @retval #UART2_STATUS_EAGAIN In #UART2_Mode_NONBLOCKING, no data is + * currently available. + * @retval #UART2_STATUS_ECANCELLED In #UART2_Mode_BLOCKING, the read was + * canceled by a call to UART2_readCancel() + * before any data could be received. + */ +extern int_fast16_t UART2_read(UART2_Handle handle, void *buffer, size_t size, size_t *bytesRead); + +/*! @cond NODOC */ +extern int_fast16_t __attribute__((weak)) +UART2_readFull(UART2_Handle handle, void *buffer, size_t size, size_t *bytesRead); +/*! @endcond */ + +/*! + * @brief Function that reads data from a UART, with a specified timeout + * for blocking mode. + * + * %UART2_readTimeout() reads data from a UART controller. The destination is + * specified by \a buffer and the number of bytes to read is given by + * \a size. + * + * In #UART2_Mode_BLOCKING with #UART2_ReadReturnMode_FULL, + * %UART2_readTimeout() blocks task execution until all the data in buffer + * has been read, or the specified timeout has elapsed. + * In #UART2_Mode_BLOCKING with #UART2_ReadReturnMode_PARTIAL, + * %UART2_readTimeout() returns before all the data has been read, if some + * data has been received, but reception has been inactive sufficiently + * long for a hardware read timeout to occur (e.g., for a 32-bit period). + * %UART2_readTimeout() will also return if the specified timeout parameter + * has elapsed. Note that the timeout parameter is different from the + * hardware read timeout. + * + * In #UART2_Mode_CALLBACK, %UART2_readTimeout() does not block task + * execution. Instead, a callback function specified by + * UART2_Params::readCallback is called when the transfer is finished + * (#UART2_ReadReturnMode_FULL), or reception has become inactive + * (#UART2_ReadReturnMode_PARTIAL). + * The callback function can occur in the caller's context or in HWI + * context, depending on the device-specific implementation. + * An unfinished asynchronous read operation must always be cancelled using + * UART2_readCancel() before calling UART2_close(). In #UART2_Mode_CALLBACK, + * the timeout parameter passed to %UART2_readTimeout(), is ignored. + * + * In #UART2_Mode_NONBLOCKING, %UART2_readTimeout() will return the minimum of + * size and the number of data in the RX circular buffer. In this mode, + * the application should check the number of bytes read in the + * bytesRead parameter. A status of success will be returned if + * one or more bytes is available, unless an error occured. + * In #UART2_Mode_NONBLOCKING, the timeout parameter passed to + * %UART2_readTimeout(), is ignored. + * + * @note It is ok to call %UART2_readTimeout() from its own callback + * function when in #UART2_Mode_CALLBACK. + * + * @warning By calling this function, RX will be enabled even after the function + * has returned. This is in order to keep collecting data into the RX buffer + * to prevent losing data at high baud-rates. As a consequence, entering low + * power mode will be inhibited. To disable RX and enable entering low power + * mode, UART2_rxDisable must be called. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @param[in] buffer A pointer to an empty buffer to which + * received data should be read + * + * @param[in] size The number of bytes to be read into buffer + * + * @param[out] bytesRead If non-NULL, the location to store the number of + * bytes actually read into the buffer. If NULL, this + * parameter will be ignored. In callback mode, NULL + * could be passed in for this parameter, since the + * callback function will be passed the number of bytes + * read. Similarly, in blocking mode with infinite + * timeout, NULL can be passed. However, status should + * be checked in case the number of bytes requested was + * not received due to errors. + * In nonblocking mode, it is not recommended to pass + * NULL for this parameter, as it would be impossible to + * determine the number of bytes actually read. + * + * @param[in] timeout The number of system clock ticks to wait until + * all data is received. If not all requested data + * was received within the timeout period, an error of + * UART2_STATUS_ETIMEOUT will be returned. This + * parameter is only applicable to #UART2_Mode_BLOCKING. + * + * @return Returns a status indicating success or failure of the read. + * + * @retval #UART2_STATUS_SUCCESS The call was successful. + * @retval #UART2_STATUS_EINUSE Another read from the UART is currently + * ongoing. + * @retval #UART2_STATUS_EAGAIN In #UART2_Mode_NONBLOCKING, no data is + * currently available. + * @retval #UART2_STATUS_ECANCELLED In #UART2_Mode_BLOCKING, the read was + * canceled by a call to UART2_readCancel() + * before any data could be received. + * @retval #UART2_STATUS_ETIMEOUT The read operation timed out. + */ +extern int_fast16_t UART2_readTimeout(UART2_Handle handle, + void *buffer, + size_t size, + size_t *bytesRead, + uint32_t timeout); + +/*! + * @brief Function that cancels a UART2_read() function call. + * + * This function cancels an asynchronous UART2_read() operation in + * in #UART2_Mode_CALLBACK, or unblocks a UART2_read() call in + * #UART2_Mode_BLOCKING. + * In #UART2_Mode_CALLBACK, UART2_readCancel() calls the registered read + * callback function with the number of bytes received so far. + * It is the application's responsibility to check the count argument + * in the callback function and handle the case where only a subset of the + * bytes were received. The callback function will be passed a status of + * #UART2_STATUS_ECANCELLED. + * + * In #UART2_Mode_BLOCKING, #UART2_read() will return + * #UART2_STATUS_ECANCELLED, and the bytesRead parameter will be set to + * the number of bytes received so far. + * + * This API has no affect in #UART2_Mode_NONBLOCKING. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + */ +extern void UART2_readCancel(UART2_Handle handle); + +/*! + * @brief Function that writes data to a UART. + * + * %UART2_write() writes data from a memory buffer to the UART interface. + * The source is specified by \a buffer and the number of bytes to write + * is given by \a size. + * + * In #UART2_Mode_BLOCKING, UART2_write() blocks task execution until all + * the data in buffer has been transmitted onto the TX pin. + * + * In #UART2_Mode_CALLBACK, %UART2_write() does not block task execution. + * Instead, a callback function specified by UART2_Params::writeCallback is + * called when all data has been written to the hardware FIFO. This means that + * that driver is ready to accept another call to UART2_write(). + * @note In contrast to #UART2_Mode_BLOCKING, it is not guaranteed that all + * data has been transmitted onto the TX pin when callback is invoked. + * This is instead signalled by the event UART2_EVENT_TX_FINISHED. + * + * The buffer passed to UART2_write() in #UART2_Mode_CALLBACK is not + * copied. The buffer must remain coherent until all the characters have + * been sent (ie until the write callback has been called with a byte count + * equal to that passed to UART2_write()). + * The callback function can occur in the caller's task context or in + * interrupt context, depending on the device implementation. + * An unfinished asynchronous write operation must always be cancelled using + * UART2_writeCancel() before calling UART2_close(). + * + * In #UART2_Mode_NONBLOCKING, UART2_write() will send out as many of the + * bytes in the buffer as possible, until the TX circular buffer is + * full. In nonblocking mode, UART2_write() can be called from + * any context. + * The bytesWritten parameter should not be NULL so the application can + * determine the number of bytes actually written. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @param[in] buffer A read-only pointer to buffer containing data to + * be written to the UART + * + * @param[in] size The number of bytes in the buffer that should be + * written to the UART + * + * @param[out] bytesWritten If non-NULL, the location to store the number of + * bytes actually written to the UART in + * UART2_Mode_BLOCKING and UART2_Mode_NONBLOCKING. In + * UART2_Mode_CALLBACK, bytesWritten will be set to 0. + * If bytesWritten is NULL, this parameter will be + * ignored. + * In nonblocking mode, it is not recommended to pass + * NULL for bytesWritten, as the application would have + * no way to determine the number of bytes actually + * written. In nonblocking mode, a status of success + * will be returned even if not all the requested + * bytes could be written. + * + * @return Returns a status indicating success or failure of the write. + * + * @retval #UART2_STATUS_SUCCESS The call was successful. + * @retval #UART2_STATUS_EINUSE Another write to the UART is currently + * ongoing. + */ +extern int_fast16_t UART2_write(UART2_Handle handle, const void *buffer, size_t size, size_t *bytesWritten); + +/*! + * @brief Function that disables collecting of RX data into the circular + * buffer. + * + * The driver implementation uses a circular buffer to collect RX + * data while a UART2_read() is not in progress. This function will + * disable buffering of RX data into the circular buffer. UART2_read() will + * read directly from the UART driver's RX buffer. Disabling the circular + * buffer will also allow the device to go into low power modes. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @sa UART2_rxEnable() + */ +extern void UART2_rxDisable(UART2_Handle handle); + +/*! + * @brief Function that enables collecting of RX data into the circular + * buffer. + * + * The driver implementation uses a circular buffer to collect RX + * data while a UART2_read() is not in progress. This function will + * enable buffering of RX data into the circular buffer. UART2_read() will + * read directly from the UART drivers RX buffer. Enabling the circular + * buffer will also prevent the device from going into low power modes. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @sa UART2_rxDisable() + */ +extern void UART2_rxEnable(UART2_Handle handle); + +/*! + * @brief Function that writes data to a UART, with a specified timeout. + * + * %UART2_writeTimeout() writes data from a memory buffer to the UART + * interface. + * The source is specified by \a buffer and the number of bytes to write + * is given by \a size. + * A timeout in system clock ticks specifies the maximum time to wait + * until all data is written (#UART2_Mode_BLOCKING only). + * + * In #UART2_Mode_BLOCKING, UART2_writeTimeout() blocks task execution until + * all the data in buffer has been transmitted, or the timeout expires. + * + * In #UART2_Mode_CALLBACK, %UART2_writeTimeout() does not block task execution. + * Instead, a callback function specified by UART2_Params::writeCallback is + * called when all data has been written to the hardware FIFO. This means that + * that driver is ready to accept another call to UART2_writeTimeout(). + * @note In contrast to #UART2_Mode_BLOCKING, it is not guaranteed that all + * data has been transmitted onto the TX pin when callback is invoked. + * This is instead signalled by the event UART2_EVENT_TX_FINISHED. + * + * The buffer passed to UART2_writeTimeout() in #UART2_Mode_CALLBACK is not + * copied. The buffer must remain coherent until all the characters have + * been sent (ie until the write callback has been called with a byte count + * equal to that passed to UART2_writeTimeout()). + * The callback function can occur in the caller's task context or in + * interrupt context, depending on the device implementation. + * An unfinished asynchronous write operation must always be cancelled using + * UART2_writeCancel() before calling UART2_close(). + * + * In #UART2_Mode_NONBLOCKING, UART2_writeTimeout() will send out as many of + * the bytes in the buffer as possible, until the TX FIFO is full. In + * nonblocking mode, UART2_writeTimeout() is nonblocking and can be called + * from any context. The bytesWritten parameter should not be NULL so the + * application can determine the number of bytes actually written. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + * + * @param[in] buffer A read-only pointer to buffer containing data to + * be written to the UART + * + * @param[in] size The number of bytes in the buffer that should be + * written to the UART + * + * @param[out] bytesWritten If non-NULL, the location to store the number of + * bytes actually written to the UART in + * UART2_Mode_BLOCKING and UART2_Mode_NONBLOCKING. In + * UART2_Mode_CALLBACK, bytesWritten will be set to 0. + * If bytesWritten is NULL, this parameter will be + * ignored. + * In nonblocking mode, it is not recommended to pass + * NULL for bytesWritten, as the application would have + * no way to determine the number of bytes actually + * written. In nonblocking mode, a status of success + * will be returned even if not all the requested + * bytes could be written. + * + * @param[in] timeout The number of system clock ticks to wait for the + * write to complete (#UART2_Mode_BLOCKING only). If + * the timeout expires before all bytes are written, a + * status of UART2_STATUS_ETIMEOUT will be returned. + * + * @return Returns a status indicating success or failure of the write. + * + * @retval #UART2_STATUS_SUCCESS The call was successful. + * @retval #UART2_STATUS_EINUSE Another write to the UART is currently + * ongoing. + * @retval #UART2_STATUS_ETIMEOUT The write operation timed out. + */ +extern int_fast16_t UART2_writeTimeout(UART2_Handle handle, + const void *buffer, + size_t size, + size_t *bytesWritten, + uint32_t timeout); + +/*! + * @brief Function that cancels a UART2_write() function call. + * + * This function cancels an asynchronous UART2_write() operation when + * write mode is #UART2_Mode_CALLBACK, or an ongoing UART2_write() in + * #UART2_Mode_NONBLOCKING. + * In callback mode, UART2_writeCancel() calls the registered + * write callback function no matter how many bytes were sent. It + * is the application's responsibility to check the count argument in the + * callback function and handle cases where only a subset of the bytes were + * sent. The callback function will be passed a status of + * #UART2_STATUS_ECANCELLED. + * In blocking mode, UART2_write() will return #UART2_STATUS_ECANCELLED. + * + * @note The above applies to %UART2_writeTimeout() as well. + * + * This API has no affect in nonblocking mode. + * + * @param[in] handle A #UART2_Handle returned by UART2_open() + */ +extern void UART2_writeCancel(UART2_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UART2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/Watchdog.c b/simplelink_lpf2/source/ti/drivers/Watchdog.c new file mode 100644 index 00000000..c01d6164 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Watchdog.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Watchdog.c ======== + */ + +#include +#include +#include + +#include +#include + +extern const Watchdog_Config Watchdog_config[]; +extern const uint_least8_t Watchdog_count; + +/* Default Watchdog parameters structure */ +const Watchdog_Params Watchdog_defaultParams = { + NULL, /* callbackFxn */ + Watchdog_RESET_ON, /* resetMode */ + Watchdog_DEBUG_STALL_ON, /* debugStallMode */ + NULL /* custom */ +}; + +static bool isInitialized = false; + +/* + * ======== Watchdog_clear ======== + */ +void Watchdog_clear(Watchdog_Handle handle) +{ + handle->fxnTablePtr->watchdogClear(handle); +} + +/* + * ======== Watchdog_close ======== + */ +void Watchdog_close(Watchdog_Handle handle) +{ + handle->fxnTablePtr->watchdogClose(handle); +} + +/* + * ======== Watchdog_control ======== + */ +int_fast16_t Watchdog_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (handle->fxnTablePtr->watchdogControl(handle, cmd, arg)); +} + +/* + * ======== Watchdog_init ======== + */ +void Watchdog_init(void) +{ + uint_least8_t i; + uint_fast32_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + isInitialized = (bool)true; + + /* Call each driver's init function */ + for (i = 0; i < Watchdog_count; i++) + { + Watchdog_config[i].fxnTablePtr->watchdogInit((Watchdog_Handle) & (Watchdog_config[i])); + } + } + + HwiP_restore(key); +} + +/* + * ======== Watchdog_open ======== + */ +Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params) +{ + Watchdog_Handle handle = NULL; + + /* Verify driver index and state */ + if (isInitialized && (index < Watchdog_count)) + { + /* If params are NULL use defaults */ + if (params == NULL) + { + params = (Watchdog_Params *)&Watchdog_defaultParams; + } + + handle = (Watchdog_Handle) & (Watchdog_config[index]); + handle = handle->fxnTablePtr->watchdogOpen(handle, params); + } + + return (handle); +} + +/* + * ======== Watchdog_Params_init ======== + */ +void Watchdog_Params_init(Watchdog_Params *params) +{ + *params = Watchdog_defaultParams; +} + +/* + * ======== Watchdog_setReload ======== + */ +int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks) +{ + return (handle->fxnTablePtr->watchdogSetReload(handle, ticks)); +} + +/* + * ======== Watchdog_convertMsToTicks ======== + */ +uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds) +{ + return (handle->fxnTablePtr->watchdogConvertMsToTicks(handle, milliseconds)); +} diff --git a/simplelink_lpf2/source/ti/drivers/Watchdog.h b/simplelink_lpf2/source/ti/drivers/Watchdog.h new file mode 100644 index 00000000..b1b3027c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/Watchdog.h @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file Watchdog.h + * + * @brief Watchdog driver interface + * + * @anchor ti_drivers_Watchdog_Overview + * # Overview # + * + * A watchdog timer can be used to generate a reset signal if a system has + * become unresponsive. The Watchdog driver simplifies configuring and + * starting the watchdog peripherals. The watchdog peripheral can be + * configured with resets either on or off and a user-specified timeout + * period. + * + * When the watchdog peripheral is configured not to generate a reset, it + * can be used to cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a user-provided callback + * function that is called when the watchdog causes an interrupt. + * + * The Watchdog driver simplifies configuring and starting the Watchdog + * peripherals. The Watchdog can be set up to produce a reset signal after a + * timeout, or simply cause a hardware interrupt at a programmable interval. + * The driver provides the ability to specify a callback function that is + * called when the Watchdog causes an interrupt. + * + * When resets are turned on, it is the user application's responsibility to + * call Watchdog_clear() in order to clear the Watchdog and prevent a reset. + * Watchdog_clear() can be called at any time. + * + * @anchor ti_drivers_Watchdog_Usage + * # Usage # + * + * This section will cover driver usage. + * @anchor ti_drivers_Watchdog_Synopsis + * ## Synopsis # + * + * Open the driver with default settings: + * @code + * Watchdog_Handle watchdogHandle; + * + * Watchdog_init(); + * watchdogHandle = Watchdog_open(WATCHDOG_INDEX, NULL); + * if (watchdogHandle == NULL) { + * // Spin forever + * while(1); + * } + * @endcode + * + * The Watchdog driver must be initialized by calling Watchdog_init(), + * before any other Watchdog APIs can be called. + * Once the watchdog is initialized, a Watchdog object can be created + * through the following steps: + * - Create and initialize the #Watchdog_Params structure. + * - Assign desired values to parameters. + * - Call Watchdog_open(). + * - Save the Watchdog_Handle returned by Watchdog_open(). This will be + * used to interact with the Watchdog object just created. + * + * To have a user-defined function run at the hardware interrupt caused by + * a watchdog timer timeout, define a function of the following type: + * @code + * typedef void (*Watchdog_Callback)(uintptr_t); + * @endcode + * Then pass the function to Watchdog_open() through the #Watchdog_Params + * structure. + * + * An example of the Watchdog creation process that uses a callback + * function: + * @anchor ti_drivers_Watchdog_example_callback + * @code + * void UserCallbackFxn(Watchdog_Handle handle) + * { + * printf("Watchdog timer triggered!\n"); + * releaseResources(); + * } + * + * ... + * + * Watchdog_Params params; + * Watchdog_Handle watchdogHandle; + * + * Watchdog_init(); + * + * Watchdog_Params_init(¶ms); + * params.resetMode = Watchdog_RESET_ON; + * params.callbackFxn = (Watchdog_Callback) UserCallbackFxn; + * + * watchdogHandle = Watchdog_open(CONFIG_WATCHDOG0, ¶ms); + * if (watchdogHandle == NULL) { + * // Error opening Watchdog + * while (1); + * } + * + * @endcode + * + * If no #Watchdog_Params structure is passed to Watchdog_open(), the + * default values are used. By default, the Watchdog driver has resets + * turned on, no callback function specified, and stalls the timer at + * breakpoints during debugging. + * + * Options for the resetMode parameter are #Watchdog_RESET_ON and + * #Watchdog_RESET_OFF. The latter allows the watchdog to be used like + * another timer interrupt. When resetMode is #Watchdog_RESET_ON, it is up + * to the application to call Watchdog_clear() to clear the Watchdog + * interrupt flag to prevent a reset. Watchdog_clear() can be called at + * any time. + * + * @anchor ti_drivers_Watchdog_Examples + * # Examples + * - @ref ti_drivers_Watchdog_Synopsis "Default Example" + * - @ref ti_drivers_Watchdog_example_callback "Callback Function before watchdog reset" + * + * @anchor ti_drivers_Watchdog_Configuration + * # Configuration + * + * Refer to the @ref driver_configuration "Driver's Configuration" section + * for more information. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_Watchdog__include +#define ti_drivers_Watchdog__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup Watchdog_CONTROL Watchdog_control command and status codes + * These Watchdog macros are reservations for Watchdog.h + * @{ + */ + +/*! + * Common Watchdog_control command code reservation offset. + * Watchdog driver implementations should offset command codes with + * Watchdog_CMD_RESERVED growing positively + * + * Example implementation specific command codes: + * @code + * #define WatchdogXYZ_CMD_COMMAND0 Watchdog_CMD_RESERVED + 0 + * #define WatchdogXYZ_CMD_COMMAND1 Watchdog_CMD_RESERVED + 1 + * @endcode + */ +#define Watchdog_CMD_RESERVED (32) + +/*! + * Common Watchdog_control status code reservation offset. + * Watchdog driver implementations should offset status codes with + * Watchdog_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define WatchdogXYZ_STATUS_ERROR0 Watchdog_STATUS_RESERVED - 0 + * #define WatchdogXYZ_STATUS_ERROR1 Watchdog_STATUS_RESERVED - 1 + * #define WatchdogXYZ_STATUS_ERROR2 Watchdog_STATUS_RESERVED - 2 + * @endcode + */ +#define Watchdog_STATUS_RESERVED (-32) + +/** + * @defgroup Watchdog_STATUS Status Codes + * Watchdog_STATUS_* macros are general status codes returned by Watchdog_control() + * @{ + * @ingroup Watchdog_CONTROL + */ + +/*! + * @brief Successful status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_SUCCESS if the control code was + * executed successfully. + */ +#define Watchdog_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code returned by Watchdog_control(). + * + * Watchdog_control() returns Watchdog_STATUS_ERROR if the control code was not + * executed successfully. + */ +#define Watchdog_STATUS_ERROR (-1) + +/*! + * @brief An error status code returned by Watchdog_control() for undefined + * command codes. + * + * Watchdog_control() returns Watchdog_STATUS_UNDEFINEDCMD if the control code + * is not recognized by the driver implementation. + */ +#define Watchdog_STATUS_UNDEFINEDCMD (-2) + +/*! + * @brief An error status code returned by Watchdog_setReload() for drivers + * which do not support the aforementioned API. + * + * Watchdog_setReload() returns Watchdog_STATUS_UNSUPPORTED if the driver + * implementation does not support the aforementioned API. + */ +#define Watchdog_STATUS_UNSUPPORTED (-3) +/** @}*/ + +/** + * @defgroup Watchdog_CMD Command Codes + * Watchdog_CMD_* macros are general command codes for Watchdog_control(). Not all Watchdog + * driver implementations support these command codes. + * @{ + * @ingroup Watchdog_CONTROL + */ + +/* Add Watchdog_CMD_ here */ + +/** @}*/ + +/** @}*/ + +/*! + * @brief Watchdog Handle + */ +typedef struct Watchdog_Config_ *Watchdog_Handle; + +/*! + * @brief Watchdog debug stall settings + * + * This enumeration defines the debug stall modes for the Watchdog. On some + * targets, the Watchdog timer will continue to count down while a debugging + * session is halted. To avoid unwanted resets, the Watchdog can be set to + * stall while the processor is stopped by the debugger. + */ +typedef enum +{ + Watchdog_DEBUG_STALL_ON, /*!< Watchdog will be stalled at breakpoints */ + Watchdog_DEBUG_STALL_OFF /*!< Watchdog will keep running at breakpoints */ +} Watchdog_DebugMode; + +/*! + * @brief Watchdog reset mode settings + * + * This enumeration defines the reset modes for the Watchdog. The Watchdog can + * be configured to either generate a reset upon timeout or simply produce a + * periodic interrupt. + */ +typedef enum +{ + Watchdog_RESET_OFF, /*!< Timeouts generate interrupts only */ + Watchdog_RESET_ON /*!< Generates reset after timeout */ +} Watchdog_ResetMode; + +/*! + * @brief Watchdog callback pointer + * + * This is the typedef for the function pointer that will allow a callback + * function to be specified in the #Watchdog_Params structure. The function + * will take a #Watchdog_Handle of the Watchdog causing the interrupt (cast as + * a uintptr_t) as an argument. + */ +typedef void (*Watchdog_Callback)(uintptr_t handle); + +/*! + * @brief Watchdog Parameters + * + * Watchdog parameters are used to with the Watchdog_open() call. Default + * values for these parameters are set using Watchdog_Params_init(). + * + * @sa Watchdog_Params_init() + */ +typedef struct +{ + Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /*!< Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. + Not supported on all targets. */ + void *custom; /*!< Custom argument used by driver + implementation */ +} Watchdog_Params; + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_clear(). + */ +typedef void (*Watchdog_ClearFxn)(Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_close(). + */ +typedef void (*Watchdog_CloseFxn)(Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_control(). + */ +typedef int_fast16_t (*Watchdog_ControlFxn)(Watchdog_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_init(). + */ +typedef void (*Watchdog_InitFxn)(Watchdog_Handle handle); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_open(). + */ +typedef Watchdog_Handle (*Watchdog_OpenFxn)(Watchdog_Handle handle, Watchdog_Params *params); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_setReload(). + */ +typedef int_fast16_t (*Watchdog_SetReloadFxn)(Watchdog_Handle handle, uint32_t ticks); + +/*! + * @brief A function pointer to a driver specific implementation of + * Watchdog_ConvertMsToTicksFxn(). + */ +typedef uint32_t (*Watchdog_ConvertMsToTicksFxn)(Watchdog_Handle handle, uint32_t milliseconds); + +/*! + * @brief The definition of a Watchdog function table that contains the + * required set of functions to control a specific Watchdog driver + * implementation. + */ +typedef struct +{ + Watchdog_ClearFxn watchdogClear; + Watchdog_CloseFxn watchdogClose; + Watchdog_ControlFxn watchdogControl; + Watchdog_InitFxn watchdogInit; + Watchdog_OpenFxn watchdogOpen; + Watchdog_SetReloadFxn watchdogSetReload; + Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; +} Watchdog_FxnTable; + +/*! + * @brief Watchdog Global configuration + * + * The Watchdog_Config structure contains a set of pointers used to + * characterize the Watchdog driver implementation. + * + * This structure needs to be defined before calling Watchdog_init() and + * it must not be changed thereafter. + * + * @sa Watchdog_init() + */ +typedef struct Watchdog_Config_ +{ + /*! + * Pointer to a table of driver-specific implementations of Watchdog APIs + */ + Watchdog_FxnTable const *fxnTablePtr; + + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} Watchdog_Config; + +/*! + * @brief Clears the Watchdog + * + * Clears the Watchdog to to prevent a reset signal from being generated if the + * module is in #Watchdog_RESET_ON reset mode. + * + * @param handle A #Watchdog_Handle + */ +extern void Watchdog_clear(Watchdog_Handle handle); + +/*! + * @brief Function to close a Watchdog peripheral specified by the Watchdog + * handle.It stops (holds) the Watchdog counting on applicable + * platforms. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A #Watchdog_Handle returned from Watchdog_open() + * + * @sa Watchdog_open() + */ +extern void Watchdog_close(Watchdog_Handle handle); + +/*! + * @brief Function performs implementation specific features on a given + * #Watchdog_Handle. + * + * Commands for Watchdog_control can originate from Watchdog.h or from implementation + * specific Watchdog*.h files. + * While commands from Watchdog.h are API portable across driver implementations, + * not all implementations may support all these commands. + * Conversely, commands from driver implementation specific Watchdog*.h files add + * unique driver capabilities but are not API portable across all Watchdog driver + * implementations. + * + * Commands supported by Watchdog.h follow a Watchdog_CMD_\ naming + * convention.
+ * Commands supported by Watchdog*.h follow a Watchdog*_CMD_\ naming + * convention.
+ * Each control command defines @b arg differently. The types of @b arg are + * documented with each command. + * + * See @ref Watchdog_CMD "Watchdog_control command codes" for command codes. + * + * See @ref Watchdog_STATUS "Watchdog_control return status codes" for status codes. + * + * @pre Watchdog_open() has to be called first. + * + * @param handle A #Watchdog_Handle returned from Watchdog_open() + * + * @param cmd Watchdog.h or Watchdog*.h commands. + * + * @param arg An optional R/W (read/write) command argument + * accompanied with cmd + * + * @return Implementation specific return codes. Negative values indicate + * unsuccessful operations. + * + * @sa Watchdog_open() + */ +extern int_fast16_t Watchdog_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg); + +/*! + * @brief Initializes the Watchdog module + * + * The application-provided Watchdog_config must be present before the + * Watchdog_init() function is called. The Watchdog_config must be persistent + * and not changed after Watchdog_init is called. This function must be called + * before any of the other Watchdog driver APIs. + */ +extern void Watchdog_init(void); + +/*! + * @brief Opens a Watchdog + * + * Opens a Watchdog object with the index and parameters specified, and + * returns a #Watchdog_Handle. + * + * @param index Logical peripheral number for the Watchdog indexed + * into the Watchdog_config table + * + * @param params Pointer to a #Watchdog_Params, if NULL it will use + * default values. All the fields in this structure are + * RO (read-only). + * + * @return A #Watchdog_Handle on success or a NULL on an error or if it has + * been opened already. + * + * @sa Watchdog_init() + * @sa Watchdog_close() + */ +extern Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params); + +/*! + * @brief Function to initialize the #Watchdog_Params structure to its defaults + * + * @param params An pointer to #Watchdog_Params structure for + * initialization + * + * Default parameters: + * callbackFxn = NULL + * resetMode = #Watchdog_RESET_ON + * debugStallMode = #Watchdog_DEBUG_STALL_ON + */ +extern void Watchdog_Params_init(Watchdog_Params *params); + +/*! + * @brief Sets the Watchdog reload value + * + * Sets the value from which the Watchdog will countdown after it reaches + * zero. This is how the reload value can be changed after the Watchdog has + * already been opened. The new reload value will be loaded into the Watchdog + * timer when this function is called. Watchdog_setReload is not reentrant. + * For CC13XX/CC26XX, if the parameter 'ticks' is set to zero (0), a Watchdog + * interrupt is immediately generated. + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle A #Watchdog_Handle + * + * @param ticks Value to be loaded into Watchdog timer + * Unit is in Watchdog clock ticks + * + * @return #Watchdog_STATUS_SUCCESS on success, #Watchdog_STATUS_UNSUPPORTED + * if driver does not support this API. + */ +extern int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks); + +/*! + * @brief Converts milliseconds to Watchdog clock ticks + * + * Converts the input value into number of Watchdog clock ticks as close as + * possible. If the converted value exceeds 32 bits, a zero (0) will be + * returned to indicate overflow. The converted value can be used as the + * function parameter 'ticks' in Watchdog_setReload(). + * + * This API is not applicable for all platforms. See the page for your + * specific driver implementation for details. + * + * @param handle A #Watchdog_Handle + * + * @param milliseconds Value to be converted + * + * @return Converted value in number of Watchdog clock ticks + * A value of zero (0) means the converted value exceeds 32 bits + * or that the operation is not supported for the specific device. + * + * @sa Watchdog_setReload() + */ +extern uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Watchdog__include */ diff --git a/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.c b/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.c new file mode 100644 index 00000000..46248456 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.c @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2016-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ +#endif + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCCC26XX_close(ADC_Handle handle); +void ADCCC26XX_init(ADC_Handle handle); +ADC_Handle ADCCC26XX_open(ADC_Handle handle, ADC_Params *params); +int_fast16_t ADCCC26XX_convert(ADC_Handle handle, uint16_t *value); +int_fast16_t ADCCC26XX_convertChain(ADC_Handle *handleList, uint16_t *dataBuffer, uint8_t channelCount); +int_fast16_t ADCCC26XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg); +uint32_t ADCCC26XX_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADC function table for ADCCC26XX implementation */ +const ADC_FxnTable ADCCC26XX_fxnTable = {ADCCC26XX_close, + ADCCC26XX_control, + ADCCC26XX_convert, + ADCCC26XX_convertChain, + ADCCC26XX_convertToMicroVolts, + ADCCC26XX_init, + ADCCC26XX_open}; + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Keep track of the adc handle instance to create and delete adcSemaphore */ +static uint16_t adcInstance = 0; + +/* Semaphore to arbitrate access to the single ADC peripheral between multiple handles */ +static SemaphoreP_Struct adcSemaphore; + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCCC26XX_close ======== + */ +void ADCCC26XX_close(ADC_Handle handle) +{ + ADCCC26XX_HWAttrs const *hwAttrs; + ADCCC26XX_Object *object; + + DebugP_assert(handle); + + object = handle->object; + hwAttrs = handle->hwAttrs; + + uint32_t key = HwiP_disable(); + + if (object->isOpen) + { + adcInstance--; + if (adcInstance == 0) + { + SemaphoreP_destruct(&adcSemaphore); + } + + /* Deallocate pins */ + GPIO_resetConfig(hwAttrs->adcDIO); + DebugP_log0("ADC: Object closed"); + } + object->isOpen = false; + HwiP_restore(key); +} + +/* + * ======== ADCCC26XX_control ======== + */ +int_fast16_t ADCCC26XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg) +{ + /* No implementation yet */ + return ADC_STATUS_UNDEFINEDCMD; +} + +/* + * ======== ADCCC26XX_convert ======== + */ +int_fast16_t ADCCC26XX_convert(ADC_Handle handle, uint16_t *value) +{ + ADCCC26XX_HWAttrs const *hwAttrs; + ADCCC26XX_Object *object; + int_fast16_t conversionResult = ADC_STATUS_ERROR; + uint16_t conversionValue = 0; + uint32_t interruptStatus = 0; + + DebugP_assert(handle); + + /* Get handle */ + hwAttrs = handle->hwAttrs; + + /* Get the object */ + object = handle->object; + + if (object->isProtected) + { + /* Acquire the lock for this particular ADC handle */ + SemaphoreP_pend(&adcSemaphore, SemaphoreP_WAIT_FOREVER); + } + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Acquire the ADC hw semaphore. Return an error if the hw semaphore is not + * available. There is only one interrupt available for the hw semaphores + * and it is used by the TDC already. Busy-wait polling might lock up the + * device and starting timeout clocks would add overhead and be clunky. It + * is better if such functionality is implemented at application level + * if desired. + */ + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) + { + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + if (object->isProtected) + { + SemaphoreP_post(&adcSemaphore); + } + return conversionResult; + } + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcCompBInput); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!hwAttrs->inputScalingEnabled) + { + AUXADCDisableInputScaling(); + } + + /* Use synchronous sampling mode and prepare for trigger */ + AUXADCEnableSync(hwAttrs->refSource, hwAttrs->samplingDuration, hwAttrs->triggerSource); + + /* Manually trigger the ADC once */ + AUXADCGenManualTrigger(); + + /* Poll until the sample is ready */ + conversionValue = AUXADCReadFifo(); + + /* Get the status of the ADC_IRQ line and ADC_DONE. + * Despite not using the interrupt line, we need to clear it so that the + * ADCBuf driver does not call Hwi_construct and have the interrupt fire + * immediately. + */ + interruptStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & + (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + + /* Clear the ADC_IRQ flag in AUX_EVTCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = interruptStatus; + + /* Clear the ADC_IRQ within the NVIC as AUX_EVTCTL will only set the + * relevant flag in the NVIC it will not clear it. + */ + HwiP_clearInterrupt(INT_AUX_ADC_IRQ); + + conversionResult = ADC_STATUS_SUCCESS; + + /* Shut down the ADC peripheral */ + AUXADCDisable(); + + /* Release the ADC hw semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + + /* Allow entering standby again after ADC conversion complete */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->isProtected) + { + /* Release the lock for this particular ADC handle */ + SemaphoreP_post(&adcSemaphore); + } + + /* If we want to return the trimmed value, calculate it here. */ + if (hwAttrs->returnAdjustedVal) + { + uint32_t gain = AUXADCGetAdjustmentGain(hwAttrs->refSource); + uint32_t offset = AUXADCGetAdjustmentOffset(hwAttrs->refSource); + conversionValue = AUXADCAdjustValueForGainAndOffset(conversionValue, gain, offset); + } + + *value = conversionValue; + + /* Return the status-code of the conversion */ + return conversionResult; +} + +/* + * ======== ADCCC26XX_convertChain ======== + */ +int_fast16_t ADCCC26XX_convertChain(ADC_Handle *handleList, uint16_t *dataBuffer, uint8_t channelCount) +{ + ADCCC26XX_HWAttrs const *hwAttrs; + int_fast16_t conversionResult = ADC_STATUS_ERROR; + uint16_t conversionValue = 0; + uint8_t i; + uint32_t gain = 1; + uint32_t offset = 0; + + /* Use the first handle in the list to set the sampling mode and + * prepare the trigger for the entire conversion chain. This means that + * we are effectively ignoring the attributes of the other handles since + * we expect them to be the same. + */ + hwAttrs = handleList[0]->hwAttrs; + + /* Acquire the lock used arbitrate access to the ADC peripheral + * between multiple handles. + */ + SemaphoreP_pend(&adcSemaphore, SemaphoreP_WAIT_FOREVER); + + /* Try to acquire the ADC hw semaphore. */ + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) + { + SemaphoreP_post(&adcSemaphore); + return conversionResult; + } + + /* Flush the ADC FIFO since we have triggered the ADC prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!hwAttrs->inputScalingEnabled) + { + AUXADCDisableInputScaling(); + } + + /* Use synchronous sampling mode and prepare for trigger */ + AUXADCEnableSync(hwAttrs->refSource, hwAttrs->samplingDuration, hwAttrs->triggerSource); + + /* Calculate gain and offset in case we want to return a trimmed value */ + if (hwAttrs->returnAdjustedVal) + { + gain = AUXADCGetAdjustmentGain(hwAttrs->refSource); + offset = AUXADCGetAdjustmentOffset(hwAttrs->refSource); + } + + for (i = 0; i < channelCount; i++) + { + + /* Get the particular handle */ + hwAttrs = handleList[i]->hwAttrs; + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcCompBInput); + + /* Manually trigger the ADC once */ + AUXADCGenManualTrigger(); + + /* Poll until the sample is ready */ + conversionValue = AUXADCReadFifo(); + + /* If necessary, adjust value for gain and offset */ + if (hwAttrs->returnAdjustedVal) + { + conversionValue = AUXADCAdjustValueForGainAndOffset(conversionValue, gain, offset); + } + dataBuffer[i] = conversionValue; + } + + /* Clear the ADC_IRQ and ADC_DONE flags in AUX_EVTCTL. + * We need to clear it so that the ADCBuf driver does not call + * Hwi_construct and have the interrupt fire immediately.*/ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | + AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + + /* Clear the ADC_IRQ within the NVIC as AUX_EVTCTL will only set the + * relevant flag in the NVIC it will not clear it. + */ + HwiP_clearInterrupt(INT_AUX_ADC_IRQ); + + /* Shut down the ADC peripheral.*/ + AUXADCDisable(); + + /* Release the ADC hw semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + + conversionResult = ADC_STATUS_SUCCESS; + + /* Release the lock used arbitrate access to the single ADC peripheral + * between multiple handles. + */ + SemaphoreP_post(&adcSemaphore); + + /* Return the status-code of the conversion */ + return conversionResult; +} + +/* + * ======== ADCCC26XX_convertToMicroVolts ======== + */ +uint32_t ADCCC26XX_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue) +{ + ADCCC26XX_HWAttrs const *hwAttrs; + uint32_t adjustedValue; + + DebugP_assert(handle); + + /* Get the pointer to the hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* If returnAdjustedVal is set, the raw value has already been adjusted by convert-function. + * If not, we need to adjust it here. (This is why the logic here appears inverted) + */ + if (hwAttrs->returnAdjustedVal) + { + adjustedValue = adcValue; + } + else + { + uint32_t gain = AUXADCGetAdjustmentGain(hwAttrs->refSource); + uint32_t offset = AUXADCGetAdjustmentOffset(hwAttrs->refSource); + adjustedValue = AUXADCAdjustValueForGainAndOffset(adcValue, gain, offset); + } + + if (hwAttrs->refSource == ADCCC26XX_FIXED_REFERENCE) + { + return AUXADCValueToMicrovolts((hwAttrs->inputScalingEnabled ? AUXADC_FIXED_REF_VOLTAGE_NORMAL + : AUXADC_FIXED_REF_VOLTAGE_UNSCALED), + adjustedValue); + } + else + { + return AUXADCValueToMicrovolts(hwAttrs->refVoltage, adjustedValue); + } +} + +/* + * ======== ADCCC26XX_init ======== + */ +void ADCCC26XX_init(ADC_Handle handle) +{ + ADCCC26XX_Object *object; + + /* Get the object */ + object = handle->object; + + /* Mark the object as available */ + object->isOpen = false; +} + +/* + * ======== ADCCC26XX_open ======== + */ +ADC_Handle ADCCC26XX_open(ADC_Handle handle, ADC_Params *params) +{ + ADCCC26XX_Object *object; + ADCCC26XX_HWAttrs const *hwAttrs; + + DebugP_assert(handle); + + /* Get object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Determine if the driver was already opened */ + uint32_t key = HwiP_disable(); + + if (object->isOpen) + { + DebugP_log0("ADC: Error! Already in use."); + HwiP_restore(key); + return NULL; + } + object->isOpen = true; + + /* Remember thread safety protection setting */ + object->isProtected = params->isProtected; + + /* If this is the first handle requested, set up the semaphore as well */ + if (adcInstance == 0) + { + /* Setup semaphore */ + SemaphoreP_constructBinary(&adcSemaphore, 1); + } + adcInstance++; + + /* On Chameleon, ANAIF must be clocked to use it. On Agama, the register + * interface is always available. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + /* Turn on the ANAIF clock. ANIAF contains the aux ADC. */ + AUXWUCClockEnable(AUX_WUC_ANAIF_CLOCK); + AUXWUCClockEnable(AUX_WUC_ADI_CLOCK); +#endif + + HwiP_restore(key); + + /* Reserve the DIO defined in the hwAttrs */ + GPIO_setConfig(hwAttrs->adcDIO, GPIO_CFG_NO_DIR); + + DebugP_log0("ADC: Object opened"); + + return handle; +} diff --git a/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.h b/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.h new file mode 100644 index 00000000..fc4ff22b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adc/ADCCC26XX.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCCC26XX.h + * @brief ADC driver implementation for the ADC peripheral on CC26XX + * + * This ADC driver implementation is designed to operate on a ADC peripheral + * for CC26XX. + * + * Refer to @ref ADC.h for a complete description of APIs & example of use. + * + ****************************************************************************** + */ +#ifndef ti_drivers_adc_ADCCC26XX__include +#define ti_drivers_adc_ADCCC26XX__include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the + * CC26XX ADC, the sampling and conversion phases. During the sampling phase, + * the ADC samples the analogue input signal. The duration of the sampling + * phase is configurable. Larger input loads require longer sample times for + * the most accurate results. + */ +typedef enum +{ + ADCCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCCC26XX_Sampling_Duration; + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from + * the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper + * range of the ADC to a fixed value. That value is 4.3V with input scaling + * enabled and ~1.4785V with input scaling disabled. In this mode, the output + * is a function of the input voltage multiplied by the resolution in + * alternatives (not bits) divided by the upper voltage range of the ADC. + * Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the + * battery voltage. As the battery depletes and its voltage drops, so does the + * range of the ADC. This is helpful when measuring signals that are generated + * relative to the battery voltage. In this mode, the output is a function of + * the input voltage multiplied by the resolution in alternatives (not bits) + * divided by VDDS multiplied by a scaling factor derived from the input + * scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), where the + * scaling factor is ~1.4785/4.3 for input scaling disabled and 1 for input + * scaling enabled. + * + * @note The actual reference values are slightly different for each device + * and are higher than the values specified above. This gain is saved + * in the FCFG. The function ::ADC_convertToMicroVolts() must be used + * to derive actual voltage values. Do not attempt to compare raw + * values between devices or derive a voltage from them yourself. The + * results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in + * fixed mode with input scaling enabled, the input should never + * exceed VDDS as per the data sheet. + */ +typedef enum +{ + ADCCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCCC26XX_Reference_Source; + +/*! + * @brief List of sources the ADC can be configured to trigger off of. + * + * The ADC driver currently only supports the driver manually triggering a + * conversion. Support for other trigger sources may be added later. + */ +typedef enum +{ + ADCCC26XX_TRIGGER_MANUAL = AUXADC_TRIGGER_MANUAL, +} ADCCC26XX_Trigger_Source; + +/* ADC function table pointer */ +extern const ADC_FxnTable ADCCC26XX_fxnTable; + +/*! + * @brief ADCCC26XX Hardware attributes + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. + * + */ +typedef struct +{ + /*! DIO that the ADC is routed to */ + uint8_t adcDIO; + /*! Internal signal routed to comparator B */ + uint8_t adcCompBInput; + /*! Should the raw output be trimmed before returning it */ + bool returnAdjustedVal; + /*! Is input scaling enabled */ + bool inputScalingEnabled; + /*! Reference voltage in microvolts*/ + uint_fast32_t refVoltage; + /*! Reference source for the ADC to use */ + ADCCC26XX_Reference_Source refSource; + /*! Time the ADC spends sampling. This is load dependent */ + ADCCC26XX_Sampling_Duration samplingDuration; + /*! Source that the ADC triggers off of. Currently only supports AUXADC_TRIGGER_MANUAL */ + ADCCC26XX_Trigger_Source triggerSource; +} ADCCC26XX_HWAttrs; + +/*! + * @brief ADCCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /*! Flag if the instance is in use */ + bool isOpen; + /*! Flag to indicate if thread safety is ensured by the driver */ + bool isProtected; +} ADCCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.c b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.c new file mode 100644 index 00000000..43e3a0f7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.c @@ -0,0 +1,1021 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(inc/hw_event.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCBufCC26X2_init(ADCBuf_Handle handle); +ADCBuf_Handle ADCBufCC26X2_open(ADCBuf_Handle handle, const ADCBuf_Params *params); +int_fast16_t ADCBufCC26X2_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); +int_fast16_t ADCBufCC26X2_convertCancel(ADCBuf_Handle handle); +void ADCBufCC26X2_close(ADCBuf_Handle handle); +uint_fast8_t ADCBufCC26X2_getResolution(ADCBuf_Handle handle); +int_fast16_t ADCBufCC26X2_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); +int_fast16_t ADCBufCC26X2_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); +int_fast16_t ADCBufCC26X2_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ +static bool ADCBufCC26X2_acquireADCSemaphore(ADCBuf_Handle handle); +static bool ADCBufCC26X2_releaseADCSemaphore(ADCBuf_Handle handle); +static void ADCBufCC26X2_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26X2_hwiFxn(uintptr_t arg); +static void ADCBufCC26X2_swiFxn(uintptr_t arg0, uintptr_t arg1); +static void ADCBufCC26X2_conversionCallback(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel, + int_fast16_t status); +static uint32_t ADCBufCC26X2_freqToCounts(uint32_t frequency); +static void ADCBufCC26X2_cleanADC(ADCBuf_Handle handle); +static void ADCBufCC26X2_loadDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry); + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +const ADCBuf_FxnTable ADCBufCC26X2_fxnTable = { + /*! Function to close the specified peripheral */ + ADCBufCC26X2_close, + /*! Function to driver implementation specific control function */ + ADCBufCC26X2_control, + /*! Function to initialize the given data object */ + ADCBufCC26X2_init, + /*! Function to open the specified peripheral */ + ADCBufCC26X2_open, + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBufCC26X2_convert, + /*! Function to abort a conversion being carried out by the specified peripheral */ + ADCBufCC26X2_convertCancel, + /*! Function to get the resolution in bits of the ADC */ + ADCBufCC26X2_getResolution, + /*! Function to adjust raw ADC output values to values comparable between + * devices of the same type */ + ADCBufCC26X2_adjustRawValues, + /*! Function to convert adjusted ADC values to microvolts */ + ADCBufCC26X2_convertAdjustedToMicroVolts}; + +/* Default ADCBuf parameters structure */ +const ADCBufCC26X2_ParamsExtension ADCBufCC26X2_defaultParamsExtension = { + .samplingDuration = ADCBufCC26X2_SAMPLING_DURATION_2P7_US, + .samplingMode = ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS, + .refSource = ADCBufCC26X2_FIXED_REFERENCE, + .inputScalingEnabled = true, +}; + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Allocate space for DMA control table entry */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCPriControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCAltControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_ALT_SELECT)); + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCBufCC26X2_init ======== + */ +void ADCBufCC26X2_init(ADCBuf_Handle handle) +{ + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + /* Mark the object as available */ + object->isOpen = false; +} + +/* + * ======== ADCBufCC26X2_open ======== + */ +ADCBuf_Handle ADCBufCC26X2_open(ADCBuf_Handle handle, const ADCBuf_Params *params) +{ + /* Use union to save on stack allocation */ + union + { + HwiP_Params hwiParams; + SwiP_Params swiParams; + GPTimerCC26XX_Params timerParams; + } paramsUnion; + ADCBufCC26X2_Object *object; + ADCBufCC26X2_HWAttrs const *hwAttrs; + uint32_t key; + uint32_t adcPeriodCounts; + uint32_t gptConfig; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the ADC is open. */ + key = HwiP_disable(); + + /* Check if the ADC is open already with the base addr. */ + if (object->isOpen == true) + { + HwiP_restore(key); + + DebugP_log0("ADCBuf: already in use."); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + + HwiP_restore(key); + + /* Initialise the ADC object */ + /* Initialise params section of object */ + object->conversionInProgress = false; + object->semaphoreTimeout = params->blockingTimeout; + object->samplingFrequency = params->samplingFrequency; + object->returnMode = params->returnMode; + object->recurrenceMode = params->recurrenceMode; + object->keepADCSemaphore = false; + object->adcSemaphoreInPossession = false; + + if (params->custom) + { + /* If CC26X2 specific params were specified, use them */ + object->samplingDuration = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->samplingDuration; + object->refSource = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->refSource; + object->samplingMode = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->samplingMode; + object->inputScalingEnabled = ((ADCBufCC26X2_ParamsExtension *)(params->custom))->inputScalingEnabled; + } + else + { + /* Initialise CC26X2 specific settings to defaults */ + object->inputScalingEnabled = true; + object->refSource = ADCBufCC26X2_FIXED_REFERENCE; + object->samplingMode = ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS; + object->samplingDuration = ADCBufCC26X2_SAMPLING_DURATION_2P7_US; + } + + if (hwAttrs->acquireADCSem) + { + /* Acquire ADC semaphore */ + if (!ADCBufCC26X2_acquireADCSemaphore(handle)) + { + /* We were not able to acquire the ADC semaphore */ + DebugP_log0("ADC: semaphore could not be acquired during open()"); + object->isOpen = false; + return NULL; + } + } + + /* Open timer resource */ + GPTimerCC26XX_Params_init(¶msUnion.timerParams); + paramsUnion.timerParams.width = GPT_CONFIG_16BIT; + paramsUnion.timerParams.mode = GPT_MODE_PERIODIC_UP; + paramsUnion.timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + object->timerHandle = GPTimerCC26XX_open(hwAttrs->gpTimerUnit, ¶msUnion.timerParams); + + if (object->timerHandle == NULL) + { + /* We did not manage to open the GPTimer we wanted */ + object->isOpen = false; + return NULL; + } + + /* Enable capture toggle event on timeout. The ADC will trigger a + conversion on the rising edge of the event pulse. */ + gptConfig = HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_TAMR); + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_TAMR) = (gptConfig & 0xFF) | GPT_TAMR_TCACT_TOG_ON_TO; + + /* Calculate period count for the GPT using double the sample frequency. + The GPT need to generate two events each ADC period to create + the trigger pulse. */ + adcPeriodCounts = ADCBufCC26X2_freqToCounts(params->samplingFrequency * 2); + GPTimerCC26XX_setLoadValue(object->timerHandle, adcPeriodCounts); + + if (params->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + /* Continuous trigger mode and blocking return mode is an illegal combination */ + DebugP_assert(!(params->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS)); + + /* Create a semaphore to block task execution for the duration of the + * ADC conversions */ + SemaphoreP_constructBinary(&(object->conversionComplete), 0); + + /* Store internal callback function */ + object->callbackFxn = ADCBufCC26X2_conversionCallback; + } + else + { + /* Callback mode without a callback function defined */ + DebugP_assert(params->callbackFxn); + + /* Save the callback function pointer */ + object->callbackFxn = params->callbackFxn; + } + + /* Check if the ADC data interface is already enabled - if so, then a + * previous configuration was halted without cleanly disabling the ADC */ + if (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) && AUX_ANAIF_ADCCTL_CMD_EN) + { + /* Disable the ADC and disable UDMA mode for ADC */ + AUXADCDisable(); + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | + AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + } + + /* Clear the event flags to prevent an immediate interrupt from a previous + * configuration */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | + AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + HwiP_clearInterrupt(INT_AUX_ADC_IRQ); + + /* Create the Hwi for this ADC peripheral. */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_AUX_ADC_IRQ, ADCBufCC26X2_hwiFxn, ¶msUnion.hwiParams); + + /* Create the Swi object for this ADC peripheral */ + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), ADCBufCC26X2_swiFxn, &(paramsUnion.swiParams)); + + /* Declare the dependency on the UDMA driver */ + object->udmaHandle = UDMACC26XX_open(); + + /* Return the handle after finishing initialisation of the driver */ + DebugP_log0("ADC: opened"); + return handle; +} + +/* + * ======== ADCBufCC26X2_ParamsExtension_init ======== + */ +void ADCBufCC26X2_ParamsExtension_init(ADCBufCC26X2_ParamsExtension *params) +{ + *params = ADCBufCC26X2_defaultParamsExtension; +} + +/*! + * @brief HWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg An ADCBufCC26X2_Handle + * + */ +static void ADCBufCC26X2_hwiFxn(uintptr_t arg) +{ + ADCBufCC26X2_Object *object; + ADCBuf_Conversion *conversion; + uint32_t intStatus; + + /* Get the pointer to the object and current conversion*/ + object = ((ADCBuf_Handle)arg)->object; + conversion = object->currentConversion; + + /* Set activeSampleBuffer to primary as default */ + object->activeSampleBuffer = conversion->sampleBuffer; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + /* Disable the ADC */ + AUXADCDisable(); + /* Disable ADC DMA if we are only doing one conversion and clear DMA + * done interrupt. */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | + AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + } + else if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) + { + /* Reload the finished DMA control table entry */ + if (HWREG(UDMA0_BASE + UDMA_O_SETCHNLPRIALT) & (1 << UDMA_CHAN_AUX_ADC)) + { + /* We are currently using the alternate entry -> we just finished + * the primary entry -> reload primary entry */ + ADCBufCC26X2_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + } + else + { + /* We are currently using the primary entry -> we just finished the + * alternate entry -> reload the alternate entry */ + ADCBufCC26X2_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + object->activeSampleBuffer = conversion->sampleBufferTwo; + } + } + /* Clear DMA interrupts */ + UDMACC26XX_clearInterrupt(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC)); + + /* Get the status of the ADC_IRQ line and ADC_DONE */ + intStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & + (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + /* Clear the ADC_IRQ flag if it triggered the ISR */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = intStatus; + + /* Get the status of the ADC FIFO */ + intStatus = AUXADCGetFifoStatus(); + + /* Check for overflow/underflow events */ + if (intStatus & (AUXADC_FIFO_OVERFLOW_M | AUXADC_FIFO_UNDERFLOW_M)) + { + AUXADCFlushFifo(); + } + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); +} + +/*! + * @brief SWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg0 An ADCBufCC26X2_Handle + * + */ +static void ADCBufCC26X2_swiFxn(uintptr_t arg0, uintptr_t arg1) +{ + uint32_t key; + ADCBuf_Conversion *conversion; + ADCBufCC26X2_Object *object; + uint16_t *sampleBuffer; + uint8_t channel; + + /* Get the pointer to the object */ + object = ((ADCBuf_Handle)arg0)->object; + + DebugP_log0("ADC: swi interrupt context start"); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Use a temporary pointers in case the callback function + * attempts to perform another ADCBuf_transfer call + */ + conversion = object->currentConversion; + sampleBuffer = object->activeSampleBuffer; + channel = object->currentChannel; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + /* Clean up ADC and DMA */ + ADCBufCC26X2_cleanADC(((ADCBuf_Handle)arg0)); + /* Indicate we are done with this transfer */ + object->currentConversion = NULL; + } + + /* Restore interrupts */ + HwiP_restore(key); + + /* Perform callback */ + object->callbackFxn((ADCBuf_Handle)arg0, conversion, sampleBuffer, channel, ADCBuf_STATUS_SUCCESS); + + DebugP_log0("ADC: swi interrupt context end"); +} + +/*! + * @brief CC26X2 internal callback function that posts the semaphore in + * blocking mode + * + * @param handle An ADCBufCC26X2_Handle + * + * @param conversion A pointer to the current ADCBuf_Conversion + * + */ +static void ADCBufCC26X2_conversionCallback(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel, + int_fast16_t status) +{ + ADCBufCC26X2_Object *object; + + DebugP_log0("ADC DMA: posting conversionComplete semaphore"); + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->conversionComplete)); +} + +/* + * ======== ADCBufCC26X2_convert ======== + */ +int_fast16_t ADCBufCC26X2_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) +{ + uint32_t key; + ADCBufCC26X2_Object *object; + ADCBufCC26X2_HWAttrs const *hwAttrs; + ADCBufCC26X2_AdcChannelLutEntry channelLookup; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + channelLookup = hwAttrs->adcChannelLut[conversions->adcChannel]; + + DebugP_assert(channelCount == 1); + DebugP_assert((conversions->samplesRequestedCount <= UDMA_XFER_SIZE_MAX)); + DebugP_assert(conversions->sampleBuffer); + DebugP_assert(!(object->recurrenceMode == (ADCBuf_RECURRENCE_MODE_CONTINUOUS && !(conversions->sampleBufferTwo)))); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + /* Restore interrupts */ + HwiP_restore(key); + DebugP_log0("ADCBuf: conversion failed"); + return ADCBuf_STATUS_ERROR; + } + object->conversionInProgress = true; + + /* Restore interrupts*/ + HwiP_restore(key); + + /* Try to acquire the ADC semaphore if we do not already have it. */ + if (object->adcSemaphoreInPossession == false) + { + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) + { + object->conversionInProgress = false; + DebugP_log0("ADCBuf: failed to acquire semaphore"); + return ADCBuf_STATUS_ERROR; + } + object->adcSemaphoreInPossession = true; + } + + /* Specify input in ADC module */ + AUXADCSelectInput(channelLookup.compBInput); + + /* Save which channel we are converting on for the callbackFxn */ + object->currentChannel = conversions->adcChannel; + + /* Add pin to measure on */ + GPIO_setConfig(channelLookup.dio, GPIO_CFG_NO_DIR); + + /* Store location of the current conversion */ + object->currentConversion = conversions; + + /* Configure and arm the DMA and AUX DMA control */ + ADCBufCC26X2_configDMA(handle, conversions); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!object->inputScalingEnabled) + { + AUXADCDisableInputScaling(); + } + + /* Arm the ADC in preparation for incoming conversion triggers */ + if (object->samplingMode == ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS) + { + /* ADCBufCC26X2_SYNCHRONOUS sampling mode */ + AUXADCEnableSync(object->refSource, object->samplingDuration, AUXADC_TRIGGER_GPT0A_CMP); + } + else + { + /* ADCBufCC26X2_ASYNCHRONOUS sampling mode */ + AUXADCEnableAsync(object->refSource, AUXADC_TRIGGER_GPT0A_CMP); + } + + /* Start the GPTimer to create ADC triggers */ + GPTimerCC26XX_start(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + DebugP_log0("ADCBuf: transfer pending on conversionComplete " + "semaphore"); + + if (SemaphoreP_OK != SemaphoreP_pend(&(object->conversionComplete), object->semaphoreTimeout)) + { + /* Cancel the transfer if we experience a timeout */ + ADCBufCC26X2_convertCancel(handle); + /* + * ADCBufCC26X2_convertCancel performs a callback which posts a + * conversionComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(&(object->conversionComplete), SemaphoreP_NO_WAIT); + return ADCBuf_STATUS_ERROR; + } + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_convertCancel ======== + */ +int_fast16_t ADCBufCC26X2_convertCancel(ADCBuf_Handle handle) +{ + ADCBufCC26X2_Object *object; + ADCBuf_Conversion *conversion; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs*/ + object = handle->object; + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->conversionInProgress)) + { + DebugP_log0("ADCBuf: a conversion must be in progress to cancel one"); + return ADCBuf_STATUS_ERROR; + } + + /* Stop triggering a conversion on trigger events */ + AUXADCDisable(); + + /* Set hardware and software configuration to default and turn off driver */ + ADCBufCC26X2_cleanADC(handle); + + /* Use a temporary transaction pointer in case the callback function + * attempts to perform another ADCBuf_convert call + */ + conversion = object->currentConversion; + + /* Perform callback if we are in one-shot mode. In continuous mode, + * ADCBuf_convertCancel will probably be called from the callback function + * itself. No need to call it again. */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + object->callbackFxn(handle, + conversion, + conversion->sampleBuffer, + object->currentChannel, + ADCBuf_STATUS_SUCCESS); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_close ======== + */ +void ADCBufCC26X2_close(ADCBuf_Handle handle) +{ + ADCBufCC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Check if the ADC is running and abort conversion if necessary. */ + if (object->conversionInProgress) + { + ADCBuf_convertCancel(handle); + } + + /* Get the pointer to the object */ + object = handle->object; + + /* Release the uDMA dependency and potentially power down uDMA. */ + UDMACC26XX_close(object->udmaHandle); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Destroy the Swi */ + SwiP_destruct(&(object->swi)); + + /* Close the timer */ + GPTimerCC26XX_close(object->timerHandle); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + SemaphoreP_destruct(&(object->conversionComplete)); + } + + if (object->adcSemaphoreInPossession) + { + ADCBufCC26X2_releaseADCSemaphore(handle); + } + + /* Mark the module as available */ + object->isOpen = false; + + DebugP_log0("ADCBuf: closed"); +} + +/* + * ======== ADCBufCC26X2_getResolution ======== + */ +uint_fast8_t ADCBufCC26X2_getResolution(ADCBuf_Handle handle) +{ + return (ADCBufCC26X2_RESOLUTION); +} + +/* + * ======== ADCBufCC26X2_adjustRawValues ======== + */ +int_fast16_t ADCBufCC26X2_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel) +{ + ADCBufCC26X2_Object *object; + uint32_t gain; + uint32_t offset; + uint16_t i; + + object = handle->object; + + gain = AUXADCGetAdjustmentGain(object->refSource); + offset = AUXADCGetAdjustmentOffset(object->refSource); + + for (i = 0; i < sampleCount; i++) + { + uint16_t tmpRawADCVal = ((uint16_t *)sampleBuffer)[i]; + ((uint16_t *)sampleBuffer)[i] = AUXADCAdjustValueForGainAndOffset(tmpRawADCVal, gain, offset); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26X2_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBufCC26X2_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount) +{ + ADCBufCC26X2_Object *object; + uint16_t i; + uint32_t voltageRef; + + object = handle->object; + + voltageRef = (object->inputScalingEnabled) ? AUXADC_FIXED_REF_VOLTAGE_NORMAL : AUXADC_FIXED_REF_VOLTAGE_UNSCALED; + + for (i = 0; i < sampleCount; i++) + { + outputMicroVoltBuffer[i] = AUXADCValueToMicrovolts(voltageRef, ((uint16_t *)adjustedSampleBuffer)[i]); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/*! + * @brief Function to configure the DMA to automatically transfer ADC output + * data into a provided array + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26X2_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) +{ + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26X2_loadDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continuous mode, load the alternate DMA control + * table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) + { + ADCBufCC26X2_loadDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_AUX_ADC); + + /* Configure DMA settings in AUX_EVCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_EN | + AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + DebugP_log0("ADCBuf: DMA transfer enabled"); +} + +/*! + * @brief Function to configure the adc DMA control table entry for basic or + * ping pong mode + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate + * control table entry + * + */ +static void ADCBufCC26X2_loadDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry) +{ + ADCBufCC26X2_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + uint32_t numberOfBytes; + + /* Get the pointer to the object*/ + object = handle->object; + + /* Calculate the number of bytes for the transfer */ + numberOfBytes = (uint16_t)(conversion->samplesRequestedCount) * ADCBufCC26X2_BYTES_PER_SAMPLE; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaADCPriControlTableEntry : &dmaADCAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + ? UDMA_MODE_BASIC + : UDMA_MODE_PINGPONG) | + UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(primaryEntry ? conversion->sampleBuffer + : conversion->sampleBufferTwo) + + numberOfBytes - 1); + dmaControlTableEntry->pvSrcEndAddr = (void *)(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +/*! + * @brief Function to undo all configurations done by the ADC driver + * + * @pre ADCBuf_open() has to be called first. + * + * @pre ADCBuf_convert() has to be called first. + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static void ADCBufCC26X2_cleanADC(ADCBuf_Handle handle) +{ + ADCBufCC26X2_Object *object; + ADCBufCC26X2_HWAttrs const *hwAttrs; + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Stop the timer to stop generating triggers */ + GPTimerCC26XX_stop(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->adcSemaphoreInPossession && !object->keepADCSemaphore) + { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Disable the UDMA channels */ + UDMACC26XX_channelDisable(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC)); + + /* Deallocate conversion pin */ + GPIO_resetConfig(hwAttrs->adcChannelLut[object->currentChannel].dio); + + /* Disable UDMA mode for ADC */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + /* Note that the driver is no longer converting */ + object->conversionInProgress = false; +} + +/* Return period in timer counts */ +static uint32_t ADCBufCC26X2_freqToCounts(uint32_t frequency) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts = (freq.lo / frequency) - 1; + + return periodCounts; +} + +/*! + * @brief Function to acquire the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static bool ADCBufCC26X2_acquireADCSemaphore(ADCBuf_Handle handle) +{ + uint32_t key; + bool semaphoreAvailable; + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set semaphoreAvailable false at default */ + semaphoreAvailable = false; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + DebugP_log0("ADC: driver must be open and no conversion must be in " + "progress to disable input scaling"); + } + /* This is a non-blocking call to acquire the ADC semaphore. */ + else if (AUXSMPHTryAcquire(AUX_SMPH_2)) + { + object->adcSemaphoreInPossession = true; + semaphoreAvailable = true; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreAvailable; +} + +/*! + * @brief This function releases the ADC semaphore + * + * @pre ADCBufCC26X2_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26X2 handle returned from ADCBufCC26X2_open() + * + */ +static bool ADCBufCC26X2_releaseADCSemaphore(ADCBuf_Handle handle) +{ + uint32_t key; + bool semaphoreReleased; + ADCBufCC26X2_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set semaphoreReleased true at default */ + semaphoreReleased = true; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + DebugP_log0("ADC: driver must be open and no conversion must be in " + "progress to disable input scaling"); + semaphoreReleased = false; + } + else + { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreReleased; +} + +/* + * ======== ADCBufCC26X2_control ======== + */ +int_fast16_t ADCBufCC26X2_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg) +{ + ADCBufCC26X2_Object *object = handle->object; + int status = ADCBuf_STATUS_ERROR; + + DebugP_assert(handle); + + switch (cmd) + { + case ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE: + if (ADCBufCC26X2_acquireADCSemaphore(handle)) + { + status = ADCBuf_STATUS_SUCCESS; + } + break; + case ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE: + object->keepADCSemaphore = true; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE: + object->keepADCSemaphore = false; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE: + if (ADCBufCC26X2_releaseADCSemaphore(handle)) + { + status = ADCBuf_STATUS_SUCCESS; + } + break; + default: + status = ADCBuf_STATUS_UNDEFINEDCMD; + break; + } + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.h b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.h new file mode 100644 index 00000000..57517095 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26X2.h @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCBufCC26X2.h + * + * @brief ADCBuf driver implementation for a CC26X2 analog-to-digital converter + * + * # Driver include # + * The ADCBuf header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * # Overview # + * This is a CC26X2 specific implementation of the generic TI-RTOS ADCBuf + * driver. The generic ADCBuf API specified in ti/drivers/ADCBuf.h should be + * called by the application, not the device specific implementation in + * ti/drivers/adcbuf/ADCBufCC26X2. The board file defines the device specific + * configuration and casting in the general API ensures the correct device + * specific functions are called. You should specify an + * ADCBufCC26X2_ParamsExtension in the custom field of the ADCBuf_Params that + * suits your application. The default settings work for many, but not all, + * use cases. + * + * # General Behavior # + * A timer and the DMA are used to trigger the ADC and fill a buffer in the + * background (in hardware) at a specified frequency. The application may + * execute other tasks while the hardware handles the conversions. In contrast + * to the standard ti/drivers/ADC driver, this driver allows for precise + * sampling of waveforms. + * + * | Driver | Number of samples needed in one call | + * |----------------|-----------------------------------------| + * | ADC.h | 1 | + * | ADCBuf.h | > 1 | + * + * This ADCBuf driver provides an API interface to using the analog-to-digital + * converter directly from the CM3 without going through the sensor controller. + * The sensor controller can still use the ADC, support for sharing the ADC + * resource between the sensor controller and the CM3 is built into the driver. + * There is a hardware semaphore that the driver must acquire before beginning + * any number of conversions. This same hardware semaphore also prevents the + * simultaneous use of this driver and the basic ADC driver. + * + * The ADC drivers supports making between one and 1024 measurements once or + * continuous measuring with returned buffer sizes between one and 1024 + * measurements. + * + * The application should call ADCBuf_init() once by the application to set the + * isOpened flag to false, indicating that the driver is ready to use. + * + * The ADC driver is opened by calling ADCBuf_open() which will + * set up interrupts and configure the internal components of the driver. + * However, the ADC hardware or analog pins are not yet configured, since the + * sensor controller or basic ADC driver might be using the ADC. + * + * In order to perform an ADC conversion, the application should call + * ADCBuf_convert(). This call will request the ADC resource, configure the ADC, + * set up the DMA and GPTimer, and perform the requested ADC conversions on the + * selected DIO or internal signal. The DIO or internal signal is defined by the + * ADCBuf_Conversion structure in the application code and adcBufCC26x2Objects + * in the board file. + * + * @warning If the ADCBUF driver is setup in ADCBuf_RECURRENCE_MODE_CONTINUOUS + * mode, the user must assure that the provided callback function is + * completed before the next conversion completes. If the next + * conversion completes before the callback function finishes, the DMA + * will clobber the previous buffer with new data. + * + * If the sensor controller is using the ADC when the driver requests it at the + * start of the ADC_convert() call, the conversion will fail and return false. + * The ADC resource may be pre-acquired by calling the control function + * ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE. It will be released again + * automatically after the next conversion completes. + * + * In both ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS mode and + * ADCBufCC26X2_SAMPING_MODE_ASYNCHRONOUS mode, enough sampling time must be + * provided between conversions that each measurement may be completed before + * the next trigger arrives. + * + * @note The ADCBuf driver requires GPTimer0A to function correctly. It will + * be unavailable for other uses. + * + * # Supported ADC pins # + * Below is a table of the supported ADC IO pins for each package size, for both + * CC26x2 and CC13x2. It maps a DIO to its corresponding driverlib define for the + * CompBInput that it is hardwired to. This table can be used to create virtual + * channel entries in the ADCBufCC26X2_adcChannelLut table in the board file. + * + * | DIO | CC26x2 7x7 AUXIO CompBInput | CC13x2 7x7 AUXIO CompBInput + * |--------|-------------------------------|------------------------------- + * | 0 | No | No + * | 1 | No | No + * | 2 | No | No + * | 3 | No | No + * | 4 | No | No + * | 5 | No | No + * | 6 | No | No + * | 7 | No | No + * | 8 | No | No + * | 9 | No | No + * | 10 | No | No + * | 11 | No | No + * | 12 | No | No + * | 13 | No | No + * | 14 | No | No + * | 15-22 | No | No + * | 23 | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 + * | 24 | ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 + * | 25 | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 + * | 26 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 + * | 27 | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 + * | 28 | ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 + * | 29 | ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 + * | 30 | ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 + * + * # Supported Internal Signals # + * Below is a table of internal signals that can be measured using the ADC. + * Since we are not connecting to a DIO, there is no DIO to internal signal mapping. + * The DIO field in the channel lookup table should be marked GPIO_INVALID_INDEX. + * This table can be used to create virtual channel entries in the + * ADCBufCC26X2_adcChannelLut table in the board file. + * + * | DIO | Internal Signal CompBInput | + * |--------------------|-------------------------------| + * | GPIO_INVALID_INDEX | ADC_COMPB_IN_DCOUPL | + * | GPIO_INVALID_INDEX | ADC_COMPB_IN_VSS | + * | GPIO_INVALID_INDEX | ADC_COMPB_IN_VDDS | + * + * # Error handling # + * The following errors may occur when opening the ADC without assertions enabled: + * - The ADC handle is already open. + * + * The following errors may occur when requesting an ADC conversion: + * - The ADC is currently already doing a conversion. + * - The ADC was not available (used by sensor controller or basic ADC). + * + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the + * most power efficient mode whenever possible. Please see the technical + * reference manual for further details on each power mode. + * + * While converting, the ADCBufCC26X2 driver sets a power constraint to keep + * the device out of standby. When the conversion has finished, the power + * constraint is released. The driver also sets a dependency on the DMA to + * enable background transfers from the ADC FIFO to memory. + * The following statements are valid: + * - After ADCBuf_convert(): the device cannot enter standby. + * - After ADCBuf_convertCancel(): the device can enter standby again. + * - After a conversion finishes: the device can enter standby again. + * + * + * # Supported Functions # + * | API function | Description | + * |------------------------------------|-----------------------------------------------------------------------| + * | ADCBuf_init() | Initialize ADC driver | + * | ADCBuf_open() | Open the ADC driver and configure driver | + * | ADCBuf_convert() | Perform ADC conversion | + * | ADCBuf_convertCancel() | Cancel ongoing ADC conversion | + * | ADCBuf_close() | Close ADC driver | + * | ADCBuf_Params_init() | Initialise ADCBuf_Params structure to default values | + * | ADCBuf_getResolution() | Get the resolution of the ADC of the current device | + * | ADCBuf_adjustRawValues() | Adjust the values in a returned buffer for manufacturing tolerances | + * | ADCBuf_convertAdjustedToMicroVolts | Convert a buffer of adjusted values to microvolts | + * | ADCBuf_control() | Execute device specific functions | + * + * + * # Not Supported Functionality # + * - Performing conversions on multiple channels simultaneously is not supported. + * In other words, the parameter channelCount must always be set to 1 when + * calling ADCBuf_convert(). The ADC on CC26XX devices does not support + * time-division multiplexing of channels or pins in hardware. + * + * # Use Cases # + * ## Basic one-shot conversion # + * Perform one conversion on CONFIG_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * + * ADCBuf_Params_init(&adcBufParams); + * adcBufHandle = ADCBuf_open(CONFIG_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = CONFIG_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * ## Using ADCBufCC26X2_ParamsExtension # + * This specific configuration performs one conversion on CONFIG_ADCCHANNEL_A1 + * in ::ADCBuf_RETURN_MODE_BLOCKING. The custom parameters used here are + * identical to the defaults parameters. Users can of course define their own + * parameters. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * ADCBufCC26X2_ParamsExtension customParams; + * + * ADCBuf_Params_init(&adcBufParams); + * ADCBufCC26X2_ParamsExtension_init(&customParams); + * customParams.samplingDuration = ADCBufCC26X2_SAMPLING_DURATION_2P7_US; + * customParams.refSource = ADCBufCC26X2_FIXED_REFERENCE; + * customParams.samplingMode = ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS; + * customParams.inputScalingEnabled = true; + * + * adcBufParams.custom = &customParams; + * + * adcBufHandle = ADCBuf_open(CONFIG_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = CONFIG_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * # Instrumentation # + * The ADC driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic ADCBuf operations performed | + * Diags_USER2 | detailed ADCBuf operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_adc_adcbufcc26xx__include +#define ti_drivers_adc_adcbufcc26xx__include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @}*/ + +/** + * @addtogroup ADCBuf_CMD + * ADCBufCC26X2_CMD_* macros are command codes only defined in the + * ADCBufCC26X2.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add ADCBufCC26X2_CMD_* macros here */ + +/*! + * @brief This control function acquires the semaphore that arbitrates access + * to the ADC between the CM3 and the sensor controller + * + * This function pre-acquires the ADC semaphore before ADCBuf_convert() is + * called by the application. Normally, the ADC driver acquires the ADC + * semaphore when calling ADCBufCC26X2_convert(). The driver may need to wait + * for the sensor controller to release the semaphore in order to access the + * ADC hardware module. Consequently, the time at which the conversion is + * actually made is normally non-deterministic. Pre-acquiring the semaphore + * makes the ADCBuf_convert() call deterministic. + * + * @note This function returns an error if the handle is not open or a transfer + * is in progress + */ +#define ADCBufCC26X2_CMD_ACQUIRE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 1 + +/*! + * @brief This function makes the ADC driver keep the ADC semaphore until released + * + * Calling this function will make the ADC driver keep the ADC semaphore until + * it is released by the application by calling the control function + * ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE. This enables multiple deterministic + * conversions to be made. Usually, the driver will release the semaphore after + * the conversion finishes. + * + * @warning The sensor controller can no longer access the ADC until the + * semaphore is released by the application manually. + * + * @sa ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE + */ +#define ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 2 + +/*! + * @brief This function makes the ADC driver no longer keep the ADC semaphore + * until released + * + * This function effectively reverses a call to ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE. + * + * @sa ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE + */ +#define ADCBufCC26X2_CMD_KEEP_ADC_SEMAPHORE_DISABLE ADCBuf_CMD_RESERVED + 3 + +/*! + * @brief This function releases the ADC semaphore + * + * @note This function returns an error if the handle is not open or a + * transfer is in progress + */ +#define ADCBufCC26X2_CMD_RELEASE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 4 + +/** @}*/ + +/*! + * @brief Resolution in bits of the CC26X2 ADC + */ +#define ADCBufCC26X2_RESOLUTION 12 + +#define ADCBufCC26X2_BYTES_PER_SAMPLE 2 + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADCBuf function table pointer */ +extern const ADCBuf_FxnTable ADCBufCC26X2_fxnTable; + +/* + * ============================================================================= + * Enumerations + * ============================================================================= + */ + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from + * the battery voltage or a fixed internal source. + * + * The CC26X2 ADC can operate in two different ways with regards to the + * sampling phase of the ADC conversion process: + * - It can spend a fixed amount of time sampling the signal after getting + * the start conversion trigger. + * - It can constantly keep sampling and immediately start the conversion + * process after getting the trigger. + * + * In ADCBufCC26X2_SYNCHRONOUS mode, the ADC goes into IDLE in between + * conversions and uses less power. The minimum sample time for full precision + * in ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS is dependent on the input load. + */ +typedef enum +{ + ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS, + ADCBufCC26X2_SAMPING_MODE_ASYNCHRONOUS +} ADCBufCC26X2_Sampling_Mode; + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the + * CC26X2 ADC, the sampling and conversion phases. During the sampling phase, + * the ADC samples the analogue input signal. Larger input loads require longer + * sample times for the most accurate results. + * In ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS mode, this enum specifies the + * sampling times available. + */ +typedef enum +{ + ADCBufCC26X2_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26X2_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26X2_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26X2_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26X2_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26X2_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26X2_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26X2_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26X2_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26X2_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26X2_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26X2_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26X2_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCBufCC26X2_Sampling_Duration; + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from + * the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper + * range of the ADC to a fixed value. That value is 4.3V with input scaling + * enabled and ~1.4785V with input scaling disabled. In this mode, the output + * is a function of the input voltage multiplied by the resolution in + * alternatives (not bits) divided by the upper voltage range of the ADC. + * Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the + * battery voltage. As the battery depletes and its voltage drops, so does + * the range of the ADC. This is helpful when measuring signals that are + * generated relative to the battery voltage. In this mode, the output is a + * function of the input voltage multiplied by the resolution in alternatives + * (not bits) divided by VDDS multiplied by a scaling factor derived from the + * input scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), + * where the scaling factor is ~1.4785/4.3 for input scaling disabled and 1 + * for input scaling enabled. + * + * @note The actual reference values are slightly different for each device + * and are higher than the values specified above. This gain is saved + * in the FCFG. The function ADCBuf_convertRawToMicroVolts() must be + * used to derive actual voltage values. Do not attempt to compare raw + * values between devices or derive a voltage from them yourself. The + * results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in + * fixed mode with input scaling enabled, the input should never + * exceed VDDS as per the data sheet. + */ +typedef enum +{ + ADCBufCC26X2_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26X2_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCBufCC26X2_Reference_Source; + +/* + * ============================================================================= + * Structs + * ============================================================================= + */ + +/*! + * @brief Table entry that maps a virtual adc channel to a dio and its + * corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the + * driverlib define corresponding to the desired non-dio signal and dio is set + * to GPIO_INVALID_INDEX. + */ +typedef struct +{ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ +} ADCBufCC26X2_AdcChannelLutEntry; + +/*! + * @brief CC26X2 specific extension to ADCBuf_Params + * + * To use non-default CC26X2 specific parameters when calling ADCBuf_open(), a + * pointer to an instance of this struct must be specified in + * ADCBuf_Params::custom. Alternatively, these values can be set using the + * control function after calling ADCBuf_open(). + */ +typedef struct +{ + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26X2_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the + * entire time since the last conversion */ + ADCBufCC26X2_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the + * battery voltage or a fixed internal source */ + ADCBufCC26X2_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; +} ADCBufCC26X2_ParamsExtension; + +/*! + * @brief ADCBufCC26X2 Hardware Attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * A sample structure is shown below: + * @code + * const ADCBufCC26X2_HWAttrs ADCBufCC26X2HWAttrs[] = { + * { + * .intPriority = ~0, + * .swiPriority = 0, + * } + * }; + * @endcode + */ +typedef struct +{ + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26X2_AdcChannelLutEntry's mapping internal + * CompBInput to DIO */ + ADCBufCC26X2_AdcChannelLutEntry const *adcChannelLut; + /*! GPTimer unit index (0A, 0B, 1A..). Currently only the 0A unit index is + * supported. */ + uint8_t gpTimerUnit; + /*! Specifies whether the ADC semaphore should be acquired during open() */ + bool acquireADCSem; +} ADCBufCC26X2_HWAttrs; + +/*! + * @brief ADCBufCC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* ADC control variables */ + bool isOpen; /*!< Has the obj been opened */ + bool conversionInProgress; /*!< Is the ADC currently doing conversions */ + bool inputScalingEnabled; /*!< Is the analogue input scaled */ + bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ + bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ + uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ + ADCBufCC26X2_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCBufCC26X2_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ + ADCBufCC26X2_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in + ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ + ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ + uint16_t *activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ + + /* ADC SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ + + ADCBuf_Conversion *currentConversion; /*!< Pointer to the current conversion struct */ + + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ + + /* GPTimer driver handle */ + GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ + + uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ +} ADCBufCC26X2_Object, *ADCBufCC26X2_Handle; + +/* + * ============================================================================= + * Functions + * ============================================================================= + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCBufCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.c b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.c new file mode 100644 index 00000000..b4127f12 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.c @@ -0,0 +1,1078 @@ +/* + * Copyright (c) 2016-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include +#include +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE + #define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ +#endif + +/* + * ============================================================================= + * Public Function Declarations + * ============================================================================= + */ +void ADCBufCC26XX_init(ADCBuf_Handle handle); +ADCBuf_Handle ADCBufCC26XX_open(ADCBuf_Handle handle, const ADCBuf_Params *params); +int_fast16_t ADCBufCC26XX_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount); +int_fast16_t ADCBufCC26XX_convertCancel(ADCBuf_Handle handle); +void ADCBufCC26XX_close(ADCBuf_Handle handle); +uint_fast8_t ADCBufCC26XX_getResolution(ADCBuf_Handle handle); +int_fast16_t ADCBufCC26XX_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); +int_fast16_t ADCBufCC26XX_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount); +int_fast16_t ADCBufCC26XX_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg); + +/* + * ============================================================================= + * Private Function Declarations + * ============================================================================= + */ +static bool ADCBufCC26XX_acquireADCSemaphore(ADCBuf_Handle handle); +static bool ADCBufCC26XX_releaseADCSemaphore(ADCBuf_Handle handle); +static void ADCBufCC26XX_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26XX_hwiFxn(uintptr_t arg); +static void ADCBufCC26XX_swiFxn(uintptr_t arg0, uintptr_t arg1); +static void ADCBufCC26XX_conversionCallback(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel, + int_fast16_t status); +static uint32_t ADCBufCC26XX_freqToCounts(uint32_t frequency); +static void ADCBufCC26XX_configGPTDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion); +static void ADCBufCC26XX_cleanADC(ADCBuf_Handle handle); +static void ADCBufCC26XX_loadDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry); +static void ADCBufCC26XX_loadGPTDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry); + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +const ADCBuf_FxnTable ADCBufCC26XX_fxnTable = { + /*! Function to close the specified peripheral */ + ADCBufCC26XX_close, + /*! Function to driver implementation specific control function */ + ADCBufCC26XX_control, + /*! Function to initialize the given data object */ + ADCBufCC26XX_init, + /*! Function to open the specified peripheral */ + ADCBufCC26XX_open, + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBufCC26XX_convert, + /*! Function to abort a conversion being carried out by the specified + * peripheral */ + ADCBufCC26XX_convertCancel, + /*! Function to get the resolution in bits of the ADC */ + ADCBufCC26XX_getResolution, + /*! Function to adjust raw ADC output values to values comparable between + * devices of the same type */ + ADCBufCC26XX_adjustRawValues, + /*! Function to convert adjusted ADC values to microvolts */ + ADCBufCC26XX_convertAdjustedToMicroVolts}; + +/* + * ============================================================================= + * Private Global Variables + * ============================================================================= + */ + +/* Allocate space for DMA control table entry */ +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCPriControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaADCAltControlTableEntry, (UDMA_CHAN_AUX_ADC + UDMA_ALT_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaGPT0APriControlTableEntry, (UDMA_CHAN_TIMER0_A + UDMA_PRI_SELECT)); +ALLOCATE_CONTROL_TABLE_ENTRY(dmaGPT0AAltControlTableEntry, (UDMA_CHAN_TIMER0_A + UDMA_ALT_SELECT)); + +/*! + * Timeout interrupt bitmask of the GPT that the DMA copies into GPT_O_ICLR + * to bring the DMA trigger event low. + * Needs to go into RAM not flash to prevent system from hanging in edge cases. + */ +static uint8_t gptClear = GPT_ICLR_TATOCINT; + +/* + * ============================================================================= + * Function Definitions + * ============================================================================= + */ + +/* + * ======== ADCBufCC26XX_init ======== + */ +void ADCBufCC26XX_init(ADCBuf_Handle handle) +{ + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + /* Mark the object as available */ + object->isOpen = false; +} + +/* + * ======== ADCBufCC26XX_open ======== + */ +ADCBuf_Handle ADCBufCC26XX_open(ADCBuf_Handle handle, const ADCBuf_Params *params) +{ + /* Use union to save on stack allocation */ + union + { + HwiP_Params hwiParams; + SwiP_Params swiParams; + GPTimerCC26XX_Params timerParams; + } paramsUnion; + ADCBufCC26XX_Object *object; + ADCBufCC26XX_HWAttrs const *hwAttrs; + uint32_t key; + uint32_t adcPeriodCounts; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the ADC is open. */ + key = HwiP_disable(); + + /* Check if the ADC is open already with the base addr. */ + if (object->isOpen == true) + { + HwiP_restore(key); + + DebugP_log0("ADCBuf: already in use."); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + + /* On Chameleon, ANAIF must be clocked to use it. On Agama, the register + * inferface is always available. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + /* Turn on the ANAIF clock. ANIAF contains the AUX ADC. */ + AUXWUCClockEnable(AUX_WUC_ANAIF_CLOCK); + AUXWUCClockEnable(AUX_WUC_ADI_CLOCK); +#endif + + HwiP_restore(key); + + /* Initialise the ADC object */ + /* Initialise params section of object */ + object->conversionInProgress = false; + object->semaphoreTimeout = params->blockingTimeout; + object->samplingFrequency = params->samplingFrequency; + object->returnMode = params->returnMode; + object->recurrenceMode = params->recurrenceMode; + object->keepADCSemaphore = false; + object->adcSemaphoreInPossession = false; + + if (params->custom) + { + /* If CC26XX specific params were specified, use them */ + object->samplingDuration = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->samplingDuration; + object->refSource = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->refSource; + object->samplingMode = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->samplingMode; + object->inputScalingEnabled = ((ADCBufCC26XX_ParamsExtension *)(params->custom))->inputScalingEnabled; + } + else + { + /* Initialise CC26XX specific settings to defaults */ + object->inputScalingEnabled = true; + object->refSource = ADCBufCC26XX_FIXED_REFERENCE; + object->samplingMode = ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS; + object->samplingDuration = ADCBufCC26XX_SAMPLING_DURATION_2P7_US; + } + + /* Open timer resource */ + GPTimerCC26XX_Params_init(¶msUnion.timerParams); + paramsUnion.timerParams.width = GPT_CONFIG_16BIT; + paramsUnion.timerParams.mode = GPT_MODE_PERIODIC_UP; + paramsUnion.timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + /* Open position 0 of the GPT config table - by convention this is timer 0A. */ + object->timerHandle = GPTimerCC26XX_open(0, ¶msUnion.timerParams); + + if (object->timerHandle == NULL) + { + /* We did not manage to open the GPTimer we wanted */ + return NULL; + } + + adcPeriodCounts = ADCBufCC26XX_freqToCounts(params->samplingFrequency); + GPTimerCC26XX_setLoadValue(object->timerHandle, adcPeriodCounts); + + GPTimerCC26XX_enableInterrupt(object->timerHandle, GPT_INT_TIMEOUT); + + if (params->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + /* Continuous trigger mode and blocking return mode is an illegal combination */ + DebugP_assert(!(params->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS)); + + /* Create a semaphore to block task execution for the duration of the + * ADC conversions */ + SemaphoreP_constructBinary(&(object->conversionComplete), 0); + + /* Store internal callback function */ + object->callbackFxn = ADCBufCC26XX_conversionCallback; + } + else + { + /* Callback mode without a callback function defined */ + DebugP_assert(params->callbackFxn); + + /* Save the callback function pointer */ + object->callbackFxn = params->callbackFxn; + } + + /* Clear the event flags to prevent an immediate interrupt from a previous + * configuration */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | + AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + HwiP_clearInterrupt(INT_AUX_ADC_IRQ); + + /* Create the Hwi for this ADC peripheral. */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_AUX_ADC_IRQ, ADCBufCC26XX_hwiFxn, ¶msUnion.hwiParams); + + /* Create the Swi object for this ADC peripheral */ + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), ADCBufCC26XX_swiFxn, &(paramsUnion.swiParams)); + + /* Declare the dependency on the UDMA driver */ + object->udmaHandle = UDMACC26XX_open(); + + /* Return the handle after finishing initialisation of the driver */ + DebugP_log0("ADC: opened"); + return handle; +} + +/*! + * @brief HWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg An ADCBufCC26XX_Handle + * + */ +static void ADCBufCC26XX_hwiFxn(uintptr_t arg) +{ + ADCBufCC26XX_Object *object; + ADCBuf_Conversion *conversion; + uint32_t intStatus; + + /* Get the pointer to the object and current conversion*/ + object = ((ADCBuf_Handle)arg)->object; + conversion = object->currentConversion; + + /* Set activeSampleBuffer to primary as default */ + object->activeSampleBuffer = conversion->sampleBuffer; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + /* Disable the ADC */ + AUXADCDisable(); + /* Disable ADC DMA if we are only doing one conversion and clear DMA + * done interrupt. */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | + AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + } + else if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) + { + /* Reload the finished DMA control table entry */ + if (HWREG(UDMA0_BASE + UDMA_O_SETCHNLPRIALT) & (1 << UDMA_CHAN_AUX_ADC)) + { + /* We are currently using the alternate entry -> we just finished + * the primary entry -> reload primary entry */ + ADCBufCC26XX_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + ADCBufCC26XX_loadGPTDMAControlTableEntry((ADCBuf_Handle)arg, conversion, true); + } + else + { + /* We are currently using the primary entry -> we just finished the + * alternate entry -> reload the alternate entry */ + ADCBufCC26XX_loadDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + ADCBufCC26XX_loadGPTDMAControlTableEntry((ADCBuf_Handle)arg, conversion, false); + object->activeSampleBuffer = conversion->sampleBufferTwo; + } + } + /* Clear DMA interrupts */ + UDMACC26XX_clearInterrupt(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC) | (1 << UDMA_CHAN_TIMER0_A)); + + /* Get the status of the ADC_IRQ line and ADC_DONE */ + intStatus = HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGS) & + (AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ | AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE); + /* Clear the ADC_IRQ flag if it triggered the ISR */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = intStatus; + + /* Post SWI to handle remaining clean up and invocation of callback */ + SwiP_post(&(object->swi)); +} + +/*! + * @brief SWI ISR of the ADC triggered when the DMA transaction is complete + * + * @param arg0 An ADCBufCC26XX_Handle + * + */ +static void ADCBufCC26XX_swiFxn(uintptr_t arg0, uintptr_t arg1) +{ + uint32_t key; + ADCBuf_Conversion *conversion; + ADCBufCC26XX_Object *object; + uint16_t *sampleBuffer; + uint8_t channel; + + /* Get the pointer to the object */ + object = ((ADCBuf_Handle)arg0)->object; + + DebugP_log0("ADC: swi interrupt context start"); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Use a temporary pointers in case the callback function + * attempts to perform another ADCBuf_transfer call + */ + conversion = object->currentConversion; + sampleBuffer = object->activeSampleBuffer; + channel = object->currentChannel; + + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + /* Clean up ADC and DMA */ + ADCBufCC26XX_cleanADC(((ADCBuf_Handle)arg0)); + /* Indicate we are done with this transfer */ + object->currentConversion = NULL; + } + + /* Restore interrupts */ + HwiP_restore(key); + + /* Perform callback */ + object->callbackFxn((ADCBuf_Handle)arg0, conversion, sampleBuffer, channel, ADCBuf_STATUS_SUCCESS); + + DebugP_log0("ADC: swi interrupt context end"); +} + +/*! + * @brief CC26XX internal callback function that posts the semaphore in blocking mode + * + * @param handle An ADCBufCC26XX_Handle + * + * @param conversion A pointer to the current ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_conversionCallback(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + void *completedADCBuffer, + uint32_t completedChannel, + int_fast16_t status) +{ + ADCBufCC26XX_Object *object; + + DebugP_log0("ADC DMA: posting conversionComplete semaphore"); + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->conversionComplete)); +} + +/* + * ======== ADCBufCC26XX_convert ======== + */ +int_fast16_t ADCBufCC26XX_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount) +{ + uint32_t key; + ADCBufCC26XX_Object *object; + ADCBufCC26XX_HWAttrs const *hwAttrs; + PIN_Config adcPinTable[2]; + uint8_t i = 0; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + DebugP_assert(channelCount == 1); + DebugP_assert((conversions->samplesRequestedCount <= UDMA_XFER_SIZE_MAX)); + DebugP_assert(conversions->sampleBuffer); + DebugP_assert(!(object->recurrenceMode == (ADCBuf_RECURRENCE_MODE_CONTINUOUS && !(conversions->sampleBufferTwo)))); + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + /* Restore interrupts */ + HwiP_restore(key); + DebugP_log0("ADCBuf: conversion failed"); + return ADCBuf_STATUS_ERROR; + } + object->conversionInProgress = true; + + /* Restore interrupts*/ + HwiP_restore(key); + + /* Specify input in ADC module */ + AUXADCSelectInput(hwAttrs->adcChannelLut[conversions->adcChannel].compBInput); + + /* Add pin to measure on */ + adcPinTable[i++] = (hwAttrs->adcChannelLut[conversions->adcChannel].dio) | PIN_NOPULL | PIN_INPUT_DIS | + PIN_GPIO_OUTPUT_DIS | PIN_IRQ_DIS | PIN_DRVSTR_MIN; + + /* Terminate pin list */ + adcPinTable[i] = PIN_TERMINATE; + object->pinHandle = PIN_open(&object->pinState, adcPinTable); + if (!object->pinHandle) + { + object->conversionInProgress = false; + return ADCBuf_STATUS_ERROR; + } + + /* Save which channel we are converting on for the callbackFxn */ + object->currentChannel = conversions->adcChannel; + + /* Try to acquire the ADC semaphore if we do not already have it. */ + if (object->adcSemaphoreInPossession == false) + { + if (!AUXSMPHTryAcquire(AUX_SMPH_2)) + { + PIN_close(object->pinHandle); + object->conversionInProgress = false; + DebugP_log0("ADCBuf: failed to acquire semaphore"); + return ADCBuf_STATUS_ERROR; + } + object->adcSemaphoreInPossession = true; + } + + /* Store location of the current conversion */ + object->currentConversion = conversions; + + /* Configure and arm the DMA and AUX DMA control */ + ADCBufCC26XX_configDMA(handle, conversions); + + /* Configure and arm the GPT DMA channel to clear the level-based GPT IRQ signal */ + ADCBufCC26XX_configGPTDMA(handle, conversions); + + /* Flush the ADC FIFO in case we have triggered prior to this call */ + AUXADCFlushFifo(); + + /* If input scaling is set to disabled in the params, disable it */ + if (!object->inputScalingEnabled) + { + AUXADCDisableInputScaling(); + } + + /* Arm the ADC in preparation for incoming conversion triggers */ + if (object->samplingMode == ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS) + { + /* ADCBufCC26XX_SYNCHRONOUS sampling mode */ + AUXADCEnableSync(object->refSource, object->samplingDuration, AUXADC_TRIGGER_GPT0A); + } + else + { + /* ADCBufCC26XX_ASYNCHRONOUS sampling mode */ + AUXADCEnableAsync(object->refSource, AUXADC_TRIGGER_GPT0A); + } + + /* Start the GPTimer to create ADC triggers */ + GPTimerCC26XX_start(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + DebugP_log0("ADCBuf: transfer pending on conversionComplete " + "semaphore"); + + if (SemaphoreP_OK != SemaphoreP_pend(&(object->conversionComplete), object->semaphoreTimeout)) + { + /* Cancel the transfer if we experience a timeout */ + ADCBufCC26XX_convertCancel(handle); + /* + * ADCBufCC26XX_convertCancel performs a callback which posts a + * conversionComplete semaphore. This call consumes this extra post. + */ + SemaphoreP_pend(&(object->conversionComplete), SemaphoreP_NO_WAIT); + return ADCBuf_STATUS_ERROR; + } + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26XX_convertCancel ======== + */ +int_fast16_t ADCBufCC26XX_convertCancel(ADCBuf_Handle handle) +{ + ADCBufCC26XX_Object *object; + ADCBuf_Conversion *conversion; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs*/ + object = handle->object; + + /* Check if ADC is open and that no other transfer is in progress */ + if (!(object->conversionInProgress)) + { + DebugP_log0("ADCBuf: a conversion must be in progress to cancel one"); + return ADCBuf_STATUS_ERROR; + } + + /* Stop triggering a conversion on trigger events */ + AUXADCDisable(); + + /* Set hardware and software configuration to default and turn off driver */ + ADCBufCC26XX_cleanADC(handle); + + /* Use a temporary transaction pointer in case the callback function + * attempts to perform another ADCBuf_convert call + */ + conversion = object->currentConversion; + + /* Perform callback if we are in one-shot mode. In continuous mode, + * ADCBuf_convertCancel will probably be called from the callback function + * itself. No need to call it again. */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + { + object->callbackFxn(handle, + conversion, + conversion->sampleBuffer, + object->currentChannel, + ADCBuf_STATUS_SUCCESS); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26XX_close ======== + */ +void ADCBufCC26XX_close(ADCBuf_Handle handle) +{ + ADCBufCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Check if the ADC is running and abort conversion if necessary. */ + if (object->conversionInProgress) + { + ADCBuf_convertCancel(handle); + } + + /* Get the pointer to the object */ + object = handle->object; + + /* Release the uDMA dependency and potentially power down uDMA. */ + UDMACC26XX_close(object->udmaHandle); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Destroy the Swi */ + SwiP_destruct(&(object->swi)); + + /* Close the timer */ + GPTimerCC26XX_close(object->timerHandle); + + if (object->returnMode == ADCBuf_RETURN_MODE_BLOCKING) + { + SemaphoreP_destruct(&(object->conversionComplete)); + } + + if (object->adcSemaphoreInPossession) + { + ADCBufCC26XX_releaseADCSemaphore(handle); + } + + /* Mark the module as available */ + object->isOpen = false; + + DebugP_log0("ADCBuf: closed"); +} + +/* + * ======== ADCBufCC26XX_getResolution ======== + */ +uint_fast8_t ADCBufCC26XX_getResolution(ADCBuf_Handle handle) +{ + return (ADCBufCC26XX_RESOLUTION); +} + +/* + * ======== ADCBufCC26XX_adjustRawValues ======== + */ +int_fast16_t ADCBufCC26XX_adjustRawValues(ADCBuf_Handle handle, + void *sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel) +{ + ADCBufCC26XX_Object *object; + uint32_t gain; + uint32_t offset; + uint16_t i; + + object = handle->object; + + gain = AUXADCGetAdjustmentGain(object->refSource); + offset = AUXADCGetAdjustmentOffset(object->refSource); + + for (i = 0; i < sampleCount; i++) + { + uint16_t tmpRawADCVal = ((uint16_t *)sampleBuffer)[i]; + ((uint16_t *)sampleBuffer)[i] = AUXADCAdjustValueForGainAndOffset(tmpRawADCVal, gain, offset); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/* + * ======== ADCBufCC26XX_convertAdjustedToMicroVolts ======== + */ +int_fast16_t ADCBufCC26XX_convertAdjustedToMicroVolts(ADCBuf_Handle handle, + uint32_t adcChannel, + void *adjustedSampleBuffer, + uint32_t outputMicroVoltBuffer[], + uint_fast16_t sampleCount) +{ + ADCBufCC26XX_Object *object; + uint16_t i; + uint32_t voltageRef; + + object = handle->object; + + voltageRef = (object->inputScalingEnabled) ? AUXADC_FIXED_REF_VOLTAGE_NORMAL : AUXADC_FIXED_REF_VOLTAGE_UNSCALED; + + for (i = 0; i < sampleCount; i++) + { + outputMicroVoltBuffer[i] = AUXADCValueToMicrovolts(voltageRef, ((uint16_t *)adjustedSampleBuffer)[i]); + } + + return ADCBuf_STATUS_SUCCESS; +} + +/*! + * @brief Function to configure the DMA to automatically transfer ADC output + * data into a provided array + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_configDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) +{ + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26XX_loadDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continous mode, load the alternate DMA control + * table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) + { + ADCBufCC26XX_loadDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_AUX_ADC); + + /* Configure DMA settings in AUX_EVCTL */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_EN | + AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + DebugP_log0("ADCBuf: DMA transfer enabled"); +} + +/*! + * @brief Function to configure the adc DMA control table entry for basic or + * ping pong mode + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate + * control table entry + * + */ +static void ADCBufCC26XX_loadDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry) +{ + ADCBufCC26XX_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + uint32_t numberOfBytes; + + /* Get the pointer to the object*/ + object = handle->object; + + /* Calculate the number of bytes for the transfer */ + numberOfBytes = (uint16_t)(conversion->samplesRequestedCount) * ADCBufCC26XX_BYTES_PER_SAMPLE; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaADCPriControlTableEntry : &dmaADCAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + ? UDMA_MODE_BASIC + : UDMA_MODE_PINGPONG) | + UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(primaryEntry ? conversion->sampleBuffer + : conversion->sampleBufferTwo) + + numberOfBytes - 1); + dmaControlTableEntry->pvSrcEndAddr = (void *)(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); +} + +/*! + * @brief Function to configure the DMA to automatically clear the GPT_IRQ + * line that the ADC triggers off of without using an interrupt handler + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + */ +static void ADCBufCC26XX_configGPTDMA(ADCBuf_Handle handle, ADCBuf_Conversion *conversion) +{ + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + ADCBufCC26XX_loadGPTDMAControlTableEntry(handle, conversion, true); + + /* If we are operating in continous mode, load the alternate DMA control + * table data structure */ + if (object->recurrenceMode == ADCBuf_RECURRENCE_MODE_CONTINUOUS) + { + ADCBufCC26XX_loadGPTDMAControlTableEntry(handle, conversion, false); + } + + /* Enable the channels */ + UDMACC26XX_channelEnable(object->udmaHandle, 1 << UDMA_CHAN_TIMER0_A); + + /* Enable event signal */ + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_DMAEV) = GPT_DMAEV_TATODMAEN; +} + +/*! + * @brief Function to configure the GPT DMA control table entry for basic or + * ping pong mode + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + * @param conversion A pointer to an ADCBuf_Conversion + * + * @param primaryEntry Is this supposed to modify the primary or the alternate + * control table entry + * + */ +static void ADCBufCC26XX_loadGPTDMAControlTableEntry(ADCBuf_Handle handle, + ADCBuf_Conversion *conversion, + bool primaryEntry) +{ + ADCBufCC26XX_Object *object; + volatile tDMAControlTable *dmaControlTableEntry; + + /* Get the pointer to the object */ + object = handle->object; + + /* Set configure control table entry */ + dmaControlTableEntry = primaryEntry ? &dmaGPT0APriControlTableEntry : &dmaGPT0AAltControlTableEntry; + dmaControlTableEntry->ui32Control = ((object->recurrenceMode == ADCBuf_RECURRENCE_MODE_ONE_SHOT) + ? UDMA_MODE_BASIC + : UDMA_MODE_PINGPONG) | + UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1 | + UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)conversion->samplesRequestedCount); + dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(object->timerHandle->hwAttrs->baseAddr + GPT_O_ICLR)); + dmaControlTableEntry->pvSrcEndAddr = (void *)(&gptClear); +} + +/*! + * @brief Function to undo all configurations done by the ADC driver + * + * @pre ADCBuf_open() has to be called first. + * + * @pre ADCBuf_convert() has to be called first. + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static void ADCBufCC26XX_cleanADC(ADCBuf_Handle handle) +{ + ADCBufCC26XX_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Stop the timer to stop generating triggers */ + GPTimerCC26XX_stop(object->timerHandle); + + /* Set constraints to guarantee operation */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->adcSemaphoreInPossession && !object->keepADCSemaphore) + { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Disable the UDMA channels */ + UDMACC26XX_channelDisable(object->udmaHandle, (1 << UDMA_CHAN_AUX_ADC) | (1 << UDMA_CHAN_TIMER0_A)); + + /* Deallocate pins */ + PIN_close(object->pinHandle); + + /* Disable UDMA mode for ADC */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_DMACTL) = AUX_EVCTL_DMACTL_REQ_MODE_SINGLE | AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY; + + /* Clear any remaining GPT_IRQ flags */ + HWREG(object->timerHandle->hwAttrs->baseAddr + GPT_O_ICLR) = GPT_ICLR_DMAAINT + GPT_ICLR_TATOCINT; + + /* Note that the driver is no longer converting */ + object->conversionInProgress = false; +} + +/* Return period in timer counts */ +static uint32_t ADCBufCC26XX_freqToCounts(uint32_t frequency) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts = (freq.lo / frequency) - 1; + + return periodCounts; +} + +/*! + * @brief Function to acquire the semaphore that arbitrates access to the ADC + * between the CM3 and the sensor controller + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static bool ADCBufCC26XX_acquireADCSemaphore(ADCBuf_Handle handle) +{ + uint32_t key; + bool semaphoreAvailable; + ADCBufCC26XX_Object *object; + + object = handle->object; + + /* Set semaphoreAvailable false at default */ + semaphoreAvailable = false; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + DebugP_log0("ADC: driver must be open and no conversion must be in " + "progress to disable input scaling"); + } + /* This is a non-blocking call to acquire the ADC semaphore. */ + else if (AUXSMPHTryAcquire(AUX_SMPH_2)) + { + object->adcSemaphoreInPossession = true; + semaphoreAvailable = true; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreAvailable; +} + +/*! + * @brief This function releases the ADC semaphore + * + * @pre ADCBufCC26XX_open() has to be called first. + * + * @pre There must not currently be a conversion in progress + * + * @param handle An ADCBufCC26XX handle returned from ADCBufCC26XX_open() + * + */ +static bool ADCBufCC26XX_releaseADCSemaphore(ADCBuf_Handle handle) +{ + uint32_t key; + bool semaphoreReleased; + ADCBufCC26XX_Object *object; + + object = handle->object; + + /* Set semaphoreReleased true at default */ + semaphoreReleased = true; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Check if ADC is closed or a conversion is in progress */ + if (!(object->isOpen) || object->conversionInProgress) + { + DebugP_log0("ADC: driver must be open and no conversion must be in " + "progress to disable input scaling"); + semaphoreReleased = false; + } + else + { + /* Release the ADC semaphore */ + AUXSMPHRelease(AUX_SMPH_2); + object->adcSemaphoreInPossession = false; + } + + /* Restore interrupts */ + HwiP_restore(key); + + return semaphoreReleased; +} + +/* + * ======== ADCBufCC26XX_control ======== + */ +int_fast16_t ADCBufCC26XX_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *arg) +{ + ADCBufCC26XX_Object *object = handle->object; + int status = ADCBuf_STATUS_ERROR; + + DebugP_assert(handle); + + switch (cmd) + { + case ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE: + if (ADCBufCC26XX_acquireADCSemaphore(handle)) + { + status = ADCBuf_STATUS_SUCCESS; + } + break; + case ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE: + object->keepADCSemaphore = true; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE: + object->keepADCSemaphore = false; + status = ADCBuf_STATUS_SUCCESS; + break; + case ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE: + if (ADCBufCC26XX_releaseADCSemaphore(handle)) + { + status = ADCBuf_STATUS_SUCCESS; + } + break; + default: + status = ADCBuf_STATUS_UNDEFINEDCMD; + break; + } + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.h b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.h new file mode 100644 index 00000000..b5b25f90 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/adcbuf/ADCBufCC26XX.h @@ -0,0 +1,677 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ADCBufCC26XX.h + * + * @brief ADCBuf driver implementation for a CC26XX analog-to-digital + * converter + * + * # Driver include # + * The ADCBuf header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * # Overview # + * This is a CC26XX specific implementation of the generic TI-RTOS ADCBuf driver. + * The generic ADCBuf API specified in ti/drivers/ADCBuf.h should be called by + * the application, not the device specific implementation in + * ti/drivers/adcbuf/ADCBufCC26XX. The board file defines the device specific + * configuration and casting in the general API ensures the correct device + * specific functions are called. You should specify an + * ADCBufCC26XX_ParamsExtension in the custom field of the ADCBuf_Params that + * suits your application. The default settings work for many, but not all, + * use cases. + * + * # General Behavior # + * A timer and the DMA are used to trigger the ADC and fill a buffer in the + * background (in hardware) at a specified frequency. The application may + * execute other tasks while the hardware handles the conversions. In contrast + * to the standard ti/drivers/ADC driver, this driver allows for precise + * sampling of waveforms. + * + * | Driver | Number of samples needed in one call | + * |----------------|-----------------------------------------| + * | ADC.h | 1 | + * | ADCBuf.h | > 1 | + * + * This ADCBuf driver provides an API interface to using the analog-to-digital + * converter directly from the CM3 without going through the sensor controller. + * The sensor controller can still use the ADC, support for sharing the ADC + * resource between the sensor controller and the CM3 is built into the driver. + * There is a hardware semaphore that the driver must acquire before beginning + * any number of conversions. This same hardware semaphore also prevents the + * simultaneous use of this driver and the basic ADC driver. + * + * The ADC drivers supports making between one and 1024 measurements once or + * continuous measuring with returned buffer sizes between one and 1024 + * measurements. + * + * The application should call ADCBuf_init() once by the application to set the + * isOpened flag to false, indicating that the driver is ready to use. + * + * The ADC driver is opened by calling ADCBuf_open() which will + * set up interrupts and configure the internal components of the driver. + * However, the ADC hardware or analog pins are not yet configured, since the + * sensor controller or basic ADC driver might be using the ADC. + * + * In order to perform an ADC conversion, the application should call + * ADCBuf_convert(). This call will request the ADC resource, configure the ADC, + * set up the DMA and GPTimer, and perform the requested ADC conversions on the + * selected DIO or internal signal. The DIO or internal signal is defined by the + * ADCBuf_Conversion structure in the application code and adcBufCC26xxObjects + * in the board file. + * + * @warning If the ADCBUF driver is setup in ADCBuf_RECURRENCE_MODE_CONTINUOUS + * mode, the user must assure that the provided callback function is + * completed before the next conversion completes. If the next + * conversion completes before the callback function finishes, the DMA + * will clobber the previous buffer with new data. + * + * If the sensor controller is using the ADC when the driver requests it at the + * start of the ADC_convert() call, the conversion will fail and return false. + * The ADC resource may be pre-acquired by calling the control function + * ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE. It will be released again + * automatically after the next conversion completes. + * + * In both ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS mode and + * ADCBufCC26XX_SAMPING_MODE_ASYNCHRONOUS mode, enough sampling time must be + * provided between conversions that each measurement may be completed before + * the next trigger arrives. + * + * @note The ADCBuf driver requires GPTimer0A to function correctly. It + * expects it to be configured as position 0 in the GPTimer Config + * Table. GPTimer0A will be unavailable for other uses. + * + * # Supported ADC pins # + * Below is a table of the supported ADC IO pins for each package size, for both + * CC26xx and CC13xx. It maps a DIO to its corresponding driverlib define for + * the CompBInput that it is hardwired to. This table can be used to create + * virtual channel entries in the ADCBufCC26XX_adcChannelLut table in the board + * file. + * + * | DIO | CC26xx 7x7 AUXIO CompBInput | CC13xx 7x7 AUXIO CompBInput | CC26xx 5x5 AUXIO CompBInput | CC13xx 5x5 + *AUXIO CompBInput | CC26xx 4x4 AUXIO CompBInput | CC13xx 4x4 AUXIO CompBInput + * |--------|-------------------------------|-------------------------------|-------------------------------|-------------------------------|-------------------------------|----------------------------- + * | 0 | No | No | No | No | No | + *No | 1 | No | No | No | No | No + *| No | 2 | No | No | No | No | + *No | No | 3 | No | No | No | No + *| No | No | 4 | No | No | No | + *No | No | No | 5 | No | No | No + *| No | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 | 6 | No | No | No | No | + *ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 | 7 | No | No | + *ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 | + *8 | No | No | ADC_COMPB_IN_AUXIO6 | + *ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 | 9 | No | No | + *ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 | + *10 | No | No | ADC_COMPB_IN_AUXIO5 | + *ADC_COMPB_IN_AUXIO5 | No | No | 11 | No | No | + *ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 | No | No | 12 | No | No + *| ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 | No | No | 13 | No | + *No | ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 | No | No | 14 | No + *| No | ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 | No | No | 15-22 | + *No | No | No | No | No | No | 23 | + *ADC_COMPB_IN_AUXIO7 | ADC_COMPB_IN_AUXIO7 | No | No | No | No | 24 | + *ADC_COMPB_IN_AUXIO6 | ADC_COMPB_IN_AUXIO6 | No | No | No | No | 25 | + *ADC_COMPB_IN_AUXIO5 | ADC_COMPB_IN_AUXIO5 | No | No | No | No | 26 | + *ADC_COMPB_IN_AUXIO4 | ADC_COMPB_IN_AUXIO4 | No | No | No | No | 27 | + *ADC_COMPB_IN_AUXIO3 | ADC_COMPB_IN_AUXIO3 | No | No | No | No | 28 | + *ADC_COMPB_IN_AUXIO2 | ADC_COMPB_IN_AUXIO2 | No | No | No | No | 29 | + *ADC_COMPB_IN_AUXIO1 | ADC_COMPB_IN_AUXIO1 | No | No | No | No | 30 | + *ADC_COMPB_IN_AUXIO0 | ADC_COMPB_IN_AUXIO0 | No | No | No | No + * + * # Supported Internal Signals # + * Below is a table of internal signals that can be measured using the ADC. + * Since we are not connecting to a DIO, there is no DIO to internal signal + * mapping. The DIO field in the channel lookup table should be marked + * PIN_UNASSIGNED. This table can be used to create virtual channel entries in + * the ADCBufCC26XX_adcChannelLut table in the board file. + * + * | DIO | Internal Signal CompBInput | + * |--------------------|-------------------------------| + * | PIN_UNASSIGNED | ADC_COMPB_IN_DCOUPL | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VSS | + * | PIN_UNASSIGNED | ADC_COMPB_IN_VDDS | + * + * # Error handling # + * The following errors may occur when opening the ADC without assertions enabled: + * - The ADC handle is already open. + * + * The following errors may occur when requesting an ADC conversion: + * - The ADC is currently already doing a conversion. + * - The ADC was not available (used by sensor controller or basic ADC). + * + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the + * most power efficient mode whenever possible. Please see the technical + * reference manual for further details on each power mode. + * + * While converting, the ADCBufCC26XX driver sets a power constraint to keep + * the device out of standby. When the conversion has finished, the power + * constraint is released. The driver also sets a dependency on the DMA to + * enable background transfers from the ADC FIFO to memory and to clear the + * GPTimer interrupt. + * The following statements are valid: + * - After ADCBuf_convert(): the device cannot enter standby. + * - After ADCBuf_convertCancel(): the device can enter standby again. + * - After a conversion finishes: the device can enter standby again. + * + * + * # Supported Functions # + * | API function | Description | + * |------------------------------------|-----------------------------------------------------------------------| + * | ADCBuf_init() | Initialize ADC driver | + * | ADCBuf_open() | Open the ADC driver and configure driver | + * | ADCBuf_convert() | Perform ADC conversion | + * | ADCBuf_convertCancel() | Cancel ongoing ADC conversion | + * | ADCBuf_close() | Close ADC driver | + * | ADCBuf_Params_init() | Initialise ADCBuf_Params structure to default values | + * | ADCBuf_getResolution() | Get the resolution of the ADC of the current device | + * | ADCBuf_adjustRawValues() | Adjust the values in a returned buffer for manufacturing tolerances | + * | ADCBuf_convertAdjustedToMicroVolts | Convert a buffer of adjusted values to microvolts | + * | ADCBuf_control() | Execute device specific functions | + * + * + * # Not Supported Functionality # + * - Performing conversions on multiple channels simultaneously is not + * supported. In other words, the parameter channelCount must always be + * set to 1 when calling ADCBuf_convert(). The ADC on CC26XX devices does + * not support time-division multiplexing of channels or pins in hardware. + * + * # Use Cases # + * ## Basic one-shot conversion # + * Perform one conversion on CONFIG_ADCCHANNEL_A1 in ::ADCBuf_RETURN_MODE_BLOCKING. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * + * ADCBuf_Params_init(&adcBufParams); + * adcBufHandle = ADCBuf_open(CONFIG_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = CONFIG_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * ## Using ADCBufCC26XX_ParamsExtension # + * This specific configuration performs one conversion on CONFIG_ADCCHANNEL_A1 + * in ::ADCBuf_RETURN_MODE_BLOCKING. The custom parameters used here are + * identical to the defaults parameters. Users can of course define their own + * parameters. + * @code + * #include + * + * #define ADCBUFFERSIZE 100 + * + * ADCBuf_Handle adcBufHandle; + * ADCBuf_Params adcBufParams; + * ADCBuf_Conversion blockingConversion; + * uint16_t sampleBufferOne[ADCBUFFERSIZE]; + * ADCBufCC26XX_ParamsExtension customParams; + * + * ADCBuf_Params_init(&adcBufParams); + * customParams.samplingDuration = ADCBufCC26XX_SAMPLING_DURATION_2P7_US; + * customParams.refSource = ADCBufCC26XX_FIXED_REFERENCE; + * customParams.samplingMode = ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS; + * customParams.inputScalingEnabled = true; + * + * adcBufParams.custom = &customParams; + * + * adcBufHandle = ADCBuf_open(CONFIG_ADCBuf0, &adcBufParams); + * if (adcBufHandle == NULL) { + * // handle error + * } + * + * blockingConversion.arg = NULL; + * blockingConversion.adcChannel = CONFIG_ADCCHANNEL_A1; + * blockingConversion.sampleBuffer = sampleBufferOne; + * blockingConversion.sampleBufferTwo = NULL; + * blockingConversion.samplesRequestedCount = ADCBUFFERSIZE; + * + * if (ADCBuf_convert(adcBufHandle, &blockingConversion, 1) != ADCBuf_STATUS_SUCCESS) { + * // handle error + * } + * @endcode + * + * # Instrumentation # + * The ADC driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic ADCBuf operations performed | + * Diags_USER2 | detailed ADCBuf operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_adc_adcbufcc26xx__include +#define ti_drivers_adc_adcbufcc26xx__include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_adc.h) + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @}*/ + +/** + * @addtogroup ADCBuf_CMD + * ADCBufCC26XX_CMD_* macros are command codes only defined in the + * ADCBufCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add ADCBufCC26XX_CMD_* macros here */ + +/*! + * @brief This control function acquires the semaphore that arbitrates access + * to the ADC between the CM3 and the sensor controller + * + * This function pre-acquires the ADC semaphore before ADCBuf_convert() is + * called by the application. Normally, the ADC driver acquires the ADC + * semaphore when calling ADCBufCC26XX_convert(). The driver may need to wait + * for the sensor controller to release the semaphore in order to access the + * ADC hardware module. Consequently, the time at which the conversion is + * actually made is normally non-deterministic. Pre-acquiring the semaphore + * makes the ADCBuf_convert() call deterministic. + * + * @note This function returns an error if the handle is not open or a transfer + * is in progress + */ +#define ADCBufCC26XX_CMD_ACQUIRE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 1 + +/*! + * @brief This function makes the ADC driver keep the ADC semaphore until + * released + * + * Calling this function will make the ADC driver keep the ADC semaphore until + * it is released by the application by calling the control function + * ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE. This enables multiple deterministic + * conversions to be made. Usually, the driver will release the semaphore after + * the conversion finishes. + * + * @warning The sensor controller can no longer access the ADC until the + * semaphore is released by the application manually. + * + * @sa ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE + */ +#define ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 2 + +/*! + * @brief This function makes the ADC driver no longer keep the ADC semaphore + * until released + * + * This function effectively reverses a call to ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE. + * + * @sa ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE + */ +#define ADCBufCC26XX_CMD_KEEP_ADC_SEMAPHORE_DISABLE ADCBuf_CMD_RESERVED + 3 + +/*! + * @brief This function releases the ADC semaphore + * + * @note This function returns an error if the handle is not open or a + * transfer is in progress + */ +#define ADCBufCC26XX_CMD_RELEASE_ADC_SEMAPHORE ADCBuf_CMD_RESERVED + 4 + +/** @}*/ + +/*! + * @brief Resolution in bits of the CC26XX ADC + */ +#define ADCBufCC26XX_RESOLUTION 12 + +#define ADCBufCC26XX_BYTES_PER_SAMPLE 2 + +/* + * ============================================================================= + * Constants + * ============================================================================= + */ + +/* ADCBuf function table pointer */ +extern const ADCBuf_FxnTable ADCBufCC26XX_fxnTable; + +/* + * ============================================================================= + * Enumerations + * ============================================================================= + */ + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from + * the battery voltage or a fixed internal source. + * + * The CC26XX ADC can operate in two different ways with regards to the + * sampling phase of the ADC conversion process: + * - It can spend a fixed amount of time sampling the signal after getting + * the start conversion trigger. + * - It can constantly keep sampling and immediately start the conversion + * process after getting the trigger. + * + * In ADCBufCC26XX_SYNCHRONOUS mode, the ADC goes into IDLE in between + * conversions and uses less power. The minimum sample time for full precision + * in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS is dependent on the input load. + */ +typedef enum +{ + ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS, + ADCBufCC26XX_SAMPING_MODE_ASYNCHRONOUS +} ADCBufCC26XX_Sampling_Mode; + +/*! + * @brief Amount of time the ADC spends sampling the analogue input. + * + * The analogue to digital conversion process consists of two phases in the + * CC26XX ADC, the sampling and conversion phases. During the sampling phase, + * the ADC samples the analogue input signal. Larger input loads require longer + * sample times for the most accurate results. + * In ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS mode, this enum specifies the + * sampling times available. + */ +typedef enum +{ + ADCBufCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS +} ADCBufCC26XX_Sampling_Duration; + +/*! + * @brief Specifies whether the internal reference of the ADC is sourced from + * the battery voltage or a fixed internal source. + * + * - In practice, using the internal fixed voltage reference sets the upper + * range of the ADC to a fixed value. That value is 4.3V with input scaling + * enabled and ~1.4785V with input scaling disabled. In this mode, the output + * is a function of the input voltage multiplied by the resolution in + * alternatives (not bits) divided by the upper voltage range of the ADC. + * Output = Input (V) * 2^12 / (ADC range (V)) + * + * - Using VDDS as a reference scales the upper range of the ADC with the + * battery voltage. As the battery depletes and its voltage drops, so does + * the range of the ADC. This is helpful when measuring signals that are + * generated relative to the battery voltage. In this mode, the output is a + * function of the input voltage multiplied by the resolution in alternatives + * (not bits) divided by VDDS multiplied by a scaling factor derived from the + * input scaling. Output = Input (V) * 2^12 / (VDDS (V) * Scaling factor), + * where the scaling factor is ~1.4785/4.3 for input scaling disabled and 1 + * for input scaling enabled. + * + * @note The actual reference values are slightly different for each device + * and are higher than the values specified above. This gain is saved + * in the FCFG. The function ADCBuf_convertRawToMicroVolts() must be + * used to derive actual voltage values. Do not attempt to compare raw + * values between devices or derive a voltage from them yourself. The + * results of doing so will only be approximately correct. + * + * @warning Even though the upper voltage range of the ADC is 4.3 volts in + * fixed mode with input scaling enabled, the input should never + * exceed VDDS as per the data sheet. + */ +typedef enum +{ + ADCBufCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL +} ADCBufCC26XX_Reference_Source; + +/* + * ============================================================================= + * Structs + * ============================================================================= + */ + +/*! + * @brief Table entry that maps a virtual adc channel to a dio and its + * corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the + * driverlib define corresponding to the desired non-dio signal and dio is set + * to PIN_UNASSIGNED. + */ +typedef struct +{ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ +} ADCBufCC26XX_AdcChannelLutEntry; + +/*! + * @brief CC26XX specfic extension to ADCBuf_Params + * + * To use non-default CC26XX specific parameters when calling ADCBuf_open(), + * a pointer to an instance of this struct must be specified in + * ADCBuf_Params::custom. Alternatively, these values can be set using the + * control function after calling ADCBuf_open(). + */ +typedef struct +{ + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26XX_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the + * entire time since the last conversion */ + ADCBufCC26XX_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the + * battery voltage or a fixed internal source */ + ADCBufCC26XX_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; +} ADCBufCC26XX_ParamsExtension; + +/*! + * @brief ADCBufCC26XX Hardware Attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * A sample structure is shown below: + * @code + * const ADCBufCC26XX_HWAttrs ADCBufCC26XXHWAttrs[] = { + * { + * .intPriority = ~0, + * .swiPriority = 0, + * .gpTimerUnit = CC2650_GPTIMER0A, + * .gptDMAChannelMask = 1 << UDMA_CHAN_TIMER0_A, + * } + * }; + * @endcode + */ +typedef struct +{ + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26XX_AdcChannelLutEntry's mapping internal + * CompBInput to DIO */ + ADCBufCC26XX_AdcChannelLutEntry const *adcChannelLut; +} ADCBufCC26XX_HWAttrs; + +/*! + * @brief ADCBufCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* ADC control variables */ + /*! Has the obj been opened */ + bool isOpen; + /*! Is the ADC currently doing conversions */ + bool conversionInProgress; + /*! Is the analogue input scaled */ + bool inputScalingEnabled; + /*! Should the driver keep the ADC semaphore after a conversion */ + bool keepADCSemaphore; + /*! Does the driver currently possess the ADC semaphore */ + bool adcSemaphoreInPossession; + /*! The current virtual channel the ADCBuf driver is sampling on */ + uint8_t currentChannel; + /*! Reference source for the ADC to use */ + ADCBufCC26XX_Reference_Source refSource; + /*! Synchronous or asynchronous sampling mode */ + ADCBufCC26XX_Sampling_Mode samplingMode; + /*! Time the ADC spends sampling in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS */ + ADCBufCC26XX_Sampling_Duration samplingDuration; + /*! Pointer to callback function */ + ADCBuf_Callback callbackFxn; + /*! Should we convert continuously or one-shot */ + ADCBuf_Recurrence_Mode recurrenceMode; + /*! Mode for all conversions */ + ADCBuf_Return_Mode returnMode; + /*! The last complete sample buffer used by the DMA */ + uint16_t *activeSampleBuffer; + + /* ADC SYS/BIOS objects */ + /*! Hwi object */ + HwiP_Struct hwi; + /*! Swi object */ + SwiP_Struct swi; + /*! ADC semaphore */ + SemaphoreP_Struct conversionComplete; + /*! Pointer to the current conversion struct */ + ADCBuf_Conversion *currentConversion; + + /* PIN driver state object and handle */ + /*! Pin state object */ + PIN_State pinState; + /*! Pin handle */ + PIN_Handle pinHandle; + + /* UDMA driver handle */ + /*! UDMA handle */ + UDMACC26XX_Handle udmaHandle; + + /* GPTimer driver handle */ + /*! Handle to underlying GPTimer peripheral */ + GPTimerCC26XX_Handle timerHandle; + + /*! Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t semaphoreTimeout; + /*! Frequency in Hz at which the ADC is triggered */ + uint32_t samplingFrequency; +} ADCBufCC26XX_Object, *ADCBufCC26XX_Handle; + +/* + * ============================================================================= + * Functions + * ============================================================================= + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_adc_ADCBufCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.c new file mode 100644 index 00000000..5a234692 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.c @@ -0,0 +1,606 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESCBC_s_SecureCallback aescbcSecureCB_ns[]; +extern AESCBCCC26X4_ns_Object aescbcObject_ns[]; + +/* + * ======== AESCBC_ns_callbackFxn ======== + */ +void AESCBC_ns_callbackFxn(uintptr_t arg) +{ + AESCBC_s_SecureCallback *secureCallbackObject = (AESCBC_s_SecureCallback *)arg; + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application */ + aescbcObject_ns[index].callbackFxn(aescbcSecureCB_ns[index].handle, + aescbcSecureCB_ns[index].returnValue, + aescbcSecureCB_ns[index].operation, + aescbcSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESCBC_ns_registerCallback ======== + */ +static psa_status_t AESCBC_ns_registerCallback(AESCBC_Handle handle, const AESCBC_Params *params) +{ + AESCBC_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCallback object */ + SecureCallback_construct(&aescbcSecureCB_ns[index].object, + AESCBC_ns_callbackFxn, + (uintptr_t)&aescbcSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aescbcSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESCBC_init ======== + */ +void AESCBC_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCallback driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESCBC_open ======== + */ +AESCBC_Handle AESCBC_open(uint_least8_t index, const AESCBC_Params *params) +{ + AESCBC_Handle handle = NULL; + AESCBC_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCBC_Params *)&AESCBC_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING)) + { + if (AESCBC_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aescbcObject_ns[index].returnBehavior = params->returnBehavior; + aescbcObject_ns[index].callbackFxn = params->callbackFxn; + aescbcObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCBC_construct ======== + */ +AESCBC_Handle AESCBC_construct(AESCBC_Config *config, const AESCBC_Params *params) +{ + AESCBC_Handle handle = NULL; + AESCBC_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCBC_Params *)&AESCBC_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING)) + { + if (AESCBC_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aescbcObject_ns[index].returnBehavior = params->returnBehavior; + aescbcObject_ns[index].callbackFxn = params->callbackFxn; + aescbcObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCBC_close ======== + */ +void AESCBC_close(AESCBC_Handle handle) +{ + AESCBC_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aescbcSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCBC_oneStepOperation ======== + */ +static int_fast16_t AESCBC_oneStepOperation(AESCBC_Handle handle, + AESCBC_OneStepOperation *operationStruct, + int32_t type) +{ + AESCBC_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operationStruct; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescbcObject_ns[index].semaphoreTimeout) == false) + { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) && (result != AESCBC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescbcSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCBC_oneStepEncrypt ======== + */ +int_fast16_t AESCBC_oneStepEncrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct) +{ + return AESCBC_oneStepOperation(handle, operationStruct, AESCBC_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESCBC_oneStepDecrypt ======== + */ +int_fast16_t AESCBC_oneStepDecrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct) +{ + return AESCBC_oneStepOperation(handle, operationStruct, AESCBC_S_MSG_TYPE_ONE_STEP_DECRYPT); +} + +/* + * ======== AESCBC_setupOperation ======== + */ +static int_fast16_t AESCBC_setupOperation(AESCBC_Handle handle, const CryptoKey *key, int32_t type) +{ + AESCBC_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCBC_setupEncrypt ======== + */ +int_fast16_t AESCBC_setupEncrypt(AESCBC_Handle handle, const CryptoKey *key) +{ + return AESCBC_setupOperation(handle, key, AESCBC_S_MSG_TYPE_SETUP_ENCRYPT); +} + +/* + * ======== AESCBC_setupDecrypt ======== + */ +int_fast16_t AESCBC_setupDecrypt(AESCBC_Handle handle, const CryptoKey *key) +{ + return AESCBC_setupOperation(handle, key, AESCBC_S_MSG_TYPE_SETUP_DECRYPT); +} + +/* + * ======== AESCBC_setIV ======== + */ +int_fast16_t AESCBC_setIV(AESCBC_Handle handle, const uint8_t *iv, size_t ivLength) +{ + AESCBC_s_SetIVMsg setIVMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setIVMsg.handle = handle; + setIVMsg.iv = iv; + setIVMsg.ivLength = ivLength; + invecs[0].base = &setIVMsg; + invecs[0].len = sizeof(setIVMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_SET_IV, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCBC_addData ======== + */ +int_fast16_t AESCBC_addData(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation) +{ + AESCBC_s_AddDataMsg addDataMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescbcObject_ns[index].semaphoreTimeout) == false) + { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) && (result != AESCBC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescbcSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCBC_finalize ======== + */ +int_fast16_t AESCBC_finalize(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation) +{ + AESCBC_s_FinalizeMsg finalizeMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescbcObject_ns[index].semaphoreTimeout) == false) + { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_FINALIZE, invecs, outvecs); + + if ((aescbcObject_ns[index].returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) && (result != AESCBC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescbcObject_ns[index].returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescbcSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCBC_cancelOperation ======== + */ +int_fast16_t AESCBC_cancelOperation(AESCBC_Handle handle) +{ + AESCBC_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESCBC_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCBC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCBC_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCBC_generateIV ======== + */ +int_fast16_t AESCBC_generateIV(AESCBC_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength) +{ + /* This is not currently supported */ + return (AESCBC_STATUS_FEATURE_NOT_SUPPORTED); +} diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.h new file mode 100644 index 00000000..0d7e4e38 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCBCCC26X4_ns.h + * + * @brief AESCBC Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_aescbc_AESCBCCC26X4_ns__include +#define ti_drivers_aescbc_AESCBCCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESCBCCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESCBC_CallbackFxn callbackFxn; + AESCBC_ReturnBehavior returnBehavior; +} AESCBCCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescbc_AESCBCCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.c new file mode 100644 index 00000000..4a3b2aaa --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.c @@ -0,0 +1,1016 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESCBCCC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESCBC_OperationUnion *operation_ns; /* Pointer to non-secure operation */ + AESCBC_OperationUnion operation_s; /* Secure copy of operation */ +} AESCBC_s_Operation; + +static AESCBC_s_Operation AESCBC_s_operation; + +/* + * AES CBC Secure Dynamic Instance struct. + */ +typedef struct +{ + AESCBC_Config config; + AESCBCCC26XX_Object object; + AESCBCCC26XX_HWAttrs hwAttrs; +} AESCBC_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the object + * and hwAttrs that it points to) provided by non-secure calls to + * AESCBC_construct. + */ +static AESCBC_s_DynamicInstance AESCBC_s_dynInstance[CONFIG_AESCBC_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESCBC_s_SecureCallbacks for each driver instance opened or constructed */ +static AESCBC_s_SecureCallback *AESCBC_s_secureCB[AESCBC_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESCBC_Config AESCBC_config[]; + +/* + * ======== AESCBC_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t AESCBC_s_getCallbackIndex(AESCBC_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESCBC_COUNT; index++) + { + if (handle_s == (AESCBC_Handle)&AESCBC_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESCBC_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESCBC_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESCBC_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESCBC_s_hwiCallback ======== + */ +static void AESCBC_s_hwiCallback(AESCBC_Handle handle_s, + int_fast16_t returnValue, + AESCBC_OperationUnion *operation, + AESCBC_OperationType operationType) +{ + int8_t index; + AESCBC_s_SecureCallback *aescbcSecureCB_ns; + + index = AESCBC_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESCBC_SECURE_CALLBACK_COUNT)) + { + aescbcSecureCB_ns = AESCBC_s_secureCB[index]; + + if (aescbcSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aescbcSecureCB_ns->handle = (AESCBC_Handle)(CRYPTO_S_HANDLE_ID_AESCBC | index); + aescbcSecureCB_ns->returnValue = returnValue; + aescbcSecureCB_ns->operation = AESCBC_s_operation.operation_ns; + aescbcSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aescbcSecureCB_ns->object); + } + } +} + +/* + * ======== AESCBC_s_copyConfig ======== + */ +static inline psa_status_t AESCBC_s_copyConfig(AESCBC_Config **secureConfig, + const AESCBC_Config *config, + AESCBC_Handle *retHandle) +{ + AESCBC_Config *config_s; + AESCBC_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESCBC_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESCBC_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCBC_s_secureCB[i + CONFIG_TI_DRIVERS_AESCBC_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESCBC OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESCBC_Handle)(CRYPTO_S_HANDLE_ID_AESCBC | (i + CONFIG_TI_DRIVERS_AESCBC_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESCBC_s_releaseConfig ======== + */ +static inline void AESCBC_s_releaseConfig(AESCBC_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCBC) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESCBC_COUNT) && (i < AESCBC_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESCBC_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCBC_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESCBC_s_copyOneStepOperation ======== + */ +static inline psa_status_t AESCBC_s_copyOneStepOperation(AESCBC_OneStepOperation *secureOperation, + CryptoKey *secureKey, + const AESCBC_OneStepOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCBC_OneStepOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCBC_OneStepOperation)); + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the key struct and update the operation + * struct to point to the secure key copy. + */ + (void)spm_memcpy(secureKey, secureOperation->key, sizeof(CryptoKey)); + secureOperation->key = secureKey; + + if (CryptoKey_verifySecureInputKey(secureOperation->key) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify IV address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->iv, AES_IV_LENGTH_BYTES) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Internal IV generation is currently not supported */ + if (secureOperation->ivInternallyGenerated) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_copySegmentedOperation ======== + */ +static psa_status_t AESCBC_s_copySegmentedOperation(AESCBC_SegmentedOperation *secureOperation, + const AESCBC_SegmentedOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCBC_SegmentedOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCBC_SegmentedOperation)); + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_copyParams ======== + */ +static psa_status_t AESCBC_s_copyParams(AESCBC_Params *secureParams, const AESCBC_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESCBC_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESCBC_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != AESCBC_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESCBC_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESCBC_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESCBC_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESCBC_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESCBC_Handle AESCBC_s_getHandle(AESCBC_Handle nsHandle) +{ + AESCBC_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCBC) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESCBC_COUNT) + { + secureHandle = (AESCBC_Handle)&AESCBC_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESCBC_COUNT) && (i < AESCBC_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESCBC_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCBC_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESCBC_s_registerCallback ======== + */ +static inline psa_status_t AESCBC_s_registerCallback(psa_msg_t *msg) +{ + AESCBC_Handle handle_s; + AESCBC_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESCBC_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESCBC_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESCBC_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESCBC_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESCBC_s_SecureCallback located in + * non-secure memory. + */ + AESCBC_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCBC_s_construct ======== + */ +static inline psa_status_t AESCBC_s_construct(psa_msg_t *msg) +{ + AESCBC_s_ConstructMsg constructMsg; + AESCBC_Handle handle; + AESCBC_Params params_s; + const AESCBC_Params *paramsPtr_s = NULL; + AESCBC_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESCBC_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESCBC_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESCBC_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESCBC_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_open ======== + */ +static inline psa_status_t AESCBC_s_open(psa_msg_t *msg) +{ + AESCBC_s_OpenMsg openMsg; + AESCBC_Handle handle; + AESCBC_Params params_s; + AESCBC_Params *paramsPtr_s = NULL; + AESCBC_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESCBC_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESCBC_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCBC_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESCBC OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESCBC_Handle)(CRYPTO_S_HANDLE_ID_AESCBC | openMsg.index); + } + else + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_close ======== + */ +static inline psa_status_t AESCBC_s_close(psa_msg_t *msg) +{ + AESCBC_Handle handle_s; + AESCBC_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESCBC_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESCBC_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESCBC_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_oneStepOperation ======== + */ +static inline psa_status_t AESCBC_s_oneStepOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCBC_s_OneStepOperationMsg oneStepMsg; + AESCBC_Handle handle_s; + AESCBC_OneStepOperation *operation_s; + CryptoKey key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(oneStepMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &oneStepMsg, sizeof(oneStepMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(oneStepMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCBC_s_operation.operation_s.oneStepOperation; + + /* Save pointer to non-secure operation struct */ + AESCBC_s_operation.operation_ns = (AESCBC_OperationUnion *)oneStepMsg.operation; + + /* Validate and copy operation and key structs */ + status = AESCBC_s_copyOneStepOperation(operation_s, &key_s, oneStepMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = oneStepMsg.handle; + operation_s = oneStepMsg.operation; + } + + if (msgType == AESCBC_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + ret = AESCBC_oneStepEncrypt(handle_s, operation_s); + } + else + { + ret = AESCBC_oneStepDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCBC_s_setupOperation ======== + */ +static inline psa_status_t AESCBC_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCBC_s_SetupOperationMsg setupMsg; + AESCBC_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESCBC_S_MSG_TYPE_SETUP_ENCRYPT) + { + ret = AESCBC_setupEncrypt(handle_s, keyPtr_s); + } + else + { + ret = AESCBC_setupDecrypt(handle_s, keyPtr_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_setIV ======== + */ +static inline psa_status_t AESCBC_s_setIV(psa_msg_t *msg) +{ + AESCBC_Handle handle_s; + AESCBC_s_SetIVMsg setIVMsg; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setIVMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setIVMsg, sizeof(setIVMsg)); + + if ((setIVMsg.iv == NULL) || (setIVMsg.ivLength != AES_IV_LENGTH_BYTES)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(setIVMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify IV address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setIVMsg.iv, setIVMsg.ivLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = setIVMsg.handle; + } + + ret = AESCBC_setIV(handle_s, setIVMsg.iv, setIVMsg.ivLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_addData ======== + */ +static inline psa_status_t AESCBC_s_addData(psa_msg_t *msg) +{ + AESCBC_Handle handle_s; + AESCBC_SegmentedOperation *operation_s; + AESCBC_s_AddDataMsg addDataMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCBC_s_operation.operation_s.segmentedOperation; + + /* Save pointer to non-secure operation struct */ + AESCBC_s_operation.operation_ns = (AESCBC_OperationUnion *)addDataMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCBC_s_copySegmentedOperation(operation_s, addDataMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCBC_addData(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCBC_addData(addDataMsg.handle, addDataMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCBC_s_finalizeOperation ======== + */ +static inline psa_status_t AESCBC_s_finalizeOperation(psa_msg_t *msg) +{ + AESCBC_s_FinalizeMsg finalizeMsg; + AESCBC_SegmentedOperation *operation_s; + AESCBC_Handle handle_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCBC_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCBC_s_operation.operation_s.segmentedOperation; + + /* Save pointer to non-secure operation struct */ + AESCBC_s_operation.operation_ns = (AESCBC_OperationUnion *)finalizeMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCBC_s_copySegmentedOperation(operation_s, finalizeMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCBC_finalize(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCBC_finalize(finalizeMsg.handle, finalizeMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCBC_s_cancelOperation ======== + */ +static inline psa_status_t AESCBC_s_cancelOperation(psa_msg_t *msg) +{ + AESCBC_Handle handle_s; + AESCBC_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESCBC_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESCBC_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCBC_s_handlePsaMsg ======== + */ +psa_status_t AESCBC_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESCBC_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESCBC_S_MSG_TYPE_CONSTRUCT: + status = AESCBC_s_construct(msg); + break; + + case AESCBC_S_MSG_TYPE_OPEN: + status = AESCBC_s_open(msg); + break; + + /* + * AESCBC_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESCBC_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESCBC_s_registerCallback(msg); + break; + + case AESCBC_S_MSG_TYPE_CLOSE: + status = AESCBC_s_close(msg); + break; + + case AESCBC_S_MSG_TYPE_ONE_STEP_DECRYPT: /* Fall through */ + case AESCBC_S_MSG_TYPE_ONE_STEP_ENCRYPT: + status = AESCBC_s_oneStepOperation(msg, msg->type); + break; + + case AESCBC_S_MSG_TYPE_SETUP_ENCRYPT: /* Fall through */ + case AESCBC_S_MSG_TYPE_SETUP_DECRYPT: + status = AESCBC_s_setupOperation(msg, msg->type); + break; + + case AESCBC_S_MSG_TYPE_SET_IV: + status = AESCBC_s_setIV(msg); + break; + + case AESCBC_S_MSG_TYPE_ADD_DATA: + status = AESCBC_s_addData(msg); + break; + + case AESCBC_S_MSG_TYPE_FINALIZE: + status = AESCBC_s_finalizeOperation(msg); + break; + + /* + * AESCBC_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESCBC_S_MSG_TYPE_CANCEL_OPERATION: + status = AESCBC_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESCBC_s_init ======== + */ +void AESCBC_s_init(void) +{ + AESCBC_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.h new file mode 100644 index 00000000..0ddb9170 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26X4_s.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aescbc_AESCBCCC26X4_s__include +#define ti_drivers_aescbc_AESCBCCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES CBC secure message types + */ +#define AESCBC_S_MSG_TYPE_CONSTRUCT AESCBC_S_MSG_TYPE(0U) +#define AESCBC_S_MSG_TYPE_OPEN AESCBC_S_MSG_TYPE(1U) +#define AESCBC_S_MSG_TYPE_REGISTER_CALLBACK AESCBC_S_MSG_TYPE(2U) +#define AESCBC_S_MSG_TYPE_CLOSE AESCBC_S_MSG_TYPE(3U) +#define AESCBC_S_MSG_TYPE_ONE_STEP_ENCRYPT AESCBC_S_MSG_TYPE(4U) +#define AESCBC_S_MSG_TYPE_ONE_STEP_DECRYPT AESCBC_S_MSG_TYPE(5U) +#define AESCBC_S_MSG_TYPE_SETUP_ENCRYPT AESCBC_S_MSG_TYPE(6U) +#define AESCBC_S_MSG_TYPE_SETUP_DECRYPT AESCBC_S_MSG_TYPE(7U) +#define AESCBC_S_MSG_TYPE_SET_IV AESCBC_S_MSG_TYPE(8U) +#define AESCBC_S_MSG_TYPE_ADD_DATA AESCBC_S_MSG_TYPE(9U) +#define AESCBC_S_MSG_TYPE_FINALIZE AESCBC_S_MSG_TYPE(10U) +#define AESCBC_S_MSG_TYPE_CANCEL_OPERATION AESCBC_S_MSG_TYPE(11U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESCBC_construct(). + */ +#ifndef CONFIG_AESCBC_S_CONFIG_POOL_SIZE + #define CONFIG_AESCBC_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESCBC_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESCBC_COUNT + CONFIG_AESCBC_S_CONFIG_POOL_SIZE) + +/* + * ========= AES CBC Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES CBC callback fxn parameters */ + AESCBC_Handle handle; + int_fast16_t returnValue; + AESCBC_OperationUnion *operation; + AESCBC_OperationType operationType; +} AESCBC_s_SecureCallback; + +/* + * ========= AES CBC Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES CBC secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESCBC_Config *config; + const AESCBC_Params *params; +} AESCBC_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESCBC_Params *params; +} AESCBC_s_OpenMsg; + +typedef struct +{ + AESCBC_Handle handle; + AESCBC_s_SecureCallback *callback; +} AESCBC_s_CallbackMsg; + +typedef struct +{ + AESCBC_Handle handle; +} AESCBC_s_CloseMsg; + +typedef struct +{ + AESCBC_Handle handle; + AESCBC_OneStepOperation *operation; +} AESCBC_s_OneStepOperationMsg; + +typedef struct +{ + AESCBC_Handle handle; + const CryptoKey *key; +} AESCBC_s_SetupOperationMsg; + +typedef struct +{ + AESCBC_Handle handle; + const uint8_t *iv; + size_t ivLength; +} AESCBC_s_SetIVMsg; + +typedef struct +{ + AESCBC_Handle handle; + AESCBC_SegmentedOperation *operation; +} AESCBC_s_AddDataMsg; + +typedef AESCBC_s_AddDataMsg AESCBC_s_FinalizeMsg; + +typedef struct +{ + AESCBC_Handle handle; +} AESCBC_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for AES CBC secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESCBC_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES CBC secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESCBC_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescbc_AESCBCCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.c b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.c new file mode 100644 index 00000000..790d1274 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.c @@ -0,0 +1,1006 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0F + +/* Forward declarations */ +static void AESCBC_hwiFxn(uintptr_t arg0); +static int_fast16_t AESCBC_startOperation(AESCBC_Handle handle, + AESCBC_OneStepOperation *operation, + AESCBC_OperationType operationType); +static int_fast16_t AESCBC_waitForResult(AESCBC_Handle handle); +static void AESCBC_cleanup(AESCBCCC26XX_Object *object); +static int_fast16_t AESCBC_addDataInternal(AESCBC_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESCBC_Mode direction); +static int_fast16_t AESCBC_setupSegmentedOperation(AESCBC_Handle handle, const CryptoKey *key); +static int_fast16_t AESCBC_setOperationInProgress(AESCBCCC26XX_Object *object); + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESCBC_hwiFxn ======== + */ +static void AESCBC_hwiFxn(uintptr_t arg0) +{ + AESCBCCC26XX_Object *object = ((AESCBC_Handle)arg0)->object; + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Mark that we are done with the operation so that AESCBC_cancelOperation + * knows not to try canceling. + */ + object->hwBusy = false; + + if (object->operationType != AESCBC_OP_TYPE_DECRYPT_SEGMENTED && + object->operationType != AESCBC_OP_TYPE_ENCRYPT_SEGMENTED) + { + /* One shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCBC_STATUS_ERROR; + } + else + { + if (AESGetCtrl() & CRYPTO_AESCTL_SAVE_CONTEXT_M) + { + /* + * Store the new iv into object for the next block should we want to + * continue the chain of blocks in a later segmented operation. + */ + AESReadNonAuthenticationModeIV(object->iv); + } + else + { + /* + * For one-shot and finalize operations, clear the IV buffer + * to prevent data leakage + */ + CryptoUtils_memset(object->iv, sizeof(object->iv), 0, sizeof(object->iv)); + } + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_BUS_ERR); + + /* + * Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + * + * When the access semaphore is freed during cleanup, + * if a higher priority ISR shares this driver instance and wishes + * to start a new operation, it must handle synchronization with + * the other thread(s) sharing this driver instance to avoid + * corrupting the driver's object data by starting a new operation + * before the callback is executed for the current operation. + */ + AESCBC_cleanup(object); + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn((AESCBC_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCBC_cleanup ======== + */ +static void AESCBC_cleanup(AESCBCCC26XX_Object *object) +{ + /* + * Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* + * This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + if (object->cryptoResourceLocked) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } +} + +/* + * ======== AESCBC_init ======== + */ +void AESCBC_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCBC_construct ======== + */ +AESCBC_Handle AESCBC_construct(AESCBC_Config *config, const AESCBC_Params *params) +{ + AESCBC_Handle handle; + AESCBCCC26XX_Object *object; + uintptr_t key; + + handle = config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESCBC_Params *)&AESCBC_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + + if (params->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + object->semaphoreTimeout = params->timeout; + } + else + { + object->semaphoreTimeout = SemaphoreP_NO_WAIT; + } + + object->threadSafe = true; + object->cryptoResourceLocked = false; + object->hwBusy = false; + object->operationInProgress = false; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCBC_close ======== + */ +void AESCBC_close(AESCBC_Handle handle) +{ + AESCBCCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCBC_startOperation ======== + */ +static int_fast16_t AESCBC_startOperation(AESCBC_Handle handle, + AESCBC_OneStepOperation *operation, + AESCBC_OperationType operationType) +{ + /* + * Even though this function is not public, assert handle and operation + * since those are used in this function + */ + DebugP_assert(handle); + DebugP_assert(operation); + + /* Internal generation of IVs is currently not supported */ + DebugP_assert(!operation->ivInternallyGenerated); + + AESCBCCC26XX_Object *object = handle->object; + + int_fast16_t result = AESCBC_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESCBC_setOperationInProgress(object); + + if (result != AESCBC_STATUS_SUCCESS) + { + return result; + } + + AESCBC_Mode direction = AESCBC_MODE_ENCRYPT; + + if (operationType == AESCBC_OPERATION_TYPE_DECRYPT) + { + direction = AESCBC_MODE_DECRYPT; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + object->operationInProgress = false; + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operation = (AESCBC_OperationUnion *)operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESCBC_STATUS_SUCCESS; + + memcpy(object->iv, operation->iv, sizeof(object->iv)); + + object->key = *(operation->key); + + result = AESCBC_addDataInternal(handle, operation->input, operation->output, operation->inputLength, direction); + + if ((result != AESCBC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + return result; +} + +/* + * ======== AESCBC_setOperationInProgress ======== + */ +static int_fast16_t AESCBC_setOperationInProgress(AESCBCCC26XX_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + + return AESCBC_STATUS_ERROR; + } + + object->operationInProgress = true; + + HwiP_restore(interruptKey); + + return AESCBC_STATUS_SUCCESS; +} + +/* + * ======== AESCBC_waitForResult ======== + */ +static int_fast16_t AESCBC_waitForResult(AESCBC_Handle handle) +{ + AESCBCCC26XX_Object *object = handle->object; + + int_fast16_t result = AESCBC_STATUS_ERROR; + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCBC_STATUS_ERROR; + } + else + { + if (AESGetCtrl() & CRYPTO_AESCTL_SAVE_CONTEXT_M) + { + /* + * Store the new iv into object for the next block should we want to + * continue the chain of blocks in a later segmented operation. + */ + AESReadNonAuthenticationModeIV(object->iv); + } + else + { + /* + * For one-shot or finalize operations, clear the IV buffer + * to prevent data leakage + */ + CryptoUtils_memset((uint8_t *)object->iv, sizeof(object->iv), 0, sizeof(object->iv)); + } + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + if (object->operationType != AESCBC_OP_TYPE_DECRYPT_SEGMENTED && + object->operationType != AESCBC_OP_TYPE_ENCRYPT_SEGMENTED) + { + /* One shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESCBC_cleanup(object); + } + else if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + /* Success is always returned in callback mode */ + result = AESCBC_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESCBC_oneStepEncrypt ======== + */ +int_fast16_t AESCBC_oneStepEncrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct) +{ + + return AESCBC_startOperation(handle, operationStruct, AESCBC_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCBC_oneStepDecrypt ======== + */ +int_fast16_t AESCBC_oneStepDecrypt(AESCBC_Handle handle, AESCBC_OneStepOperation *operationStruct) +{ + + return AESCBC_startOperation(handle, operationStruct, AESCBC_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCBC_setupSegmentedOperation ======== + */ +static int_fast16_t AESCBC_setupSegmentedOperation(AESCBC_Handle handle, const CryptoKey *key) +{ + /* + * Not all of the input values will be asserted here since they will be + * asserted/checked later. Asserts checking the key's validity will occur + * in addDataInternal for maintainability purposes. + */ + DebugP_assert(handle); + + AESCBCCC26XX_Object *object = handle->object; + + int_fast16_t result = AESCBC_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESCBC_setOperationInProgress(object); + + if (result != AESCBC_STATUS_ERROR) + { + object->key = *key; + /* returnStatus is changed in the case of an error or cancellation */ + object->returnStatus = AESCBC_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESCBC_setupEncrypt ======== + */ +int_fast16_t AESCBC_setupEncrypt(AESCBC_Handle handle, const CryptoKey *key) +{ + int_fast16_t result = AESCBC_setupSegmentedOperation(handle, key); + + if (result != AESCBC_STATUS_ERROR) + { + AESCBCCC26XX_Object *object = handle->object; + object->operationType = AESCBC_OP_TYPE_ENCRYPT_SEGMENTED; + } + + return result; +} + +/* + * ======== AESCBC_setupDecrypt ======== + */ +int_fast16_t AESCBC_setupDecrypt(AESCBC_Handle handle, const CryptoKey *key) +{ + int_fast16_t result = AESCBC_setupSegmentedOperation(handle, key); + + if (result != AESCBC_STATUS_ERROR) + { + AESCBCCC26XX_Object *object = handle->object; + object->operationType = AESCBC_OP_TYPE_DECRYPT_SEGMENTED; + } + + return result; +} + +/* + * ======== AESCBC_setIV ======== + */ +int_fast16_t AESCBC_setIV(AESCBC_Handle handle, const uint8_t *iv, size_t ivLength) +{ + /* Public accesible functions should check inputs */ + DebugP_assert(handle); + DebugP_assert(iv); + + AESCBCCC26XX_Object *object = handle->object; + + /* Don't continue the operation if there was an error or cancellation */ + if (object->returnStatus != AESCBC_STATUS_SUCCESS) + { + return object->returnStatus; + } + + /* This function is reserved for segmented operations only */ + DebugP_assert(object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESCBC_OP_TYPE_ENCRYPT_SEGMENTED); + + /* The length of the new IV should be 16 or AES_BLOCK_SIZE bytes */ + if (ivLength != AES_BLOCK_SIZE) + { + return AESCBC_STATUS_ERROR; + } + + /* + * Copy the user-provided IV to the object structure since the IV in + * operation struct is reserved for one-shot operations only + */ + memcpy(object->iv, iv, sizeof(object->iv)); + + return AESCBC_STATUS_SUCCESS; +} + +/* + * ======== AESCBC_generateIV ======== + */ +int_fast16_t AESCBC_generateIV(AESCBC_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength) +{ + /* This is not currently supported */ + return AESCBC_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESCBC_addData ======== + */ +int_fast16_t AESCBC_addData(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCBCCC26XX_Object *object = handle->object; + + /* Don't continue the operation if there was an error or cancellation */ + if (object->returnStatus != AESCBC_STATUS_SUCCESS) + { + return object->returnStatus; + } + + DebugP_assert(object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESCBC_OP_TYPE_ENCRYPT_SEGMENTED); + + AESCBC_Mode direction = AESCBC_MODE_ENCRYPT; + if (object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED) + { + direction = AESCBC_MODE_DECRYPT; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + /* + * Reload the operation struct, there's no guarantee that this remains the + * same in between calls + */ + object->operation = (AESCBC_OperationUnion *)operation; + + int_fast16_t result = AESCBC_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + direction); + + if ((result != AESCBC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + + return result; +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== AESCBC_getKeyStoreKeyUsage ======== + */ +static KeyStore_PSA_KeyUsage AESCBC_getKeyStoreKeyUsage(AESCBC_Mode direction) +{ + switch (direction) + { + case AESCBC_MODE_ENCRYPT: + return KEYSTORE_PSA_KEY_USAGE_ENCRYPT; + + case AESCBC_MODE_DECRYPT: + return KEYSTORE_PSA_KEY_USAGE_DECRYPT; + + default: + return 0; + } +} +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +/* + * ======== AESCBC_addDataInternal ======== + */ +static int_fast16_t AESCBC_addDataInternal(AESCBC_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESCBC_Mode direction) +{ + /* Check for these since the function uses them */ + DebugP_assert(handle); + DebugP_assert(input); + DebugP_assert(output); + + AESCBCCC26XX_Object *object = handle->object; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* + * The key is provided as an input in setupEncrypt/Decrypt() + * and within the input operation struct for oneStepEncrypt/Decrypt(), + * and users should check those inputs. + */ + DebugP_assert(object->key); + + /* Only plaintext and KeyStore CryptoKeys are supported for now */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESCBC_getKeyStoreKeyUsage(direction); + + if (!keyUsage) + { + return AESCBC_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_CBC_NO_PADDING, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESCBC_STATUS_KEYSTORE_INVALID_ID; + } + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESCBC_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESCBC_STATUS_FEATURE_NOT_SUPPORTED; + } + + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + if (inputLength == 0 || (inputLength & AES_NON_BLOCK_MULTIPLE_MASK)) + { + return AESCBC_STATUS_ERROR; + } + + AESCBCCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCBC_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at + * a hardcoded and reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + return AESCBC_STATUS_ERROR; + } + + /* + * DMA_IN_DONE must be disabled, since hwiFxn() is assuming that + * the interrupt source is RESULT_AVAIL + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* + * If we are in AESCBC_RETURN_BEHAVIOR_POLLING, we do not want an + * interrupt to trigger. AESWriteToKeyStore() disables and then re-enables + * the CRYPTO IRQ in the NVIC so we need to disable it + * before kicking off the operation. + */ + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_POLLING) + { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks of + * the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in + * the keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + AESSelectAlgorithm(0); + + return AESCBC_STATUS_ERROR; + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESSetInitializationVector(object->iv); + + uint32_t ctrlVal = CRYPTO_AESCTL_CBC | (direction == AESCBC_MODE_ENCRYPT ? CRYPTO_AESCTL_DIR : 0); + + if (object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESCBC_OP_TYPE_ENCRYPT_SEGMENTED) + { + /* Save the context to continue a segmented operation */ + ctrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + } + + AESSetCtrl(ctrlVal); + + AESSetDataLength(inputLength); + AESSetAuthLength(0); + + object->hwBusy = true; + + AESStartDMAOperation(input, inputLength, output, inputLength); + + return AESCBC_waitForResult(handle); +} + +/* + * ======== AESCBC_finalize ======== + */ +int_fast16_t AESCBC_finalize(AESCBC_Handle handle, AESCBC_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCBCCC26XX_Object *object = handle->object; + + /* Don't continue the operation if there was an error or cancellation */ + if (object->returnStatus != AESCBC_STATUS_SUCCESS) + { + return object->returnStatus; + } + + DebugP_assert(object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESCBC_OP_TYPE_ENCRYPT_SEGMENTED); + + AESCBC_OperationType operationType = AESCBC_OP_TYPE_FINALIZE_ENCRYPT_SEGMENTED; + AESCBC_Mode direction = AESCBC_MODE_ENCRYPT; + + if (object->operationType == AESCBC_OP_TYPE_DECRYPT_SEGMENTED) + { + operationType = AESCBC_OP_TYPE_FINALIZE_DECRYPT_SEGMENTED; + direction = AESCBC_MODE_DECRYPT; + } + + int_fast16_t result = AESCBC_STATUS_SUCCESS; + + if (operation->inputLength > 0) + { + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCBC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + /* + * operationType in Object should be updated to a finalize type + * for the application callback + */ + object->operationType = operationType; + object->operation = (AESCBC_OperationUnion *)operation; + + result = AESCBC_addDataInternal(handle, operation->input, operation->output, operation->inputLength, direction); + + if ((result != AESCBC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + } + else + { + /* Clear the IV buffer to prevent data leakage */ + CryptoUtils_memset(object->iv, sizeof(object->iv), 0, sizeof(object->iv)); + + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new segmented operation after operationInProgress is + * cleared + */ + result = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, result, (AESCBC_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + result = AESCBC_STATUS_SUCCESS; + } + } + + return result; +} + +/* + * ======== AESCBC_cancelOperation ======== + */ +int_fast16_t AESCBC_cancelOperation(AESCBC_Handle handle) +{ + AESCBCCC26XX_Object *object = handle->object; + + /* Cancel is only supported for callback mode */ + if (object->returnBehavior != AESCBC_RETURN_BEHAVIOR_CALLBACK) + { + return AESCBC_STATUS_ERROR; + } + + uintptr_t key; + key = HwiP_disable(); + + if (!object->hwBusy) + { + object->returnStatus = AESCBC_STATUS_CANCELED; + object->operationInProgress = false; + + HwiP_restore(key); + + /* A success should be returned if no hw operations are in progress */ + return AESCBC_STATUS_SUCCESS; + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(key); + + /* + * The IV buffer in Object should be cleared if a segmented operation is + * taking place for security purposes + */ + CryptoUtils_memset(object->iv, sizeof(object->iv), 0, sizeof(object->iv)); + + bool clearedIV = CryptoUtils_isBufferAllZeros(object->iv, AES_BLOCK_SIZE); + + int_fast16_t result = AESCBC_STATUS_SUCCESS; + + if (!clearedIV) + { + result = AESCBC_STATUS_ERROR; + } + + AESDMAReset(); + + AESReset(); + + /* + * Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * The operation in progress states should be cleared so that the user + * can start another operation after canceling + */ + object->returnStatus = AESCBC_STATUS_CANCELED; + object->operationInProgress = false; + object->hwBusy = false; + + if (object->returnBehavior == AESCBC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, AESCBC_STATUS_CANCELED, object->operation, object->operationType); + } + + AESCBC_cleanup(object); + + return result; +} + +bool AESCBC_acquireLock(AESCBC_Handle handle, uint32_t timeout) +{ + return CryptoResourceCC26XX_acquireLock(timeout); +} + +void AESCBC_releaseLock(AESCBC_Handle handle) +{ + CryptoResourceCC26XX_releaseLock(); +} + +void AESCBC_enableThreadSafety(AESCBC_Handle handle) +{ + AESCBCCC26XX_Object *object = handle->object; + + object->threadSafe = true; +} +void AESCBC_disableThreadSafety(AESCBC_Handle handle) +{ + AESCBCCC26XX_Object *object = handle->object; + + object->threadSafe = false; +} diff --git a/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.h b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.h new file mode 100644 index 00000000..9eb59fc4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescbc/AESCBCCC26XX.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2018-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCBCCC26XX.h + * + * @brief AESCBC driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the AESCBC_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CBC. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aescbc_AESCBCCC26XX__include +#define ti_drivers_aescbc_AESCBCCC26XX__include + +#include +#include + +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESCBCCC26XX Hardware Attributes + * + * AESCBC26XX hardware attributes should be included in the board file + * and pointed to by the AESCBC_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESCBCCC26XX_HWAttrs; + +/*! + * @brief AESCBCCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t iv[AES_BLOCK_SIZE / 4]; + uint32_t semaphoreTimeout; + AESCBC_CallbackFxn callbackFxn; + AESCBC_OperationUnion *operation; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESCBC_ReturnBehavior returnBehavior; + AESCBC_OperationType operationType; + bool isOpen; + volatile bool operationInProgress; + bool threadSafe; + volatile bool hwBusy; + volatile bool cryptoResourceLocked; +} AESCBCCC26XX_Object; + +/*! + * @cond NODOC + * @brief Non-public functions required by other drivers + * + * The functions may be required by other drivers and are required to + * ensure thread-safe behavior across multiple calls. + */ +bool AESCBC_acquireLock(AESCBC_Handle handle, uint32_t timeout); +void AESCBC_releaseLock(AESCBC_Handle handle); +void AESCBC_enableThreadSafety(AESCBC_Handle handle); +void AESCBC_disableThreadSafety(AESCBC_Handle handle); +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescbc_AESCBCCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.c b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.c new file mode 100644 index 00000000..512c2fb6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.c @@ -0,0 +1,1917 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0F + +/* Forward declarations */ +static void AESCCM_generateIntermediateDigest(AESCCM_Handle handle); +static uint32_t AESGetDefaultCCMCtrlValue(uint32_t nonceLength, uint32_t macLength, bool encrypt); +static void AESCCM_hwiFxn(uintptr_t arg0); +static void AESCCM_cleanup(AESCCMCC26X4_Object *object); +static void AESCCM_getResult(AESCCM_Handle handle); +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType); +static int_fast16_t AESCCM_setOperationInProgress(AESCCMCC26X4_Object *object); +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle); +static int_fast16_t AESCCM_waitForDMAInDone(AESCCM_Handle handle); +static int_fast16_t AESCCM_setupSegmentedOperation(AESCCM_Handle handle, + const CryptoKey *key, + size_t aadLength, + size_t plaintextLength, + size_t macLength); +static int_fast16_t AESCCM_addAADInternal(AESCCM_Handle handle, uint8_t *aad, size_t aadLength, AESCCM_Mode direction); +static int_fast16_t AESCCM_addDataInternal(AESCCM_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESCCM_Mode direction); + +/* Static globals */ +static bool isInitialized = false; + +static void AESCCM_generateIntermediateDigest(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object = handle->object; + + uint32_t ctrlVal = AESGetDefaultCCMCtrlValue(object->nonceLength, + object->macLength, + object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + /* + * Setting get_digest allows an intermediate digest to be generated. + * This is necessary so that the saved context ready bit is set, + * and the intermediate values can be read. + */ + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GET_DIGEST); +} + +/* Function for configuring CCM mode in the AESCTL register */ +static uint32_t AESGetDefaultCCMCtrlValue(uint32_t nonceLength, uint32_t macLength, bool encrypt) +{ + uint32_t ctrlVal = 0; + + ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); + if (macLength >= 2) + { + ctrlVal |= (((macLength - 2) >> 1) << CRYPTO_AESCTL_CCM_M_S); + } + ctrlVal |= CRYPTO_AESCTL_CCM | CRYPTO_AESCTL_CTR | CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + return (ctrlVal); +} + +/* + * ======== AESCCM_hwiFxn ======== + */ +static void AESCCM_hwiFxn(uintptr_t arg0) +{ + AESCCMCC26X4_Object *object = ((AESCCM_Handle)arg0)->object; + + /* Propagate the DMA error from driverlib to the application */ + uint32_t irqStatus = AESIntStatusRaw(); + + if (irqStatus & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCCM_STATUS_ERROR; + } + else + { + /* Generate an intermediate digest if there is leftover data to process */ + if ((object->actualAADLength != object->expectedAADLength) || + (object->actualPlaintextLength != object->expectedPlaintextLength)) + { + AESCCM_generateIntermediateDigest((AESCCM_Handle)arg0); + } + } + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Mark that we are done with the operation so that AESCCM_cancelOperation + * knows not to try canceling. + */ + object->hwBusy = false; + + if (object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + if (object->returnStatus != AESCCM_STATUS_ERROR) + { + /* + * Read out the intermediate values. If a finalize or one-shot + * operation is occurring, the tag is read out and verified against + * a provided MAC or stored + */ + AESCCM_getResult((AESCCM_Handle)arg0); + + /* + * Clear the pending interrupt from setting get_digest when generating + * an intermediate digest + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + * + * When the access semaphore is freed during cleanup, + * if a higher priority ISR shares this driver instance and wishes + * to start a new operation, it must handle synchronization with + * the other thread(s) sharing this driver instance to avoid + * corrupting the driver's object data by starting a new operation + * before the callback is executed for the current operation. + */ + AESCCM_cleanup(object); + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESCCM_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +static void AESCCM_cleanup(AESCCMCC26X4_Object *object) +{ + /* + * Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use without + * reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* + * This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides + * small power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the + * chaining of operations. + */ + if (object->cryptoResourceLocked) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } +} + +static void AESCCM_getResult(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object = handle->object; + + /* + * The ISR is not reached in polling mode, and generating an + * intermediate digest is necessary if these is more data to process + */ + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + /* Generate an intermediate digest if there is leftover data to process */ + if ((object->actualAADLength != object->expectedAADLength) || + (object->actualPlaintextLength != object->expectedPlaintextLength)) + { + AESCCM_generateIntermediateDigest(handle); + } + } + + /* + * If we have done a HW operation, read the intermediate values from + * the HW to successfully continue future operations. + */ + if (object->continueAADOperation || object->continueDataOperation) + { + /* Read the tag, this will clear the saved context ready bit */ + AESReadTag((uint8_t *)object->intermediateTag, AES_BLOCK_SIZE); + + /* Read the block counter */ + object->blockCounter = AESGetBlockCounter(); + + /* Read the IV, must be read after the tag. */ + AESReadAuthenticationModeIV(object->intermediateIV); + + if (object->continueAADOperation) + { + /* Read the CCM align data word (for AAD) */ + object->alignmentInfo = AESGetCCMAlignWord(); + + if (object->actualAADLength == object->expectedAADLength) + { + object->continueAADOperation = false; + } + } + + if (object->actualPlaintextLength == object->expectedPlaintextLength) + { + object->continueDataOperation = false; + } + } + + /* Make sure that the operation can be finalized at this point */ + if ((object->actualAADLength == object->expectedAADLength) && + (object->actualPlaintextLength == object->expectedPlaintextLength)) + { + uint8_t *mac = NULL; + uint8_t macLength = 0; + + if (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) + { + mac = object->operation->oneStepOperation.mac; + macLength = object->operation->oneStepOperation.macLength; + } + else if (object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT) + { + mac = object->operation->segmentedFinalizeOperation.mac; + macLength = object->operation->segmentedFinalizeOperation.macLength; + } + + /* + * We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT) + { + /* + * If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + memcpy(mac, object->intermediateTag, macLength); + } + else if (object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT) + { + /* + * If we are decrypting and verifying a message, we must now verify that + * the provided MAC matches the one calculated in the decryption + * operation. + */ + bool macValid = CryptoUtils_buffersMatch((uint8_t *)object->intermediateTag, mac, macLength); + + if (!macValid) + { + object->returnStatus = AESCCM_STATUS_MAC_INVALID; + } + } + + /* + * Clear intermediate buffers to prevent leakage for one-shot + * or finalize operations + */ + if (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT) + { + CryptoUtils_memset(object->intermediateIV, + sizeof(object->intermediateIV), + 0, + sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + } + } +} + +/* + * ======== AESCCM_init ======== + */ +void AESCCM_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCCM_construct ======== + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params) +{ + AESCCM_Handle handle; + AESCCMCC26X4_Object *object; + uint_fast8_t key; + + handle = (AESCCM_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESCCM_Params *)&AESCCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING ? params->timeout + : SemaphoreP_NO_WAIT; + + object->cryptoResourceLocked = false; + object->hwBusy = false; + object->operationInProgress = false; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCCM_close ======== + */ +void AESCCM_close(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCCM_startOperation ======== + */ +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + AESCCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMCC26X4_Object *object = handle->object; + + /* Internally generated nonces aren't supported for now */ + DebugP_assert(!operation->nonceInternallyGenerated); + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESCCM_setOperationInProgress(object); + + if (result != AESCCM_STATUS_SUCCESS) + { + return (result); + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + object->operationInProgress = false; + return (AESCCM_STATUS_RESOURCE_UNAVAILABLE); + } + else + { + object->cryptoResourceLocked = true; + } + + object->returnStatus = AESCCM_STATUS_SUCCESS; + + result = AESCCM_setLengths(handle, operation->aadLength, operation->inputLength, operation->macLength); + + if (result != AESCCM_STATUS_ERROR) + { + result = AESCCM_setNonce(handle, operation->nonce, operation->nonceLength); + + if (result != AESCCM_STATUS_ERROR) + { + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + + if (operationType == AESCCM_OPERATION_TYPE_DECRYPT) + { + direction = AESCCM_MODE_DECRYPT; + } + + object->operationType = operationType; + object->operation = (AESCCM_OperationUnion *)operation; + + object->key = *(operation->key); + + /* Start processing from a clean slate */ + object->blockCounter = 0; + object->alignmentInfo = 0; + + object->continueAADOperation = false; + object->continueDataOperation = false; + + object->actualAADLength = 0; + object->actualPlaintextLength = 0; + + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + + if (operation->aadLength > 0) + { + /* + * If there is remaining payload data, it will be processed + * in addAADInternal. One-shot operations must process AAD + * and payload data in one go. For one-shot operations, the + * access semaphore shouldn't be released in between + * processing AAD and payload data since another thread + * could take the semaphore and corrupt the Object + */ + result = AESCCM_addAADInternal(handle, operation->aad, operation->aadLength, direction); + } + else if (operation->inputLength > 0) + { + result = AESCCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + direction); + } + } + } + + if ((result != AESCCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + return (result); +} + +/* + * ======== AESCCM_setOperationInProgress ======== + */ +static int_fast16_t AESCCM_setOperationInProgress(AESCCMCC26X4_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + + return (AESCCM_STATUS_ERROR); + } + + object->operationInProgress = true; + + HwiP_restore(interruptKey); + + return (AESCCM_STATUS_SUCCESS); +} + +/* + * ======== AESCCM_waitForResult ======== + */ +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESCCM_STATUS_ERROR; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCCM_STATUS_ERROR; + } + else + { + AESCCM_getResult(handle); + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + if (object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESCCM_cleanup(object); + } + else if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + /* Success is always returned in callback mode */ + result = AESCCM_STATUS_SUCCESS; + } + + return (result); +} + +/* + * ======== AESCCM_waitForDMAInDone ======== + */ +static int_fast16_t AESCCM_waitForDMAInDone(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESCCM_STATUS_ERROR; + + /* + * One-step operations containing both AAD and payload data must poll for + * the completion of the AAD transfer and then process the payload data + */ + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the AAD transfer is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCCM_STATUS_ERROR; + } + else + { + AESCCM_getResult(handle); + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + if (object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESCCM_cleanup(object); + } + else if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + /* Success is always returned in callback mode */ + result = AESCCM_STATUS_SUCCESS; + } + + return (result); +} + +/* + * ======== AESCCM_oneStepEncrypt ======== + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct) +{ + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCCM_oneStepDecrypt ======== + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct) +{ + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCCM_setupSegmentedOperation ======== + */ +static int_fast16_t AESCCM_setupSegmentedOperation(AESCCM_Handle handle, + const CryptoKey *key, + size_t aadLength, + size_t plaintextLength, + size_t macLength) +{ + /* + * Not all of the input values will be asserted here since they will be + * asserted/checked later. Asserts checking the key's validity will occur + * in addAAD/DataInternal for maintainability purposes. The length input + * parameters will be checked in setLengths(). + */ + DebugP_assert(handle); + + AESCCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESCCM_setOperationInProgress(object); + + if (result != AESCCM_STATUS_ERROR) + { + /* + * If the user doesn't provide the total lengths in the setupXXXX() + * calls, they must provide the lengths in setLengths(). + */ + object->expectedAADLength = aadLength; + object->expectedPlaintextLength = plaintextLength; + object->macLength = macLength; + + /* Start processing from a clean slate */ + object->blockCounter = 0; + object->alignmentInfo = 0; + + object->continueAADOperation = false; + object->continueDataOperation = false; + + object->actualAADLength = 0; + object->actualPlaintextLength = 0; + + object->key = *(key); + + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + + /* returnStatus is changed in the case of an error or cancellation */ + object->returnStatus = AESCCM_STATUS_SUCCESS; + } + + return (result); +} + +/* + * ======== AESCCM_setupEncrypt ======== + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + /* Input values will be asserted in setupSegmentedOperation */ + int_fast16_t result = AESCCM_setupSegmentedOperation(handle, key, totalAADLength, totalPlaintextLength, macLength); + + if (result != AESCCM_STATUS_ERROR) + { + AESCCMCC26X4_Object *object = handle->object; + + object->operationType = AESCCM_OPERATION_TYPE_ENCRYPT; + } + + return (result); +} + +/* + * ======== AESCCM_setupDecrypt ======== + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + /* Input values will be asserted in setupSegmentedOperation */ + int_fast16_t result = AESCCM_setupSegmentedOperation(handle, key, totalAADLength, totalPlaintextLength, macLength); + if (result != AESCCM_STATUS_ERROR) + { + AESCCMCC26X4_Object *object = handle->object; + + object->operationType = AESCCM_OPERATION_TYPE_DECRYPT; + } + + return (result); +} + +/* + * ======== AESCCM_setLengths ======== + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength) +{ + DebugP_assert(handle); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + /* This shouldn't be called after addXXX() or finalizeXXX() */ + DebugP_assert(object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + /* The combined length of AAD and payload data must be non-zero */ + if (aadLength == 0 && plaintextLength == 0) + { + return (AESCCM_STATUS_ERROR); + } + + object->expectedAADLength = aadLength; + object->expectedPlaintextLength = plaintextLength; + object->macLength = macLength; + + return (AESCCM_STATUS_SUCCESS); +} + +/* + * ======== AESCCM_setNonce ======== + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength) +{ + /* Public accessible functions should check inputs */ + DebugP_assert(handle); + DebugP_assert(nonce); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + /* This shouldn't be called after addXXX() or finalizeXXX() */ + DebugP_assert(object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + /* The nonce length must be 7 to 13 bytes long */ + if (nonceLength < 7 || nonceLength > 13) + { + return (AESCCM_STATUS_ERROR); + } + + object->nonceLength = nonceLength; + + /* Compute the CCM IV and store in Object's IV buffer */ + uint8_t iv[16] = {0}; + + iv[0] = 15 - nonceLength - 1; + + memcpy(&(iv[1]), nonce, nonceLength); + + memcpy(object->intermediateIV, iv, AES_BLOCK_SIZE); + + return (AESCCM_STATUS_SUCCESS); +} + +/* + * ======== AESCCM_generateNonce ======== + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength) +{ + /* This feature is not currently supported */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_addAAD ======== + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + /* This operation can be called after setup or after addAAD again */ + DebugP_assert(object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT); + + /* + * The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of AAD + */ + if (operation->aadLength == 0 || ((operation->aadLength & AES_NON_BLOCK_MULTIPLE_MASK) && + object->actualAADLength + operation->aadLength != object->expectedAADLength)) + { + return (AESCCM_STATUS_ERROR); + } + + /* + * The total AAD input length must not exceed the total length specified + * in AESCCM_setLengths() or the setupXXXX() call. + */ + if (object->actualAADLength + operation->aadLength > object->expectedAADLength) + { + return (AESCCM_STATUS_ERROR); + } + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + AESCCM_OperationType operationType = AESCCM_OP_TYPE_AAD_ENCRYPT; + + if (object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) + { + direction = AESCCM_MODE_DECRYPT; + operationType = AESCCM_OP_TYPE_AAD_DECRYPT; + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return (AESCCM_STATUS_RESOURCE_UNAVAILABLE); + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESCCM_OperationUnion *)operation; + + int_fast16_t result = AESCCM_addAADInternal(handle, operation->aad, operation->aadLength, direction); + + if ((result != AESCCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + + return (result); +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== AESCCM_getKeyStoreKeyUsage ======== + */ +static KeyStore_PSA_KeyUsage AESCCM_getKeyStoreKeyUsage(AESCCM_Mode direction) +{ + switch (direction) + { + case AESCCM_MODE_ENCRYPT: + return KEYSTORE_PSA_KEY_USAGE_ENCRYPT; + + case AESCCM_MODE_DECRYPT: + return KEYSTORE_PSA_KEY_USAGE_DECRYPT; + + default: + return 0; + } +} +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +/* + * ======== AESCCM_addAADInternal ======== + */ +static int_fast16_t AESCCM_addAADInternal(AESCCM_Handle handle, uint8_t *aad, size_t aadLength, AESCCM_Mode direction) +{ + DebugP_assert(handle); + DebugP_assert(aad && aadLength); + + AESCCMCC26X4_Object *object = handle->object; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* + * The key is provided as an input in setupEncrypt/Decrypt() + * and within the input operation struct for oneStepEncrypt/Decrypt(), + * and users should check those inputs. + * Only plaintext and KeyStore CryptoKeys are supported for now + */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESCCM_getKeyStoreKeyUsage(direction); + + if (!keyUsage) + { + return AESCCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_CCM, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return (AESCCM_STATUS_KEYSTORE_INVALID_ID); + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return (AESCCM_STATUS_KEYSTORE_GENERIC_ERROR); + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); + } + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + AESCCMCC26X4_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at a hardcoded and + * reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + return (AESCCM_STATUS_ERROR); + } + + /* + * We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * Only AES_DMA_IN_DONE is asserted when processing intermediate chunks + * of AAD. In that case, the interrupt source is expected to be + * AES_DMA_IN_DONE instead of AES_RESULT_RDY, which is asserted when + * the crypto result is ready after processing payload data or the very + * last chunk of data (which could be AAD). + */ + if ((object->actualAADLength + aadLength == object->expectedAADLength) && object->expectedPlaintextLength == 0) + { + /* + * Disable this interrupt source if this AAD chunk is the very last + * chunk of data to be processed + */ + AESIntDisable(AES_DMA_IN_DONE); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks of + * the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + AESSelectAlgorithm(0); + + return (AESCCM_STATUS_ERROR); + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Write zeroes or the intermediate tag to the Key3 registers */ + AESCCMSetTag(object->intermediateTag); + + /* Write the initial or intermediate IV */ + AESSetInitializationVector(object->intermediateIV); + + uint32_t ctrlVal = AESGetDefaultCCMCtrlValue(object->nonceLength, + object->macLength, + direction == AESCCM_MODE_ENCRYPT); + if (object->continueAADOperation) + { + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GCM_CCM_CONTINUE_AAD); + } + else + { + AESSetCtrl(ctrlVal); + } + + AESSetDataLength(object->expectedPlaintextLength); + + if (object->continueAADOperation) + { + AESSetBlockCounter(object->blockCounter); + AESSetCCMAlignWord(object->alignmentInfo); + } + + AESSetAuthLength(object->expectedAADLength); + + object->hwBusy = true; + object->actualAADLength += aadLength; + object->continueAADOperation = true; + + AESStartDMAOperation(aad, aadLength, NULL, 0); + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + /* Process payload data, if any, for one-shot operations */ + if ((object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) && + object->expectedPlaintextLength > 0) + { + /* Wait until the AAD transfer is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + result = AESCCM_STATUS_ERROR; + object->hwBusy = false; + + /* Reset the AESCTL register */ + AESSetCtrl(0); + + /* + * Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore. + * + * The semaphore must be posted after the callback is executed + * to prevent another thread which shares the same driver instance + * from starting a new operation and overwriting the object's + * operation and operationType provided to the callback. + */ + AESCCM_cleanup(object); + } + + /* Disable pending interrupt from DMA_IN_DONE */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + if (result != AESCCM_STATUS_ERROR) + { + object->actualPlaintextLength += object->operation->oneStepOperation.inputLength; + object->continueDataOperation = true; + + AESStartDMAOperation(object->operation->oneStepOperation.input, + object->operation->oneStepOperation.inputLength, + object->operation->oneStepOperation.output, + object->operation->oneStepOperation.inputLength); + } + } + + if (result != AESCCM_STATUS_ERROR) + { + /* + * If we are in AESCCM_RETURN_BEHAVIOR_POLLING, + * we do not want an interrupt to trigger. + */ + if (object->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + if ((object->actualAADLength == object->expectedAADLength) && + (object->expectedPlaintextLength == object->actualPlaintextLength)) + { + result = AESCCM_waitForResult(handle); + } + else + { + result = AESCCM_waitForDMAInDone(handle); + } + } + + return (result); +} + +/* + * ======== AESCCM_addData ======== + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + /* This operation can be called after setupXXXX, addAAD, or addData. */ + DebugP_assert(object->operationType != AESCCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType != AESCCM_OP_TYPE_FINALIZE_ENCRYPT); + + /* + * The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of payload data + */ + if (operation->inputLength == 0 || + ((operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK) && + object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength)) + { + return (AESCCM_STATUS_ERROR); + } + + /* + * The AAD input length specified so far must match the total length + * specified in the setLengths() or setupXXXX() calls. + * All AAD input must be processed at this point. + */ + if (object->actualAADLength != object->expectedAADLength) + { + return (AESCCM_STATUS_ERROR); + } + + /* + * The total input length must not exceed the lengths specified in + * AESCCM_setLengths() or setupXXXX(). + */ + if (object->actualPlaintextLength + operation->inputLength > object->expectedPlaintextLength) + { + return (AESCCM_STATUS_ERROR); + } + + AESCCM_Mode direction = AESCCM_MODE_ENCRYPT; + AESCCM_OperationType operationType = AESCCM_OP_TYPE_DATA_ENCRYPT; + + if (object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT) + { + direction = AESCCM_MODE_DECRYPT; + operationType = AESCCM_OP_TYPE_DATA_DECRYPT; + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return (AESCCM_STATUS_RESOURCE_UNAVAILABLE); + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESCCM_OperationUnion *)operation; + + int_fast16_t result = AESCCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + direction); + + if ((result != AESCCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + + return (result); +} + +/* + * ======== AESCCM_addDataInternal ======== + */ +static int_fast16_t AESCCM_addDataInternal(AESCCM_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESCCM_Mode direction) +{ + DebugP_assert(handle); + DebugP_assert(input && output && inputLength); + + AESCCMCC26X4_Object *object = handle->object; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* + * The key is provided as an input in setupEncrypt/Decrypt() + * and within the input operation struct for oneStepEncrypt/Decrypt(), + * and users should check those inputs. + * Only plaintext and KeyStore CryptoKeys are supported for now + */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESCCM_getKeyStoreKeyUsage(direction); + + if (!keyUsage) + { + return AESCCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_CCM, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return (AESCCM_STATUS_KEYSTORE_INVALID_ID); + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return (AESCCM_STATUS_KEYSTORE_GENERIC_ERROR); + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); + } + + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + AESCCMCC26X4_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI + * callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at a hardcoded + * and reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + return (AESCCM_STATUS_ERROR); + } + + /* + * We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * Disable AES_DMA_IN_DONE to prevent triggering an interrupt + * before the crypto result is ready. + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks + * of the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in + * the keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + AESSelectAlgorithm(0); + + return (AESCCM_STATUS_ERROR); + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESCCMSetTag(object->intermediateTag); + AESSetInitializationVector(object->intermediateIV); + + uint32_t ctrlVal = AESGetDefaultCCMCtrlValue(object->nonceLength, + object->macLength, + direction == AESCCM_MODE_ENCRYPT); + + /* You are continuing off an operation if AAD has been processed */ + if (object->continueDataOperation || object->actualAADLength != 0) + { + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GCM_CCM_CONTINUE); + } + else + { + AESSetCtrl(ctrlVal); + } + + AESSetDataLength(object->expectedPlaintextLength); + + if (object->continueDataOperation || object->actualAADLength != 0) + { + AESSetBlockCounter(object->blockCounter); + } + + AESSetAuthLength(object->expectedAADLength); + + object->hwBusy = true; + object->actualPlaintextLength += inputLength; + object->continueDataOperation = true; + + AESStartDMAOperation(input, inputLength, output, inputLength); + + if (object->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + return (AESCCM_waitForResult(handle)); +} + +/* + * ======== AESCCM_finalizeEncrypt ======== + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + DebugP_assert(object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT); + + /* All AAD should be processed at this point in time */ + if (object->actualAADLength != object->expectedAADLength) + { + return (AESCCM_STATUS_ERROR); + } + + /* Additional payload data can be passed in finalize */ + if (object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength) + { + return (AESCCM_STATUS_ERROR); + } + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + if (operation->inputLength > 0) + { + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return (AESCCM_STATUS_RESOURCE_UNAVAILABLE); + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = AESCCM_OP_TYPE_FINALIZE_ENCRYPT; + object->operation = (AESCCM_OperationUnion *)operation; + + result = AESCCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + AESCCM_MODE_ENCRYPT); + + if ((result != AESCCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + } + else + { + /* + * If not passing any new data in finalize, no HW operation is done. + * The previous call will have processed all remaining data and have + * stored the output tag in Object in cleanup(). + */ + memcpy(operation->mac, object->intermediateTag, operation->macLength); + + /* Clear intermediate buffers to prevent data leakage */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new segmented operation after operationInProgress is + * cleared + */ + result = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK) + { + /* Invoke the application callback function */ + object->callbackFxn(handle, result, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_ENCRYPT); + + /* Always return success in callback mode */ + result = AESCCM_STATUS_SUCCESS; + } + } + + return (result); +} + +/* + * ======== AESCCM_finalizeDecrypt ======== + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESCCM_STATUS_SUCCESS) + { + return (object->returnStatus); + } + + DebugP_assert(object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT); + + /* All AAD should be processed at this point in time */ + if (object->actualAADLength != object->expectedAADLength) + { + return (AESCCM_STATUS_ERROR); + } + + /* Additional payload data can be passed in finalize */ + if (object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength) + { + return (AESCCM_STATUS_ERROR); + } + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + if (operation->inputLength > 0) + { + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return (AESCCM_STATUS_RESOURCE_UNAVAILABLE); + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = AESCCM_OP_TYPE_FINALIZE_DECRYPT; + object->operation = (AESCCM_OperationUnion *)operation; + + result = AESCCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + AESCCM_MODE_DECRYPT); + + if ((result != AESCCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + } + else + { + /* + * If not passing any new data in finalize, no HW operation is done. + * The previous call will have processed all remaining data and have + * stored the output tag in Object in cleanup(). + */ + bool macValid = CryptoUtils_buffersMatch(object->intermediateTag, operation->mac, operation->macLength); + + if (!macValid) + { + object->returnStatus = AESCCM_STATUS_MAC_INVALID; + } + + /* Clear intermediate buffers to prevent data leakage */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new segmented operation after operationInProgress is + * cleared + */ + result = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK) + { + /* Invoke the application callback function */ + object->callbackFxn(handle, result, (AESCCM_OperationUnion *)operation, AESCCM_OP_TYPE_FINALIZE_DECRYPT); + + /* Always return success in callback mode */ + result = AESCCM_STATUS_SUCCESS; + } + } + + return (result); +} + +/* + * ======== AESCCM_cancelOperation ======== + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) +{ + AESCCMCC26X4_Object *object = handle->object; + + uint32_t key; + + key = HwiP_disable(); + + /* Cancel is only supported for callback mode */ + if (object->returnBehavior != AESCCM_RETURN_BEHAVIOR_CALLBACK) + { + HwiP_restore(key); + + return (AESCCM_STATUS_ERROR); + } + + if (!object->hwBusy) + { + object->returnStatus = AESCCM_STATUS_CANCELED; + object->operationInProgress = false; + HwiP_restore(key); + + /* Canceling returns success if no HW operations are in progress */ + return (AESCCM_STATUS_SUCCESS); + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(key); + + /* + * When canceling an operation, data associated with + * the operation should be wiped for security purposes. + */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, sizeof(object->intermediateTag), 0, sizeof(object->intermediateTag)); + + uint8_t *outputBuffer = NULL; + size_t outputLength = 0; + uint8_t *mac = NULL; + uint8_t macLength = 0; + + /* + * Clear the output buffer. In-progress one-step + * and finalize operations should also clear the MAC + */ + if (object->operationType == AESCCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + { + outputBuffer = object->operation->oneStepOperation.output; + outputLength = object->operation->oneStepOperation.inputLength; + mac = object->operation->oneStepOperation.mac; + macLength = object->operation->oneStepOperation.macLength; + } + else if (object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT) + { + /* + * The output is not guaranteed to be contiguous. Therefore, only + * the passed in output buffer is cleared + */ + outputBuffer = object->operation->segmentedDataOperation.output; + outputLength = object->operation->segmentedDataOperation.inputLength; + } + else if (object->operationType == AESCCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESCCM_OP_TYPE_FINALIZE_ENCRYPT) + { + outputBuffer = object->operation->segmentedFinalizeOperation.output; + outputLength = object->operation->segmentedFinalizeOperation.inputLength; + mac = object->operation->segmentedFinalizeOperation.mac; + macLength = object->operation->segmentedFinalizeOperation.macLength; + } + + bool clearedBuffer = true; + + int_fast16_t result = AESCCM_STATUS_SUCCESS; + + if (outputBuffer && outputLength) + { + if (object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT || object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) + { + /* + * Attempting to clear the output during an AAD operation + * results in a failure + */ + result = AESCCM_STATUS_ERROR; + } + + CryptoUtils_memset(outputBuffer, outputLength, 0, outputLength); + clearedBuffer = CryptoUtils_isBufferAllZeros(outputBuffer, outputLength); + + if (!clearedBuffer) + { + result = AESCCM_STATUS_ERROR; + } + } + + if (mac && macLength) + { + if (object->operationType == AESCCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESCCM_OP_TYPE_DATA_DECRYPT || + object->operationType == AESCCM_OP_TYPE_AAD_ENCRYPT || object->operationType == AESCCM_OP_TYPE_AAD_DECRYPT) + { + /* + * Attempting to clear the MAC during a non one-shot or finalize + * operation results in a failure + */ + result = AESCCM_STATUS_ERROR; + } + + CryptoUtils_memset(mac, macLength, 0, macLength); + clearedBuffer = CryptoUtils_isBufferAllZeros(mac, macLength); + + if (!clearedBuffer) + { + result = AESCCM_STATUS_ERROR; + } + } + + AESDMAReset(); + + AESReset(); + + /* + * Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * The operation in progress state must be cleared so a user can + * start another operation after canceling. + */ + object->operationInProgress = false; + object->hwBusy = false; + object->returnStatus = AESCCM_STATUS_CANCELED; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, AESCCM_STATUS_CANCELED, object->operation, object->operationType); + } + + /* + * Power down and reset the crypto module, release the power constraint, + * and post the access semaphore + */ + AESCCM_cleanup(object); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.h b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.h new file mode 100644 index 00000000..9ee3bc67 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCCMCC26X4.h + * + * @brief AESCCM driver implementation for the CC26X4 family + * + * This file should only be included in the board file to fill the AESCCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26X4 family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CCM. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure that + * sensible access timeouts are set. + * + * # Key Store # + * The CC26X4 crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesccm_AESCCMCC26X4__include +#define ti_drivers_aesccm_AESCCMCC26X4__include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESCCMCC26X4 Hardware Attributes + * + * AESCCM26X4 hardware attributes should be included in the board file + * and pointed to by the AESCCM_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC27xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESCCMCC26X4_HWAttrs; + +/*! + * @brief AESCCMCC26X4 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t intermediateIV[AES_IV_LENGTH_BYTES / 4]; + uint32_t intermediateTag[AES_TAG_LENGTH_BYTES / 4]; + uint32_t blockCounter; + uint32_t alignmentInfo; + uint32_t semaphoreTimeout; + AESCCM_CallbackFxn callbackFxn; + AESCCM_OperationUnion *operation; + size_t expectedAADLength; + size_t expectedPlaintextLength; + size_t actualAADLength; + size_t actualPlaintextLength; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESCCM_ReturnBehavior returnBehavior; + AESCCM_OperationType operationType; + /* MAC and nonceLength are stored for configuring the AESCTL register */ + uint8_t macLength; + uint8_t nonceLength; + /* Track when to set gcm_ccm_continue or continue_aad bit */ + bool continueAADOperation; + bool continueDataOperation; + bool isOpen; + volatile bool operationInProgress; + volatile bool hwBusy; + volatile bool cryptoResourceLocked; +} AESCCMCC26X4_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMCC26X4__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.c new file mode 100644 index 00000000..a1e64e00 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.c @@ -0,0 +1,806 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESCCM_s_SecureCallback aesccmSecureCB_ns[]; +extern AESCCMCC26X4_ns_Object aesccmObject_ns[]; + +/* + * ======== AESCCM_ns_callbackFxn ======== + */ +void AESCCM_ns_callbackFxn(uintptr_t arg) +{ + AESCCM_s_SecureCallback *secureCallbackObject = (AESCCM_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + aesccmObject_ns[index].callbackFxn(aesccmSecureCB_ns[index].handle, + aesccmSecureCB_ns[index].returnValue, + aesccmSecureCB_ns[index].operation, + aesccmSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESCCM_ns_registerCallback ======== + */ +static psa_status_t AESCCM_ns_registerCallback(AESCCM_Handle handle, const AESCCM_Params *params) +{ + AESCCM_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCallback object */ + SecureCallback_construct(&aesccmSecureCB_ns[index].object, + AESCCM_ns_callbackFxn, + (uintptr_t)&aesccmSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aesccmSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESCCM_init ======== + */ +void AESCCM_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCallback driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESCCM_open ======== + */ +AESCCM_Handle AESCCM_open(uint_least8_t index, const AESCCM_Params *params) +{ + AESCCM_Handle handle = NULL; + AESCCM_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCCM_Params *)&AESCCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING)) + { + if (AESCCM_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesccmObject_ns[index].returnBehavior = params->returnBehavior; + aesccmObject_ns[index].callbackFxn = params->callbackFxn; + aesccmObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCCM_construct ======== + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params) +{ + AESCCM_Handle handle = NULL; + AESCCM_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCCM_Params *)&AESCCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING)) + { + if (AESCCM_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesccmObject_ns[index].returnBehavior = params->returnBehavior; + aesccmObject_ns[index].callbackFxn = params->callbackFxn; + aesccmObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCCM_close ======== + */ +void AESCCM_close(AESCCM_Handle handle) +{ + AESCCM_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aesccmSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCCM_oneStepOperation ======== + */ +static int_fast16_t AESCCM_oneStepOperation(AESCCM_Handle handle, + AESCCM_OneStepOperation *operationStruct, + int32_t type) +{ + AESCCM_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + uintptr_t key; + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesccmObject_ns[index].semaphoreTimeout) == false) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if ((aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) && + (operationStruct->inputLength <= 256)) + { + /* Call fast veneer */ + key = HwiP_disable(); + + if (type == AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + result = AESCCM_s_oneStepEncryptFast(handle, operationStruct); + } + else + { + result = AESCCM_s_oneStepDecryptFast(handle, operationStruct); + } + + HwiP_restore(key); + CryptoPSACC26X4_releaseLock(); + } + else + { + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operationStruct; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + if (aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) && + (result != AESCCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesccmSecureCB_ns[index].returnValue; + } + } + + return (result); +} + +/* + * ======== AESCCM_oneStepEncrypt ======== + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct) +{ + return AESCCM_oneStepOperation(handle, operationStruct, AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESCCM_oneStepDecrypt ======== + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_OneStepOperation *operationStruct) +{ + return AESCCM_oneStepOperation(handle, operationStruct, AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT); +} + +/* + * ======== AESCCM_setupOperation ======== + */ +static int_fast16_t AESCCM_setupOperation(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength, + int32_t type) +{ + AESCCM_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + setupMsg.aadLength = totalAADLength; + setupMsg.plaintextLength = totalPlaintextLength; + setupMsg.macLength = macLength; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCCM_setupEncrypt ======== + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + return AESCCM_setupOperation(handle, + key, + totalAADLength, + totalPlaintextLength, + macLength, + AESCCM_S_MSG_TYPE_SETUP_ENCRYPT); +} + +/* + * ======== AESCCM_setupDecrypt ======== + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + return AESCCM_setupOperation(handle, + key, + totalAADLength, + totalPlaintextLength, + macLength, + AESCCM_S_MSG_TYPE_SETUP_DECRYPT); +} + +/* + * ======== AESCCM_addAAD ======== + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation) +{ + AESCCM_s_AddAADMsg addADDMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addADDMsg.handle = handle; + addADDMsg.operation = operation; + invecs[0].base = &addADDMsg; + invecs[0].len = sizeof(addADDMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesccmObject_ns[index].semaphoreTimeout) == false) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_ADD_AAD, invecs, outvecs); + + if ((aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) && (result != AESCCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesccmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCCM_addData ======== + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation) +{ + AESCCM_s_AddDataMsg addDataMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesccmObject_ns[index].semaphoreTimeout) == false) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) && (result != AESCCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesccmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCCM_finalizeEncrypt ======== + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + AESCCM_s_FinalizeOperationMsg finalizeMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesccmObject_ns[index].semaphoreTimeout) == false) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_FINALIZE_ENCRYPT, invecs, outvecs); + + if ((aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) && (result != AESCCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesccmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCCM_finalizeDecrypt ======== + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + AESCCM_s_FinalizeOperationMsg finalizeMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesccmObject_ns[index].semaphoreTimeout) == false) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_FINALIZE_DECRYPT, invecs, outvecs); + + if ((aesccmObject_ns[index].returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) && (result != AESCCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesccmObject_ns[index].returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + (void)SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesccmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCCM_cancelOperation ======== + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) +{ + AESCCM_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCCM_setLengths ======== + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength) +{ + AESCCM_s_SetLengthsMsg setLengthMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setLengthMsg.handle = handle; + setLengthMsg.aadLength = aadLength; + setLengthMsg.plaintextLength = plaintextLength; + setLengthMsg.macLength = macLength; + invecs[0].base = &setLengthMsg; + invecs[0].len = sizeof(setLengthMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_SET_LENGTHS, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCCM_setNonce ======== + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength) +{ + AESCCM_s_SetNonceMsg setNonceMsg; + int_fast16_t result = AESCCM_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setNonceMsg.handle = handle; + setNonceMsg.nonce = nonce; + setNonceMsg.nonceLength = nonceLength; + invecs[0].base = &setNonceMsg; + invecs[0].len = sizeof(setNonceMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCCM_S_MSG_TYPE_SET_NONCE, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCCM_generateNonce ======== + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength) +{ + /* This feature is not currently supported */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.h new file mode 100644 index 00000000..b4fa08dc --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCCMCC26X4_ns.h + * + * @brief AESCCM Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_aesccm_AESCCMCC26X4_ns__include +#define ti_drivers_aesccm_AESCCMCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESCCMCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESCCM_CallbackFxn callbackFxn; + AESCCM_ReturnBehavior returnBehavior; +} AESCCMCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.c new file mode 100644 index 00000000..91392e33 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.c @@ -0,0 +1,1285 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESCCMCC26X4_s.h" + +#include +#include +#include + +#include + +#include /* __tz_c_veneer */ + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESCCM_OperationUnion *operation_ns; /* Pointer to non-secure operation */ + AESCCM_OperationUnion operation_s; /* Secure copy of operation */ +} AESCCM_s_Operation; + +static AESCCM_s_Operation AESCCM_s_operation; + +/* + * AES CCM Secure Dynamic Instance struct. + */ +typedef struct +{ + AESCCM_Config config; + AESCCMCC26X4_Object object; + AESCCMCC26X4_HWAttrs hwAttrs; +} AESCCM_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESCCM_construct. + */ +static AESCCM_s_DynamicInstance AESCCM_s_dynInstance[CONFIG_AESCCM_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESCCM_s_SecureCallbacks for each driver instance opened or constructed */ +static AESCCM_s_SecureCallback *AESCCM_s_secureCB[AESCCM_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESCCM_Config AESCCM_config[]; + +/* + * ======== AESCCM_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t AESCCM_s_getCallbackIndex(AESCCM_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESCCM_COUNT; index++) + { + if (handle_s == (AESCCM_Handle)&AESCCM_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESCCM_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESCCM_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESCCM_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESCCM_s_hwiCallback ======== + */ +static void AESCCM_s_hwiCallback(AESCCM_Handle handle_s, + int_fast16_t returnValue, + AESCCM_OperationUnion *operation, + AESCCM_OperationType operationType) +{ + int8_t index; + AESCCM_s_SecureCallback *aesccmSecureCB_ns; + + index = AESCCM_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESCCM_SECURE_CALLBACK_COUNT)) + { + aesccmSecureCB_ns = AESCCM_s_secureCB[index]; + + if (aesccmSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aesccmSecureCB_ns->handle = (AESCCM_Handle)(CRYPTO_S_HANDLE_ID_AESCCM | index); + aesccmSecureCB_ns->returnValue = returnValue; + aesccmSecureCB_ns->operation = AESCCM_s_operation.operation_ns; + aesccmSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aesccmSecureCB_ns->object); + } + } +} + +/* + * ======== AESCCM_s_copyConfig ======== + */ +static inline psa_status_t AESCCM_s_copyConfig(AESCCM_Config **secureConfig, + const AESCCM_Config *config, + AESCCM_Handle *retHandle) +{ + AESCCM_Config *config_s; + AESCCM_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESCCM_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESCCM_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCCM_s_secureCB[i + CONFIG_TI_DRIVERS_AESCCM_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESCCM OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESCCM_Handle)(CRYPTO_S_HANDLE_ID_AESCCM | (i + CONFIG_TI_DRIVERS_AESCCM_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESCCM_s_releaseConfig ======== + */ +static inline void AESCCM_s_releaseConfig(AESCCM_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCCM) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESCCM_COUNT) && (i < AESCCM_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESCCM_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCCM_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESCCM_s_copyOneStepOperation ======== + */ +static psa_status_t AESCCM_s_copyOneStepOperation(AESCCM_OneStepOperation *secureOperation, + CryptoKey *secureKey, + const AESCCM_OneStepOperation *operation, + int32_t msgType) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCCM_OneStepOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCCM_OneStepOperation)); + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the key struct and update the operation + * struct to point to the secure key copy. + */ + (void)spm_memcpy(secureKey, secureOperation->key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(secureKey) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + secureOperation->key = secureKey; + + /* Verify nonce address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->nonce, secureOperation->nonceLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * The combined length of AAD and input data must be non-zero. This validation + * check will occur within the AES CCM driver. + */ + + /* Verify AAD address range if AAD provided */ + if ((secureOperation->aadLength > 0) && + (cmse_has_unpriv_nonsecure_read_access(secureOperation->aad, secureOperation->aadLength) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify input and output address range if input data provided */ + if (secureOperation->inputLength > 0) + { + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* + * Verify MAC address range - MAC is an output for encrypt operation and an + * input for decrypt operation. + */ + if (msgType == AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else + { + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_copyAddAADOperation ======== + */ +static inline psa_status_t AESCCM_s_copyAddAADOperation(AESCCM_SegmentedAADOperation *secureOperation, + const AESCCM_SegmentedAADOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCCM_SegmentedAADOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCCM_SegmentedAADOperation)); + + /* Verify AAD address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->aad, secureOperation->aadLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_copyAddDataOperation ======== + */ +static inline psa_status_t AESCCM_s_copyAddDataOperation(AESCCM_SegmentedDataOperation *secureOperation, + const AESCCM_SegmentedDataOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCCM_SegmentedDataOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCCM_SegmentedDataOperation)); + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_copyFinalizeOperation ======== + */ +static inline psa_status_t AESCCM_s_copyFinalizeOperation(AESCCM_SegmentedFinalizeOperation *secureOperation, + const AESCCM_SegmentedFinalizeOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCCM_SegmentedFinalizeOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCCM_SegmentedFinalizeOperation)); + + /* Operations can be finalized with or without additional data */ + if (secureOperation->inputLength > 0) + { + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* + * Verify MAC address range - MAC is an output for encrypt operation, and an + * input for decrypt operation. For simplicity, check for non-secure read + * access only. If a non-secure read-only address is provided for a encrypt + * operation, the MAC output will not be written. There is no security + * vulnerability. + */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_copyParams ======== + */ +static psa_status_t AESCCM_s_copyParams(AESCCM_Params *secureParams, const AESCCM_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESCCM_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESCCM_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESCCM_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESCCM_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESCCM_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESCCM_Handle AESCCM_s_getHandle(AESCCM_Handle nsHandle) +{ + AESCCM_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCCM) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESCCM_COUNT) + { + secureHandle = (AESCCM_Handle)&AESCCM_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESCCM_COUNT) && (i < AESCCM_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESCCM_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCCM_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESCCM_s_registerCallback ======== + */ +static inline psa_status_t AESCCM_s_registerCallback(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESCCM_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESCCM_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESCCM_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESCCM_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESCCM_s_SecureCallback located in + * non-secure memory. + */ + AESCCM_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCCM_s_construct ======== + */ +static inline psa_status_t AESCCM_s_construct(psa_msg_t *msg) +{ + AESCCM_s_ConstructMsg constructMsg; + AESCCM_Handle handle; + AESCCM_Params params_s; + const AESCCM_Params *paramsPtr_s = NULL; + AESCCM_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESCCM_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESCCM_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESCCM_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESCCM_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_open ======== + */ +static inline psa_status_t AESCCM_s_open(psa_msg_t *msg) +{ + AESCCM_s_OpenMsg openMsg; + AESCCM_Handle handle; + AESCCM_Params params_s; + AESCCM_Params *paramsPtr_s = NULL; + AESCCM_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESCCM_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESCCM_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCCM_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESCCM OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESCCM_Handle)(CRYPTO_S_HANDLE_ID_AESCCM | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_close ======== + */ +static inline psa_status_t AESCCM_s_close(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESCCM_close(handle_s); + + /* Release the secure config if it is a dynamic */ + AESCCM_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESCCM_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_oneStepOperation ======== + */ +static inline psa_status_t AESCCM_s_oneStepOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCCM_s_OneStepOperationMsg oneStepMsg; + AESCCM_Handle handle_s; + AESCCM_OneStepOperation *operation_s; + CryptoKey key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(oneStepMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &oneStepMsg, sizeof(oneStepMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(oneStepMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCCM_s_operation.operation_s.oneStepOperation; + + /* Save pointer to non-secure operation struct */ + AESCCM_s_operation.operation_ns = (AESCCM_OperationUnion *)oneStepMsg.operation; + + /* Validate and copy operation and key structs */ + status = AESCCM_s_copyOneStepOperation(operation_s, &key_s, oneStepMsg.operation, msgType); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = oneStepMsg.handle; + operation_s = oneStepMsg.operation; + } + + if (msgType == AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + ret = AESCCM_oneStepEncrypt(handle_s, operation_s); + } + else + { + ret = AESCCM_oneStepDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCCM_s_setupOperation ======== + */ +static inline psa_status_t AESCCM_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCCM_s_SetupOperationMsg setupMsg; + AESCCM_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESCCM_S_MSG_TYPE_SETUP_ENCRYPT) + { + ret = AESCCM_setupEncrypt(handle_s, keyPtr_s, setupMsg.aadLength, setupMsg.plaintextLength, setupMsg.macLength); + } + else + { + ret = AESCCM_setupDecrypt(handle_s, keyPtr_s, setupMsg.aadLength, setupMsg.plaintextLength, setupMsg.macLength); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_setLengths ======== + */ +static inline psa_status_t AESCCM_s_setLengths(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_s_SetLengthsMsg setLengthsMsg; + int_fast16_t ret; + + if (msg->in_size[0] != sizeof(setLengthsMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setLengthsMsg, sizeof(setLengthsMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(setLengthsMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = setLengthsMsg.handle; + } + + ret = AESCCM_setLengths(handle_s, setLengthsMsg.aadLength, setLengthsMsg.plaintextLength, setLengthsMsg.macLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_setNonce ======== + */ +static inline psa_status_t AESCCM_s_setNonce(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_s_SetNonceMsg setNonceMsg; + int_fast16_t ret; + + if (msg->in_size[0] != sizeof(setNonceMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setNonceMsg, sizeof(setNonceMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(setNonceMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate nonce address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setNonceMsg.nonce, setNonceMsg.nonceLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = setNonceMsg.handle; + } + + ret = AESCCM_setNonce(handle_s, setNonceMsg.nonce, setNonceMsg.nonceLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_addAAD ======== + */ +static inline psa_status_t AESCCM_s_addAAD(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_SegmentedAADOperation *operation_s; + AESCCM_s_AddAADMsg addAADMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addAADMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addAADMsg, sizeof(addAADMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(addAADMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCCM_s_operation.operation_s.segmentedAADOperation; + + /* Save pointer to non-secure operation struct */ + AESCCM_s_operation.operation_ns = (AESCCM_OperationUnion *)addAADMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCCM_s_copyAddAADOperation(operation_s, addAADMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCCM_addAAD(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCCM_addAAD(addAADMsg.handle, addAADMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCCM_s_addData ======== + */ +static inline psa_status_t AESCCM_s_addData(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_SegmentedDataOperation *operation_s; + AESCCM_s_AddDataMsg addDataMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCCM_s_operation.operation_s.segmentedDataOperation; + + /* Save pointer to non-secure operation struct */ + AESCCM_s_operation.operation_ns = (AESCCM_OperationUnion *)addDataMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCCM_s_copyAddDataOperation(operation_s, addDataMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCCM_addData(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCCM_addData(addDataMsg.handle, addDataMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCCM_s_finalizeOperation ======== + */ +static inline psa_status_t AESCCM_s_finalizeOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCCM_s_FinalizeOperationMsg finalizeMsg; + AESCCM_SegmentedFinalizeOperation *operation_s; + AESCCM_Handle handle_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCCM_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCCM_s_operation.operation_s.segmentedFinalizeOperation; + + /* Save pointer to non-secure operation struct */ + AESCCM_s_operation.operation_ns = (AESCCM_OperationUnion *)finalizeMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCCM_s_copyFinalizeOperation(operation_s, finalizeMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = finalizeMsg.handle; + operation_s = finalizeMsg.operation; + } + + if (msgType == AESCCM_S_MSG_TYPE_FINALIZE_ENCRYPT) + { + ret = AESCCM_finalizeEncrypt(handle_s, operation_s); + } + else + { + ret = AESCCM_finalizeDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCCM_s_cancelOperation ======== + */ +static inline psa_status_t AESCCM_s_cancelOperation(psa_msg_t *msg) +{ + AESCCM_Handle handle_s; + AESCCM_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESCCM_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESCCM_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCCM_s_handlePsaMsg ======== + */ +psa_status_t AESCCM_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESCCM_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESCCM_S_MSG_TYPE_CONSTRUCT: + status = AESCCM_s_construct(msg); + break; + + case AESCCM_S_MSG_TYPE_OPEN: + status = AESCCM_s_open(msg); + break; + + /* + * AESCCM_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESCCM_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESCCM_s_registerCallback(msg); + break; + + case AESCCM_S_MSG_TYPE_CLOSE: + status = AESCCM_s_close(msg); + break; + + /* + * For optimal performance, non-secure clients should use the + * AESCCM_s_oneStepDecryptFast and AESCCM_s_oneStepDecryptFast veneers + * instead of PSA calls with AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT or + * AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT. + */ + case AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT: /* Fall through */ + case AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT: + status = AESCCM_s_oneStepOperation(msg, msg->type); + break; + + case AESCCM_S_MSG_TYPE_SETUP_ENCRYPT: /* Fall through */ + case AESCCM_S_MSG_TYPE_SETUP_DECRYPT: + status = AESCCM_s_setupOperation(msg, msg->type); + break; + + case AESCCM_S_MSG_TYPE_SET_LENGTHS: + status = AESCCM_s_setLengths(msg); + break; + + case AESCCM_S_MSG_TYPE_SET_NONCE: + status = AESCCM_s_setNonce(msg); + break; + + case AESCCM_S_MSG_TYPE_ADD_AAD: + status = AESCCM_s_addAAD(msg); + break; + + case AESCCM_S_MSG_TYPE_ADD_DATA: + status = AESCCM_s_addData(msg); + break; + + case AESCCM_S_MSG_TYPE_FINALIZE_ENCRYPT: /* Fall through */ + case AESCCM_S_MSG_TYPE_FINALIZE_DECRYPT: + status = AESCCM_s_finalizeOperation(msg, msg->type); + break; + + /* + * AESCCM_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESCCM_S_MSG_TYPE_CANCEL_OPERATION: + status = AESCCM_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESCCM_s_init ======== + */ +void AESCCM_s_init(void) +{ + AESCCM_init(); +} + +/* + * ======== AESCCM_s_oneStepOperationFast ======== + */ +static int_fast16_t AESCCM_s_oneStepOperationFast(AESCCM_Handle handle, + AESCCM_OneStepOperation *operation, + int32_t msgType) +{ + AESCCM_Handle handle_s; + AESCCM_OneStepOperation *operation_s; + CryptoKey key_s; + int_fast16_t status; + psa_status_t psaStatus = PSA_ERROR_PROGRAMMER_ERROR; + + handle_s = AESCCM_s_getHandle(handle); + + if (handle_s != NULL) + { + operation_s = &AESCCM_s_operation.operation_s.oneStepOperation; + + /* Validate and copy operation and key structs */ + psaStatus = AESCCM_s_copyOneStepOperation(operation_s, &key_s, operation, msgType); + } + + if (psaStatus == PSA_SUCCESS) + { + if (msgType == AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + status = AESCCM_oneStepEncrypt(handle_s, operation_s); + } + else + { + status = AESCCM_oneStepDecrypt(handle_s, operation_s); + } + } + else + { + /* + * PSA error codes can be returned because their values do not overlap + * with existing crypto driver return codes. + */ + status = ((int_fast16_t)psaStatus); + } + + return status; +} + +/* + * ======== AESCCM_s_oneStepEncryptFast ======== + */ +__tz_c_veneer int_fast16_t AESCCM_s_oneStepEncryptFast(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) +{ + return AESCCM_s_oneStepOperationFast(handle, operation, AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESCCM_s_oneStepDecryptFast ======== + */ +__tz_c_veneer int_fast16_t AESCCM_s_oneStepDecryptFast(AESCCM_Handle handle, AESCCM_OneStepOperation *operation) +{ + return AESCCM_s_oneStepOperationFast(handle, operation, AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.h new file mode 100644 index 00000000..a9b7455f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26X4_s.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aesccm_AESCCMCC26X4_s__include +#define ti_drivers_aesccm_AESCCMCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES CCM secure message types + * + * For optimal performance, non-secure clients must use the + * AESCCM_s_oneStepEncryptFast and AESCCM_s_oneStepDecryptFast veneers + * instead of PSA calls with AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT + * or AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT. + */ +#define AESCCM_S_MSG_TYPE_CONSTRUCT AESCCM_S_MSG_TYPE(0U) +#define AESCCM_S_MSG_TYPE_OPEN AESCCM_S_MSG_TYPE(1U) +#define AESCCM_S_MSG_TYPE_REGISTER_CALLBACK AESCCM_S_MSG_TYPE(2U) +#define AESCCM_S_MSG_TYPE_CLOSE AESCCM_S_MSG_TYPE(3U) +#define AESCCM_S_MSG_TYPE_ONE_STEP_ENCRYPT AESCCM_S_MSG_TYPE(4U) +#define AESCCM_S_MSG_TYPE_ONE_STEP_DECRYPT AESCCM_S_MSG_TYPE(5U) +#define AESCCM_S_MSG_TYPE_SETUP_ENCRYPT AESCCM_S_MSG_TYPE(6U) +#define AESCCM_S_MSG_TYPE_SETUP_DECRYPT AESCCM_S_MSG_TYPE(7U) +#define AESCCM_S_MSG_TYPE_SET_LENGTHS AESCCM_S_MSG_TYPE(8U) +#define AESCCM_S_MSG_TYPE_SET_NONCE AESCCM_S_MSG_TYPE(9U) +#define AESCCM_S_MSG_TYPE_ADD_AAD AESCCM_S_MSG_TYPE(10U) +#define AESCCM_S_MSG_TYPE_ADD_DATA AESCCM_S_MSG_TYPE(11U) +#define AESCCM_S_MSG_TYPE_FINALIZE_ENCRYPT AESCCM_S_MSG_TYPE(12U) +#define AESCCM_S_MSG_TYPE_FINALIZE_DECRYPT AESCCM_S_MSG_TYPE(13U) +#define AESCCM_S_MSG_TYPE_CANCEL_OPERATION AESCCM_S_MSG_TYPE(14U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESCCM_construct(). + */ +#ifndef CONFIG_AESCCM_S_CONFIG_POOL_SIZE + #define CONFIG_AESCCM_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESCCM_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESCCM_COUNT + CONFIG_AESCCM_S_CONFIG_POOL_SIZE) + +/* + * ========= AES CCM Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES CCM callback fxn parameters */ + AESCCM_Handle handle; + int_fast16_t returnValue; + AESCCM_OperationUnion *operation; + AESCCM_OperationType operationType; +} AESCCM_s_SecureCallback; + +/* + * ========= AES CCM Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES CCM secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESCCM_Config *config; + const AESCCM_Params *params; +} AESCCM_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESCCM_Params *params; +} AESCCM_s_OpenMsg; + +typedef struct +{ + AESCCM_Handle handle; + AESCCM_s_SecureCallback *callback; +} AESCCM_s_CallbackMsg; + +typedef struct +{ + AESCCM_Handle handle; +} AESCCM_s_CloseMsg; + +typedef struct +{ + AESCCM_Handle handle; + AESCCM_OneStepOperation *operation; +} AESCCM_s_OneStepOperationMsg; + +typedef struct +{ + AESCCM_Handle handle; + const CryptoKey *key; + size_t aadLength; + size_t plaintextLength; + size_t macLength; +} AESCCM_s_SetupOperationMsg; + +typedef struct +{ + AESCCM_Handle handle; + size_t aadLength; + size_t plaintextLength; + size_t macLength; +} AESCCM_s_SetLengthsMsg; + +typedef struct +{ + AESCCM_Handle handle; + const uint8_t *nonce; + size_t nonceLength; +} AESCCM_s_SetNonceMsg; + +typedef struct +{ + AESCCM_Handle handle; + AESCCM_SegmentedAADOperation *operation; +} AESCCM_s_AddAADMsg; + +typedef struct +{ + AESCCM_Handle handle; + AESCCM_SegmentedDataOperation *operation; +} AESCCM_s_AddDataMsg; + +typedef struct +{ + AESCCM_Handle handle; + AESCCM_SegmentedFinalizeOperation *operation; +} AESCCM_s_FinalizeOperationMsg; + +typedef struct +{ + AESCCM_Handle handle; +} AESCCM_s_CancelOperationMsg; + +/*! + * @brief Fast veneer to perform a single-step AESCCM encryption & + * authentication operation in polling mode without the overhead of + * PSA call. + * + * @note See AESCCM_oneStepEncrypt() for full description, parameters, and + * return values. PSA_ERROR_PROGRAMMER_ERROR is an additional return + * value. + * + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses + * or handle is invalid. + */ +int_fast16_t AESCCM_s_oneStepEncryptFast(AESCCM_Handle handle, AESCCM_Operation *operation); + +/*! + * @brief Fast veneer to perform a single-step AESCCM decryption & + * verification operation in polling mode without the overhead of + * PSA call. + * + * @note See AESCCM_oneStepDecrypt() for full description, parameters, and + * return values. PSA_ERROR_PROGRAMMER_ERROR is an additional return + * value. + * + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses + * or handle is invalid. + */ +int_fast16_t AESCCM_s_oneStepDecryptFast(AESCCM_Handle handle, AESCCM_Operation *operation); + +/*! + * @brief Handles PSA messages for AES CCM secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESCCM_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES CCM secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESCCM_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.c b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.c new file mode 100644 index 00000000..caa49ca3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.c @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +/* Forward declarations */ +static void AESCCM_hwiFxn(uintptr_t arg0); +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_Operation *operation, + AESCCM_OperationType operationType); +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle); +static void AESCCM_cleanup(AESCCM_Handle handle); + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESCCM_hwiFxn ======== + */ +static void AESCCM_hwiFxn(uintptr_t arg0) +{ + AESCCMCC26XX_Object *object = ((AESCCM_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) + { + + /* Mark that we are done with the operation so that AESCCM_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else + { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCCM_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Read out the tag + * or verify it against the provided one, invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESCCM_cleanup((AESCCM_Handle)arg0); + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESCCM_Handle)arg0, + object->returnStatus, + (AESCCM_OperationUnion *)object->operation, + object->operationType); + } +} + +static void AESCCM_cleanup(AESCCM_Handle handle) +{ + AESCCMCC26XX_Object *object = handle->object; + + /* We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESCCM_OPERATION_TYPE_ENCRYPT) + { + /* If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + AESReadTag(object->operation->mac, object->operation->macLength); + } + else + { + uint8_t computedTag[AES_BLOCK_SIZE]; + /* If we are decrypting and verifying a message, we must now verify that + * the provided MAC matches the one calculated in the decryption + * operation. + */ + AESReadTag(computedTag, object->operation->macLength); + + bool macValid = CryptoUtils_buffersMatch(computedTag, object->operation->mac, object->operation->macLength); + + object->returnStatus = macValid ? object->returnStatus : AESCCM_STATUS_MAC_INVALID; + } + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} + +/* + * ======== AESCCM_init ======== + */ +void AESCCM_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESCCM_construct ======== + */ +AESCCM_Handle AESCCM_construct(AESCCM_Config *config, const AESCCM_Params *params) +{ + AESCCM_Handle handle; + AESCCMCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESCCM_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESCCM_Params *)&AESCCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCCM_close ======== + */ +void AESCCM_close(AESCCM_Handle handle) +{ + AESCCMCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCCM_startOperation ======== + */ +static int_fast16_t AESCCM_startOperation(AESCCM_Handle handle, + AESCCM_Operation *operation, + AESCCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + /* Internally generated nonces aren't supported for now */ + DebugP_assert(!operation->nonceInternallyGenerated); + + DebugP_assert(operation->nonce && (operation->nonceLength >= 7 && operation->nonceLength <= 13)); + DebugP_assert((operation->aad && operation->aadLength) || (operation->input && operation->inputLength)); + DebugP_assert(operation->mac && (operation->macLength <= 16)); + + DebugP_assert(operationType == AESCCM_OPERATION_TYPE_DECRYPT || operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + AESCCMCC26XX_Object *object = handle->object; + AESCCMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + + /* Only plaintext CryptoKeys are supported for now */ + DebugP_assert(operation->key); + DebugP_assert(operation->key->encoding == CryptoKey_PLAINTEXT); + + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return AESCCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESCCM_STATUS_SUCCESS; + object->operationCanceled = false; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + object->operationInProgress = false; + + return AESCCM_STATUS_ERROR; + } + + /* We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + object->operationInProgress = false; + + return AESCCM_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESWriteCCMInitializationVector(operation->nonce, operation->nonceLength); + + AESConfigureCCMCtrl(operation->nonceLength, operation->macLength, operationType == AESCCM_OPERATION_TYPE_ENCRYPT); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(operation->aadLength); + + if (operation->aadLength) + { + /* If aadLength were 0, AESWaitForIRQFlags() would never return as the AES_DMA_IN_DONE flag + * would never trigger. + */ + AESStartDMAOperation(operation->aad, operation->aadLength, NULL, 0); + AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + } + + /* If we are in AESCCM_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. */ + if (object->returnBehavior != AESCCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESCCM_waitForResult(handle); +} + +/* + * ======== AESCCM_waitForResult ======== + */ +static int_fast16_t AESCCM_waitForResult(AESCCM_Handle handle) +{ + AESCCMCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCCM_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here */ + AESCCM_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else + { + return AESCCM_STATUS_SUCCESS; + } +} + +/* + * ======== AESCCM_oneStepEncrypt ======== + */ +int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct) +{ + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCCM_oneStepDecrypt ======== + */ +int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle, AESCCM_Operation *operationStruct) +{ + + return AESCCM_startOperation(handle, operationStruct, AESCCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCCM_setupEncrypt ======== + */ +int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_setupDecrypt ======== + */ +int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + size_t macLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_setLengths ======== + */ +int_fast16_t AESCCM_setLengths(AESCCM_Handle handle, size_t aadLength, size_t plaintextLength, size_t macLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_setNonce ======== + */ +int_fast16_t AESCCM_setNonce(AESCCM_Handle handle, const uint8_t *nonce, size_t nonceLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_generateNonce ======== + */ +int_fast16_t AESCCM_generateNonce(AESCCM_Handle handle, uint8_t *nonce, size_t nonceSize, size_t *nonceLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_addAAD ======== + */ +int_fast16_t AESCCM_addAAD(AESCCM_Handle handle, AESCCM_SegmentedAADOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_addData ======== + */ +int_fast16_t AESCCM_addData(AESCCM_Handle handle, AESCCM_SegmentedDataOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_finalizeEncrypt ======== + */ +int_fast16_t AESCCM_finalizeEncrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_finalizeDecrypt ======== + */ +int_fast16_t AESCCM_finalizeDecrypt(AESCCM_Handle handle, AESCCM_SegmentedFinalizeOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return (AESCCM_STATUS_FEATURE_NOT_SUPPORTED); +} + +/* + * ======== AESCCM_cancelOperation ======== + */ +int_fast16_t AESCCM_cancelOperation(AESCCM_Handle handle) +{ + AESCCMCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) + { + HwiP_restore(key); + return AESCCM_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESCCM_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + if (object->returnBehavior == AESCCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESCCM_STATUS_CANCELED, + (AESCCM_OperationUnion *)object->operation, + object->operationType); + } + + return AESCCM_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.h b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.h new file mode 100644 index 00000000..8c8e9e3e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesccm/AESCCMCC26XX.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2017-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCCMCC26XX.h + * + * @brief AESCCM driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the AESCCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CCM. Only one operation + * can be carried out on the accerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure that + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesccm_AESCCMCC26XX__include +#define ti_drivers_aesccm_AESCCMCC26XX__include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESCCMCC26XX Hardware Attributes + * + * AESCCM26XX hardware attributes should be included in the board file + * and pointed to by the AESCCM_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESCCMCC26XX_HWAttrs; + +/*! + * @brief AESCCMCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESCCM_ReturnBehavior returnBehavior; + AESCCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESCCM_CallbackFxn callbackFxn; + AESCCM_Operation *operation; +} AESCCMCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesccm_AESCCMCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.c new file mode 100644 index 00000000..5c53a7a8 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.c @@ -0,0 +1,627 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESCMAC_s_SecureCallback aescmacSecureCB_ns[]; +extern AESCMACCC26X4_ns_Object aescmacObject_ns[]; + +/* + * ======== AESCMAC_ns_callbackFxn ======== + */ +void AESCMAC_ns_callbackFxn(uintptr_t arg) +{ + AESCMAC_s_SecureCallback *secureCallbackObject = (AESCMAC_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + aescmacObject_ns[index].callbackFxn(aescmacSecureCB_ns[index].handle, + aescmacSecureCB_ns[index].returnValue, + aescmacSecureCB_ns[index].operation, + aescmacSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESCMAC_ns_registerCallback ======== + */ +static psa_status_t AESCMAC_ns_registerCallback(AESCMAC_Handle handle, const AESCMAC_Params *params) +{ + AESCMAC_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCallback object */ + SecureCallback_construct(&aescmacSecureCB_ns[index].object, + AESCMAC_ns_callbackFxn, + (uintptr_t)&aescmacSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aescmacSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESCMAC_init ======== + */ +void AESCMAC_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCallback driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESCMAC_open ======== + */ +AESCMAC_Handle AESCMAC_open(uint_least8_t index, const AESCMAC_Params *params) +{ + AESCMAC_Handle handle = NULL; + AESCMAC_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCMAC_Params *)&AESCMAC_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCMAC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING)) + { + if (AESCMAC_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aescmacObject_ns[index].returnBehavior = params->returnBehavior; + aescmacObject_ns[index].callbackFxn = params->callbackFxn; + aescmacObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCMAC_construct ======== + */ +AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *params) +{ + AESCMAC_Handle handle = NULL; + AESCMAC_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCMAC_Params *)&AESCMAC_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCMAC_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING)) + { + if (AESCMAC_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aescmacObject_ns[index].returnBehavior = params->returnBehavior; + aescmacObject_ns[index].callbackFxn = params->callbackFxn; + aescmacObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCMAC_close ======== + */ +void AESCMAC_close(AESCMAC_Handle handle) +{ + AESCMAC_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aescmacSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCMAC_setupSign ======== + */ +int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key) +{ + AESCMAC_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_SETUP_SIGN, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCMAC_setupVerify ======== + */ +int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key) +{ + AESCMAC_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_SETUP_VERIFY, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCMAC_addData ======== + */ +int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + AESCMAC_s_AddDataMsg addDataMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescmacObject_ns[index].semaphoreTimeout) == false) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) && + (result != AESCMAC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescmacSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCMAC_finalize ======== + */ +int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + AESCMAC_s_FinalizeMsg finalizeMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescmacObject_ns[index].semaphoreTimeout) == false) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_FINALIZE, invecs, outvecs); + + if ((aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) && + (result != AESCMAC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescmacSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCMAC_oneStepSign ======== + */ +int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + AESCMAC_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operation; + oneStepMsg.key = key; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescmacObject_ns[index].semaphoreTimeout) == false) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_ONE_STEP_SIGN, invecs, outvecs); + + if ((aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) && + (result != AESCMAC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescmacSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCMAC_oneStepVerify ======== + */ +int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + AESCMAC_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operation; + oneStepMsg.key = key; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aescmacObject_ns[index].semaphoreTimeout) == false) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_ONE_STEP_VERIFY, invecs, outvecs); + + if ((aescmacObject_ns[index].returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) && + (result != AESCMAC_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aescmacObject_ns[index].returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aescmacSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCMAC_cancelOperation ======== + */ +int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) +{ + AESCMAC_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESCMAC_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCMAC_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCMAC_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.h new file mode 100644 index 00000000..d226629f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCMACCC26X4_ns.h + * + * @brief AESCMAC Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_aescmac_AESCMACCC26X4_ns__include +#define ti_drivers_aescmac_AESCMACCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESCMACCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESCMAC_CallbackFxn callbackFxn; + AESCMAC_ReturnBehavior returnBehavior; +} AESCMACCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescmac_AESCMACCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.c new file mode 100644 index 00000000..e86314d9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.c @@ -0,0 +1,953 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESCMACCC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESCMAC_Operation *operation_ns; /* Pointer to non-secure operation */ + AESCMAC_Operation operation_s; /* Secure copy of operation */ +} AESCMAC_s_Operation; + +static AESCMAC_s_Operation AESCMAC_s_operation; + +/* + * AES CMAC Secure Dynamic Instance struct. + */ +typedef struct +{ + AESCMAC_Config config; + AESCMACCC26XX_Object object; + AESCMACCC26XX_HWAttrs hwAttrs; +} AESCMAC_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESCMAC_construct. + */ +static AESCMAC_s_DynamicInstance AESCMAC_s_dynInstance[CONFIG_AESCMAC_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESCMAC_s_SecureCallbacks for each driver instance opened or constructed */ +static AESCMAC_s_SecureCallback *AESCMAC_s_secureCB[AESCMAC_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESCMAC_Config AESCMAC_config[]; + +/* + * ======== AESCMAC_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t AESCMAC_s_getCallbackIndex(AESCMAC_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESCMAC_COUNT; index++) + { + if (handle_s == (AESCMAC_Handle)&AESCMAC_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESCMAC_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESCMAC_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESCMAC_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESCMAC_s_hwiCallback ======== + */ +static void AESCMAC_s_hwiCallback(AESCMAC_Handle handle_s, + int_fast16_t returnValue, + AESCMAC_Operation *operation, + AESCMAC_OperationType operationType) +{ + int8_t index; + AESCMAC_s_SecureCallback *aescmacSecureCB_ns; + + index = AESCMAC_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESCMAC_SECURE_CALLBACK_COUNT)) + { + aescmacSecureCB_ns = AESCMAC_s_secureCB[index]; + + if (aescmacSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aescmacSecureCB_ns->handle = (AESCMAC_Handle)(CRYPTO_S_HANDLE_ID_AESCMAC | index); + aescmacSecureCB_ns->returnValue = returnValue; + aescmacSecureCB_ns->operation = AESCMAC_s_operation.operation_ns; + aescmacSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aescmacSecureCB_ns->object); + } + } +} + +/* + * ======== AESCMAC_s_copyConfig ======== + */ +static inline psa_status_t AESCMAC_s_copyConfig(AESCMAC_Config **secureConfig, + const AESCMAC_Config *config, + AESCMAC_Handle *retHandle) +{ + AESCMAC_Config *config_s; + AESCMAC_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESCMAC_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESCMAC_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCMAC_s_secureCB[i + CONFIG_TI_DRIVERS_AESCMAC_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESCMAC OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESCMAC_Handle)(CRYPTO_S_HANDLE_ID_AESCMAC | (i + CONFIG_TI_DRIVERS_AESCMAC_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} +/* + * ======== AESCMAC_s_releaseConfig ======== + */ +static inline void AESCMAC_s_releaseConfig(AESCMAC_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCMAC) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESCMAC_COUNT) && (i < AESCMAC_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESCMAC_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCMAC_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESCMAC_s_copyOperation ======== + */ +psa_status_t AESCMAC_s_copyOperation(AESCMAC_Operation *secureOperation, + const AESCMAC_Operation *operation, + AESCMAC_OperationType operationType) +{ + psa_status_t status = PSA_SUCCESS; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCMAC_Operation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCMAC_Operation)); + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Verify MAC address range - MAC is an output for sign operation, and an + * input for verify operation. MAC pointer is only used for one-step and + * finalize operations. + */ + if ((operationType & AESCMAC_OP_CODE_SEGMENTED) == 0) + { + if ((operationType & AESCMAC_OP_FLAG_SIGN) == 0) + { + /* Verify operation */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + status = PSA_ERROR_PROGRAMMER_ERROR; + } + } + else + { + /* Sign operation */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + status = PSA_ERROR_PROGRAMMER_ERROR; + } + } + } + + return status; +} + +/* + * ======== AESCMAC_s_copyParams ======== + */ +static psa_status_t AESCMAC_s_copyParams(AESCMAC_Params *secureParams, const AESCMAC_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESCMAC_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESCMAC_Params)); + + /* Validate the operational mode and return behavior */ + if (((secureParams->operationalMode == AESCMAC_OPMODE_CMAC) || + (secureParams->operationalMode == AESCMAC_OPMODE_CBCMAC)) && + ((secureParams->returnBehavior == AESCMAC_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING))) + { + if (secureParams->returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESCMAC_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESCMAC_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESCMAC_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESCMAC_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESCMAC_Handle AESCMAC_s_getHandle(AESCMAC_Handle nsHandle) +{ + AESCMAC_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCMAC) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESCMAC_COUNT) + { + secureHandle = (AESCMAC_Handle)&AESCMAC_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESCMAC_COUNT) && (i < AESCMAC_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESCMAC_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCMAC_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESCMAC_s_registerCallback ======== + */ +static inline psa_status_t AESCMAC_s_registerCallback(psa_msg_t *msg) +{ + AESCMAC_Handle handle_s; + AESCMAC_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESCMAC_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESCMAC_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESCMAC_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESCMAC_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESCMAC_s_SecureCallback located in + * non-secure memory. + */ + AESCMAC_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCMAC_s_construct ======== + */ +static inline psa_status_t AESCMAC_s_construct(psa_msg_t *msg) +{ + AESCMAC_s_ConstructMsg constructMsg; + AESCMAC_Handle handle; + AESCMAC_Params params_s; + const AESCMAC_Params *paramsPtr_s = NULL; + AESCMAC_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESCMAC_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESCMAC_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESCMAC_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESCMAC_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCMAC_s_open ======== + */ +static inline psa_status_t AESCMAC_s_open(psa_msg_t *msg) +{ + AESCMAC_s_OpenMsg openMsg; + AESCMAC_Handle handle; + AESCMAC_Params params_s; + AESCMAC_Params *paramsPtr_s = NULL; + AESCMAC_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESCMAC_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESCMAC_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCMAC_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESCMAC OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESCMAC_Handle)(CRYPTO_S_HANDLE_ID_AESCMAC | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCMAC_s_close ======== + */ +static inline psa_status_t AESCMAC_s_close(psa_msg_t *msg) +{ + AESCMAC_Handle handle_s; + AESCMAC_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCMAC_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESCMAC_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESCMAC_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESCMAC_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCMAC_s_oneStepOperation ======== + */ +static inline psa_status_t AESCMAC_s_oneStepOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCMAC_s_OneStepOperationMsg oneStepMsg; + AESCMAC_Handle handle_s; + AESCMAC_Operation *operation_s; + AESCMACCC26XX_Object *object; + CryptoKey key_s; + CryptoKey *keyPtr_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(oneStepMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &oneStepMsg, sizeof(oneStepMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCMAC_s_getHandle(oneStepMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + + operation_s = &AESCMAC_s_operation.operation_s; + + /* Save pointer to non-secure operation struct */ + AESCMAC_s_operation.operation_ns = oneStepMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCMAC_s_copyOperation(operation_s, oneStepMsg.operation, object->operationType); + if (status != PSA_SUCCESS) + { + return status; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)oneStepMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, oneStepMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = oneStepMsg.handle; + operation_s = oneStepMsg.operation; + keyPtr_s = oneStepMsg.key; + } + + if (msgType == AESCMAC_S_MSG_TYPE_ONE_STEP_SIGN) + { + ret = AESCMAC_oneStepSign(handle_s, operation_s, keyPtr_s); + } + else + { + ret = AESCMAC_oneStepVerify(handle_s, operation_s, keyPtr_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCMAC_s_setupOperation ======== + */ +static inline psa_status_t AESCMAC_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCMAC_s_SetupOperationMsg setupMsg; + AESCMAC_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCMAC_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESCMAC_S_MSG_TYPE_SETUP_SIGN) + { + ret = AESCMAC_setupSign(handle_s, keyPtr_s); + } + else + { + ret = AESCMAC_setupVerify(handle_s, keyPtr_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCMAC_s_addData ======== + */ +static inline psa_status_t AESCMAC_s_addData(psa_msg_t *msg) +{ + AESCMAC_Handle handle_s; + AESCMAC_Operation *operation_s; + AESCMAC_s_AddDataMsg addDataMsg; + AESCMACCC26XX_Object *object; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCMAC_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + + operation_s = &AESCMAC_s_operation.operation_s; + + /* Save pointer to non-secure operation struct */ + AESCMAC_s_operation.operation_ns = addDataMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCMAC_s_copyOperation(operation_s, addDataMsg.operation, object->operationType); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCMAC_addData(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCMAC_addData(addDataMsg.handle, addDataMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCMAC_s_finalizeOperation ======== + */ +static inline psa_status_t AESCMAC_s_finalizeOperation(psa_msg_t *msg) +{ + AESCMAC_s_FinalizeMsg finalizeMsg; + AESCMAC_Operation *operation_s; + AESCMAC_Handle handle_s; + AESCMACCC26XX_Object *object; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCMAC_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + operation_s = &AESCMAC_s_operation.operation_s; + + /* Save pointer to non-secure operation struct */ + AESCMAC_s_operation.operation_ns = finalizeMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCMAC_s_copyOperation(operation_s, finalizeMsg.operation, object->operationType); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCMAC_finalize(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCMAC_finalize(finalizeMsg.handle, finalizeMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCMAC_s_cancelOperation ======== + */ +static inline psa_status_t AESCMAC_s_cancelOperation(psa_msg_t *msg) +{ + AESCMAC_Handle handle_s; + AESCMAC_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESCMAC_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESCMAC_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCMAC_s_handlePsaMsg ======== + */ +psa_status_t AESCMAC_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESCMAC_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESCMAC_S_MSG_TYPE_CONSTRUCT: + status = AESCMAC_s_construct(msg); + break; + + case AESCMAC_S_MSG_TYPE_OPEN: + status = AESCMAC_s_open(msg); + break; + + /* + * AESCMAC_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESCMAC_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESCMAC_s_registerCallback(msg); + break; + + case AESCMAC_S_MSG_TYPE_CLOSE: + status = AESCMAC_s_close(msg); + break; + + case AESCMAC_S_MSG_TYPE_ONE_STEP_SIGN: /* Fall through */ + case AESCMAC_S_MSG_TYPE_ONE_STEP_VERIFY: + status = AESCMAC_s_oneStepOperation(msg, msg->type); + break; + + case AESCMAC_S_MSG_TYPE_SETUP_SIGN: /* Fall through */ + case AESCMAC_S_MSG_TYPE_SETUP_VERIFY: + status = AESCMAC_s_setupOperation(msg, msg->type); + break; + + case AESCMAC_S_MSG_TYPE_ADD_DATA: + status = AESCMAC_s_addData(msg); + break; + + case AESCMAC_S_MSG_TYPE_FINALIZE: + status = AESCMAC_s_finalizeOperation(msg); + break; + + /* + * AESCMAC_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESCMAC_S_MSG_TYPE_CANCEL_OPERATION: + status = AESCMAC_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESCMAC_s_init ======== + */ +void AESCMAC_s_init(void) +{ + AESCMAC_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.h new file mode 100644 index 00000000..97541813 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26X4_s.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aescmac_AESCMACCC26X4_s__include +#define ti_drivers_aescmac_AESCMACCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES CMAC secure message types + */ +#define AESCMAC_S_MSG_TYPE_CONSTRUCT AESCMAC_S_MSG_TYPE(0U) +#define AESCMAC_S_MSG_TYPE_OPEN AESCMAC_S_MSG_TYPE(1U) +#define AESCMAC_S_MSG_TYPE_REGISTER_CALLBACK AESCMAC_S_MSG_TYPE(2U) +#define AESCMAC_S_MSG_TYPE_CLOSE AESCMAC_S_MSG_TYPE(3U) +#define AESCMAC_S_MSG_TYPE_ONE_STEP_SIGN AESCMAC_S_MSG_TYPE(4U) +#define AESCMAC_S_MSG_TYPE_ONE_STEP_VERIFY AESCMAC_S_MSG_TYPE(5U) +#define AESCMAC_S_MSG_TYPE_SETUP_SIGN AESCMAC_S_MSG_TYPE(6U) +#define AESCMAC_S_MSG_TYPE_SETUP_VERIFY AESCMAC_S_MSG_TYPE(7U) +#define AESCMAC_S_MSG_TYPE_ADD_DATA AESCMAC_S_MSG_TYPE(8U) +#define AESCMAC_S_MSG_TYPE_FINALIZE AESCMAC_S_MSG_TYPE(9U) +#define AESCMAC_S_MSG_TYPE_CANCEL_OPERATION AESCMAC_S_MSG_TYPE(10U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESCMAC_construct(). + */ +#ifndef CONFIG_AESCMAC_S_CONFIG_POOL_SIZE + #define CONFIG_AESCMAC_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESCMAC_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESCMAC_COUNT + CONFIG_AESCMAC_S_CONFIG_POOL_SIZE) + +/* + * ========= AES CMAC Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES CMAC callback fxn parameters */ + AESCMAC_Handle handle; + int_fast16_t returnValue; + AESCMAC_Operation *operation; + AESCMAC_OperationType operationType; +} AESCMAC_s_SecureCallback; + +/* + * ========= AES CMAC Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES CMAC secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESCMAC_Config *config; + const AESCMAC_Params *params; +} AESCMAC_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESCMAC_Params *params; +} AESCMAC_s_OpenMsg; + +typedef struct +{ + AESCMAC_Handle handle; + AESCMAC_s_SecureCallback *callback; +} AESCMAC_s_CallbackMsg; + +typedef struct +{ + AESCMAC_Handle handle; +} AESCMAC_s_CloseMsg; + +typedef struct +{ + AESCMAC_Handle handle; + AESCMAC_Operation *operation; + CryptoKey *key; +} AESCMAC_s_OneStepOperationMsg; + +typedef struct +{ + AESCMAC_Handle handle; + const CryptoKey *key; +} AESCMAC_s_SetupOperationMsg; + +typedef struct +{ + AESCMAC_Handle handle; + AESCMAC_Operation *operation; +} AESCMAC_s_AddDataMsg; + +typedef AESCMAC_s_AddDataMsg AESCMAC_s_FinalizeMsg; + +typedef struct +{ + AESCMAC_Handle handle; +} AESCMAC_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for AES CMAC secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESCMAC_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES CMAC secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESCMAC_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescmac_AESCMACCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.c b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.c new file mode 100644 index 00000000..019db4e4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.c @@ -0,0 +1,1214 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE / 4) + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0FU + +#define AESCMAC_CONST_RB ((uint8_t)0x87U) +#define AESCMAC_MSB_CHECK ((uint8_t)0x80U) +#define AESCMAC_PADDING ((uint8_t)0x80U) + +typedef enum +{ + AESCMAC_SUBKEY1, + AESCMAC_SUBKEY2 +} AESCMAC_SUBKEY_NUM; + +/* Forward declarations */ +static void AESCMAC_hwiFxn(uintptr_t arg0); +static int_fast16_t AESCMAC_setOperationInProgress(AESCMACCC26XX_Object *object); +static int_fast16_t AESCMAC_startOneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + CryptoKey *key, + AESCMAC_OperationType operationType); +static int_fast16_t AESCMAC_processData(AESCMAC_Handle handle); +static inline int_fast16_t AESCMAC_waitForResult(AESCMACCC26XX_Object *object); +static void AESCMAC_cleanup(AESCMACCC26XX_Object *object); +static void AESCMAC_getResult(AESCMACCC26XX_Object *object, bool isAfterDMAExecution); +static inline void AESCMAC_prepareFinalInputBlock(AESCMACCC26XX_Object *object, size_t *transactionLength); +static inline void AESCMAC_processFinalInputBlock(AESCMACCC26XX_Object *object); +static int_fast16_t AESCMAC_setupSegmentedOperation(AESCMACCC26XX_Object *object, const CryptoKey *key); +static int_fast16_t AESCMAC_loadKey(AESCMACCC26XX_Object *object); +static int_fast16_t AESCMAC_loadContext(AESCMACCC26XX_Object *object, size_t inputLength); +static void AESCMAC_deriveSubKey(uint8_t *buffer); +static inline void AESCMAC_xorBlock(uint32_t *block1_dst, const uint32_t *block2); +static int_fast16_t AESCMAC_generateSubKey(AESCMACCC26XX_Object *object, + AESCMAC_SUBKEY_NUM subKeyNum, + uint32_t *subKey); + +/* Static globals */ +static bool AESCMAC_isInitialized = false; + +/* + * ======== AESCMAC_processFinalInputBlock ======== + */ +static inline void AESCMAC_processFinalInputBlock(AESCMACCC26XX_Object *object) +{ + object->returnStatus = AESCMAC_loadContext(object, AES_BLOCK_SIZE); + + /* AESCMAC_loadContext() calls AESWriteKeyStore() which enables + * CRYPTO IRQ so we must disable it to poll for completion of + * the final input block. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + if (object->returnStatus == AESCMAC_STATUS_SUCCESS) + { + /* Start the input DMA. There is no output DMA. */ + AESStartDMAOperation((uint8_t *)object->buffer, AES_BLOCK_SIZE, NULL, 0U); + + /* Wait until the operation is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCMAC_STATUS_ERROR; + } + else + { + if (AESReadTag((uint8_t *)object->intermediateTag, AES_BLOCK_SIZE) != AES_SUCCESS) + { + object->returnStatus = AESCMAC_STATUS_ERROR; + } + } + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + } +} + +/* + * ======== AESCMAC_getResult ======== + */ +static void AESCMAC_getResult(AESCMACCC26XX_Object *object, bool isAfterDMAExecution) +{ + AESCMAC_Operation *operation = object->operation; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + + /* If DMA was executed, read the output tag */ + if (isAfterDMAExecution) + { + if (AESReadTag((uint8_t *)object->intermediateTag, AES_BLOCK_SIZE) != AES_SUCCESS) + { + object->returnStatus = AESCMAC_STATUS_ERROR; + } + } + + /* If CMAC One-step or Final operation, process the final input block */ + if ((object->operationalMode == AESCMAC_OPMODE_CMAC) && (opcode != AESCMAC_OP_CODE_SEGMENTED) && + (object->returnStatus == AESCMAC_STATUS_SUCCESS)) + { + AESCMAC_processFinalInputBlock(object); + } + + /* If One-step or Final operation, verify or copy the MAC */ + if ((opcode != AESCMAC_OP_CODE_SEGMENTED) && (object->returnStatus == AESCMAC_STATUS_SUCCESS)) + { + if (object->operationType & AESCMAC_OP_FLAG_SIGN) + { + memcpy(operation->mac, object->intermediateTag, operation->macLength); + } + else + { + /* Constant time comparison of output tag versus provided MAC */ + if (!CryptoUtils_buffersMatch(object->intermediateTag, operation->mac, operation->macLength)) + { + object->returnStatus = AESCMAC_STATUS_MAC_INVALID; + } + } + } +} + +/* + * ======== AESCMAC_hwiFxn ======== + */ +static void AESCMAC_hwiFxn(uintptr_t arg0) +{ + AESCMACCC26XX_Object *object = ((AESCMAC_Handle)arg0)->object; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + uintptr_t interruptKey; + + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + /* Propagate the DMA error from driverlib to the application */ + object->returnStatus = AESCMAC_STATUS_ERROR; + } + else /* Must be RESULT_AVAIL because DMA_IN_DONE was disabled */ + { + AESCMAC_getResult(object, true); + } + + /* AESCMAC_getResult() needs to perform a polling HW operation to process + * the final input block for CMAC so hwBusy and operationInProgress flags + * are not cleared until afterward. + */ + interruptKey = HwiP_disable(); + + /* Mark that we are done with the operation so that + * AESCMAC_cancelOperation knows not to try canceling. + */ + object->hwBusy = false; + + /* Mark operation as no longer in-progress if one-step or final operation */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + AESIntClear(AES_RESULT_RDY | AES_DMA_BUS_ERR); + + /* Handle clean up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + * + * When the access semaphore is freed during cleanup, + * if a higher priority ISR shares this driver instance and wishes + * to start a new operation, it must handle synchronization with + * the other thread(s) sharing this driver instance to avoid + * corrupting the driver's object data by starting a new operation + * before the callback is executed for the current operation. + */ + AESCMAC_cleanup(object); + + if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else /* AESCMAC_RETURN_BEHAVIOR_CALLBACK */ + { + /* Call the callback function provided by the application */ + object->callbackFxn((AESCMAC_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCMAC_cleanup ======== + */ +static void AESCMAC_cleanup(AESCMACCC26XX_Object *object) +{ + /* Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use without + * reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* NOTE: IV register may contain intermediate or final tag but we are + * not required to clear it since this information is not valuable to + * an attacker. + */ + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides + * small power savings. + */ + AESSelectAlgorithm(0U); + + if (object->returnBehavior != AESCMAC_RETURN_BEHAVIOR_POLLING) + { + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the + * chaining of operations. + */ + if (object->cryptoResourceLocked) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } +} + +/* + * ======== AESCMAC_init ======== + */ +void AESCMAC_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + AESCMAC_isInitialized = true; +} + +/* + * ======== AESCMAC_construct ======== + */ +AESCMAC_Handle AESCMAC_construct(AESCMAC_Config *config, const AESCMAC_Params *params) +{ + DebugP_assert(config); + DebugP_assert(params); + + AESCMAC_Handle handle = config; + AESCMACCC26XX_Object *object = handle->object; + + DebugP_assert(object); + + uintptr_t interruptKey = HwiP_disable(); + + if (!AESCMAC_isInitialized || object->isOpen) + { + HwiP_restore(interruptKey); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(interruptKey); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESCMAC_Params *)&AESCMAC_defaultParams; + } + + DebugP_assert((params->returnBehavior != AESCMAC_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->returnBehavior = params->returnBehavior; + object->operationalMode = params->operationalMode; + object->callbackFxn = params->callbackFxn; + if (params->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + object->semaphoreTimeout = params->timeout; + } + else + { + object->semaphoreTimeout = SemaphoreP_NO_WAIT; + } + object->threadSafe = true; + object->cryptoResourceLocked = false; + object->hwBusy = false; + object->operationInProgress = false; + + /* Set power dependency - i.e. power up and enable clock for Crypto + * (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCMAC_close ======== + */ +void AESCMAC_close(AESCMAC_Handle handle) +{ + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + AESCMACCC26XX_Object *object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCMAC_loadKey ======== + */ +static int_fast16_t AESCMAC_loadKey(AESCMACCC26XX_Object *object) +{ + size_t keyLength; + uint8_t *keyingMaterial = NULL; + int_fast16_t status = AESCMAC_STATUS_SUCCESS; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* Only plaintext CryptoKeys are supported for now */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || + (object->key.encoding == CryptoKey_BLANK_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if ((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_BLANK_PLAINTEXT)) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + switch (object->operationType) + { + case AESCMAC_OP_TYPE_SIGN: + case AESCMAC_OP_TYPE_FINALIZE_SIGN: + case AESCMAC_OP_TYPE_SEGMENTED_SIGN: + keyUsage = KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE; + break; + + case AESCMAC_OP_TYPE_VERIFY: + case AESCMAC_OP_TYPE_FINALIZE_VERIFY: + case AESCMAC_OP_TYPE_SEGMENTED_VERIFY: + keyUsage = KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE; + break; + + default: + return AESCMAC_STATUS_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + (object->operationalMode == AESCMAC_OPMODE_CMAC) + ? KEYSTORE_PSA_ALG_CMAC + : KEYSTORE_PSA_ALG_CBC_MAC, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESCMAC_STATUS_KEYSTORE_INVALID_ID; + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESCMAC_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESCMAC_STATUS_ERROR; + } + + DebugP_assert(keyingMaterial); + DebugP_assert((keyLength == AES_128_KEY_LENGTH_BYTES) || (keyLength == AES_192_KEY_LENGTH_BYTES) || + (keyLength == AES_256_KEY_LENGTH_BYTES)); + + /* Workaround for a bug in AESWriteToKeyStore() as it invalidates only + * the key area provided as an argument and not the subsequent key + * area which is required when using key lengths greater than 128-bits. + */ + AESInvalidateKey(AES_KEY_AREA_7); + + /* Load the key from RAM or flash into the key store at a hardcoded and + * reserved location. + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + status = AESCMAC_STATUS_ERROR; + } + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* AESWriteToKeyStore() enables both DMA_IN_DONE and RESULT_AVAIL + * interrupts but since this driver only depends on RESULT_AVAIL, + * disable the DMA_IN_DONE interrupt to simplify handling. + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the + * AES sub-module known as AES_KEY1. + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use without + * reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides + * small power savings. + */ + AESSelectAlgorithm(0U); + + status = AESCMAC_STATUS_ERROR; + } + + /* Write zeros to AES_KEY2 and AES_KEY3 registers */ + AESCBCMACClearKeys(); + } + + return status; +} + +/* + * ======== AESCMAC_loadContext ======== + */ +static int_fast16_t AESCMAC_loadContext(AESCMACCC26XX_Object *object, size_t inputLength) +{ + int_fast16_t status; + + status = AESCMAC_loadKey(object); + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* Set IV to intermediate tag (initialized to zero at the start + * of a new operation). + */ + AESSetInitializationVector(object->intermediateTag); + + AESSetCtrl(CRYPTO_AESCTL_CBC_MAC | CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_DIR); + + AESSetDataLength(inputLength); + AESSetAuthLength(0U); + } + + return status; +} + +/* + * ======== AESCMAC_processData ======== + */ +static int_fast16_t AESCMAC_processData(AESCMAC_Handle handle) +{ + AESCMACCC26XX_Object *object = handle->object; + AESCMAC_Operation *operation = object->operation; + AESCMAC_OperationType operationType; + bool isResultHandled = false; + int_fast16_t status = AESCMAC_STATUS_ERROR; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + AESCMACCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + size_t transactionLength = operation->inputLength; + + /* Input pointer cannot be NULL if input length is non-zero */ + DebugP_assert((operation->inputLength == 0U) || operation->input); + + /* MAC pointer cannot be NULL if performing a one-step operation or + * finalizing a segmented operation */ + DebugP_assert((opcode == AESCMAC_OP_CODE_SEGMENTED) || (operation->mac)); + + /* We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback with + * the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCMAC_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* If CMAC One-step or Finalization operation, prepare the final input + * block and adjust the transaction length accordingly. + */ + if ((object->operationalMode == AESCMAC_OPMODE_CMAC) && (opcode != AESCMAC_OP_CODE_SEGMENTED)) + { + AESCMAC_prepareFinalInputBlock(object, &transactionLength); + } + + if (object->returnStatus == AESCMAC_STATUS_SUCCESS) + { + if (transactionLength == 0U) + { + /* If transaction length is zero, only the last locally buffered block + * of data remains to be processed for CMAC. Call AESCMAC_getResult() + * to process the last block, obtain the result, and store status of + * the operation in object->returnStatus. + */ + AESCMAC_getResult(object, false); + } + else + { + status = AESCMAC_loadContext(object, transactionLength); + + if (status == AESCMAC_STATUS_SUCCESS) + { + if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + /* AESCMAC_loadContext() calls AESWriteKeyStore() which enables + * CRYPTO IRQ so we must disable it when in polling mode. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + else + { + /* Prevent system from entering standby and powering down Crypto + * peripheral while the operation is running. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + object->hwBusy = true; + + /* Start the input DMA. There is no output DMA. */ + AESStartDMAOperation(operation->input, transactionLength, NULL, 0U); + + status = AESCMAC_waitForResult(object); + isResultHandled = true; + } + } + } + + if (!isResultHandled) + { + /* Save the object's data to provide to callback in case it + * is overwritten during by the start of a new operation + * after the operationInProgress flag is cleared or access + * semaphore is posted. + */ + status = object->returnStatus; + operationType = object->operationType; + + object->operationInProgress = false; + + /* Handle clean up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + */ + AESCMAC_cleanup(object); + + if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application + * to provide actual status of the operation. + */ + object->callbackFxn(handle, status, operation, operationType); + + /* Always return success in callback mode */ + status = AESCMAC_STATUS_SUCCESS; + } + } + else if (status != AESCMAC_STATUS_SUCCESS) + { + /* Save the failure status in case the application ignores the return + * value so the driver can reject any attempts to continue a failed + * segmented operation. + */ + object->returnStatus = status; + } + + return status; +} + +/* + * ======== AESCMAC_xorBlock ======== + * XOR's two 16-byte blocks, storing the result in block1_dst. + */ +static inline void AESCMAC_xorBlock(uint32_t *block1_dst, const uint32_t *block2) +{ + uint_fast8_t i; + + for (i = 0U; i < AES_BLOCK_SIZE_WORDS; i++) + { + block1_dst[i] = block1_dst[i] ^ block2[i]; + } +} + +/* + * ======== AESCMAC_prepareFinalInputBlock ======== + */ +static inline void AESCMAC_prepareFinalInputBlock(AESCMACCC26XX_Object *object, size_t *transactionLength) +{ + AESCMAC_Operation *operation = object->operation; + size_t finalInputLength = 0U; + size_t truncatedInputLength = 0U; + uint32_t subKey[AES_BLOCK_SIZE_WORDS]; + + /* Copy last partial or full block of input into local buffer */ + memset(object->buffer, 0, AES_BLOCK_SIZE); + + if (operation->inputLength != 0U) + { + finalInputLength = operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK; + + if (finalInputLength == 0U) + { + finalInputLength = AES_BLOCK_SIZE; + } + + truncatedInputLength = operation->inputLength - finalInputLength; + + memcpy(object->buffer, &operation->input[truncatedInputLength], finalInputLength); + } + + /* Check if input message length is a positive block multiple */ + if ((operation->inputLength != 0U) && (finalInputLength == AES_BLOCK_SIZE)) + { + /* Generate subkey1 */ + object->returnStatus = AESCMAC_generateSubKey(object, AESCMAC_SUBKEY1, subKey); + } + else + { + /* Generate subkey2 */ + object->returnStatus = AESCMAC_generateSubKey(object, AESCMAC_SUBKEY2, subKey); + + /* Set padding byte if partial block */ + ((uint8_t *)object->buffer)[finalInputLength] = AESCMAC_PADDING; + } + + if (object->returnStatus == AESCMAC_STATUS_SUCCESS) + { + /* XOR final block with subkey */ + AESCMAC_xorBlock(object->buffer, subKey); + + *transactionLength = truncatedInputLength; + } +} + +/* + * ======== AESCMAC_startOneStepOperation ======== + */ +static int_fast16_t AESCMAC_startOneStepOperation(AESCMAC_Handle handle, + AESCMAC_Operation *operation, + CryptoKey *key, + AESCMAC_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(key); + /* No need to assert operationType since we control it within the driver */ + + AESCMACCC26XX_Object *object = handle->object; + int_fast16_t status; + + /* CBC-MAC is not permitted for zero length messages */ + if ((object->operationalMode == AESCMAC_OPMODE_CBCMAC) && (operation->inputLength == 0)) + { + return AESCMAC_STATUS_ERROR; + } + + /* Check that there is no operation already in progress for this driver + * instance. + */ + status = AESCMAC_setOperationInProgress(object); + + if (status != AESCMAC_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + object->operationInProgress = false; + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operation = operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->returnStatus = AESCMAC_STATUS_SUCCESS; + /* Make internal copy of crypto key */ + object->key = *key; + + /* Zero the intermediate tag because it will be used as the IV */ + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + + status = AESCMAC_processData(handle); + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + return status; +} + +/* + * ======== AESCMAC_waitForResult ======== + */ +static inline int_fast16_t AESCMAC_waitForResult(AESCMACCC26XX_Object *object) +{ + int_fast16_t status = AESCMAC_STATUS_ERROR; + uint8_t opcode = (object->operationType & AESCMAC_OP_CODE_MASK); + + if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCMAC_STATUS_ERROR; + } + else + { + AESCMAC_getResult(object, true); + } + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + /* Save the object's returnStatus before clearing operationInProgress or + * posting the access semaphore in case it is overwritten. + */ + status = object->returnStatus; + + /* Mark operation as no longer in progress if one-step or final operation */ + if (opcode != AESCMAC_OP_CODE_SEGMENTED) + { + object->operationInProgress = false; + } + + AESCMAC_cleanup(object); + } + else if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + status = object->returnStatus; + } + else /* AESCMAC_RETURN_BEHAVIOR_CALLBACK */ + { + /* AESCMAC_STATUS_SUCCESS is always returned in callback mode */ + status = AESCMAC_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCMAC_oneStepSign ======== + */ +int_fast16_t AESCMAC_oneStepSign(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + return AESCMAC_startOneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_SIGN); +} + +/* + * ======== AESCMAC_oneStepVerify ======== + */ +int_fast16_t AESCMAC_oneStepVerify(AESCMAC_Handle handle, AESCMAC_Operation *operation, CryptoKey *key) +{ + return AESCMAC_startOneStepOperation(handle, operation, key, AESCMAC_OP_TYPE_VERIFY); +} + +/* + * ======== AESCMAC_setOperationInProgress ======== + */ +static int_fast16_t AESCMAC_setOperationInProgress(AESCMACCC26XX_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + return AESCMAC_STATUS_ERROR; + } + object->operationInProgress = true; + HwiP_restore(interruptKey); + return AESCMAC_STATUS_SUCCESS; +} + +/* + * ======== AESCMAC_setupSegmentedOperation ======== + */ +static int_fast16_t AESCMAC_setupSegmentedOperation(AESCMACCC26XX_Object *object, const CryptoKey *key) +{ + DebugP_assert(key); + + /* Key material pointer and length are not asserted until adding or + * finalizing data. + */ + + /* Check that there is no operation already in progress for this driver + * instance. + */ + int_fast16_t status = AESCMAC_setOperationInProgress(object); + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* We will only change the returnStatus if there is an error or cancellation */ + object->returnStatus = AESCMAC_STATUS_SUCCESS; + /* Make internal copy of crypto key */ + object->key = *key; + + /* Zero the intermediate tag because it will be used as the IV */ + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + } + + return status; +} + +/* + * ======== AESCMAC_setupSign ======== + */ +int_fast16_t AESCMAC_setupSign(AESCMAC_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + AESCMACCC26XX_Object *object = handle->object; + DebugP_assert(object); + + int_fast16_t status = AESCMAC_setupSegmentedOperation(object, key); + + if (status == AESCMAC_STATUS_SUCCESS) + { + object->operationType = AESCMAC_OP_TYPE_SEGMENTED_SIGN; + } + + return status; +} + +/* + * ======== AESCMAC_setupVerify ======== + */ +int_fast16_t AESCMAC_setupVerify(AESCMAC_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + AESCMACCC26XX_Object *object = handle->object; + DebugP_assert(object); + + int_fast16_t status = AESCMAC_setupSegmentedOperation(object, key); + + if (status == AESCMAC_STATUS_SUCCESS) + { + object->operationType = AESCMAC_OP_TYPE_SEGMENTED_VERIFY; + } + + return status; +} + +/* + * ======== AESCMAC_addData ======== + */ +int_fast16_t AESCMAC_addData(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACCC26XX_Object *object = handle->object; + int_fast16_t status; + + /* Check for previous failure or cancellation of segmented operation */ + if (object->returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->returnStatus; + } + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || (operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK)) + { + return AESCMAC_STATUS_ERROR; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + if ((object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) || + (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY)) + { + object->operation = operation; + status = AESCMAC_processData(handle); + } + else + { + status = AESCMAC_STATUS_ERROR; + } + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + + return status; +} + +/* + * ======== AESCMAC_generateSubKey ======== + * Generate AES CMAC subkey based on + * https://tools.ietf.org/html/rfc4493#section-2.3 + */ +static int_fast16_t AESCMAC_generateSubKey(AESCMACCC26XX_Object *object, AESCMAC_SUBKEY_NUM subKeyNum, uint32_t *subKey) +{ + uint32_t zeroBlock[AES_BLOCK_SIZE_WORDS] = {0}; + int_fast16_t status = AESCMAC_loadKey(object); + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* AESWriteKeyStore() enables the CRYPTO IRQ so we must disable it + * to poll for completion. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* Perform AES ECB encryption on a block of 0's */ + AESSetDataLength(AES_BLOCK_SIZE); + AESSetAuthLength(0U); + AESSetCtrl(CRYPTO_AESCTL_DIR); + + /* Start the DMA input of a zeroed block and output to the subKey buffer */ + AESStartDMAOperation((uint8_t *)zeroBlock, AES_BLOCK_SIZE, (uint8_t *)subKey, AES_BLOCK_SIZE); + + /* Wait until the operation is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + status = AESCMAC_STATUS_ERROR; + } + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + if (status == AESCMAC_STATUS_SUCCESS) + { + /* At this point, subKey buffer only has the ciphertext + * generated by encrypting a block of 0's. + * Derive SubKey1. */ + AESCMAC_deriveSubKey((uint8_t *)subKey); + + if (subKeyNum == AESCMAC_SUBKEY2) + { + /* At this point, subKey buffer contains SubKey1. + * Derive SubKey2. */ + AESCMAC_deriveSubKey((uint8_t *)subKey); + } + } + + return status; +} + +/* + * ======== AESCMAC_deriveSubKey ======== + */ +static void AESCMAC_deriveSubKey(uint8_t *buffer) +{ + uint_fast8_t i; + uint8_t xorMask = 0U; + + if ((buffer[0] & AESCMAC_MSB_CHECK) != 0U) + { + xorMask = AESCMAC_CONST_RB; + } + + /* Left shift buffer by 1 position */ + for (i = 0U; i < AES_BLOCK_SIZE; i += 1U) + { + if (i != 0U) + { + buffer[i - 1U] += (buffer[i] >> 7U); + } + + buffer[i] = buffer[i] << 1U; + } + + buffer[AES_BLOCK_SIZE - 1U] ^= xorMask; +} + +/* + * ======== AESCMAC_finalize ======== + */ +int_fast16_t AESCMAC_finalize(AESCMAC_Handle handle, AESCMAC_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCMACCC26XX_Object *object = handle->object; + int_fast16_t status = AESCMAC_STATUS_SUCCESS; + + /* Check for previous failure or cancellation of segmented operation */ + if (object->returnStatus != AESCMAC_STATUS_SUCCESS) + { + /* Return the failure status of previous call. + * The callback will not be called. + */ + return object->returnStatus; + } + + if (operation->inputLength == 0U) + { + /* Finalizing an operation without providing data to process is not + * supported. Return an error. + */ + status = AESCMAC_STATUS_ERROR; + } + else + { + /* Try and obtain access to the crypto module */ + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCMAC_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + if (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_SIGN) + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_SIGN; + } + else if (object->operationType == AESCMAC_OP_TYPE_SEGMENTED_VERIFY) + { + object->operationType = AESCMAC_OP_TYPE_FINALIZE_VERIFY; + } + else + { + status = AESCMAC_STATUS_ERROR; + } + + if (status == AESCMAC_STATUS_SUCCESS) + { + object->operation = operation; + status = AESCMAC_processData(handle); + } + + if ((status != AESCMAC_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + } + + return status; +} + +/* + * ======== AESCMAC_cancelOperation ======== + */ +int_fast16_t AESCMAC_cancelOperation(AESCMAC_Handle handle) +{ + AESCMACCC26XX_Object *object = handle->object; + uintptr_t interruptKey; + + interruptKey = HwiP_disable(); + + /* Check if the HW operation already completed */ + if (!object->hwBusy) + { + object->returnStatus = AESCMAC_STATUS_CANCELED; + object->operationInProgress = false; + + HwiP_restore(interruptKey); + + /* No need to call the callback function provided by the application + * since it would have already been called when the HW operation + * completed. + */ + + return AESCMAC_STATUS_SUCCESS; + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(interruptKey); + + /* Reset the DMA to stop transfers */ + AESDMAReset(); + + /* Issue SW reset to recover the AES engine */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued since disabling + * interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + object->returnStatus = AESCMAC_STATUS_CANCELED; + object->hwBusy = false; + object->operationInProgress = false; + + if (object->returnBehavior == AESCMAC_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else /* AESCMAC_RETURN_BEHAVIOR_CALLBACK */ + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESCMAC_STATUS_CANCELED, object->operation, object->operationType); + } + + /* Cleanup posts the crypto access semaphore and must be done after the + * operational semaphore is posted to avoid a potential race condition + * when starting a new operation using a different driver instance. + */ + AESCMAC_cleanup(object); + + /* Always return success */ + return AESCMAC_STATUS_SUCCESS; +} + +bool AESCMAC_acquireLock(AESCMAC_Handle handle, uint32_t timeout) +{ + return CryptoResourceCC26XX_acquireLock(timeout); +} + +void AESCMAC_releaseLock(AESCMAC_Handle handle) +{ + CryptoResourceCC26XX_releaseLock(); +} + +void AESCMAC_enableThreadSafety(AESCMAC_Handle handle) +{ + AESCMACCC26XX_Object *object = handle->object; + + object->threadSafe = true; +} + +void AESCMAC_disableThreadSafety(AESCMAC_Handle handle) +{ + AESCMACCC26XX_Object *object = handle->object; + + object->threadSafe = false; +} diff --git a/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.h b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.h new file mode 100644 index 00000000..01d56211 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aescmac/AESCMACCC26XX.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCMACCC26XX.h + * + * @brief AESCMAC driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the + * AESCMAC_config struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CBC-MAC. Only one + * operation can be carried out on the accelerator at a time. Mutual exclusion + * is implemented at the driver level and coordinated between all drivers + * relying on the accelerator. It is transparent to the application and only + * noted to ensure sensible access timeouts are set. + * + * # Key Store # + * The CC26XX' crypto module contains a key store. The only way to load a key + * into the AES accelerator is to first load it into the key store. To guarantee + * availability of open key locations in the key store for AES operations, the + * last two key locations (6 and 7) are reserved for ad-hoc operations. The key + * is loaded into the key store, the AES operation is carried out, and the key + * is deleted from the key store. Since the key store does not have retention + * and the keys can not survive going into standby, the key store is only used + * to load keys into the AES accelerator rather than store keys. Support for + * pre-loading keys into the key store and using them in an AES operation is not + * supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to them + * are checked (such as whether a driver is already open). Higher input + * parameter validation coverage is achieved by turning on assertions when + * compiling the driver. + */ + +#ifndef ti_drivers_aescmac_AESCMACCC26XX__include +#define ti_drivers_aescmac_AESCMACCC26XX__include + +#include +#include + +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESCMACCC26XX Hardware Attributes + * + * AESCMAC26XX hardware attributes should be included in the board file + * and pointed to by the AESCMAC_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26XX uses three of the priority bits, meaning ~0 has the same + effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; +} AESCMACCC26XX_HWAttrs; + +/*! + * @brief AESCMACCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t intermediateTag[AES_TAG_LENGTH_BYTES / 4]; + uint32_t buffer[AES_BLOCK_SIZE / 4]; + uint32_t semaphoreTimeout; + AESCMAC_CallbackFxn callbackFxn; + AESCMAC_Operation *operation; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESCMAC_ReturnBehavior returnBehavior; + AESCMAC_OperationType operationType; + AESCMAC_OperationalMode operationalMode; + bool isOpen; + bool threadSafe; + volatile bool cryptoResourceLocked; + volatile bool hwBusy; + volatile bool operationInProgress; +} AESCMACCC26XX_Object; + +/*! + * @cond NODOC + * @brief Internal functions which may be called by other drivers to handle + * thread safety directly. + */ +bool AESCMAC_acquireLock(AESCMAC_Handle handle, uint32_t timeout); +void AESCMAC_releaseLock(AESCMAC_Handle handle); +void AESCMAC_enableThreadSafety(AESCMAC_Handle handle); +void AESCMAC_disableThreadSafety(AESCMAC_Handle handle); +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aescmac_AESCMACCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.c new file mode 100644 index 00000000..8ae163f5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.c @@ -0,0 +1,567 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESCTR_s_SecureCallback aesctrSecureCB_ns[]; +extern AESCTRCC26X4_ns_Object aesctrObject_ns[]; + +/* + * ======== AESCTR_ns_callbackFxn ======== + */ +void AESCTR_ns_callbackFxn(uintptr_t arg) +{ + AESCTR_s_SecureCallback *secureCallbackObject = (AESCTR_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + aesctrObject_ns[index].callbackFxn(aesctrSecureCB_ns[index].handle, + aesctrSecureCB_ns[index].returnValue, + aesctrSecureCB_ns[index].operation, + aesctrSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESCTR_ns_registerCallback ======== + */ +static psa_status_t AESCTR_ns_registerCallback(AESCTR_Handle handle, const AESCTR_Params *params) +{ + AESCTR_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCallback object */ + SecureCallback_construct(&aesctrSecureCB_ns[index].object, + AESCTR_ns_callbackFxn, + (uintptr_t)&aesctrSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aesctrSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESCTR_init ======== + */ +void AESCTR_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESCTR_open ======== + */ +AESCTR_Handle AESCTR_open(uint_least8_t index, const AESCTR_Params *params) +{ + AESCTR_Handle handle = NULL; + AESCTR_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCTR_Params *)&AESCTR_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING)) + { + if (AESCTR_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesctrObject_ns[index].returnBehavior = params->returnBehavior; + aesctrObject_ns[index].callbackFxn = params->callbackFxn; + aesctrObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCTR_construct ======== + */ +AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *params) +{ + AESCTR_Handle handle = NULL; + AESCTR_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCTR_Params *)&AESCTR_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING)) + { + if (AESCTR_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesctrObject_ns[index].returnBehavior = params->returnBehavior; + aesctrObject_ns[index].callbackFxn = params->callbackFxn; + aesctrObject_ns[index].semaphoreTimeout = params->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESCTR_close ======== + */ +void AESCTR_close(AESCTR_Handle handle) +{ + AESCTR_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aesctrSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCTR_oneStepOperation ======== + */ +static int_fast16_t AESCTR_oneStepOperation(AESCTR_Handle handle, AESCTR_OneStepOperation *operation, int32_t type) +{ + AESCTR_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESCTR_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operation; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesctrObject_ns[index].semaphoreTimeout) == false) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTR_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) && (result != AESCTR_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesctrSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCTR_oneStepEncrypt ======== + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation) +{ + return AESCTR_oneStepOperation(handle, operation, AESCTR_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESCTR_oneStepDecrypt ======== + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operation) +{ + return AESCTR_oneStepOperation(handle, operation, AESCTR_S_MSG_TYPE_ONE_STEP_DECRYPT); +} + +/* + * ======== AESCTR_setupOperation ======== + */ +static int_fast16_t AESCTR_setupOperation(AESCTR_Handle handle, + const CryptoKey *key, + const uint8_t *initialCounter, + int32_t type) +{ + AESCTR_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESCTR_STATUS_ERROR; + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + setupMsg.initialCounter = initialCounter; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTR_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCTR_setupEncrypt ======== + */ +int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + return AESCTR_setupOperation(handle, key, initialCounter, AESCTR_S_MSG_TYPE_SETUP_ENCRYPT); +} + +/* + * ======== AESCTR_setupDecrypt ======== + */ +int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + return AESCTR_setupOperation(handle, key, initialCounter, AESCTR_S_MSG_TYPE_SETUP_DECRYPT); +} + +/* + * ======== AESCTR_addData ======== + */ +int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + AESCTR_s_AddDataMsg addDataMsg; + int_fast16_t result = AESCTR_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesctrObject_ns[index].semaphoreTimeout) == false) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTR_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) && (result != AESCTR_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesctrSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCTR_finalize ======== + */ +int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + AESCTR_s_FinalizeMsg finalizeMsg; + int_fast16_t result = AESCTR_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesctrObject_ns[index].semaphoreTimeout) == false) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTR_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_FINALIZE, invecs, outvecs); + + if ((aesctrObject_ns[index].returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) && (result != AESCTR_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesctrObject_ns[index].returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesctrSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESCTR_cancelOperation ======== + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) +{ + AESCTR_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESCTR_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTR_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTR_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.h new file mode 100644 index 00000000..e516951c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_ns.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCTRCC26X4_ns.h + * + * @brief AESCTR Nonsecure driver implementation for the CC26X4 family + */ + +#ifndef ti_drivers_aesctr_AESCTRCC26X4_ns__include +#define ti_drivers_aesctr_AESCTRCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESCTRCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESCTR_CallbackFxn callbackFxn; + AESCTR_ReturnBehavior returnBehavior; +} AESCTRCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctr_AESCTRCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.c new file mode 100644 index 00000000..8f1b5c63 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.c @@ -0,0 +1,974 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESCTRCC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESCTR_OperationUnion *operation_ns; /* Pointer to non-secure operation */ + AESCTR_OperationUnion operation_s; /* Secure copy of operation */ +} AESCTR_s_Operation; + +static AESCTR_s_Operation AESCTR_s_operation; + +/* + * AES CTR Secure Dynamic Instance struct. + */ +typedef struct +{ + AESCTR_Config config; + AESCTRCC26XX_Object object; + AESCTRCC26XX_HWAttrs hwAttrs; +} AESCTR_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESCTR_construct. + */ +static AESCTR_s_DynamicInstance AESCTR_s_dynInstance[CONFIG_AESCTR_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESCTR_s_SecureCallbacks for each driver instance opened or constructed */ +static AESCTR_s_SecureCallback *AESCTR_s_secureCB[AESCTR_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESCTR_Config AESCTR_config[]; + +/* + * ======== AESCTR_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t AESCTR_s_getCallbackIndex(AESCTR_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESCTR_COUNT; index++) + { + if (handle_s == (AESCTR_Handle)&AESCTR_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESCTR_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESCTR_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESCTR_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESCTR_s_hwiCallback ======== + */ +static void AESCTR_s_hwiCallback(AESCTR_Handle handle_s, + int_fast16_t returnValue, + AESCTR_OperationUnion *operation, + AESCTR_OperationType operationType) +{ + int8_t index; + AESCTR_s_SecureCallback *aesctrSecureCB_ns; + + index = AESCTR_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESCTR_SECURE_CALLBACK_COUNT)) + { + aesctrSecureCB_ns = AESCTR_s_secureCB[index]; + + if (aesctrSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aesctrSecureCB_ns->handle = (AESCTR_Handle)(CRYPTO_S_HANDLE_ID_AESCTR | index); + aesctrSecureCB_ns->returnValue = returnValue; + aesctrSecureCB_ns->operation = AESCTR_s_operation.operation_ns; + aesctrSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aesctrSecureCB_ns->object); + } + } +} + +/* + * ======== AESCTR_s_copyConfig ======== + */ +static inline psa_status_t AESCTR_s_copyConfig(AESCTR_Config **secureConfig, + const AESCTR_Config *config, + AESCTR_Handle *retHandle) +{ + AESCTR_Config *config_s; + AESCTR_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESCTR_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESCTR_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCTR_s_secureCB[i + CONFIG_TI_DRIVERS_AESCTR_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESCTR OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESCTR_Handle)(CRYPTO_S_HANDLE_ID_AESCTR | (i + CONFIG_TI_DRIVERS_AESCTR_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESCTR_s_releaseConfig ======== + */ +static inline void AESCTR_s_releaseConfig(AESCTR_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCTR) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESCTR_COUNT) && (i < AESCTR_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESCTR_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCTR_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESCTR_s_copyOneStepOperation ======== + */ +static inline psa_status_t AESCTR_s_copyOneStepOperation(AESCTR_OneStepOperation *secureOperation, + CryptoKey *secureKey, + const AESCTR_OneStepOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCTR_OneStepOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCTR_OneStepOperation)); + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the key struct and update the operation + * struct to point to the secure key copy. + */ + (void)spm_memcpy(secureKey, secureOperation->key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(secureKey) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + secureOperation->key = secureKey; + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Verify initial counter address range if the pointer is not NULL. + * If the pointer is NULL, zero will be used for the initial counter value. + */ + if ((secureOperation->initialCounter != NULL) && + (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->initialCounter, AES_BLOCK_SIZE) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_copySegmentedOperation ======== + */ +static psa_status_t AESCTR_s_copySegmentedOperation(AESCTR_SegmentedOperation *secureOperation, + const AESCTR_SegmentedOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESCTR_SegmentedOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESCTR_SegmentedOperation)); + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_copyParams ======== + */ +static psa_status_t AESCTR_s_copyParams(AESCTR_Params *secureParams, const AESCTR_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESCTR_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESCTR_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESCTR_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESCTR_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESCTR_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESCTR_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESCTR_Handle AESCTR_s_getHandle(AESCTR_Handle nsHandle) +{ + AESCTR_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCTR) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESCTR_COUNT) + { + secureHandle = (AESCTR_Handle)&AESCTR_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESCTR_COUNT) && (i < AESCTR_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESCTR_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCTR_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESCTR_s_registerCallback ======== + */ +static inline psa_status_t AESCTR_s_registerCallback(psa_msg_t *msg) +{ + AESCTR_Handle handle_s; + AESCTR_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESCTR_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESCTR_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESCTR_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESCTR_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESCTR_s_SecureCallback located in + * non-secure memory. + */ + AESCTR_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCTR_s_construct ======== + */ +static inline psa_status_t AESCTR_s_construct(psa_msg_t *msg) +{ + AESCTR_s_ConstructMsg constructMsg; + AESCTR_Handle handle; + AESCTR_Params params_s; + const AESCTR_Params *paramsPtr_s = NULL; + AESCTR_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESCTR_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESCTR_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESCTR_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESCTR_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_open ======== + */ +static inline psa_status_t AESCTR_s_open(psa_msg_t *msg) +{ + AESCTR_s_OpenMsg openMsg; + AESCTR_Handle handle; + AESCTR_Params params_s; + AESCTR_Params *paramsPtr_s = NULL; + AESCTR_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESCTR_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESCTR_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESCTR_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESCTR OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESCTR_Handle)(CRYPTO_S_HANDLE_ID_AESCTR | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_close ======== + */ +static inline psa_status_t AESCTR_s_close(psa_msg_t *msg) +{ + AESCTR_Handle handle_s; + AESCTR_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTR_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESCTR_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESCTR_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESCTR_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_oneStepOperation ======== + */ +static inline psa_status_t AESCTR_s_oneStepOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCTR_s_OneStepOperationMsg oneStepMsg; + AESCTR_Handle handle_s; + AESCTR_OneStepOperation *operation_s; + CryptoKey key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(oneStepMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &oneStepMsg, sizeof(oneStepMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTR_s_getHandle(oneStepMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCTR_s_operation.operation_s.oneStepOperation; + + /* Save pointer to non-secure operation struct */ + AESCTR_s_operation.operation_ns = (AESCTR_OperationUnion *)oneStepMsg.operation; + + /* Validate and copy operation */ + status = AESCTR_s_copyOneStepOperation(operation_s, &key_s, oneStepMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = oneStepMsg.handle; + operation_s = oneStepMsg.operation; + } + + if (msgType == AESCTR_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + ret = AESCTR_oneStepEncrypt(handle_s, operation_s); + } + else + { + ret = AESCTR_oneStepDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTR_s_setupOperation ======== + */ +static inline psa_status_t AESCTR_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESCTR_s_SetupOperationMsg setupMsg; + AESCTR_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTR_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Verify initial counter address range if the pointer is not NULL. + * If the pointer is NULL, zero will be used for the initial counter value. + */ + if ((setupMsg.initialCounter != NULL) && + (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.initialCounter, AES_BLOCK_SIZE) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESCTR_S_MSG_TYPE_SETUP_ENCRYPT) + { + ret = AESCTR_setupEncrypt(handle_s, keyPtr_s, setupMsg.initialCounter); + } + else + { + ret = AESCTR_setupDecrypt(handle_s, keyPtr_s, setupMsg.initialCounter); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_addData ======== + */ +static inline psa_status_t AESCTR_s_addData(psa_msg_t *msg) +{ + AESCTR_Handle handle_s; + AESCTR_SegmentedOperation *operation_s; + AESCTR_s_AddDataMsg addDataMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTR_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCTR_s_operation.operation_s.segmentedOperation; + + /* Save pointer to non-secure operation struct */ + AESCTR_s_operation.operation_ns = (AESCTR_OperationUnion *)addDataMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCTR_s_copySegmentedOperation(operation_s, addDataMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCTR_addData(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCTR_addData(addDataMsg.handle, addDataMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTR_s_finalizeOperation ======== + */ +static inline psa_status_t AESCTR_s_finalizeOperation(psa_msg_t *msg) +{ + AESCTR_s_FinalizeMsg finalizeMsg; + AESCTR_SegmentedOperation *operation_s; + AESCTR_Handle handle_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTR_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESCTR_s_operation.operation_s.segmentedOperation; + + /* Save pointer to non-secure operation struct */ + AESCTR_s_operation.operation_ns = (AESCTR_OperationUnion *)finalizeMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESCTR_s_copySegmentedOperation(operation_s, finalizeMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESCTR_finalize(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESCTR_finalize(finalizeMsg.handle, finalizeMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTR_s_cancelOperation ======== + */ +static inline psa_status_t AESCTR_s_cancelOperation(psa_msg_t *msg) +{ + AESCTR_Handle handle_s; + AESCTR_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESCTR_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESCTR_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTR_s_handlePsaMsg ======== + */ +psa_status_t AESCTR_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESCTR_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESCTR_S_MSG_TYPE_CONSTRUCT: + status = AESCTR_s_construct(msg); + break; + + case AESCTR_S_MSG_TYPE_OPEN: + status = AESCTR_s_open(msg); + break; + + /* + * AESCTR_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESCTR_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESCTR_s_registerCallback(msg); + break; + + case AESCTR_S_MSG_TYPE_CLOSE: + status = AESCTR_s_close(msg); + break; + + case AESCTR_S_MSG_TYPE_ONE_STEP_ENCRYPT: /* Fall through */ + case AESCTR_S_MSG_TYPE_ONE_STEP_DECRYPT: + status = AESCTR_s_oneStepOperation(msg, msg->type); + break; + + case AESCTR_S_MSG_TYPE_SETUP_ENCRYPT: /* Fall through */ + case AESCTR_S_MSG_TYPE_SETUP_DECRYPT: + status = AESCTR_s_setupOperation(msg, msg->type); + break; + + case AESCTR_S_MSG_TYPE_ADD_DATA: + status = AESCTR_s_addData(msg); + break; + + case AESCTR_S_MSG_TYPE_FINALIZE: + status = AESCTR_s_finalizeOperation(msg); + break; + + /* + * AESCTR_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESCTR_S_MSG_TYPE_CANCEL_OPERATION: + status = AESCTR_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESCTR_s_init ======== + */ +void AESCTR_s_init(void) +{ + AESCTR_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.h new file mode 100644 index 00000000..b4eafe87 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26X4_s.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aesctr_AESCTRCC26X4_s__include +#define ti_drivers_aesctr_AESCTRCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES CTR secure message types + */ +#define AESCTR_S_MSG_TYPE_CONSTRUCT AESCTR_S_MSG_TYPE(0U) +#define AESCTR_S_MSG_TYPE_OPEN AESCTR_S_MSG_TYPE(1U) +#define AESCTR_S_MSG_TYPE_REGISTER_CALLBACK AESCTR_S_MSG_TYPE(2U) +#define AESCTR_S_MSG_TYPE_CLOSE AESCTR_S_MSG_TYPE(3U) +#define AESCTR_S_MSG_TYPE_ONE_STEP_ENCRYPT AESCTR_S_MSG_TYPE(4U) +#define AESCTR_S_MSG_TYPE_ONE_STEP_DECRYPT AESCTR_S_MSG_TYPE(5U) +#define AESCTR_S_MSG_TYPE_SETUP_ENCRYPT AESCTR_S_MSG_TYPE(6U) +#define AESCTR_S_MSG_TYPE_SETUP_DECRYPT AESCTR_S_MSG_TYPE(7U) +#define AESCTR_S_MSG_TYPE_ADD_DATA AESCTR_S_MSG_TYPE(8U) +#define AESCTR_S_MSG_TYPE_FINALIZE AESCTR_S_MSG_TYPE(9U) +#define AESCTR_S_MSG_TYPE_CANCEL_OPERATION AESCTR_S_MSG_TYPE(10U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESCTR_construct(). + */ +#ifndef CONFIG_AESCTR_S_CONFIG_POOL_SIZE + #define CONFIG_AESCTR_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESCTR_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESCTR_COUNT + CONFIG_AESCTR_S_CONFIG_POOL_SIZE) + +/* + * ========= AES CTR Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES CTR callback fxn parameters */ + AESCTR_Handle handle; + int_fast16_t returnValue; + AESCTR_OperationUnion *operation; + AESCTR_OperationType operationType; +} AESCTR_s_SecureCallback; + +/* + * ========= AES CTR Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES CTR secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESCTR_Config *config; + const AESCTR_Params *params; +} AESCTR_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESCTR_Params *params; +} AESCTR_s_OpenMsg; + +typedef struct +{ + AESCTR_Handle handle; + AESCTR_s_SecureCallback *callback; +} AESCTR_s_CallbackMsg; + +typedef struct +{ + AESCTR_Handle handle; +} AESCTR_s_CloseMsg; + +typedef struct +{ + AESCTR_Handle handle; + AESCTR_OneStepOperation *operation; +} AESCTR_s_OneStepOperationMsg; + +typedef struct +{ + AESCTR_Handle handle; + const CryptoKey *key; + const uint8_t *initialCounter; +} AESCTR_s_SetupOperationMsg; + +typedef struct +{ + AESCTR_Handle handle; + AESCTR_SegmentedOperation *operation; +} AESCTR_s_AddDataMsg; + +typedef AESCTR_s_AddDataMsg AESCTR_s_FinalizeMsg; + +typedef struct +{ + AESCTR_Handle handle; +} AESCTR_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for AES CTR secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESCTR_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES CTR secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESCTR_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctr_AESCTRCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.c b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.c new file mode 100644 index 00000000..255ed3a1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.c @@ -0,0 +1,928 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0F + +/* Forward declarations */ +static void AESCTR_hwiFxn(uintptr_t arg0); +static int_fast16_t AESCTR_startOneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType); +static inline int_fast16_t AESCTR_waitForResult(AESCTRCC26XX_Object *object); +static void AESCTR_cleanup(AESCTRCC26XX_Object *object); +static void AESCTR_initCounter(AESCTRCC26XX_Object *object, const uint8_t *initialCounter); +static int_fast16_t AESCTR_setOperationInProgress(AESCTRCC26XX_Object *object); + +/* Static globals */ +static bool AESCTR_isInitialized = false; + +/* + * ======== AESCTR_hwiFxn ======== + */ +static void AESCTR_hwiFxn(uintptr_t arg0) +{ + AESCTRCC26XX_Object *object = ((AESCTR_Handle)arg0)->object; + uintptr_t interruptKey = HwiP_disable(); + + /* Mark that we are done with the operation so that + * AESCTR_cancelOperation knows not to try canceling. + */ + object->hwBusy = false; + + /* Check for one-step or final operation */ + if (!(object->operationType & AESCTR_OP_FLAG_SEGMENTED)) + { + /* Operation is complete */ + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + /* Propagate the DMA error from driverlib to the application */ + object->returnStatus = AESCTR_STATUS_ERROR; + } + else /* Must be RESULT_AVAIL because DMA_IN_DONE was disabled */ + { + if (AESGetCtrl() & CRYPTO_AESCTL_SAVE_CONTEXT_M) + { + /* Save counter value if the context was saved */ + AESReadNonAuthenticationModeIV(object->counter); + } + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + * + * When the access semaphore is freed during cleanup, + * if a higher priority ISR shares this driver instance and wishes + * to start a new operation, it must handle synchronization with + * the other thread(s) sharing this driver instance to avoid + * corrupting the driver's object data by starting a new operation + * before the callback is executed for the current operation. + */ + AESCTR_cleanup(object); + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else /* AESCTR_RETURN_BEHAVIOR_CALLBACK */ + { + /* Call the callback function provided by the application */ + object->callbackFxn((AESCTR_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESCTR_cleanup ======== + */ +static void AESCTR_cleanup(AESCTRCC26XX_Object *object) +{ + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + if (object->returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + if (object->cryptoResourceLocked) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } +} + +/* + * ======== AESCTR_init ======== + */ +void AESCTR_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + AESCTR_isInitialized = true; +} + +/* + * ======== AESCTR_construct ======== + */ +AESCTR_Handle AESCTR_construct(AESCTR_Config *config, const AESCTR_Params *params) +{ + DebugP_assert(config); + DebugP_assert(params); + + AESCTR_Handle handle = config; + AESCTRCC26XX_Object *object = handle->object; + + DebugP_assert(object); + + uintptr_t interruptKey = HwiP_disable(); + + if (!AESCTR_isInitialized || object->isOpen) + { + HwiP_restore(interruptKey); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(interruptKey); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESCTR_Params *)&AESCTR_defaultParams; + } + + DebugP_assert((params->returnBehavior != AESCTR_RETURN_BEHAVIOR_CALLBACK) || (params->callbackFxn != NULL)); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + if (params->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + object->semaphoreTimeout = params->timeout; + } + else + { + object->semaphoreTimeout = SemaphoreP_NO_WAIT; + } + object->threadSafe = true; + object->cryptoResourceLocked = false; + object->hwBusy = false; + object->operationInProgress = false; + + /* Set power dependency - i.e. power up and enable clock for Crypto + * (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESCTR_close ======== + */ +void AESCTR_close(AESCTR_Handle handle) +{ + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + AESCTRCC26XX_Object *object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== AESCTR_getKeyStoreKeyUsage ======== + */ +static KeyStore_PSA_KeyUsage AESCTR_getKeyStoreKeyUsage(AESCTR_OperationType operationType) +{ + switch (operationType) + { + case AESCTR_OPERATION_TYPE_ENCRYPT: + case AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED: + case AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE: + return KEYSTORE_PSA_KEY_USAGE_ENCRYPT; + + case AESCTR_OPERATION_TYPE_DECRYPT: + case AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED: + case AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE: + return KEYSTORE_PSA_KEY_USAGE_DECRYPT; + + default: + return 0; + } +} +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +/* + * ======== AESCTR_processData ======== + */ +static int_fast16_t AESCTR_processData(AESCTR_Handle handle) +{ + AESCTRCC26XX_Object *object = handle->object; + int_fast16_t status = AESCTR_STATUS_SUCCESS; + AESCTRCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + size_t keyLength; + uint8_t *keyingMaterial = NULL; + uint32_t ctrlVal; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + DebugP_assert(object->input); + DebugP_assert(object->output); + + /* Only plaintext and KeyStore CryptoKeys are supported currently */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || + (object->key.encoding == CryptoKey_BLANK_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT || object->key.encoding == CryptoKey_BLANK_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESCTR_getKeyStoreKeyUsage(object->operationType); + + if (!keyUsage) + { + return AESCTR_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_CTR, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESCTR_STATUS_KEYSTORE_INVALID_ID; + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESCTR_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESCTR_STATUS_FEATURE_NOT_SUPPORTED; + } + + DebugP_assert(keyingMaterial); + DebugP_assert((keyLength == 16) || (keyLength == 24) || (keyLength == 32)); + + /* We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback with + * the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESCTR_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and + * reserved location. + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + status = AESCTR_STATUS_ERROR; + } + + if (status == AESCTR_STATUS_SUCCESS) + { + /* AESWriteKeyStore() enables the CRYPTO IRQ. Disable it if polling mode */ + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) + { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* AESWriteToKeyStore() enables both DMA_IN_DONE and RESULT_AVAIL + * interrupts but since this driver only utilizes RESULT_AVAIL, + * disable the DMA_IN_DONE interrupt to simplify handling. + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the + * AES sub-module known as AES_KEY1. + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use without + * reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides + * small power savings. + */ + AESSelectAlgorithm(0x0); + + status = AESCTR_STATUS_ERROR; + } + } + + if (status == AESCTR_STATUS_SUCCESS) + { + /* Load counter value */ + AESSetInitializationVector(object->counter); + + ctrlVal = CRYPTO_AESCTL_CTR | CRYPTO_AESCTL_CTR_WIDTH_128_BIT; + + if ((object->operationType & AESCTR_OP_MODE_MASK) == AESCTR_MODE_ENCRYPT) + { + ctrlVal |= CRYPTO_AESCTL_DIR; + } + + /* Context save is only necessary in the middle of segmented + * operation. + */ + if (object->operationType & AESCTR_OP_FLAG_SEGMENTED) + { + ctrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; + } + + AESSetCtrl(ctrlVal); + AESSetDataLength(object->inputLength); + AESSetAuthLength(0); + + object->hwBusy = true; + + if (object->returnBehavior != AESCTR_RETURN_BEHAVIOR_POLLING) + { + /* Prevent system from entering standby and powering down Crypto + * peripheral while the operation is running. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* Start the input/output DMA */ + AESStartDMAOperation(object->input, object->inputLength, object->output, object->inputLength); + + status = AESCTR_waitForResult(object); + } + + if (status != AESCTR_STATUS_SUCCESS) + { + /* Save the failure status in case the application ignores the return value + * so the driver can reject any attempts to continue the failed operation. + */ + object->returnStatus = status; + } + + return status; +} + +/* + * ======== AESCTR_setOperationInProgress ======== + */ +static int_fast16_t AESCTR_setOperationInProgress(AESCTRCC26XX_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + return AESCTR_STATUS_ERROR; + } + object->operationInProgress = true; + HwiP_restore(interruptKey); + return AESCTR_STATUS_SUCCESS; +} + +/* + * ======== AESCTR_initCounter ======== + */ +static void AESCTR_initCounter(AESCTRCC26XX_Object *object, const uint8_t *initialCounter) +{ + if (initialCounter != NULL) + { + memcpy(object->counter, initialCounter, sizeof(object->counter)); + } + else + { + memset(object->counter, 0, sizeof(object->counter)); + } +} + +/* + * ======== AESCTR_startOneStepOperation ======== + */ +static int_fast16_t AESCTR_startOneStepOperation(AESCTR_Handle handle, + AESCTR_OneStepOperation *operation, + AESCTR_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + DebugP_assert(operation->key); + /* No need to assert operationType since we control it within the driver */ + + AESCTRCC26XX_Object *object = handle->object; + int_fast16_t status; + + /* Verify input length is non-zero */ + if (operation->inputLength == 0) + { + return AESCTR_STATUS_ERROR; + } + + /* Check that there is no operation already in progress for this driver + * instance. + */ + status = AESCTR_setOperationInProgress(object); + + if (status != AESCTR_STATUS_SUCCESS) + { + return status; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + object->operationInProgress = false; + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operation = (AESCTR_OperationUnion *)operation; + object->operationType = operationType; + /* We will only change the returnStatus if there is an error or cancellation */ + object->returnStatus = AESCTR_STATUS_SUCCESS; + + /* Make internal copy of operational params */ + object->key = *(operation->key); + object->input = operation->input; + object->inputLength = operation->inputLength; + object->output = operation->output; + + AESCTR_initCounter(object, operation->initialCounter); + + status = AESCTR_processData(handle); + + if ((status != AESCTR_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + return status; +} + +/* + * ======== AESCTR_waitForResult ======== + */ +static inline int_fast16_t AESCTR_waitForResult(AESCTRCC26XX_Object *object) +{ + int_fast16_t status = AESCTR_STATUS_ERROR; + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESCTR_STATUS_ERROR; + } + else /* Must be RESULT_AVAIL because DMA_IN_DONE was disabled */ + { + if (AESGetCtrl() & CRYPTO_AESCTL_SAVE_CONTEXT_M) + { + /* Save counter value if the context was saved */ + AESReadNonAuthenticationModeIV(object->counter); + } + } + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + /* Save the object's returnStatus before clearing operationInProgress or + * posting the access semaphore in case it is overwritten. + */ + status = object->returnStatus; + + if (!(object->operationType & AESCTR_OP_FLAG_SEGMENTED)) + { + /* One-step or finalization operation is complete */ + object->operationInProgress = false; + } + + AESCTR_cleanup(object); + } + else if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + status = object->returnStatus; + } + else /* AESCTR_RETURN_BEHAVIOR_CALLBACK */ + { + /* AESCTR_STATUS_SUCCESS is always returned in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== AESCTR_oneStepEncrypt ======== + */ +int_fast16_t AESCTR_oneStepEncrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) +{ + return AESCTR_startOneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESCTR_oneStepDecrypt ======== + */ +int_fast16_t AESCTR_oneStepDecrypt(AESCTR_Handle handle, AESCTR_OneStepOperation *operationStruct) +{ + return AESCTR_startOneStepOperation(handle, operationStruct, AESCTR_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESCTR_setupSegmentedOperation ======== + */ +static int_fast16_t AESCTR_setupSegmentedOperation(AESCTRCC26XX_Object *object, + const CryptoKey *key, + const uint8_t *initialCounter) +{ + DebugP_assert(key); + + /* Key material pointer and length are not checked until adding or + * finalizing data. + */ + + /* Check that there is no operation already in progress for this driver + * instance. + */ + int_fast16_t status = AESCTR_setOperationInProgress(object); + + if (status == AESCTR_STATUS_SUCCESS) + { + /* We will only change the returnStatus if there is an error or cancellation */ + object->returnStatus = AESCTR_STATUS_SUCCESS; + + /* Make internal copy of crypto key */ + object->key = *key; + + AESCTR_initCounter(object, initialCounter); + } + + return status; +} + +/* + * ======== AESCTR_setupEncrypt ======== + */ +int_fast16_t AESCTR_setupEncrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + DebugP_assert(handle); + AESCTRCC26XX_Object *object = handle->object; + DebugP_assert(object); + + int_fast16_t status = AESCTR_setupSegmentedOperation(object, key, initialCounter); + + if (status == AESCTR_STATUS_SUCCESS) + { + object->operationType = AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED; + } + + return status; +} + +/* + * ======== AESCTR_setupDecrypt ======== + */ +int_fast16_t AESCTR_setupDecrypt(AESCTR_Handle handle, const CryptoKey *key, const uint8_t *initialCounter) +{ + DebugP_assert(handle); + AESCTRCC26XX_Object *object = handle->object; + DebugP_assert(object); + + int_fast16_t status = AESCTR_setupSegmentedOperation(object, key, initialCounter); + + if (status == AESCTR_STATUS_SUCCESS) + { + object->operationType = AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED; + } + + return status; +} + +/* + * ======== AESCTR_addData ======== + */ +int_fast16_t AESCTR_addData(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRCC26XX_Object *object = handle->object; + int_fast16_t status; + + /* Check for previous failure or cancellation of segmented operation */ + if (object->returnStatus != AESCTR_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->returnStatus; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || (operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK)) + { + return AESCTR_STATUS_ERROR; + } + + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operation = (AESCTR_OperationUnion *)operation; + + /* Make internal copy of operational params */ + object->input = operation->input; + object->inputLength = operation->inputLength; + object->output = operation->output; + + status = AESCTR_processData(handle); + + if ((status != AESCTR_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + + return status; +} + +/* + * ======== AESCTR_finalize ======== + */ +int_fast16_t AESCTR_finalize(AESCTR_Handle handle, AESCTR_SegmentedOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESCTRCC26XX_Object *object = handle->object; + AESCTR_OperationType operationType = object->operationType; + int_fast16_t status = AESCTR_STATUS_ERROR; + + /* Check for previous failure of segmented operation */ + if (object->returnStatus != AESCTR_STATUS_SUCCESS) + { + /* Return the failure status of previous call. + * The callback will not be called. + */ + return object->returnStatus; + } + + /* Assert the segmented operation was setup */ + DebugP_assert((object->operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) || + (object->operationType == AESCTR_OPERATION_TYPE_DECRYPT_SEGMENTED)); + + /* Determine final operation type but do not save to object until + * we have obtained access to CRYPTO resource or there is no input + * to process. This allows app to retry finalization if the CRYPTO + * resource is unavailable. + */ + if (operationType == AESCTR_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + operationType = AESCTR_OPERATION_TYPE_ENCRYPT_FINALIZE; + } + else + { + operationType = AESCTR_OPERATION_TYPE_DECRYPT_FINALIZE; + } + + if (operation->inputLength > 0) + { + /* Try and obtain access to the crypto module */ + if (object->threadSafe) + { + if (!CryptoResourceCC26XX_acquireLock(object->semaphoreTimeout)) + { + return AESCTR_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESCTR_OperationUnion *)operation; + + /* Make internal copy of operational params */ + object->input = operation->input; + object->inputLength = operation->inputLength; + object->output = operation->output; + + status = AESCTR_processData(handle); + + if ((status != AESCTR_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + CryptoResourceCC26XX_releaseLock(); + object->cryptoResourceLocked = false; + } + } + else /* Operation was finalized without additional data to process */ + { + /* Save the object's returnStatus in case it is + * overwritten during setup of a new segmented operation + * after the operationInProgress flag is cleared. + */ + status = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, status, (AESCTR_OperationUnion *)operation, operationType); + + /* Always return success in callback mode */ + status = AESCTR_STATUS_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESCTR_cancelOperation ======== + */ +int_fast16_t AESCTR_cancelOperation(AESCTR_Handle handle) +{ + AESCTRCC26XX_Object *object = handle->object; + uintptr_t interruptKey; + + interruptKey = HwiP_disable(); + + /* Check if the HW operation already completed or was never started */ + if (!object->hwBusy) + { + object->returnStatus = AESCTR_STATUS_CANCELED; + object->operationInProgress = false; + + HwiP_restore(interruptKey); + + /* No need to call the callback function provided by the application + * since it would have already been called when the HW operation + * completed. + */ + + return AESCTR_STATUS_SUCCESS; + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(interruptKey); + + /* Reset the DMA to stop transfers */ + AESDMAReset(); + + /* Issue SW reset to recover the AES engine */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued since disabling + * interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + object->returnStatus = AESCTR_STATUS_CANCELED; + object->hwBusy = false; + object->operationInProgress = false; + + if (object->returnBehavior == AESCTR_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else /* AESCTR_RETURN_BEHAVIOR_CALLBACK */ + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, AESCTR_STATUS_CANCELED, object->operation, object->operationType); + } + + /* Cleanup posts the crypto access semaphore and must be done after the + * operational semaphore is posted to avoid a potential race condition + * when starting a new operation using a different driver instance. + */ + AESCTR_cleanup(object); + + /* Always return success */ + return AESCTR_STATUS_SUCCESS; +} + +bool AESCTR_acquireLock(AESCTR_Handle handle, uint32_t timeout) +{ + return CryptoResourceCC26XX_acquireLock(timeout); +} + +void AESCTR_releaseLock(AESCTR_Handle handle) +{ + CryptoResourceCC26XX_releaseLock(); +} + +void AESCTR_enableThreadSafety(AESCTR_Handle handle) +{ + AESCTRCC26XX_Object *object = handle->object; + + object->threadSafe = true; +} + +void AESCTR_disableThreadSafety(AESCTR_Handle handle) +{ + AESCTRCC26XX_Object *object = handle->object; + + object->threadSafe = false; +} diff --git a/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.h b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.h new file mode 100644 index 00000000..8eb0734e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctr/AESCTRCC26XX.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2018-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESCTRCC26XX.h + * + * @brief AESCTR driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the AESCTR_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including CTR. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesctr_AESCTRCC26XX__include +#define ti_drivers_aesctr_AESCTRCC26XX__include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESCTRCC26XX Hardware Attributes + * + * AESCTR26XX hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESCTRCC26XX_HWAttrs; + +/*! + * @brief AESCTRCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t counter[AES_BLOCK_SIZE / 4]; + uint32_t semaphoreTimeout; + AESCTR_CallbackFxn callbackFxn; + AESCTR_OperationUnion *operation; + const uint8_t *input; + uint8_t *output; + size_t inputLength; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESCTR_ReturnBehavior returnBehavior; + AESCTR_OperationType operationType; + bool isOpen; + bool threadSafe; + volatile bool cryptoResourceLocked; + volatile bool hwBusy; + volatile bool operationInProgress; +} AESCTRCC26XX_Object; + +/*! + * @cond NODOC + * @brief Internal functions which may be called by other drivers to handle + * thread safety directly. + */ +bool AESCTR_acquireLock(AESCTR_Handle handle, uint32_t timeout); +void AESCTR_releaseLock(AESCTR_Handle handle); +void AESCTR_enableThreadSafety(AESCTR_Handle handle); +void AESCTR_disableThreadSafety(AESCTR_Handle handle); +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctr_AESCTRCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.c b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.c new file mode 100644 index 00000000..45a5bd15 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.c @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* + * ======== AESCTRDRBG_init ======== + */ +void AESCTRDRBG_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESCTRDRBG_open ======== + */ +AESCTRDRBG_Handle AESCTRDRBG_open(uint_least8_t index, const AESCTRDRBG_Params *params) +{ + AESCTRDRBG_Handle handle = NULL; + AESCTRDRBG_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCTRDRBG_Params *)&AESCTRDRBG_defaultParams; + } + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * Set power dependency before opening driver since the DRBG reseed will + * take place immediately. + */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_OPEN, invecs, outvecs); + + return handle; +} + +/* + * ======== AESCTRDRBG_construct ======== + */ +AESCTRDRBG_Handle AESCTRDRBG_construct(AESCTRDRBG_Config *config, const AESCTRDRBG_Params *params) +{ + AESCTRDRBG_Handle handle = NULL; + AESCTRDRBG_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESCTRDRBG_Params *)&AESCTRDRBG_defaultParams; + } + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * Set power dependency before constructing driver instance since the DRBG + * reseed will take place immediately. + */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + return handle; +} + +/* + * ======== AESCTRDRBG_close ======== + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle) +{ + AESCTRDRBG_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESCTRDRBG_getBytes ======== + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes) +{ + return AESCTRDRBG_generateKey(handle, randomBytes); +} + +/* + * ======== AESCTRDRBG_generateKey ======== + */ +int_fast16_t AESCTRDRBG_generateKey(AESCTRDRBG_Handle handle, CryptoKey *randomKey) +{ + AESCTRDRBG_s_GenerateKeyMsg generateMsg; + int_fast16_t result = AESCTRDRBG_STATUS_ERROR; + + /* Setup interface for input parameters */ + generateMsg.handle = handle; + generateMsg.randomKey = randomKey; + invecs[0].base = &generateMsg; + invecs[0].len = sizeof(generateMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTRDRBG_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_GENERATE_KEY, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCTRDRBG_getRandomBytes ======== + */ +int_fast16_t AESCTRDRBG_getRandomBytes(AESCTRDRBG_Handle handle, void *randomBytes, size_t randomBytesSize) +{ + AESCTRDRBG_s_GetRandomBytesMsg getRandomMsg; + int_fast16_t result = AESCTRDRBG_STATUS_ERROR; + + /* Setup interface for input parameters */ + getRandomMsg.handle = handle; + getRandomMsg.randomBytes = randomBytes; + getRandomMsg.randomBytesSize = randomBytesSize; + invecs[0].base = &getRandomMsg; + invecs[0].len = sizeof(getRandomMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTRDRBG_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_GET_RANDOM_BYTES, invecs, outvecs); + + return (result); +} + +/* + * ======== AESCTRDRBG_reseed ======== + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength) +{ + AESCTRDRBG_s_ReseedMsg reseedMsg; + int_fast16_t result = AESCTRDRBG_STATUS_ERROR; + + /* Setup interface for input parameters */ + reseedMsg.handle = handle; + reseedMsg.seed = seed; + reseedMsg.additionalData = additionalData; + reseedMsg.additionalDataLength = additionalDataLength; + invecs[0].base = &reseedMsg; + invecs[0].len = sizeof(reseedMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESCTRDRBG_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESCTRDRBG_S_MSG_TYPE_RESEED, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.h b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.h new file mode 100644 index 00000000..0a09aea6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_ns.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBGX4_ns.h + * + * @brief AESCTRDRBG CC26X4 Nonsecure implementation based on the AESCTR driver + */ + +#ifndef ti_drivers_aesctrdrbg_AESCTRDRBGX4_ns__include +#define ti_drivers_aesctrdrbg_AESCTRDRBGX4_ns__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctrdrbg_AESCTRDRBGX4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.c b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.c new file mode 100644 index 00000000..db03ada9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.c @@ -0,0 +1,594 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESCTRDRBGX4_s.h" + +#include +#include +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * AES CTR DRBG Secure Dynamic Instance struct. + */ +typedef struct +{ + AESCTRDRBG_Config config; + AESCTRDRBGXX_Object object; + AESCTRDRBGXX_HWAttrs hwAttrs; +} AESCTRDRBG_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESCTRDRBG_construct. + */ +static AESCTRDRBG_s_DynamicInstance AESCTRDRBG_s_dynInstance[CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE]; + +/* Static driver instances allocated by SysConfig */ +extern const AESCTRDRBG_Config AESCTRDRBG_config[]; + +/* + * ======== AESCTRDRBG_s_copyConfig ======== + */ +static inline psa_status_t AESCTRDRBG_s_copyConfig(AESCTRDRBG_Config **secureConfig, + const AESCTRDRBG_Config *config, + AESCTRDRBG_Handle *retHandle) +{ + AESCTRDRBG_Config *config_s; + AESCTRDRBG_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESCTRDRBG_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESCTRDRBG OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESCTRDRBG_Handle)(CRYPTO_S_HANDLE_ID_AESCTRDRBG | (i + CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESCTRDRBG_s_releaseConfig ======== + */ +static inline void AESCTRDRBG_s_releaseConfig(AESCTRDRBG_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCTRDRBG) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT) && + (i < (CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT + CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE))) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESCTRDRBG_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESCTRDRBG_s_copyParams ======== + */ +static psa_status_t AESCTRDRBG_s_copyParams(AESCTRDRBG_Params *secureParams, const AESCTRDRBG_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESCTRDRBG_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESCTRDRBG_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESCTRDRBG_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESCTRDRBG_RETURN_BEHAVIOR_POLLING)) + { + /* Force to polling return behavior */ + secureParams->returnBehavior = AESCTRDRBG_RETURN_BEHAVIOR_POLLING; + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESCTRDRBG_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESCTRDRBG_Handle AESCTRDRBG_s_getHandle(AESCTRDRBG_Handle nsHandle) +{ + AESCTRDRBG_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESCTRDRBG) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT) + { + secureHandle = (AESCTRDRBG_Handle)&AESCTRDRBG_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT) && + (i < (CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT + CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE))) + { + secureHandle = &AESCTRDRBG_s_dynInstance[i - CONFIG_TI_DRIVERS_AESCTRDRBG_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESCTRDRBG_s_construct ======== + */ +static inline psa_status_t AESCTRDRBG_s_construct(psa_msg_t *msg) +{ + AESCTRDRBG_s_ConstructMsg constructMsg; + AESCTRDRBG_Handle handle; + AESCTRDRBG_Params params_s; + const AESCTRDRBG_Params *paramsPtr_s = NULL; + AESCTRDRBG_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESCTRDRBG_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESCTRDRBG_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESCTRDRBG_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESCTRDRBG_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTRDRBG_s_open ======== + */ +static inline psa_status_t AESCTRDRBG_s_open(psa_msg_t *msg) +{ + AESCTRDRBG_s_OpenMsg openMsg; + AESCTRDRBG_Handle handle; + AESCTRDRBG_Params params_s; + AESCTRDRBG_Params *paramsPtr_s = NULL; + AESCTRDRBG_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESCTRDRBG_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESCTRDRBG_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return CRYPTO_S_HANDLE_ID_AESCTRDRBG OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESCTRDRBG_Handle)(CRYPTO_S_HANDLE_ID_AESCTRDRBG | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESCTRDRBG_s_close ======== + */ +static inline psa_status_t AESCTRDRBG_s_close(psa_msg_t *msg) +{ + AESCTRDRBG_Handle handle_s; + AESCTRDRBG_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTRDRBG_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESCTRDRBG_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESCTRDRBG_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESCTRDRBG_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESCTRDRBG_s_reseed ======== + */ +static inline psa_status_t AESCTRDRBG_s_reseed(psa_msg_t *msg) +{ + AESCTRDRBG_s_ReseedMsg reseedMsg; + AESCTRDRBG_Handle handle_s; + AESCTRDRBGXX_Object *object; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(reseedMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &reseedMsg, sizeof(reseedMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTRDRBG_s_getHandle(reseedMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + + /* Validate seed address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)reseedMsg.seed, object->seedLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate additional data address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)reseedMsg.additionalData, reseedMsg.additionalDataLength) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = reseedMsg.handle; + } + + ret = AESCTRDRBG_reseed(handle_s, reseedMsg.seed, reseedMsg.additionalData, reseedMsg.additionalDataLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTRDRBG_s_getRandomBytes ======== + */ +static inline psa_status_t AESCTRDRBG_s_getRandomBytes(psa_msg_t *msg) +{ + AESCTRDRBG_s_GetRandomBytesMsg getBytesMsg; + AESCTRDRBG_Handle handle_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(getBytesMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getBytesMsg, sizeof(getBytesMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTRDRBG_s_getHandle(getBytesMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate output address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)getBytesMsg.randomBytes, getBytesMsg.randomBytesSize) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = getBytesMsg.handle; + } + + ret = AESCTRDRBG_getRandomBytes(handle_s, getBytesMsg.randomBytes, getBytesMsg.randomBytesSize); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTRDRBG_s_generateKey ======== + */ +static inline psa_status_t AESCTRDRBG_s_generateKey(psa_msg_t *msg) +{ + AESCTRDRBG_s_GenerateKeyMsg genKeyMsg; + CryptoKey randomKey_s; + AESCTRDRBG_Handle handle_s; + int_fast16_t ret = AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genKeyMsg, sizeof(genKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESCTRDRBG_s_getHandle(genKeyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy randomKey to secure memory */ + (void)spm_memcpy(&randomKey_s, genKeyMsg.randomKey, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureOutputKey(&randomKey_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESCTRDRBG_generateKey(handle_s, &randomKey_s); + + /* Copy the updated encoding to the non-secure key struct */ + genKeyMsg.randomKey->encoding = randomKey_s.encoding; + + if (randomKey_s.encoding == CryptoKey_KEYSTORE) + { + /* Copy the updated keyID to the non-secure key struct for KeyStore keys */ + genKeyMsg.randomKey->u.keyStore.keyID = randomKey_s.u.keyStore.keyID; + } + } + else /* Secure client */ + { + ret = AESCTRDRBG_generateKey(genKeyMsg.handle, genKeyMsg.randomKey); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESCTRDRBG_s_handlePsaMsg ======== + */ +psa_status_t AESCTRDRBG_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESCTRDRBG_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESCTRDRBG_S_MSG_TYPE_CONSTRUCT: + status = AESCTRDRBG_s_construct(msg); + break; + + case AESCTRDRBG_S_MSG_TYPE_OPEN: + status = AESCTRDRBG_s_open(msg); + break; + + case AESCTRDRBG_S_MSG_TYPE_CLOSE: + status = AESCTRDRBG_s_close(msg); + break; + + case AESCTRDRBG_S_MSG_TYPE_RESEED: + status = AESCTRDRBG_s_reseed(msg); + break; + + case AESCTRDRBG_S_MSG_TYPE_GET_RANDOM_BYTES: + status = AESCTRDRBG_s_getRandomBytes(msg); + break; + + case AESCTRDRBG_S_MSG_TYPE_GENERATE_KEY: + status = AESCTRDRBG_s_generateKey(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESCTRDRBG_s_init ======== + */ +void AESCTRDRBG_s_init(void) +{ + AESCTRDRBG_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.h b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.h new file mode 100644 index 00000000..2dd93e55 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGX4_s.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aesctrdrbg_AESCTRDRBGX4_s__include +#define ti_drivers_aesctrdrbg_AESCTRDRBGX4_s__include + +#include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES CTR DRBG secure message types + * + * The underlying AES CTR DRBG driver does not support callback return behavior, + * therefore this secure service can only support polling mode. If the non-secure + * client specifies blocking mode, polling mode will be automatically substituted. + */ +#define AESCTRDRBG_S_MSG_TYPE_CONSTRUCT AESCTRDRBG_S_MSG_TYPE(0U) +#define AESCTRDRBG_S_MSG_TYPE_OPEN AESCTRDRBG_S_MSG_TYPE(1U) +#define AESCTRDRBG_S_MSG_TYPE_CLOSE AESCTRDRBG_S_MSG_TYPE(2U) +#define AESCTRDRBG_S_MSG_TYPE_RESEED AESCTRDRBG_S_MSG_TYPE(3U) +#define AESCTRDRBG_S_MSG_TYPE_GET_RANDOM_BYTES AESCTRDRBG_S_MSG_TYPE(4U) +#define AESCTRDRBG_S_MSG_TYPE_GENERATE_KEY AESCTRDRBG_S_MSG_TYPE(5U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESCTRDRBG_construct(). + */ +#ifndef CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE + #define CONFIG_AESCTRDRBG_S_CONFIG_POOL_SIZE 1 +#endif + +/* + * ========= AES CTR DRBG Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES CTR DRBG secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESCTRDRBG_Config *config; + const AESCTRDRBG_Params *params; +} AESCTRDRBG_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESCTRDRBG_Params *params; +} AESCTRDRBG_s_OpenMsg; + +typedef struct +{ + AESCTRDRBG_Handle handle; +} AESCTRDRBG_s_CloseMsg; + +typedef struct +{ + AESCTRDRBG_Handle handle; + const void *seed; + const void *additionalData; + size_t additionalDataLength; +} AESCTRDRBG_s_ReseedMsg; + +typedef struct +{ + AESCTRDRBG_Handle handle; + void *randomBytes; + size_t randomBytesSize; +} AESCTRDRBG_s_GetRandomBytesMsg; + +typedef struct +{ + AESCTRDRBG_Handle handle; + CryptoKey *randomKey; +} AESCTRDRBG_s_GenerateKeyMsg; + +/*! + * @brief Handles PSA messages for AES CTR DRBG secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESCTRDRBG_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES CTR DRBG secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESCTRDRBG_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctrdrbg_AESCTRDRBGX4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c new file mode 100644 index 00000000..b514a63b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.c @@ -0,0 +1,738 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include + #include +#endif + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#else + #include +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #define CryptoKeyPlaintext_initKey CryptoKeyPlaintextHSM_initKey +#endif + +/* Forward declarations */ +static void AESCTRDRBGXX_addBigendCounter(uint8_t *counter, uint32_t increment); +static int_fast16_t AESCTRDRBGXX_updateState(AESCTRDRBG_Handle handle, + const void *additionalData, + size_t additionalDataLength); +static void AESCTRDRBG_uninstantiate(AESCTRDRBG_Handle handle); + +/* Static globals */ +static bool isInitialized = false; + +#define CEIL(x, y) (1 + (((x)-1) / (y))) + +/* + * ======== AESCTRDRBG_init ======== + */ +void AESCTRDRBG_init(void) +{ + AESCTR_init(); + + isInitialized = true; +} + +/* + * ======== AESCTRDRBGXX_updateState ======== + */ +static int_fast16_t AESCTRDRBGXX_updateState(AESCTRDRBG_Handle handle, + const void *additionalData, + size_t additionalDataLength) +{ + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + /* + * Buffer must be word aligned as some AESCTR implementations require + * word aligned I/O. + */ + uint32_t buf32[(AESCTRDRBG_MAX_SEED_LENGTH + 3) / 4] = {0}; + + object = handle->object; + + /* + * We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + * We do not need to worry about the counter being 1 over afterwards + * as we will replace the global counter with part of the + * encrypted result. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, 1); + + /* + * Wrap the memcpy below in a zero-length check. Do not remove it! + * The explicit check is necessary for klocwork to stop emitting a critical + * warning. Theoretically, memcpy with a length argument of 0 should do + * nothing. However klocwork emits a warning that there is an out + * of bounds array access (underflow) on buf32 if this check is not in place. + */ + if (additionalDataLength > 0) + { + /* + * Copy over any additional data and operate on buf32 in place. This way + * we can have the case where additionalDataLength < seedLength. This is + * useful in AESCTRDRBG_getBytes() to avoid allocating a spare empty + * buffer. + */ + memcpy(buf32, additionalData, additionalDataLength); + } + + operation.key = &object->key; + operation.input = (uint8_t *)buf32; + operation.output = (uint8_t *)buf32; + operation.initialCounter = object->counter; + operation.inputLength = object->key.u.plaintext.keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + + if (AESCTR_oneStepEncrypt(object->ctrHandle, &operation) != AESCTR_STATUS_SUCCESS) + { + return AESCTRDRBG_STATUS_ERROR; + } + + /* Copy the left most keyLength bytes of the computed result */ + memcpy(object->keyingMaterial, buf32, object->key.u.plaintext.keyLength); + + /* + * Copy new counter value as the right most 16 bytes of the computed result. + * The key length is always a word multiple number of bytes so we can divide + * by word size to determine the buf32 index. + */ + memcpy(object->counter, + &buf32[object->key.u.plaintext.keyLength / sizeof(uint32_t)], + AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + /* Wipe the stack buffer */ + memset(buf32, 0, object->seedLength); + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== AESCTRDRBGXX_addBigendCounter ======== + */ +static void AESCTRDRBGXX_addBigendCounter(uint8_t *counter, uint32_t increment) +{ + uint64_t *counter64 = (uint64_t *)counter; + uint64_t prior; + + /* Turn it into a little-endian counter */ + CryptoUtils_reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + + prior = counter64[0]; + + /* Increment as a 64-bit number */ + counter64[0] += increment; + + /* Check if we wrapped and need to increment the upper 64 bits */ + if (counter64[0] < prior) + { + counter64[1]++; + } + + /* Turn it back into a big-endian integer */ + CryptoUtils_reverseBufferBytewise(counter64, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); +} + +/* + * ======== AESCTRDRBG_uninstantiate ======== + * + * Per the NIST Recommendation SP 800-90A Rev. 1 for DRBG, uninstantiate is the operation + * of clearing the internal state {keyingMaterial, counter, reseedCounter} by writing + * all 0's. Once uninstantiated, the DRBG instance shall not be used until it's + * instantiated again with a fresh seed. + * + * This implementation also sets the isInstantiated flag to false. This function + * should be called if any of the AESCTR operations fail so that the DRBG instance + * will never be usable when its internal state is potentially corrupt. + */ +static void AESCTRDRBG_uninstantiate(AESCTRDRBG_Handle handle) +{ + AESCTRDRBGXX_Object *object; + + object = handle->object; + + object->isInstantiated = false; + memset(object->keyingMaterial, 0, object->key.u.plaintext.keyLength); + memset(object->counter, 0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + object->reseedCounter = 0; +} + +/* + * ======== AESCTRDRBG_construct ======== + */ +AESCTRDRBG_Handle AESCTRDRBG_construct(AESCTRDRBG_Config *config, const AESCTRDRBG_Params *params) +{ + AESCTRDRBG_Handle handle = (AESCTRDRBG_Handle)config; + AESCTRDRBGXX_Object *object; + const AESCTRDRBGXX_HWAttrs *hwAttrs; + AESCTR_Params ctrParams; + uintptr_t key; + int_fast16_t status; + + /* There are no valid default params for this driver */ + if (params == NULL) + { + return NULL; + } + + DebugP_assert(handle); + object = handle->object; + hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* + * personalizationDataLength must be within + * [0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES + KeyLength] bytes. + */ + if (params->personalizationDataLength > params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) + { + return NULL; + } + + /* Open the driver's AESCTR instance */ + AESCTR_Params_init(&ctrParams); +#if (TFM_ENABLED == 0) + ctrParams.returnBehavior = (AESCTR_ReturnBehavior)(params->returnBehavior); +#else + /* + * For the secure-only implementation, AESCTRDRBG supports blocking or + * polling return behavior. However, when TF-M is enabled, polling return + * behavior must be forced since drivers cannot block inside the TF-M. + */ + ctrParams.returnBehavior = AESCTR_RETURN_BEHAVIOR_POLLING; +#endif + + /* Zero out the AESCTR object to ensure AESCTR_construct() will not fail */ + memset(&object->aesctrObject, 0, sizeof(object->aesctrObject)); + object->ctrConfig.object = &object->aesctrObject; + object->ctrConfig.hwAttrs = &hwAttrs->aesctrHWAttrs; + + object->ctrHandle = AESCTR_construct(&object->ctrConfig, &ctrParams); + + if (object->ctrHandle == NULL) + { + object->isOpen = false; + + return NULL; + } + + /* Initialize CryptoKey for later use */ + CryptoKeyPlaintext_initKey(&object->key, object->keyingMaterial, params->keyLength); + + /* Zero-out counter and keyingMaterial */ + memset(object->counter, 0, AESCTRDRBG_AES_BLOCK_SIZE_BYTES); + memset(object->keyingMaterial, 0, params->keyLength); + + /* Store constants for later */ + object->seedLength = params->keyLength + AESCTRDRBG_AES_BLOCK_SIZE_BYTES; + object->reseedInterval = params->reseedInterval; + + /* Ideally this should be set only after instantiation is complete. However + * since this implementation uses the reseed function, this flag is set here + * to ensure it doesn't fail with AESCTRDRBG_STATUS_UNINSTANTIATED. + * Note that if reseed fails due to other reasons, the following call to + * uninstantiate will clear this flag. + */ + object->isInstantiated = true; + + /* Reseed the instance to generate the initial (counter, keyingMaterial) pair */ + status = AESCTRDRBG_reseed(handle, params->seed, params->personalizationData, params->personalizationDataLength); + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTR_close(object->ctrHandle); + AESCTRDRBG_uninstantiate(handle); + object->isOpen = false; + + return NULL; + } + + return handle; +} + +/* + * ======== AESCTRDRBG_close ======== + */ +void AESCTRDRBG_close(AESCTRDRBG_Handle handle) +{ + AESCTRDRBGXX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + AESCTR_close(object->ctrHandle); + + AESCTRDRBG_uninstantiate(handle); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== AESCTRDRBG_getBytes ======== + */ +int_fast16_t AESCTRDRBG_getBytes(AESCTRDRBG_Handle handle, CryptoKey *randomBytes) +{ + return AESCTRDRBG_generateKey(handle, randomBytes); +} + +/* + * ======== AESCTRDRBG_generateKey ======== + */ +int_fast16_t AESCTRDRBG_generateKey(AESCTRDRBG_Handle handle, CryptoKey *randomKey) +{ + int_fast16_t status = AESCTRDRBG_STATUS_ERROR; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + uint8_t KeyStore_keyingMaterial[AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE]; + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyAttributes *attributesPtr; + + attributesPtr = &attributes; + +#endif /* ENABLE_KEY_STORAGE */ + + if (randomKey != NULL) + { + if (randomKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + status = AESCTRDRBG_getRandomBytes(handle, + randomKey->u.plaintext.keyMaterial, + randomKey->u.plaintext.keyLength); + if (status == AESCTRDRBG_STATUS_SUCCESS) + { + randomKey->encoding = CryptoKey_PLAINTEXT; + } + } +#if (ENABLE_KEY_STORAGE == 1) + else if (randomKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + if ((randomKey->u.keyStore.keyLength != 0) && + (randomKey->u.keyStore.keyLength <= AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE)) + { + /* Copy keyAttributes from CryptoKey structure */ + #if (TFM_ENABLED == 0) + attributesPtr = (KeyStore_PSA_KeyAttributes *)randomKey->u.keyStore.keyAttributes; + #else + keyStoreStatus = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *) + randomKey->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #endif + status = AESCTRDRBG_getRandomBytes(handle, KeyStore_keyingMaterial, randomKey->u.keyStore.keyLength); + + if (status == AESCTRDRBG_STATUS_SUCCESS) + { + keyStoreStatus = KeyStore_PSA_importKey(attributesPtr, + KeyStore_keyingMaterial, + randomKey->u.keyStore.keyLength, + &attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id)); + if (keyStoreStatus == KEYSTORE_PSA_STATUS_SUCCESS) + { + if (attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) == + KEYSTORE_PSA_KEY_LIFETIME_VOLATILE) + { + /* Set the keyID of volatile keys provided by KeyStore driver in the cryptokey structure */ + KeyStore_PSA_initKey(randomKey, + attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id), + randomKey->u.keyStore.keyLength, + NULL); + } + else + { + /* Only update the KeyStore encoding for persistent keys */ + randomKey->encoding = CryptoKey_KEYSTORE; + } + status = AESCTRDRBG_STATUS_SUCCESS; + } + else + { + status = AESCTRDRBG_STATUS_KEYSTORE_ERROR; + } + } + } + } +#endif /* ENABLE_KEY_STORAGE */ + } + + return status; +} + +/* + * ======== AESCTRDRBG_getRandomBytes ======== + */ +int_fast16_t AESCTRDRBG_getRandomBytes(AESCTRDRBG_Handle handle, void *randomBytes, size_t randomBytesSize) +{ + AESCTRDRBGXX_Object *object; + AESCTR_Operation operation; + int_fast16_t status; +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + bool lockAcquired; + uint32_t lockAcquireTimeout; +#endif + + object = handle->object; + + if (object->isInstantiated == false) + { + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + if (object->reseedCounter >= object->reseedInterval) + { + return AESCTRDRBG_STATUS_RESEED_REQUIRED; + } + + /* For CC27XX devices, AES-CTR DRBG leverages the HSM engine for encryption operations. + * The underlying SW architecture maintains an internal mutex mechanism to ensure only + * one driver instance is utilizing the HSM engine at once. Therefore, there is no need + * to call `AESCTR_acquireLock`, `AESCTR_disableThreadSafety`, and `AESCTR_releaseLock`. + */ +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + if (SwiP_inISR() || HwiP_inISR()) + { + lockAcquireTimeout = SemaphoreP_NO_WAIT; + } + else + { + lockAcquireTimeout = SemaphoreP_WAIT_FOREVER; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle, lockAcquireTimeout); + if (!lockAcquired) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); +#endif + + /* Set the keying material of the CryptoKey to 0. + * If we use AESCTR to encrypt a buffer full of zeros, + * the resultant output will be the bitstream of the + * encrypted counters. That is what is used as + * random bits by AESCTRDRBG. + * Zeroing out the keying material and performing + * the AESCTR encryption in place saves us from + * allocating a buffer of the right length full + * of zeros or repeatedly encrypting a 16-byte + * buffer full of zeros. + */ + memset(randomBytes, 0, randomBytesSize); + + /* We need to increment the counter here since regular AESCTR + * only increments the counter after encrypting it while + * AESCTRDRBG increments the counter before encrypting it. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, 1); + + operation.key = &object->key; + operation.input = randomBytes; + operation.output = randomBytes; + operation.initialCounter = object->counter; + operation.inputLength = randomBytesSize; + + status = AESCTR_oneStepEncrypt(object->ctrHandle, &operation); + + if (status != AESCTR_STATUS_SUCCESS) + { +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + AESCTR_releaseLock(object->ctrHandle); +#endif + + if (status == AESCTR_STATUS_UNALIGNED_IO_NOT_SUPPORTED) + { + status = AESCTRDRBG_STATUS_UNALIGNED_IO_NOT_SUPPORTED; + } + else + { + AESCTRDRBG_uninstantiate(handle); + status = AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + return status; + } + + /* Add the number of counter blocks we produced to the + * internal counter. We already incremented by one above + * so we increment by one less here. + */ + AESCTRDRBGXX_addBigendCounter(object->counter, CEIL(randomBytesSize, AESCTRDRBG_AES_BLOCK_SIZE_BYTES) - 1); + + status = AESCTRDRBGXX_updateState(handle, NULL, 0); + +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); +#endif + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTRDRBG_uninstantiate(handle); + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + object->reseedCounter += 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} + +/* + * ======== AESCTRDRBG_reseed ======== + */ +int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, + const void *seed, + const void *additionalData, + size_t additionalDataLength) +{ + AESCTRDRBGXX_Object *object; + int_fast16_t status; + uint8_t tmp[AESCTRDRBG_MAX_SEED_LENGTH]; + uint32_t i; +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + bool lockAcquired; + uint32_t lockAcquireTimeout; +#endif + + object = handle->object; + + if (object->isInstantiated == false) + { + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + if (additionalDataLength > object->seedLength) + { + return AESCTRDRBG_STATUS_ERROR; + } + + /* For CC27XX devices, AES-CTR DRBG leverages the HSM engine for encryption operations. + * The underlying SW architecture maintains an internal mutex mechanism to ensure only + * one driver instance is utilizing the HSM engine at once. Therefore, there is no need + * to call `AESCTR_acquireLock`, `AESCTR_disableThreadSafety`, and `AESCTR_releaseLock`. + */ +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + if (SwiP_inISR() || HwiP_inISR()) + { + lockAcquireTimeout = SemaphoreP_NO_WAIT; + } + else + { + lockAcquireTimeout = SemaphoreP_WAIT_FOREVER; + } + + lockAcquired = AESCTR_acquireLock(object->ctrHandle, lockAcquireTimeout); + if (!lockAcquired) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + AESCTR_disableThreadSafety(object->ctrHandle); +#endif + + /* Set temporary buffer as additionalData padded with zeros */ + memset(tmp, 0, object->seedLength); + memcpy(tmp, additionalData, additionalDataLength); + + /* XOR-in the seed. It should always be a multiple of 32 bits */ + for (i = 0; i < object->seedLength / sizeof(uint32_t); i++) + { + ((uint32_t *)tmp)[i] ^= ((uint32_t *)seed)[i]; + } + + /* Use the combined seed to generate a new (counter, keyingMaterial) pair */ + status = AESCTRDRBGXX_updateState(handle, tmp, object->seedLength); + +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + AESCTR_enableThreadSafety(object->ctrHandle); + AESCTR_releaseLock(object->ctrHandle); +#endif + + if (status != AESCTRDRBG_STATUS_SUCCESS) + { + AESCTRDRBG_uninstantiate(handle); + return AESCTRDRBG_STATUS_UNINSTANTIATED; + } + + object->reseedCounter = 1; + + return AESCTRDRBG_STATUS_SUCCESS; +} + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/* + * ======== AESCTRDRBG_getRandomBytesFromHSM ======== + */ +int_fast16_t AESCTRDRBG_getRandomBytesFromHSM(void *randomBytes, size_t randomBytesSize) +{ + int_fast16_t status = AESCTRDRBG_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + int32_t tokenResult = 0U; + + if ((randomBytesSize > HSM_RAW_RNG_MAX_LENGTH) || (!HSM_IS_SIZE_MULTIPLE_OF_WORD(randomBytesSize))) + { + /* Return error. */ + return AESCTRDRBG_STATUS_INPUT_LENGTH_INVALID; + } + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)0U)) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Populates the HSMLPF3 commandToken as a RNG get DRBG random number operation */ + HSMLPF3_constructRNGGetRandomNumberPhysicalToken((uintptr_t)randomBytes, randomBytesSize); + + /* Submit token to the HSM IP engine */ + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_POLLING, NULL, (uintptr_t)0U); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + /* Handles post command token submission mechanism. + * Waits for a result token from the HSM IP in polling and blocking modes (and calls the drivers post-processing + * fxn) and returns immediately when in callback mode. + */ + hsmRetval = HSMLPF3_waitForResult(); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + tokenResult = HSMLPF3_getResultCode(); + + if ((tokenResult & HSMLPF3_RETVAL_MASK) == EIP130TOKEN_RESULT_SUCCESS) + { + status = AESCTRDRBG_STATUS_SUCCESS; + } + } + } + + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + + return status; +} + +/* + * ======== AESCTRDRBG_reseedHSMPostProcessing ======== + */ +static inline void AESCTRDRBG_reseedHSMPostProcessing(uintptr_t arg0) +{ + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); +} + +/* + * ======== AESCTRDRBG_reseedHSM ======== + */ +int_fast16_t AESCTRDRBG_reseedHSM(void) +{ + int_fast16_t status = AESCTRDRBG_STATUS_ERROR; + int_fast16_t hsmRetval = HSMLPF3_STATUS_ERROR; + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)0U)) + { + return AESCTRDRBG_STATUS_RESOURCE_UNAVAILABLE; + } + + Power_setConstraint(PowerLPF3_DISALLOW_STANDBY); + + /* Populates the HSMLPF3 commandToken as an RNG configure operation */ + HSMLPF3_constructRNGReseedDRBGPhysicalToken(); + + /* Submit token to the HSM IP engine */ + hsmRetval = HSMLPF3_submitToken(HSMLPF3_RETURN_BEHAVIOR_CALLBACK, + AESCTRDRBG_reseedHSMPostProcessing, + (uintptr_t)0U); + + if (hsmRetval == HSMLPF3_STATUS_SUCCESS) + { + status = AESCTRDRBG_STATUS_SUCCESS; + } + else + { + HSMLPF3_releaseLock(); + + Power_releaseConstraint(PowerLPF3_DISALLOW_STANDBY); + } + + return status; +} +#endif \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h new file mode 100644 index 00000000..4ccffd3b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file AESCTRDRBGXX.h + * + * @brief Generic AESCTRDRBG implementation based on the AESCTR driver + * + * This file should only be included in the board file to fill the AESCTR_config + * struct. + * + * # Use of AESCTR # + * This implementation uses the AESCTR driver to generate the random bitstream + * required to mutate the internal AESCTRDRBG state and provide random output + * bits. The driver will construct a dynamic instance of the AESCTR driver. + * Mutual exclusion and hardware access are all handled by the AESCTR driver + * instance. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to them + * are checked (such as whether a driver is already open). Higher input + * parameter validation coverage is achieved by turning on assertions when + * compiling the driver. + */ + +#ifndef ti_drivers_aesctrdrbg_AESCTRDRBGXX__include +#define ti_drivers_aesctrdrbg_AESCTRDRBGXX__include + +#include +#include + +#include +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#else + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @brief Define that specifies the maximum AES key length required + * + * This define defines what the largest AES key length used in an application is. + * Since this implementation needs to support all AES key lengths by default, + * temporary buffers and the internal driver state are sized to accommodate AES-256. + * If only AES-128 is used in an application, the driver can be recompiled + * with a different #AESCTRDRBG_MAX_KEY_LENGTH to save RAM in the #AESCTRDRBGXX_Object + * and reducing stack size requirements. + */ +#ifndef AESCTRDRBG_MAX_KEY_LENGTH + #define AESCTRDRBG_MAX_KEY_LENGTH AESCTRDRBG_AES_KEY_LENGTH_256 +#endif + +/*! @brief Define that specifies the maximum seed length used by the driver */ +#define AESCTRDRBG_MAX_SEED_LENGTH (AESCTRDRBG_MAX_KEY_LENGTH + AESCTRDRBG_AES_BLOCK_SIZE_BYTES) + +#if (ENABLE_KEY_STORAGE == 1) || (TFM_ENABLED == 1) + /*! @brief Maximum output key size in bytes when using KeyStore */ + #define AESCTRDRBG_MAX_KEYSTORE_KEY_SIZE 64 +#endif + +/*! + * @brief AESCTRDRBGXX Hardware Attributes + * + * AESCTR26XX hardware attributes should be included in the board file + * and pointed to by the AESCTR_config struct. + */ +typedef struct +{ + /* + * Priority in HWAttrs will be passed to AESCTR instance upon construct + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + AESCTRLPF3_HWAttrs aesctrHWAttrs; +#else + AESCTRCC26XX_HWAttrs aesctrHWAttrs; +#endif +} AESCTRDRBGXX_HWAttrs; + +/*! + * @brief AESCTRDRBGXX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint8_t keyingMaterial[AESCTRDRBG_AES_KEY_LENGTH_256]; + uint8_t counter[AESCTRDRBG_AES_BLOCK_SIZE_BYTES]; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + AESCTRLPF3_Object aesctrObject; +#else + AESCTRCC26XX_Object aesctrObject; +#endif + AESCTR_Config ctrConfig; + AESCTR_Handle ctrHandle; + CryptoKey key; + size_t seedLength; + uint32_t reseedCounter; + uint32_t reseedInterval; + int_fast16_t returnStatus; + bool isOpen; + bool isInstantiated; +} AESCTRDRBGXX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesctrdrbg_AESCTRDRBGXX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.c new file mode 100644 index 00000000..40db4de3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.c @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESECB_s_SecureCallback aesecbSecureCB_ns[]; +extern AESECBCC26X4_ns_Object aesecbObject_ns[]; + +/* + * ======== AESECB_ns_callbackFxn ======== + */ +void AESECB_ns_callbackFxn(uintptr_t arg) +{ + AESECB_s_SecureCallback *secureCallbackObject = (AESECB_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + aesecbObject_ns[index].callbackFxn(aesecbSecureCB_ns[index].handle, + aesecbSecureCB_ns[index].returnValue, + aesecbSecureCB_ns[index].operation, + aesecbSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESECB_ns_registerCallback ======== + */ +static psa_status_t AESECB_ns_registerCallback(AESECB_Handle handle, const AESECB_Params *params) +{ + AESECB_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&aesecbSecureCB_ns[index].object, + AESECB_ns_callbackFxn, + (uintptr_t)&aesecbSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aesecbSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESECB_init ======== + */ +void AESECB_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESECB_open ======== + */ +AESECB_Handle AESECB_open(uint_least8_t index, const AESECB_Params *params) +{ + AESECB_Handle handle = NULL; + AESECB_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESECB_Params *)&AESECB_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING)) + { + if (AESECB_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesecbObject_ns[index].returnBehavior = params->returnBehavior; + aesecbObject_ns[index].callbackFxn = params->callbackFxn; + aesecbObject_ns[index].semaphoreTimeout = params->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESECB_construct ======== + */ +AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *params) +{ + AESECB_Handle handle = NULL; + AESECB_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESECB_Params *)&AESECB_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING)) + { + if (AESECB_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesecbObject_ns[index].returnBehavior = params->returnBehavior; + aesecbObject_ns[index].callbackFxn = params->callbackFxn; + aesecbObject_ns[index].semaphoreTimeout = params->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESECB_close ======== + */ +void AESECB_close(AESECB_Handle handle) +{ + AESECB_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aesecbSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESECB_oneStepOperation ======== + */ +static int_fast16_t AESECB_oneStepOperation(AESECB_Handle handle, AESECB_Operation *operation, int32_t type) +{ + AESECB_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESECB_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operation; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesecbObject_ns[index].semaphoreTimeout) == false) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESECB_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) && (result != AESECB_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesecbSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESECB_oneStepEncrypt ======== + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + return AESECB_oneStepOperation(handle, operation, AESECB_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESECB_oneStepDecrypt ======== + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + return AESECB_oneStepOperation(handle, operation, AESECB_S_MSG_TYPE_ONE_STEP_DECRYPT); +} + +/* + * ======== AESECB_setupOperation ======== + */ +static int_fast16_t AESECB_setupOperation(AESECB_Handle handle, const CryptoKey *key, int32_t type) +{ + AESECB_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESECB_STATUS_ERROR; + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESECB_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return (result); +} + +/* + * ======== AESECB_setupEncrypt ======== + */ +int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key) +{ + return AESECB_setupOperation(handle, key, AESECB_S_MSG_TYPE_SETUP_ENCRYPT); +} + +/* + * ======== AESECB_setupDecrypt ======== + */ +int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key) +{ + return AESECB_setupOperation(handle, key, AESECB_S_MSG_TYPE_SETUP_DECRYPT); +} + +/* + * ======== AESECB_addData ======== + */ +int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation) +{ + AESECB_s_AddDataMsg addDataMsg; + int_fast16_t result = AESECB_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesecbObject_ns[index].semaphoreTimeout) == false) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESECB_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) && (result != AESECB_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesecbSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESECB_finalize ======== + */ +int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation) +{ + AESECB_s_FinalizeMsg finalizeMsg; + int_fast16_t result = AESECB_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesecbObject_ns[index].semaphoreTimeout) == false) + { + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESECB_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_FINALIZE, invecs, outvecs); + + if ((aesecbObject_ns[index].returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) && (result != AESECB_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesecbObject_ns[index].returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesecbSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESECB_cancelOperation ======== + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) +{ + AESECB_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESECB_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESECB_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESECB_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.h new file mode 100644 index 00000000..14e2b6e8 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESECBCC26X4_ns.h + * + * @brief AESECB Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_aesecb_AESECBCC26X4_ns__include +#define ti_drivers_aesecb_AESECBCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESECBCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESECB_CallbackFxn callbackFxn; + AESECB_ReturnBehavior returnBehavior; +} AESECBCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesecb_AESECBCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.c new file mode 100644 index 00000000..6043cfab --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.c @@ -0,0 +1,838 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESECBCC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESECB_Operation *operation_ns; /* Pointer to non-secure operation */ + AESECB_Operation operation_s; /* Secure copy of operation */ +} AESECB_s_Operation; + +static AESECB_s_Operation AESECB_s_operation; + +/* + * AES ECB Secure Dynamic Instance struct. + */ +typedef struct +{ + AESECB_Config config; + AESECBCC26XX_Object object; + AESECBCC26XX_HWAttrs hwAttrs; +} AESECB_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESECB_construct. + */ +static AESECB_s_DynamicInstance AESECB_s_dynInstance[CONFIG_AESECB_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESECB_s_SecureCallbacks for each driver instance opened or constructed */ +static AESECB_s_SecureCallback *AESECB_s_secureCB[AESECB_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESECB_Config AESECB_config[]; + +/* + * ======== AESECB_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t AESECB_s_getCallbackIndex(AESECB_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESECB_COUNT; index++) + { + if (handle_s == (AESECB_Handle)&AESECB_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESECB_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESECB_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESECB_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESECB_s_hwiCallback ======== + */ +static void AESECB_s_hwiCallback(AESECB_Handle handle_s, + int_fast16_t returnValue, + AESECB_Operation *operation, + AESECB_OperationType operationType) +{ + int8_t index; + AESECB_s_SecureCallback *aesecbSecureCB_ns; + + index = AESECB_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESECB_SECURE_CALLBACK_COUNT)) + { + aesecbSecureCB_ns = AESECB_s_secureCB[index]; + + if (aesecbSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aesecbSecureCB_ns->handle = (AESECB_Handle)(CRYPTO_S_HANDLE_ID_AESECB | index); + aesecbSecureCB_ns->returnValue = returnValue; + aesecbSecureCB_ns->operation = AESECB_s_operation.operation_ns; + aesecbSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aesecbSecureCB_ns->object); + } + } +} + +/* + * ======== AESECB_s_copyConfig ======== + */ +static inline psa_status_t AESECB_s_copyConfig(AESECB_Config **secureConfig, + const AESECB_Config *config, + AESECB_Handle *retHandle) +{ + AESECB_Config *config_s; + AESECB_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESECB_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESECB_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESECB_s_secureCB[i + CONFIG_TI_DRIVERS_AESECB_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESECB OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESECB_Handle)(CRYPTO_S_HANDLE_ID_AESECB | (i + CONFIG_TI_DRIVERS_AESECB_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESECB_s_releaseConfig ======== + */ +static inline void AESECB_s_releaseConfig(AESECB_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESECB) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESECB_COUNT) && (i < AESECB_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESECB_s_dynInstance[i - CONFIG_TI_DRIVERS_AESECB_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESECB_s_copyOperation ======== + * Set secureKey to NULL for segmented operations. + */ +static inline psa_status_t AESECB_s_copyOperation(AESECB_Operation *secureOperation, + CryptoKey *secureKey, + const AESECB_Operation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESECB_Operation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESECB_Operation)); + + /* + * Crypto key member of the AESECB_Operation is used for one-step operations + * only. + */ + if (secureKey != NULL) + { + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the key struct and update the operation + * struct to point to the secure key copy. + */ + (void)spm_memcpy(secureKey, secureOperation->key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(secureKey) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + secureOperation->key = secureKey; + } + + /* Segmented operations may be finalized with or without additional data */ + if (secureOperation->inputLength > 0) + { + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_copyParams ======== + */ +static psa_status_t AESECB_s_copyParams(AESECB_Params *secureParams, const AESECB_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESECB_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESECB_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != AESECB_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESECB_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESECB_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESECB_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESECB_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESECB_Handle AESECB_s_getHandle(AESECB_Handle nsHandle) +{ + AESECB_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESECB) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESECB_COUNT) + { + secureHandle = (AESECB_Handle)&AESECB_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESECB_COUNT) && (i < AESECB_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESECB_s_dynInstance[i - CONFIG_TI_DRIVERS_AESECB_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESECB_s_registerCallback ======== + */ +static inline psa_status_t AESECB_s_registerCallback(psa_msg_t *msg) +{ + AESECB_Handle handle_s; + AESECB_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESECB_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESECB_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESECB_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESECB_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESECB_s_SecureCallback located in + * non-secure memory. + */ + AESECB_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESECB_s_construct ======== + */ +static inline psa_status_t AESECB_s_construct(psa_msg_t *msg) +{ + AESECB_s_ConstructMsg constructMsg; + AESECB_Handle handle; + AESECB_Params params_s; + const AESECB_Params *paramsPtr_s = NULL; + AESECB_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESECB_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESECB_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESECB_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESECB_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_open ======== + */ +static inline psa_status_t AESECB_s_open(psa_msg_t *msg) +{ + AESECB_s_OpenMsg openMsg; + AESECB_Handle handle; + AESECB_Params params_s; + AESECB_Params *paramsPtr_s = NULL; + AESECB_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESECB_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESECB_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESECB_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESECB OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESECB_Handle)(CRYPTO_S_HANDLE_ID_AESECB | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_close ======== + */ +static inline psa_status_t AESECB_s_close(psa_msg_t *msg) +{ + AESECB_Handle handle_s; + AESECB_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESECB_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESECB_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESECB_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + AESECB_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_startOperation ======== + */ +static inline psa_status_t AESECB_s_startOperation(psa_msg_t *msg, int32_t msgType) +{ + AESECB_s_OperationMsg opMsg; + AESECB_Handle handle_s; + AESECB_Operation *operation_s; + CryptoKey key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(opMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &opMsg, sizeof(opMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESECB_s_getHandle(opMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESECB_s_operation.operation_s; + + /* Save pointer to non-secure operation struct */ + AESECB_s_operation.operation_ns = opMsg.operation; + + /* Validate and copy operation */ + status = AESECB_s_copyOperation(operation_s, &key_s, opMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = opMsg.handle; + operation_s = opMsg.operation; + } + + if (msgType == AESECB_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + ret = AESECB_oneStepEncrypt(handle_s, operation_s); + } + else if (msgType == AESECB_S_MSG_TYPE_ONE_STEP_DECRYPT) + { + ret = AESECB_oneStepDecrypt(handle_s, operation_s); + } + else if (msgType == AESECB_S_MSG_TYPE_ADD_DATA) + { + ret = AESECB_addData(handle_s, operation_s); + } + else /* AESECB_S_MSG_TYPE_FINALIZE */ + { + ret = AESECB_finalize(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESECB_s_setupOperation ======== + */ +static inline psa_status_t AESECB_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESECB_s_SetupOperationMsg setupMsg; + AESECB_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESECB_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESECB_S_MSG_TYPE_SETUP_ENCRYPT) + { + ret = AESECB_setupEncrypt(handle_s, keyPtr_s); + } + else + { + ret = AESECB_setupDecrypt(handle_s, keyPtr_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_cancelOperation ======== + */ +static inline psa_status_t AESECB_s_cancelOperation(psa_msg_t *msg) +{ + AESECB_Handle handle_s; + AESECB_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESECB_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESECB_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESECB_s_handlePsaMsg ======== + */ +psa_status_t AESECB_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESECB_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESECB_S_MSG_TYPE_CONSTRUCT: + status = AESECB_s_construct(msg); + break; + + case AESECB_S_MSG_TYPE_OPEN: + status = AESECB_s_open(msg); + break; + + /* + * AESECB_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESECB_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESECB_s_registerCallback(msg); + break; + + case AESECB_S_MSG_TYPE_CLOSE: + status = AESECB_s_close(msg); + break; + + case AESECB_S_MSG_TYPE_ONE_STEP_ENCRYPT: /* Fall through */ + case AESECB_S_MSG_TYPE_ONE_STEP_DECRYPT: /* Fall through */ + case AESECB_S_MSG_TYPE_ADD_DATA: /* Fall through */ + case AESECB_S_MSG_TYPE_FINALIZE: + status = AESECB_s_startOperation(msg, msg->type); + break; + + case AESECB_S_MSG_TYPE_SETUP_ENCRYPT: /* Fall through */ + case AESECB_S_MSG_TYPE_SETUP_DECRYPT: + status = AESECB_s_setupOperation(msg, msg->type); + break; + + /* + * AESECB_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESECB_S_MSG_TYPE_CANCEL_OPERATION: + status = AESECB_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESECB_s_init ======== + */ +void AESECB_s_init(void) +{ + AESECB_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.h new file mode 100644 index 00000000..d6e3cfe1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26X4_s.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aesecb_AESECBCC26X4_s__include +#define ti_drivers_aesecb_AESECBCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES ECB secure message types + */ +#define AESECB_S_MSG_TYPE_CONSTRUCT AESECB_S_MSG_TYPE(0U) +#define AESECB_S_MSG_TYPE_OPEN AESECB_S_MSG_TYPE(1U) +#define AESECB_S_MSG_TYPE_REGISTER_CALLBACK AESECB_S_MSG_TYPE(2U) +#define AESECB_S_MSG_TYPE_CLOSE AESECB_S_MSG_TYPE(3U) +#define AESECB_S_MSG_TYPE_ONE_STEP_ENCRYPT AESECB_S_MSG_TYPE(4U) +#define AESECB_S_MSG_TYPE_ONE_STEP_DECRYPT AESECB_S_MSG_TYPE(5U) +#define AESECB_S_MSG_TYPE_SETUP_ENCRYPT AESECB_S_MSG_TYPE(6U) +#define AESECB_S_MSG_TYPE_SETUP_DECRYPT AESECB_S_MSG_TYPE(7U) +#define AESECB_S_MSG_TYPE_ADD_DATA AESECB_S_MSG_TYPE(8U) +#define AESECB_S_MSG_TYPE_FINALIZE AESECB_S_MSG_TYPE(9U) +#define AESECB_S_MSG_TYPE_CANCEL_OPERATION AESECB_S_MSG_TYPE(10U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESECB_construct(). + */ +#ifndef CONFIG_AESECB_S_CONFIG_POOL_SIZE + #define CONFIG_AESECB_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESECB_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESECB_COUNT + CONFIG_AESECB_S_CONFIG_POOL_SIZE) + +/* + * ========= AES ECB Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES ECB callback fxn parameters */ + AESECB_Handle handle; + int_fast16_t returnValue; + AESECB_Operation *operation; + AESECB_OperationType operationType; +} AESECB_s_SecureCallback; + +/* + * ========= AES ECB Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES ECB secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESECB_Config *config; + const AESECB_Params *params; +} AESECB_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESECB_Params *params; +} AESECB_s_OpenMsg; + +typedef struct +{ + AESECB_Handle handle; + AESECB_s_SecureCallback *callback; +} AESECB_s_CallbackMsg; + +typedef struct +{ + AESECB_Handle handle; +} AESECB_s_CloseMsg; + +typedef struct +{ + AESECB_Handle handle; + AESECB_Operation *operation; +} AESECB_s_OperationMsg; + +typedef AESECB_s_OperationMsg AESECB_s_OneStepOperationMsg; + +typedef struct +{ + AESECB_Handle handle; + const CryptoKey *key; +} AESECB_s_SetupOperationMsg; + +typedef AESECB_s_OperationMsg AESECB_s_AddDataMsg; + +typedef AESECB_s_OperationMsg AESECB_s_FinalizeMsg; + +typedef struct +{ + AESECB_Handle handle; +} AESECB_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for AES ECB secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESECB_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES ECB secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESECB_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesecb_AESECBCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.c b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.c new file mode 100644 index 00000000..8dde9655 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.c @@ -0,0 +1,838 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +/* Forward declarations */ +static void AESECB_hwiFxn(uintptr_t arg0); +static int_fast16_t AESECB_waitForResult(AESECB_Handle handle); +static void AESECB_cleanup(AESECB_Handle handle); +static int_fast16_t AESECB_startOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType); +static int_fast16_t AESECB_addDataInternal(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType); +static int_fast16_t AESECB_setupSegmentedOperation(AESECB_Handle handle, const CryptoKey *key); + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0F + +/* Extern globals */ +extern const AESECB_Config AESECB_config[]; +extern const uint_least8_t AESECB_count; + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESECB_hwiFxn ======== + */ +static void AESECB_hwiFxn(uintptr_t arg0) +{ + AESECBCC26XX_Object *object = ((AESECB_Handle)arg0)->object; + uintptr_t interruptKey; + + interruptKey = HwiP_disable(); + + /* Mark the crypto HW is no longer needed for the current operation */ + object->hwBusy = false; + + /* Mark that the current single-step or multi-step operation is complete */ + if ((object->operationType != AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) && + (object->operationType != AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED)) + { + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + object->returnStatus = AESECB_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_BUS_ERR); + + AESECB_cleanup((AESECB_Handle)arg0); + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + object->callbackFxn((AESECB_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +/* + * ======== AESECB_cleanup ======== + */ +static void AESECB_cleanup(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object = handle->object; + + /* + * Since plaintext keys use two reserved (by convention) slots in + * the keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* + * This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and + * provides small power savings. + */ + AESSelectAlgorithm(0x00); + + if (object->cryptoResourceLocked) + { + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow + * the chaining of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== AESECB_init ======== + */ +void AESECB_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESECB_construct ======== + */ +AESECB_Handle AESECB_construct(AESECB_Config *config, const AESECB_Params *params) +{ + AESECB_Handle handle; + AESECBCC26XX_Object *object; + uintptr_t interruptKey; + + handle = config; + object = handle->object; + + interruptKey = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(interruptKey); + + return NULL; + } + + object->isOpen = true; + + HwiP_restore(interruptKey); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESECB_Params *)&AESECB_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING ? params->timeout + : SemaphoreP_NO_WAIT; + object->threadSafe = true; + object->hwBusy = false; + object->operationInProgress = false; + object->cryptoResourceLocked = false; + + /* + * Set power dependency - that is power up and enable clock + * for Crypto (CryptoResourceCC26XX) module. + */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESECB_close ======== + */ +void AESECB_close(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESECB_waitForResult ======== + */ +static int_fast16_t AESECB_waitForResult(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object = handle->object; + + int_fast16_t result = AESECB_STATUS_ERROR; + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESECB_STATUS_ERROR; + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark the crypto HW is no longer needed for the current operation */ + object->hwBusy = false; + + /* Mark that the current single-step or multi-step operation is complete */ + if ((object->operationType != AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) && + (object->operationType != AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED)) + { + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESECB_cleanup(handle); + } + else if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + result = AESECB_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESECB_startOperation ======== + */ +static int_fast16_t AESECB_startOperation(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBCC26XX_Object *object = handle->object; + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || (operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK)) + { + return AESECB_STATUS_ERROR; + } + + uintptr_t interruptKey; + interruptKey = HwiP_disable(); + + /* Ensure that no other operation is already in progress for this driver instance */ + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + + return AESECB_STATUS_ERROR; + } + else + { + /* Mark the current operation (single-step) is in progress */ + object->operationInProgress = true; + HwiP_restore(interruptKey); + + /* Create an internal copy of the key */ + object->key = *(operation->key); + } + + return AESECB_addDataInternal(handle, operation, operationType); +} + +/* + * ======== AESECB_oneStepEncrypt ======== + */ +int_fast16_t AESECB_oneStepEncrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + return AESECB_startOperation(handle, operation, AESECB_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESECB_oneStepDecrypt ======== + */ +int_fast16_t AESECB_oneStepDecrypt(AESECB_Handle handle, AESECB_Operation *operation) +{ + return AESECB_startOperation(handle, operation, AESECB_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESECB_setupEncrypt ======== + */ +int_fast16_t AESECB_setupEncrypt(AESECB_Handle handle, const CryptoKey *key) +{ + int_fast16_t result = AESECB_setupSegmentedOperation(handle, key); + + if (result != AESECB_STATUS_ERROR) + { + AESECBCC26XX_Object *object = handle->object; + object->operationType = AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED; + } + + return result; +} + +/* + * ======== AESECB_setupDecrypt ======== + */ +int_fast16_t AESECB_setupDecrypt(AESECB_Handle handle, const CryptoKey *key) +{ + int_fast16_t result = AESECB_setupSegmentedOperation(handle, key); + + if (result != AESECB_STATUS_ERROR) + { + AESECBCC26XX_Object *object = handle->object; + object->operationType = AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED; + } + + return result; +} + +/* + * ======== AESECB_setupSegmentedOperation ======== + */ +static int_fast16_t AESECB_setupSegmentedOperation(AESECB_Handle handle, const CryptoKey *key) +{ + DebugP_assert(handle); + + AESECBCC26XX_Object *object = handle->object; + + uintptr_t interruptKey; + interruptKey = HwiP_disable(); + + int_fast16_t result = AESECB_STATUS_SUCCESS; + + /* Ensure that no other operation is already in progress for this driver instance */ + if (object->operationInProgress) + { + result = AESECB_STATUS_ERROR; + HwiP_restore(interruptKey); + } + else + { + /* Mark the current operation (multi-step) is in progress */ + object->operationInProgress = true; + HwiP_restore(interruptKey); + + /* Create an internal copy of the key */ + object->key = *(key); + } + + return result; +} + +/* + * ======== AESECB_addData ======== + */ +int_fast16_t AESECB_addData(AESECB_Handle handle, AESECB_Operation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBCC26XX_Object *object = handle->object; + + /* Check for previous failure or cancellation of segmented operation */ + if (object->returnStatus != AESECB_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->returnStatus; + } + + DebugP_assert(object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED); + + /* Verify the input length is non-zero and a multiple of the block size */ + if ((operation->inputLength == 0U) || (operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK)) + { + return AESECB_STATUS_ERROR; + } + + /* + * Pass object->operationType so that the object's operationType is not + * changed in between calls + */ + return AESECB_addDataInternal(handle, operation, object->operationType); +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== AESECB_getKeyStoreKeyUsage ======== + */ +static KeyStore_PSA_KeyUsage AESECB_getKeyStoreKeyUsage(AESECB_OperationType operationType) +{ + switch (operationType) + { + case AESECB_OPERATION_TYPE_ENCRYPT: + case AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED: + case AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED: + return KEYSTORE_PSA_KEY_USAGE_ENCRYPT; + + case AESECB_OPERATION_TYPE_DECRYPT: + case AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED: + case AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED: + return KEYSTORE_PSA_KEY_USAGE_DECRYPT; + + default: + return 0; + } +} +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +/* + * ======== AESECB_addDataInternal ======== + */ +static int_fast16_t AESECB_addDataInternal(AESECB_Handle handle, + AESECB_Operation *operation, + AESECB_OperationType operationType) +{ + /* Check for these since the function uses them */ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBCC26XX_Object *object = handle->object; + AESECBCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* Only plaintext and KeyStore CryptoKeys are supported for now */ + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESECB_getKeyStoreKeyUsage(operationType); + + if (!keyUsage) + { + return AESECB_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_ECB_NO_PADDING, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESECB_STATUS_KEYSTORE_INVALID_ID; + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESECB_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESECB_STATUS_FEATURE_NOT_SUPPORTED; + } + + /* Only plaintext and KeyStore keys are supported in the current implementation */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + if (object->threadSafe) + { + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + object->operationInProgress = false; + /* Do not capture this status in object->returnStatus to facilitate + * a retry later. */ + return AESECB_STATUS_RESOURCE_UNAVAILABLE; + } + + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESECB_STATUS_SUCCESS; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESECB_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at a hardcoded + * and reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + if (object->cryptoResourceLocked) + { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + object->returnStatus = AESECB_STATUS_ERROR; + + return object->returnStatus; + } + + /* + * DMA_IN_DONE must be disabled, since hwiFxn() is assuming that + * the interrupt source is RESULT_AVAIL + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* + * If we are in AESECB_RETURN_BEHAVIOR_POLLING, we do not want an + * interrupt to trigger. AESWriteToKeyStore() disables and then + * re-enables the CRYPTO IRQ in the NVIC so we need to disable it before + * kicking off the operation. + */ + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_POLLING) + { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks of + * the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in + * the keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + if (object->cryptoResourceLocked) + { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + AESSelectAlgorithm(0); + + object->returnStatus = AESECB_STATUS_ERROR; + + return object->returnStatus; + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Set direction of operation. */ + AESSetCtrl((operationType == AESECB_OPERATION_TYPE_DECRYPT || + operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED || + operationType == AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED) + ? 0 + : CRYPTO_AESCTL_DIR); + + AESSetDataLength(operation->inputLength); + + object->hwBusy = true; + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESECB_waitForResult(handle); +} + +/* + * ======== AESECB_finalize ======== + */ +int_fast16_t AESECB_finalize(AESECB_Handle handle, AESECB_Operation *operation) +{ + /* Publicly accessible functions should check their inputs */ + DebugP_assert(handle); + DebugP_assert(operation); + + AESECBCC26XX_Object *object = handle->object; + + /* Check for previous failure or cancellation of segmented operation */ + if (object->returnStatus != AESECB_STATUS_SUCCESS) + { + /* Return the status of the previous call. + * The callback function will not be executed. + */ + return object->returnStatus; + } + + /* finalize() should only be used in segmented operations */ + DebugP_assert(object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED || + object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED); + + AESECB_OperationType operationType; + + if (object->operationType == AESECB_OPERATION_TYPE_ENCRYPT_SEGMENTED) + { + operationType = AESECB_OPERATION_TYPE_FINALIZE_ENCRYPT_SEGMENTED; + } + else if (object->operationType == AESECB_OPERATION_TYPE_DECRYPT_SEGMENTED) + { + operationType = AESECB_OPERATION_TYPE_FINALIZE_DECRYPT_SEGMENTED; + } + else + { + return AESECB_STATUS_ERROR; + } + + int_fast16_t result = AESECB_STATUS_SUCCESS; + + /* + * Must call addData() with an inputLength > 0 otherwise the crypto core + * will assume the length to be infinite. + */ + if (operation->inputLength > 0) + { + result = AESECB_addDataInternal(handle, operation, operationType); + } + else + { + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new operation after operationInProgress is cleared + */ + result = object->returnStatus; + + /* Since there's no more data to process, mark that the multi-step + * operation is complete here. */ + object->operationInProgress = false; + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_CALLBACK) + { + /* Invoke the application callback function */ + object->callbackFxn(handle, result, operation, operationType); + + /* Always return success in callback mode */ + result = AESECB_STATUS_SUCCESS; + } + } + + return result; +} + +/* + * ======== AESECB_cancelOperation ======== + */ +int_fast16_t AESECB_cancelOperation(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object = handle->object; + uintptr_t interruptKey; + + interruptKey = HwiP_disable(); + + /* Check if the HW operation already completed */ + if (!object->hwBusy) + { + object->returnStatus = AESECB_STATUS_CANCELED; + object->operationInProgress = false; + + HwiP_restore(interruptKey); + + /* No need to call the callback function provided by the application + * since it would have already been called when the HW operation + * completed. + */ + + return AESECB_STATUS_SUCCESS; + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(interruptKey); + + /* Reset the DMA to stop transfers */ + AESDMAReset(); + + /* Issue SW reset to recover the AES engine */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued since disabling + * interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + object->returnStatus = AESECB_STATUS_CANCELED; + object->hwBusy = false; + object->operationInProgress = false; + + if (object->returnBehavior == AESECB_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else /* AESECB_RETURN_BEHAVIOR_CALLBACK */ + { + /* Call the callback function provided by the application */ + object->callbackFxn(handle, AESECB_STATUS_CANCELED, object->operation, object->operationType); + } + + /* Cleanup posts the crypto access semaphore and must be done after the + * operational semaphore is posted to avoid a potential race condition + * when starting a new operation using a different driver instance. + */ + AESECB_cleanup(handle); + + /* Always return success */ + return AESECB_STATUS_SUCCESS; +} + +bool AESECB_acquireLock(AESECB_Handle handle, uint32_t timeout) +{ + + return CryptoResourceCC26XX_acquireLock(timeout); +} + +void AESECB_releaseLock(AESECB_Handle handle) +{ + CryptoResourceCC26XX_releaseLock(); +} + +void AESECB_enableThreadSafety(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object = handle->object; + + object->threadSafe = true; +} +void AESECB_disableThreadSafety(AESECB_Handle handle) +{ + AESECBCC26XX_Object *object = handle->object; + + object->threadSafe = false; +} diff --git a/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.h b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.h new file mode 100644 index 00000000..3eeb8e10 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesecb/AESECBCC26XX.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ========================================================================== + * @file AESECBCC26XX.h + * + * @brief AESECB driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the + * AESECB_config struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is + * capable of multiple AES block cipher modes of operation including ECB. + * Only one operation can be carried out on the accelerator at a time. + * Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the + * application and only noted ensure sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key + * into the AES accelerator is to first load it into the key store. + * To guarantee availability of open key locations in the key store for + * AES operations, the last two key locations (6 and 7) are reserved for + * ad-hoc operations. The key is loaded into the key store, the AES operation + * is carried out, and the key is deleted from the key store. Since the key + * store does not have retention and the keys cannot survive going into + * standby, the key store is only used to load keys into the AES accelerator + * rather than store keys. Support for pre-loading keys into the key store + * and using them in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to + * them are checked (such as whether a driver is already open). + * Higher input parameter validation coverage is achieved by turning + * on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesecb_AESECBCC26XX__include +#define ti_drivers_aesecb_AESECBCC26XX__include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESECBCC26XX Hardware Attributes + * + * AESECB26XX hardware attributes should be included in the board file + * and pointed to by the AESECB_config struct. + */ +typedef struct +{ + /*! + @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support + zero-latency interrupts, thus invalidating the critical sections + in this driver. + */ + uint8_t intPriority; +} AESECBCC26XX_HWAttrs; + +/*! + * @brief AESECBCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + AESECB_Operation *operation; + AESECB_CallbackFxn callbackFxn; + uint32_t semaphoreTimeout; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESECB_ReturnBehavior returnBehavior; + AESECB_OperationType operationType; + bool isOpen; + bool threadSafe; + volatile bool hwBusy; + volatile bool operationInProgress; + volatile bool cryptoResourceLocked; +} AESECBCC26XX_Object; + +/// @cond NODOC +/*! + * @brief Non-public functions required by other drivers + * + * The functions may be required by other drivers to + * ensure thread-safe behavior across multiple calls. + */ +bool AESECB_acquireLock(AESECB_Handle handle, uint32_t timeout); +void AESECB_releaseLock(AESECB_Handle handle); +void AESECB_enableThreadSafety(AESECB_Handle handle); +void AESECB_disableThreadSafety(AESECB_Handle handle); +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesecb_AESECBCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.c b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.c new file mode 100644 index 00000000..fa36f697 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.c @@ -0,0 +1,1893 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#define AES_NON_BLOCK_MULTIPLE_MASK 0x0F + +/* Forward declarations */ +static void AESGCM_generateIntermediateDigest(AESGCM_Handle handle); +static uint32_t AESGetDefaultGCMCtrlValue(bool encrypt); +static void AESGCM_hwiFxn(uintptr_t arg0); +static void AESGCM_cleanup(AESGCMCC26X4_Object *object); +static void AESGCM_getResult(AESGCM_Handle handle); +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_OneStepOperation *operation, + AESGCM_OperationType operationType); +static int_fast16_t AESGCM_setOperationInProgress(AESGCMCC26X4_Object *object); +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle); +static int_fast16_t AESGCM_waitForDMAInDone(AESGCM_Handle handle); +static int_fast16_t AESGCM_setupSegmentedOperation(AESGCM_Handle handle, + const CryptoKey *key, + size_t aadLength, + size_t plaintextLength); +static int_fast16_t AESGCM_addAADInternal(AESGCM_Handle handle, uint8_t *aad, size_t aadLength, AESGCM_Mode direction); +static int_fast16_t AESGCM_addDataInternal(AESGCM_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESGCM_Mode direction); + +/* Static globals */ +static bool isInitialized = false; + +static void AESGCM_generateIntermediateDigest(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object = handle->object; + + uint32_t ctrlVal = AESGetDefaultGCMCtrlValue(object->operationType == AESGCM_OP_TYPE_AAD_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT); + + /* + * Setting get_digest allows an intermediate digest to be generated. + * This is necessary so that the saved context ready bit is set, + * and the intermediate values can be read. + */ + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GET_DIGEST); +} + +/* Function for configuring GCM mode in the AESCTL register */ +static uint32_t AESGetDefaultGCMCtrlValue(bool encrypt) +{ + uint32_t ctrlVal = 0; + + /* + * We need to split building ctrlVal into multiple calls. + * Trying to combine all of the below leads to the compiler removing + * the GCM flag for some reason. + * Unlike CCM, GCM CTR only increments the 32-bit counter at the end of + * the IV not the entire 16-byte IV itself. + * The CTR width should be 32-bits since IVs of length 12 bytes are + * only supported for now. The entire IV will be 16 bytes, 12 bytes + * from the passed-in IV and 4 bytes from the counter. + */ + ctrlVal = CRYPTO_AESCTL_GCM_M | CRYPTO_AESCTL_CTR | CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CTR_WIDTH_32_BIT; + ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; + + return ctrlVal; +} + +/* + * ======== AESGCM_hwiFxn ======== + */ +static void AESGCM_hwiFxn(uintptr_t arg0) +{ + AESGCMCC26X4_Object *object = ((AESGCM_Handle)arg0)->object; + + /* Propagate the DMA error from driverlib to the application */ + uint32_t irqStatus = AESIntStatusRaw(); + + if (irqStatus & AES_DMA_BUS_ERR) + { + object->returnStatus = AESGCM_STATUS_ERROR; + } + else + { + /* Generate an intermediate digest if there is leftover data to process */ + if ((object->actualAADLength != object->expectedAADLength) || + (object->actualPlaintextLength != object->expectedPlaintextLength)) + { + AESGCM_generateIntermediateDigest((AESGCM_Handle)arg0); + } + } + + uintptr_t interruptKey = HwiP_disable(); + + /* + * Mark that we are done with the operation so that AESGCM_cancelOperation + * knows not to try canceling. + */ + object->hwBusy = false; + + if (object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + HwiP_restore(interruptKey); + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + if (object->returnStatus != AESGCM_STATUS_ERROR) + { + /* + * Read out the intermediate values. If a finalize or one-shot + * operation is occurring, the tag is read out and verified against + * a provided MAC or stored + */ + AESGCM_getResult((AESGCM_Handle)arg0); + + /* + * Clear the pending interrupt from setting get_digest when generating + * an intermediate digest + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + /* + * Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore to allow + * callback to chain operations. + * + * When the access semaphore is freed during cleanup, + * if a higher priority ISR shares this driver instance and wishes + * to start a new operation, it must handle synchronization with + * the other thread(s) sharing this driver instance to avoid + * corrupting the driver's object data by starting a new operation + * before the callback is executed for the current operation. + */ + AESGCM_cleanup(object); + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn((AESGCM_Handle)arg0, object->returnStatus, object->operation, object->operationType); + } +} + +static void AESGCM_cleanup(AESGCMCC26X4_Object *object) +{ + /* + * Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use without + * reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* + * This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides + * small power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the + * chaining of operations. + */ + if (object->cryptoResourceLocked) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } +} + +static void AESGCM_getResult(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object = handle->object; + + /* + * The ISR is not reached in polling mode, and generating an + * intermediate digest is necessary if these is more data to process + */ + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + /* Generate an intermediate digest if there is leftover data to process */ + if ((object->actualAADLength != object->expectedAADLength) || + (object->actualPlaintextLength != object->expectedPlaintextLength)) + { + AESGCM_generateIntermediateDigest(handle); + } + } + + /* + * If we have done a HW operation, read the intermediate values from + * the HW to successfully continue future operations. + */ + if (object->continueAADOperation || object->continueDataOperation) + { + /* Read the tag, this will clear the saved context ready bit */ + AESReadTag((uint8_t *)object->intermediateTag, AES_BLOCK_SIZE); + + /* Read the block counter */ + object->blockCounter = AESGetBlockCounter(); + + if (object->actualAADLength == object->expectedAADLength) + { + /* + * Read the IV, must be read after the tag. Unlike CCM, the IV + * should only be updated after processing the last chunk of AAD + * or working with payload data + */ + AESReadAuthenticationModeIV(object->intermediateIV); + + object->continueAADOperation = false; + } + + if (object->actualPlaintextLength == object->expectedPlaintextLength) + { + object->continueDataOperation = false; + } + } + + /* Make sure that the operation can be finalized at this point */ + if ((object->actualAADLength == object->expectedAADLength) && + (object->actualPlaintextLength == object->expectedPlaintextLength)) + { + uint8_t *mac = NULL; + uint8_t macLength = 0; + + if (object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_DECRYPT) + { + mac = object->operation->oneStepOperation.mac; + macLength = object->operation->oneStepOperation.macLength; + } + else if (object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT) + { + mac = object->operation->segmentedFinalizeOperation.mac; + macLength = object->operation->segmentedFinalizeOperation.macLength; + } + + /* + * We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT) + { + /* + * If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + memcpy(mac, object->intermediateTag, macLength); + } + else if (object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT) + { + /* + * If we are decrypting and verifying a message, we must now verify that + * the provided MAC matches the one calculated in the decryption + * operation. + */ + bool macValid = CryptoUtils_buffersMatch((uint8_t *)object->intermediateTag, mac, macLength); + + if (!macValid) + { + object->returnStatus = AESGCM_STATUS_MAC_INVALID; + } + } + + /* + * Clear intermediate buffers to prevent leakage for one-shot + * or finalize operations + */ + if (object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT) + { + CryptoUtils_memset(object->intermediateIV, + sizeof(object->intermediateIV), + 0, + sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + } + } +} + +/* + * ======== AESGCM_init ======== + */ +void AESGCM_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESGCM_construct ======== + */ +AESGCM_Handle AESGCM_construct(AESGCM_Config *config, const AESGCM_Params *params) +{ + AESGCM_Handle handle; + AESGCMCC26X4_Object *object; + uint_fast8_t key; + + handle = (AESGCM_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + object->operationInProgress = false; + object->cryptoResourceLocked = false; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESGCM_Params *)&AESGCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + + if (params->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + object->semaphoreTimeout = params->timeout; + } + else + { + object->semaphoreTimeout = SemaphoreP_NO_WAIT; + } + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESGCM_close ======== + */ +void AESGCM_close(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESGCM_startOperation ======== + */ +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_OneStepOperation *operation, + AESGCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESGCMCC26X4_Object *object = handle->object; + + /* Internally generated ivs aren't supported for now */ + DebugP_assert(!operation->ivInternallyGenerated); + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESGCM_setOperationInProgress(object); + + if (result != AESGCM_STATUS_SUCCESS) + { + return result; + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + object->operationInProgress = false; + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + object->cryptoResourceLocked = true; + } + + object->returnStatus = AESGCM_STATUS_SUCCESS; + + result = AESGCM_setLengths(handle, operation->aadLength, operation->inputLength); + + if (result != AESGCM_STATUS_ERROR) + { + result = AESGCM_setIV(handle, operation->iv, operation->ivLength); + + if (result != AESGCM_STATUS_ERROR) + { + AESGCM_Mode direction = AESGCM_MODE_ENCRYPT; + + if (operationType == AESGCM_OPERATION_TYPE_DECRYPT) + { + direction = AESGCM_MODE_DECRYPT; + } + + object->operationType = operationType; + object->operation = (AESGCM_OperationUnion *)operation; + + object->key = *(operation->key); + + /* Start processing from a clean slate */ + object->blockCounter = 0; + + object->continueAADOperation = false; + object->continueDataOperation = false; + + object->actualAADLength = 0; + object->actualPlaintextLength = 0; + + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + + if (operation->aadLength > 0) + { + /* + * If there is remaining payload data, it will be processed + * in addAADInternal. One-shot operations must process AAD + * and payload data in one go. For one-shot operations, the + * access semaphore shouldn't be released in between + * processing AAD and payload data since another thread + * could take the semaphore and corrupt the Object + */ + result = AESGCM_addAADInternal(handle, operation->aad, operation->aadLength, direction); + } + else if (operation->inputLength > 0) + { + result = AESGCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + direction); + } + } + } + + if ((result != AESGCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + object->operationInProgress = false; + } + + return result; +} + +/* + * ======== AESGCM_setOperationInProgress ======== + */ +static int_fast16_t AESGCM_setOperationInProgress(AESGCMCC26X4_Object *object) +{ + uintptr_t interruptKey = HwiP_disable(); + + if (object->operationInProgress) + { + HwiP_restore(interruptKey); + + return AESGCM_STATUS_ERROR; + } + + object->operationInProgress = true; + + HwiP_restore(interruptKey); + + return AESGCM_STATUS_SUCCESS; +} + +/* + * ======== AESGCM_waitForResult ======== + */ +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESGCM_STATUS_ERROR; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESGCM_STATUS_ERROR; + } + else + { + AESGCM_getResult(handle); + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + if (object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESGCM_cleanup(object); + } + else if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + /* Success is always returned in callback mode */ + result = AESGCM_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESGCM_waitForDMAInDone ======== + */ +static int_fast16_t AESGCM_waitForDMAInDone(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESGCM_STATUS_ERROR; + + /* + * One-step operations containing both AAD and payload data must poll for + * the completion of the AAD transfer and then process the payload data + */ + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the AAD transfer is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESGCM_STATUS_ERROR; + } + else + { + AESGCM_getResult(handle); + } + + /* + * Save the returnStatus prior clearing operationInProgress or + * releasing the access semaphore in case it's overwritten + */ + result = object->returnStatus; + + /* Mark that we are done with the operation */ + object->hwBusy = false; + + if (object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OPERATION_TYPE_DECRYPT) + { + /* One-shot and finalize operations are done at this point */ + object->operationInProgress = false; + } + + /* + * Instead of posting the swi to handle cleanup, we will execute + * the core of the function here + */ + AESGCM_cleanup(object); + } + else if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + result = object->returnStatus; + } + else + { + /* Success is always returned in callback mode */ + result = AESGCM_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESGCM_oneStepEncrypt ======== + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct) +{ + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESGCM_oneStepDecrypt ======== + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct) +{ + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESGCM_setupSegmentedOperation ======== + */ +static int_fast16_t AESGCM_setupSegmentedOperation(AESGCM_Handle handle, + const CryptoKey *key, + size_t aadLength, + size_t plaintextLength) +{ + /* + * Not all of the input values will be asserted here since they will be + * asserted/checked later. Asserts checking the key's validity will occur + * in addAAD/DataInternal for maintainability purposes. The length input + * parameters will be checked in setLengths(). + */ + DebugP_assert(handle); + + AESGCMCC26X4_Object *object = handle->object; + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + /* + * Check that there is no operation in progress for this driver + * instance + */ + result = AESGCM_setOperationInProgress(object); + + if (result != AESGCM_STATUS_ERROR) + { + /* + * If the user doesn't provide the total lengths in the setupXXXX() + * calls, they must provide the lengths in setLengths(). + */ + object->expectedAADLength = aadLength; + object->expectedPlaintextLength = plaintextLength; + + /* Start processing from a clean slate */ + object->blockCounter = 0; + + object->continueAADOperation = false; + object->continueDataOperation = false; + + object->actualAADLength = 0; + object->actualPlaintextLength = 0; + + object->key = *(key); + + memset(object->intermediateTag, 0, sizeof(object->intermediateTag)); + + /* returnStatus is changed in the case of an error or cancellation */ + object->returnStatus = AESGCM_STATUS_SUCCESS; + } + + return result; +} + +/* + * ======== AESGCM_setupEncrypt ======== + */ +int_fast16_t AESGCM_setupEncrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + /* Input values will be asserted in setupSegmentedOperation */ + int_fast16_t result = AESGCM_setupSegmentedOperation(handle, key, totalAADLength, totalPlaintextLength); + + if (result != AESGCM_STATUS_ERROR) + { + AESGCMCC26X4_Object *object = handle->object; + + object->operationType = AESGCM_OPERATION_TYPE_ENCRYPT; + } + + return result; +} + +/* + * ======== AESGCM_setupDecrypt ======== + */ +int_fast16_t AESGCM_setupDecrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + /* Input values will be asserted in setupSegmentedOperation */ + int_fast16_t result = AESGCM_setupSegmentedOperation(handle, key, totalAADLength, totalPlaintextLength); + if (result != AESGCM_STATUS_ERROR) + { + AESGCMCC26X4_Object *object = handle->object; + + object->operationType = AESGCM_OPERATION_TYPE_DECRYPT; + } + + return result; +} + +/* + * ======== AESGCM_setLengths ======== + */ +int_fast16_t AESGCM_setLengths(AESGCM_Handle handle, size_t aadLength, size_t plaintextLength) +{ + DebugP_assert(handle); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + /* This shouldn't be called after addXXX() or finalizeXXX() */ + DebugP_assert(object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT); + + /* The combined length of AAD and payload data must be non-zero */ + if (aadLength == 0 && plaintextLength == 0) + { + return AESGCM_STATUS_ERROR; + } + + object->expectedAADLength = aadLength; + object->expectedPlaintextLength = plaintextLength; + + return AESGCM_STATUS_SUCCESS; +} + +/* + * ======== AESGCM_setIV ======== + */ +int_fast16_t AESGCM_setIV(AESGCM_Handle handle, const uint8_t *iv, size_t ivLength) +{ + /* Public accessible functions should check inputs */ + DebugP_assert(handle); + DebugP_assert(iv); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + /* This shouldn't be called after addXXX() or finalizeXXX() */ + DebugP_assert(object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT); + + /* Only IVs with a length of 12 bytes are supported for now */ + if (ivLength != AESGCM_IV_LENGTH_BYTES) + { + return AESGCM_STATUS_ERROR; + } + + (void)memcpy(object->intermediateIV, iv, ivLength); + + /* Set initial counter value to 1. + * Counter is interpreted as big-endian number of last 4 bytes of IV + */ + object->intermediateIV[3] = 0x01000000; + + return AESGCM_STATUS_SUCCESS; +} + +/* + * ======== AESGCM_generateIV ======== + */ +int_fast16_t AESGCM_generateIV(AESGCM_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength) +{ + /* This feature is not currently supported */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_addAAD ======== + */ +int_fast16_t AESGCM_addAAD(AESGCM_Handle handle, AESGCM_SegmentedAADOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + /* This operation can be called after setup or after addAAD again */ + DebugP_assert(object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESGCM_OP_TYPE_AAD_ENCRYPT); + + /* + * The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of AAD + */ + if (operation->aadLength == 0 || ((operation->aadLength & AES_NON_BLOCK_MULTIPLE_MASK) && + object->actualAADLength + operation->aadLength != object->expectedAADLength)) + { + return AESGCM_STATUS_ERROR; + } + + /* + * The total AAD input length must not exceed the total length specified + * in AESGCM_setLengths() or the setupXXXX() call. + */ + if (object->actualAADLength + operation->aadLength > object->expectedAADLength) + { + return AESGCM_STATUS_ERROR; + } + + AESGCM_Mode direction = AESGCM_MODE_ENCRYPT; + AESGCM_OperationType operationType = AESGCM_OP_TYPE_AAD_ENCRYPT; + + if (object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT) + { + direction = AESGCM_MODE_DECRYPT; + operationType = AESGCM_OP_TYPE_AAD_DECRYPT; + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESGCM_OperationUnion *)operation; + + int_fast16_t result = AESGCM_addAADInternal(handle, operation->aad, operation->aadLength, direction); + + if ((result != AESGCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + + return result; +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== AESGCM_getKeyStoreKeyUsage ======== + */ +static KeyStore_PSA_KeyUsage AESGCM_getKeyStoreKeyUsage(AESGCM_Mode mode) +{ + switch (mode) + { + case AESGCM_MODE_ENCRYPT: + return KEYSTORE_PSA_KEY_USAGE_ENCRYPT; + + case AESGCM_MODE_DECRYPT: + return KEYSTORE_PSA_KEY_USAGE_DECRYPT; + + default: + return 0; + } +} +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +/* + * ======== AESGCM_addAADInternal ======== + */ +static int_fast16_t AESGCM_addAADInternal(AESGCM_Handle handle, uint8_t *aad, size_t aadLength, AESGCM_Mode direction) +{ + DebugP_assert(handle); + DebugP_assert(aad && aadLength); + + AESGCMCC26X4_Object *object = handle->object; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* + * The key is provided as an input in setupEncrypt/Decrypt() + * and within the input operation struct for oneStepEncrypt/Decrypt(), + * and users should check those inputs. + * Only plaintext and KeyStore CryptoKeys are supported for now + */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESGCM_getKeyStoreKeyUsage(direction); + + if (!keyUsage) + { + return AESGCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_GCM, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESGCM_STATUS_KEYSTORE_INVALID_ID; + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESGCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; + } + + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + AESGCMCC26X4_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESGCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at a hardcoded and + * reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + return AESGCM_STATUS_ERROR; + } + + /* + * We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * Only AES_DMA_IN_DONE is asserted when processing intermediate chunks + * of AAD. In that case, the interrupt source is expected to be + * AES_DMA_IN_DONE instead of AES_RESULT_RDY, which is asserted when + * the crypto result is ready after processing payload data or the very + * last chunk of data (which could be AAD). + */ + if ((object->actualAADLength + aadLength == object->expectedAADLength) && object->expectedPlaintextLength == 0) + { + /* + * Disable this interrupt source if this AAD chunk is the very last + * chunk of data to be processed + */ + AESIntDisable(AES_DMA_IN_DONE); + } + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks of + * the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in the + * keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + AESSelectAlgorithm(0); + + return AESGCM_STATUS_ERROR; + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Write zeroes or the intermediate tag to the Key3 registers */ + AESCCMSetTag(object->intermediateTag); + + /* Write the initial or intermediate IV */ + AESSetInitializationVector(object->intermediateIV); + + uint32_t ctrlVal = AESGetDefaultGCMCtrlValue(direction == AESGCM_MODE_ENCRYPT); + + if (object->continueAADOperation) + { + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GCM_CCM_CONTINUE_AAD); + } + else + { + AESSetCtrl(ctrlVal); + } + + AESSetDataLength(object->expectedPlaintextLength); + + if (object->continueAADOperation) + { + AESSetBlockCounter(object->blockCounter); + } + + AESSetAuthLength(object->expectedAADLength); + + object->hwBusy = true; + object->actualAADLength += aadLength; + object->continueAADOperation = true; + + AESStartDMAOperation(aad, aadLength, NULL, 0); + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + /* Process payload data, if any, for one-shot operations */ + if ((object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT) && + object->expectedPlaintextLength > 0) + { + /* Wait until the AAD transfer is complete and check for DMA errors */ + if (AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + result = AESGCM_STATUS_ERROR; + object->hwBusy = false; + + /* Reset the AESCTL register */ + AESSetCtrl(0); + + /* + * Handle cleaning up of the operation: Invalidate the key, + * release power constraint, and post access semaphore. + * + * The semaphore must be posted after the callback is executed + * to prevent another thread which shares the same driver instance + * from starting a new operation and overwriting the object's + * operation and operationType provided to the callback. + */ + AESGCM_cleanup(object); + } + + /* Disable pending interrupt from DMA_IN_DONE */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + if (result != AESGCM_STATUS_ERROR) + { + object->actualPlaintextLength += object->operation->oneStepOperation.inputLength; + object->continueDataOperation = true; + + AESStartDMAOperation(object->operation->oneStepOperation.input, + object->operation->oneStepOperation.inputLength, + object->operation->oneStepOperation.output, + object->operation->oneStepOperation.inputLength); + } + } + + if (result != AESGCM_STATUS_ERROR) + { + /* + * If we are in AESGCM_RETURN_BEHAVIOR_POLLING, + * we do not want an interrupt to trigger. + */ + if (object->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + if ((object->actualAADLength == object->expectedAADLength) && + (object->expectedPlaintextLength == object->actualPlaintextLength)) + { + result = AESGCM_waitForResult(handle); + } + else + { + result = AESGCM_waitForDMAInDone(handle); + } + } + + return result; +} + +/* + * ======== AESGCM_addData ======== + */ +int_fast16_t AESGCM_addData(AESGCM_Handle handle, AESGCM_SegmentedDataOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + /* This operation can be called after setupXXXX, addAAD, or addData. */ + DebugP_assert(object->operationType != AESGCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType != AESGCM_OP_TYPE_FINALIZE_ENCRYPT); + + /* + * The input length must be a non-zero multiple of an AES block size + * unless you are dealing with the last chunk of payload data + */ + if (operation->inputLength == 0 || + ((operation->inputLength & AES_NON_BLOCK_MULTIPLE_MASK) && + object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength)) + { + return AESGCM_STATUS_ERROR; + } + + /* + * The AAD input length specified so far must match the total length + * specified in the setLengths() or setupXXXX() calls. + * All AAD input must be processed at this point. + */ + if (object->actualAADLength != object->expectedAADLength) + { + return AESGCM_STATUS_ERROR; + } + + /* + * The total input length must not exceed the lengths specified in + * AESGCM_setLengths() or setupXXXX(). + */ + if (object->actualPlaintextLength + operation->inputLength > object->expectedPlaintextLength) + { + return AESGCM_STATUS_ERROR; + } + + AESGCM_Mode direction = AESGCM_MODE_ENCRYPT; + AESGCM_OperationType operationType = AESGCM_OP_TYPE_DATA_ENCRYPT; + + if (object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_DECRYPT) + { + direction = AESGCM_MODE_DECRYPT; + operationType = AESGCM_OP_TYPE_DATA_DECRYPT; + } + + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = operationType; + object->operation = (AESGCM_OperationUnion *)operation; + + int_fast16_t result = AESGCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + direction); + + if ((result != AESGCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + + return result; +} + +/* + * ======== AESGCM_addDataInternal ======== + */ +static int_fast16_t AESGCM_addDataInternal(AESGCM_Handle handle, + uint8_t *input, + uint8_t *output, + size_t inputLength, + AESGCM_Mode direction) +{ + DebugP_assert(handle); + DebugP_assert(input && output && inputLength); + + AESGCMCC26X4_Object *object = handle->object; + size_t keyLength; + uint8_t *keyingMaterial = NULL; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage keyUsage; + uint8_t KeyStore_keyingMaterial[AES_256_KEY_LENGTH_BYTES]; +#endif + + /* + * The key is provided as an input in setupEncrypt/Decrypt() + * and within the input operation struct for oneStepEncrypt/Decrypt(), + * and users should check those inputs. + * Only plaintext and KeyStore CryptoKeys are supported for now + */ + DebugP_assert((object->key.encoding == CryptoKey_PLAINTEXT) || (object->key.encoding == CryptoKey_KEYSTORE)); + + if (object->key.encoding == CryptoKey_PLAINTEXT) + { + keyLength = object->key.u.plaintext.keyLength; + keyingMaterial = object->key.u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->key.encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, object->key.u.keyStore.keyID); + + keyUsage = AESGCM_getKeyStoreKeyUsage(direction); + + if (!keyUsage) + { + return AESGCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + &KeyStore_keyingMaterial[0], + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_GCM, + keyUsage); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + return AESGCM_STATUS_KEYSTORE_INVALID_ID; + } + + if (keyLength != object->key.u.keyStore.keyLength) + { + return AESGCM_STATUS_KEYSTORE_GENERIC_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; + } + + /* + * keyMaterial and keyLength are passed to AESWriteToKeyStore(), + * which may be in ROM where it won't have asserts so these + * should be checked in this function. + */ + DebugP_assert(keyingMaterial); + DebugP_assert(keyLength == AES_128_KEY_LENGTH_BYTES || keyLength == AES_192_KEY_LENGTH_BYTES || + keyLength == AES_256_KEY_LENGTH_BYTES); + + AESGCMCC26X4_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI + * callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESGCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* + * Load the key from RAM or flash into the key store at a hardcoded + * and reserved location + */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + return AESGCM_STATUS_ERROR; + } + + /* + * We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * Disable AES_DMA_IN_DONE to prevent triggering an interrupt + * before the crypto result is ready. + */ + AESIntDisable(AES_DMA_IN_DONE); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* + * Load the key from the key store into the internal register banks + * of the AES sub-module + */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* + * Since plaintext keys use two reserved (by convention) slots in + * the keystore, the slots must be invalidated to prevent its re-use + * without reloading the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + AESSelectAlgorithm(0); + + return AESGCM_STATUS_ERROR; + } + + /* + * Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail + * out of the function. This way, we do not need to undo it each time we + * exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + AESCCMSetTag(object->intermediateTag); + AESSetInitializationVector(object->intermediateIV); + + uint32_t ctrlVal = AESGetDefaultGCMCtrlValue(direction == AESGCM_MODE_ENCRYPT); + + /* You are continuing off an operation if AAD has been processed */ + if (object->continueDataOperation || object->actualAADLength != 0) + { + AESSetCtrl(ctrlVal | CRYPTO_AESCTL_GCM_CCM_CONTINUE); + } + else + { + AESSetCtrl(ctrlVal); + } + + AESSetDataLength(object->expectedPlaintextLength); + + if (object->continueDataOperation || object->actualAADLength != 0) + { + AESSetBlockCounter(object->blockCounter); + } + + AESSetAuthLength(object->expectedAADLength); + + object->hwBusy = true; + object->actualPlaintextLength += inputLength; + object->continueDataOperation = true; + + AESStartDMAOperation(input, inputLength, output, inputLength); + + if (object->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + return AESGCM_waitForResult(handle); +} + +/* + * ======== AESGCM_finalizeEncrypt ======== + */ +int_fast16_t AESGCM_finalizeEncrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + DebugP_assert(object->operationType == AESGCM_OP_TYPE_AAD_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_ENCRYPT); + + /* All AAD should be processed at this point in time */ + if (object->actualAADLength != object->expectedAADLength) + { + return AESGCM_STATUS_ERROR; + } + + /* Additional payload data can be passed in finalize */ + if (object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength) + { + return AESGCM_STATUS_ERROR; + } + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + if (operation->inputLength > 0) + { + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = AESGCM_OP_TYPE_FINALIZE_ENCRYPT; + object->operation = (AESGCM_OperationUnion *)operation; + + result = AESGCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + AESGCM_MODE_ENCRYPT); + + if ((result != AESGCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + } + else + { + /* + * An AAD-only operation has been finalized with no new data. + * Copy the output tag computed in cleanup() to the destination + * buffer. + */ + memcpy(operation->mac, object->intermediateTag, operation->macLength); + + /* Clear intermediate buffers to prevent data leakage */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new segmented operation after operationInProgress is + * cleared + */ + result = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, result, (AESGCM_OperationUnion *)operation, AESGCM_OP_TYPE_FINALIZE_ENCRYPT); + + /* Always return success in callback mode */ + result = AESGCM_STATUS_SUCCESS; + } + } + + return result; +} + +/* + * ======== AESGCM_finalizeDecrypt ======== + */ +int_fast16_t AESGCM_finalizeDecrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + AESGCMCC26X4_Object *object = handle->object; + + /* + * Don't continue the segmented operation if there + * was an error or a cancellation + */ + if (object->returnStatus != AESGCM_STATUS_SUCCESS) + { + return object->returnStatus; + } + + DebugP_assert(object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_DECRYPT); + + /* All AAD should be processed at this point in time */ + if (object->actualAADLength != object->expectedAADLength) + { + return AESGCM_STATUS_ERROR; + } + + /* Additional payload data can be passed in finalize */ + if (object->actualPlaintextLength + operation->inputLength != object->expectedPlaintextLength) + { + return AESGCM_STATUS_ERROR; + } + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + if (operation->inputLength > 0) + { + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + object->cryptoResourceLocked = true; + } + + object->operationType = AESGCM_OP_TYPE_FINALIZE_DECRYPT; + object->operation = (AESGCM_OperationUnion *)operation; + + result = AESGCM_addDataInternal(handle, + operation->input, + operation->output, + operation->inputLength, + AESGCM_MODE_DECRYPT); + + if ((result != AESGCM_STATUS_SUCCESS) && (object->cryptoResourceLocked)) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + object->cryptoResourceLocked = false; + } + } + else + { + /* + * An AAD_only operation has been finalized with no new data. + * Compare the provided MAC with the MAC that was calculated in + * cleanup() and stored in Object. + */ + bool macValid = CryptoUtils_buffersMatch(object->intermediateTag, operation->mac, operation->macLength); + + if (!macValid) + { + object->returnStatus = AESGCM_STATUS_MAC_INVALID; + } + + /* Clear intermediate buffers to prevent data leakage */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + + CryptoUtils_memset(object->intermediateTag, + sizeof(object->intermediateTag), + 0, + sizeof(object->intermediateTag)); + + /* + * Save the object's returnStatus in case it's overwritten during + * setup of a new segmented operation after operationInProgress is + * cleared + */ + result = object->returnStatus; + + object->operationInProgress = false; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, result, (AESGCM_OperationUnion *)operation, AESGCM_OP_TYPE_FINALIZE_DECRYPT); + } + } + + return result; +} + +/* + * ======== AESGCM_cancelOperation ======== + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle) +{ + AESGCMCC26X4_Object *object = handle->object; + + uint32_t key; + + key = HwiP_disable(); + + /* Cancel is only supported for callback mode */ + if (object->returnBehavior != AESGCM_RETURN_BEHAVIOR_CALLBACK) + { + HwiP_restore(key); + + return AESGCM_STATUS_ERROR; + } + + if (!object->hwBusy) + { + object->returnStatus = AESGCM_STATUS_CANCELED; + object->operationInProgress = false; + HwiP_restore(key); + + /* Canceling returns success if no HW operations are in progress */ + return AESGCM_STATUS_SUCCESS; + } + + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + HwiP_restore(key); + + /* + * When canceling an operation, data associated with + * the operation should be wiped for security purposes. + */ + CryptoUtils_memset(object->intermediateIV, sizeof(object->intermediateIV), 0, sizeof(object->intermediateIV)); + CryptoUtils_memset(object->intermediateTag, sizeof(object->intermediateTag), 0, sizeof(object->intermediateTag)); + + uint8_t *outputBuffer = NULL; + size_t outputLength = 0; + uint8_t *mac = NULL; + uint8_t macLength = 0; + + /* + * Clear the output buffer. In-progress one-step + * and finalize operations should also clear the MAC + */ + if (object->operationType == AESGCM_OPERATION_TYPE_DECRYPT || + object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT) + { + outputBuffer = object->operation->oneStepOperation.output; + outputLength = object->operation->oneStepOperation.inputLength; + mac = object->operation->oneStepOperation.mac; + macLength = object->operation->oneStepOperation.macLength; + } + else if (object->operationType == AESGCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_DECRYPT) + { + /* + * The output is not guaranteed to be contiguous. Therefore, only + * the passed in output buffer is cleared + */ + outputBuffer = object->operation->segmentedDataOperation.output; + outputLength = object->operation->segmentedDataOperation.inputLength; + } + else if (object->operationType == AESGCM_OP_TYPE_FINALIZE_DECRYPT || + object->operationType == AESGCM_OP_TYPE_FINALIZE_ENCRYPT) + { + outputBuffer = object->operation->segmentedFinalizeOperation.output; + outputLength = object->operation->segmentedFinalizeOperation.inputLength; + mac = object->operation->segmentedFinalizeOperation.mac; + macLength = object->operation->segmentedFinalizeOperation.macLength; + } + + bool clearedBuffer = true; + + int_fast16_t result = AESGCM_STATUS_SUCCESS; + + if (outputBuffer && outputLength) + { + if (object->operationType == AESGCM_OP_TYPE_AAD_ENCRYPT || object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT) + { + /* + * Attempting to clear the output during an AAD operation + * results in a failure + */ + result = AESGCM_STATUS_ERROR; + } + + CryptoUtils_memset(outputBuffer, outputLength, 0, outputLength); + clearedBuffer = CryptoUtils_isBufferAllZeros(outputBuffer, outputLength); + + if (!clearedBuffer) + { + result = AESGCM_STATUS_ERROR; + } + } + + if (mac && macLength) + { + if (object->operationType == AESGCM_OP_TYPE_DATA_ENCRYPT || + object->operationType == AESGCM_OP_TYPE_DATA_DECRYPT || + object->operationType == AESGCM_OP_TYPE_AAD_ENCRYPT || object->operationType == AESGCM_OP_TYPE_AAD_DECRYPT) + { + /* + * Attempting to clear the MAC during a non one-shot or finalize + * operation results in a failure + */ + result = AESGCM_STATUS_ERROR; + } + + CryptoUtils_memset(mac, macLength, 0, macLength); + clearedBuffer = CryptoUtils_isBufferAllZeros(mac, macLength); + + if (!clearedBuffer) + { + result = AESGCM_STATUS_ERROR; + } + } + + AESDMAReset(); + + AESReset(); + + /* + * Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* + * The operation in progress state must be cleared so a user can + * start another operation after canceling. + */ + object->operationInProgress = false; + object->hwBusy = false; + object->returnStatus = AESGCM_STATUS_CANCELED; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, AESGCM_STATUS_CANCELED, object->operation, object->operationType); + } + + /* + * Power down and reset the crypto module, release the power constraint, + * and post the access semaphore + */ + AESGCM_cleanup(object); + + return result; +} diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.h b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.h new file mode 100644 index 00000000..e29893f1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESGCMCC26X4.h + * + * @brief AESGCM driver implementation for the CC26X4 family + * + * This file should only be included in the board file to fill the AESGCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26X4 family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including GCM. Only one operation + * can be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted to ensure that + * sensible access timeouts are set. + * + * # Key Store # + * The CC26X4 crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only 12-byte IV lengths are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesgcm_AESGCMCC26X4__include +#define ti_drivers_aesgcm_AESGCMCC26X4__include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aes.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESGCMCC26X4 Hardware Attributes + * + * AESGCM26X4 hardware attributes should be included in the board file + * and pointed to by the AESGCM_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC27xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESGCMCC26X4_HWAttrs; + +/*! + * @brief AESGCMCC26X4 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t intermediateIV[AES_IV_LENGTH_BYTES / 4]; + uint32_t intermediateTag[AES_TAG_LENGTH_BYTES / 4]; + uint32_t blockCounter; + uint32_t semaphoreTimeout; + AESGCM_CallbackFxn callbackFxn; + AESGCM_OperationUnion *operation; + size_t expectedAADLength; + size_t expectedPlaintextLength; + size_t actualAADLength; + size_t actualPlaintextLength; + CryptoKey key; + volatile int_fast16_t returnStatus; + AESGCM_ReturnBehavior returnBehavior; + AESGCM_OperationType operationType; + /* Track when to set gcm_ccm_continue or continue_aad bit */ + bool continueAADOperation; + bool continueDataOperation; + bool isOpen; + volatile bool operationInProgress; + volatile bool hwBusy; + volatile bool cryptoResourceLocked; +} AESGCMCC26X4_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesgcm_AESGCMCC26X4__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.c new file mode 100644 index 00000000..e4516f38 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.c @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern AESGCM_s_SecureCallback aesgcmSecureCB_ns[]; +extern AESGCMCC26X4_ns_Object aesgcmObject_ns[]; + +/* + * ======== AESGCM_ns_callbackFxn ======== + */ +void AESGCM_ns_callbackFxn(uintptr_t arg) +{ + AESGCM_s_SecureCallback *secureCallbackObject = (AESGCM_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + aesgcmObject_ns[index].callbackFxn(aesgcmSecureCB_ns[index].handle, + aesgcmSecureCB_ns[index].returnValue, + aesgcmSecureCB_ns[index].operation, + aesgcmSecureCB_ns[index].operationType); + } +} + +/* + * ======== AESGCM_ns_registerCallback ======== + */ +static psa_status_t AESGCM_ns_registerCallback(AESGCM_Handle handle, const AESGCM_Params *params) +{ + AESGCM_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&aesgcmSecureCB_ns[index].object, + AESGCM_ns_callbackFxn, + (uintptr_t)&aesgcmSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &aesgcmSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== AESGCM_init ======== + */ +void AESGCM_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== AESGCM_open ======== + */ +AESGCM_Handle AESGCM_open(uint_least8_t index, const AESGCM_Params *params) +{ + AESGCM_Handle handle = NULL; + AESGCM_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESGCM_Params *)&AESGCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING)) + { + if (AESGCM_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesgcmObject_ns[index].returnBehavior = params->returnBehavior; + aesgcmObject_ns[index].callbackFxn = params->callbackFxn; + aesgcmObject_ns[index].semaphoreTimeout = params->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESGCM_construct ======== + */ +AESGCM_Handle AESGCM_construct(AESGCM_Config *config, const AESGCM_Params *params) +{ + AESGCM_Handle handle = NULL; + AESGCM_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (AESGCM_Params *)&AESGCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING)) + { + if (AESGCM_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + aesgcmObject_ns[index].returnBehavior = params->returnBehavior; + aesgcmObject_ns[index].callbackFxn = params->callbackFxn; + aesgcmObject_ns[index].semaphoreTimeout = params->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== AESGCM_close ======== + */ +void AESGCM_close(AESGCM_Handle handle) +{ + AESGCM_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&aesgcmSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESGCM_oneStepOperation ======== + */ +static int_fast16_t AESGCM_oneStepOperation(AESGCM_Handle handle, + AESGCM_OneStepOperation *operationStruct, + int32_t type) +{ + AESGCM_s_OneStepOperationMsg oneStepMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + oneStepMsg.handle = handle; + oneStepMsg.operation = operationStruct; + invecs[0].base = &oneStepMsg; + invecs[0].len = sizeof(oneStepMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesgcmObject_ns[index].semaphoreTimeout) == false) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) && (result != AESGCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesgcmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESGCM_oneStepEncrypt ======== + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct) +{ + return AESGCM_oneStepOperation(handle, operationStruct, AESGCM_S_MSG_TYPE_ONE_STEP_ENCRYPT); +} + +/* + * ======== AESGCM_oneStepDecrypt ======== + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_OneStepOperation *operationStruct) +{ + return AESGCM_oneStepOperation(handle, operationStruct, AESGCM_S_MSG_TYPE_ONE_STEP_DECRYPT); +} + +/* + * ======== AESGCM_setupOperation ======== + */ +static int_fast16_t AESGCM_setupOperation(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength, + int32_t type) +{ + AESGCM_s_SetupOperationMsg setupMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + + /* Setup interface for input parameters */ + setupMsg.handle = handle; + setupMsg.key = key; + setupMsg.totalAADLength = totalAADLength; + setupMsg.totalPlaintextLength = totalPlaintextLength; + invecs[0].base = &setupMsg; + invecs[0].len = sizeof(setupMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return (result); +} + +/* + * ======== AESGCM_setupEncrypt ======== + */ +int_fast16_t AESGCM_setupEncrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + return AESGCM_setupOperation(handle, key, totalAADLength, totalPlaintextLength, AESGCM_S_MSG_TYPE_SETUP_ENCRYPT); +} + +/* + * ======== AESGCM_setupDecrypt ======== + */ +int_fast16_t AESGCM_setupDecrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + return AESGCM_setupOperation(handle, key, totalAADLength, totalPlaintextLength, AESGCM_S_MSG_TYPE_SETUP_DECRYPT); +} + +/* + * ======== AESGCM_setLengths ======== + */ +int_fast16_t AESGCM_setLengths(AESGCM_Handle handle, size_t aadLength, size_t plaintextLength) +{ + AESGCM_s_SetLengthsMsg setLengthMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setLengthMsg.handle = handle; + setLengthMsg.aadLength = aadLength; + setLengthMsg.plaintextLength = plaintextLength; + invecs[0].base = &setLengthMsg; + invecs[0].len = sizeof(setLengthMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_SET_LENGTHS, invecs, outvecs); + + return (result); +} + +/* + * ======== AESGCM_setIV ======== + */ +int_fast16_t AESGCM_setIV(AESGCM_Handle handle, const uint8_t *iv, size_t ivLength) +{ + AESGCM_s_SetIVMsg setIVMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + + DebugP_assert(handle); + + /* Setup interface for input parameters */ + setIVMsg.handle = handle; + setIVMsg.iv = iv; + setIVMsg.ivLength = ivLength; + invecs[0].base = &setIVMsg; + invecs[0].len = sizeof(setIVMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_SET_IV, invecs, outvecs); + + return (result); +} + +/* + * ======== AESGCM_addAAD ======== + */ +int_fast16_t AESGCM_addAAD(AESGCM_Handle handle, AESGCM_SegmentedAADOperation *operation) +{ + AESGCM_s_AddAADMsg addADDMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addADDMsg.handle = handle; + addADDMsg.operation = operation; + invecs[0].base = &addADDMsg; + invecs[0].len = sizeof(addADDMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesgcmObject_ns[index].semaphoreTimeout) == false) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_ADD_AAD, invecs, outvecs); + + if ((aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) && (result != AESGCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesgcmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESGCM_addData ======== + */ +int_fast16_t AESGCM_addData(AESGCM_Handle handle, AESGCM_SegmentedDataOperation *operation) +{ + AESGCM_s_AddDataMsg addDataMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.operation = operation; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesgcmObject_ns[index].semaphoreTimeout) == false) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) && (result != AESGCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesgcmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESGCM_finalizeOperation ======== + */ +static int_fast16_t AESGCM_finalizeOperation(AESGCM_Handle handle, + AESGCM_SegmentedFinalizeOperation *operation, + int32_t type) +{ + AESGCM_s_FinalizeOperationMsg finalizeMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.operation = operation; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(aesgcmObject_ns[index].semaphoreTimeout) == false) + { + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + if (aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + if ((aesgcmObject_ns[index].returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) && (result != AESGCM_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (aesgcmObject_ns[index].returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = aesgcmSecureCB_ns[index].returnValue; + } + + return (result); +} + +/* + * ======== AESGCM_finalizeEncrypt ======== + */ +int_fast16_t AESGCM_finalizeEncrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + return AESGCM_finalizeOperation(handle, operation, AESGCM_S_MSG_TYPE_FINALIZE_ENCRYPT); +} + +/* + * ======== AESGCM_finalizeDecrypt ======== + */ +int_fast16_t AESGCM_finalizeDecrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + { + return AESGCM_finalizeOperation(handle, operation, AESGCM_S_MSG_TYPE_FINALIZE_DECRYPT); + } +} + +/* + * ======== AESGCM_cancelOperation ======== + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle) +{ + AESGCM_s_CancelOperationMsg cancelMsg; + int_fast16_t result = AESGCM_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to AESGCM_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(AESGCM_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.h new file mode 100644 index 00000000..9406a544 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_ns.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESGCMCC26X4.h + * + * @brief AESGCM Nonsecure driver implementation for the CC26X4 family + */ + +#ifndef ti_drivers_aesgcm_AESGCMCC26X4_ns__include +#define ti_drivers_aesgcm_AESGCMCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief AESCCMCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + AESGCM_CallbackFxn callbackFxn; + AESGCM_ReturnBehavior returnBehavior; +} AESGCMCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesgcm_AESGCMCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.c new file mode 100644 index 00000000..d8bd0535 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.c @@ -0,0 +1,1240 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "AESGCMCC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * Stores a secure copy of the operation and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + AESGCM_OperationUnion *operation_ns; /* Pointer to non-secure operation */ + AESGCM_OperationUnion operation_s; /* Secure copy of operation */ +} AESGCM_s_Operation; + +static AESGCM_s_Operation AESGCM_s_operation; + +/* + * AES GCM Secure Dynamic Instance struct. + */ +typedef struct +{ + AESGCM_Config config; + AESGCMCC26X4_Object object; + AESGCMCC26X4_HWAttrs hwAttrs; +} AESGCM_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * AESGCM_construct. + */ +static AESGCM_s_DynamicInstance AESGCM_s_dynInstance[CONFIG_AESGCM_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure AESGCM_s_SecureCallbacks for each driver instance opened or constructed */ +static AESGCM_s_SecureCallback *AESGCM_s_secureCB[AESGCM_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const AESGCM_Config AESGCM_config[]; + +/* + * ======== AESGCM_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +int8_t AESGCM_s_getCallbackIndex(AESGCM_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_AESGCM_COUNT; index++) + { + if (handle_s == (AESGCM_Handle)&AESGCM_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_AESGCM_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &AESGCM_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_AESGCM_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== AESGCM_s_hwiCallback ======== + */ +static void AESGCM_s_hwiCallback(AESGCM_Handle handle_s, + int_fast16_t returnValue, + AESGCM_OperationUnion *operation, + AESGCM_OperationType operationType) +{ + int8_t index; + AESGCM_s_SecureCallback *aesgcmSecureCB_ns; + + index = AESGCM_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < AESGCM_SECURE_CALLBACK_COUNT)) + { + aesgcmSecureCB_ns = AESGCM_s_secureCB[index]; + + if (aesgcmSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + aesgcmSecureCB_ns->handle = (AESGCM_Handle)(CRYPTO_S_HANDLE_ID_AESGCM | index); + aesgcmSecureCB_ns->returnValue = returnValue; + aesgcmSecureCB_ns->operation = AESGCM_s_operation.operation_ns; + aesgcmSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&aesgcmSecureCB_ns->object); + } + } +} + +/* + * ======== AESGCM_s_copyConfig ======== + */ +static inline psa_status_t AESGCM_s_copyConfig(AESGCM_Config **secureConfig, + const AESGCM_Config *config, + AESGCM_Handle *retHandle) +{ + AESGCM_Config *config_s; + AESGCM_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_AESGCM_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &AESGCM_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESGCM_s_secureCB[i + CONFIG_TI_DRIVERS_AESGCM_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_AESGCM OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (AESGCM_Handle)(CRYPTO_S_HANDLE_ID_AESGCM | (i + CONFIG_TI_DRIVERS_AESGCM_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== AESGCM_s_releaseConfig ======== + */ +static inline void AESGCM_s_releaseConfig(AESGCM_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESGCM) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_AESGCM_COUNT) && (i < AESGCM_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + AESGCM_s_dynInstance[i - CONFIG_TI_DRIVERS_AESGCM_COUNT].config.object = NULL; + } + } +} + +/* + * ======== AESGCM_s_copyOneStepOperation ======== + */ +psa_status_t AESGCM_s_copyOneStepOperation(AESGCM_OneStepOperation *secureOperation, + CryptoKey *secureKey, + const AESGCM_OneStepOperation *operation, + int32_t msgType) +{ + /* Internally generated IV is not supported */ + if (secureOperation->ivInternallyGenerated) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESGCM_OneStepOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESGCM_OneStepOperation)); + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the key struct and update the operation + * struct to point to the secure key copy. + */ + (void)spm_memcpy(secureKey, secureOperation->key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(secureKey) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + secureOperation->key = secureKey; + + /* Verify IV address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->iv, secureOperation->ivLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * The combined length of AAD and input data must be non-zero. This validation + * check will occur within the AES GCM driver. + */ + + /* Verify AAD address range if AAD provided */ + if ((secureOperation->aadLength > 0) && + (cmse_has_unpriv_nonsecure_read_access(secureOperation->aad, secureOperation->aadLength) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify input and output address range if input data provided */ + if (secureOperation->inputLength > 0) + { + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* + * Verify MAC address range - MAC is an output for encrypt operation, and an + * input for decrypt operation. + */ + if (msgType == AESGCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else + { + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_copyAddAADOperation ======== + */ +static inline psa_status_t AESGCM_s_copyAddAADOperation(AESGCM_SegmentedAADOperation *secureOperation, + const AESGCM_SegmentedAADOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESGCM_SegmentedAADOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESGCM_SegmentedAADOperation)); + + /* Verify AAD address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->aad, secureOperation->aadLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_copyAddDataOperation ======== + */ +static inline psa_status_t AESGCM_s_copyAddDataOperation(AESGCM_SegmentedDataOperation *secureOperation, + const AESGCM_SegmentedDataOperation *operation) +{ + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESGCM_SegmentedDataOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESGCM_SegmentedDataOperation)); + + /* + * The input length must be a non-zero. This validation check will occur in + * within the AES GCM driver. + */ + + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_copyFinalizeOperation ======== + */ +static inline psa_status_t AESGCM_s_copyFinalizeOperation(AESGCM_SegmentedFinalizeOperation *secureOperation, + const AESGCM_SegmentedFinalizeOperation *operation, + int32_t msgType) +{ + psa_status_t status = PSA_SUCCESS; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(AESGCM_SegmentedFinalizeOperation)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(AESGCM_SegmentedFinalizeOperation)); + + /* Operations can be finalized with or without additional data */ + if (secureOperation->inputLength > 0) + { + /* Verify input address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->input, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->output, secureOperation->inputLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* + * Verify MAC address range - MAC is an output for encrypt operation, and an + * input for decrypt operation. + */ + if (msgType == AESGCM_S_MSG_TYPE_FINALIZE_ENCRYPT) + { + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + status = PSA_ERROR_PROGRAMMER_ERROR; + } + } + else + { + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->mac, secureOperation->macLength) == NULL) + { + status = PSA_ERROR_PROGRAMMER_ERROR; + } + } + + return status; +} + +/* + * ======== AESGCM_s_copyParams ======== + */ +static psa_status_t AESGCM_s_copyParams(AESGCM_Params *secureParams, const AESGCM_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(AESGCM_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(AESGCM_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using AESGCM_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = AESGCM_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = AESGCM_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== AESGCM_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static AESGCM_Handle AESGCM_s_getHandle(AESGCM_Handle nsHandle) +{ + AESGCM_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_AESGCM) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_AESGCM_COUNT) + { + secureHandle = (AESGCM_Handle)&AESGCM_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_AESGCM_COUNT) && (i < AESGCM_SECURE_CALLBACK_COUNT)) + { + secureHandle = &AESGCM_s_dynInstance[i - CONFIG_TI_DRIVERS_AESGCM_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== AESGCM_s_registerCallback ======== + */ +static inline psa_status_t AESGCM_s_registerCallback(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = AESGCM_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = AESGCM_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < AESGCM_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(AESGCM_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to AESGCM_s_SecureCallback located in + * non-secure memory. + */ + AESGCM_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== AESGCM_s_construct ======== + */ +static inline psa_status_t AESGCM_s_construct(psa_msg_t *msg) +{ + AESGCM_s_ConstructMsg constructMsg; + AESGCM_Handle handle; + AESGCM_Params params_s; + const AESGCM_Params *paramsPtr_s = NULL; + AESGCM_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + AESGCM_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = AESGCM_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = AESGCM_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = AESGCM_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_open ======== + */ +static inline psa_status_t AESGCM_s_open(psa_msg_t *msg) +{ + AESGCM_s_OpenMsg openMsg; + AESGCM_Handle handle; + AESGCM_Params params_s; + AESGCM_Params *paramsPtr_s = NULL; + AESGCM_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = AESGCM_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = AESGCM_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + AESGCM_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_AESGCM OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (AESGCM_Handle)(CRYPTO_S_HANDLE_ID_AESGCM | openMsg.index); + } + else + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_close ======== + */ +static inline psa_status_t AESGCM_s_close(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + AESGCM_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + AESGCM_s_releaseConfig(closeMsg.handle); + } + else + { + AESGCM_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_oneStepOperation ======== + */ +static inline psa_status_t AESGCM_s_oneStepOperation(psa_msg_t *msg, int32_t msgType) +{ + AESGCM_s_OneStepOperationMsg oneStepMsg; + AESGCM_Handle handle_s; + AESGCM_OneStepOperation *operation_s; + CryptoKey key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(oneStepMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &oneStepMsg, sizeof(oneStepMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(oneStepMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESGCM_s_operation.operation_s.oneStepOperation; + + /* Save pointer to non-secure operation struct */ + AESGCM_s_operation.operation_ns = (AESGCM_OperationUnion *)oneStepMsg.operation; + + /* Validate and copy operation and key structs */ + status = AESGCM_s_copyOneStepOperation(operation_s, &key_s, oneStepMsg.operation, msgType); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = oneStepMsg.handle; + operation_s = oneStepMsg.operation; + } + + if (msgType == AESGCM_S_MSG_TYPE_ONE_STEP_ENCRYPT) + { + ret = AESGCM_oneStepEncrypt(handle_s, operation_s); + } + else + { + ret = AESGCM_oneStepDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESGCM_s_setupOperation ======== + */ +static inline psa_status_t AESGCM_s_setupOperation(psa_msg_t *msg, int32_t msgType) +{ + AESGCM_s_SetupOperationMsg setupMsg; + AESGCM_Handle handle_s; + CryptoKey key_s; + const CryptoKey *keyPtr_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setupMsg.key, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy key to secure memory */ + (void)spm_memcpy(&key_s, setupMsg.key, sizeof(CryptoKey)); + + if (CryptoKey_verifySecureInputKey(&key_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + keyPtr_s = &key_s; + } + else /* Secure client */ + { + handle_s = setupMsg.handle; + keyPtr_s = setupMsg.key; + } + + if (msgType == AESGCM_S_MSG_TYPE_SETUP_ENCRYPT) + { + ret = AESGCM_setupEncrypt(handle_s, keyPtr_s, setupMsg.totalAADLength, setupMsg.totalPlaintextLength); + } + else + { + ret = AESGCM_setupDecrypt(handle_s, keyPtr_s, setupMsg.totalAADLength, setupMsg.totalPlaintextLength); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_setLengths ======== + */ +static inline psa_status_t AESGCM_s_setLengths(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_s_SetLengthsMsg setLengthsMsg; + int_fast16_t ret; + + if (msg->in_size[0] != sizeof(setLengthsMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setLengthsMsg, sizeof(setLengthsMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(setLengthsMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = setLengthsMsg.handle; + } + + ret = AESGCM_setLengths(handle_s, setLengthsMsg.aadLength, setLengthsMsg.plaintextLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_setIV ======== + */ +static inline psa_status_t AESGCM_s_setIV(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_s_SetIVMsg setIVMsg; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setIVMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setIVMsg, sizeof(setIVMsg)); + + if ((setIVMsg.iv == NULL) || (setIVMsg.ivLength != AESGCM_IV_LENGTH_BYTES)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(setIVMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify IV address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)setIVMsg.iv, setIVMsg.ivLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = setIVMsg.handle; + } + + ret = AESGCM_setIV(handle_s, setIVMsg.iv, setIVMsg.ivLength); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_addAAD ======== + */ +static inline psa_status_t AESGCM_s_addAAD(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_SegmentedAADOperation *operation_s; + AESGCM_s_AddAADMsg addAADMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addAADMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addAADMsg, sizeof(addAADMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(addAADMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESGCM_s_operation.operation_s.segmentedAADOperation; + + /* Save pointer to non-secure operation struct */ + AESGCM_s_operation.operation_ns = (AESGCM_OperationUnion *)addAADMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESGCM_s_copyAddAADOperation(operation_s, addAADMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESGCM_addAAD(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESGCM_addAAD(addAADMsg.handle, addAADMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESGCM_s_addData ======== + */ +static inline psa_status_t AESGCM_s_addData(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_SegmentedDataOperation *operation_s; + AESGCM_s_AddDataMsg addDataMsg; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESGCM_s_operation.operation_s.segmentedDataOperation; + + /* Save pointer to non-secure operation struct */ + AESGCM_s_operation.operation_ns = (AESGCM_OperationUnion *)addDataMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESGCM_s_copyAddDataOperation(operation_s, addDataMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = AESGCM_addData(handle_s, operation_s); + } + else /* Secure client */ + { + ret = AESGCM_addData(addDataMsg.handle, addDataMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESGCM_s_finalizeOperation ======== + */ +static inline psa_status_t AESGCM_s_finalizeOperation(psa_msg_t *msg, int32_t msgType) +{ + AESGCM_s_FinalizeOperationMsg finalizeMsg; + AESGCM_SegmentedFinalizeOperation *operation_s; + AESGCM_Handle handle_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = AESGCM_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &AESGCM_s_operation.operation_s.segmentedFinalizeOperation; + + /* Save pointer to non-secure operation struct */ + AESGCM_s_operation.operation_ns = (AESGCM_OperationUnion *)finalizeMsg.operation; + + /* Verify and copy operation to secure memory */ + status = AESGCM_s_copyFinalizeOperation(operation_s, finalizeMsg.operation, msgType); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + handle_s = finalizeMsg.handle; + operation_s = finalizeMsg.operation; + } + + if (msgType == AESGCM_S_MSG_TYPE_FINALIZE_ENCRYPT) + { + ret = AESGCM_finalizeEncrypt(handle_s, operation_s); + } + else + { + ret = AESGCM_finalizeDecrypt(handle_s, operation_s); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== AESGCM_s_cancelOperation ======== + */ +static inline psa_status_t AESGCM_s_cancelOperation(psa_msg_t *msg) +{ + AESGCM_Handle handle_s; + AESGCM_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = AESGCM_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = AESGCM_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== AESGCM_s_handlePsaMsg ======== + */ +psa_status_t AESGCM_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If AESGCM_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case AESGCM_S_MSG_TYPE_CONSTRUCT: + status = AESGCM_s_construct(msg); + break; + + case AESGCM_S_MSG_TYPE_OPEN: + status = AESGCM_s_open(msg); + break; + + /* + * AESGCM_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case AESGCM_S_MSG_TYPE_REGISTER_CALLBACK: + status = AESGCM_s_registerCallback(msg); + break; + + case AESGCM_S_MSG_TYPE_CLOSE: + status = AESGCM_s_close(msg); + break; + + case AESGCM_S_MSG_TYPE_ONE_STEP_DECRYPT: /* Fall through */ + case AESGCM_S_MSG_TYPE_ONE_STEP_ENCRYPT: + status = AESGCM_s_oneStepOperation(msg, msg->type); + break; + + case AESGCM_S_MSG_TYPE_SETUP_ENCRYPT: /* Fall through */ + case AESGCM_S_MSG_TYPE_SETUP_DECRYPT: + status = AESGCM_s_setupOperation(msg, msg->type); + break; + + case AESGCM_S_MSG_TYPE_SET_LENGTHS: + status = AESGCM_s_setLengths(msg); + break; + + case AESGCM_S_MSG_TYPE_SET_IV: + status = AESGCM_s_setIV(msg); + break; + + case AESGCM_S_MSG_TYPE_ADD_AAD: + status = AESGCM_s_addAAD(msg); + break; + + case AESGCM_S_MSG_TYPE_ADD_DATA: + status = AESGCM_s_addData(msg); + break; + + case AESGCM_S_MSG_TYPE_FINALIZE_ENCRYPT: /* Fall through */ + case AESGCM_S_MSG_TYPE_FINALIZE_DECRYPT: + status = AESGCM_s_finalizeOperation(msg, msg->type); + break; + + /* + * AESGCM_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case AESGCM_S_MSG_TYPE_CANCEL_OPERATION: + status = AESGCM_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== AESGCM_s_init ======== + */ +void AESGCM_s_init(void) +{ + AESGCM_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.h new file mode 100644 index 00000000..79043d67 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26X4_s.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_aesgcm_AESGCMCC26X4_s__include +#define ti_drivers_aesgcm_AESGCMCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * AES GCM secure message types + */ +#define AESGCM_S_MSG_TYPE_CONSTRUCT AESGCM_S_MSG_TYPE(0U) +#define AESGCM_S_MSG_TYPE_OPEN AESGCM_S_MSG_TYPE(1U) +#define AESGCM_S_MSG_TYPE_REGISTER_CALLBACK AESGCM_S_MSG_TYPE(2U) +#define AESGCM_S_MSG_TYPE_CLOSE AESGCM_S_MSG_TYPE(3U) +#define AESGCM_S_MSG_TYPE_ONE_STEP_ENCRYPT AESGCM_S_MSG_TYPE(4U) +#define AESGCM_S_MSG_TYPE_ONE_STEP_DECRYPT AESGCM_S_MSG_TYPE(5U) +#define AESGCM_S_MSG_TYPE_SETUP_ENCRYPT AESGCM_S_MSG_TYPE(6U) +#define AESGCM_S_MSG_TYPE_SETUP_DECRYPT AESGCM_S_MSG_TYPE(7U) +#define AESGCM_S_MSG_TYPE_SET_LENGTHS AESGCM_S_MSG_TYPE(8U) +#define AESGCM_S_MSG_TYPE_SET_IV AESGCM_S_MSG_TYPE(9U) +#define AESGCM_S_MSG_TYPE_ADD_AAD AESGCM_S_MSG_TYPE(10U) +#define AESGCM_S_MSG_TYPE_ADD_DATA AESGCM_S_MSG_TYPE(11U) +#define AESGCM_S_MSG_TYPE_FINALIZE_ENCRYPT AESGCM_S_MSG_TYPE(12U) +#define AESGCM_S_MSG_TYPE_FINALIZE_DECRYPT AESGCM_S_MSG_TYPE(13U) +#define AESGCM_S_MSG_TYPE_CANCEL_OPERATION AESGCM_S_MSG_TYPE(14U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using AESGCM_construct(). + */ +#ifndef CONFIG_AESGCM_S_CONFIG_POOL_SIZE + #define CONFIG_AESGCM_S_CONFIG_POOL_SIZE 1 +#endif + +#define AESGCM_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_AESGCM_COUNT + CONFIG_AESGCM_S_CONFIG_POOL_SIZE) + +/* + * ========= AES GCM Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* AES GCM callback fxn parameters */ + AESGCM_Handle handle; + int_fast16_t returnValue; + AESGCM_OperationUnion *operation; + AESGCM_OperationType operationType; +} AESGCM_s_SecureCallback; + +/* + * ========= AES GCM Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * AES GCM secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + AESGCM_Config *config; + const AESGCM_Params *params; +} AESGCM_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const AESGCM_Params *params; +} AESGCM_s_OpenMsg; + +typedef struct +{ + AESGCM_Handle handle; + AESGCM_s_SecureCallback *callback; +} AESGCM_s_CallbackMsg; + +typedef struct +{ + AESGCM_Handle handle; +} AESGCM_s_CloseMsg; + +typedef struct +{ + AESGCM_Handle handle; + AESGCM_OneStepOperation *operation; +} AESGCM_s_OneStepOperationMsg; + +typedef struct +{ + AESGCM_Handle handle; + const CryptoKey *key; + size_t totalAADLength; + size_t totalPlaintextLength; +} AESGCM_s_SetupOperationMsg; + +typedef struct +{ + AESGCM_Handle handle; + size_t aadLength; + size_t plaintextLength; +} AESGCM_s_SetLengthsMsg; + +typedef struct +{ + AESGCM_Handle handle; + const uint8_t *iv; + size_t ivLength; +} AESGCM_s_SetIVMsg; + +typedef struct +{ + AESGCM_Handle handle; + AESGCM_SegmentedAADOperation *operation; +} AESGCM_s_AddAADMsg; + +typedef struct +{ + AESGCM_Handle handle; + AESGCM_SegmentedDataOperation *operation; +} AESGCM_s_AddDataMsg; + +typedef struct +{ + AESGCM_Handle handle; + AESGCM_SegmentedFinalizeOperation *operation; +} AESGCM_s_FinalizeOperationMsg; + +typedef struct +{ + AESGCM_Handle handle; +} AESGCM_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for AES GCM secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t AESGCM_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the AES GCM secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void AESGCM_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesgcm_AESGCMCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.c b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.c new file mode 100644 index 00000000..18c8b678 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.c @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) + +/* Forward declarations */ +static void AESGCM_hwiFxn(uintptr_t arg0); +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_Operation *operation, + AESGCM_OperationType operationType); +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle); +static void AESGCM_cleanup(AESGCM_Handle handle); + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== AESGCM_hwiFxn ======== + */ +static void AESGCM_hwiFxn(uintptr_t arg0) +{ + AESGCMCC26XX_Object *object = ((AESGCM_Handle)arg0)->object; + uint32_t key; + + key = HwiP_disable(); + if (!object->operationCanceled) + { + + /* Mark that we are done with the operation so that AESGCM_cancelOperation + * knows not to try canceling. + */ + object->operationInProgress = false; + + HwiP_restore(key); + } + else + { + HwiP_restore(key); + return; + } + + /* Propagate the DMA error from driverlib to the application */ + if (AESIntStatusRaw() & AES_DMA_BUS_ERR) + { + object->returnStatus = AESGCM_STATUS_ERROR; + } + + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Handle cleaning up of the operation. Read out the tag + * or verify it against the provided one, invalidate the key, + * release the Power constraints, and post the access semaphore. + */ + AESGCM_cleanup((AESGCM_Handle)arg0); + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. + */ + object->callbackFxn((AESGCM_Handle)arg0, + object->returnStatus, + (AESGCM_OperationUnion *)object->operation, + object->operationType); + } +} + +/* + * ======== AESGCM_cleanup ======== + */ +static void AESGCM_cleanup(AESGCM_Handle handle) +{ + AESGCMCC26XX_Object *object = handle->object; + + /* We need to copy / verify the MAC now so that it is not clobbered when we + * release the CryptoResourceCC26XX_accessSemaphore semaphore. + */ + if (object->operationType == AESGCM_OPERATION_TYPE_ENCRYPT) + { + /* If we are encrypting and authenticating a message, we only want to + * copy the MAC to the target buffer + */ + AESReadTag(object->operation->mac, object->operation->macLength); + } + else + { + uint8_t computedTag[AES_BLOCK_SIZE]; + /* If we are decrypting and verifying a message, we must now verify that + * the provided MAC matches the one calculated in the decryption + * operation. + */ + AESReadTag(computedTag, object->operation->macLength); + + bool macValid = CryptoUtils_buffersMatch(computedTag, object->operation->mac, object->operation->macLength); + + object->returnStatus = macValid ? object->returnStatus : AESGCM_STATUS_MAC_INVALID; + } + + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + /* This powers down all sub-modules of the crypto module until needed. + * It does not power down the crypto module at PRCM level and provides small + * power savings. + */ + AESSelectAlgorithm(0x00); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} + +/* + * ======== AESGCM_init ======== + */ +void AESGCM_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== AESGCM_construct ======== + */ +AESGCM_Handle AESGCM_construct(AESGCM_Config *config, const AESGCM_Params *params) +{ + AESGCM_Handle handle; + AESGCMCC26XX_Object *object; + uint_fast8_t key; + + handle = (AESGCM_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (AESGCM_Params *)&AESGCM_defaultParams; + } + + DebugP_assert(params->returnBehavior == AESGCM_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->semaphoreTimeout = params->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== AESGCM_close ======== + */ +void AESGCM_close(AESGCM_Handle handle) +{ + AESGCMCC26XX_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== AESGCM_startOperation ======== + */ +static int_fast16_t AESGCM_startOperation(AESGCM_Handle handle, + AESGCM_Operation *operation, + AESGCM_OperationType operationType) +{ + DebugP_assert(handle); + DebugP_assert(operation); + + /* Internally generated IVs aren't supported for now */ + DebugP_assert(!operation->ivInternallyGenerated); + + /* Only IVs of length 12 are supported for now */ + DebugP_assert(operation->iv && (operation->ivLength == AESGCM_IV_LENGTH_BYTES)); + DebugP_assert((operation->aad && operation->aadLength) || (operation->input && operation->inputLength)); + DebugP_assert(operation->mac && (operation->macLength <= 16)); + + DebugP_assert(operationType == AESGCM_OPERATION_TYPE_DECRYPT || operationType == AESGCM_OPERATION_TYPE_ENCRYPT); + + AESGCMCC26XX_Object *object = handle->object; + AESGCMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + SemaphoreP_Status resourceAcquired; + uint32_t aesCtrl; + uint32_t iv[4]; + + /* Only IVs with a length of 12 bytes are supported for now */ + if (operation->ivLength != AESGCM_IV_LENGTH_BYTES) + { + return AESGCM_STATUS_ERROR; + } + + /* Only plaintext CryptoKeys are supported for now */ + DebugP_assert(operation->key); + DebugP_assert(operation->key->encoding == CryptoKey_PLAINTEXT); + + uint16_t keyLength = operation->key->u.plaintext.keyLength; + uint8_t *keyingMaterial = operation->key->u.plaintext.keyMaterial; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->semaphoreTimeout); + + if (resourceAcquired != SemaphoreP_OK) + { + object->operationInProgress = false; + return AESGCM_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operationType = operationType; + object->operation = operation; + /* We will only change the returnStatus if there is an error */ + object->returnStatus = AESGCM_STATUS_SUCCESS; + object->operationCanceled = false; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, AESGCM_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + /* Load the key from RAM or flash into the key store at a hardcoded and reserved location */ + if (AESWriteToKeyStore(keyingMaterial, keyLength, AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESGCM_STATUS_ERROR; + } + + /* We need to disable interrupts here to prevent a race condition in + * AESWaitForIRQFlags when inputLength == 0. AESWriteToKeyStore() above + * has enabled the crypto interrupt. + */ + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + + /* Power the AES sub-module of the crypto module */ + AESSelectAlgorithm(AES_ALGSEL_AES); + + /* Load the key from the key store into the internal register banks of the AES sub-module */ + if (AESReadFromKeyStore(AES_KEY_AREA_6) != AES_SUCCESS) + { + /* Since plaintext keys use two reserved (by convention) slots in the keystore, + * the slots must be invalidated to prevent its re-use without reloading + * the key material again. + */ + AESInvalidateKey(AES_KEY_AREA_6); + AESInvalidateKey(AES_KEY_AREA_7); + + object->operationInProgress = false; + + /* Release the CRYPTO mutex */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + return AESGCM_STATUS_ERROR; + } + + /* Disallow standby. We are about to configure and start the accelerator. + * Setting the constraint should happen after all opportunities to fail out of the + * function. This way, we do not need to undo it each time we exit with a failure. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Copy IV to a word-aligned buffer */ + (void)memcpy(iv, (void *)operation->iv, operation->ivLength); + + /* + * Set initial counter value to 1. Counter is interpreted as big-endian + * number of last four bytes of IV. + */ + iv[3] = 0x01000000; + + AESSetInitializationVector(iv); + + /* We need to split building aesCtrl into multiple calls. + * Trying to combine all of the below leads to the compiler removing the GCM flag + * for some reason. + * Unlike CCM, GCM CTR only increments the 32-bit counter at the end of the IV not + * the entire 16-byte IV itself. + */ + aesCtrl = CRYPTO_AESCTL_GCM_M | CRYPTO_AESCTL_CTR | CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CTR_WIDTH_32_BIT; + aesCtrl |= (operationType == AESGCM_OPERATION_TYPE_ENCRYPT) ? CRYPTO_AESCTL_DIR : 0; + AESSetCtrl(aesCtrl); + + AESSetDataLength(operation->inputLength); + AESSetAuthLength(operation->aadLength); + + if (operation->aadLength) + { + /* If aadLength were 0, AESWaitForIRQFlags() would never return as the AES_DMA_IN_DONE flag + * would never trigger. + */ + AESStartDMAOperation(operation->aad, operation->aadLength, NULL, 0); + AESWaitForIRQFlags(AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + } + + /* If we are in AESGCM_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. */ + if (object->returnBehavior != AESGCM_RETURN_BEHAVIOR_POLLING) + { + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + + AESStartDMAOperation(operation->input, operation->inputLength, operation->output, operation->inputLength); + + return AESGCM_waitForResult(handle); +} + +/* + * ======== AESGCM_waitForResult ======== + */ +static int_fast16_t AESGCM_waitForResult(AESGCM_Handle handle) +{ + AESGCMCC26XX_Object *object = handle->object; + + object->operationInProgress = true; + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_POLLING) + { + /* Wait until the operation is complete and check for DMA errors. */ + if (AESWaitForIRQFlags(AES_RESULT_RDY | AES_DMA_BUS_ERR) & AES_DMA_BUS_ERR) + { + object->returnStatus = AESGCM_STATUS_ERROR; + } + + /* Mark that we are done with the operation */ + object->operationInProgress = false; + + /* Make sure to also clear DMA_IN_DONE as it is not cleared above + * but will be set none-the-less. + */ + AESIntClear(AES_RESULT_RDY | AES_DMA_IN_DONE | AES_DMA_BUS_ERR); + + /* Instead of posting the swi to handle cleanup, we will execute + * the core of the function here */ + AESGCM_cleanup(handle); + + return object->returnStatus; + } + else if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else + { + return AESGCM_STATUS_SUCCESS; + } +} + +/* + * ======== AESGCM_oneStepEncrypt ======== + */ +int_fast16_t AESGCM_oneStepEncrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct) +{ + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_ENCRYPT); +} + +/* + * ======== AESGCM_oneStepDecrypt ======== + */ +int_fast16_t AESGCM_oneStepDecrypt(AESGCM_Handle handle, AESGCM_Operation *operationStruct) +{ + + return AESGCM_startOperation(handle, operationStruct, AESGCM_OPERATION_TYPE_DECRYPT); +} + +/* + * ======== AESGCM_setupEncrypt ======== + */ +int_fast16_t AESGCM_setupEncrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_setupDecrypt ======== + */ +int_fast16_t AESGCM_setupDecrypt(AESGCM_Handle handle, + const CryptoKey *key, + size_t totalAADLength, + size_t totalPlaintextLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_setLengths ======== + */ +int_fast16_t AESGCM_setLengths(AESGCM_Handle handle, size_t aadLength, size_t plaintextLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_setIV ======== + */ +int_fast16_t AESGCM_setIV(AESGCM_Handle handle, const uint8_t *iv, size_t ivLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_generateIV ======== + */ +int_fast16_t AESGCM_generateIV(AESGCM_Handle handle, uint8_t *iv, size_t ivSize, size_t *ivLength) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_addAAD ======== + */ +int_fast16_t AESGCM_addAAD(AESGCM_Handle handle, AESGCM_SegmentedAADOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_addData ======== + */ +int_fast16_t AESGCM_addData(AESGCM_Handle handle, AESGCM_SegmentedDataOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_finalizeEncrypt ======== + */ +int_fast16_t AESGCM_finalizeEncrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_finalizeDecrypt ======== + */ +int_fast16_t AESGCM_finalizeDecrypt(AESGCM_Handle handle, AESGCM_SegmentedFinalizeOperation *operation) +{ + /* Segmented operations aren't supported by the HW on this device */ + return AESGCM_STATUS_FEATURE_NOT_SUPPORTED; +} + +/* + * ======== AESGCM_cancelOperation ======== + */ +int_fast16_t AESGCM_cancelOperation(AESGCM_Handle handle) +{ + AESGCMCC26XX_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) + { + HwiP_restore(key); + return AESGCM_STATUS_ERROR; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + AESReset(); + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->operationCanceled = true; + object->returnStatus = AESGCM_STATUS_CANCELED; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + if (object->returnBehavior == AESGCM_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, + AESGCM_STATUS_CANCELED, + (AESGCM_OperationUnion *)object->operation, + object->operationType); + } + + return AESGCM_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.h b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.h new file mode 100644 index 00000000..d5c41219 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/aesgcm/AESGCMCC26XX.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file AESGCMCC26XX.h + * + * @brief AESGCM driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the AESGCM_config + * struct. + * + * # Hardware Accelerator # + * The CC26XX family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation including GCM. Only one operation + * can be carried out on the accerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying on + * the accelerator. It is transparent to the application and only noted ensure + * sensible access timeouts are set. + * + * # Key Store # + * The CC26XX crypto module contains a key store. The only way to load a key into + * the AES accelerator is to first load it into the key store. To guarantee availability + * of open key locations in the key store for AES operations, the last two key + * locations (6 and 7) are reserved for ad-hoc operations. The key is loaded into the + * key store, the AES operation is carried out, and the key is deleted from the key store. + * Since the key store does not have retention and the keys can not survive going into + * standby, the key store is only used to load keys into the AES accelerator rather + * than store keys. Support for pre-loading keys into the key store and using them + * in an AES operation is not supported in this driver. + * + * # Implementation Limitations + * - Only plaintext CryptoKeys are supported by this implementation. + * - Only 12-byte IV lengths are supported by this implementation. + * - This implementation does not support internal generation of IVs + * + * # Runtime Parameter Validation # + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + */ + +#ifndef ti_drivers_aesgcm_AESGCMCC26XX__include +#define ti_drivers_aesgcm_AESGCMCC26XX__include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief AESGCMCC26XX Hardware Attributes + * + * AESGCM26XX hardware attributes should be included in the board file + * and pointed to by the AESGCM_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} AESGCMCC26XX_HWAttrs; + +/*! + * @brief AESGCMCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESGCM_ReturnBehavior returnBehavior; + AESGCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESGCM_CallbackFxn callbackFxn; + AESGCM_Operation *operation; +} AESGCMCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_aesgcm_AESGCMCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.c b/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.c new file mode 100644 index 00000000..b0d5bf23 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#if (defined(__IAR_SYSTEMS_ICC__) || defined(__TI_COMPILER_VERSION__)) + #include + #define BSWAP32 __rev +#else + #define BSWAP32 __builtin_bswap32 +#endif + +/* Static globals */ +static bool ANSIX936KDF_isInitialized = false; + +/* Forward declarations */ +static ANSIX936KDFXX_Object *ANSIX936KDFXX_getObject(ANSIX936KDF_Handle handle); + +/* + * ======== ANSIX936KDFXX_getObject ======== + */ +static inline ANSIX936KDFXX_Object *ANSIX936KDFXX_getObject(ANSIX936KDF_Handle handle) +{ + return (ANSIX936KDFXX_Object *)handle->object; +} + +/* + * ======== ANSIX936KDF_init ======== + */ +void ANSIX936KDF_init(void) +{ + SHA2_init(); + + ANSIX936KDF_isInitialized = true; +} + +/* + * ======== ANSIX936KDF_construct ======== + */ +ANSIX936KDF_Handle ANSIX936KDF_construct(ANSIX936KDF_Config *config, const ANSIX936KDF_Params *params) +{ + ANSIX936KDF_Handle handle = (ANSIX936KDF_Config *)config; + ANSIX936KDFXX_Object *object = ANSIX936KDFXX_getObject(handle); + const ANSIX936KDFXX_HWAttrs *hwAttrs = config->hwAttrs; + SHA2_Params sha2Params; + uintptr_t key; + + key = HwiP_disable(); + + if (!ANSIX936KDF_isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + if (params == NULL) + { + params = &ANSIX936KDF_defaultParams; + } + + /* Zero out the SHA2 object to ensure SHA2_construct() will not fail */ + memset(&object->sha2Object, 0, sizeof(object->sha2Object)); + object->sha2Config.object = &object->sha2Object; + object->sha2Config.hwAttrs = &hwAttrs->sha2HWAttrs; + + /* Initialize SHA2 params - default hash type is SHA2_HASH_TYPE_256 */ + SHA2_Params_init(&sha2Params); + sha2Params.returnBehavior = (SHA2_ReturnBehavior)params->returnBehavior; + + object->sha2Handle = SHA2_construct(&object->sha2Config, &sha2Params); + + if (object->sha2Handle == NULL) + { + object->isOpen = false; + + handle = NULL; + } + + return handle; +} + +/* + * ======== ANSIX936KDF_close ======== + */ +void ANSIX936KDF_close(ANSIX936KDF_Handle handle) +{ + ANSIX936KDFXX_Object *object = ANSIX936KDFXX_getObject(handle); + + SHA2_close(object->sha2Handle); + + object->isOpen = false; +} + +/* + * ======== ANSIX936KDF_deriveKey ======== + */ +int_fast16_t ANSIX936KDF_deriveKey(ANSIX936KDF_Handle handle, + const void *input, + size_t inputLen, + const void *sharedInfo, + size_t sharedInfoLen, + void *output, + size_t outputLen) +{ + ANSIX936KDFXX_Object *object = ANSIX936KDFXX_getObject(handle); + int_fast16_t sha2Status = SHA2_STATUS_SUCCESS; + int_fast16_t status; + SHA2_Handle sha2Handle = object->sha2Handle; + size_t copyLen; + size_t outputBytesRemaining = outputLen; + uint32_t bigEndianCounter; + uint32_t counter; + uint32_t digest[SHA2_DIGEST_LENGTH_BYTES_256] = {0}; + uint8_t *dest = (uint8_t *)output; + + if ((sharedInfo == NULL) && (sharedInfoLen != 0)) + { + return ANSIX936KDF_STATUS_ERROR; + } + + /* ======================================================================== + * Reference SEC 1 version 2.0 standard section 3.6.1. + * + * Skipping the check for "|Z| + |SharedInfo| + 4 < hashmaxlength" where Z + * is the input data since the SHA2 driver can handle size_t length for + * each individual component. + * + * Skipping the check for "keydatalen < hashlen * (2^32-1)" where keydatalen + * is the output length since the output length is limited to size_t which + * means the check will always pass. + * + * For i = 1 to keydatalen/hashLen, where keydatalen equals outputLen, + * Compute: Ki = SHA-2(Z || Counter || [SharedInfo]) + * where Counter is 32-bit, big-endian byte order with initial value of 1. + * + * The output is the concatenation of computed K values truncated to the + * specified output length. + * ======================================================================== + */ + + counter = 1; + + while ((outputBytesRemaining > 0U) && (sha2Status == SHA2_STATUS_SUCCESS)) + { + if (sha2Status == SHA2_STATUS_SUCCESS) + { + /* Hash the input */ + sha2Status = SHA2_addData(sha2Handle, input, inputLen); + } + + if (sha2Status == SHA2_STATUS_SUCCESS) + { + /* Hash the counter converted to big endian */ + bigEndianCounter = BSWAP32(counter); + sha2Status = SHA2_addData(sha2Handle, &bigEndianCounter, sizeof(counter)); + } + + if ((sharedInfoLen != 0) && (sha2Status == SHA2_STATUS_SUCCESS)) + { + /* Hash the shared info */ + sha2Status = SHA2_addData(sha2Handle, sharedInfo, sharedInfoLen); + } + + if (sha2Status == SHA2_STATUS_SUCCESS) + { + sha2Status = SHA2_finalize(sha2Handle, digest); + } + + if (sha2Status == SHA2_STATUS_SUCCESS) + { + copyLen = Math_MIN(outputBytesRemaining, SHA2_DIGEST_LENGTH_BYTES_256); + memcpy(dest, digest, copyLen); + + outputBytesRemaining -= copyLen; + dest += copyLen; + } + + counter++; + } + + if (sha2Status == SHA2_STATUS_SUCCESS) + { + status = ANSIX936KDF_STATUS_SUCCESS; + } + else if (sha2Status == SHA2_STATUS_RESOURCE_UNAVAILABLE) + { + status = ANSIX936KDF_STATUS_RESOURCE_UNAVAILABLE; + } + else + { + status = ANSIX936KDF_STATUS_ERROR; + } + + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.h b/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.h new file mode 100644 index 00000000..d6ef600f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ansix936kdf/ANSIX936KDFXX.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ANSIX936KDFXX.h + * + * @brief ANSI-X9.63 Key Derivation Function driver implementation + * for the CC13X1/CC26X1, CC13X2/CC26X2, CC13X4/CC26X4, and CC23X0 + * families + * + * This file should only be included in the board file to fill the + * ANSIX936KDF_config struct. + * + * # Supported Hash Type # + * SHA-256 is in the only hash type supported. + * + * # Limitations # + * - Callback return behavior is not supported. + * - For devices which utilize SW-backed SHA2 implementations: + * - Blocking return behavior does not yield and operates exactly the same as + * polling mode. + */ + +#ifndef ti_drivers_ansix936kdf_ANSIX936KDFXX__include +#define ti_drivers_ansix936kdf_ANSIX936KDFXX__include + +#include + +#include + +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + #include +#elif ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)) + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + #include +#else + #error "ANSIX936KDFXX device family not supported" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Hardware-specific configuration attributes + * + * ANSIX936KDFXX hardware attributes are used in the board file by the + * #ANSIX936KDF_Config struct. + */ +typedef struct +{ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + SHA2CC26X1_HWAttrs sha2HWAttrs; +#elif ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)) + SHA2CC26X2_HWAttrs sha2HWAttrs; +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + SHA2LPF3SW_HWAttrs sha2HWAttrs; +#endif +} ANSIX936KDFXX_HWAttrs; + +/*! + * @brief ANSIX936KDFXX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + SHA2_Config sha2Config; + SHA2_Handle sha2Handle; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + SHA2CC26X1_Object sha2Object; +#elif ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)) + SHA2CC26X2_Object sha2Object; +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + SHA2LPF3SW_Object sha2Object; +#endif + bool isOpen; +} ANSIX936KDFXX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ansix936kdf_ANSIX936KDFXX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/apps/Button.c b/simplelink_lpf2/source/ti/drivers/apps/Button.c new file mode 100644 index 00000000..0bcf2ea3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/apps/Button.c @@ -0,0 +1,500 @@ +/* + * Copyright (c) 2016-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== Button.c ======== + */ + +#include +#include + +#include +#include +#include + +/* Default Button_Params parameters structure */ +const Button_Params Button_defaultParams = { + 5, /* 5 ms is the debounce timer value */ + 2000, /* 2 seconds long press duration */ + 200, /* 200 ms double key press detection timeout */ + 0xFF /* button subscribed for all callbacks */ +}; + +extern Button_Config Button_config[]; + +/* Local functions */ + +/* + * ======== ticksToMs ======== + * Convert system ticks to milliseconds(ms). If the value cannot be represented + * with 32 bits, ~0 is returned. + */ +static uint32_t ticksToMs(uint32_t ticks) +{ + uint64_t ms = (ticks * ClockP_getSystemTickPeriod()) / 1000; + + if ((uint64_t)ms > (uint32_t)ms) + { + return ((uint32_t)~0); + } + else + { + return ((uint32_t)ms); + } +} + +/* + * ======== timediff ======== + * Calculates time difference between input system tick and current system + * tick value. If more than 32 bits of ticks have passed, this function is + * unreliable. + */ +static uint32_t timediff(uint32_t startTick) +{ + uint32_t currentTick = ClockP_getSystemTicks(); + + if (currentTick > startTick) + { + return (currentTick - startTick); + } + else + { + /* System tick value overflowed */ + return (currentTick + ((uint32_t)(~0) - startTick)); + } +} + +/* + * ======== msToTicks ======== + * Convert milliseconds to system ticks + */ +static uint32_t msToTicks(uint32_t ms) +{ + if (ms == 0) + { + return 0; + } + + uint32_t ticks = (ms * 1000) / ClockP_getSystemTickPeriod(); + + /* If ticks is 0, return 1 (the smallest representable value) */ + return ticks ? ticks : 1; +} + +/* + * ======== Button_close ======== + * Closes an instance of a Button + */ +void Button_close(Button_Handle handle) +{ + Button_Object *obj = (Button_Object *)(handle->object); + Button_HWAttrs *hw = (Button_HWAttrs *)handle->hwAttrs; + + GPIO_resetConfig(hw->gpioIndex); + + ClockP_stop(obj->clockHandle); + ClockP_delete(obj->clockHandle); + obj->clockHandle = NULL; +} + +/* + * ======== Button_gpioCallbackFxn ======== + * Callback function for the button interrupts + */ +void Button_gpioCallbackFxn(uint_least8_t index) +{ + /* Handle GPIO interrupt */ + uint_least8_t i; + + for (i = 0; i < Button_count; i++) + { + Button_Object *obj = (Button_Object *)Button_config[i].object; + Button_HWAttrs *hw = (Button_HWAttrs *)Button_config[i].hwAttrs; + if (hw->gpioIndex == index) + { + ClockP_setTimeout(obj->clockHandle, obj->debounceDuration); + ClockP_start(obj->clockHandle); + + switch (obj->buttonStateVariables.state) + { + case Button_PRESSING: + obj->buttonStateVariables.state = Button_RELEASING; + break; + case Button_PRESSED: + case Button_LONGPRESSING: + obj->buttonStateVariables.state = Button_RELEASING; + break; + case Button_LONGPRESSED: + obj->buttonStateVariables.state = Button_RELEASING_LONG; + break; + case Button_RELEASED: + obj->buttonStateVariables.state = Button_PRESSING; + break; + case Button_DBLPRESS_DETECTION: + obj->buttonStateVariables.state = Button_DBLPRESSING; + break; + case Button_DBLPRESSED: + obj->buttonStateVariables.state = Button_RELEASING_DBLPRESSED; + break; + /* + * Any other case, mark the button as pressed. + * Typically we should not come here. + */ + default: + obj->buttonStateVariables.state = Button_PRESSING; + break; + } + /* Disable the interrupt until the debounce timer expires */ + GPIO_disableInt(index); + break; + } + } +} + +/* + * ======== Button_init ======== + */ +void Button_init(void) +{ + /* Initialize GPIO driver if it wasn't already */ + GPIO_init(); +} + +/* + * ======== Button_clockTimeoutHandler ======== + * Timeout handler for the clock timeouts + */ +static void Button_clockTimeoutHandler(uintptr_t arg) +{ + Button_Object *obj; + Button_HWAttrs *hw; + Button_Handle buttonHandle; + Button_EventMask buttonEvents = 0; + + buttonHandle = (Button_Handle)arg; + obj = (Button_Object *)buttonHandle->object; + hw = (Button_HWAttrs *)buttonHandle->hwAttrs; + + if (GPIO_read(hw->gpioIndex) == hw->pullMode) + { + /* + * Getting a debounce duration timeout callback. The button is + * currently in unpressed (pull) state. + */ + switch (obj->buttonStateVariables.state) + { + case Button_RELEASING: + if (obj->buttonEventMask & Button_EV_DOUBLECLICKED) + { + /* Set clock to detect a double press */ + obj->buttonStateVariables.state = Button_DBLPRESS_DETECTION; + ClockP_setTimeout(obj->clockHandle, obj->doublePressDetectiontimeout - obj->debounceDuration); + ClockP_start(obj->clockHandle); + } + else + { + obj->buttonStateVariables.lastPressedDuration = timediff( + obj->buttonStateVariables.pressedStartTime); + obj->buttonStateVariables.state = Button_RELEASED; + if (obj->buttonEventMask & Button_EV_RELEASED) + { + buttonEvents |= Button_EV_RELEASED; + } + if (obj->buttonEventMask & Button_EV_CLICKED) + { + buttonEvents |= Button_EV_CLICKED; + } + } + break; + + case Button_DBLPRESS_DETECTION: + obj->buttonStateVariables.lastPressedDuration = timediff(obj->buttonStateVariables.pressedStartTime); + if (obj->buttonEventMask & Button_EV_RELEASED) + { + buttonEvents |= Button_EV_RELEASED; + } + if (obj->buttonEventMask & Button_EV_CLICKED) + { + buttonEvents |= Button_EV_CLICKED; + } + obj->buttonStateVariables.state = Button_RELEASED; + break; + + case Button_RELEASING_LONG: + obj->buttonStateVariables.lastPressedDuration = timediff(obj->buttonStateVariables.pressedStartTime); + if (obj->buttonEventMask & Button_EV_LONGCLICKED) + { + buttonEvents |= Button_EV_LONGCLICKED; + } + if (obj->buttonEventMask & Button_EV_RELEASED) + { + buttonEvents |= Button_EV_RELEASED; + } + obj->buttonStateVariables.state = Button_RELEASED; + break; + + case Button_RELEASING_DBLPRESSED: + obj->buttonStateVariables.state = Button_RELEASED; + if (obj->buttonEventMask & Button_EV_RELEASED) + { + buttonEvents |= Button_EV_RELEASED; + } + break; + + case Button_PRESSING: + case Button_DBLPRESSING: + case Button_LONGPRESSING: + /* + * Button was pressed and released within debounce time + * Does not count. + */ + obj->buttonStateVariables.state = Button_RELEASED; + break; + + /* + * Any other case, mark the button as pressed. + * Typically we should not come here. + */ + default: + obj->buttonStateVariables.state = Button_RELEASED; + break; + } + if (hw->pullMode == Button_PULL_DOWN) + { + GPIO_setInterruptConfig(hw->gpioIndex, GPIO_CFG_IN_INT_RISING | GPIO_CFG_INT_ENABLE); + } + else if (hw->pullMode == Button_PULL_UP) + { + GPIO_setInterruptConfig(hw->gpioIndex, GPIO_CFG_IN_INT_FALLING | GPIO_CFG_INT_ENABLE); + } + } + /* + * Getting a debounce duration timeout callback. The button is currently + * pressed. + */ + else + { + switch (obj->buttonStateVariables.state) + { + case Button_PRESSING: + /* This is a debounced press */ + obj->buttonStateVariables.pressedStartTime = ClockP_getSystemTicks(); + if (obj->buttonEventMask & Button_EV_PRESSED) + { + buttonEvents |= Button_EV_PRESSED; + } + /* Start countdown if interest in long-press */ + if (obj->buttonEventMask & (Button_EV_LONGPRESSED | Button_EV_LONGCLICKED)) + { + obj->buttonStateVariables.state = Button_LONGPRESSING; + ClockP_setTimeout(obj->clockHandle, obj->longPressDuration - obj->debounceDuration); + ClockP_start(obj->clockHandle); + } + else + { + obj->buttonStateVariables.state = Button_PRESSED; + } + break; + + case Button_DBLPRESSING: + /* This is a debounced press (this is considered as double click) */ + if (obj->buttonEventMask & Button_EV_DOUBLECLICKED) + { + buttonEvents |= Button_EV_DOUBLECLICKED; + } + obj->buttonStateVariables.state = Button_DBLPRESSED; + break; + + case Button_LONGPRESSING: + obj->buttonStateVariables.state = Button_LONGPRESSED; + if (obj->buttonEventMask & Button_EV_LONGPRESSED) + { + buttonEvents |= Button_EV_LONGPRESSED; + } + break; + + case Button_RELEASING: + case Button_RELEASING_LONG: + case Button_RELEASING_DBLPRESSED: + /* + * We're releasing, but isn't released after debounce. + * Start count down again if interest in long-press + */ + if (obj->buttonEventMask & (Button_EV_LONGPRESSED | Button_EV_LONGCLICKED)) + { + obj->buttonStateVariables.state = Button_LONGPRESSING; + ClockP_setTimeout(obj->clockHandle, obj->longPressDuration - obj->debounceDuration); + ClockP_start(obj->clockHandle); + obj->buttonStateVariables.state = Button_LONGPRESSING; + } + else + { + obj->buttonStateVariables.state = Button_PRESSED; + } + break; + + /* + * Any other case, mark the button as pressed. + * Typically we should not come here + */ + default: + obj->buttonStateVariables.state = Button_PRESSED; + break; + } + if (hw->pullMode == Button_PULL_DOWN) + { + GPIO_setInterruptConfig(hw->gpioIndex, GPIO_CFG_IN_INT_FALLING | GPIO_CFG_INT_ENABLE); + } + else if (hw->pullMode == Button_PULL_UP) + { + GPIO_setInterruptConfig(hw->gpioIndex, GPIO_CFG_IN_INT_RISING | GPIO_CFG_INT_ENABLE); + } + } + if ((buttonEvents != 0) && (obj->buttonCallback != NULL)) + { + obj->buttonCallback(buttonHandle, buttonEvents); + } +} + +/* + * ======== Button_open ======== + * Open a Button instance + */ +Button_Handle Button_open(uint_least8_t buttonIndex, Button_Params *params) +{ + Button_Params localParams; + Button_Handle handle; + Button_Object *obj; + Button_HWAttrs *hw; + GPIO_PinConfig pinConfig; + ClockP_Params clockParams; + + /* + * This sets the init state of the button + * buttonIndex cannot be greater than total ButtonCount + */ + if (buttonIndex >= Button_count) + { + return NULL; + } + + /* If params is null then use the default params */ + if (params == NULL) + { + /* + * Make a local copy of default params to pass, to avoid casting away + * const on Button_defaultParams + */ + localParams = Button_defaultParams; + params = &localParams; + } + + /* Get instance state structure */ + handle = (Button_Handle)&Button_config[buttonIndex]; + obj = (Button_Object *)(Button_config[buttonIndex].object); + hw = (Button_HWAttrs *)(Button_config[buttonIndex].hwAttrs); + + /* Set internal variables */ + obj->debounceDuration = msToTicks(params->debounceDuration); + obj->longPressDuration = msToTicks(params->longPressDuration); + obj->doublePressDetectiontimeout = msToTicks(params->doublePressDetectiontimeout); + obj->buttonCallback = params->buttonCallback; + obj->buttonEventMask = params->buttonEventMask; + + /* If instance already has a clock then it is already open */ + if (obj->clockHandle != NULL) + { + return NULL; + } + + /* Create one shot clock for handling debounce */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; /* Indicates a one shot clock */ + clockParams.startFlag = false; + clockParams.arg = (uintptr_t)handle; + obj->clockHandle = ClockP_create(Button_clockTimeoutHandler, 0, &clockParams); + if (NULL == obj->clockHandle) + { + return NULL; + } + + /* Enable interrupt by default */ + pinConfig = GPIO_CFG_INT_ENABLE; + pinConfig |= hw->pullMode == Button_PULL_DOWN ? GPIO_CFG_IN_INT_RISING : GPIO_CFG_IN_INT_FALLING; + + /* Configure input mode with or without pull */ + if (hw->internalPullEnabled) + { + pinConfig |= hw->pullMode == Button_PULL_DOWN ? GPIO_CFG_IN_PD : GPIO_CFG_IN_PU; + } + else + { + pinConfig |= GPIO_CFG_IN_NOPULL; + } + + /* Set callback first in case we have a pending interrupt */ + GPIO_setCallback(hw->gpioIndex, &Button_gpioCallbackFxn); + GPIO_setConfig(hw->gpioIndex, pinConfig); + + return handle; +} + +/* + * ======== Button_Params_init ======== + * Initialize a Button_Params struct to default settings. + */ +void Button_Params_init(Button_Params *params) +{ + *params = Button_defaultParams; +} + +/* + * ======== Button_setCallback ======== + * Set the callback for the buttons. + */ +void Button_setCallback(Button_Handle handle, Button_Callback buttonCallback) +{ + Button_Object *obj = (Button_Object *)handle->object; + + obj->buttonCallback = buttonCallback; +} + +/* + * ======== Button_getLastPressedDuration ======== + * Return the get last pressed duration + */ +extern uint32_t Button_getLastPressedDuration(Button_Handle handle) +{ + Button_Object *obj = (Button_Object *)handle->object; + uint32_t ticks = obj->buttonStateVariables.lastPressedDuration; + return ticksToMs(ticks); +} diff --git a/simplelink_lpf2/source/ti/drivers/apps/Button.h b/simplelink_lpf2/source/ti/drivers/apps/Button.h new file mode 100644 index 00000000..b75117e4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/apps/Button.h @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2016-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!*************************************************************************** + * @file Button.h + * + * @brief Button driver + * + * @anchor ti_drivers_Button_Synopsis + * # Synopsis # + * + * @code + * #include + * + * int main(void) + * { + * Button_Params params; + * Button_Handle handle; + * + * Button_Params_init(¶ms); + * + * handle = Button_open(CONFIG_BUTTON0, buttonCallbackFxn, ¶ms); + * + * ... + * } + * + * void buttonCallbackFxn(Button_Handle handle, Button_EventMask events) + * { + * if (events & Button_EV_CLICKED) + * { + * // Received a click, handle app condition 0 etc + * handleAppCond(0); + * } + * if (events & Button_EV_LONGCLICKED) + * { + * // Long press, handle app condition 1 etc + * handleAppCond(1); + * } + * ... + * } + * @endcode + * + * @anchor ti_drivers_Button_Examples + * ## Examples # + * + * * @ref ti_drivers_Button_Examples_config "Generic Configuration" + * + * ## Overview # + * + * The Button driver simplifies interfacing push buttons. For example, push + * buttons on LaunchPads, BoosterPacks, or custom boards may easily be managed + * via the Button API. A given button instance may subscribe to one or several + * #Button_Events. When a subscribed event occurs, the user will receive a + * callback with the handle of the button and the event(s) that occured. + * + * ## User requirements # + * Buttons use the @ref GPIO.h interface for interfacing with hardware, so a + * #GPIO_PinConfig array must exist and contain a config for the button pin. + * The user must statically allocate a #Button_Config array called + * Button_config. Each physical button should map to an index in + * Button_config. + * + * ## Defining #Button_Config, #Button_Object and #Button_HWAttrs # + * Each structure must be defined by the application. The following + * example is for a MSP432 in which two buttons are setup. + * The following declarations are placed in "ti_drivers_config.h" + * and "ti_drivers_config.c" respectively. How the GPIO configs are defined + * are detailed in the next example. + * + * @anchor ti_drivers_Button_Examples_config + * + * "ti_drivers_config.h" + * @code + * #define CONFIG_BUTTON_0 0 //Button number 1 + * #define CONFIG_BUTTON_1 1 //Button number 2 + * @endcode + * + * "ti_drivers_config.c" + * @code + * #include + * + * Button_Object Button_object[2]; + * + * const Button_HWAttrs Button_hwAttrs[2] = { + * { + * .gpioIndex = CONFIG_S1, + * }, + * { + * .gpioIndex = CONFIG_S2, + * } + * }; + * + * const Button_Config Button_config[2] = { + * { + * .hwAttrs = &Button_hwAttrs[0], + * .object = &Button_object[0], + * }, + * { + * .hwAttrs = &Button_hwAttrs[1], + * .object = &Button_object[1], + * }, + * }; + * @endcode + * + * ##Setting up GPIO configurations # + * + * The following example is for a MSP432. + * We are showing interfacing of two push buttons. Each need a GPIO pin. The + * following definitions are in "ti_drivers_config.h" and + * "ti_drivers_config.c" respectively. This example uses GPIO pins 1.1 and + * 1.4. The other GPIO configuration structures must exist, see @ref GPIO.h. + * + * "ti_drivers_config.h" + * @code + * #define CONFIG_S1 0 + * #define CONFIG_S2 1 + * @endcode + * + * "ti_drivers_config.c" + * @code + * #include + * GPIO_PinConfig gpioPinConfigs[] = { + * GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, + * } + * + * @endcode + ****************************************************************************** + */ +#ifndef ti_drivers_Button__include +#define ti_drivers_Button__include + +#include +#include + +/* Driver Header files */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of user defined Button configurations */ +extern const uint_least8_t Button_count; + +/*! + * @brief Button configuration + * + * Each #Button_Config represents a single physical button. It contains + * pointers to the button's #Button_HWAttrs and #Button_Object. The user must + * statically allocate all of these structures. + */ +typedef struct Button_Config +{ + /*! Pointer to a #Button_Object struct */ + void *object; + + /*! Pointer to a #Button_HWAttrs structure */ + void const *hwAttrs; +} Button_Config; + +/*! + * @brief A handle that is returned from a Button_open() call. + * + * User will use this handle to interact with a given button instance. + */ +typedef struct Button_Config *Button_Handle; + +/*! + * @brief Button State + * @private + * + * This enumeration describes whether the button is pressed or released etc. + * This is for internal state machine handling. + */ +typedef enum Button_State +{ + /*! Edge detected, debouncing */ + Button_PRESSING = 1, + /*! Press verified, not detecting longpress */ + Button_PRESSED = 2, + /*! Press verified, waiting for longpress timeout. */ + Button_LONGPRESSING = 3, + /*! Longpress verified, waiting for neg-edge */ + Button_LONGPRESSED = 4, + /*! Neg-edge received, debouncing */ + Button_RELEASING = 5, + /*! Neg-edge received after long-press, debouncing. */ + Button_RELEASING_LONG = 6, + /*! Button release verified. */ + Button_RELEASED = 7, + /*! EDGE detected doublepress */ + Button_DBLPRESS_DETECTION = 8, + /*! EDGE detected doublepress */ + Button_DBLPRESSING = 9, + /*! DOUBLE PRESS verified, waiting for neg edge */ + Button_DBLPRESSED = 10, + /*! DOUBLE PRESS verified, waiting for neg edge k*/ + Button_RELEASING_DBLPRESSED = 11 +} Button_State; + +/*! + * @brief Button event flags + * + * The event flags can be used by the user to subscribe to specific kinds of + * button actions and by the driver to signal which event caused a callback. + */ +typedef enum Button_Events +{ + /*! Button pressed down, may or may not subsequently have been released */ + Button_EV_PRESSED = 0x01, + /*! Button held down for more than tLongpress (ms) */ + Button_EV_LONGPRESSED = 0x02, + /*! Button released after press or longpress */ + Button_EV_RELEASED = 0x04, + /*! Button was pressed and released, but was not a long press */ + Button_EV_CLICKED = 0x08, + /*! + * Button was pressed and released, and held for longer than + * longPressDuration (ms) + */ + Button_EV_LONGCLICKED = 0x10, + /*! Button was pressed when double click detection was active */ + Button_EV_DOUBLECLICKED = 0x20, +} Button_Events; + +/*! @brief Event subscription and notification mask type */ +typedef uint8_t Button_EventMask; + +/*! + * @brief A handler to receive button callbacks. + */ +typedef void (*Button_Callback)(Button_Handle buttonHandle, Button_EventMask buttonEvents); + +/*! + * @brief Button Pull settings + * + * This enumeration defines whether the button is active low (PULL_UP) or + * active high (PULL_DOWN) and is used to control internal logic. + */ +typedef enum Button_Pull +{ + /* NOTE: DO NOT change the values of DOWN/UP from (0,1) */ + Button_PULL_DOWN = 0, /*!< Button is PULLED DOWN. */ + Button_PULL_UP = 1, /*!< Button is PULLED UP. */ +} Button_Pull; + +/*! + * @brief Hardware specific settings for a button + * + * This structure should be defined and provided by the application. + */ +typedef struct Button_HWAttrs +{ + /*! GPIO configuration index. */ + uint_least8_t gpioIndex; + + /*! Whether the button is active high or active low. */ + Button_Pull pullMode; + + /*! True/False whether the pullup on the GPIO pin should be enabled */ + uint32_t internalPullEnabled; +} Button_HWAttrs; + +/*! + * @brief Button State Variables + * @private + * + * Each button instance needs set of variables to monitor its state. + * We group these variables under the structure Button_State. + * + * @sa Button_Params_init() + */ +typedef struct Button_StateVariables +{ + /*! Button state */ + Button_State state; + /*! Button pressed start time in milliseconds(ms) */ + uint32_t pressedStartTime; + /*! Button pressed duration (ms) */ + uint32_t lastPressedDuration; +} Button_StateVariables; + +/*! + * @brief Internal to Button module. Members should not be accessed + * by the application. + */ +typedef struct Button_Object +{ + /*! Handle to clock used for timing */ + ClockP_Handle clockHandle; + + /*! State variables for handling the debounce state machine */ + Button_StateVariables buttonStateVariables; + + /*! Event subscription mask for the button */ + Button_EventMask buttonEventMask; + + /*! Callback function for the button */ + Button_Callback buttonCallback; + + /*! Debounce duration for the button in milliseconds(ms) */ + uint32_t debounceDuration; + + /*! Long press duration is milliseconds(ms) */ + uint32_t longPressDuration; + + /*! Double press detection timeout is milliseconds(ms) */ + uint32_t doublePressDetectiontimeout; +} Button_Object; + +/*! + * @brief Button Parameters + * + * Button parameters are used with the Button_open() call. Default values for + * these parameters are set using Button_Params_init(). + * + * @sa Button_Params_init() + */ +typedef struct Button_Params +{ + /*! Debounce duration for the button in milliseconds(ms) */ + uint32_t debounceDuration; + + /*! Long press duration is milliseconds(ms) */ + uint32_t longPressDuration; + + /*! Double press detection timeout is milliseconds(ms) */ + uint32_t doublePressDetectiontimeout; + + /*! Event subscription mask for the button */ + Button_EventMask buttonEventMask; + + /*! A #Button_Callback that is called when a masked event occurs. */ + Button_Callback buttonCallback; +} Button_Params; + +/*! + * @brief Function to close a Button specified by the #Button_Handle + * + * @pre Button_open() had to be called first. + * + * @param[in] handle A #Button_Handle returned from Button_open() call + * + * @return True on success or false upon failure. + */ +extern void Button_close(Button_Handle handle); + +/*! + * @brief Function to initialize Button driver. + */ +extern void Button_init(void); + +/*! + * @brief Function to open a given Button + * + * Function to open a button instance corresponding to a #Button_Config in the + * Button_config array. The GPIO configurations must exist prior to calling + * this function. The #Button_Params may be used to specify runtime parameters. + * + * @pre Button_init() has to be called first + * + * @param[in] buttonIndex Logical button number indexed into + * the Button_config table + * + * @param[in] *params A pointer to #Button_Params structure. If NULL, + * it will use default values. + * + * @return A #Button_Handle on success, or a NULL on failure. + * + * @sa Button_init() + * @sa Button_Params_init() + * @sa Button_close() + */ +extern Button_Handle Button_open(uint_least8_t buttonIndex, Button_Params *params); + +/*! + * @brief Function to initialize a #Button_Params struct to its defaults + * + * @param[in] params A pointer to a #Button_Params structure that will be + * initialized. + * + * Default values + * ------------------------------------------------------------------ + * parameter | value | description | unit + * -----------------|--------------|--------------------------|------------ + * debounceDuration | 10 | debounce duration | ms + * longPressDuration| 2000 | long press duration | ms + * buttonEventMask | 0xFF | subscribed to all events | NA + */ +extern void Button_Params_init(Button_Params *params); + +/*! + * @brief Function to return the lastPressedDuration (valid only for short + * press, long press) + * + * The API returns last pressed duration and it is valid only for shortpress, + * longpress. If this API is called after receiving an event click or long + * click then the API returns the press duration which is time delta between + * the press and release of the button. + * @note This API call is only valid after a click or long click and not after + * a double click. + * + * @param[in] handle Pointer to the #Button_Handle of the desired button. + * + * @return time duration in milliseconds. + * + */ +extern uint32_t Button_getLastPressedDuration(Button_Handle handle); + +/*! + * @brief Function to set callback function for the button instance + * + * @param[in] handle A #Button_Handle returned from Button_open() + * + * @param[in] buttonCallback button callback function + * + */ +extern void Button_setCallback(Button_Handle handle, Button_Callback buttonCallback); + +/*! + * @brief This is the GPIO interrupt callback function which is called on a + * button press or release. This is internally used by button module. + * + * This function is internally used by button module for receiving the GPIO + * interrupt callbacks. This is exposed to the application for wake up cases. + * In some of the MCUs, when in LPDS(Low power deep sleep) the GPIO interrupt + * is consumed for wake up, and in order to make the button module work the + * the application has to call this API with the index of the GPIO pin which + * actually was the reason for the wake up. + * + * @param[in] index Index of the GPIO for which the button press has to be + * detected. This is an index in #GPIO_PinConfig array. + */ +void Button_gpioCallbackFxn(uint_least8_t index); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_Button__include */ diff --git a/simplelink_lpf2/source/ti/drivers/apps/LED.c b/simplelink_lpf2/source/ti/drivers/apps/LED.c new file mode 100644 index 00000000..10818d81 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/apps/LED.c @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2016-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== LED.c ======== + */ + +/* Drivers */ +#include +#include +#include + +/* Module Header */ +#include + +#define LED_PWMPERIOD_1MS 1000U /* Default PWM period is 1 ms*/ + +/* Default LED parameters structure */ +const LED_Params LED_defaultParams = { + .pwmPeriod = LED_PWMPERIOD_1MS, /* Default PWM period is 1 ms*/ + .brightness = LED_BRIGHTNESS_MAX, /* Start at max brightness*/ + .setState = LED_STATE_OFF, /* Set LED state to OFF*/ + .blinkPeriod = 0 /* No blinking*/ +}; + +extern LED_Config LED_config[]; + +/* Number of user defined LED configs */ +extern const uint_least8_t LED_count; + +/* Local functions: */ + +static void clockTimeoutHandler(uintptr_t arg); +static uint32_t msToTicks(uint32_t ms); + +/* + * ======== clockTimeoutHandler ======== + * Called when blinker clock times out + */ +static void clockTimeoutHandler(uintptr_t arg) +{ + LED_Object *obj = ((LED_Handle)arg)->object; + ClockP_setTimeout(obj->clockHandle, msToTicks(obj->togglePeriod)); + ClockP_start(obj->clockHandle); + LED_toggle((LED_Handle)arg); + + /* Handle blink counting */ + if (obj->blinkCount != LED_BLINK_FOREVER && obj->blinkCount != 0) + { + obj->blinkCount--; + if (obj->blinkCount == 0) + { + /* Hit the requested number of blinks */ + LED_stopBlinking((LED_Handle)arg); + } + } +} + +/* + * ======== msToTicks ======== + * Convert milliseconds to system ticks. + * If passed zero, returns zero. If passed a ms value that converts to less + * than one system tick, returns one. + */ +static uint32_t msToTicks(uint32_t ms) +{ + uint32_t ticks; + + if (ms == 0) + { + return (0); + } + + ticks = (ms * 1000) / ClockP_getSystemTickPeriod(); + if (ticks == 0) + { + ticks = 1; + } + return (ticks); +} + +/* API functions: */ + +/* + * ======== LED_close ======== + * Closes an instance of a LED sensor. + */ +void LED_close(LED_Handle ledHandle) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + + LED_stopBlinking(ledHandle); + LED_setOff(ledHandle); + + /* Delete clock instance */ + ClockP_delete(obj->clockHandle); + obj->clockHandle = NULL; + + /* Close PWM handle if applicable */ + if (obj->pwmHandle != NULL) + { + PWM_close(obj->pwmHandle); + obj->pwmHandle = NULL; + } + + /* Set type to NONE to indicate the instance is closed */ + obj->ledType = LED_NONE; +} + +/* + * ======== LED_getState ======== + */ +LED_State LED_getState(LED_Handle ledHandle) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + + return (obj->state); +} + +/* + * ======== LED_init ======== + */ +void LED_init(void) +{ + /* + * Must NOT call GPIO or PWM init here as the weak symbol may be used. + * Init will be done at open time. + */ +} + +/* + * ======== LED_open ======== + * Sets up LED and returns LED_Handle + */ +LED_Handle LED_open(uint_least8_t ledIndex, LED_Params *params) +{ + LED_Handle ledHandle; + LED_Object *obj; + LED_HWAttrs *hw; + PWM_Params pwmParams; + ClockP_Params clockParams; + + ledHandle = (LED_Handle)(&LED_config[ledIndex]); + obj = (LED_Object *)(LED_config[ledIndex].object); + hw = (LED_HWAttrs *)(LED_config[ledIndex].hwAttrs); + + /* ledIndex cannot be more than number of available LEDs */ + if ((ledIndex >= LED_count)) + { + return (NULL); + } + + /* If params are NULL use defaults. */ + if (params == NULL) + { + params = (LED_Params *)&LED_defaultParams; + } + + /* If we already have a ledType then the instance is already open */ + if (obj->ledType != LED_NONE) + { + return (NULL); + } + + if (hw->type == LED_PWM_CONTROLLED) + { + obj->ledType = LED_PWM_CONTROLLED; + + /* PWM init must only be called if a PWM_config is strongly declared */ + PWM_init(); + + PWM_Params_init(&pwmParams); + pwmParams.periodValue = params->pwmPeriod; + pwmParams.dutyUnits = PWM_DUTY_US; + pwmParams.periodUnits = PWM_PERIOD_US; + pwmParams.dutyValue = 0; + + /* Open the PWM instance */ + obj->pwmHandle = PWM_open(hw->index, &pwmParams); + if (NULL == obj->pwmHandle) + { + return (NULL); + } + + /* Handle params and start conditions */ + PWM_start(obj->pwmHandle); + if (params->setState != LED_STATE_OFF) + { + PWM_setDuty(obj->pwmHandle, params->pwmPeriod * params->brightness / 100); + } + } + else + { + /* GPIO init must only be called if a GPIO_config is strongly declared */ + GPIO_init(); + /* Store gpio index so we don't have to potentially read from flash */ + obj->gpioIndex = hw->index; + obj->ledType = LED_GPIO_CONTROLLED; + } + + /* Create the clock instance */ + ClockP_Params_init(&clockParams); + clockParams.startFlag = false; + clockParams.arg = (uintptr_t)ledHandle; + clockParams.period = 0; // One shot clock + obj->clockHandle = ClockP_create(clockTimeoutHandler, 0, &clockParams); + if (NULL == obj->clockHandle) + { + /* Also close PWM if we opened one */ + if (obj->pwmHandle != NULL) + { + PWM_close(obj->pwmHandle); + } + return (NULL); + } + + /* Update Object fields*/ + obj->pwmPeriod = params->pwmPeriod; + obj->brightness = params->brightness; + + /* Set LED state, default is Off if setState is not modified by user*/ + switch (params->setState) + { + case LED_STATE_OFF: + LED_setOff(ledHandle); + break; + + case LED_STATE_ON: + LED_setOn(ledHandle, obj->brightness); + break; + + case LED_STATE_BLINKING: + LED_startBlinking(ledHandle, (params->blinkPeriod) / 2, LED_BLINK_FOREVER); + break; + + default: + /* Invalid setState value*/ + break; + } + + return (ledHandle); +} + +/* + * ======== LED_Params_init ======== + * Initialize a LED_Params struct to default settings. + */ +void LED_Params_init(LED_Params *params) +{ + *params = LED_defaultParams; +} + +/* + * ======== LED_setBrightnessLevel ======== + * Sets brightness level as requested. + */ +bool LED_setBrightnessLevel(LED_Handle ledHandle, uint8_t level) +{ + bool ret; + uint32_t duty = 0; + LED_Object *obj = (LED_Object *)(ledHandle->object); + + /* If in GPIO mode or a pwm handle was not provided, fail */ + if (NULL == obj->pwmHandle) + { + return (false); + } + + /* Report false if brightness request is more than maximum(100%) level */ + if (level > LED_BRIGHTNESS_MAX) + { + return (false); + } + + /* Calculate duty based on requested level and set that */ + duty = (obj->pwmPeriod * level) / 100; + if (PWM_setDuty(obj->pwmHandle, duty) == PWM_STATUS_SUCCESS) + { + ret = true; + obj->brightness = level; + } + else + { + ret = false; + } + + if (duty > 0) + { + obj->rawState = LED_STATE_ON; + } + else + { + obj->rawState = LED_STATE_OFF; + } + + return (ret); +} + +/* + * ======== LED_setOff ======== + * Turns Off a specified a LED sensor. + */ +bool LED_setOff(LED_Handle ledHandle) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + uint16_t level; + bool ret = true; + + obj->rawState = LED_STATE_OFF; + + if (obj->ledType == LED_GPIO_CONTROLLED) + { + GPIO_write(obj->gpioIndex, LED_OFF); + } + + /* For PWM LED, set brightness to zero + * Also, restoring brightness level which was there before turning it Off + * so that Toggle APIs can set same brightness while turning it On */ + else + { + level = obj->brightness; + ret = LED_setBrightnessLevel(ledHandle, LED_BRIGHTNESS_MIN); + obj->brightness = level; + } + + /* Set LED state + * If LED is blinking, which is a separate state(mix of ON + OFF), no need + * to change state; rawState contains the actual ON or OFF state*/ + if (obj->state != LED_STATE_BLINKING) + { + obj->state = LED_STATE_OFF; + } + + return (ret); +} + +/* + * ======== LED_setOn ======== + * Turns On a specified LED sensor. + */ +bool LED_setOn(LED_Handle ledHandle, uint8_t brightness) +{ + bool ret = true; + LED_Object *obj = (LED_Object *)(ledHandle->object); + + if (obj->ledType == LED_GPIO_CONTROLLED) + { + GPIO_write(obj->gpioIndex, LED_ON); + } + + /* For PWM LED, turn it On with requested level*/ + else + { + ret = LED_setBrightnessLevel(ledHandle, brightness); + } + + /* Set LED state(conditional) and rawState(always)*/ + if (ret == true) + { + if (obj->state != LED_STATE_BLINKING) + { + obj->state = LED_STATE_ON; + } + + obj->rawState = LED_STATE_ON; + } + + return (ret); +} + +/* + * ======== LED_startBlinking ======== + * Starts blinking an LED with specified period (in ms) and specified number of times + */ +void LED_startBlinking(LED_Handle ledHandle, uint16_t blinkPeriod, uint16_t blinkCount) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + + if (blinkPeriod == 0 || blinkCount == 0) + { + LED_stopBlinking(ledHandle); + } + else + { + /* + * Start the periodic clock with period = blinkperiod in ms units. If + * not blinking forever, we set the number of timeouts to be twice the + * number of requested blinks since one blink is two toggles. + */ + LED_setOff(ledHandle); + ClockP_stop(obj->clockHandle); + + if (blinkCount == LED_BLINK_FOREVER) + { + /* + * clockTimeoutHandler knows not to decrement blinkCount when it + * is set to LED_BLINK_FOREVER + */ + obj->blinkCount = LED_BLINK_FOREVER; + } + else + { + /* Don't overflow or set blinkCount to LED_BLINK_FOREVER */ + if (blinkCount > 0x7FFF) + { + blinkCount = 0x7FFF; + } + obj->blinkCount = 2 * blinkCount; + } + obj->togglePeriod = blinkPeriod / 2; + ClockP_setTimeout(obj->clockHandle, msToTicks(obj->togglePeriod)); + ClockP_start(obj->clockHandle); + obj->state = LED_STATE_BLINKING; + } +} + +/* + * ======== LED_stopBlinking ======== + * Stops blinking a led. + */ +void LED_stopBlinking(LED_Handle ledHandle) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + + if (obj->state == LED_STATE_BLINKING) + { + /* Stop the clock*/ + ClockP_stop(obj->clockHandle); + + /* After stopping blinking, sets LED Off, a default LED state*/ + LED_setOff(ledHandle); + obj->state = LED_STATE_OFF; + } + else + { + /* If LED is not blinking, no need to stop it, so ignore the request*/ + } +} + +/* + * ======== LED_toggle ======== + * Toggle a led. + */ +void LED_toggle(LED_Handle ledHandle) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + + if (obj->rawState == LED_STATE_ON) + { + LED_setOff(ledHandle); + } + else if (obj->rawState == LED_STATE_OFF) + { + LED_setOn(ledHandle, obj->brightness); + } +} + +/* + * ======== LED_write ======== + * Set the state of an LED instance + */ +void LED_write(LED_Handle ledHandle, bool value) +{ + LED_Object *obj = (LED_Object *)(ledHandle->object); + if (value) + { + LED_setOn(ledHandle, obj->brightness); + } + else + { + LED_setOff(ledHandle); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/apps/LED.h b/simplelink_lpf2/source/ti/drivers/apps/LED.h new file mode 100644 index 00000000..ed04a584 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/apps/LED.h @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2016-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file LED.h + * + * @brief LED driver + * + * The LED driver is provided for easy access to common LED functionality. + * All functionality can be replicated using the GPIO.h and PWM.h APIs. + * + * @anchor ti_drivers_LED_Synopsis + * # Synopsis # + * + * @code + * #include + * + * LED_Handle handle; + * LED_Params ledParams; + * + * // Assume our LED is configured to be a PWM LED + * LED_Params_init(&ledParams); + * ledHandle = LED_open(CONFIG_LED0, &ledParams); + * + * // Turn on, set brightness, and blink + * LED_setOn(handle, 80); + * LED_startBlinking(handle, 500, LED_BLINK_FOREVER); + * + * LED_setOff(handle); + * LED_close(handle); + * + * @endcode + * + * @anchor ti_drivers_LED_Examples + * ## Examples # + * + * * @ref ti_drivers_LED_Examples_config_array "Generic Configuration" + * * @ref ti_drivers_LED_Examples_gpio_config "GPIO Configuration" + * * @ref ti_drivers_LED_Examples_pwm_led "PWM Mode" + * + * # Operation # + * LED driver simplifies using an LED (may be GPIO or PWM controlled) + * available on board and supports following operations - + * + * 1. To Turn ON/OFF + * 2. Blink with requested delay, stop when requested + * 3. Vary brightness (can only be done to a PWM controlled LED) + * 4. Toggle + * + * There are also APIs to open and close an LED handle and also one to get + * current state of a LED. User can request to set a LED into particular state + * while opening itself i.e. to start blink as part of LED_open() call. + * + * LED_init() must be called before using LED_open(). + * + * ## Defining #LED_Config, #LED_Object and #LED_HWAttrs # + * To use the LED driver, an application has to indicate how many LEDs it + * wants to operate, of what type (PWM or GPIO controlled), and which GPIO or + * PWM to index for each LED. + * + * Each structure must be defined by the application. The following + * example is for an MSP432P401R platform in which four LEDs are available + * on board. + * The following declarations are placed in "ti_drivers_config.c". + * How the gpio indices are defined is detailed in the next section. + * + * ### LED_config structures # + * @anchor ti_drivers_LED_Examples_config_array + * "ti_drivers_config.c" + * @code + * #include + * + * LED_Object LED_object[4]; + * + * const LED_HWAttrs LED_hwAttrs[4] = { + * { + * .index = CONFIG_LED1, + * .type = LED_GPIO_CONTROLLED + * }, + * { + * .index = CONFIG_LED_RED, + * .type = LED_GPIO_CONTROLLED + * }, + * { + * .index = CONFIG_NA_GPIO_PWMLED, + * .type = LED_PWM_CONTROLLED + * }, + * { + * .index = CONFIG_NA_GPIO_PWMLED, + * .type = LED_PWM_CONTROLLED + * } + * }; + * + * const LED_Config LED_config[] = { + * { + * .object = &LED_object[0], + * .hwAttrs = &LED_hwAttrs[0], + * }, + * { + * .object = &LED_object[1], + * .hwAttrs = &LED_hwAttrs[1], + * }, + * { + * .object = &LED_object[2], + * .hwAttrs = &LED_hwAttrs[2], + * }, + * { + * .object = &LED_object[3], + * .hwAttrs = &LED_hwAttrs[3], + * } + * }; + * + * uint32_t LED_count = 4; + * + * @endcode + * + * ##Setting up a GPIO controlled LED # + * The following code snippet shows how a GPIO pin controlling an LED is + * configured. The index the user provides to LED_open() corresponds to an + * entry in the #GPIO_PinConfig array which will source the LED. It is the + * user's responsibility to ensure that the pin is configured properly in the + * pin array. Typically this means configuring the pin as an output. + * + * ### GPIO controlled LED # + * @anchor ti_drivers_LED_Examples_gpio_config + * + * The following definitions are in + * "ti_drivers_config.h" and "ti_drivers_config.c" respectively. This + * example uses GPIO pins 1.0 and 2.0 which control LED1 and RED LED on + * LaunchPad respectively. In addition to the structures shown below, the + * other GPIO configuration data must exist. See @ref GPIO.h. + * + * "ti_drivers_config.h" + * @code + * #define CONFIG_LED1 0 + * #define CONFIG_LED_RED 1 + * @endcode + * + * "ti_drivers_config.c" + * @code + * #include + * GPIO_PinConfig gpioPinConfigs[] = { + * GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + * } + * + * @endcode + * + * ## Configuring a PWM controlled LED # + * The LED driver allows for an LED to be driven by the PWM driver. This allows + * the user to set a brightness level in addition to the other LED features. + * The user must specify in the #LED_HWAttrs of each #LED_Config entry which + * #PWM_Config the LED instance is allowed to use. LED instances cannot share + * a PWM instance. + * + * The user may specify the period of the PWM signal in the #LED_Params passed + * to LED_open(). This is not to be confused with #LED_Params.blinkPeriod + * which specifies the default blink period. + * + * ### Opening a PWM LED # + * @anchor ti_drivers_LED_Examples_pwm_led + * + * We will borrow the 3rd LED_config entry from the + * @ref ti_drivers_LED_Examples_config_array + * + * In "ti_drivers_config.h" + * @code + * #define CONFIG_LED0 0 + * @endcode + * + * In application code: + * @code + * #include + * + * LED_Handle LEDHandle; + * LED_Params ledParams; + * + * LED_Params_init(&ledParams); + * ledParams.pwmPeriod = 100; // 0.1 ms period + * ledParams.blinkPeriod = 500; // LED will toggle twice a second + * ledParams.setState = LED_STATE_BLINKING; // Start LED blink on open + * ledHandle = LED_open(CONFIG_LED0, &ledParams); // Open the first LED_Config + * + * // Turn on at half brightness level + * LED_setOn(ledHandle, 50); + * @endcode + * + ******************************************************************************* + */ + +#ifndef ti_drivers_LED__include +#define ti_drivers_LED__include + +#include +#include + +/* Driver Header files */ +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED_BRIGHTNESS_MAX 100U /* Max brightness in % is 100%*/ +#define LED_BRIGHTNESS_MIN 0U /* Max brightness in % is 0%*/ + +#define LED_ON 1U +#define LED_OFF 0U + +#define LED_BLINK_FOREVER 0xFFFF + +/* Number of user defined LED configurations */ +extern const uint_least8_t LED_count; + +/*! + * @brief LED types based on control source + * + * A LED can be controlled by GPIO or PWM. Only a PWM controlled LED can + * be operated to show brightness variation. An unopened instance will be of + * type #LED_NONE. + */ +typedef enum +{ + LED_NONE = 0, + LED_GPIO_CONTROLLED, + LED_PWM_CONTROLLED +} LED_Type; + +/*! + * @brief LED State + * + * A LED can be in OFF, ON or BLINKING state + * + * State of particular LED may be tied with a warning/alert in system + * which a thread/task may want to know. + */ +typedef enum +{ + LED_STATE_OFF = 0, + LED_STATE_ON, + LED_STATE_BLINKING +} LED_State; + +/*! + * @brief LED configuration + * + * The LED_Config structure contains a set of pointers used to characterize + * the LED driver implementation. + * + * This structure needs to be defined and provided by the application and will + * be NULL terminated. + */ +typedef struct +{ + /*! Pointer to drivers internal data state object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} LED_Config; + +/*! + * @brief A handle that is returned from a LED_open() call. + */ +typedef LED_Config *LED_Handle; + +/*! + * @brief Hardware specific settings for a LED module. + * + * This structure should be defined and provided by the application. The + * index should be correspond to the desired pin in either the PWM or GPIO + * config tables depending on the requested #LED_Type. + */ +typedef struct +{ + uint_least8_t index; /*!< Index into GPIO or PWM config array */ + LED_Type type; /* + * .... + * + * // Initialize Attestation_PSA driver + * Attestation_PSA_init(); + * + * // A buffer of maximum allowed token size to store the generated token + * // Alternatively, application can obtain the size of token using Attestation_PSA_getTokenSize() + * // to dynamically allocate buffer of required size + * uint8_t token[ATTESTATION_PSA_MAX_TOKEN_SIZE]; + * + * // A buffer for nonce or challenge provided by the attestation service to prevent replay or re-use of token + * uint8_t nonce[32]; + * + * int_fast16_t status; + * size_t tokenLength; + * + * // Generate the token + * status = Attestation_PSA_getToken(&nonce[0], sizeof(nonce), &token[0], sizeof(token), &tokenLength); + * + * if (status != ATTESTATION_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * @endcode + * + */ + +#ifndef ti_drivers_attestation_Attestation_PSA__include +#define ti_drivers_attestation_Attestation_PSA__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Maximum attestation token size + * + * The maximum size of an attestation token that can be generated by the + * attestation service. Used to configure buffers for services that verify the + * produced tokens. + */ +#define ATTESTATION_PSA_MAX_TOKEN_SIZE (PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE) + +/*! + * @brief Successful status code. + * + * Functions return ATTESTATION_PSA_STATUS_SUCCESS if the function was executed + * successfully. + */ +#define ATTESTATION_PSA_STATUS_SUCCESS ((int_fast16_t)0) + +/*! + * @brief Generic error status code. + * + * Functions return ATTESTATION_PSA_STATUS_ERROR if the function was not executed + * successfully and no more pertinent error code could be returned. + */ +#define ATTESTATION_PSA_STATUS_ERROR ((int_fast16_t)-1) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * Attestation driver implementations may have hardware or software limitations on how + * many clients can simultaneously perform operations. This status code is returned + * if the mutual exclusion mechanism signals that an operation cannot currently be performed. + */ +#define ATTESTATION_PSA_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-2) + +/*! + * @brief Operation failed due to invalid inputs. + * + * Functions return ATTESTATION_PSA_STATUS_INVALID_INPUTS if input validation fails. + */ +#define ATTESTATION_PSA_STATUS_INVALID_INPUTS ((int_fast16_t)-3) + +/** + * @brief Get initial attestation token + * + * @param[in] auth_challenge Pointer to buffer where challenge input is + * stored. + * @param[in] challenge_size Size of challenge object in bytes. + * Must be 32, 48, or 64-bytes. + * @param[out] token_buf Pointer to the buffer where attestation token + * will be stored, with a maximum buffer size + * of ATTESTATION_PSA_MAX_TOKEN_SIZE. + * @param[in] token_buf_size Size of allocated buffer for token, in bytes. + * @param[out] token_size Size of the token that has been returned, in + * bytes. + * + * @retval #ATTESTATION_PSA_STATUS_SUCCESS The operation succeeded. + * @retval #ATTESTATION_PSA_STATUS_ERROR The operation failed. + * @retval #ATTESTATION_PSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #ATTESTATION_PSA_STATUS_INVALID_INPUTS Input validation failed. + */ +int_fast16_t Attestation_PSA_getToken(const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size); + +/** + * @brief Get the exact size of initial attestation token in bytes. + * + * Returns the size of the IAT token. It can be used if the caller + * dynamically allocates memory for the token buffer. + * + * @param[in] challenge_size Size of challenge object in bytes. + * Must be 32, 48, or 64-bytes. + * @param[out] token_size Size of the token in bytes, which is created by + * initial attestation service. + * + * @retval #ATTESTATION_PSA_STATUS_SUCCESS The operation succeeded. + * @retval #ATTESTATION_PSA_STATUS_ERROR The operation failed. + * @retval #ATTESTATION_PSA_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. + * Try again later. + * @retval #ATTESTATION_PSA_STATUS_INVALID_INPUTS Input validation failed. + */ +int_fast16_t Attestation_PSA_getTokenSize(size_t challenge_size, size_t *token_size); + +/*! + * @brief This function initializes the Attestation module. + * + * @pre This function must also be called before + * any other Attestation driver APIs. This function call does not modify any + * peripheral registers. + */ +void Attestation_PSA_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_attestation_Attestation_PSA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/attestation/Attestation_PSA_ns.c b/simplelink_lpf2/source/ti/drivers/attestation/Attestation_PSA_ns.c new file mode 100644 index 00000000..7c061641 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/attestation/Attestation_PSA_ns.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Static globals */ +static bool isInitialized = false; + +/* + * ======== Attestation_PSA_mapPSAToAttestationPSAStatus ======== + */ +static int_fast16_t Attestation_PSA_mapPSAToAttestationPSAStatus(psa_status_t psaStatus) +{ + int_fast16_t status = ATTESTATION_PSA_STATUS_ERROR; + + if (psaStatus == PSA_SUCCESS) + { + status = ATTESTATION_PSA_STATUS_SUCCESS; + } + else if (psaStatus == PSA_ERROR_INVALID_ARGUMENT) + { + status = ATTESTATION_PSA_STATUS_INVALID_INPUTS; + } + + return status; +} + +/* + * ======== Attestation_PSA_setup ======== + */ +static int_fast16_t Attestation_PSA_setup(void) +{ + int_fast16_t status = ATTESTATION_PSA_STATUS_SUCCESS; + + /* Set power dependency for SHA2 */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + /* Set power dependency for PKA for ECDSA driver */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(SemaphoreP_NO_WAIT) == false) + { + status = ATTESTATION_PSA_STATUS_RESOURCE_UNAVAILABLE; + } + + return status; +} + +/* + * ======== Attestation_PSA_cleanup ======== + */ +static void Attestation_PSA_cleanup(void) +{ + /* Release power dependencies */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); + (void)Power_releaseDependency(PowerCC26X2_PERIPH_PKA); + + CryptoPSACC26X4_releaseLock(); +} + +/* + * ======== Attestation_PSA_getToken ======== + */ +int_fast16_t Attestation_PSA_getToken(const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size) +{ + int_fast16_t status = ATTESTATION_PSA_STATUS_ERROR; + psa_status_t psaStatus; + + status = Attestation_PSA_setup(); + + if (status != ATTESTATION_PSA_STATUS_SUCCESS) + { + return status; + } + + if (token_buf_size > ATTESTATION_PSA_MAX_TOKEN_SIZE) + { + return ATTESTATION_PSA_STATUS_INVALID_INPUTS; + } + + psaStatus = psa_initial_attest_get_token(auth_challenge, challenge_size, token_buf, token_buf_size, token_size); + + Attestation_PSA_cleanup(); + + return Attestation_PSA_mapPSAToAttestationPSAStatus(psaStatus); +} + +/* + * ======== Attestation_PSA_getTokenSize ======== + */ +int_fast16_t Attestation_PSA_getTokenSize(size_t challenge_size, size_t *token_size) +{ + int_fast16_t status; + psa_status_t psaStatus; + + status = Attestation_PSA_setup(); + + if (status != ATTESTATION_PSA_STATUS_SUCCESS) + { + return status; + } + + psaStatus = psa_initial_attest_get_token_size(challenge_size, token_size); + + Attestation_PSA_cleanup(); + + return Attestation_PSA_mapPSAToAttestationPSAStatus(psaStatus); +} + +/* + * ======== Attestation_PSA_init ======== + */ +void Attestation_PSA_init(void) +{ + if (!isInitialized) + { + /* TRNG is required for ECDSA signature */ + TRNG_init(); + + /* Initialize CryptoPSA semaphores */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} diff --git a/simplelink_lpf2/source/ti/drivers/can/TCAN455X.c b/simplelink_lpf2/source/ti/drivers/can/TCAN455X.c new file mode 100644 index 00000000..ea37840a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/can/TCAN455X.c @@ -0,0 +1,1394 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== TCAN455X.c ======== + */ +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#if (defined(__IAR_SYSTEMS_ICC__) || defined(__TI_COMPILER_VERSION__)) + #include + #define BSWAP32 __rev +#elif defined(__GNUC__) + #define BSWAP32 __builtin_bswap32 +#else + #error Unsupported compiler +#endif + +#define TCAN455X_RESET_DELAY_US 800U /* Must be at least 700us */ + +#define TCAN455X_SPI_READ_OPCODE 0x41U +#define TCAN455X_SPI_WRITE_OPCODE 0x61U + +/* + * Counter for number of times Rx Ring buffer was full when there was a Rx + * message available in Rx FIFO0/1 resulting in a lost message. This can be used + * to fine tune the size of the Rx ring buffer when the CAN bus is under maximum + * load. + */ +static uint32_t rxRingBufFullCnt = 0U; + +static SemaphoreP_Struct tcanIRQSemaphore; +static SemaphoreP_Struct spiAccessSemaphore; +static TaskP_Params taskParams; +static TaskP_Struct tcanTask; + +static MCAN_TxBufElement txElem; +static MCAN_RxBufElement rxElem; + +extern const TCAN455X_Config TCAN455X_config; + +/* Default device-specific message RAM configuration: + * - Each standard filter element occupies 4-bytes. + * - Each extended filter element occupies 8-bytes. + * - Each Rx/Tx buffer occupies 72-bytes when CAN FD is enabled or 16-bytes + * for classic CAN. + * - Each Tx Event occupies 8-bytes. + */ +const CAN_MsgRamConfig TCAN455X_defaultMsgRamConfig = { + .stdFilterNum = 0U, + .extFilterNum = 0U, + .stdMsgIDFilterList = NULL, + .extMsgIDFilterList = NULL, + + .rxFifoNum[0U] = 18U, + .rxFifoNum[1U] = 0U, + .rxBufNum = 0U, + .txBufNum = 0U, + .txFifoQNum = 10U, + .txFifoQMode = 1U, /* Tx Queue mode */ + .txEventFifoNum = 4U, +}; + +static SPI_Handle TCAN455X_spiHandle; + +/* Forward declarations */ +static inline void TCAN455X_assertSPICSN(void); +static inline void TCAN455X_deassertSPICSN(void); +static void TCAN455X_startSPITransfer(uint8_t opcode, uint16_t addr, uint8_t numWords); +static void TCAN455X_doSPITransfer(SPI_Transaction *transaction); +static inline void TCAN455X_endSPITransfer(void); +static void TCAN455X_writeSPI(uint32_t data); +static uint32_t TCAN455X_readSPI(void); +static void TCAN455X_writeReg(uint16_t offset, uint32_t value); +static uint32_t TCAN455X_readReg(uint16_t offset); +static inline void TCAN455X_disableInterrupt(void); +static inline void TCAN455X_enableInterrupt(void); +static bool TCAN455X_isRxStructRingBufFull(CAN_Handle handle); +static void TCAN455X_handleRxFifo(CAN_Handle handle, uint32_t fifoNum); +static void TCAN455X_handleRxBuf(CAN_Handle handle); +static void TCAN455X_irqHandler(uint_least8_t index); +static inline int_fast16_t TCAN455X_initSPI(void); +static void TCAN455X_clearMsgRam(void); +static int_fast16_t TCAN455X_setBitRate(const CAN_Config *config, uint32_t canInputClkFreq); +static void TCAN455X_setInterruptEnable(uint32_t ie); +static void TCAN455X_clearInterrupt(uint32_t mask); +static void TCAN455X_modifyModeReg(uint32_t mask, uint32_t val); +static void TCAN455X_reset(void); +static int_fast16_t TCAN455X_init(const CAN_Config *config, + const CAN_MsgRamConfig *msgRamConfig, + const CAN_BitRateTimingRaw *bitTiming, + uint32_t tsPrescaler); +static void TCAN455X_enableLoopback(bool externalModeEnable); +static inline int_fast16_t TCAN455X_setExtTsPrescaler(uint32_t prescalar); +static void TCAN455X_taskFxn(void *arg); + +/* Definitions for extern functions defined in MCAN.h */ + +/* + * ======== MCAN_getMRAMOffset ======== + */ +uint32_t MCAN_getMRAMOffset(void) +{ + return TCAN455X_MRAM; +} + +/* + * ======== MCAN_writeReg ======== + */ +void MCAN_writeReg(uint32_t offset, uint32_t value) +{ + uint32_t addr = offset; + + if (addr < TCAN455X_MRAM) + { + addr += TCAN455X_MCAN; + } + + TCAN455X_writeReg((uint16_t)addr, value); +} + +/* + * ======== MCAN_writeMsgRam ======== + */ +void MCAN_writeMsgRam(uint32_t offset, const uint8_t *src, size_t numBytes) +{ + size_t bytesRemaining; + size_t bytesWritten = 0U; + size_t numWords = numBytes >> 2U; + uint32_t loopCnt; + uint32_t word; + + if (numBytes != 0U) + { + /* + * Check whether numBytes[1:0] is non-zero which means numBytes is a + * non-word multiple. + */ + if ((numBytes << 30U) != 0U) + { + /* Additional word write is required for remaining data bytes */ + TCAN455X_startSPITransfer(TCAN455X_SPI_WRITE_OPCODE, (uint16_t)offset, (uint8_t)(numWords + 1U)); + } + else + { + TCAN455X_startSPITransfer(TCAN455X_SPI_WRITE_OPCODE, (uint16_t)offset, (uint8_t)numWords); + } + + /* Write all the full words of source data */ + for (loopCnt = 0U; loopCnt < numWords; loopCnt++) + { + (void)memcpy(&word, &src[bytesWritten], sizeof(word)); + + TCAN455X_writeSPI(word); + bytesWritten += 4U; + } + + bytesRemaining = numBytes - bytesWritten; + + /* Create a full word out of any remaining source data bytes */ + if (bytesRemaining > 0U) + { + word = 0U; + (void)memcpy(&word, &src[bytesWritten], bytesRemaining); + + TCAN455X_writeSPI(word); + } + + TCAN455X_endSPITransfer(); + } +} + +/* + * ======== MCAN_readReg ======== + */ +uint32_t MCAN_readReg(uint32_t offset) +{ + uint32_t addr = offset; + + if (addr < TCAN455X_MRAM) + { + addr += TCAN455X_MCAN; + } + + return TCAN455X_readReg((uint16_t)addr); +} + +/* + * ======== MCAN_readMsgRam ======== + */ +void MCAN_readMsgRam(uint8_t *dst, uint32_t offset, size_t numBytes) +{ + size_t numWords = numBytes >> 2U; + SPI_Transaction xfer; + uint32_t loopCnt; + /* Save memory by reusing the Rx element data buffer which is guaranteed to + * be word-aligned. + */ + uint32_t *rxBuf = (uint32_t *)&rxElem.data[0]; + + /* Verify numBytes does not exceed the size of Rx element data buffer */ + if ((numBytes != 0U) && (numBytes <= sizeof(rxElem.data))) + { + /* + * Check whether numBytes[1:0] is non-zero which means numBytes is a + * non-word multiple. + */ + if ((numBytes << 30U) != 0U) + { + /* Additional word read is required for remaining data bytes */ + numWords++; + } + + TCAN455X_startSPITransfer(TCAN455X_SPI_READ_OPCODE, (uint16_t)offset, (uint8_t)numWords); + + xfer.txBuf = NULL; + xfer.rxBuf = rxBuf; + xfer.count = numWords << 2U; /* Number of 8-bit frames */ + + TCAN455X_doSPITransfer(&xfer); + + for (loopCnt = 0U; loopCnt < numWords; loopCnt++) + { + rxBuf[loopCnt] = BSWAP32(rxBuf[loopCnt]); + } + + (void)memcpy(&dst[0], &rxBuf[0], numBytes); + + TCAN455X_endSPITransfer(); + } +} + +/* + * ======== TCAN455X_assertSPICSN ======== + */ +static inline void TCAN455X_assertSPICSN(void) +{ + GPIO_write(TCAN455X_config.spiCSPin, 0U); +} + +/* + * ======== TCAN455X_deassertSPICSN ======== + */ +static inline void TCAN455X_deassertSPICSN(void) +{ + GPIO_write(TCAN455X_config.spiCSPin, 1U); +} + +/* + * ======== TCAN455X_doSPITransfer ======== + */ +static void TCAN455X_doSPITransfer(SPI_Transaction *transaction) +{ + const CAN_Config *config = &CAN_config[0]; + CAN_Handle handle = (CAN_Handle)config; + CAN_Object *object = config->object; + + if (!SPI_transfer(TCAN455X_spiHandle, transaction) || (transaction->status != SPI_TRANSFER_COMPLETED)) + { + if ((CAN_EVENT_SPI_XFER_ERROR & object->eventMask) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_SPI_XFER_ERROR, transaction->status, object->userArg); + } + } +} + +/* + * ======== TCAN455X_startSPITransfer ======== + */ +static void TCAN455X_startSPITransfer(uint8_t opcode, uint16_t addr, uint8_t numWords) +{ + SPI_Transaction xfer; + uint8_t hdr[4]; + + /* No need to check return value when waiting forever */ + (void)SemaphoreP_pend(&spiAccessSemaphore, SemaphoreP_WAIT_FOREVER); + + TCAN455X_assertSPICSN(); + + hdr[0] = opcode; + + /* Set 16-bit address */ + hdr[1] = (uint8_t)(addr >> 8U); + hdr[2] = (uint8_t)(addr); + + /* Set number of words */ + hdr[3] = numWords; + + xfer.txBuf = &hdr[0]; + xfer.rxBuf = NULL; + xfer.count = 4U; /* 1 word converted to 8-bit frames */ + + TCAN455X_doSPITransfer(&xfer); +} + +/* + * ======== TCAN455X_endSPITransfer ======== + */ +static inline void TCAN455X_endSPITransfer(void) +{ + TCAN455X_deassertSPICSN(); + + SemaphoreP_post(&spiAccessSemaphore); +} + +/* + * ======== TCAN455X_writeSPI ======== + */ +static void TCAN455X_writeSPI(uint32_t data) +{ + SPI_Transaction xfer; + uint32_t txData; + + /* Byte swap */ + txData = BSWAP32(data); + + xfer.txBuf = &txData; + xfer.rxBuf = NULL; + xfer.count = sizeof(txData); /* Number of 8-bit frames */ + + TCAN455X_doSPITransfer(&xfer); +} + +/* + * ======== TCAN455X_readSPI ======== + */ +static uint32_t TCAN455X_readSPI(void) +{ + SPI_Transaction xfer; + uint32_t data; + + xfer.txBuf = NULL; + xfer.rxBuf = &data; + xfer.count = sizeof(data); /* Number of 8-bit frames */ + + TCAN455X_doSPITransfer(&xfer); + + /* Byte swap */ + data = BSWAP32(data); + + return data; +} + +/* + * ======== TCAN455X_writeReg ======== + */ +static void TCAN455X_writeReg(uint16_t offset, uint32_t val) +{ + TCAN455X_startSPITransfer(TCAN455X_SPI_WRITE_OPCODE, offset, 1U); + TCAN455X_writeSPI(val); + TCAN455X_endSPITransfer(); +} + +/* + * ======== TCAN455X_readReg ======== + */ +static uint32_t TCAN455X_readReg(uint16_t offset) +{ + uint32_t data; + + TCAN455X_startSPITransfer(TCAN455X_SPI_READ_OPCODE, offset, 1U); + data = TCAN455X_readSPI(); + TCAN455X_endSPITransfer(); + + return data; +} + +/* + * ======== TCAN455X_disableInterrupt ======== + */ +static inline void TCAN455X_disableInterrupt(void) +{ + GPIO_disableInt(TCAN455X_config.interruptPin); +} + +/* + * ======== TCAN455X_enableInterrupt ======== + */ +static inline void TCAN455X_enableInterrupt(void) +{ + GPIO_enableInt(TCAN455X_config.interruptPin); +} + +/* + * ======== TCAN455X_isRxStructRingBufFull ======== + */ +static bool TCAN455X_isRxStructRingBufFull(CAN_Handle handle) +{ + CAN_Object *object = (CAN_Object *)handle->object; + bool isFull = StructRingBuf_isFull(&object->rxStructRingBuf); + + if (isFull) + { + rxRingBufFullCnt++; + + if ((CAN_EVENT_RX_RING_BUFFER_FULL & object->eventMask) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_RX_RING_BUFFER_FULL, rxRingBufFullCnt, object->userArg); + } + } + + return isFull; +} + +/* + * ======== TCAN455X_handleRxFifo ======== + */ +static void TCAN455X_handleRxFifo(CAN_Handle handle, uint32_t fifoNum) +{ + CAN_Object *object = (CAN_Object *)handle->object; + MCAN_RxFifoStatus fifoStatus = {0}; + + MCAN_getRxFifoStatus(fifoNum, &fifoStatus); + + if ((fifoStatus.fillLvl > 0U) && !TCAN455X_isRxStructRingBufFull(handle)) + { + MCAN_readRxMsg(MCAN_MEM_TYPE_FIFO, fifoNum, &rxElem); + /* Return value can be ignored since ring buffer is not full */ + (void)StructRingBuf_put(&object->rxStructRingBuf, &rxElem); + + fifoStatus.fillLvl--; + + while ((fifoStatus.fillLvl > 0U) && !TCAN455X_isRxStructRingBufFull(handle)) + { + MCAN_readRxMsg(MCAN_MEM_TYPE_FIFO, fifoNum, &rxElem); + /* Return value can be ignored since ring buffer is not full */ + (void)StructRingBuf_put(&object->rxStructRingBuf, &rxElem); + + fifoStatus.fillLvl--; + fifoStatus.getIdx++; + + /* Check for rollover */ + if (fifoStatus.getIdx >= object->rxFifoNum[fifoNum]) + { + fifoStatus.getIdx = 0U; + } + } + } + + /* Return value can be ignored since the inputs are known to be valid */ + (void)MCAN_setRxFifoAck(fifoNum, fifoStatus.getIdx); +} + +/* + * ======== TCAN455X_handleRxBuf ======== + */ +static void TCAN455X_handleRxBuf(CAN_Handle handle) +{ + CAN_Object *object = (CAN_Object *)handle->object; + MCAN_RxNewDataStatus clearNewDataStatus = {0U}; + MCAN_RxNewDataStatus newDataStatus; + uint32_t bufNum; + + MCAN_getNewDataStatus(&newDataStatus); + + /* Check for Rx messages in buffers 0-31 */ + if (newDataStatus.statusLow != 0U) + { + for (bufNum = 0U; bufNum < Math_MIN(object->rxBufNum, 32U); bufNum++) + { + if ((newDataStatus.statusLow & ((uint32_t)1U << bufNum)) != 0U) + { + if (!TCAN455X_isRxStructRingBufFull(handle)) + { + MCAN_readRxMsg(MCAN_MEM_TYPE_BUF, bufNum, &rxElem); + + (void)StructRingBuf_put(&object->rxStructRingBuf, &rxElem); + } + + clearNewDataStatus.statusLow |= ((uint32_t)1U << bufNum); + } + } + } + + if (object->rxBufNum > 32U) + { + /* Check for Rx messages in buffers 32-63 */ + if (newDataStatus.statusHigh != 0U) + { + for (bufNum = 0U; bufNum < Math_MIN((object->rxBufNum - 32U), 32U); bufNum++) + { + if ((newDataStatus.statusHigh & ((uint32_t)1U << bufNum)) != 0U) + { + if (!TCAN455X_isRxStructRingBufFull(handle)) + { + MCAN_readRxMsg(MCAN_MEM_TYPE_BUF, (bufNum + 32U), &rxElem); + + (void)StructRingBuf_put(&object->rxStructRingBuf, &rxElem); + } + + clearNewDataStatus.statusHigh |= ((uint32_t)1U << bufNum); + } + } + } + } + + MCAN_clearNewDataStatus(&clearNewDataStatus); +} + +/* + * ======== TCAN455X_irqHandler ======== + */ +static void TCAN455X_irqHandler(uint_least8_t index) +{ + (void)index; /* unused arg */ + + /* Since TCAN455X is controlled via SPI, IRQ handling must be deferred + * to a task to avoid delaying lower priority interrupts while waiting + * for SPI transactions. + */ + + /* Unblock task to handle the interrupt */ + SemaphoreP_post(&tcanIRQSemaphore); +} + +/* + * ======== TCAN455X_initSPI ======== + */ +static inline int_fast16_t TCAN455X_initSPI(void) +{ + int_fast16_t status = CAN_STATUS_SUCCESS; + SPI_Params spiParams; + + SPI_init(); + + if (TCAN455X_spiHandle == NULL) + { + /* Configure SPI as controller for TCAN455X */ + SPI_Params_init(&spiParams); + spiParams.bitRate = TCAN455X_config.spiBitRate; + spiParams.frameFormat = SPI_POL0_PHA0; + spiParams.mode = SPI_CONTROLLER; + spiParams.transferMode = SPI_MODE_BLOCKING; + + TCAN455X_spiHandle = SPI_open(TCAN455X_config.spiIndex, &spiParams); + } + + if (TCAN455X_spiHandle == NULL) + { + status = CAN_STATUS_ERROR; + } + else + { + /* Config GPIO for SW-controlled SPI CS */ + GPIO_setConfig(TCAN455X_config.spiCSPin, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_HIGH); + + /* Create binary semaphore for SPI resource access */ + if (SemaphoreP_constructBinary(&spiAccessSemaphore, 1) == NULL) + { + status = CAN_STATUS_ERROR; + } + } + + return status; +} + +/* + * ======== TCAN455X_clearMsgRam ======== + * To avoid ECC errors right after initialization, the MRAM should be zeroed out + * during the initialization, power up, power on reset and wake events, a + * process thus ensuring ECC is properly calculated. + */ +static void TCAN455X_clearMsgRam(void) +{ + uint16_t endAddr; + uint32_t addr; + uint8_t buf[32] = {0}; + + addr = MCAN_getMRAMOffset(); + endAddr = (uint16_t)(addr + TCAN455X_MRAM_SIZE); + + while (addr < endAddr) + { + MCAN_writeMsgRam(addr, &buf[0], sizeof(buf)); + addr += sizeof(buf); + } +} + +/* + * ======== TCAN455X_setBitRate ======== + */ +static int_fast16_t TCAN455X_setBitRate(const CAN_Config *config, uint32_t canInputClkFreq) +{ + const CAN_HWAttrs *hwAttrs = config->hwAttrs; + int_fast16_t status = CAN_STATUS_SUCCESS; + MCAN_BitTimingParams bitTiming = {0}; + + /* Only 40MHz input clock is supported for maximum bit rate */ + if (canInputClkFreq == 40U) + { + /* NOTE: Add 1 to each programmed bit time to get functional value and +1 for for sync segment. + * Bit Time = TSEG1 + TSEG2 + 1 + * Bit Rate = (MCAN clock / Prescaler) / (Bit Time) + * Sample Point % = ((TSEG1 + 1) / (Bit Time)) * 100 + * - All TSEG1 and TSEG2 values above refer to the functional values + * + * Sampling Point % was chosen to be < 80 according to CiA 601 CAN FD Node + * and System Design, Part 3 System Design Recommendation v1.0.0. + */ + switch (hwAttrs->nominalBitRate) + { + case 125000U: + /* 125kbps nominal with 40MHz clk and 75% sample point: ((40E6 / 2) / (119 + 40 + 1) = 125E3) */ + bitTiming.nomRatePrescaler = 1U; + bitTiming.nomTimeSeg1 = 118U; + bitTiming.nomTimeSeg2 = 39U; + bitTiming.nomSynchJumpWidth = 39U; /* typically set equal to seg 2 */ + break; + + case 250000U: + /* 250kbps nominal with 40MHz clk and 75% sample point: ((40E6 / 1) / (119 + 40 + 1) = 250E3) */ + bitTiming.nomRatePrescaler = 0U; + bitTiming.nomTimeSeg1 = 118U; + bitTiming.nomTimeSeg2 = 39U; + bitTiming.nomSynchJumpWidth = 39U; /* typically set equal to seg 2 */ + break; + + case 500000U: + /* 500kbps nominal with 40MHz clk and 75% sample point ((40E6 / 1) / (59 + 20 + 1) = 500E3) */ + bitTiming.nomRatePrescaler = 0U; + bitTiming.nomTimeSeg1 = 58U; + bitTiming.nomTimeSeg2 = 19U; + bitTiming.nomSynchJumpWidth = 19U; /* typically set equal to seg 2 */ + break; + + case 1000000U: + /* 1Mbps nominal with 40MHz clk and 75% sample point ((40E6 / 1) / (29 + 10 + 1) = 1E6) */ + bitTiming.nomRatePrescaler = 0U; + bitTiming.nomTimeSeg1 = 28U; + bitTiming.nomTimeSeg2 = 9U; + bitTiming.nomSynchJumpWidth = 9U; /* typically set equal to seg 2 */ + break; + + default: + status = CAN_STATUS_ERROR; + break; + } + + if (hwAttrs->enableBRS) + { + switch (hwAttrs->dataBitRate) + { + case 125000U: + /* 125kbps with 40MHz clk and 75% sample point: ((40E6 / 10) / (23 + 8 + 1) = 125E3) */ + bitTiming.dataRatePrescaler = 9U; + bitTiming.dataTimeSeg1 = 22U; + bitTiming.dataTimeSeg2 = 7U; + bitTiming.dataSynchJumpWidth = 7U; /* typically set equal to seg 2 */ + break; + + case 250000U: + /* 250kbps with 40MHz clk and 75% sample point: ((40E6 / 8) / (14 + 5 + 1) = 250E3) */ + bitTiming.dataRatePrescaler = 7U; + bitTiming.dataTimeSeg1 = 13U; + bitTiming.dataTimeSeg2 = 4U; + bitTiming.dataSynchJumpWidth = 4U; /* typically set equal to seg 2 */ + break; + + case 500000U: + /* 500kbps with 40MHz clk and 75% sample point ((40E6 / 2) / (29 + 10 + 1) = 500E3) */ + bitTiming.dataRatePrescaler = 1U; + bitTiming.dataTimeSeg1 = 28U; + bitTiming.dataTimeSeg2 = 9U; + bitTiming.dataSynchJumpWidth = 9U; /* typically set equal to seg 2 */ + break; + + case 1000000U: + /* 1Mbps with 40MHz clk and 75% sample point ((40E6 / 1) / (29 + 10 + 1) = 1E6) */ + bitTiming.dataRatePrescaler = 0U; + bitTiming.dataTimeSeg1 = 28U; + bitTiming.dataTimeSeg2 = 9U; + bitTiming.dataSynchJumpWidth = 9U; /* typically set equal to seg 2 */ + break; + + case 2000000U: + /* 2Mbps with 40MHz clk and 75% sample point ((40E6 / 1) / (14 + 5 + 1) = 2E6) */ + bitTiming.dataRatePrescaler = 0U; + bitTiming.dataTimeSeg1 = 13U; + bitTiming.dataTimeSeg2 = 4U; + bitTiming.dataSynchJumpWidth = 4U; /* typically set equal to seg 2 */ + break; + + case 4000000U: + /* 4Mbps with 40MHz clk and 70% sample point ((40E6 / 1) / (6 + 3 + 1) = 4E6) */ + bitTiming.dataRatePrescaler = 0U; + bitTiming.dataTimeSeg1 = 5U; + bitTiming.dataTimeSeg2 = 2U; + bitTiming.dataSynchJumpWidth = 2U; /* typically set equal to seg 2 */ + break; + + case 5000000U: + /* 5Mbps with 40MHz clk and 62.5% sample point ((40E6 / 1) / (4 + 3 + 1) = 5E6) */ + bitTiming.dataRatePrescaler = 0U; + bitTiming.dataTimeSeg1 = 3U; + bitTiming.dataTimeSeg2 = 2U; + bitTiming.dataSynchJumpWidth = 2U; /* typically set equal to seg 2 */ + break; + + default: + status = CAN_STATUS_ERROR; + break; + } + } + } + else + { + status = CAN_STATUS_ERROR; + } + + if (status == CAN_STATUS_SUCCESS) + { + if (MCAN_setBitTime(&bitTiming) != MCAN_STATUS_SUCCESS) + { + status = CAN_STATUS_ERROR; + } + } + + return status; +} + +/* + * ======== TCAN455X_getStatus ======== + */ +uint32_t TCAN455X_getStatus(void) +{ + return TCAN455X_readReg(TCAN455X_STATUS); +} + +/* + * ======== TCAN455X_clearStatus ======== + */ +void TCAN455X_clearStatus(void) +{ + TCAN455X_writeReg(TCAN455X_STATUS, (uint32_t)0xFFFFFFFFU); +} + +/* + * ======== TCAN455X_setInterruptEnable ======== + * Sets TCAN455X-specific interrupt enables. + */ +static void TCAN455X_setInterruptEnable(uint32_t ie) +{ + TCAN455X_writeReg(TCAN455X_IE, ie); +} + +/* + * ======== TCAN455X_clearInterrupt ======== + * Clears TCAN455X-specific interrupt flags. + */ +static void TCAN455X_clearInterrupt(uint32_t mask) +{ + TCAN455X_writeReg(TCAN455X_IR, mask); +} + +/* + * ======== TCAN455X_modifyModeReg ======== + */ +static void TCAN455X_modifyModeReg(uint32_t mask, uint32_t val) +{ + uint32_t regVal = TCAN455X_readReg(TCAN455X_MODE); + + regVal &= ~mask; + /* Bit 5 is a reserved bit that must be written as a 1 */ + regVal |= ((val & mask) | (uint32_t)TCAN455X_MODE_FORCED_SET_BITS); + + TCAN455X_writeReg(TCAN455X_MODE, regVal); +} + +/* + * ======== TCAN455X_setExtTsPrescaler ======== + */ +static inline int_fast16_t TCAN455X_setExtTsPrescaler(uint32_t prescaler) +{ + /* Copy the parameter - MISRA 17.8 */ + uint32_t myPrescaler = prescaler; + + if (myPrescaler == 1U) + { + myPrescaler = 0U; + } + + /* Return error if prescaler value is not a multiple of 8 */ + if ((myPrescaler & 0x7U) != 0U) + { + return CAN_STATUS_ERROR; + } + + /* Divide prescaler value by 8 when writing the register */ + TCAN455X_writeReg(TCAN455X_TS_PRESCALER, myPrescaler >> 3U); + + return CAN_STATUS_SUCCESS; +} + +/* + * ======== TCAN455X_setMode ======== + */ +void TCAN455X_setMode(uint32_t mode) +{ + TCAN455X_modifyModeReg(TCAN455X_MODE_OPMODE_MASK, mode); +} + +/* + * ======== TCAN455X_getMode ======== + */ +uint32_t TCAN455X_getMode(void) +{ + uint32_t mode = TCAN455X_readReg(TCAN455X_MODE) & (uint32_t)TCAN455X_MODE_OPMODE_MASK; + + return mode; +} + +/* + * ======== TCAN455X_disableSleepWakeErrorTimeout ======== + */ +void TCAN455X_disableSleepWakeErrorTimeout(void) +{ + /* Disable Sleep Wake Error */ + TCAN455X_modifyModeReg(TCAN455X_MODE_SWE_DIS, TCAN455X_MODE_SWE_DIS); +} + +/* + * ======== TCAN455X_reset ======== + * Note: This function will trigger TCAN455X interrupt during the reset which + * should be ignored. + */ +static void TCAN455X_reset(void) +{ + /* Perform TCAN455X device reset. + * + * Default configuration after reset: + * - 40 MHz input clock + * - GPIO1 is MCAN_INT 1 + * - GPIO2 has no action + * - INH pin (inhibit for system voltage regulators) enabled + * - nWKRQ pin mirrors INH pin + * - Standby mode + * - WDT enabled + * - Sleep wake error enabled (if no SPI writes for 4 minutes after wake, + * go back to sleep) + * - Test mode disabled + * - All device-specific interrupts enabled + */ + TCAN455X_modifyModeReg(TCAN455X_MODE_RESET, TCAN455X_MODE_RESET); + + /* After device reset, a wait of at least 700us should be used before R/W + * to TCAN455X. + */ + ClockP_usleep(TCAN455X_RESET_DELAY_US); +} + +/* + * ======== TCAN455X_init ======== + */ +static int_fast16_t TCAN455X_init(const CAN_Config *config, + const CAN_MsgRamConfig *msgRamConfig, + const CAN_BitRateTimingRaw *bitTiming, + uint32_t tsPrescaler) +{ + const CAN_HWAttrs *hwAttrs = config->hwAttrs; + CAN_Object *object = config->object; + int_fast16_t status = CAN_STATUS_SUCCESS; + MCAN_ConfigParams configParams = {0U}; + MCAN_InitParams initParams = {0U}; + MCAN_RxNewDataStatus newDataStatus; + const CAN_MsgRamConfig *tempMsgRamConfig; + + TCAN455X_reset(); + + /* Ensure SPI communication is operational */ + if (MCAN_readReg(MCAN_ENDN) != MCAN_ENDN_ETV_VALUE) + { + return CAN_STATUS_ERROR; + } + + /* Disable TCAN4550-specific WDT */ + TCAN455X_modifyModeReg(TCAN455X_MODE_WDT_MASK, TCAN455X_MODE_WDT_DIS); + + /* Disable all device-specific interrupt enables */ + TCAN455X_setInterruptEnable((uint32_t)0x0U); + + /* Clear all status bits */ + TCAN455X_clearStatus(); + + /* Clear all interrupts */ + TCAN455X_clearInterrupt((uint32_t)0xFFFFFFFFU); + + /* MCAN SW init mode should be set already but explicitly set it again */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_STANDBY); + + /* Set FD mode and bit rate switching */ + initParams.fdMode = hwAttrs->enableCANFD ? 1U : 0U; + initParams.brsEnable = hwAttrs->enableBRS ? 1U : 0U; + + if (MCAN_init(&initParams) != MCAN_STATUS_SUCCESS) + { + status = CAN_STATUS_ERROR; + } + + if (status == CAN_STATUS_SUCCESS) + { + /* TCAN455X uses a prescaler off of the Host Clock frequency + * (crystal/clkin) that allows for a divided down clock value to be used + * as the timestamp. + */ + status = TCAN455X_setExtTsPrescaler(tsPrescaler); + } + + if (status == CAN_STATUS_SUCCESS) + { + /* CAN FD requires using "external" timestamp value. "External" means + * external to MCAN IP. + */ + configParams.tsSelect = MCAN_TSCC_COUNTER_EXTERNAL; + + /* Reject remote frames since they are rarely used and do not even exist + * in the CAN FD format. + */ + configParams.filterConfig.rrfs = 1U; + configParams.filterConfig.rrfe = 1U; + + if (hwAttrs->rejectNonMatchingMsgs) + { + /* Reject incoming messages that do not match a filter, the default + * is to accept them into Rx FIFO0. + */ + configParams.filterConfig.anfs = MCAN_GFC_NM_REJECT; + configParams.filterConfig.anfe = MCAN_GFC_NM_REJECT; + } + + if (MCAN_config(&configParams) != MCAN_STATUS_SUCCESS) + { + status = CAN_STATUS_ERROR; + } + } + + if (status == CAN_STATUS_SUCCESS) + { + object->intMask = CANMCAN_getInterruptMask(object->eventMask); + + /* Always enable transmit complete IRQ if there is a Tx FIFO/Queue + * and the Tx ring buffer size is non-zero. + */ + if ((object->txFifoQNum != 0U) && (hwAttrs->txRingBufSize != 0U)) + { + object->intMask |= (uint32_t)MCAN_INT_SRC_TRANS_COMPLETE; + } + + MCAN_setIntLineSel(object->intMask, MCAN_INT_LINE_NUM_0); + MCAN_enableInt(object->intMask); + MCAN_enableIntLine(MCAN_INT_LINE_NUM_0); + + if ((object->intMask & MCAN_INT_SRC_TRANS_COMPLETE) != 0U) + { + /* Enable transmission interrupt for all buffers */ + MCAN_enableTxBufTransInt(0xFFFFFFFFU); + } + + if (bitTiming != NULL) + { + status = CANMCAN_setBitTimingRaw(bitTiming); + } + else + { + status = TCAN455X_setBitRate(config, TCAN455X_config.clkFreqMHz); + } + } + + if (status == CAN_STATUS_SUCCESS) + { + /* Clear message RAM to avoid ECC errors */ + TCAN455X_clearMsgRam(); + + if (msgRamConfig == NULL) + { + /* If msg RAM config is NULL use default */ + tempMsgRamConfig = &TCAN455X_defaultMsgRamConfig; + } + else + { + tempMsgRamConfig = msgRamConfig; + } + + /* Copy config attributes needed for run-time */ + object->txBufNum = tempMsgRamConfig->txBufNum; + object->txFifoQNum = tempMsgRamConfig->txFifoQNum; + object->txEventFifoNum = tempMsgRamConfig->txEventFifoNum; + object->rxBufNum = tempMsgRamConfig->rxBufNum; + object->rxFifoNum[0] = tempMsgRamConfig->rxFifoNum[0]; + object->rxFifoNum[1] = tempMsgRamConfig->rxFifoNum[1]; + + /* Setup message RAM sections and filters */ + status = CANMCAN_configMsgRam(tempMsgRamConfig, TCAN455X_MRAM_SIZE, hwAttrs->enableCANFD); + } + + if (status == CAN_STATUS_SUCCESS) + { + MCAN_clearIntStatus(object->intMask); + newDataStatus.statusLow = 0xFFFFFFFFU; + newDataStatus.statusHigh = 0xFFFFFFFFU; + MCAN_clearNewDataStatus(&newDataStatus); + } + + return status; +} + +/* + * ======== TCAN455X_taskFxn ======== + */ +static void TCAN455X_taskFxn(void *arg) +{ + CAN_Handle handle = (CAN_Handle)arg; + CAN_Object *object = (CAN_Object *)handle->object; + int32_t rxCnt; + MCAN_ProtocolStatus protStatus; + MCAN_TxFifoQStatus fifoQStatus; + MCAN_TxEventFifoStatus txEventFifoStatus; + uint32_t event; + uint32_t intStatus; + uint32_t txOccurred = 0U; + + while (1) + { + /* Wait for TCAN455X_irqHandler to post semaphore. No need to check return value when waiting forever. */ + (void)SemaphoreP_pend(&tcanIRQSemaphore, SemaphoreP_WAIT_FOREVER); + + intStatus = MCAN_getIntStatus() & object->intMask; + + while (intStatus != 0U) + { + MCAN_clearIntStatus(intStatus); + + if ((intStatus & MCAN_INT_SRC_BUS_OFF_STATUS) != 0U) + { + MCAN_getProtocolStatus(&protStatus); + + /* Node is Bus Off when transmit error count >= 256 */ + if (protStatus.busOffStatus == 1U) + { + /* Error recovery - normal operation will resume after 129 occurrences of Bus Idle */ + MCAN_setOpMode(MCAN_OPERATION_MODE_NORMAL); + event = CAN_EVENT_BUS_OFF; + } + else + { + event = CAN_EVENT_BUS_ON; + } + + /* Bus Off interrupt is always enabled regardless of event mask + * so we must check the event mask before executing the callback. + */ + if ((event & object->eventMask) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, event, 0U, object->userArg); + } + } + + if ((intStatus & MCAN_INT_SRC_ERR_PASSIVE) != 0U) + { + MCAN_getProtocolStatus(&protStatus); + + if (protStatus.errPassive == 1U) + { + /* Node is Error Passive when either transmit or receiver error count >= 128 */ + event = CAN_EVENT_ERR_PASSIVE; + } + else + { + /* Node is Error Active when both transmit and receiver error count < 128 */ + event = CAN_EVENT_ERR_ACTIVE; + } + + /* Call the event callback function provided by the application */ + object->eventCbk(handle, event, 0U, object->userArg); + } + + if ((intStatus & MCAN_INT_SRC_RX_FIFO0_NEW_MSG) != 0U) + { + TCAN455X_handleRxFifo(handle, MCAN_RX_FIFO_NUM_0); + } + + if ((intStatus & MCAN_INT_SRC_RX_FIFO1_NEW_MSG) != 0U) + { + TCAN455X_handleRxFifo(handle, MCAN_RX_FIFO_NUM_1); + } + + if ((intStatus & MCAN_INT_SRC_DEDICATED_RX_BUFF_MSG) != 0U) + { + TCAN455X_handleRxBuf(handle); + } + + if ((intStatus & MCAN_INT_SRC_TRANS_COMPLETE) != 0U) + { + /* Read TX buffer transmission status if the Tx finished event mask + * is set so it can be provided to the event callback. + */ + if ((object->eventMask & CAN_EVENT_TX_FINISHED) != 0U) + { + txOccurred = MCAN_getTxBufTransmissionStatus(); + } + + if ((object->txFifoQNum != 0U) && (StructRingBuf_getCount(&object->txStructRingBuf) > 0)) + { + MCAN_getTxFifoQStatus(&fifoQStatus); + + if (fifoQStatus.fifoFull == 0U) + { + /* Return value can be ignored since count was checked */ + (void)StructRingBuf_get(&object->txStructRingBuf, &txElem); + + /* Return value can be ignored as the FIFO is not full */ + (void)CAN_write(handle, &txElem); + } + } + + /* Source Tx complete interrupt is always enabled if the Tx ring + * buffer size is non-zero so we must check the event mask before + * executing the callback. + */ + if ((object->eventMask & CAN_EVENT_TX_FINISHED) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_TX_FINISHED, txOccurred, object->userArg); + } + } + + if ((intStatus & MCAN_INT_SRC_TX_EVT_FIFO_ELEM_LOST) != 0U) + { + if ((object->eventMask & CAN_EVENT_TX_EVENT_LOST) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_TX_EVENT_LOST, 0U, object->userArg); + } + } + + if ((intStatus & MCAN_INT_SRC_TX_EVT_FIFO_NEW_ENTRY) != 0U) + { + MCAN_getTxEventFifoStatus(&txEventFifoStatus); + + if ((object->eventMask & CAN_EVENT_TX_EVENT_AVAIL) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_TX_EVENT_AVAIL, txEventFifoStatus.fillLvl, object->userArg); + } + } + + if ((intStatus & MCAN_INT_SRC_RX_MASK) != 0U) + { + event = CAN_EVENT_RX_DATA_AVAIL; + + rxCnt = StructRingBuf_getCount(&object->rxStructRingBuf); + + if (rxCnt > 0) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_RX_DATA_AVAIL, (uint32_t)rxCnt, object->userArg); + } + } + + if ((intStatus & MCAN_INT_SRC_RX_FIFO0_MSG_LOST) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_RX_FIFO_MSG_LOST, 0U, object->userArg); + } + + if ((intStatus & MCAN_INT_SRC_RX_FIFO1_MSG_LOST) != 0U) + { + /* Call the event callback function provided by the application */ + object->eventCbk(handle, CAN_EVENT_RX_FIFO_MSG_LOST, 1U, object->userArg); + } + + /* Since we are using edge-triggered IRQ, re-check the status to ensure interrupts are not missed */ + intStatus = MCAN_getIntStatus() & object->intMask; + } + } +} + +/* + * ======== CAN_initDevice ======== + */ +int_fast16_t CAN_initDevice(uint_least8_t index, CAN_Params *params) +{ + const CAN_Config *config = &CAN_config[index]; + int_fast16_t status = CAN_STATUS_SUCCESS; + + /* Call driver init functions */ + status = TCAN455X_initSPI(); + + if (status == CAN_STATUS_SUCCESS) + { + /* Config GPIO for TCAN455X nINT: internal pull-up, interrupt on falling edge. + * Many devices do not support interrupt on level low (GPIO_CFG_IN_INT_LOW). + */ + GPIO_setConfig(TCAN455X_config.interruptPin, GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING); + GPIO_setCallback(TCAN455X_config.interruptPin, TCAN455X_irqHandler); + + /* TCAN455X_init() issues a device reset which will trigger an interrupt + * so the GPIO interrupt must be disable to avoid R/W to TCAN455X before + * the reset is completed (~700us). + */ + TCAN455X_disableInterrupt(); + + status = TCAN455X_init(config, params->msgRamConfig, params->bitTiming, params->tsPrescaler); + } + + if (status == CAN_STATUS_SUCCESS) + { + /* Create binary semaphore for IRQ handling */ + if (SemaphoreP_constructBinary(&tcanIRQSemaphore, 0) == NULL) + { + status = CAN_STATUS_ERROR; + } + } + + if (status == CAN_STATUS_SUCCESS) + { + /* Initialize task params */ + TaskP_Params_init(&taskParams); + taskParams.name = "TCAN455X"; + taskParams.priority = TCAN455X_config.taskPri; + taskParams.stack = TCAN455X_config.taskStack; + taskParams.stackSize = TCAN455X_config.taskStackSize; + taskParams.arg = (void *)config; + + /* Construct a task for handling TCAN455X interrupts */ + if (TaskP_construct(&tcanTask, TCAN455X_taskFxn, &taskParams) == NULL) + { + status = CAN_STATUS_ERROR; + } + } + + if (status == CAN_STATUS_SUCCESS) + { + TCAN455X_enableInterrupt(); + + /* Set mode of operation to Normal - this also clears MCAN.CCCR.INIT + * so no need to call MCAN_setOpMode(MCAN_OPERATION_MODE_NORMAL) + */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_NORMAL); + } + + return status; +} + +/* + * ======== CAN_close ======== + */ +void CAN_close(CAN_Handle handle) +{ + CAN_Object *object = handle->object; + + TCAN455X_disableInterrupt(); + + TCAN455X_reset(); + + TaskP_destruct(&tcanTask); + + SemaphoreP_destruct(&tcanIRQSemaphore); + SemaphoreP_destruct(&spiAccessSemaphore); + + object->isOpen = false; +} + +/* + * ======== TCAN455X_enableLoopback ======== + */ +static void TCAN455X_enableLoopback(bool externalModeEnable) +{ + /* Set mode of operation to Standby - this also sets MCAN.CCCR.INIT + * so no need to call MCAN_setOpMode(MCAN_OPERATION_MODE_SW_INIT) + */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_STANDBY); + + if (externalModeEnable) + { + MCAN_enableLoopbackMode(MCAN_LPBK_MODE_EXTERNAL); + } + else + { + MCAN_enableLoopbackMode(MCAN_LPBK_MODE_INTERNAL); + } + + /* Set mode of operation to Normal - this also clears MCAN.CCCR.INIT + * so no need to call MCAN_setOpMode(MCAN_OPERATION_MODE_NORMAL) + */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_NORMAL); +} + +/* + * ======== CAN_enableLoopbackExt ======== + */ +int_fast16_t CAN_enableLoopbackExt(CAN_Handle handle) +{ + (void)handle; /* unused arg */ + + TCAN455X_enableLoopback(true); + + return CAN_STATUS_SUCCESS; +} + +/* + * ======== CAN_enableLoopbackInt ======== + */ +int_fast16_t CAN_enableLoopbackInt(CAN_Handle handle) +{ + (void)handle; /* unused arg */ + + TCAN455X_enableLoopback(false); + + return CAN_STATUS_SUCCESS; +} + +/* + * ======== CAN_disableLoopback ======== + */ +int_fast16_t CAN_disableLoopback(CAN_Handle handle) +{ + (void)handle; /* unused arg */ + + /* Set mode of operation to Normal - this also sets MCAN.CCCR.INIT + * so no need to call MCAN_setOpMode(MCAN_OPERATION_MODE_SW_INIT) + */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_STANDBY); + + MCAN_disableLoopbackMode(); + + /* Set mode of operation to Normal - this also clears MCAN.CCCR.INIT + * so no need to call MCAN_setOpMode(MCAN_OPERATION_MODE_NORMAL) + */ + TCAN455X_setMode(TCAN455X_MODE_OPMODE_NORMAL); + + return CAN_STATUS_SUCCESS; +} + +/* + * ======== CAN_getBitTiming ======== + */ +void CAN_getBitTiming(CAN_Handle handle, CAN_BitTimingParams *bitTiming, uint32_t *clkFreq) +{ + (void)handle; /* unused arg */ + + MCAN_getBitTime(bitTiming); + + *clkFreq = TCAN455X_config.clkFreqMHz * 1000U; +} diff --git a/simplelink_lpf2/source/ti/drivers/can/TCAN455X.h b/simplelink_lpf2/source/ti/drivers/can/TCAN455X.h new file mode 100644 index 00000000..8d3406f6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/can/TCAN455X.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file TCAN455X.h + * + * @brief TCAN455X Driver Interface + * + * @anchor ti_drivers_TCAN455X_Overview + * + * # Overview + * The TCAN455X driver performs the hardware access to the TCAN455x CAN + * controller with integrated transceiver via SPI. + * + * ## Message RAM Size + * The TCAN455X device has 2KB of message RAM. + ******************************************************************************* + */ + +#ifndef ti_drivers_can_tcan455x__include +#define ti_drivers_can_tcan455x__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define TCAN455X_MRAM_SIZE 2048U + +/*! + * @brief TCAN455X global configuration + */ +typedef struct +{ + uint32_t clkFreqMHz; /*!< TCAN455X input clock frequency in MHz */ + uint32_t spiBitRate; /*!< SPI bit rate to communicate with TCAN455X */ + void *taskStack; /*!< Pointer to TCAN455X interrupt handler task stack */ + uint16_t taskStackSize; /*!< TCAN455X interrupt handler task stack size */ + uint8_t taskPri; /*!< TCAN455X interrupt handler task priority */ + uint_least8_t spiIndex; /*!< SPI instance index from Board file */ + uint_least8_t spiCSPin; /*!< SPI Chip Select pin */ + uint_least8_t interruptPin; /*!< TCAN455X interrupt pin */ +} TCAN455X_Config; + +/* Externs from ti_drivers_config.c */ +extern const TCAN455X_Config TCAN455X_config; + +/*! + * @brief Reads the TCAN455X device status flags + * + * @return Device status flags. + * + * @sa #TCAN455X_clearStatus + */ +uint32_t TCAN455X_getStatus(void); + +/*! + * @brief Clears all TCAN455X device status flags + * + * @sa #TCAN455X_getStatus + */ +void TCAN455X_clearStatus(void); + +/*! + * @brief Sets the TCAN455X operational mode + * + * @param mode Operational mode to set: + * TCAN455X_MODE_OPMODE_SLEEP, + * TCAN455X_MODE_OPMODE_STANDBY, + * TCAN455X_MODE_OPMODE_NORMAL + * + * @sa #TCAN455X_getMode + */ +void TCAN455X_setMode(uint32_t mode); + +/*! + * @brief Reads the TCAN455X operational mode + * + * @return Operational mode: + * TCAN455X_MODE_OPMODE_SLEEP, + * TCAN455X_MODE_OPMODE_STANDBY, + * TCAN455X_MODE_OPMODE_NORMAL + * + * @sa #TCAN455X_setMode + */ +uint32_t TCAN455X_getMode(void); + +/*! + * @brief Disables the sleep wake error timeout + * + * The sleep wake error timeout is enabled by default and powers down the + * TCAN455X device within four minutes after power-on, reset, or coming out of + * sleep if the device is not configured by the host. This function can be used + * to disable the sleep wake error timeout and prevent the device from powering + * down. + * + */ +void TCAN455X_disableSleepWakeErrorTimeout(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_can_tcan455x__include */ diff --git a/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.c b/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.c new file mode 100644 index 00000000..20add55b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CANMCAN.c ======== + */ + +#include + +#include +#include + +#include + +#define MCAN_STD_FILTER_ELEM_MAX (128U) +#define MCAN_EXT_FILTER_ELEM_MAX (64U) +#define MCAN_RX_FIFO_ELEM_MAX (64U) +#define MCAN_RX_BUFFERS_ELEM_MAX (64U) +#define MCAN_TX_BUFFERS_ELEM_MAX (32U) + +/* + * ======== CANMCAN_setBitTimingRaw ======== + */ +int_fast16_t CANMCAN_setBitTimingRaw(const CAN_BitRateTimingRaw *rawTiming) +{ + int_fast16_t status = CAN_STATUS_SUCCESS; + MCAN_BitTimingParams bitTiming = {0U}; + + bitTiming.nomRatePrescaler = rawTiming->nbrp; + bitTiming.nomTimeSeg1 = rawTiming->ntSeg1; + bitTiming.nomTimeSeg2 = rawTiming->ntSeg2; + bitTiming.nomSynchJumpWidth = rawTiming->nsjw; + + if (rawTiming->dataTiming != NULL) + { + bitTiming.dataRatePrescaler = rawTiming->dataTiming->dbrp; + bitTiming.dataTimeSeg1 = rawTiming->dataTiming->dtSeg1; + bitTiming.dataTimeSeg2 = rawTiming->dataTiming->dtSeg2; + bitTiming.dataSynchJumpWidth = rawTiming->dataTiming->dsjw; + bitTiming.tdcConfig.tdco = rawTiming->dataTiming->tdcOffset; + bitTiming.tdcConfig.tdcf = rawTiming->dataTiming->tdcFilterWinLen; + } + + if (MCAN_setBitTime(&bitTiming) != MCAN_STATUS_SUCCESS) + { + status = CAN_STATUS_ERROR; + } + + return status; +} + +/* ======== CANMCAN_configMsgRam ======== + * Message RAM sections are configured in this order: + * - Standard ID filters + * - Extended ID filters + * - RX FIFO0 + * - RX FIFO1 + * - RX Buffers + * - TX EventFIFO + * - TX Buffers + * - TX FIFO (or TX Queue) + */ +int_fast16_t CANMCAN_configMsgRam(const CAN_MsgRamConfig *config, uint32_t msgRamSize, bool enableCANFD) +{ + int_fast16_t status = CAN_STATUS_SUCCESS; + MCAN_MsgRamConfig msgRamConfig; + uint_fast8_t i; + uint32_t addr = 0U; + uint32_t payloadSize; + uint32_t msgRamUsage; + uint32_t totalTxBufCnt; + + totalTxBufCnt = config->txBufNum + config->txFifoQNum; + + /* Validate the configuration */ + if ((MCAN_STD_FILTER_ELEM_MAX < config->stdFilterNum) || (MCAN_EXT_FILTER_ELEM_MAX < config->extFilterNum) || + (MCAN_RX_FIFO_ELEM_MAX < config->rxFifoNum[0]) || (MCAN_RX_FIFO_ELEM_MAX < config->rxFifoNum[1]) || + (MCAN_RX_BUFFERS_ELEM_MAX < config->rxBufNum) || (MCAN_TX_BUFFERS_ELEM_MAX < totalTxBufCnt)) + { + return CAN_STATUS_ERROR; + } + + /* Set common element size for all sections */ + if (enableCANFD) + { + msgRamConfig.rxBufElemSize = MCAN_ELEM_SIZE_64BYTES; + msgRamConfig.rxFifo0ElemSize = MCAN_ELEM_SIZE_64BYTES; + msgRamConfig.rxFifo1ElemSize = MCAN_ELEM_SIZE_64BYTES; + msgRamConfig.txBufElemSize = MCAN_ELEM_SIZE_64BYTES; + payloadSize = MCAN_MAX_PAYLOAD_SIZE; + } + else + { + msgRamConfig.rxBufElemSize = MCAN_ELEM_SIZE_8BYTES; + msgRamConfig.rxFifo0ElemSize = MCAN_ELEM_SIZE_8BYTES; + msgRamConfig.rxFifo1ElemSize = MCAN_ELEM_SIZE_8BYTES; + msgRamConfig.txBufElemSize = MCAN_ELEM_SIZE_8BYTES; + payloadSize = 8U; + } + + /* SID filters */ + msgRamConfig.sidFilterStartAddr = 0U; + msgRamConfig.sidFilterListSize = config->stdFilterNum; + addr += MCAN_STD_ID_FILTER_ELEM_SIZE * config->stdFilterNum; + + /* XID filters */ + msgRamConfig.xidFilterStartAddr = addr; + msgRamConfig.xidFilterListSize = config->extFilterNum; + addr += MCAN_EXT_ID_FILTER_ELEM_SIZE * config->extFilterNum; + + /* Rx FIFO 0 */ + msgRamConfig.rxFifo0StartAddr = addr; + msgRamConfig.rxFifo0Size = config->rxFifoNum[0]; + msgRamConfig.rxFifo0Watermark = 0U; /* 0 = watermark interrupt disabled */ + msgRamConfig.rxFifo0OpMode = 0U; /* 0 = blocking mode */ + addr += config->rxFifoNum[0] * (MCAN_TX_RX_ELEMENT_HEADER_SIZE + payloadSize); + + /* Rx FIFO 1 */ + msgRamConfig.rxFifo1StartAddr = addr; + msgRamConfig.rxFifo1Size = config->rxFifoNum[1]; + msgRamConfig.rxFifo1Watermark = 0U; /* 0 = watermark interrupt disabled */ + msgRamConfig.rxFifo1OpMode = 0U; /* 0 = blocking mode */ + addr += config->rxFifoNum[1] * (MCAN_TX_RX_ELEMENT_HEADER_SIZE + payloadSize); + + /* Rx Buffers */ + msgRamConfig.rxBufStartAddr = addr; + addr += config->rxBufNum * (MCAN_TX_RX_ELEMENT_HEADER_SIZE + payloadSize); + + /* Tx Event FIFO */ + msgRamConfig.txEventFifoStartAddr = addr; + msgRamConfig.txEventFifoSize = config->txEventFifoNum; + msgRamConfig.txEventFifoWatermark = 0U; /* 0 = watermark interrupt disabled */ + addr += config->txEventFifoNum * MCAN_TX_EVENT_ELEM_SIZE; + + /* Tx Buffers */ + msgRamConfig.txBufStartAddr = addr; + msgRamConfig.txBufNum = config->txBufNum; + + /* Tx FIFO/Q */ + msgRamConfig.txFifoQSize = config->txFifoQNum; + msgRamConfig.txFifoQMode = config->txFifoQMode; + + msgRamUsage = addr + ((config->txBufNum + config->txFifoQNum) * (MCAN_TX_RX_ELEMENT_HEADER_SIZE + payloadSize)); + + if (msgRamUsage > msgRamSize) + { + status = CAN_STATUS_ERROR; + } + else + { + MCAN_configMsgRam(&msgRamConfig); + + for (i = 0U; i < config->stdFilterNum; i++) + { + MCAN_addStdMsgIDFilter(i, &config->stdMsgIDFilterList[i]); + } + + for (i = 0U; i < config->extFilterNum; i++) + { + MCAN_addExtMsgIDFilter(i, &config->extMsgIDFilterList[i]); + } + } + + return status; +} + +/* + * ======== CANMCAN_getInterruptMask ======== + */ +uint32_t CANMCAN_getInterruptMask(uint32_t eventMask) +{ + /* Bus Off interrupt source is always enabled to allow for recovery */ + uint32_t intMask = (uint32_t)MCAN_INT_SRC_BUS_OFF_STATUS; + + if ((eventMask & CAN_EVENT_RX_DATA_AVAIL) != 0U) + { + intMask |= MCAN_INT_SRC_RX_MASK; + } + + if ((eventMask & CAN_EVENT_TX_FINISHED) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_TRANS_COMPLETE; + } + + if ((eventMask & CAN_EVENT_TX_EVENT_AVAIL) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_TX_EVT_FIFO_NEW_ENTRY; + } + + if ((eventMask & CAN_EVENT_TX_EVENT_LOST) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_TX_EVT_FIFO_ELEM_LOST; + } + + if ((eventMask & (CAN_EVENT_ERR_PASSIVE | CAN_EVENT_ERR_ACTIVE)) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_ERR_PASSIVE; + } + + if ((eventMask & CAN_EVENT_RX_FIFO_MSG_LOST) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_RX_FIFO0_MSG_LOST; + intMask |= (uint32_t)MCAN_INT_SRC_RX_FIFO1_MSG_LOST; + } + + if ((eventMask & CAN_EVENT_BIT_ERR_UNCORRECTED) != 0U) + { + intMask |= (uint32_t)MCAN_INT_SRC_BIT_ERR_UNCORRECTED; + } + + return intMask; +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.h b/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.h new file mode 100644 index 00000000..8b28d3d6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/can/common/CANMCAN.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file CANMCAN.h + * + * @brief Common CAN functions for MCAN configuration + ******************************************************************************* + */ + +#ifndef ti_drivers_can_common_canmcan__include +#define ti_drivers_can_common_canmcan__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Interrupt mask for all Rx sources (Rx FIFO 0, Rx FIFO 1, and dedicated Rx + * buffers). + */ +#define MCAN_INT_SRC_RX_MASK \ + ((uint32_t)MCAN_INT_SRC_RX_FIFO0_NEW_MSG | (uint32_t)MCAN_INT_SRC_RX_FIFO1_NEW_MSG | \ + (uint32_t)MCAN_INT_SRC_DEDICATED_RX_BUFF_MSG) + +/*! + * @brief Sets the MCAN raw bit timing. + * + * @param rawTiming A pointer to CAN_BitRateTimingRaw. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_ERROR if any timing values are invalid. + */ +int_fast16_t CANMCAN_setBitTimingRaw(const CAN_BitRateTimingRaw *rawTiming); + +/*! + * @brief Configures the MCAN message RAM + * + * Configures the MCAN message RAM. If CAN FD is enabled, buffers are configured + * to support a max payload size of 64-bytes. Otherwise, the buffers are + * configured to support a max payload size of 8-bytes for classic CAN. + * + * @param config A pointer to CAN_MsgRamConfig. + * @param msgRamSize Size of the message RAM in bytes. + * @param enableCANFD Set to true if CAN FD is enabled, false otherwise. + * + * @retval CAN_STATUS_SUCCESS if successful. + * @retval CAN_STATUS_ERROR if the message RAM config is invalid. + */ +int_fast16_t CANMCAN_configMsgRam(const CAN_MsgRamConfig *config, uint32_t msgRamSize, bool enableCANFD); + +/*! + * @brief Returns the MCAN interrupt mask based on the CAN event mask. + * + * @param eventMask CAN event mask. + * + * @return MCAN interrupt mask + */ +uint32_t CANMCAN_getInterruptMask(uint32_t eventMask); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_can_common_canmcan__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ITS_s.c b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ITS_s.c new file mode 100644 index 00000000..89c80394 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ITS_s.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * Copyright (c) 2024, Texas Instruments Incorporated - http://www.ti.com + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* The following code is copied from tfm_its_req_mngr.c from TF-M v1.1 and + * its_signal_handle() was modified to support TF-M v2.0. + */ + +#include + +#include +#include +#include +#include + +typedef psa_status_t (*its_func_t)(void); + +static psa_status_t tfm_its_set_ipc(void) +{ + psa_storage_uid_t uid; + size_t data_length; + psa_storage_create_flags_t create_flags; + size_t num; + + if (msg.in_size[0] != sizeof(uid) || msg.in_size[2] != sizeof(create_flags)) + { + /* The size of one of the arguments is incorrect */ + return PSA_ERROR_PROGRAMMER_ERROR; + } + + data_length = msg.in_size[1]; + + num = psa_read(msg.handle, 0, &uid, sizeof(uid)); + if (num != sizeof(uid)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + num = psa_read(msg.handle, 2, &create_flags, sizeof(create_flags)); + if (num != sizeof(create_flags)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return tfm_its_set(msg.client_id, uid, data_length, create_flags); +} + +static psa_status_t tfm_its_get_ipc(void) +{ + psa_storage_uid_t uid; + size_t data_offset; + size_t data_size; + size_t data_length; + size_t num; + + if (msg.in_size[0] != sizeof(uid) || msg.in_size[1] != sizeof(data_offset)) + { + /* The size of one of the arguments is incorrect */ + return PSA_ERROR_PROGRAMMER_ERROR; + } + + data_size = msg.out_size[0]; + + num = psa_read(msg.handle, 0, &uid, sizeof(uid)); + if (num != sizeof(uid)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + num = psa_read(msg.handle, 1, &data_offset, sizeof(data_offset)); + if (num != sizeof(data_offset)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return tfm_its_get(msg.client_id, uid, data_offset, data_size, &data_length); +} + +static psa_status_t tfm_its_get_info_ipc(void) +{ + psa_status_t status; + psa_storage_uid_t uid; + struct psa_storage_info_t info; + size_t num; + + if (msg.in_size[0] != sizeof(uid) || msg.out_size[0] != sizeof(info)) + { + /* The size of one of the arguments is incorrect */ + return PSA_ERROR_PROGRAMMER_ERROR; + } + + num = psa_read(msg.handle, 0, &uid, sizeof(uid)); + if (num != sizeof(uid)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = tfm_its_get_info(msg.client_id, uid, &info); + if (status == PSA_SUCCESS) + { + psa_write(msg.handle, 0, &info, sizeof(info)); + } + + return status; +} + +static psa_status_t tfm_its_remove_ipc(void) +{ + psa_storage_uid_t uid; + size_t num; + + if (msg.in_size[0] != sizeof(uid)) + { + /* The input argument size is incorrect */ + return PSA_ERROR_PROGRAMMER_ERROR; + } + + num = psa_read(msg.handle, 0, &uid, sizeof(uid)); + if (num != sizeof(uid)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return tfm_its_remove(msg.client_id, uid); +} + +static void its_signal_handle(psa_signal_t signal, its_func_t pfn) +{ + psa_status_t status; + + status = psa_get(signal, &msg); + if (status != PSA_SUCCESS) + { + return; + } + + switch (msg.type) + { + case PSA_IPC_CONNECT: + psa_reply(msg.handle, PSA_SUCCESS); + break; + + case PSA_IPC_DISCONNECT: + psa_reply(msg.handle, PSA_SUCCESS); + break; + + default: + if (msg.type >= PSA_IPC_CALL) + { + psa_reply(msg.handle, pfn()); + } + else + { + psa_reply(msg.handle, PSA_ERROR_PROGRAMMER_ERROR); + } + break; + } +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.c new file mode 100644 index 00000000..2dee2013 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "CryptoCC26X4_ns.h" + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#include + +#include +#include + +#define STATUS_SUCCESS ((int_fast16_t)0) +#define STATUS_ERROR ((int_fast16_t)-1) + +/* Semaphore used to synchronize access to TF-M Crypto service */ +SemaphoreP_Struct CryptoPSACC26X4_accessSemaphore; +/* Semaphore used to block the task when blocking return behavior is used */ +SemaphoreP_Struct CryptoPSACC26X4_operationSemaphore; + +static bool isInitialized = false; + +static psa_handle_t sp_handle = PSA_NULL_HANDLE; + +/* + * ======== CryptoPSACC26X4_setupCall ======== + */ +static int_fast16_t CryptoPSACC26X4_setupCall(void) +{ + int_fast16_t status = STATUS_SUCCESS; + + if (!PSA_HANDLE_IS_VALID(sp_handle)) + { + /* Connect to the Crypto Service */ + sp_handle = psa_connect(TI_CRYPTO_SERVICE_SID, TI_CRYPTO_SERVICE_VERSION); + + if (!PSA_HANDLE_IS_VALID(sp_handle)) + { + status = (int_fast16_t)sp_handle; + } + } + + return (status); +} + +/* + * ======== CryptoPSACC26X4_cleanupCall ======== + */ +static void CryptoPSACC26X4_cleanupCall(psa_status_t psaStatus) +{ + if (psaStatus == PSA_ERROR_PROGRAMMER_ERROR) + { + /* When a PSA_ERROR_PROGRAMMER_ERROR occurs, the PSA connection must be + * closed and re-established before normal operation can resume. The PSA + * connection will be re-established during the next crypto function + * call. + */ + psa_close(sp_handle); + + sp_handle = PSA_NULL_HANDLE; + } +} + +/* + * ======== CryptoPSACC26X4_call ======== + */ +psa_status_t CryptoPSACC26X4_call(int32_t type, psa_invec *invecs, psa_outvec *outvecs) +{ + psa_status_t psaStatus; + uintptr_t key; + + if (CryptoPSACC26X4_setupCall() != 0) + { + return STATUS_ERROR; + } + + /* Disable context switching */ + key = HwiP_disable(); + + psaStatus = psa_call(sp_handle, type, invecs, 1, outvecs, 1); + + /* Reenable context switching */ + HwiP_restore(key); + + CryptoPSACC26X4_cleanupCall(psaStatus); + + return (psaStatus); +} + +/* + * ======== CryptoPSACC26X4_init ======== + */ +void CryptoPSACC26X4_init(void) +{ + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + SemaphoreP_constructBinary(&CryptoPSACC26X4_accessSemaphore, 1); + SemaphoreP_constructBinary(&CryptoPSACC26X4_operationSemaphore, 0); + + /* Initialize SecureCB driver */ + SecureCallback_init(); + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== CryptoPSACC26X4_acquireLock ======== + */ +bool CryptoPSACC26X4_acquireLock(uint32_t timeout) +{ + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoPSACC26X4_accessSemaphore, timeout); + + return resourceAcquired == SemaphoreP_OK; +} diff --git a/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.h new file mode 100644 index 00000000..384a71e3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_ns.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoCC26X4_ns.h + * + * @brief Shared resources to arbitrate access to Crypto engines on Secure/Nonsecure devices + * + */ + +#ifndef ti_drivers_crypto_CryptoCC26X4_ns__include +#define ti_drivers_crypto_CryptoCC26X4_ns__include + +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) + +#include + +/*! @cond NODOC */ + +extern SemaphoreP_Struct CryptoPSACC26X4_accessSemaphore; +extern SemaphoreP_Struct CryptoPSACC26X4_operationSemaphore; + +/*! + * @brief Non-secure client wrapper to make PSA calls to secure service. + * Disables context switching around psa_call() + * + * @pre CryptoPSACC26X4_init() must be called first + * + * @param type Secure message type + * @param invecs Input vector pointer to secure message struct + * @param outvecs Output vector pointer to storage for return value + * @return Returns 0 on success, or -129 on PSA programmer error + */ +psa_status_t CryptoPSACC26X4_call(int32_t type, psa_invec *invecs, psa_outvec *outvecs); + +/*! + * @brief Initialization function constructs semaphores and inits SecureCB driver + */ +void CryptoPSACC26X4_init(void); + +/*! + * @brief Get the CryptoPSACC26X4_accessSemaphore (callback and blocking modes) + * Returns bool False on timeout. + * + * @pre CryptoPSACC26X4_init() must be called first + * + * @param timeout Semaphore timeout value + * @return Returns True on success, False on timeout + */ +bool CryptoPSACC26X4_acquireLock(uint32_t timeout); + +/*! + * @brief Post the CryptoPSACC26X4_accessSemaphore (callback and blocking modes) + * + * @pre CryptoPSACC26X4_init() must be called first + */ +__STATIC_INLINE void CryptoPSACC26X4_releaseLock(void) +{ + SemaphoreP_post(&CryptoPSACC26X4_accessSemaphore); +} + +/*! @endcond */ + +#endif /* ti_drivers_crypto_CryptoCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.c new file mode 100644 index 00000000..4872bf4a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "CryptoCC26X4_s.h" +#include +#include /* Auto-generated header */ + +#ifdef TI_CRYPTO_ITS_INTEGRATION + #include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +// #include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +static psa_msg_t msg; + +#ifdef ENABLE_ITS_IPC_INTEGRATION + #include "CryptoCC26X4_ITS_s.c" +#endif + +/* + * ======== pka_irqn_flih ======== + */ +psa_flih_result_t pka_irqn_flih(void) +{ + HwiP_dispatchInterrupt(INT_PKA_IRQ); + + return PSA_FLIH_NO_SIGNAL; +} + +/* + * ======== cryptoresultavail_irqn_flih ======== + */ +psa_flih_result_t cryptoresultavail_irqn_flih(void) +{ + HwiP_dispatchInterrupt(INT_CRYPTO_RESULT_AVAIL_IRQ); + + return PSA_FLIH_NO_SIGNAL; +} + +/* + * ======== trng_irqn_flih ======== + */ +psa_flih_result_t trng_irqn_flih(void) +{ + HwiP_dispatchInterrupt(INT_TRNG_IRQ); + + return PSA_FLIH_NO_SIGNAL; +} + +/* + * ======== Crypto_s_handlePsaMsg ======== + */ +static psa_status_t Crypto_s_handlePsaMsg(psa_msg_t *msg) +{ + int32_t msgTypeIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + msgTypeIndex = GET_CRYPTO_S_MSG_TYPE_INDEX(msg->type); + + switch (msgTypeIndex) + { + case CRYPTO_S_MSG_TYPE_INDEX_AESCBC: + status = AESCBC_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESCCM: + status = AESCCM_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESCMAC: + status = AESCMAC_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESCTR: + status = AESCTR_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESECB: + status = AESECB_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESGCM: + status = AESGCM_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_AESCTRDRBG: + status = AESCTRDRBG_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_ECDH: + status = ECDH_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_ECDSA: + status = ECDSA_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_ECJPAKE: + status = ECJPAKE_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_EDDSA: + status = EDDSA_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_SHA2: + status = SHA2_s_handlePsaMsg(msg); + break; + + case CRYPTO_S_MSG_TYPE_INDEX_TRNG: + status = TRNG_s_handlePsaMsg(msg); + break; + +#if (ENABLE_KEY_STORAGE == 1) + case CRYPTO_S_MSG_TYPE_INDEX_KEYSTORE: + status = KeyStore_s_handlePsaMsg(msg); + break; + + // BQ - commented out as we should be using native PSA call support. + // Delete once implementation finalized. + // case CRYPTO_S_MSG_TYPE_INDEX_PSA: + // status = PSA_s_handlePsaMsg(msg); + // break; +#endif + + default: + /* Unknown msg type - do nothing */ + break; + } + + return status; +} + +/* + * ======== Crypto_sp_main ======== + * Crypto Secure Partition entry point + */ +void Crypto_sp_main(void) +{ + uint32_t signals; + +#if defined(TI_CRYPTO_ITS_INTEGRATION) || defined(ENABLE_ITS_IPC_INTEGRATION) + /* Initialize ITS */ + if (tfm_its_init() != PSA_SUCCESS) + { + psa_panic(); + } +#endif + + /* Initialize all secure crypto drivers except TRNG. TRNG init requires TRNG + * HW to be powered ON first so must be done by non-secure world where power + * is controlled. + */ + AESCBC_s_init(); + AESCCM_s_init(); + AESCMAC_s_init(); + AESCTR_s_init(); + AESECB_s_init(); + AESGCM_s_init(); + + AESCTRDRBG_s_init(); + + ECDH_s_init(); + ECDSA_s_init(); + ECJPAKE_s_init(); + EDDSA_s_init(); + + SHA2_s_init(); + +#if (ENABLE_KEY_STORAGE == 1) + KeyStore_s_init(); + + // BQ - commented out as we should be using native PSA call support. + // Delete once implementation finalized. + // PSA_s_init(); +#endif + + /* Enable external interrupts for AES and TRNG. PKA interrupt is not enabled + * here since it must be enabled by the PKA driver for proper operation. + */ + psa_irq_enable(CryptoResultAvail_IRQn_SIGNAL); + psa_irq_enable(TRNG_IRQn_SIGNAL); + + while (1) + { + signals = psa_wait(PSA_WAIT_ANY, PSA_BLOCK); + + if (signals & TI_CRYPTO_SERVICE_SIGNAL) + { + psa_get(TI_CRYPTO_SERVICE_SIGNAL, &msg); + + switch (msg.type) + { + case PSA_IPC_CONNECT: + /* This partition supports multiple simultaneous connections */ + psa_reply(msg.handle, PSA_SUCCESS); + break; + + case PSA_IPC_DISCONNECT: + psa_reply(msg.handle, PSA_SUCCESS); + break; + + default: + if (msg.type >= PSA_IPC_CALL) + { + psa_reply(msg.handle, Crypto_s_handlePsaMsg(&msg)); + } + else + { + psa_reply(msg.handle, PSA_ERROR_PROGRAMMER_ERROR); + } + break; + } + } +#ifdef ENABLE_ITS_IPC_INTEGRATION + else if (signals & TFM_ITS_SET_SIGNAL) + { + its_signal_handle(TFM_ITS_SET_SIGNAL, tfm_its_set_ipc); + } + else if (signals & TFM_ITS_GET_SIGNAL) + { + its_signal_handle(TFM_ITS_GET_SIGNAL, tfm_its_get_ipc); + } + else if (signals & TFM_ITS_GET_INFO_SIGNAL) + { + its_signal_handle(TFM_ITS_GET_INFO_SIGNAL, tfm_its_get_info_ipc); + } + else if (signals & TFM_ITS_REMOVE_SIGNAL) + { + its_signal_handle(TFM_ITS_REMOVE_SIGNAL, tfm_its_remove_ipc); + } +#endif /* ENABLE_ITS_IPC_INTEGRATION */ + else + { + psa_panic(); + } + } + + return; +} diff --git a/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.h new file mode 100644 index 00000000..38e90dab --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/crypto/CryptoCC26X4_s.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file CryptoCC26X4_s.h + * @brief Secure Crypto Service + * + * @anchor ti_drivers_crypto_CryptoCC26X4_s_Overview + * # Overview + * The Secure Crypto Service is used to access all cryptographic functions + * when using the TF-M. + * + ******************************************************************************* + */ +#ifndef ti_drivers_crypto_CryptoCC26X4_s__include +#define ti_drivers_crypto_CryptoCC26X4_s__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Index values for secure msg types for various crypto drivers */ +#define CRYPTO_S_MSG_TYPE_INDEX_AESCBC ((int32_t)0x11) +#define CRYPTO_S_MSG_TYPE_INDEX_AESCCM ((int32_t)0x22) +#define CRYPTO_S_MSG_TYPE_INDEX_AESCMAC ((int32_t)0x33) +#define CRYPTO_S_MSG_TYPE_INDEX_AESCTR ((int32_t)0x44) +#define CRYPTO_S_MSG_TYPE_INDEX_AESECB ((int32_t)0x55) +#define CRYPTO_S_MSG_TYPE_INDEX_AESGCM ((int32_t)0x66) +#define CRYPTO_S_MSG_TYPE_INDEX_AESCTRDRBG ((int32_t)0x77) +#define CRYPTO_S_MSG_TYPE_INDEX_ECDH ((int32_t)0x88) +#define CRYPTO_S_MSG_TYPE_INDEX_ECDSA ((int32_t)0x99) +#define CRYPTO_S_MSG_TYPE_INDEX_ECJPAKE ((int32_t)0xAA) +#define CRYPTO_S_MSG_TYPE_INDEX_EDDSA ((int32_t)0xBB) +#define CRYPTO_S_MSG_TYPE_INDEX_SHA2 ((int32_t)0xCC) +#define CRYPTO_S_MSG_TYPE_INDEX_TRNG ((int32_t)0xDD) +#define CRYPTO_S_MSG_TYPE_INDEX_KEYSTORE ((int32_t)0xEE) +#define CRYPTO_S_MSG_TYPE_INDEX_PSA ((int32_t)0xFF) + +#define CRYPTO_S_MSG_TYPE_FUNCNUM_BITS 4U +#define CRYPTO_S_MSG_TYPE_FUNCNUM_SHIFT 8U +#define CRYPTO_S_MSG_TYPE_INDEX_MASK 0xFF +#define GET_CRYPTO_S_MSG_TYPE_INDEX(type) ((type) & (int32_t)CRYPTO_S_MSG_TYPE_INDEX_MASK) + +/* TF-M PSA NS interface internally limits the type to int16_t */ +#define TFM_PSA_TYPE_MASK 0x00007FFF + +/* + * Macros used to generate PSA message type values for various crypto driver + * functions. It duplicates the funcNum in the highest nibble when possible + * for bit flip resistance. The funcNum value is limited to 15. + */ +#define CRYPTO_S_MSG_TYPE(index, funcNum) \ + (((index) | ((int32_t)(funcNum) << CRYPTO_S_MSG_TYPE_FUNCNUM_SHIFT) | \ + ((int32_t)(funcNum) << (CRYPTO_S_MSG_TYPE_FUNCNUM_SHIFT + CRYPTO_S_MSG_TYPE_FUNCNUM_BITS))) & \ + TFM_PSA_TYPE_MASK) + +#define AESCBC_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESCBC, funcNum) +#define AESCCM_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESCCM, funcNum) +#define AESCMAC_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESCMAC, funcNum) +#define AESCTR_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESCTR, funcNum) +#define AESCTRDRBG_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESCTRDRBG, funcNum) +#define AESECB_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESECB, funcNum) +#define AESGCM_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_AESGCM, funcNum) +#define ECDH_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_ECDH, funcNum) +#define ECDSA_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_ECDSA, funcNum) +#define ECJPAKE_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_ECJPAKE, funcNum) +#define EDDSA_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_EDDSA, funcNum) +#define SHA2_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_SHA2, funcNum) +#define TRNG_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_TRNG, funcNum) +#define KEYSTORE_PSA_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_KEYSTORE, funcNum) +#define PSA_S_MSG_TYPE(funcNum) CRYPTO_S_MSG_TYPE(CRYPTO_S_MSG_TYPE_INDEX_PSA, funcNum) + +/* + * Secure handle ID values which correspond to unmapped memory ranges are used + * to avoid confusion with non-secure driver handles which point to valid + * memory locations. + */ +enum +{ + CRYPTO_S_HANDLE_ID_AESCBC = 0xABCD1000U, + CRYPTO_S_HANDLE_ID_AESCCM = 0xABCD2000U, + CRYPTO_S_HANDLE_ID_AESCMAC = 0xABCD3000U, + CRYPTO_S_HANDLE_ID_AESCTR = 0xABCD4000U, + CRYPTO_S_HANDLE_ID_AESECB = 0xABCD5000U, + CRYPTO_S_HANDLE_ID_AESGCM = 0xABCD6000U, + CRYPTO_S_HANDLE_ID_AESCTRDRBG = 0xABCD7000U, + CRYPTO_S_HANDLE_ID_ECDH = 0xABCD8000U, + CRYPTO_S_HANDLE_ID_ECDSA = 0xABCD9000U, + CRYPTO_S_HANDLE_ID_ECJPAKE = 0xABCDA000U, + CRYPTO_S_HANDLE_ID_EDDSA = 0xABCDB000U, + CRYPTO_S_HANDLE_ID_SHA2 = 0xABCDC000U, + CRYPTO_S_HANDLE_ID_TRNG = 0xABCDD000U, +}; + +#define CRYPTO_S_HANDLE_ID_MASK 0xFFFFF000U +#define CRYPTO_S_HANDLE_INDEX_MASK 0x00000FFFU + +#define GET_CRYPTO_S_HANDLE_ID(handle) ((uintptr_t)(handle)&CRYPTO_S_HANDLE_ID_MASK) +#define GET_CRYPTO_S_HANDLE_INDEX(handle) ((uintptr_t)(handle)&CRYPTO_S_HANDLE_INDEX_MASK) + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_crypto_CryptoCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c new file mode 100644 index 00000000..fb729df3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#if defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + + #include /* TI CMSE helper functions */ + #include + +/* + * ======== CryptoKey_verifySecureKey ======== + */ +static int_fast16_t CryptoKey_verifySecureKey(const CryptoKey *secureKey, bool isWriteable) +{ + int_fast16_t status = CryptoKey_STATUS_ERROR; + void *ptr; + + if ((secureKey->encoding == CryptoKey_PLAINTEXT) || (secureKey->encoding == CryptoKey_BLANK_PLAINTEXT)) + { + /* Verify key material address range */ + if (isWriteable) + { + ptr = cmse_has_unpriv_nonsecure_rw_access(secureKey->u.plaintext.keyMaterial, + secureKey->u.plaintext.keyLength); + } + else + { + ptr = cmse_has_unpriv_nonsecure_read_access(secureKey->u.plaintext.keyMaterial, + secureKey->u.plaintext.keyLength); + } + + if (ptr != NULL) + { + status = CryptoKey_STATUS_SUCCESS; + } + } + else if ((secureKey->encoding == CryptoKey_KEYSTORE) || (secureKey->encoding == CryptoKey_BLANK_KEYSTORE)) + { + status = CryptoKey_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== CryptoKey_verifySecureInputKey ======== + */ +int_fast16_t CryptoKey_verifySecureInputKey(const CryptoKey *secureKey) +{ + return CryptoKey_verifySecureKey(secureKey, false); +} + +/* + * ======== CryptoKey_verifySecureOutputKey ======== + */ +int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey) +{ + return CryptoKey_verifySecureKey(secureKey, true); +} + +/* + * ======== CryptoKey_copySecureInputKey ======== + */ +int_fast16_t CryptoKey_copySecureInputKey(CryptoKey *dst, const CryptoKey **src) +{ + /* Validate source key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)*src, sizeof(CryptoKey)) == NULL) + { + return CryptoKey_STATUS_ERROR; + } + + /* Make a secure copy of the key */ + (void)spm_memcpy(dst, *src, sizeof(CryptoKey)); + + /* Validate the key material address range */ + if (CryptoKey_verifySecureInputKey(dst) != CryptoKey_STATUS_SUCCESS) + { + return CryptoKey_STATUS_ERROR; + } + + /* Update the src pointer to point to secure key copy */ + *src = dst; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKey_copySecureOutputKey ======== + */ +int_fast16_t CryptoKey_copySecureOutputKey(CryptoKey *dst, CryptoKey **src) +{ + /* Validate source key struct address range */ + if (cmse_has_unpriv_nonsecure_rw_access(*src, sizeof(CryptoKey)) == NULL) + { + return CryptoKey_STATUS_ERROR; + } + + /* Make a secure copy of the key */ + (void)spm_memcpy(dst, *src, sizeof(CryptoKey)); + + /* Validate the key material address range */ + if (CryptoKey_verifySecureOutputKey(dst) != CryptoKey_STATUS_SUCCESS) + { + return CryptoKey_STATUS_ERROR; + } + + /* Update the src pointer to point to secure key copy */ + *src = dst; + + return CryptoKey_STATUS_SUCCESS; +} + +#endif /* TFM_BUILD */ + +/* + * ======== CryptoKey_getCryptoKeyType ======== + */ +int_fast16_t CryptoKey_getCryptoKeyType(const CryptoKey *keyHandle, CryptoKey_Encoding *keyType) +{ + *keyType = keyHandle->encoding; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKey_isBlank ======== + */ +int_fast16_t CryptoKey_isBlank(const CryptoKey *keyHandle, bool *isBlank) +{ + if ((keyHandle->encoding == CryptoKey_BLANK_PLAINTEXT) || (keyHandle->encoding == CryptoKey_BLANK_KEYSTORE)) + { + *isBlank = true; + } + else + { + *isBlank = false; + } + + return CryptoKey_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h new file mode 100644 index 00000000..0779759d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoKey.h + * + * @brief The CryptoKey type is an opaque representation of a cryptographic key. + * + * @warning This is a beta API. It may change in future releases. + * + * Cryptographic keying material may be stored on an embedded system multiple ways. + * - plaintext: in plaintext in flash or RAM + * - key store: in a dedicated hardware database whose entries can not be directly + * read out. + * + * Each storage option requires different approaches to handling the keying material + * when performing a crypto operation. In order to separate these concerns from + * the API of the various crypto drivers available with TI-RTOS, the CryptoKey + * type abstracts away from these details. It does not contain any cryptographic + * keying material itself but instead contains the details necessary for drivers to use the + * keying material. The driver implementation handles preparing and moving the keying + * material as necessary to perform the desired crypto operation. + * + * The same CryptoKey may be passed to crypto APIs of different modes subject to + * restrictions placed on the key by their storage types. Plaintext keys may be used + * without restriction while key store keys have their permitted uses + * restricted when the keying material is loaded. + * These restrictions are specified in a CryptoKey_SecurityPolicy that is device-specific + * and depends on the hardware capability of the device. + * + * An application should never access a field within a CryptoKey struct itself. + * Where needed, helper functions are provided to do so. + * + * Before using a CryptoKey in another crypto API call, it must be initialized + * with a call to one of the initialization functions. + * - CryptoKeyPlaintext_initKey() + * - CryptoKeyPlaintext_initBlankKey() + * - KeyStore_PSA_initKey() + * - KeyStore_PSA_initBlankKey() + * + * The keystore CryptoKeys may be used to load a key into a key store after + * its respective _init call. + * + * CryptoKeys can be initialized "blank", without keying material but with an empty buffer + * or key store entry, to encode the destination of a key to be created in the + * future. This way, keys may be generated securely within a key store + * for example and never even be stored in RAM temporarily. + * + * Not all devices support all CryptoKey functionality. This is hardware-dependent. + * + */ + +#ifndef ti_drivers_cryptoutils_cyptokey_CryptoKey__include +#define ti_drivers_cryptoutils_cyptokey_CryptoKey__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + + */ + +/** + * @defgroup CryptoKey_CONTROL Status codes + * These CryptoKey macros are reservations for CryptoKey.h + * @{ + */ + +/*! + * Common CryptoKey_control status code reservation offset. + * CryptoKey driver implementations should offset status codes with + * CryptoKey_STATUS_RESERVED growing negatively. + * + * Example implementation specific status codes: + * @code + * #define CryptoKeyXYZ_STATUS_ERROR0 CryptoKey_STATUS_RESERVED - 0 + * #define CryptoKeyXYZ_STATUS_ERROR1 CryptoKey_STATUS_RESERVED - 1 + * #define CryptoKeyXYZ_STATUS_ERROR2 CryptoKey_STATUS_RESERVED - 2 + * @endcode + */ +#define CryptoKey_STATUS_RESERVED (-32) + +/** + * @defgroup CryptoKey_STATUS Status Codes + * CryptoKey_STATUS_* macros are general status codes returned by CryptoKey_control() + * @{ + * @ingroup CryptoKey_CONTROL + */ + +/*! + * @brief Successful status code + * + * CryptoKey_control() returns CryptoKey_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define CryptoKey_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_ERROR (-1) + +/*! + * @brief Returned if the encoding of a CryptoKey is not a CryptoKey_Encoding value + * + * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define CryptoKey_STATUS_UNDEFINED_ENCODING (-2) + +/** @}*/ + +/** @}*/ + +/* + * CRYPTOKEY_HSM is being used to mask bit 6 which determines which accelerator to use. + * Any encoding that is ORed with CRYPTOKEY_HSM indicates that the HSM is the engine of choice for the operation + */ +#define CRYPTOKEY_HSM 0x20U + +#define CRYPTOKEY_PLAINTEXT 0x02U +#define CRYPTOKEY_BLANK_PLAINTEXT 0x04U +#define CRYPTOKEY_KEYSTORE 0x08U +#define CRYPTOKEY_BLANK_KEYSTORE 0x10U + +/*! + * @brief List of the different types of CryptoKey. + * _HSM encodings are only available for select devices, CC27XX. + */ +typedef uint8_t CryptoKey_Encoding; +static const CryptoKey_Encoding CryptoKey_PLAINTEXT = CRYPTOKEY_PLAINTEXT; +static const CryptoKey_Encoding CryptoKey_BLANK_PLAINTEXT = CRYPTOKEY_BLANK_PLAINTEXT; +static const CryptoKey_Encoding CryptoKey_KEYSTORE = CRYPTOKEY_KEYSTORE; +static const CryptoKey_Encoding CryptoKey_BLANK_KEYSTORE = CRYPTOKEY_BLANK_KEYSTORE; +static const CryptoKey_Encoding CryptoKey_PLAINTEXT_HSM = CRYPTOKEY_PLAINTEXT | CRYPTOKEY_HSM; +static const CryptoKey_Encoding CryptoKey_BLANK_PLAINTEXT_HSM = CRYPTOKEY_BLANK_PLAINTEXT | CRYPTOKEY_HSM; +static const CryptoKey_Encoding CryptoKey_KEYSTORE_HSM = CRYPTOKEY_KEYSTORE | CRYPTOKEY_HSM; +static const CryptoKey_Encoding CryptoKey_BLANK_KEYSTORE_HSM = CRYPTOKEY_BLANK_KEYSTORE | CRYPTOKEY_HSM; + +/*! + * @brief Plaintext CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in plaintext form in flash or RAM. + */ +typedef struct +{ + uint8_t *keyMaterial; + uint32_t keyLength; +} CryptoKey_Plaintext; + +/*! + * @brief Key store CryptoKey datastructure. + * + * This structure contains all the information necessary to access keying material stored + * in a dedicated key store or key database with memory access controls. + * The application must ensure that the key attributes struct used to initialize the pointer + * #keyAttributes must either be a global variable or it must be available in the context of the + * function that makes the call to import the key associated with the same key attribute. + * Otherwise, the keyAttributes pointer will point to a location in stack that could be deallocated. + */ +typedef struct +{ + uint32_t keyLength; + uint32_t keyID; + const void *keyAttributes; +} CryptoKey_KeyStore; + +/*! + * @brief CryptoKey datastructure. + * + * This structure contains a CryptoKey_Encoding and one of + * - CryptoKey_Plaintext + * - CryptoKey_KeyStore + */ +typedef struct +{ + CryptoKey_Encoding encoding; + union + { + CryptoKey_Plaintext plaintext; + CryptoKey_KeyStore keyStore; + } u; +} CryptoKey; + +/*! + * @brief Structure that specifies the restrictions on a CryptoKey + * + * This structure is device-specific and declared here in incomplete form. + * The structure is fully defined in CryptoKeyDEVICE.h. This creates a link-time binding + * when using the structure with key store functions. If the instance + * of the CryptoKey_SecurityPolicy is kept in a device-specific application-file, + * the generic application code may still use references to it despite being + * an incomplete type in the generic application file at compile time. + */ +typedef struct CryptoKey_SecurityPolicy_ CryptoKey_SecurityPolicy; + +/*! + * @brief Gets the key type of the CryptoKey + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] keyType Type of the CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_getCryptoKeyType(const CryptoKey *keyHandle, CryptoKey_Encoding *keyType); + +/*! + * @brief Whether the CryptoKey is 'blank' or represents valid keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * @param [out] isBlank Whether the CryptoKey is 'blank' or not + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_isBlank(const CryptoKey *keyHandle, bool *isBlank); + +/*! + * @brief Function to initialize the CryptoKey_SecurityPolicy struct to its defaults + * + * This will zero-out all fields that cannot be set to safe defaults + * + * @param [in] policy Pointer to a CryptoKey_SecurityPolicy + * + * @return Returns a status code + */ +int_fast16_t CryptoKey_initSecurityPolicy(CryptoKey_SecurityPolicy *policy); + +/*! + * @brief Function to verify a secure CryptoKey + * + * This will check that the key type is valid and verify plaintext key material + * is located in non-secure read-access memory. + * + * @note This function may not be available in all implementations + * + * @param [in] secureKey Pointer to a CryptoKey struct located in secure memory + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_verifySecureInputKey(const CryptoKey *secureKey); + +/*! + * @brief Function to verify a secure output CryptoKey + * + * This will check that the key type is valid and verify plaintext key material + * is located in non-secure RW-access memory. + * + * @note This function may not be available in all implementations + * + * @param [in] secureKey Pointer to a CryptoKey struct located in secure memory + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_verifySecureOutputKey(const CryptoKey *secureKey); + +/*! + * @brief Function to copy and verify a secure input CryptoKey + * + * This will check that the source CryptoKey struct is located in non-secure + * read-access memory, copy the CryptoKey struct from the src to dst, and check + * that the key type is valid and verify plaintext key material is located in + * non-secure read-access memory. + * + * @note This function may not be available in all implementations + * + * @param [out] dst Pointer to the destination CryptoKey struct located in secure memory + * @param [in,out] src Pointer to a source CryptoKey struct pointer located in secure memory + * which will be updated to point to the destination CryptoKey struct + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_copySecureInputKey(CryptoKey *dst, const CryptoKey **src); + +/*! + * @brief Function to copy and verify a secure output CryptoKey + * + * This will check that the source CryptoKey struct is located in non-secure + * RW-access memory, copy the CryptoKey struct from the src to dst, and check + * that the key type is valid and verify plaintext key material is located in + * non-secure RW-access memory. + * + * @note This function may not be available in all implementations + * + * @param [out] dst Pointer to the destination CryptoKey struct located in secure memory + * @param [in,out] src Pointer to a source CryptoKey struct pointer located in secure memory + * which will be updated to point to the destination CryptoKey struct + * + * @retval CryptoKey_STATUS_SUCCESS Key passes all verification checks + * @retval CryptoKey_STATUS_ERROR Key fails any verification check + */ +int_fast16_t CryptoKey_copySecureOutputKey(CryptoKey *dst, CryptoKey **src); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cyptokey_CryptoKey__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c new file mode 100644 index 00000000..89e557c6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2022-2024 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* CryptoKey headers */ +#include +#include +#include + +/* + * ======== KeyStore_PSA_initKey ======== + */ +int_fast16_t KeyStore_PSA_initKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_KEYSTORE; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_initBlankKey ======== + */ +int_fast16_t KeyStore_PSA_initBlankKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_BLANK_KEYSTORE; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_initKeyHSM ======== + */ +int_fast16_t KeyStore_PSA_initKeyHSM(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_KEYSTORE_HSM; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_initBlankKeyHSM ======== + */ +int_fast16_t KeyStore_PSA_initBlankKeyHSM(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes) +{ + keyHandle->encoding = CryptoKey_BLANK_KEYSTORE_HSM; + + SET_KEY_ID(keyHandle->u.keyStore.keyID, keyID); + + keyHandle->u.keyStore.keyLength = keyLength; + + keyHandle->u.keyStore.keyAttributes = keyAttributes; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== KeyStore_PSA_setKeyId ======== + */ +void KeyStore_PSA_setKeyId(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyFileId key) +{ + psa_set_key_id(attributes, key); +} + +/* + * ======== KeyStore_PSA_setKeyLifetime ======== + */ +void KeyStore_PSA_setKeyLifetime(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyLifetime lifetime) +{ + psa_set_key_lifetime(attributes, lifetime); +} + +/* + * ======== KeyStore_PSA_getKeyId ======== + */ +KeyStore_PSA_KeyFileId KeyStore_PSA_getKeyId(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_id(attributes); +} + +/* + * ======== KeyStore_PSA_getKeyLifetime ======== + */ +KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_lifetime(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyUsageFlags ======== + */ +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usageFlags) +{ + psa_set_key_usage_flags(attributes, usageFlags); +} + +/* + * ======== KeyStore_PSA_getKeyUsageFlags ======== + */ +KeyStore_PSA_KeyUsage KeyStore_PSA_getKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_usage_flags(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyAlgorithm ======== + */ +void KeyStore_PSA_setKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_Algorithm alg) +{ + psa_set_key_algorithm(attributes, alg); +} + +/* + * ======== KeyStore_PSA_getKeyAlgorithm ======== + */ +KeyStore_PSA_Algorithm KeyStore_PSA_getKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_algorithm(attributes); +} + +/* + * ======== KeyStore_PSA_setKeyType ======== + */ +void KeyStore_PSA_setKeyType(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyType type) +{ + psa_set_key_type(attributes, type); +} + +/* + * ======== KeyStore_PSA_setKeyBits ======== + */ +void KeyStore_PSA_setKeyBits(KeyStore_PSA_KeyAttributes *attributes, size_t bits) +{ + psa_set_key_bits(attributes, bits); +} + +/* + * ======== KeyStore_PSA_getKeyType ======== + */ +KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_type(attributes); +} + +/* + * ======== KeyStore_PSA_getKeyBits ======== + */ +size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes) +{ + return psa_get_key_bits(attributes); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h new file mode 100644 index 00000000..f4ac11e4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA.h @@ -0,0 +1,1916 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file CryptoKeyKeyStore_PSA.h + * @brief CryptoKeyKeyStore_PSA driver header + * + * @warning This is a beta API. It may change in future releases. + * + * # Overview # + * This file contains the APIs to import, export, copy, and destroy key store + * CryptoKeys. Key store CryptoKeys reference keying material stored in flash or + * RAM using a key identifier. These CryptoKeys are subject to enforced usage + * restrictions as defined by the key attributes assigned during key import. + * This file provides definitions that are common between the Non-Secure + * Processing Environment (NSPE) and Secure Processing Environment (SPE). + * + * # Usage # + * + * After calling the key store initialization function, a CryptoKey must be + * imported into the key store before it can be used for a crypto operation APIs + * which takes a CryptoKey as an input. + + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_Example + * + * ## Importing and destroying a persistent AES-CCM KeyStore key # + * + * @code + * + * #include + * #include + * .... + * + * uint8_t keyingMaterial[16] = {0x1f, 0x8e, 0x49, 0x73, 0x95, 0x3f, 0x3f, 0xb0, + * 0xbd, 0x6b, 0x16, 0x66, 0x2e, 0x9a, 0x3c, 0x17}; + * CryptoKey cryptoKey; + * KeyStore_PSA_KeyFileId keyID; + * int_fast16_t status; + * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * + * // Assign key attributes + * KeyStore_PSA_setKeyUsageFlags(&attributes, (KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT)); + * KeyStore_PSA_setKeyAlgorithm(&attributes, KEYSTORE_PSA_ALG_CCM); + * KeyStore_PSA_setKeyType(&attributes, KEYSTORE_PSA_KEY_TYPE_AES); + * KeyStore_PSA_setKeyLifetime(&attributes, KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT); + * + * // Set key ID + * GET_KEY_ID(keyID, KEYSTORE_PSA_KEY_ID_USER_MIN); + * KeyStore_PSA_setKeyId(&attributes, keyID); + * + * // Import the keyingMaterial + * status = KeyStore_PSA_importKey(&attributes, keyingMaterial, sizeof(keyingMaterial), &keyID); + * + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * + * // Initialize cryptoKey for crypto operations + * KeyStore_PSA_initKey(&cryptoKey, keyID, sizeof(keyingMaterial), NULL); + * + * // Use the cryptoKey for AESCCM operations + * + * // Destroy key after use + * status = KeyStore_PSA_destroyKey(keyID); + * + * if (status != KEYSTORE_PSA_STATUS_SUCCESS) + * { + * // Handle error + * } + * @endcode + * + */ + +#ifndef ti_drivers_CryptoKeyKeyStore_PSA__include +#define ti_drivers_CryptoKeyKeyStore_PSA__include + +#include + +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include + #include + #include + #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include + #include + #include + #include + #include + #else + #error "Unsupported DeviceFamily_Parent for CryptoKeyKeyStore_PSA" + #endif /* #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ +#else + #include +#endif /* #if (TFM_ENABLED == 0) || defined(TFM_BUILD) */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Encoding of permitted usage on a key. */ +typedef psa_key_usage_t KeyStore_PSA_KeyUsage; + +/** Encoding of key lifetimes. + * + * The lifetime of a key indicates where it is stored and what system + * actions may create and destroy it. + * + * Lifetime values have the following structure: + * - Bits 0-7 (#KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(\c lifetime)): + * persistence level. This value indicates what device management + * actions can cause it to be destroyed. In particular, it indicates + * whether the key is _volatile_ or _persistent_. + * See ::KeyStore_PSA_KeyPersistence for more information. + * - Bits 8-31 (#KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(\c lifetime)): + * location indicator. This value indicates which part of the system + * has access to the key material and can perform operations using the key. + * See ::KeyStore_PSA_KeyLocation for more information. + * + * Volatile keys are automatically destroyed when the application instance + * terminates or on a power reset of the device. Persistent keys are + * preserved until the application explicitly destroys them or until an + * integration-specific device management event occurs (for example, + * a factory reset). + * + * Persistent keys have a key identifier of type #KeyStore_PSA_KeyFileId. + * This identifier remains valid throughout the lifetime of the key, + * even if the application instance that created the key terminates. + * + * The default lifetime of a key is #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE. The lifetime + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT is supported if persistent storage is + * available. Other lifetime values may be supported depending on the + * library configuration. + * + * Values of this type are generally constructed by macros called + * `KEYSTORE_PSA_KEY_LIFETIME_xxx`. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef psa_key_lifetime_t KeyStore_PSA_KeyLifetime; + +/** Encoding of key persistence levels. + * + * What distinguishes different persistence levels is what device management + * events may cause keys to be destroyed. _Volatile_ keys are destroyed + * by a power reset. Persistent keys may be destroyed by events such as + * a transfer of ownership or a factory reset. What management events + * actually affect persistent keys at different levels is outside the + * scope of the PSA Cryptography specification. + * + * The PSA Cryptography specification defines the following values of + * persistence levels: + * - \c 0 = #KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE: volatile key. + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * - \c 1 = #KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT: + * persistent key with a default lifetime. + * - \c 2-254: currently not supported by Mbed TLS. + * - \c 255 = #KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY: + * read-only or write-once key. + * A key with this persistence level cannot be destroyed. + * Mbed TLS does not currently offer a way to create such keys, but + * integrations of Mbed TLS can use it for built-in keys that the + * application cannot modify (for example, a hardware unique key (HUK)). + * + * @note Key persistence levels are 8-bit values. Key management + * interfaces operate on lifetimes (type ::KeyStore_PSA_KeyLifetime) which + * encode the persistence as the lower 8 bits of a 32-bit value. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef psa_key_persistence_t KeyStore_PSA_KeyPersistence; + +/** Encoding of key location indicators. + * + * If an application can make calls to external + * cryptoprocessors such as secure elements, the location of a key + * indicates which secure element performs the operations on the key. + * Depending on the design of the secure element, the key + * material may be stored either in the secure element, or + * in wrapped (encrypted) form alongside the key metadata in the + * primary local storage. + * + * The PSA Cryptography API specification defines the following values of + * location indicators: + * - \c 0: primary local storage. + * This location is always available. + * The primary local storage is typically the same storage area that + * contains the key metadata. + * - \c 1: primary secure element. + * Integrations of Mbed TLS should support this value if there is a secure + * element attached to the operating environment. + * As a guideline, secure elements may provide higher resistance against + * side channel and physical attacks than the primary local storage, but may + * have restrictions on supported key types, sizes, policies and operations + * and may have different performance characteristics. + * - \c 2-0x7fffff: other locations defined by a PSA specification. + * The PSA Cryptography API does not currently assign any meaning to these + * locations, but future versions of that specification or other PSA + * specifications may do so. + * - \c 0x800000-0xffffff: vendor-defined locations. + * No PSA specification will assign a meaning to locations in this range. + * + * @note Key location indicators are 24-bit values. Key management + * interfaces operate on lifetimes (type ::KeyStore_PSA_KeyLifetime) which + * encode the location as the upper 24 bits of a 32-bit value. + * + * @note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef psa_key_location_t KeyStore_PSA_KeyLocation; + +/** @defgroup KeyStore_PSA_Statuses Key Store status return values. + */ +/** The action was completed successfully. */ +#define KEYSTORE_PSA_STATUS_SUCCESS ((int_fast16_t)PSA_SUCCESS) + +/** An error occurred that does not correspond to any defined + * failure cause. + * + * Implementations may use this error code if none of the other standard + * error codes are applicable. */ +#define KEYSTORE_PSA_STATUS_GENERIC_ERROR ((int_fast16_t)PSA_ERROR_GENERIC_ERROR) + +/** The requested operation or a parameter is not supported + * by this implementation. + * + * Implementations should return this error code when an enumeration + * parameter such as a key type, algorithm, etc. is not recognized. + * If a combination of parameters is recognized and identified as + * not valid, return #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT instead. */ +#define KEYSTORE_PSA_STATUS_NOT_SUPPORTED ((int_fast16_t)PSA_ERROR_NOT_SUPPORTED) + +/** The requested action is denied by a policy. + * + * Implementations should return this error code when the parameters + * are recognized as valid and supported, and a policy explicitly + * denies the requested operation. + * + * If a subset of the parameters of a function call identify a + * forbidden operation, and another subset of the parameters are + * not valid or not supported, it is unspecified whether the function + * returns #KEYSTORE_PSA_STATUS_NOT_PERMITTED, #KEYSTORE_PSA_STATUS_NOT_SUPPORTED or + * #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT. */ +#define KEYSTORE_PSA_STATUS_NOT_PERMITTED ((int_fast16_t)PSA_ERROR_NOT_PERMITTED) + +/** The key ID is not valid or does not exist. + */ +#define KEYSTORE_PSA_STATUS_INVALID_KEY_ID ((int_fast16_t)PSA_ERROR_INVALID_HANDLE) + +/** An output buffer is too small. + * + * Applications can call the @c PSA_xxx_SIZE macro listed in the function + * description to determine a sufficient buffer size. + * + * Implementations should preferably return this error code only + * in cases when performing the operation with a larger output + * buffer would succeed. However implementations may return this + * error if a function has invalid or unsupported parameters in addition + * to the parameters that determine the necessary output buffer size. */ +#define KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL ((int_fast16_t)PSA_ERROR_BUFFER_TOO_SMALL) + +/** Asking for an item that already exists + * + * Implementations should return this error, when attempting + * to write an item (like a key) that already exists. */ +#define KEYSTORE_PSA_STATUS_ALREADY_EXISTS ((int_fast16_t)PSA_ERROR_ALREADY_EXISTS) + +/** Asking for an item that doesn't exist + * + * Implementations should return this error, if a requested item (like + * a key) does not exist. */ +#define KEYSTORE_PSA_STATUS_DOES_NOT_EXIST ((int_fast16_t)PSA_ERROR_DOES_NOT_EXIST) + +/** The requested action cannot be performed in the current state. + * + * Multipart operations return this error when one of the + * functions is called out of sequence. Refer to the function + * descriptions for permitted sequencing of functions. + * + * Implementations shall not return this error code to indicate that a key + * either exists or not, but shall instead return + * #KEYSTORE_PSA_STATUS_ALREADY_EXISTS or #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST as + * applicable. + * + * Implementations shall not return this error code to indicate that a + * key ID is invalid, but shall return #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * instead. */ +#define KEYSTORE_PSA_STATUS_BAD_STATE ((int_fast16_t)PSA_ERROR_BAD_STATE) + +/** The parameters passed to the function are invalid. + * + * Implementations may return this error any time a parameter or + * combination of parameters are recognized as invalid. + * + * Implementations shall not return this error code to indicate that a + * key ID is invalid, but shall return #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * instead. + */ +#define KEYSTORE_PSA_STATUS_INVALID_ARGUMENT ((int_fast16_t)PSA_ERROR_INVALID_ARGUMENT) + +/** There is not enough runtime memory. + * + * If the action is carried out across multiple security realms, this + * error can refer to available memory in any of the security realms. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY ((int_fast16_t)PSA_ERROR_INSUFFICIENT_MEMORY) + +/** There is not enough persistent storage. + * + * Functions that modify the key storage return this error code if + * there is insufficient storage space on the host media. In addition, + * many functions that do not otherwise access storage may return this + * error code if the implementation requires a mandatory log entry for + * the requested action and the log storage space is full. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE ((int_fast16_t)PSA_ERROR_INSUFFICIENT_STORAGE) + +/** There was a communication failure inside the implementation. + * + * This can indicate a communication failure between the application + * and an external cryptoprocessor or between the cryptoprocessor and + * an external volatile or persistent memory. A communication failure + * may be transient or permanent depending on the cause. + * + * @warning If a function returns this error, it is undetermined + * whether the requested action has completed or not. Implementations + * should return #KEYSTORE_PSA_STATUS_SUCCESS on successful completion + * whenever possible, however functions may return + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE if the requested action was completed + * successfully in an external cryptoprocessor but there was a breakdown of + * communication before the cryptoprocessor could report the status to the + * application. + */ +#define KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE ((int_fast16_t)PSA_ERROR_COMMUNICATION_FAILURE) + +/** There was a storage failure that may have led to data loss. + * + * This error indicates that some persistent storage is corrupted. + * It should not be used for a corruption of volatile memory + * (use #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED), for a communication error + * between the cryptoprocessor and its external storage (use + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE), or when the storage is + * in a valid state but is full (use #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE). + * + * Note that a storage failure does not indicate that any data that was + * previously read is invalid. However this previously read data may no + * longer be readable from storage. + * + * When a storage failure occurs, it is no longer possible to ensure + * the global integrity of the keystore. Depending on the global + * integrity guarantees offered by the implementation, access to other + * data may or may not fail even if the data is still readable but + * its integrity cannot be guaranteed. + * + * Implementations should only use this error code to report a + * permanent storage corruption. However application writers should + * keep in mind that transient errors while reading the storage may be + * reported using this error code. */ +#define KEYSTORE_PSA_STATUS_STORAGE_FAILURE ((int_fast16_t)PSA_ERROR_STORAGE_FAILURE) + +/** A hardware failure was detected. + * + * A hardware failure may be transient or permanent depending on the + * cause. */ +#define KEYSTORE_PSA_STATUS_HARDWARE_FAILURE ((int_fast16_t)PSA_ERROR_HARDWARE_FAILURE) + +/** There is not enough entropy to generate random data needed + * for the requested action. + * + * This error indicates a failure of a hardware random generator. + * Application writers should note that this error can be returned not + * only by functions whose purpose is to generate random data, such + * as key, IV or nonce generation, but also by functions that execute + * an algorithm with a randomized result, as well as functions that + * use randomization of intermediate computations as a countermeasure + * to certain attacks. + * + * Implementations should avoid returning this error after KeyStore_PSA_init() + * has succeeded. Implementations should generate sufficient + * entropy during initialization and subsequently use a cryptographically + * secure pseudorandom generator (PRNG). However implementations may return + * this error at any time if a policy requires the PRNG to be reseeded + * during normal operation. */ +#define KEYSTORE_PSA_STATUS_INSUFFICIENT_ENTROPY ((int_fast16_t)PSA_ERROR_INSUFFICIENT_ENTROPY) + +/** A tampering attempt was detected. + * + * If an application receives this error code, there is no guarantee + * that previously accessed or computed data was correct and remains + * confidential. Applications should not perform any security function + * and should enter a safe failure state. + * + * Implementations may return this error code if they detect an invalid + * state that cannot happen during normal operation and that indicates + * that the implementation's security guarantees no longer hold. Depending + * on the implementation architecture and on its security and safety goals, + * the implementation may forcibly terminate the application. + * + * This error code is intended as a last resort when a security breach + * is detected and it is unsure whether the keystore data is still + * protected. Implementations shall only return this error code + * to report an alarm from a tampering detector, to indicate that + * the confidentiality of stored data can no longer be guaranteed, + * or to indicate that the integrity of previously returned data is now + * considered compromised. Implementations shall not use this error code + * to indicate a hardware failure that merely makes it impossible to + * perform the requested operation (use #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE, + * #KEYSTORE_PSA_STATUS_STORAGE_FAILURE, #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE or other + * applicable error code instead). + * + * This error indicates an attack against the application. Implementations + * shall not return this error code as a consequence of the behavior of + * the application itself. */ +#define KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED ((int_fast16_t)PSA_ERROR_CORRUPTION_DETECTED) + +/*! + * @brief An error status code returned if the hardware or software resource + * is currently unavailable. + * + * KeyStore driver implementation may have limitations on how + * many clients can simultaneously perform operations on the same key. This status code is + * returned if the mutual exclusion mechanism signals that an operation cannot + * currently be performed. + */ + +#define KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE ((int_fast16_t)-250) + +/** @brief Encoding of a key type. + */ +typedef psa_key_type_t KeyStore_PSA_KeyType; + +/** Raw data. + * + * A "key" of this type cannot be used for any cryptographic operation. + * Applications may use this type to store arbitrary data in the keystore. */ +#define KEYSTORE_PSA_KEY_TYPE_RAW_DATA ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RAW_DATA) + +/** HMAC key. + * + * The key policy determines which underlying hash algorithm the key can be + * used for. + * + * HMAC keys should generally have the same size as the underlying hash. */ +#define KEYSTORE_PSA_KEY_TYPE_HMAC ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_HMAC) + +/** A secret for key derivation. + * + * The key policy determines which key derivation algorithm the key + * can be used for. + */ +#define KEYSTORE_PSA_KEY_TYPE_DERIVE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_DERIVE) + +/** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. + * + * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or + * 32 bytes (AES-256). + */ +#define KEYSTORE_PSA_KEY_TYPE_AES ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_AES) + +/** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). + * + * The size of the key can be 64 bits (single DES), 128 bits (2-key 3DES) or + * 192 bits (3-key 3DES). + * + * Note that single DES and 2-key 3DES are weak and strongly + * deprecated and should only be used to decrypt legacy data. 3-key 3DES + * is weak and deprecated and should only be used in legacy protocols. + */ +#define KEYSTORE_PSA_KEY_TYPE_DES ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_DES) + +/** Key for a cipher, AEAD or MAC algorithm based on the + * Camellia block cipher. */ +#define KEYSTORE_PSA_KEY_TYPE_CAMELLIA ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_CAMELLIA) + +/** Key for the RC4 stream cipher. + * + * Note that RC4 is weak and deprecated and should only be used in + * legacy protocols. */ +#define KEYSTORE_PSA_KEY_TYPE_ARC4 ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ARC4) + +/** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. + * + * ChaCha20 and the ChaCha20_Poly1305 construction are defined in RFC 7539. + * + * Implementations must support 12-byte nonces, may support 8-byte nonces, + * and should reject other sizes. + */ +#define KEYSTORE_PSA_KEY_TYPE_CHACHA20 ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_CHACHA20) + +/** RSA public key. + * + * The size of an RSA key is the bit size of the modulus. + */ +#define KEYSTORE_PSA_KEY_TYPE_RSA_PUBLIC_KEY ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RSA_PUBLIC_KEY) +/** RSA key pair (private and public key). + * + * The size of an RSA key is the bit size of the modulus. + */ +#define KEYSTORE_PSA_KEY_TYPE_RSA_KEY_PAIR ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_RSA_KEY_PAIR) +/** Whether a key type is an RSA key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_RSA(type) (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) + +#define KEYSTORE_PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) +#define KEYSTORE_PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_ECC_KEY_PAIR_BASE) + +/** A low-entropy secret for password hashing or key derivation. + * + * This key type is suitable for passwords and passphrases which are typically + * intended to be memorizable by humans, and have a low entropy relative to + * their size. It can be used for randomly generated or derived keys with + * maximum or near-maximum entropy, but #KEYSTORE_PSA_KEY_TYPE_PASSWORD is more suitable + * for such keys. It is not suitable for passwords with extremely low entropy, + * such as numerical PINs. + * + * The key policy determines which key derivation algorithm the key can be + * used for. + */ +#define KEYSTORE_PSA_KEY_TYPE_PASSWORD ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_PASSWORD) + +/** A secret value that can be used to verify a password hash. + * + * The key policy determines which key derivation algorithm the key + * can be used for, among the same permissible subset as for + * #KEYSTORE_PSA_KEY_TYPE_PASSWORD. + */ +#define KEYSTORE_PSA_KEY_TYPE_PASSWORD_HASH ((KeyStore_PSA_KeyType)PSA_KEY_TYPE_PASSWORD_HASH) + +/** @brief Encoding of a cryptographic algorithm. + * + * For algorithms that can be applied to multiple key types, this type + * does not encode the key type. For example, for symmetric ciphers + * based on a block cipher, #KeyStore_PSA_Algorithm encodes the block cipher + * mode and the padding mode while the block cipher itself is encoded + * via #KeyStore_PSA_KeyType. + */ +typedef psa_algorithm_t KeyStore_PSA_Algorithm; + +/** SHA2-224 */ +#define KEYSTORE_PSA_ALG_SHA_224 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_224) +/** SHA2-256 */ +#define KEYSTORE_PSA_ALG_SHA_256 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_256) +/** SHA2-384 */ +#define KEYSTORE_PSA_ALG_SHA_384 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_384) +/** SHA2-512 */ +#define KEYSTORE_PSA_ALG_SHA_512 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512) +/** SHA2-512/224 */ +#define KEYSTORE_PSA_ALG_SHA_512_224 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512_224) +/** SHA2-512/256 */ +#define KEYSTORE_PSA_ALG_SHA_512_256 ((KeyStore_PSA_Algorithm)PSA_ALG_SHA_512_256) + +/** Macro to build an HMAC algorithm */ +#define KEYSTORE_PSA_ALG_HMAC(hash_alg) ((KeyStore_PSA_Algorithm)(PSA_ALG_HMAC(hash_alg))) + +/** The CBC-MAC construction over a block cipher + * + * @warning CBC-MAC is insecure in many cases. + * A more secure mode, such as #KEYSTORE_PSA_ALG_CMAC, is recommended. + */ +#define KEYSTORE_PSA_ALG_CBC_MAC ((KeyStore_PSA_Algorithm)PSA_ALG_CBC_MAC) +/** The CMAC construction over a block cipher */ +#define KEYSTORE_PSA_ALG_CMAC ((KeyStore_PSA_Algorithm)PSA_ALG_CMAC) + +/** The CTR stream cipher mode. + * + * CTR is a stream cipher which is built from a block cipher. + * The underlying block cipher is determined by the key type. + * For example, to use AES-128-CTR, use this algorithm with + * a key of type #KEYSTORE_PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). + */ +#define KEYSTORE_PSA_ALG_CTR ((KeyStore_PSA_Algorithm)PSA_ALG_CTR) + +/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. + * + * \warning ECB mode does not protect the confidentiality of the encrypted data + * except in extremely narrow circumstances. It is recommended that applications + * only use ECB if they need to construct an operating mode that the + * implementation does not provide. Implementations are encouraged to provide + * the modes that applications need in preference to supporting direct access + * to ECB. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths are a + * multiple of the block size of the chosen block cipher. + */ +#define KEYSTORE_PSA_ALG_ECB_NO_PADDING ((KeyStore_PSA_Algorithm)PSA_ALG_ECB_NO_PADDING) + +/** The CBC block cipher chaining mode, with no padding. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths + * are whole number of blocks for the chosen block cipher. + */ +#define KEYSTORE_PSA_ALG_CBC_NO_PADDING ((KeyStore_PSA_Algorithm)PSA_ALG_CBC_NO_PADDING) + +/** The CCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define KEYSTORE_PSA_ALG_CCM ((KeyStore_PSA_Algorithm)PSA_ALG_CCM) + +/** The GCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define KEYSTORE_PSA_ALG_GCM ((KeyStore_PSA_Algorithm)PSA_ALG_GCM) + +/** The Chacha20-Poly1305 AEAD algorithm. + * + * The ChaCha20_Poly1305 construction is defined in RFC 7539. + * + * Implementations must support 12-byte nonces, may support 8-byte nonces, + * and should reject other sizes. + * + * Implementations must support 16-byte tags and should reject other sizes. + */ +#define KEYSTORE_PSA_ALG_CHACHA20_POLY1305 ((KeyStore_PSA_Algorithm)PSA_ALG_CHACHA20_POLY1305) + +/** The elliptic curve Diffie-Hellman (ECDH) key agreement algorithm. + * + * The shared secret produced by key agreement is the x-coordinate of + * the shared secret point. It is always `ceiling(m / 8)` bytes long where + * `m` is the bit size associated with the curve, i.e. the bit size of the + * order of the curve's coordinate field. When `m` is not a multiple of 8, + * the byte containing the most significant bit of the shared secret + * is padded with zero bits. The byte order is either little-endian + * or big-endian depending on the curve type. + * + * - For Montgomery curves (curve types `PSA_ECC_FAMILY_CURVEXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in little-endian byte order. + * The bit size is 448 for Curve448 and 255 for Curve25519. + * - For Weierstrass curves over prime fields (curve types + * `PSA_ECC_FAMILY_SECPXXX` and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m = ceiling(log_2(p))` for the field `F_p`. + * - For Weierstrass curves over binary fields (curve types + * `PSA_ECC_FAMILY_SECTXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m` for the field `F_{2^m}`. + */ +#define KEYSTORE_PSA_ALG_ECDH ((KeyStore_PSA_Algorithm)PSA_ALG_ECDH) + +/** ECDSA signature without hashing. + * + * This is the same signature scheme without specifying a hash algorithm. + * This algorithm may only be used to sign or verify a sequence of bytes + * that should be an pre-calculated hash. + */ +#define KEYSTORE_PSA_ALG_ECDSA ((KeyStore_PSA_Algorithm)PSA_ALG_ECDSA_ANY) + +/** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. */ +#define KEYSTORE_PSA_ALG_PAKE ((KeyStore_PSA_Algorithm)PSA_ALG_JPAKE) + +/** Edwards-curve digital signature algorithm without prehashing (PureEdDSA), + * using standard parameters. + * + * PureEdDSA requires an elliptic curve key on a twisted Edwards curve. + * In this specification, the following curves are supported: + * - PSA_ECC_FAMILY_TWISTED_EDWARDS, 255-bit: Ed25519 as specified + * in RFC 8032. + * The curve is Edwards25519. + * The hash function used internally is SHA-512. + * + * This algorithm can be used with #KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE and + * #KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE. Since there is no prehashing, it cannot be used + * with #KEYSTORE_PSA_KEY_USAGE_SIGN_HASH and #KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH. + * + */ +#define KEYSTORE_PSA_ALG_PURE_EDDSA ((KeyStore_PSA_Algorithm)PSA_ALG_PURE_EDDSA) + +/* The encoding of curve identifiers is currently aligned with the + * TLS Supported Groups Registry (formerly known as the + * TLS EC Named Curve Registry) + * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 + * The values are defined by RFC 8422 and RFC 7027. */ +#define KEYSTORE_PSA_ECC_CURVE_SECT163K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT163R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT163R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECT193R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT193R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECT233K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT233R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT239K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT283K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT283R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT409K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT409R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECT571K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECT571R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP160R2 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R2) +#define KEYSTORE_PSA_ECC_CURVE_SECP192K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP192R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP224K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP224R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP256K1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_K1) +#define KEYSTORE_PSA_ECC_CURVE_SECP256R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP384R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_PSA_ECC_CURVE_SECP521R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_SECP_R1) +#define KEYSTORE_ECC_CURVE_BRAINPOOL_P256R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +#define KEYSTORE_ECC_CURVE_BRAINPOOL_P384R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +#define KEYSTORE_ECC_CURVE_BRAINPOOL_P512R1 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_BRAINPOOL_P_R1) +/** Cur KEYSTORE_ECC_CURVE_SECPv((KeyStore_PSA_KeyType)e25519. + * + * This is the curve defined in Bernstein et al., + * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. + * The algorithm #KEYSTORE_PSA_ALG_ECDH performs X25519 when used with this curve. + */ +#define KEYSTORE_PSA_ECC_CURVE_CURVE25519 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_MONTGOMERY) +/** Curve448 + * + * This is the curve defined in Hamburg, + * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. + * The algorithm #KEYSTORE_PSA_ALG_ECDH performs X448 when used with this curve. + */ +#define KEYSTORE_PSA_ECC_CURVE_CURVE448 ((KeyStore_PSA_KeyType)PSA_ECC_FAMILY_MONTGOMERY) + +/** Minimum value for a vendor-defined ECC curve identifier + * + * The range for vendor-defined curve identifiers is a subset of the IANA + * registry private use range, `0xfe00` - `0xfeff`. + */ +#define KEYSTORE_PSA_ECC_CURVE_VENDOR_MIN ((KeyStore_PSA_KeyType)PSA_ECC_CURVE_VENDOR_MIN) +/** Maximum value for a vendor-defined ECC curve identifier + * + * The range for vendor-defined curve identifiers is a subset of the IANA + * registry private use range, `0xfe00` - `0xfeff`. + */ +#define KEYSTORE_PSA_ECC_CURVE_VENDOR_MAX ((KeyStore_PSA_KeyType)PSA_ECC_CURVE_VENDOR_MAX) + +/** Volatile Key Limit [KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, KEYSTORE_PSA_MAX_VOLATILE_KEY_ID] + * + * Upper limit for volatile key ID, KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, is KEYSTORE_PSA_KEY_ID_VENDOR_MAX. + * Lower limit for volatile key ID, KEYSTORE_PSA_MIN_VOLATILE_KEY_ID, is the last + * MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of provided by implementation reserved for vendors. + */ +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MIN + #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VOLATILE_MAX +#else + /* PSA_KEY_SLOT_COUNT is not available in TF-M's crypto.h so we must + * hardcode it to match the value in Mbed TLS's header. + */ + #define KEYSTORE_PSA_MIN_VOLATILE_KEY_ID (PSA_KEY_ID_VENDOR_MAX - MBEDTLS_PSA_KEY_SLOT_COUNT + 1) + #define KEYSTORE_PSA_MAX_VOLATILE_KEY_ID PSA_KEY_ID_VENDOR_MAX +#endif + +/* Macro to obtain size of struct member */ +#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member) + +/** \defgroup key_lifetimes Key lifetimes + * @{ + */ + +/** The default lifetime for volatile keys. + * + * A volatile key only exists as long as the identifier to it is not destroyed. + * The key material is guaranteed to be erased on a power reset. + * + * A key with this lifetime is stored in RAM. + * + * Equivalent to + * #KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(#KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE, + * #KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE) + */ +#define KEYSTORE_PSA_KEY_LIFETIME_VOLATILE ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_VOLATILE) + +/** The default lifetime for persistent keys. + * + * A persistent key remains in storage until it is explicitly destroyed or + * until the corresponding storage area is wiped. This specification does + * not define any mechanism to wipe a storage area, but implementations may + * provide their own mechanism (for example to perform a factory reset, + * to prepare for device refurbishment, or to uninstall an application). + * + * This lifetime value is the default storage area for the calling + * application. Implementations may offer other storage areas designated + * by other lifetime values as implementation-specific extensions. + * + * Equivalent to + * #KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(#KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT, + * #KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE) + */ +#define KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT ((KeyStore_PSA_KeyLifetime)PSA_KEY_LIFETIME_PERSISTENT) + +/** The persistence level of volatile keys. + * + * See ::KeyStore_PSA_KeyPersistence for more information. + */ +#define KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_VOLATILE) + +/** The default persistence level for persistent keys. + * + * See ::KeyStore_PSA_KeyPersistence for more information. + */ +#define KEYSTORE_PSA_KEY_PERSISTENCE_DEFAULT ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_DEFAULT) + +/** The persistence level for HSM Asset Store. + * + * See ::KeyStore_PSA_KeyPersistence for more information. + */ +#define KEYSTORE_PSA_KEY_PERSISTENCE_HSM_ASSET_STORE ((KeyStore_PSA_KeyPersistence)0x80U) + +/** A persistence level indicating that a key is never destroyed. + * + * See ::KeyStore_PSA_KeyPersistence for more information. + */ +#define KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY ((KeyStore_PSA_KeyPersistence)PSA_KEY_PERSISTENCE_READ_ONLY) + +/* clang-format off */ +#define KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) ((KeyStore_PSA_KeyPersistence)((lifetime) & 0x000000ff)) +/* clang-format on */ + +#define KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(lifetime) ((KeyStore_PSA_KeyLocation)((lifetime) >> 8)) + +/** Whether a key lifetime indicates that the key is volatile. + * + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * + * A key that is not volatile is persistent. Persistent keys are + * preserved until the application explicitly destroys them or until an + * implementation-specific device management event occurs (for example, + * a factory reset). + * + * @param lifetime The lifetime value to query (value of type + * ::KeyStore_PSA_KeyLifetime). + * + * @return \c 1 if the key is volatile, otherwise \c 0. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_IS_VOLATILE(lifetime) \ + (KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == KEYSTORE_PSA_KEY_PERSISTENCE_VOLATILE) + +/** Whether a key lifetime indicates that the key is read-only. + * + * Read-only keys cannot be created or destroyed through the PSA Crypto API. + * They must be created through platform-specific means that bypass the API. + * + * Some platforms may offer ways to destroy read-only keys. For example, + * consider a platform with multiple levels of privilege, where a + * low-privilege application can use a key but is not allowed to destroy + * it, and the platform exposes the key to the application with a read-only + * lifetime. High-privilege code can destroy the key even though the + * application sees the key as read-only. + * + * @param lifetime The lifetime value to query (value of type + * ::KeyStore_PSA_KeyLifetime). + * + * @return \c 1 if the key is read-only, otherwise \c 0. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime) \ + (KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == KEYSTORE_PSA_KEY_PERSISTENCE_READ_ONLY) + +/** Construct a lifetime from a persistence level and a location. + * + * @param persistence The persistence level + * (value of type ::KeyStore_PSA_KeyPersistence). + * @param location The location indicator + * (value of type ::KeyStore_PSA_KeyLocation). + * + * @return The constructed lifetime value. + */ +#define KEYSTORE_PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location) \ + (PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location)) + +/** The local storage area for persistent keys. + * + * This storage area is available on all systems that can store persistent + * keys without delegating the storage to a third-party cryptoprocessor. + * + * See ::KeyStore_PSA_KeyLocation for more information. + */ +#define KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE ((KeyStore_PSA_KeyLocation)PSA_KEY_LOCATION_LOCAL_STORAGE) + +/** The default secure element storage area for persistent keys. + * + * This storage location is available on systems that have one or more secure + * elements that are able to store keys (i.e. CC27XX only) + * + * See ::KeyStore_PSA_KeyLocation for more information. + */ +#define KEYSTORE_PSA_KEY_LOCATION_HSM_ASSET_STORE ((KeyStore_PSA_KeyLocation)0x000001U) + +/** The null key identifier. + */ +#define KEYSTORE_PSA_KEY_ID_NULL ((KeyStore_PSA_keyID)0x0) + +/** The maximum value for a key identifier chosen by the application. + */ +#define KEYSTORE_PSA_KEY_ID_USER_MAX ((KeyStore_PSA_keyID)PSA_KEY_ID_USER_MAX) + +/** The minimum value for a key identifier chosen by the application. + */ +#define KEYSTORE_PSA_KEY_ID_USER_MIN ((KeyStore_PSA_keyID)PSA_KEY_ID_USER_MIN) + +/** The maximum value for a key identifier chosen by the application. + */ +#define KEYSTORE_PSA_KEY_ID_USER_MAX ((KeyStore_PSA_keyID)PSA_KEY_ID_USER_MAX) + +/** The minimum value for a key identifier chosen by the implementation. + */ +#define KEYSTORE_PSA_KEY_ID_VENDOR_MIN ((KeyStore_PSA_keyID)PSA_KEY_ID_VENDOR_MIN) + +/** The maximum value for a key identifier chosen by the implementation. + */ +#define KEYSTORE_PSA_KEY_ID_VENDOR_MAX ((KeyStore_PSA_keyID)PSA_KEY_ID_VENDOR_MAX) + +/** Default Key Owner + */ +#define KEYSTORE_PSA_DEFAULT_OWNER MBEDTLS_PSA_CRYPTO_KEY_ID_DEFAULT_OWNER + +/**@}*/ + +/** \defgroup key_policies Key policies + * @{ + */ + +/** Whether the key may be exported. + * + * A public key or the public part of a key pair may always be exported + * regardless of the value of this permission flag. + * + * If a key does not have export permission, implementations shall not + * allow the key to be exported in plain form from the cryptoprocessor, + * whether through KeyStore_PSA_exportKey() or through a proprietary interface. + * The key may however be exportable in a wrapped form, i.e. in a form + * where it is encrypted by another key. + */ +#define KEYSTORE_PSA_KEY_USAGE_EXPORT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_EXPORT) + +/** Whether the key may be copied. + * + * This flag allows the use of KeyStore_PSA_copyKey() to make a copy of the key + * with the same policy or a more restrictive policy. + * + * For lifetimes for which the key is located in a secure element which + * enforce the non-exportability of keys, copying a key outside the secure + * element also requires the usage flag #KEYSTORE_PSA_KEY_USAGE_EXPORT. + * Copying the key inside the secure element is permitted with just + * #KEYSTORE_PSA_KEY_USAGE_COPY if the secure element supports it. + * For keys with the lifetime #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE or + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT, the usage flag #KEYSTORE_PSA_KEY_USAGE_COPY + * is sufficient to permit the copy. + */ +#define KEYSTORE_PSA_KEY_USAGE_COPY ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_COPY) + +/** Whether the key may be used to encrypt a message. + * + * This flag allows the key to be used for a symmetric encryption operation, + * for an AEAD encryption-and-authentication operation, + * or for an asymmetric encryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_ENCRYPT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_ENCRYPT) + +/** Whether the key may be used to decrypt a message. + * + * This flag allows the key to be used for a symmetric decryption operation, + * for an AEAD decryption-and-verification operation, + * or for an asymmetric decryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_DECRYPT ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_DECRYPT) + +/** Whether the key may be used to sign a message. + * + * This flag allows the key to be used for a MAC calculation operation or for + * an asymmetric message signature operation, if otherwise permitted by the + * keys type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_SIGN_MESSAGE) + +/** Whether the key may be used to verify a message. + * + * This flag allows the key to be used for a MAC verification operation or for + * an asymmetric message signature verification operation, if otherwise + * permitted by the keys type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_VERIFY_MESSAGE) + +/** Whether the key may be used to sign a message hash. + * + * This flag allows the key to be used for an asymmetric signature operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define KEYSTORE_PSA_KEY_USAGE_SIGN_HASH ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_SIGN_HASH) + +/** Whether the key may be used to verify a message hash. + * + * This flag allows the key to be used for an asymmetric signature verification operation, + * if otherwise permitted by by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_VERIFY_HASH) + +/** Whether the key may be used to derive other keys. + */ +#define KEYSTORE_PSA_KEY_USAGE_DERIVE ((KeyStore_PSA_KeyUsage)PSA_KEY_USAGE_DERIVE) +/**@}*/ + +/** \defgroup attributes Key attributes + * @{ + */ +/** The type of a structure containing key attributes. + * + * This is an opaque structure that can represent the metadata of a key + * object. Metadata that can be stored in attributes includes: + * - The location of the key in storage, indicated by its key identifier + * and its lifetime. + * - The key's policy, comprising usage flags and a specification of + * the permitted algorithm(s). + * - Information about the key itself: the key type and its size. + * + * The actual key material is not considered an attribute of a key. + * Key attributes do not contain information that is generally considered + * highly confidential. + * + * An attribute structure can be a simple data structure where each function + * `KeyStore_PSA_setKeyXXX` sets a field and the corresponding function + * `KeyStore_PSA_getKeyXXX` retrieves the value of the corresponding field. + * However, implementations may report values that are equivalent to the + * original one, but have a different encoding. For example, an + * implementation may use a more compact representation for types where + * many bit-patterns are invalid or not supported, and store all values + * that it does not support as a special marker value. In such an + * implementation, after setting an invalid value, the corresponding + * get function returns an invalid value which may not be the one that + * was originally stored. + * + * An attribute structure may contain references to auxiliary resources, + * for example pointers to allocated memory or indirect references to + * pre-calculated values. In order to free such resources, the application + * must call KeyStore_PSA_resetKeyAttributes(). As an exception, calling + * KeyStore_PSA_resetKeyAttributes() on an attribute structure is optional if + * the structure has only been modified by the following functions + * since it was initialized or last reset with + * KeyStore_PSA_resetKeyAttributes(): + * - KeyStore_PSA_setKeyId() + * - KeyStore_PSA_setKeyLifetime() + * - KeyStore_PSA_setKeyType() + * - KeyStore_PSA_setKeyBits() + * - KeyStore_PSA_setKeyUsageFlags() + * - KeyStore_PSA_setKeyAlgorithm() + * + * Before calling any function on a key attribute structure, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * KeyStore_PSA_KeyAttributes attributes; + * memset(&attributes, 0, sizeof(attributes)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * KeyStore_PSA_KeyAttributes attributes = {0}; + * \endcode + * - Initialize the structure to the initializer + * #KEYSTORE_PSA_KEY_ATTRIBUTES_INIT, for example: \code + * KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + * \endcode + * + * A freshly initialized attribute structure contains the following + * values: + * + * - lifetime: #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE. + * - key identifier: @c 0 (which is not a valid key identifier). + * - type: @c 0 (meaning that the type is unspecified). + * - key size: @c 0 (meaning that the size is unspecified). + * - usage flags: @c 0 (which allows no usage except exporting a public + * key). + * - algorithm: @c 0 (which allows no cryptographic usage, but allows + * exporting). + * + * A typical sequence to create a key is as follows: + * -# Create and initialize an attribute structure. + * -# If the key is persistent, call KeyStore_PSA_setKeyId(). + * Also call KeyStore_PSA_setKeyLifetime() to place the key in a non-default + * location. + * -# Set the key policy with KeyStore_PSA_setKeyUsageFlags() and + * KeyStore_PSA_setKeyAlgorithm(). + * -# Set the key type with KeyStore_PSA_setKeyType(). + * -# When generating a random key with KeyStore_PSA_generateKey() or deriving a + * key with KeyStore_PSA_key_derivation_output_key(), set the desired key size + * with KeyStore_PSA_setKeyBits(). + * -# Call a key creation function: KeyStore_PSA_importKey(), + * KeyStore_PSA_generateKey(), KeyStore_PSA_key_derivation_output_key(). This + * function reads the attribute structure, creates a key with these + * attributes, and outputs a handle to the newly created key. + * -# The attribute structure is now no longer necessary. + * You may call KeyStore_PSA_resetKeyAttributes(), although this is optional + * with the workflow presented here because the attributes currently + * defined in this specification do not require any additional resources + * beyond the structure itself. + * + * A typical sequence to query a key's attributes is as follows: + * -# Call KeyStore_PSA_getKeyAttributes(). + * -# Call `KeyStore_PSA_get_key_xxx` functions to retrieve the attribute(s) + * that you are interested in. + * -# Call KeyStore_PSA_resetKeyAttributes() to free any resources that may be + * used by the attribute structure. + * + * Once a key has been created, it is impossible to change its attributes. + */ +typedef psa_key_attributes_t KeyStore_PSA_KeyAttributes; +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + /** A Key owner is a PSA partition identifier. This definition follow + * 'psa_key_owner_id_t' from crypto_platform.h */ + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) +/* Building for the PSA Crypto service on a PSA platform. */ +/* A key owner is a PSA partition identifier. */ +typedef mbedtls_key_owner_id_t KeyStore_PSA_key_owner_id_t; + +typedef psa_key_id_t KeyStore_PSA_keyID; + #endif /* defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) */ + +typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; + + #define KEYSTORE_PSA_KEY_ATTRIBUTES_INIT PSA_KEY_ATTRIBUTES_INIT + + /** Macro to assign and get keyID + * + * It depends on MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER to assign keyID and + * owner if multiple partition supported by mbedtls + */ + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + #define GET_KEY_ID(keyID, ID) \ + keyID.MBEDTLS_PRIVATE(key_id) = ID; \ + keyID.MBEDTLS_PRIVATE(owner) = KEYSTORE_PSA_DEFAULT_OWNER; + + #define SET_KEY_ID(ID, keyID) ID = keyID.MBEDTLS_PRIVATE(key_id) + #else + #define GET_KEY_ID(keyID, ID) keyID = ID + + #define SET_KEY_ID(ID, keyID) ID = keyID + #endif /* defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) */ + +#else + +typedef psa_key_id_t KeyStore_PSA_keyID; + +/** Encoding of identifiers of persistent keys for client side. + * + * - Applications may freely choose key identifiers in the range + * #KEYSTORE_PSA_KEY_ID_USER_MIN to #KEYSTORE_PSA_KEY_ID_USER_MAX + * - Implementations may define additional key identifiers in the range + * #KEYSTORE_PSA_KEY_ID_VENDOR_MIN to #KEYSTORE_PSA_KEY_ID_VENDOR_MAX. + * - 0 is reserved as an invalid key identifier. + * - Key identifiers outside these ranges are reserved for future use. + */ +typedef mbedtls_svc_key_id_t KeyStore_PSA_KeyFileId; + + /** Macro to assign and get keyID */ + #define GET_KEY_ID(keyID, ID) keyID = ID + #define SET_KEY_ID(ID, keyID) ID = keyID + + #define KEYSTORE_PSA_KEY_ATTRIBUTES_INIT PSA_CLIENT_KEY_ATTRIBUTES_INIT +#endif /* #if (TFM_ENABLED == 0) || defined(TFM_BUILD) */ +/**@}*/ + +/**@}*/ + +/** + * Starting address of Pre-provisioned keys. + * + * The Immutable platform Root of Trust stores the pre-provisioned key's programmed at + * production. SKS implementation will read this address to obtain the + * KeyStore_PSA_KeyFileId and other relevant meta data of all the pre-provisioned keys stored at this address + */ +#define KEYSTORE_PSA_PREPROVISIONED_AREA_ADDR 0x0000 +/** + * @brief Area size for pre-provisioned keys, 2KB - 256B (reserved for attestation data) + */ +#define KEYSTORE_PSA_PREPROVISIONED_AREA_SIZE (0x700) /* 1792 B */ + +/** + * @brief Macro to indicate empty pre-provisioned key memory + */ +#define KEYSTORE_PSA_PREPROVISIONED_KEYS_EMPTY 0xFFFF + +/** + * @brief Pre-provisioned key storage magic header. + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER "HUK\0KEY" +#define KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END 0 +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEY_MAGIC_HEADER)) +#define KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END_LENGTH (sizeof(KEYSTORE_PSA_PRE_PROVISIONED_KEYS_END)) +#define KEYSTORE_PSA_MAX_PREPROVISIONED_KEYS 0x10 + +/** + * @brief Pre-provisioned key Lifetime + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_VALID_LIFETIME 0xAAAA +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_INVALID_LIFETIME 0x8888 + +/** + * @brief Admissible key ID range for Pre-provisioned keys + * + * 0x7fff0000 - 0x7fffefff is reserved to store pre-provisioned keys. + */ +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX MBEDTLS_PSA_KEY_ID_BUILTIN_MAX +#define KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + +/** + * @brief Declare a key as persistent and set its key identifier. + * + * If the attribute structure currently declares the key as volatile (which + * is the default content of an attribute structure), this function sets + * the lifetime attribute to #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * KeyStore_PSA_import_key(), KeyStore_PSA_generate_key(), + * KeyStore_PSA_key_derivation_output_key() or KeyStore_PSA_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param key The persistent identifier for the key. + */ +void KeyStore_PSA_setKeyId(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyFileId key); + +/** + * @brief Set the location of a persistent key. + * + * To make a key persistent, you must give it a persistent key identifier + * with KeyStore_PSA_setKeyId(). By default, a key that has a persistent + * identifier is stored in the default storage area identifier by + * #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT. Call this function to choose a storage + * area, or to explicitly declare the key as volatile. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * KeyStore_PSA_import_key(), KeyStore_PSA_generate_key(), + * KeyStore_PSA_key_derivation_output_key() or KeyStore_PSA_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param lifetime The lifetime for the key. + * If this is #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE, the + * key will be volatile, and the key identifier + * attribute is reset to 0. + */ +void KeyStore_PSA_setKeyLifetime(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyLifetime lifetime); + +/** + * @brief Retrieve the key identifier from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The persistent identifier stored in the attribute structure. + * This value is unspecified if the attribute structure declares + * the key as volatile. + */ +KeyStore_PSA_KeyFileId KeyStore_PSA_getKeyId(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Retrieve the lifetime from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The lifetime value stored in the attribute structure. + */ +KeyStore_PSA_KeyLifetime KeyStore_PSA_getKeyLifetime(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare usage flags for a key. + * + * Usage flags are part of a key's usage policy. They encode what + * kind of operations are permitted on the key. For more details, + * refer to the documentation of the type #KeyStore_PSA_KeyUsage. + * + * This function overwrites any usage flags + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param usageFlags The usage flags to write. + */ +void KeyStore_PSA_setKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyUsage usageFlags); + +/** + * @brief Retrieve the usage flags from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The usage flags stored in the attribute structure. + */ +KeyStore_PSA_KeyUsage KeyStore_PSA_getKeyUsageFlags(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare the permitted algorithm policy for a key. + * + * The permitted algorithm policy of a key encodes which algorithm or + * algorithms are permitted to be used with this key. The following + * algorithm policies are supported: + * - 0 does not allow any cryptographic operation with the key. The key + * may be used for non-cryptographic actions such as exporting (if + * permitted by the usage flags). + * - An algorithm value permits this particular algorithm. + * + * This function overwrites any algorithm policy + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param alg The permitted algorithm policy to write. + */ +void KeyStore_PSA_setKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_Algorithm alg); + +/** + * @brief Retrieve the algorithm policy from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The algorithm stored in the attribute structure. + */ +KeyStore_PSA_Algorithm KeyStore_PSA_getKeyAlgorithm(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Declare the type of a key. + * + * This function overwrites any key type + * previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param type The key type to write. + * If this is 0, the key type in @p attributes + * becomes unspecified. + */ +void KeyStore_PSA_setKeyType(KeyStore_PSA_KeyAttributes *attributes, KeyStore_PSA_KeyType type); + +/** + * @brief Declare the size of a key. + * + * This function overwrites any key size previously set in @p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * @param [out] attributes The attribute structure to write to. + * @param bits The key size in bits. + * If this is 0, the key size in @p attributes + * becomes unspecified. Keys of size 0 are + * not supported. + */ +void KeyStore_PSA_setKeyBits(KeyStore_PSA_KeyAttributes *attributes, size_t bits); + +/** + * @brief Retrieve the key type from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The key type stored in the attribute structure. + */ +KeyStore_PSA_KeyType KeyStore_PSA_getKeyType(KeyStore_PSA_KeyAttributes *attributes); + +/** @brief Retrieve the key size from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * @param [in] attributes The key attribute structure to query. + * + * @return The key size stored in the attribute structure, in bits. + */ +size_t KeyStore_PSA_getKeyBits(KeyStore_PSA_KeyAttributes *attributes); + +/** @brief Reset a key attribute structure to a freshly initialized state. + * + * You must initialize the attribute structure as described in the + * documentation of the type #KeyStore_PSA_KeyAttributes before calling this + * function. Once the structure has been initialized, you may call this + * function at any time. + * + * This function frees any auxiliary resources that the structure + * may contain. + * + * @param [in,out] attributes The attribute structure to reset. + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Export a public key or the public part of a key pair in binary + * format. + * + * The output of this function can be passed to KeyStore_PSA_importKey() to + * create an object that is equivalent to the public key. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * - For elliptic curve public keys, the format for: + * - Montgomery curves (curve types `PSA_ECC_CURVE_CURVEXXX`), is + * - `x_P` as a `ceiling(m/8)`-byte string, little-endian; + * - Weierstrass curves (curve types `PSA_ECC_CURVE_SECTXXX`, + * `PSA_ECC_CURVE_SECPXXX` and `PSA_ECC_CURVE_BRAINPOOL_PXXX`), is the + * uncompressed representation defined by SEC1 §2.3.3 as the content of + * an ECPoint. Let `m` be the bit size associated with the curve, i.e. the + * bit size of `q` for a curve over `F_q`. The representation consists of: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. + * - For Diffie-Hellman key exchange public keys, + * the format is the representation of the public key `y = g^x mod p` as a + * big-endian byte string. The length of the byte string is the length of + * the base prime `p` in bytes. + * + * Exporting a public key object or the public part of a key pair is + * always permitted, regardless of the key's usage flags. + * + * @param [in] key Key file ID of the key to export. + * @param [out] data Buffer where the key data is to be written. + * @param [in] dataSize Size of the @p data buffer in bytes. + * @param [out] dataLength On success, the number of bytes + * that make up the key data. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT + * The key is neither a public key nor a key pair. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL + * The size of the @p data buffer is too small. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength); + +/** + * @brief Export a key in binary format. + * + * The key must designated as exportable. The output of this function can be + * passed to KeyStore_PSA_importKey() to create an equivalent object. + * + * If the implementation of KeyStore_PSA_importKey() supports other formats + * beyond the format specified here, the output from KeyStore_PSA_exportKey() + * must use the representation specified here, not the original + * representation. + * + * For standard key types, the output format is as follows: + * + * - For symmetric keys (including MAC keys), the format is the + * raw bytes of the key. + * + * - For elliptic curve key pairs, the format is + * a representation of the private value as a `ceiling(m/8)`-byte string + * where `m` is the bit size associated with the curve, i.e. the bit size + * of the order of the curve's coordinate field. This byte string is + * in little-endian order for Montgomery curves (curve types + * `PSA_ECC_CURVE_CURVEXXX`), and in big-endian order for Weierstrass + * curves (curve types `PSA_ECC_CURVE_SECTXXX`, `PSA_ECC_CURVE_SECPXXX` + * and `PSA_ECC_CURVE_BRAINPOOL_PXXX`). + * This is the content of the `privateKey` field of the `ECPrivateKey` + * format defined by RFC 5915. + * - For Diffie-Hellman key exchange key pairs, the + * format is the representation of the private key `x` as a big-endian + * byte string. The length of the byte string is the private key size in + * bytes (leading zeroes are not stripped). + * - For public keys, the format is the same as for KeyStore_PSA_exportPublicKey(). + * + * This function can also be used to export other sensitive data, such as + * certificates using its corresponding key file ID. + * + * The policy on the key must have the usage flag #KEYSTORE_PSA_KEY_USAGE_EXPORT + * set. + * + * @param [in] key Key file ID of the key to export. + * @param [out] data Buffer where the key data is to be written. + * @param [in] dataSize Size of the @p data buffer in bytes. + * @param [out] dataLength On success, the number of bytes + * that make up the key data. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key does not have the #KEYSTORE_PSA_KEY_USAGE_EXPORT flag. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * @retval #KEYSTORE_PSA_STATUS_BUFFER_TOO_SMALL + * The size of the @p data buffer is too small. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength); + +/** + * @brief Import a key in binary format. + * + * This function supports any output from KeyStore_PSA_exportKey(). Refer to the + * documentation of KeyStore_PSA_exportPublicKey() for the format of public keys + * and to the documentation of KeyStore_PSA_exportKey() for the format for + * other key types. + * + * The dataLength determines the key size. The attributes may optionally + * specify a key size; in this case it must match the dataLength. A key + * size of 0 in @p attributes indicates that the key size is solely + * determined by the key data. + * + * Implementations must reject an attempt to import a key of size 0. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * This function can also be used to store other sensitive data, such as + * certificate using key type #KEYSTORE_PSA_KEY_TYPE_RAW_DATA. + * + * @param [in] attributes The attributes for the new key. + * The key size is always determined from the + * @p data buffer. + * If the key size in @p attributes is nonzero, + * it must be equal to the size from @p data. + * @param [in] data Buffer containing the key data. The content of this + * buffer is interpreted according to the type declared + * in @p attributes. + * All implementations must support at least the format + * described in the documentation + * of KeyStore_PSA_exportKey() or KeyStore_PSA_exportPublicKey() + * for the chosen type. Implementations may allow other formats, but should + * be conservative: implementations should err on the side of rejecting + * content if it may be erroneous (e.g. wrong type or truncated data). + * @param [in] dataLength Size of the @p data buffer in bytes. + * @param [out] key On success, the key file ID of the newly created key. + * @c 0 on failure. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the key is persistent, the key material and the key's metadata + * have been saved to persistent storage. + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_ALREADY_EXISTS + * This is an attempt to create a key, and there is + * already a key with the given key file identifier. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * The key type or key size is not supported, either by the + * implementation in general or in this particular persistent + * location. @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The key attributes, + * as a whole, are invalid. @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The + * key data is not correctly formatted. @retval + * #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT The size in @p attributes is nonzero + * and does not match the size of the key data. @retval + * #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY @retval + * #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE @retval + * #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE @retval + * #KEYSTORE_PSA_STATUS_STORAGE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE @retval + * #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key); + +/** @brief Retrieve the attributes of a key. + * + * This function first resets the attribute structure as with + * KeyStore_PSA_resetKeyAttributes(). It then copies the attributes of + * the given key into the given attribute structure. + * + * @note This function may allocate memory or other resources. + * Once you have called this function on an attribute structure, + * you must call KeyStore_PSA_resetKeyAttributes() to free these + * resources. + * + * @param [in] key Identifier of the key to query. + * @param [in,out] attributes On success, the attributes of the key. + * On failure, equivalent to a + * freshly-initialized structure. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_crypto_init(). It is implementation-dependent whether a failure + * to initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes); + +/** + * @brief Remove non-essential copies of key material from memory. + * + * An implementation is permitted to make additional copies of key material + * for keys that have been created with the cache policy, an implementation + * is permitted to make additional copies of the key material that are not + * in storage and not for the purpose of ongoing operations. This function + * will remove these extra copies of the key material from memory. + * + * This function is not required to remove key material from memory in any + * of the following situations: + * - The key is currently in use in a cryptographic operation. + * - The key is volatile + * + * @param [in] key Key handle to close. . + * If this is @c 0, do nothing and return @c + * KEYSTORE_PSA_STATUS_SUCCESS. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @p Handle was valid and the key material that it + * referred to has been closed. + * Alternatively, @p Handle is @c 0. + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @p handle is not a valid handle nor @c 0. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * There was an failure in communication with the cryptoprocessor. + * The key material may still be present in the cryptoprocessor. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * The storage is corrupted. Implementations shall make a best + * effort to erase key material even in this stage, however applications + * should be aware that it may be impossible to guarantee that the + * key material is not recoverable in such cases. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * An unexpected condition which is not a storage corruption or + * a communication failure occurred. The cryptoprocessor may have + * been compromised. + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key); + +/** + * @brief Destroy a key. + * + * This function destroys a key from both volatile memory and, if + * applicable, non-volatile storage. Implementations shall make a best + * effort to ensure that that the key material cannot be recovered. + * + * This function also erases any metadata such as policies and frees + * resources associated with the key. + * + * Destroying the key makes the ID invalid, and the key ID must not be used + * again by the application. + * + * If a key is currently in use in a multipart operation, then destroying + * the key will cause the multipart operation to fail. + * + * After a volatile key is destroyed, it is recommended that the + * implementation does not immediately reuse the same key ID value for a + * different key. This reduces the risk of an attack that is able to exploit + * a key identifier reuse vulnerability within an application. + * + * This function can also be used to destroy other sensitive data, such as + * certificates using its corresponding key file ID. + * + * @param [in] key Key file ID of the key to erase. + * If key ID portion is @c 0, do nothing and return @c + * KEYSTORE_PSA_STATUS_SUCCESS. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @p ID was a valid ID and the key material that it + * referred to has been erased. + * Alternatively, @p ID is @c 0. + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key cannot be erased because it is read-only, + * either due to a policy or due to physical restrictions. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @p ID is not a valid ID. + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * There was an failure in communication with the cryptoprocessor. + * The key material may still be present in the cryptoprocessor. + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * The storage is corrupted. Implementations shall make a best + * effort to erase key material even in this stage, however applications + * should be aware that it may be impossible to guarantee that the + * key material is not recoverable in such cases. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * An unexpected condition which is not a storage corruption or + * a communication failure occurred. The cryptoprocessor may have + * been compromised. + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + +/** + * @brief Make a copy of a key. + * + * Copy key material from one location to another. + * + * This function is primarily useful to copy a key from one location + * to another, since it populates a key using the material from + * another key which may have a different lifetime. + * + * This function may be used to share a key with a different party, + * subject to implementation-defined restrictions on key sharing. + * + * The policy on the source key must have the usage flag + * #KEYSTORE_PSA_KEY_USAGE_COPY set. + * This flag is sufficient to permit the copy if the key has the lifetime + * #KEYSTORE_PSA_KEY_LIFETIME_VOLATILE or #KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT. + * Some secure elements do not provide a way to copy a key without + * making it extractable from the secure element. If a key is located + * in such a secure element, then the key must have both usage flags + * #KEYSTORE_PSA_KEY_USAGE_COPY and #KEYSTORE_PSA_KEY_USAGE_EXPORT in order + * to make a copy of the key outside the secure element. + * + * The resulting key may only be used in a way that conforms to + * both the policy of the original key and the policy specified in + * the @p attributes parameter: + * - The usage flags on the resulting key are the bitwise-and of the + * usage flags on the source policy and the usage flags in @p attributes. + * - If both allow the same algorithm or wildcard-based + * algorithm policy, the resulting key has the same algorithm policy. + * - If either of the policies allows an algorithm and the other policy + * allows a wildcard-based algorithm policy that includes this algorithm, + * the resulting key allows the same algorithm. + * - If the policies do not allow any algorithm in common, this function + * fails with the status #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT. + * + * The effect of this function on implementation-defined attributes is + * implementation-defined. + * + * @param [in] source_key The key to copy. It must allow the usage + * #KEYSTORE_PSA_KEY_USAGE_COPY. If a private or secret key is + * being copied outside of a secure element it must + * also allow #KEYSTORE_PSA_KEY_USAGE_EXPORT. + * @param [in] attributes The attributes for the new key. + * They are used as follows: + * - The key type and size may be 0. If either is + * nonzero, it must match the corresponding + * attribute of the source key. + * - The key location (the lifetime and, for + * persistent keys, the key identifier) is + * used directly. + * - The policy constraints (usage flags and + * algorithm policy) are combined from + * the source key and \p attributes so that + * both sets of restrictions apply, as + * described in the documentation of this function. + * @param [out] target_key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. + * \c 0 on failure. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * @p source_key is invalid. + * @retval #KEYSTORE_PSA_STATUS_ALREADY_EXISTS + * This is an attempt to create a persistent key, and there is + * already a persistent key with the given identifier. + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT + * The lifetime or identifier in @p attributes are invalid, or + * the policy constraints on the source and specified in + * @p attributes are incompatible, or + * @p attributes specifies a key type or key size + * which does not match the attributes of the source key. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The source key does not have the #KEYSTORE_PSA_KEY_USAGE_COPY usage flag, or + * the source key is not exportable and its lifetime does not + * allow copying it to the target's lifetime. + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_MEMORY + * @retval #KEYSTORE_PSA_STATUS_INSUFFICIENT_STORAGE + * @retval #KEYSTORE_PSA_STATUS_COMMUNICATION_FAILURE + * @retval #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_STORAGE_FAILURE + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +int_fast16_t KeyStore_PSA_copyKey(KeyStore_PSA_KeyFileId source_key, + KeyStore_PSA_KeyAttributes *attributes, + KeyStore_PSA_KeyFileId *target_key); + +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_KeyStore_PSA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c new file mode 100644 index 00000000..424158c5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.c @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include /* tfm_its_init() */ + #include + #include + #include + #include + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include /* tfm_its_init() */ + #include + #include + #include /* tfm_its_init() */ + +/* Static buffer for alloc/free. The buffer size is allocated based on + * assumption of 16 largest symmetric keys (32B) and 16 largest asymmetric + * public keys (133B) that can be supported by KeyStore, with surplus bytes for + * additional calloc calls within mbedTLS. + */ +uint8_t allocBuffer[3072]; + +extern psa_status_t psa_get_and_lock_key_slot_with_policy(mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg); +/** @brief Key handle identifier from mbedTLS 'psa_key_handle_t'. */ +typedef psa_key_handle_t KeyStore_PSA_KeyHandle; +#else + #error "Unsupported DeviceFamily_Parent for CryptoKeyKeyStore_PSA_helpers" +#endif + +KeyStore_accessSemaphoreObject KeyStore_semaphoreObject = {.isAcquired = false, .isInitialized = false}; + +/* Flag to prevent multiple initialization of KeyStore driver */ +static bool isKeyStoreInitialized = false; + +/*! + * @cond NODOC + * @brief Non-public functions required by other drivers + * + * The functions may be required by other drivers and are required to + * ensure thread-safe behavior across multiple calls. + * @endcond + */ + +/* + * ======== KeyStore_acquireLock ======== + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +bool KeyStore_acquireLock(void) +#else +static inline bool KeyStore_acquireLock(void) +#endif +{ + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the KeyStore module */ + resourceAcquired = SemaphoreP_pend(&KeyStore_semaphoreObject.KeyStore_accessSemaphore, SemaphoreP_WAIT_FOREVER); + + return resourceAcquired == SemaphoreP_OK; +} + +/* + * ======== KeyStore_releaseLock ======== + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +void KeyStore_releaseLock(void) +#else +static inline void KeyStore_releaseLock(void) +#endif +{ + SemaphoreP_post(&KeyStore_semaphoreObject.KeyStore_accessSemaphore); +} + +/** \defgroup key_management Key management + * @{ + */ + +/* + * ======== KeyStore_PSA_purgeKey ======== + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_semaphoreObject.isAcquired) + { + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + } + + /* + * Only purge persistent keys, volatile keys do not have to be purged. + * Both type of keys will be destroyed after use by the application using + * KeyStore_PSA_destroyKey() + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + if (key.MBEDTLS_PRIVATE(key_id) > KEYSTORE_PSA_MAX_VOLATILE_KEY_ID) + #else + if (key > KEYSTORE_PSA_MAX_VOLATILE_KEY_ID) + #endif + { + status = psa_purge_key(key); + } +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + if ((key.MBEDTLS_PRIVATE(key_id) >= KEYSTORE_PSA_KEY_ID_USER_MIN) && + (key.MBEDTLS_PRIVATE(key_id) <= KEYSTORE_PSA_KEY_ID_USER_MAX)) + #else + if ((key >= KEYSTORE_PSA_KEY_ID_USER_MIN) && (key <= KEYSTORE_PSA_KEY_ID_USER_MAX)) + #endif + { + status = psa_purge_key(key); + } + else + { + status = KEYSTORE_PSA_STATUS_SUCCESS; + } +#endif + + if (!KeyStore_semaphoreObject.isAcquired && (status != KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE)) + { + KeyStore_releaseLock(); + } + return status; +} + +/* + * ======== KeyStore_cleanUp ======== + */ +static int_fast16_t KeyStore_cleanUp(int_fast16_t status) +{ + KeyStore_semaphoreObject.isAcquired = false; + if (status != KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE) + { + KeyStore_releaseLock(); + } + + return status; +} + +/* + * ======== KeyStore_PSA_init ======== + */ +int_fast16_t KeyStore_PSA_init(void) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!isKeyStoreInitialized) + { +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + int_fast16_t hsmStatus; + + hsmStatus = HSMLPF3_init(); + + if (hsmStatus != HSMLPF3_STATUS_SUCCESS) + { + return status; + } + + /* CC27XX requires the HSM lock before calling psa_crypto_init() because + * that function call requires a token submission. + */ + HSMLPF3_constructRTOSObjects(); + + if (!HSMLPF3_acquireLock(SemaphoreP_NO_WAIT, (uintptr_t)NULL)) + { + return KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + } + + status = KeyMgmt_psa_crypto_init(); + + HSMLPF3_releaseLock(); + +#else + mbedtls_memory_buffer_alloc_init(allocBuffer, sizeof(allocBuffer)); + + /* + * Applications may call psa_crypto_init() function more than once, + * for example in Key Store and TF-M. Once a call succeeds, + * subsequent calls are guaranteed to succeed. + */ + status = psa_crypto_init(); +#endif + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + status = tfm_its_init(); + + if (status != PSA_SUCCESS) + { +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + psa_wipe_all_key_slots(); +#endif + return KEYSTORE_PSA_STATUS_GENERIC_ERROR; + } + } + else + { + /* Error already set */ + } + + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + if (!KeyStore_semaphoreObject.isInitialized) + { + SemaphoreP_constructBinary(&KeyStore_semaphoreObject.KeyStore_accessSemaphore, 1); + KeyStore_semaphoreObject.isInitialized = true; + } + + isKeyStoreInitialized = true; + } + else + { + /* Error already set */ + } + } + else + { + status = KEYSTORE_PSA_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== KeyStore_PSA_getKey ======== + */ +int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + KeyStore_PSA_Algorithm alg, + KeyStore_PSA_KeyUsage usage) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + psa_key_context_t *slot; + psa_status_t unlockStatus; +#else + psa_key_slot_t *slot; +#endif + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* + * Reject a zero-length output buffer now, since this can never be a + * valid key representation. This way we know that data must be a valid + * pointer and we can do things like memset(data, ..., dataSize). */ + if (dataSize == 0) + { + status = PSA_ERROR_BUFFER_TOO_SMALL; + return KeyStore_cleanUp(status); + } + + /* + * Set the key to empty now, so that even when there are errors, we always + * set dataLength to a value between 0 and dataSize. On error, setting + * the key to empty is a good choice because an empty key representation is + * unlikely to be accepted anywhere. */ + *dataLength = 0; + + /* Fetch key slot from key storage. */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + status = psaInt_KeyMgmtGetAndLockKey(key, &slot); +#else + status = psa_get_and_lock_key_slot_with_policy(key, &slot, usage, alg); +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + /* Ignore return value for decrement of lock counter, the return value from attempting to fetch key is apt for + * application. Note that psaInt_KeyMgmtGetAndLockKey does not lock the key slot in the case that retrieving it + * was not successful - this means we do not need to release the key slot in this error condition. + */ +#if (DeviceFamily_PARENT != DeviceFamily_PARENT_CC27XX) + (void)psa_unlock_key_slot(slot); +#endif + return KeyStore_cleanUp(status); + } + + /* Access the key material then decrement lock counter on key slot */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + status = psaInt_KeyMgmtLoadKey(slot, NULL, alg, usage, data, dataSize, (uint32_t *)dataLength); + + unlockStatus = psaInt_KeyMgmtClrKeyInUse(key); + + /* Overwrite the psaInt_KeyMgmtLoadKey() status with the status of unlocking the key + * entry, if the unlock fails. We shouldn't overwrite status with unlockStatus in the + * case that the load fails but the unlock succeeds + */ + if (unlockStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + status = unlockStatus; + } +#else + psa_key_attributes_t attributes = {.MBEDTLS_PRIVATE(core) = slot->attr}; + + status = psa_export_key_internal(&attributes, slot->key.data, slot->key.bytes, data, dataSize, dataLength); + + status = psa_unlock_key_slot(slot); +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ + + return KeyStore_cleanUp(status); +} + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/* + * ======== KeyStore_PSA_getKeyAssetId ======== + */ +int_fast16_t KeyStore_PSA_getKeyAssetId(KeyStore_PSA_KeyFileId key, + uint32_t *const pAssetId, + KeyStore_PSA_Algorithm targetAlg, + KeyStore_PSA_KeyUsage targetUsage) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + psa_status_t unlockStatus; + psa_key_context_t *slot; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + /* Fetch key slot from key storage. */ + status = psaInt_KeyMgmtGetAndLockKey(key, &slot); + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + /* Note that psaInt_KeyMgmtGetAndLockKey does not lock the key slot in the case that retrieving it + * was not successful - this means we do not need to release the key slot in this error condition. + */ + return KeyStore_cleanUp(status); + } + + status = psaInt_KeyMgmtLoadKey(slot, pAssetId, targetAlg, targetUsage, NULL, 0, NULL); + + unlockStatus = psaInt_KeyMgmtClrKeyInUse(key); + + /* Overwrite the psaInt_KeyMgmtLoadKey() status with the status of unlocking the key + * entry, if the unlock fails. We shouldn't overwrite status with unlockStatus in the + * case that the load fails but the unlock succeeds + */ + if (unlockStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + status = unlockStatus; + } + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_retrieveFromKeyStore ======== + */ +int_fast16_t KeyStore_PSA_retrieveFromKeyStore(const CryptoKey *key, + uint8_t *keyBuffer, + size_t keyBufferSize, + uint32_t *keyAssetID, + KeyStore_PSA_Algorithm targetAlg, + KeyStore_PSA_KeyUsage targetUsage) + +{ + /* This function retrieves the key material to the provided keyBuffer OR provides the key asset ID to the object + * if the encoding and key location specify to do so + */ + int_fast16_t status; + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyLifetime lifetime; + KeyStore_PSA_KeyLocation location; + size_t keyBits; + size_t keyLength = 0; + + GET_KEY_ID(keyID, key->u.keyStore.keyID); + + status = KeyStore_PSA_getKeyAttributes(keyID, &attributes); + + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + keyBits = KeyStore_PSA_getKeyBits(&attributes); + lifetime = KeyStore_PSA_getKeyLifetime(&attributes); + location = KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + + if ((key->encoding == CryptoKey_KEYSTORE) && (location != KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE)) + { + status = KEYSTORE_PSA_STATUS_NOT_PERMITTED; + } + else if (location == KEYSTORE_PSA_KEY_LOCATION_LOCAL_STORAGE) + { + status = KeyStore_PSA_getKey(keyID, keyBuffer, keyBufferSize, &keyLength, targetAlg, targetUsage); + + /* If the key is an asymmetric key, then KeyStore stores it in the HSM's sub-vector format. + * The sub-vector format of a key is based on the associated curve bits, which are converted + * into a word-aligned byte value, plus some extra for sub-vector header words. + */ + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + if ((keyBits != 0) && ((keyLength == HSM_ASYM_DATA_SIZE_VWB(keyBits)) || + (keyLength == (2 * HSM_ASYM_DATA_SIZE_VWB(keyBits))))) + { + /* Nothing to do. The key length returned is expected for the asymmetric key. */ + } + else if (keyLength == key->u.keyStore.keyLength) + { + /* Nothing to do. The key length returned is expected for the symmetric key. */ + } + else + { + /* The key length returned is not expected for the given CryptoKey. */ + status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + } + } + else + { + /* Error already set */ + } + } + else if (location == KEYSTORE_PSA_KEY_LOCATION_HSM_ASSET_STORE) + { + status = KeyStore_PSA_getKeyAssetId(keyID, keyAssetID, targetAlg, targetUsage); + } + else + { + status = KEYSTORE_PSA_STATUS_NOT_SUPPORTED; + } + } + + return status; +} + +/* + * ======== KeyStore_PSA_assetPostProcessing ======== + */ +int_fast16_t KeyStore_PSA_assetPostProcessing(KeyStore_PSA_KeyFileId key) +{ + psa_status_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + psa_status_t unlockStatus; + psa_key_context_t *slot; + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyLifetime lifetime; + KeyStore_PSA_KeyPersistence persistence; + KeyStore_PSA_KeyLocation location; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_get_key_attributes(key, &attributes); + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + return KeyStore_cleanUp(status); + } + + lifetime = psa_get_key_lifetime(&attributes); + + location = KEYSTORE_PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + + /* Crypto drivers should only call this function if the location specifies + * that an asset was created by KeyStore. This is left to the drivers because of + * the special cases for drivers that use MAC or asymmetric keys. + */ + if (location != KEYSTORE_PSA_KEY_LOCATION_HSM_ASSET_STORE) + { + status = KEYSTORE_PSA_STATUS_INVALID_ARGUMENT; + return KeyStore_cleanUp(status); + } + + persistence = KEYSTORE_PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime); + + /* If the persistence is KEYSTORE_PSA_KEY_PERSISTENCE_HSM_ASSET_STORE, + * the asset has been designated to remain inside the HSM Asset Store + * until the application explicitly removes it - therefore, there is + * nothing to do for the driver's asset post processing. + */ + if (persistence == KEYSTORE_PSA_KEY_PERSISTENCE_HSM_ASSET_STORE) + { + status = KEYSTORE_PSA_STATUS_SUCCESS; + return KeyStore_cleanUp(status); + } + + /* Fetch key slot from key storage. */ + status = psaInt_KeyMgmtGetAndLockKey(key, &slot); + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + /* Note that psaInt_KeyMgmtGetAndLockKey does not lock the key slot in the case that retrieving it + * was not successful - this means we do not need to release the key slot in this error condition. + */ + return KeyStore_cleanUp(status); + } + + /* Remove the specified key from the asset store, and clear the Asset ID previously + * stored in the key slot. + */ + status = psaInt_KeyMgmtReleaseKey(slot); + + unlockStatus = psaInt_KeyMgmtClrKeyInUse(key); + + /* Overwrite the psaInt_KeyMgmtReleaseKey() status with the status of unlocking the key + * entry, if the unlock fails. We shouldn't overwrite status with unlockStatus in the + * case that the load fails but the unlock succeeds + */ + if (unlockStatus != KEYSTORE_PSA_STATUS_SUCCESS) + { + status = unlockStatus; + } + + return KeyStore_cleanUp(status); +} +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ + +/* + * ======== KeyStore_PSA_importKey ======== + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_import_key(attributes, data, dataLength, key); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_exportKey ======== + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_export_key(key, data, dataSize, dataLength); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_exportPublicKey ======== + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_export_public_key(key, data, dataSize, dataLength); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_destroyKey ======== + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + volatile uint32_t keyID; + + /* Create a copy of the key ID */ + SET_KEY_ID(keyID, key); + + if ((keyID >= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MIN) && (keyID <= KEYSTORE_PSA_PRE_PROVISIONED_KEY_ID_MAX)) + { + return KEYSTORE_PSA_STATUS_NOT_SUPPORTED; + } + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_destroy_key(key); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_getKeyAttributes ======== + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes) + +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_get_key_attributes(key, attributes); + + return KeyStore_cleanUp(status); +} + +/* + * ======== KeyStore_PSA_resetKeyAttributes ======== + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes) +{ + mbedtls_free(attributes->MBEDTLS_PRIVATE(domain_parameters)); + memset(attributes, 0, sizeof(*attributes)); +} + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/* + * ======== KeyStore_PSA_copyKey ======== + */ +int_fast16_t KeyStore_PSA_copyKey(KeyStore_PSA_KeyFileId source_key, + KeyStore_PSA_KeyAttributes *attributes, + KeyStore_PSA_KeyFileId *target_key) +{ + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + if (!KeyStore_acquireLock()) + { + status = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + return status; + } + + KeyStore_semaphoreObject.isAcquired = true; + + status = psa_copy_key(source_key, attributes, target_key); + + return KeyStore_cleanUp(status); +} + +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h new file mode 100644 index 00000000..70635cc6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_helpers.h @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file CryptoKeyKeyStore_PSA_helpers.h + * @brief CryptoKeyKeyStore driver header + * + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers_Overview + * # Overview + * The CryptoKeyKeyStore driver provides API to initialize keys and get plaintext + * keys from KeyStore. This file provides definitions that are only available to the + * the secure side, in both TF-M disabled and TF-M enabled environments. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include + +#include +#include + +#include + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include + #include + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#else + #error "Unsupported DeviceFamily_Parent for CryptoKeyKeyStore_PSA_helpers" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** KeyStore driver semaphore used to synchronize accesses to the keyStore + * + * isAcquired: used by openKey() and purgeKey() to check if the KeyStore semaphore is acquired by + * other KeyStore functions before opening and closing key handles passed to mbedTLS functions. + */ +typedef struct +{ + SemaphoreP_Struct KeyStore_accessSemaphore; + bool isInitialized; + bool isAcquired; +} KeyStore_accessSemaphoreObject; + +extern KeyStore_accessSemaphoreObject KeyStore_semaphoreObject; + +#define FLETCHER_CHECKSUM_ALGORITHM 32 /* FLETCHER-32 */ + +/** + * @brief Get the plaintext key in binary format. + * + * This function can only be called on secure side of SPM. It is used by SL crypto drivers + * to obtain plaintext keys, using keyIDs provided by non-secure application, which will be loaded onto crypto engine + * + * Implementations must reject an attempt to import a certificate of size 0. + * + * @param [in] key The key ID for the key in keystore. + * @param [out] data On success, the buffer contains the plaintext key + * @param [in] dataSize Size of the @p data buffer in bytes. It must be + * greater than or equal to the plaintext key material + * @param [out] dataLength Size of the returned key material in bytes. + * @param [in] alg Algorithm the key will be used for, it should match the orignal @p alg used to import the key. + * @param [in] usage Key usage, it must match the original @p usage used to import the key. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the key ID exists, matches the @p alg and @p usage , and the @p dataSize is sufficient + * the key is returned in @p data + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key does not have matching @p alg and @p usage + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_getKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + KeyStore_PSA_Algorithm alg, + KeyStore_PSA_KeyUsage usage); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) +/** + * @brief Attempt to acquire lock to access KeyStore. + * This function is used to synchronize drivers and the application + * when both are attempting to use KeyStore. For example, if a driver + * is retrieving key material from a key slot to perform an operation, + * it must be protected from the application making a call to + * psa_destroy_key() on that same slot. + * + * @retval true Successfully acquired lock + * @retval false Failed to acquire lock + */ +bool KeyStore_acquireLock(void); + +/** + * @brief Release lock to access KeyStore. + * + * Once done accessing KeyStore, either the CryptoKeyKeyStore_PSA_helpers APIs + * or the PSA Crypto APIs should release this lock so that other entities + * can use KeyStore. + */ +void KeyStore_releaseLock(void); + +/** + * @brief Retrieve the key in either plaintext format or as an Asset ID. + * + * This function handles the logic of retrieving a key from CC27XX KeyStore, which + * depends both on the CryptoKey encoding and the key lifetime/location. If the key + * location is #KEYSTORE_PSA_KEY_LOCATION_HSM_ASSET_STORE, then the key will be returned + * via asset ID. If the requested key was not already in the asset store upon request, it + * will be loaded before the asset ID is returned. + * + * @param [in] key Pointer to the CryptoKey object containing the encoding and keyID + * @param [out] keyBuffer Buffer in which to place the key if it is retrievable in plaintext + * @param [in] keyBufferSize Size of the provided buffer + * @param [out] keyAssetID Pointer to keyAssetID output, if the key location is HSM_ASSET_STORE + * @param [in] targetAlg Desired algorithm to use the key for. Before retrieving the key material, + * it must be verified that it is allowed to be used for a given algorithm. + * @param [in] targetUsage Desired usage of the resulting key - only necessary for symmetric keys + * that will be returned as HSM assets. Must be one of + * #KEYSTORE_PSA_KEY_USAGE_ENCRYPT or #KEYSTORE_PSA_KEY_USAGE_DECRYPT. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * @retval #KEYSTORE_PSA_STATUS_GENERIC_ERROR + * The key length retrieved from KeyStore doesn't match the expected + * length. Or, other generic error. + * @retval #KEYSTORE_PSA_STATUS_NOT_SUPPORTED + * The CryptoKey encoding has an unexpected/unsupported value. + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The key does not have matching @p alg and @p usage + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_retrieveFromKeyStore(const CryptoKey *key, + uint8_t *keyBuffer, + size_t keyBufferSize, + uint32_t *keyAssetID, + KeyStore_PSA_Algorithm targetAlg, + KeyStore_PSA_KeyUsage targetUsage); + +/** + * @brief Get the asset ID for a given key ID. + * + * This function can only be called on secure side of SPM. It is used by SL crypto drivers + * to obtain assetIDs to refer to keys in the HSM, using keyIDs provided by non-secure application. + * The asset ID can then be used directly with the HSM for a crypto operation. + * + * If the key is not already stored in the HSM's Asset Store, this function will perform that + * allocation and load before returning the new asset ID. + * + * @param [in] key The key ID for the key in keystore. + * @param [out] pAssetId On success, the asset ID for the corresponding key ID + * @param [in] targetAlg Desired algorithm to use the key for. Before retrieving the key asset, + * it must be verified that it is allowed to be used for a given algorithm. + * @param [in] targetUsage Desired usage of the resulting asset - only used for symmetric keys. Must + * be one of #KEYSTORE_PSA_KEY_USAGE_ENCRYPT or #KEYSTORE_PSA_KEY_USAGE_DECRYPT. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * If the key ID exists, the asset ID + * is returned in @p pAssetId + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_NOT_PERMITTED + * The provided pAssetId is NULL + * @retval #KEYSTORE_PSA_STATUS_BAD_STATE + * The library has not been previously initialized by + * KeyStore_PSA_init(). It is implementation-dependent whether a failure to + * initialize results in this error code. + */ +int_fast16_t KeyStore_PSA_getKeyAssetId(KeyStore_PSA_KeyFileId key, + uint32_t *const pAssetId, + KeyStore_PSA_Algorithm targetAlg, + KeyStore_PSA_KeyUsage targetUsage); + +/** + * @cond NODOC + * + * @brief Release the HSM Asset for a given key ID if the key's persistence allows. + * + * This function can only be called on secure side of SPM. It is used by SL crypto drivers + * to clear assets from the HSM Asset Store when necessary. The drivers will do this after each + * step of an HSM crypto operation utilizing assets only if the key persistence is not + * #KEYSTORE_PSA_KEY_PERSISTENCE_HSM_ASSET_STORE. Drivers should only call this function when + * KeyStore is enabled - it is only for freeing assets that the KeyStore module created. Further, + * it should only be called when the key's location is #KEYSTORE_PSA_KEY_LOCATION_HSM_ASSET_STORE. + * This is the only key location for which the driver will have used the KeyStore module to create + * the asset. + * + * @param [in] key The key ID for the key in keystore. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. The associated Asset was removed + * from HSM Asset Store, it wasn't there + * anyway, or the key's persistence required + * that it wasn't removed. + * @retval #KEYSTORE_PSA_STATUS_INVALID_ARGUMENT + * The specified key has an invalid location. + * @retval #KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE + * If the KeyStore lock cannot be acquired, the KeyStore + * module is in use elsewhere. + * @retval #KEYSTORE_PSA_STATUS_INVALID_KEY_ID + * The key identifier does not exist. + * @retval #KEYSTORE_PSA_STATUS_HARDWARE_FAILURE + * Failure in token submission process. + * @retval #KEYSTORE_PSA_STATUS_CORRUPTION_DETECTED + * The result token yielded an error. + */ +int_fast16_t KeyStore_PSA_assetPostProcessing(KeyStore_PSA_KeyFileId key); +/*! @endcond */ +#endif + +/** + * @brief Initialize the Key Store. + * + * Applications must call this function before calling any other + * function in this module. This function will initialize key + * slot memory and load the key IDs of any preprovisioned keys. + * + * @retval #KEYSTORE_PSA_STATUS_SUCCESS + * Success. + * @retval #KEYSTORE_PSA_STATUS_GENERIC_ERROR + * tfm_its_init() failed + * @retval #KEYSTORE_PSA_STATUS_DOES_NOT_EXIST + * KeyStore_PSA_getPreProvisionedKeyIDs() failed + * + */ +int_fast16_t KeyStore_PSA_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_helpers__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h new file mode 100644 index 00000000..76f11d51 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_init.h @@ -0,0 +1,126 @@ + +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_CryptoKeyKeyStore_PSA_init__include +#define ti_drivers_CryptoKeyKeyStore_PSA_init__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_KEYSTORE + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes); + +/*! + * @brief Initializes a Blank CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_BLANK_KEYSTORE + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initBlankKey(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes); + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_KEYSTORE_HSM + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initKeyHSM(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes); + +/*! + * @brief Initializes a Blank CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_BLANK_KEYSTORE_HSM + * and ready for use + * @param [in] keyID Key ID of the key in Key Store + * @param [in] keyLength Length of keying material in bytes + * @param [in] keyAttributes Pointer to the attributes for KeyStore key, + * use NULL if CryptoKey structure will not + * be used to generate keys + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t KeyStore_PSA_initBlankKeyHSM(CryptoKey *keyHandle, + KeyStore_PSA_KeyFileId keyID, + size_t keyLength, + const void *keyAttributes); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_KeyStore_PSA_init__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c new file mode 100644 index 00000000..889e53b5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_ns.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +/* CryptoKey headers */ +#include +#include +#include + +/* PSA headers from TF-M interface */ +#include +#include + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* + * ======== KeyStore_PSA_exportCommon ======== + */ +static int_fast16_t KeyStore_PSA_exportCommon(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength, + int32_t type) +{ + KeyStore_s_ExportMsg exportCommonMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + exportCommonMsg.key = key; + exportCommonMsg.data = data; + exportCommonMsg.dataSize = dataSize; + exportCommonMsg.dataLength = dataLength; + + invecs[0].base = &exportCommonMsg; + invecs[0].len = sizeof(exportCommonMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * if statement returns from secure driver can be ignored by the non-secure driver, + * the secure KeyStore driver returns are handled by the application using outvecs (ret) + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_exportPublicKey ======== + */ +int_fast16_t KeyStore_PSA_exportPublicKey(KeyStore_PSA_KeyFileId key, + uint8_t *data, + size_t dataSize, + size_t *dataLength) +{ + return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY); +} + +/* + * ======== KeyStore_PSA_exportKey ======== + */ +int_fast16_t KeyStore_PSA_exportKey(KeyStore_PSA_KeyFileId key, uint8_t *data, size_t dataSize, size_t *dataLength) +{ + return KeyStore_PSA_exportCommon(key, data, dataSize, dataLength, KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY); +} + +/* + * ======== KeyStore_PSA_destroyCommon ======== + */ +static int_fast16_t KeyStore_PSA_destroyCommon(KeyStore_PSA_KeyFileId key, int32_t type) +{ + KeyStore_s_DestroyPurgeKeyMsg destroyCommonMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + destroyCommonMsg.key = key; + + invecs[0].base = &destroyCommonMsg; + invecs[0].len = sizeof(destroyCommonMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(type, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_destroyKey ======== + */ +int_fast16_t KeyStore_PSA_destroyKey(KeyStore_PSA_KeyFileId key) +{ + return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY); +} + +/* + * ======== KeyStore_PSA_importKey ======== + */ +int_fast16_t KeyStore_PSA_importKey(KeyStore_PSA_KeyAttributes *attributes, + uint8_t *data, + size_t dataLength, + KeyStore_PSA_KeyFileId *key) +{ + KeyStore_s_ImportKeyMsg importKeyMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + importKeyMsg.attributes = &attributes->client; + importKeyMsg.key = key; + importKeyMsg.data = data; + importKeyMsg.dataLength = dataLength; + + invecs[0].base = &importKeyMsg; + invecs[0].len = sizeof(importKeyMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_purgeKey ======== + */ +int_fast16_t KeyStore_PSA_purgeKey(KeyStore_PSA_KeyFileId key) +{ + return KeyStore_PSA_destroyCommon(key, KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY); +} + +/* + * ======== KeyStore_PSA_getKeyAttributes ======== + */ +int_fast16_t KeyStore_PSA_getKeyAttributes(KeyStore_PSA_KeyFileId key, KeyStore_PSA_KeyAttributes *attributes) +{ + KeyStore_s_GetKeyAttributesMsg getKeyAttributesMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + + getKeyAttributesMsg.attributes = &attributes->client; + getKeyAttributesMsg.key = key; + + invecs[0].base = &getKeyAttributesMsg; + invecs[0].len = sizeof(getKeyAttributesMsg); + + outvecs[0].base = &ret; + outvecs[0].len = sizeof(ret); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES, invecs, outvecs); + + return ret; +} + +/* + * ======== KeyStore_PSA_resetKeyAttributes ======== + */ +void KeyStore_PSA_resetKeyAttributes(KeyStore_PSA_KeyAttributes *attributes) +{ + KeyStore_s_ResetKeyAttributesMsg resetKeyAttributeMsg; + + resetKeyAttributeMsg.attributes = &attributes->client; + + invecs[0].base = &resetKeyAttributeMsg; + invecs[0].len = sizeof(resetKeyAttributeMsg); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since ret (in outvecs) is initialized to KEYSTORE_PSA_STATUS_GENERIC_ERROR and + * will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES, invecs, outvecs); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c new file mode 100644 index 00000000..c77d8cc3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * ======== KeyStore_s_copyKeyAttributesFromClient ======== + */ +psa_status_t KeyStore_s_copyKeyAttributesFromClient(struct psa_client_key_attributes_s *clientKeyAttr, + int32_t clientId, + psa_key_attributes_t *keyAttributes) +{ + if (clientKeyAttr == NULL || keyAttributes == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + *keyAttributes = psa_key_attributes_init(); + + /* Copy core key attributes from the client core key attributes */ + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = clientKeyAttr->type; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = clientKeyAttr->lifetime; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage) = clientKeyAttr->usage; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg) = clientKeyAttr->alg; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = clientKeyAttr->bits; + + /* Use the client key id as the key_id and its partition id as the owner */ + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = clientKeyAttr->id; + keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = clientId; + + return PSA_SUCCESS; +} + +/** + * \brief Converts key attributes to client key attributes. + * Follows tfm_crypto_key_attributes_to_client() + * + * \param[in] keyAttributes Key attributes, no address verification necessary as this is always in secure side + * \param[out] clientKeyAttr Client key attributes, address location must be verified to be in non-secure memory by + * calling functions + * + * \return Return values as described in \ref psa_status_t + */ +/* + * ======== KeyStore_s_copyKeyAttributesToClient ======== + */ +static psa_status_t KeyStore_s_copyKeyAttributesToClient(const psa_key_attributes_t *keyAttributes, + struct psa_client_key_attributes_s *clientKeyAttr) +{ + if (clientKeyAttr == NULL || keyAttributes == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + struct psa_client_key_attributes_s v = {0, 0, 0, 0, 0, 0}; + *clientKeyAttr = v; + + /* Copy core key attributes from the client core key attributes */ + clientKeyAttr->type = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type); + clientKeyAttr->lifetime = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); + clientKeyAttr->usage = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage); + clientKeyAttr->alg = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg); + clientKeyAttr->bits = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits); + + /* Return the key_id as the client key id, do not return the owner */ + clientKeyAttr->id = keyAttributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id); + + return PSA_SUCCESS; +} + +/** + * \brief Copies key ID from secure side to client key ID + * + * \param[in] keyID Key ID, no address verification necessary as this is always in secure side + * \param[out] clientKeyID Client key ID, address location must be verified to be in non-secure memory by + * calling functions + * + */ +/* + * ======== KeyStore_s_copyKeyIDtoClient ======== + */ +static void KeyStore_s_copyKeyIDtoClient(KeyStore_PSA_KeyFileId *keyID, uint32_t *clientKeyID) +{ + /* Copy the keyID output from the KeyStore driver to client keyID */ + *clientKeyID = keyID->MBEDTLS_PRIVATE(key_id); +} + +/* + * ======== KeyStore_s_copyKeyIDFromClient ======== + */ +void KeyStore_s_copyKeyIDFromClient(KeyStore_PSA_KeyFileId *keyID, int32_t clientId, uint32_t *clientKeyID) +{ + /* Copy keyID from client to KeyStore driver and set the owner to the caller's ID */ + keyID->MBEDTLS_PRIVATE(key_id) = *clientKeyID; + keyID->MBEDTLS_PRIVATE(owner) = clientId; +} + +/* + * ======== KeyStore_s_getKeyAttributes ======== + */ +psa_status_t KeyStore_s_getKeyAttributes(psa_msg_t *msg) +{ + KeyStore_s_GetKeyAttributesMsg getKeyAttributesMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(getKeyAttributesMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getKeyAttributesMsg, sizeof(getKeyAttributesMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (cmse_has_unpriv_nonsecure_rw_access(getKeyAttributesMsg.attributes, + sizeof(struct psa_client_key_attributes_s)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &getKeyAttributesMsg.key); + + ret = KeyStore_PSA_getKeyAttributes(keyID, &keyAttributes); + + if (ret == KEYSTORE_PSA_STATUS_SUCCESS) + { + ret = KeyStore_s_copyKeyAttributesToClient(&keyAttributes, + (struct psa_client_key_attributes_s *) + getKeyAttributesMsg.attributes); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_importKey ======== + */ +psa_status_t KeyStore_s_importKey(psa_msg_t *msg) +{ + KeyStore_s_ImportKeyMsg importKeyMsg; + int_fast16_t ret = KEYSTORE_PSA_STATUS_RESOURCE_UNAVAILABLE; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(importKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &importKeyMsg, sizeof(importKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Validate input address range */ + if ((cmse_has_unpriv_nonsecure_rw_access(importKeyMsg.key, sizeof(KeyStore_PSA_KeyFileId)) == NULL) || + (cmse_has_unpriv_nonsecure_read_access(importKeyMsg.attributes, sizeof(KeyStore_PSA_KeyAttributes)) == + NULL) || + (cmse_has_unpriv_nonsecure_read_access(importKeyMsg.data, importKeyMsg.dataLength) == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + /* Copy keyID from application for persistent keys */ + if (importKeyMsg.attributes->lifetime) + { + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, importKeyMsg.key); + } + + ret = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)importKeyMsg.attributes, + msg->client_id, + &keyAttributes); + + if (ret == PSA_SUCCESS) + { + ret = KeyStore_PSA_importKey(&keyAttributes, importKeyMsg.data, importKeyMsg.dataLength, &keyID); + + KeyStore_s_copyKeyIDtoClient(&keyID, importKeyMsg.key); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_destroyPurgeKey ======== + */ +psa_status_t KeyStore_s_destroyPurgeKey(psa_msg_t *msg, int32_t msgType) +{ + KeyStore_s_DestroyPurgeKeyMsg destroyMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(destroyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &destroyMsg, sizeof(destroyMsg)); + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &destroyMsg.key); + + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY) + { + ret = KeyStore_PSA_destroyKey(keyID); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY) + { + ret = KeyStore_PSA_purgeKey(keyID); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_exportKey ======== + */ +psa_status_t KeyStore_s_exportKey(psa_msg_t *msg, int32_t msgType) +{ + KeyStore_s_ExportMsg exportMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(exportMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &exportMsg, sizeof(exportMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Validate input address range */ + if (cmse_has_unpriv_nonsecure_rw_access(exportMsg.data, exportMsg.dataSize) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &exportMsg.key); + + if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY) + { + ret = KeyStore_PSA_exportKey(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); + } + else if (msgType == KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY) + { + ret = KeyStore_PSA_exportPublicKey(keyID, exportMsg.data, exportMsg.dataSize, exportMsg.dataLength); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_resetKeyAttributes ======== + */ +psa_status_t KeyStore_s_resetKeyAttributes(psa_msg_t *msg) +{ + KeyStore_s_ResetKeyAttributesMsg resetKeyAttributeMsg; + KeyStore_PSA_KeyAttributes keyAttributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + + if ((msg->in_size[0] != sizeof(resetKeyAttributeMsg))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &resetKeyAttributeMsg, sizeof(resetKeyAttributeMsg)); + + KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)resetKeyAttributeMsg.attributes, + msg->client_id, + &keyAttributes); + + /* + * Following TF-M's implementation of psa_reset_key_attributes(), KeyStore_PSA_resetKeyAttributes() cannot be + * directly called from non-secure application. KeyStore S/NS interface makes a PSA call to reset the attributes + * using the function in secure partition + */ + KeyStore_PSA_resetKeyAttributes(&keyAttributes); + + KeyStore_s_copyKeyAttributesToClient(&keyAttributes, resetKeyAttributeMsg.attributes); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_getKey ======== + */ +psa_status_t KeyStore_s_getKey(psa_msg_t *msg) +{ + KeyStore_s_GetKeyMsg getKeyMsg; + int_fast16_t ret = PSA_ERROR_PROGRAMMER_ERROR; + KeyStore_PSA_KeyFileId keyID; + + if ((msg->in_size[0] != sizeof(getKeyMsg)) || (msg->out_size[0] != sizeof(ret)) || + TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getKeyMsg, sizeof(getKeyMsg)); + + KeyStore_s_copyKeyIDFromClient(&keyID, msg->client_id, &getKeyMsg.key); + + ret = KeyStore_PSA_getKey(keyID, + getKeyMsg.data, + getKeyMsg.dataSize, + getKeyMsg.dataLength, + getKeyMsg.alg, + getKeyMsg.usage); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== KeyStore_s_handlePsaMsg ======== + */ +psa_status_t KeyStore_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + switch (msg->type) + { + case KEYSTORE_PSA_S_MSG_TYPE_GET_KEY: + status = KeyStore_s_getKey(msg); + break; + /* Fall through for exporting */ + case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY: + case KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY: + status = KeyStore_s_exportKey(msg, msg->type); + break; + /* Fall through for destroying */ + case KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY: + case KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY: + status = KeyStore_s_destroyPurgeKey(msg, msg->type); + break; + case KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY: + status = KeyStore_s_importKey(msg); + break; + case KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES: + status = KeyStore_s_getKeyAttributes(msg); + break; + case KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES: + status = KeyStore_s_resetKeyAttributes(msg); + break; + default: + /* Unkown PSA message type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== KeyStore_s_init ======== + */ +void KeyStore_s_init(void) +{ + KeyStore_PSA_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h new file mode 100644 index 00000000..23d5f822 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyKeyStore_PSA_s.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file CryptoKeyKeyStore_PSA_s.h + * @brief Secure Crypto Service + * + * @anchor ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s_Overview + * # Overview + * The Secure KeyStore driver is used to access all KeyStore functions + * when using the TF-M. + * + ******************************************************************************* + */ +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include + +#include + +#include +#include + +#include +#include + +/* For client side key attribute structure */ +#include + +/* + * Crypto Key Store secure message types + */ +#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY KEYSTORE_PSA_S_MSG_TYPE(0U) +#define KEYSTORE_PSA_S_MSG_TYPE_GENERATE_KEY KEYSTORE_PSA_S_MSG_TYPE(1U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_PUBLIC_KEY KEYSTORE_PSA_S_MSG_TYPE(2U) +#define KEYSTORE_PSA_S_MSG_TYPE_EXPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(3U) +#define KEYSTORE_PSA_S_MSG_TYPE_DESTROY_KEY KEYSTORE_PSA_S_MSG_TYPE(4U) +#define KEYSTORE_PSA_S_MSG_TYPE_IMPORT_KEY KEYSTORE_PSA_S_MSG_TYPE(5U) +#define KEYSTORE_PSA_S_MSG_TYPE_PURGE_KEY KEYSTORE_PSA_S_MSG_TYPE(6U) +#define KEYSTORE_PSA_S_MSG_TYPE_GET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(7U) +#define KEYSTORE_PSA_S_MSG_TYPE_RESET_KEY_ATTRIBUTES KEYSTORE_PSA_S_MSG_TYPE(8U) + +/* + * ============ KeyStore driver Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * KeyStore secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + uint32_t key; + uint8_t *data; + size_t dataSize; + size_t *dataLength; + KeyStore_PSA_Algorithm alg; + KeyStore_PSA_KeyUsage usage; +} KeyStore_s_GetKeyMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; + KeyStore_PSA_KeyFileId *key; +} KeyStore_s_GenerateKeyMsg; + +/* Msg for KeyStore_PSA_exportKey() and KeyStore_PSA_exportPublicKey() */ +typedef struct +{ + uint32_t key; + uint8_t *data; + size_t dataSize; + size_t *dataLength; +} KeyStore_s_ExportMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; + uint8_t *data; + size_t dataLength; + uint32_t *key; +} KeyStore_s_ImportKeyMsg; + +/* Msg for KeyStore_PSA_destroyKey() and KeyStore_PSA_purgeKey() */ +typedef struct +{ + uint32_t key; +} KeyStore_s_DestroyPurgeKeyMsg; + +typedef struct +{ + uint32_t key; + struct psa_client_key_attributes_s *attributes; +} KeyStore_s_GetKeyAttributesMsg; + +typedef struct +{ + struct psa_client_key_attributes_s *attributes; +} KeyStore_s_ResetKeyAttributesMsg; + +/*! + * @brief Handles PSA messages for KeyStore secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t KeyStore_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the KeyStore secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void KeyStore_s_init(void); + +/** + * @brief Gets key attributes from client key attributes. + * Follows tfm_crypto_key_attributes_from_client() + * + * @param[in] clientKeyAttr Client key attributes, address location must be verified to be in non-secure memory by + * calling functions + * @param[in] clientId Partition ID of the calling client + * @param[out] keyAttributes Key attributes, no address verification necessary as this is always in secure side + * + * @return Always return #KEYSTORE_PSA_STATUS_SUCCESS + */ +psa_status_t KeyStore_s_copyKeyAttributesFromClient(struct psa_client_key_attributes_s *clientKeyAttr, + int32_t clientId, + psa_key_attributes_t *keyAttributes); + +/** + * @brief Copies client key ID from non-secure side to secure side + * + * @param[out] keyID Key ID, no address verification necessary as this is always in secure side + * @param[in] clientKeyID Client key ID, address location must be verified to be in non-secure memory by + * calling functions + * @param[in] clientId Client ID, partition ID from PSA call + */ +void KeyStore_s_copyKeyIDFromClient(KeyStore_PSA_KeyFileId *keyID, int32_t clientId, uint32_t *clientKeyID); +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyKeyStore_PSA_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c new file mode 100644 index 00000000..9ab22038 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include + +/* + * ======== CryptoKeyPlaintext_markAsBlank ======== + */ +int_fast16_t CryptoKeyPlaintext_markAsBlank(CryptoKey *keyHandle) +{ + keyHandle->encoding = CryptoKey_BLANK_PLAINTEXT; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_initKey ======== + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength) +{ + keyHandle->encoding = CryptoKey_PLAINTEXT; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_initBlankKey ======== + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength) +{ + + keyHandle->encoding = CryptoKey_BLANK_PLAINTEXT; + keyHandle->u.plaintext.keyMaterial = keyLocation; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLocation ======== + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location) +{ + keyHandle->u.plaintext.keyMaterial = location; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLocation ======== + */ +int_fast16_t CryptoKeyPlaintext_getKeyLocation(CryptoKey *keyHandle, uint8_t **location) +{ + *location = keyHandle->u.plaintext.keyMaterial; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_getKeyLength ======== + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length) +{ + *length = keyHandle->u.plaintext.keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintext_setKeyLength ======== + */ +int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length) +{ + keyHandle->u.plaintext.keyLength = length; + + return CryptoKey_STATUS_SUCCESS; +} + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + +/* + * ======== CryptoKeyPlaintext_initKey ======== + */ +int_fast16_t CryptoKeyPlaintextHSM_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength) +{ + keyHandle->encoding = CryptoKey_PLAINTEXT_HSM; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +/* + * ======== CryptoKeyPlaintextHSM_initBlankKey ======== + */ +int_fast16_t CryptoKeyPlaintextHSM_initBlankKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength) +{ + keyHandle->encoding = CryptoKey_BLANK_PLAINTEXT_HSM; + keyHandle->u.plaintext.keyMaterial = key; + keyHandle->u.plaintext.keyLength = keyLength; + + return CryptoKey_STATUS_SUCCESS; +} + +#endif \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h new file mode 100644 index 00000000..2717c3c3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file CryptoKeyPlaintext.h + * + * @warning This is a beta API. It may change in future releases. + * + * # Overview # + * This file contains the APIs to initialize and access plaintext CryptoKeys. + * Plaintext CryptoKeys point to keying material stored in flash or RAM and + * are not subject to enforced usage restrictions. That only means that calling + * a function that requires an asymmetric public key with a symmetric key will + * not return an error. It will likely not yield the desired results. + * + * # Usage # + * + * Plaintext keys are the simplest of the CryptoKeys. All they do is store the + * length of and a pointer to the keying material. Their use is hence simple as + * well. After calling the initialization function, the CryptoKey may be used in + * any of the crypto operation APIs that take a CryptoKey as an input. + * + * @code + * + * uint8_t keyingMaterial[16]; + * CryptoKey cryptoKey; + * + * // Initialise the CryptoKey + * CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial)); + * + * // Use the CryptoKey in another crypto operation + * + * @endcode + * + */ + +#ifndef ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include +#define ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Marks a CryptoKey as 'blank'. + * + * The CryptoKey will be unlinked from any previously connected keying material + * + * @param [in] keyHandle Pointer to a CryptoKey + * + * @return Returns a status code + */ +int_fast16_t CryptoKeyPlaintext_markAsBlank(CryptoKey *keyHandle); + +/*! + * @brief Initializes a CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_PLAINTEXT + * and ready for use + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); + +/*! + * @brief Initializes an empty plaintext CryptoKey type + * + * @param [in] keyHandle Pointer to a CryptoKey which will be + * initialized to type + * CryptoKey_BLANK_PLAINTEXT + * + * @param [in] keyLocation Pointer to location where plaintext keying + * material can be stored + * + * @param [in] keyLength Length of keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_initBlankKey(CryptoKey *keyHandle, uint8_t *keyLocation, size_t keyLength); + +/*! + * @brief Sets the CryptoKey keyMaterial pointer + * + * Updates the key location for a plaintext CryptoKey. + * Does not modify data at the pointer location. + * + * @param [out] keyHandle Pointer to a plaintext CryptoKey who's key + * data pointer will be modified + * + * @param [in] location Pointer to key data location + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey *keyHandle, uint8_t *location); + +/*! + * @brief Gets the CryptoKey keyMaterial pointer + * + * @param [in] keyHandle Pointer to an initialized plaintext CryptoKey + * + * @param [out] location Pointer to key data location + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLocation(CryptoKey *keyHandle, uint8_t **location); + +/*! + * @brief Gets the length of a plaintext key + * + * @param [in] keyHandle Pointer to a plaintext CryptoKey + * + * @param [out] length Length of the keying material, in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey *keyHandle, size_t *length); +/*! + * @brief Sets the length of a plaintext key + * + * @param [out] keyHandle Pointer to a CryptoKey + * + * @param [in] length Length value in bytes to update + * @c keyHandle with + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintext_setKeyLength(CryptoKey *keyHandle, size_t length); + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) +/*! + * @brief Initializes a CryptoKey type with HSM + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_PLAINTEXT_HSM + * and ready for use + * + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintextHSM_initKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); + +/*! + * @brief Initializes an empty plaintext CryptoKey type with HSM + * + * @param [in] keyHandle Pointer to a CryptoKey which will be initialized + * to type CryptoKey_BLANK_PLAINTEXT_HSM + * and ready for use + * + * @param [in] key Pointer to keying material + * + * @param [in] keyLength Length of keying material in bytes + * + * @return Returns a status code from CryptoKey.h + */ +int_fast16_t CryptoKeyPlaintextHSM_initBlankKey(CryptoKey *keyHandle, uint8_t *key, size_t keyLength); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_cryptokey_CryptoKeyPlaintext__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.c new file mode 100644 index 00000000..7b7a4156 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +/* + * ======== ECCInitCC26X1_NISTP256 ======== + */ +void ECCInitCC26X1_NISTP256(ECC_State *state, uint8_t windowSize, uint32_t *workZone) +{ + state->data_Gx = ECC_NISTP256_generatorX.word; + state->data_Gy = ECC_NISTP256_generatorY.word; + state->data_p = ECC_NISTP256_prime.word; + state->data_r = ECC_NISTP256_order.word; + state->data_a = ECC_NISTP256_a.word; + state->data_b = ECC_NISTP256_b.word; + state->data_a_mont = ECC_NISTP256_a_mont.word; + state->data_b_mont = ECC_NISTP256_b_mont.word; + state->data_k_mont = ECC_NISTP256_k_mont.word; + state->win = windowSize; + + state->workzone = workZone; +} + +/* + * ======== ECCInitCC26X1_Curve25519 ======== + */ +void ECCInitCC26X1_Curve25519(ECC_State *state, uint8_t windowSize, uint32_t *workZone) +{ + state->data_Gx = ECC_Curve25519_generatorX.word; + state->data_Gy = ECC_Curve25519_generatorY.word; + state->data_p = ECC_Curve25519_prime.word; + state->data_r = ECC_Curve25519_order.word; + state->data_a = ECC_Curve25519_a.word; + state->data_b = ECC_Curve25519_b.word; + /* The following montgomery curve params are not used for any Curve25519 functions */ + state->data_a_mont = NULL; + state->data_b_mont = NULL; + state->data_k_mont = NULL; + state->win = windowSize; + + state->workzone = workZone; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.h new file mode 100644 index 00000000..4bbb3a92 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCInitCC26X1.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCInitCC26X1__include +#define ti_drivers_cryptoutils_ecc_ECCInitCC26X1__include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initializes the ECC state with NIST P256 curve params. + * + * @note If a windowSize of 3 is selected, ECC_initialize() ROM function should + * be called instead of this function to reduce code size. + * + * @param state Points to ECC state. + * @param windowSize ECC SW window size used for computations. + * @param workZone Points to ECC workzone buffer. + */ +void ECCInitCC26X1_NISTP256(ECC_State *state, uint8_t windowSize, uint32_t *workZone); + +/*! + * @brief Initializes the ECC state with Curve25519 curve params. + * + * @param state Points to ECC state. + * @param windowSize ECC SW window size used for computations. + * @param workZone Points to ECC workzone buffer. + */ +void ECCInitCC26X1_Curve25519(ECC_State *state, uint8_t windowSize, uint32_t *workZone); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCInitCC26X1__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParams.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParams.h new file mode 100644 index 00000000..6cc6f5fc --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParams.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECCParams.h + * + * This file contains a common definition for elliptic curve structures used + * throughout the ECC based drivers. Not all devices support every curve. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCParams__include +#define ti_drivers_cryptoutils_ecc_ECCParams__include + +#include +#include +#include + +#include +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error status codes for the utility functions */ + +/*! + * @brief Successful status code. + * + * Function return ECCParams_STATUS_SUCCESS if the control code was executed + * successfully. + */ +#define ECCParams_STATUS_SUCCESS (0) + +/*! + * @brief Generic error status code. + * + * Functions return ECCParams_STATUS_ERROR if the control code was not executed + * successfully. + */ +#define ECCParams_STATUS_ERROR (-1) + +/*! + * @brief Enumeration of curve equations supported. + * + * Elliptic curves can be expressed using multiple equations of polynomials over + * finite fields. + * All forms can be converted to one another using parameter substitution. + * Each curve has a default curve equations it was designed to use. + * + * Some curve implementations have restrictions on which algorithms and schemes + * they work with. For example, Curve25519 was explicitely designed with ECDH in mind. + * It only uses and yields the X coordinate of a point on the elliptic curve in common + * implementations. Some implementations do provide X and Y affine coordinates but most + * do not. + * Therefore, ECDSA and ECJPAKE do not have compatible implementations + * for Curve25519 on some devices as the Y coordinate is required by them. + * + * Check the header files of each device-specific implementation for information + * regarding curve-support for specific schemes on a device. + * + * | Name | Equation | + * |-------------------|-------------------------------| + * | Short Weierstrass | y^2 = x^3 + a*x + b mod p | + * | Montgomery | By^2 = x^3 + Ax^2 + x mod p | + * | Edwards | x^2 + y^2 = 1 + dx^2y^2 mod p | + * + */ +typedef uint32_t ECCParams_CurveType; + +#define ECCParams_CURVE_TYPE_NONE 0U +#define ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3 1U +#define ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_GEN 2U +#define ECCParams_CURVE_TYPE_MONTGOMERY 3U +#define ECCParams_CURVE_TYPE_EDWARDS 4U + +/*! + * @brief Enumeration of ECC curve names supported by TF-M. + */ +typedef enum +{ + /* + * WARNING: Do not alter the order or contents of this enum without updating + * the corresponding curveParamTable array in ECCParamCC26X4_s.c + */ + ECCParams_SecureCurve_NISTP224 = 0, + ECCParams_SecureCurve_NISTP256, + ECCParams_SecureCurve_NISTP384, + ECCParams_SecureCurve_NISTP521, + ECCParams_SecureCurve_BrainpoolP256R1, + ECCParams_SecureCurve_BrainpoolP384R1, + ECCParams_SecureCurve_BrainpoolP512R1, + ECCParams_SecureCurve_Curve25519, + ECCParams_SecureCurve_Ed25519, + ECCParams_SecureCurve_Wei25519, + ECCParams_SecureCurve_COUNT /* This element denotes the max enum value and is not a valid curve */ +} ECCParams_SecureCurve; + +/* + * ECCParams_CurveParams have different struct members depending on the context + * of the build (Secure-only, Non-secure, or Secure) + */ +#if (TFM_ENABLED == 0) || defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + +/*! + * @brief A structure containing the parameters of an elliptic curve. + * + * Elliptical Curve Cryptography (ECC) prime curve parameters. + */ + +typedef struct ECCParams_CurveParams +{ + const ECCParams_CurveType curveType; + const uint8_t *prime; + const uint8_t *a; + const uint8_t *b; + const uint8_t *order; + const uint8_t cofactor; + const size_t length; + const uint8_t *generatorX; + const uint8_t *generatorY; +} ECCParams_CurveParams; + +#else + +/*! + * @brief A structure containing the curve name to reference elliptic curve + * parameters stored in secure memory. + */ +typedef struct ECCParams_CurveParams +{ + ECCParams_SecureCurve secureCurve; +} ECCParams_CurveParams; + +#endif /* (TFM_ENABLED == 0) || defined(TFM_BUILD) */ + +#if defined(TFM_BUILD) /* TFM_BUILD indicates this is a TF-M build */ + +/*! + * @brief A structure containing the curve name to reference elliptic curve + * parameters stored in secure memory. + */ +/* This must match the ECCParams_CurveParams struct definition directly above */ +typedef struct ECCParams_ns_CurveParams +{ + ECCParams_SecureCurve secureCurve; +} ECCParams_ns_CurveParams; + +#endif /* defined(TFM_BUILD) */ + +/* Short Weierstrass curves */ + +/*! + * + * @brief The NISTP192 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP192; + +/*! + * + * @brief The NISTP224 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP224; + +/*! + * + * @brief The NISTP256 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP256; + +/*! + * + * @brief The NISTP384 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP384; + +/*! + * + * @brief The NISTP521 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_NISTP521; + +/*! + * + * @brief The BrainpoolP256R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP256R1; + +/*! + * + * @brief The BrainpoolP384R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP384R1; + +/*! + * + * @brief The BrainpoolP512R1 curve in short Weierstrass form. + * + */ +extern const ECCParams_CurveParams ECCParams_BrainpoolP512R1; + +/*! + * @brief A short Weierstrass equivalent representation of Ed25519. + */ +extern const ECCParams_CurveParams ECCParams_Wei25519; + +/* Montgomery curves */ + +/*! + * @brief The Curve25519 curve in Montgomery form. + */ +extern const ECCParams_CurveParams ECCParams_Curve25519; + +/* Edwards curves */ + +/*! + * @brief The Ed25519 curve in Edwards form. + */ +extern const ECCParams_CurveParams ECCParams_Ed25519; + +/*! + * @brief Number of bytes for the length word prepended before all parameters + * passed into the ECC SW library functions. + */ +#define ECC_LENGTH_PREFIX_BYTES 4 + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) + + /*! + * @defgroup nistp256_params NIST P256 curve params to be used with ECC SW library + * Note: CC26X1 uses NIST P256 curve params defined in driverlib/rom_ecc.h + * @{ + */ + + /*! + * @brief Length of NIST P256 curve parameters in bytes + */ + #define ECCParams_NISTP256_LENGTH 32 + + /*! + * @brief Length in bytes of NISTP256 curve parameters including the prepended + * length word. + */ + #define ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES (ECCParams_NISTP256_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_NISTP256 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_NISTP256_PARAM_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_NISTP256_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_prime; + +/*! + * @brief 'a' constant of the ECC_NISTP256 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP256_Param ECC_NISTP256_a; + +/*! + * @brief 'b' constant of the ECC_NISTP256 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP256_Param ECC_NISTP256_b; + +/*! + * @brief Order of the generator point of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_order; + +/*! + * @brief 'k' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_k_mont; + +/*! + * @brief 'a' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_a_mont; + +/*! + * @brief 'b' in Montgomery domain of the ECC_NISTP256 curve. + */ +extern const ECC_NISTP256_Param ECC_NISTP256_b_mont; + + /*! @} */ /* end of nistp256_params */ + + /*! + * @defgroup nistp224_params NIST P224 curve params to be used with ECC SW library + * @{ + */ + + /*! + * @brief Length of NIST P224 curve parameters in bytes + */ + #define ECCParams_NISTP224_LENGTH 28 + + /*! + * @brief Length in bytes of NISTP256 curve parameters including the prepended + * length word. + */ + #define ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES (ECCParams_NISTP224_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_NISTP256 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_NISTP224_PARAM_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_NISTP224_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_prime; + +/*! + * @brief 'a' constant of the ECC_NISTP224 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP224_Param ECC_NISTP224_a; + +/*! + * @brief 'b' constant of the ECC_NISTP224 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_NISTP224_Param ECC_NISTP224_b; + +/*! + * @brief Order of the generator point of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_order; + +/*! + * @brief 'k' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_k_mont; + +/*! + * @brief 'a' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_a_mont; + +/*! + * @brief 'b' in Montgomery domain of the ECC_NISTP224 curve. + */ +extern const ECC_NISTP224_Param ECC_NISTP224_b_mont; + + /*! @} */ /* end of nistp224_params */ + + /* Octet string format requires an extra byte at the start of the public key */ + #define OCTET_STRING_OFFSET 1 + + /* Octet string format requires this value in the first byte of the public key */ + #define OCTET_STRING_PREFIX 0x04 + + /* Length of offset in bytes */ + #define ECC_LENGTH_OFFSET_BYTES 4 + + /* Param length needs to be equal to the length of the largest curve supported plus length offset bytes */ + #define ECC_PARAM_LENGTH_WITH_OFFSET_BYTES (ECCParams_NISTP256_LENGTH + ECC_LENGTH_OFFSET_BYTES) + +/*! + * @brief Union to format inputs to ECC library. + */ +typedef union +{ + uint32_t word[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES / sizeof(uint32_t)]; + uint8_t byte[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES]; +} ECC_Param; + +#endif /* (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC27XX) \ + || (DeviceFamily_PARENT == DeviceFamily_PARENT_CC35XX) */ + +/*! + * @brief Length of Curve25519 curve parameters in bytes + */ +#define ECCParams_CURVE25519_LENGTH 32 + +/*! + * @defgroup curve25519_params Curve25519 curve params to be used with ECC SW library + * @{ + */ + +/*! + * @brief Length in bytes of Curve25519 curve parameters including the prepended + * length word. + */ +#define ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES (ECCParams_CURVE25519_LENGTH + ECC_LENGTH_PREFIX_BYTES) + +/*! + * @brief Union to access ECC_Curve25519 curve params in bytes or words. + */ +typedef union +{ + uint8_t byte[ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES]; + uint32_t word[ECC_CURVE25519_LENGTH_WITH_PREFIX_BYTES / sizeof(uint32_t)]; +} ECC_Curve25519_Param; + +/*! + * @brief X coordinate of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_generatorX; + +/*! + * @brief Y coordinate of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_generatorY; + +/*! + * @brief Prime of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_prime; + +/*! + * @brief 'a' constant of the ECC_Curve25519 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_Curve25519_Param ECC_Curve25519_a; + +/*! + * @brief 'b' constant of the ECC_Curve25519 curve when expressed in short + * Weierstrass form (y^2 = x^3 + a*x + b). + */ +extern const ECC_Curve25519_Param ECC_Curve25519_b; + +/*! + * @brief Order of the generator point of the ECC_Curve25519 curve. + */ +extern const ECC_Curve25519_Param ECC_Curve25519_order; + +/*! @} */ /* end of curve25519_params */ + +/* Utility functions */ + +/* #define used for backwards compatibility */ +#define ECCParams_FormatCurve25519PrivateKey ECCParams_formatCurve25519PrivateKey + +/*! + * @brief Formats a CryptoKey to conform to Curve25519 private key requirements. + * + * Curve25519 has specific private key requirements specified by the curve definition. + * Specifically, the bottom three and the top bit may not be set and the second to + * last bit must be set. + * + * @param myPrivateKey An initialized CryptoKey describing the entropy for a + * Curve25519 private key. Platform-specific restrictions + * for the location of the keying material apply. Some + * implementations do not support modifying keying material + * in flash for example. + * + * @pre Initialize the CryptoKey with a 32-byte buffer in a compliant location. + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey); + +/*! + * @brief Extracts the curve generator point from an ecliptic curve description. + * + * The curve parameters #ECCParams_CurveParams::generatorX and + * #ECCParams_CurveParams::generatorY are extracted from \c curveParams and + * written as a concatenated octet string in big endian order to + * \c buffer. The format is defined in SEC 1: Elliptic Curve Cryptography section + * 2.3.3. + * + * The curve point has the format ``0x04 || X || Y`` and the length is + * ``2 * size_of_x_or_y + 1`` where ``0x04`` specifies octet string format. + * If the buffer \c length exceeds the curve point length, the remaining + * buffer space is zeroed. + * + * @param curveParams Points to the input curve parameters + * @param buffer Points to the destination where the generator point will + * be written to. Make sure that \c buffer is large enough to + * hold + * @param length Maximum length of \c buffer in bytes. + * + * @retval #ECCParams_STATUS_SUCCESS on success, #ECCParams_STATUS_ERROR if the + * provided buffer \c length is insufficient to hold the curve point. + * + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCParams__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X1.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X1.c new file mode 100644 index 00000000..fae3a7a5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X1.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2020-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsCC26X1.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on CC26X1 devices. + */ + +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +/* + * NIST P256 curve params in little endian format. + * byte[0-3] are the param length word as required by the ECC SW library. + * byte[4] is the least significant byte of the curve parameter. + * + * NOTE: NIST P256 curve params are in ROM for CC26X1. + */ +const ECCParams_CurveParams ECCParams_NISTP256 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = ECC_NISTP256_PARAM_LENGTH_BYTES, + .prime = ECC_NISTP256_prime.byte, + .order = ECC_NISTP256_order.byte, + .a = ECC_NISTP256_a.byte, + .b = ECC_NISTP256_b.byte, + .generatorX = ECC_NISTP256_generatorX.byte, + .generatorY = ECC_NISTP256_generatorY.byte, + .cofactor = 1}; + +/* + * Curve25519 curve params in little endian format. + * byte[0-3] are the param length word as required by the ECC SW library. + * byte[4] is the least significant byte of the curve parameter. + */ +const ECC_Curve25519_Param ECC_Curve25519_generatorX = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_generatorY = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}; + +const ECC_Curve25519_Param ECC_Curve25519_prime = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const ECC_Curve25519_Param ECC_Curve25519_a = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_b = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECC_Curve25519_Param ECC_Curve25519_order = { + .byte = {0x08, 0x00, 0x00, 0x00, /* Length word prefix */ + 0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; + +const ECCParams_CurveParams ECCParams_Curve25519 = {.curveType = ECCParams_CURVE_TYPE_MONTGOMERY, + .length = ECCParams_CURVE25519_LENGTH, + .prime = ECC_Curve25519_prime.byte, + .order = ECC_Curve25519_order.byte, + .a = ECC_Curve25519_a.byte, + .b = ECC_Curve25519_b.byte, + .generatorX = ECC_Curve25519_generatorX.byte, + .generatorY = ECC_Curve25519_generatorY.byte, + .cofactor = 1}; + +/* + * ======== ECCParams_formatCurve25519PrivateKey ======== + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey) +{ + myPrivateKey->u.plaintext.keyMaterial[31] &= 0xF8; + myPrivateKey->u.plaintext.keyMaterial[0] &= 0x7F; + myPrivateKey->u.plaintext.keyMaterial[0] |= 0x40; + + return ECCParams_STATUS_SUCCESS; +} + +/* + * ======== ECCParams_getUncompressedGeneratorPoint ======== + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length) +{ + + size_t paramLength = curveParams->length; + size_t pointLength = (paramLength * 2) + 1; + + if (length < pointLength) + { + return ECCParams_STATUS_ERROR; + } + + /* Reverse and concatenate x and y */ + uint32_t i = 0; + for (i = 0; i < paramLength; i++) + { + buffer[i + 1] = curveParams->generatorX[paramLength + ECC_LENGTH_PREFIX_BYTES - i - 1]; + buffer[i + 1 + paramLength] = curveParams->generatorY[paramLength + ECC_LENGTH_PREFIX_BYTES - i - 1]; + } + + buffer[0] = 0x04; + /* Fill the remaining buffer with 0 if needed */ + memset(buffer + pointLength, 0, length - pointLength); + + return ECCParams_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c new file mode 100644 index 00000000..67f88a61 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X2.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsCC26X2.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on CC26X2 devices. + */ + +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/pka.h) + +const ECCParams_CurveParams ECCParams_NISTP224 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP224_PARAM_SIZE_BYTES, + .prime = NISTP224_prime.byte, + .order = NISTP224_order.byte, + .a = NISTP224_a.byte, + .b = NISTP224_b.byte, + .generatorX = NISTP224_generator.x.byte, + .generatorY = NISTP224_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_NISTP256 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP256_PARAM_SIZE_BYTES, + .prime = NISTP256_prime.byte, + .order = NISTP256_order.byte, + .a = NISTP256_a.byte, + .b = NISTP256_b.byte, + .generatorX = NISTP256_generator.x.byte, + .generatorY = NISTP256_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_NISTP384 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP384_PARAM_SIZE_BYTES, + .prime = NISTP384_prime.byte, + .order = NISTP384_order.byte, + .a = NISTP384_a.byte, + .b = NISTP384_b.byte, + .generatorX = NISTP384_generator.x.byte, + .generatorY = NISTP384_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_NISTP521 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP521_PARAM_SIZE_BYTES, + .prime = NISTP521_prime.byte, + .order = NISTP521_order.byte, + .a = NISTP521_a.byte, + .b = NISTP521_b.byte, + .generatorX = NISTP521_generator.x.byte, + .generatorY = NISTP521_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_BrainpoolP256R1 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP256R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP256R1_prime.byte, + .order = BrainpoolP256R1_order.byte, + .a = BrainpoolP256R1_a.byte, + .b = BrainpoolP256R1_b.byte, + .generatorX = BrainpoolP256R1_generator.x.byte, + .generatorY = BrainpoolP256R1_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_BrainpoolP384R1 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP384R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP384R1_prime.byte, + .order = BrainpoolP384R1_order.byte, + .a = BrainpoolP384R1_a.byte, + .b = BrainpoolP384R1_b.byte, + .generatorX = BrainpoolP384R1_generator.x.byte, + .generatorY = BrainpoolP384R1_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_BrainpoolP512R1 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP512R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP512R1_prime.byte, + .order = BrainpoolP512R1_order.byte, + .a = BrainpoolP512R1_a.byte, + .b = BrainpoolP512R1_b.byte, + .generatorX = BrainpoolP512R1_generator.x.byte, + .generatorY = BrainpoolP512R1_generator.y.byte, + .cofactor = 1}; + +const ECCParams_CurveParams ECCParams_Curve25519 = {.curveType = ECCParams_CURVE_TYPE_MONTGOMERY, + .length = Curve25519_PARAM_SIZE_BYTES, + .prime = Curve25519_prime.byte, + .order = Curve25519_order.byte, + .a = Curve25519_a.byte, + .b = Curve25519_b.byte, + .generatorX = Curve25519_generator.x.byte, + .generatorY = Curve25519_generator.y.byte, + .cofactor = 1}; + +/* + * Ed25519 constants in little endian format. byte[0] is the least + * significant byte and byte[Ed25519_PARAM_SIZE_BYTES - 1] is the most + * significant. + */ +const PKA_EccPoint256 Ed25519_generator = { + .x = {.byte = {0x1a, 0xd5, 0x25, 0x8f, 0x60, 0x2d, 0x56, 0xc9, 0xb2, 0xa7, 0x25, 0x95, 0x60, 0xc7, 0x2c, 0x69, + 0x5c, 0xdc, 0xd6, 0xfd, 0x31, 0xe2, 0xa4, 0xc0, 0xfe, 0x53, 0x6e, 0xcd, 0xd3, 0x36, 0x69, 0x21}}, + .y = {.byte = {0x58, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66}}, +}; + +const PKA_EccParam256 Ed25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Ed25519_order = {.byte = {0xed, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, + 0xa2, 0xde, 0xf9, 0xde, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10}}; + +const PKA_EccParam256 Ed25519_a = {.byte = {0xec, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Ed25519_d = {.byte = {0xa3, 0x78, 0x59, 0x13, 0xca, 0x4d, 0xeb, 0x75, 0xab, 0xd8, 0x41, + 0x41, 0x4d, 0x0a, 0x70, 0x00, 0x98, 0xe8, 0x79, 0x77, 0x79, 0x40, + 0xc7, 0x8c, 0x73, 0xfe, 0x6f, 0x2b, 0xee, 0x6c, 0x03, 0x52}}; + +const ECCParams_CurveParams ECCParams_Ed25519 = {.curveType = ECCParams_CURVE_TYPE_EDWARDS, + .length = 32, + .prime = Ed25519_prime.byte, + .order = Ed25519_order.byte, + .a = Ed25519_a.byte, + .b = Ed25519_d.byte, + .generatorX = Ed25519_generator.x.byte, + .generatorY = Ed25519_generator.y.byte, + .cofactor = 8}; + +/* + * Wei25519 constants in little endian format. byte[0] is the least + * significant byte and byte[Wei25519_PARAM_SIZE_BYTES - 1] is the most + * significant. + */ +const PKA_EccPoint256 Wei25519_generator = { + .x = {.byte = {0x5a, 0x24, 0xad, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x2a}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +const PKA_EccParam256 Wei25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +const PKA_EccParam256 Wei25519_order = {.byte = {0xed, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, + 0xa2, 0xde, 0xf9, 0xde, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10}}; + +const PKA_EccParam256 Wei25519_a = {.byte = {0x44, 0xa1, 0x14, 0x49, 0x98, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x2a}}; + +const PKA_EccParam256 Wei25519_b = {.byte = {0x64, 0xc8, 0x10, 0x77, 0x9c, 0x5e, 0x0b, 0x26, 0xb4, 0x97, 0xd0, + 0x5e, 0x42, 0x7b, 0x09, 0xed, 0x25, 0xb4, 0x97, 0xd0, 0x5e, 0x42, + 0x7b, 0x09, 0xed, 0x25, 0xb4, 0x97, 0xd0, 0x5e, 0x42, 0x7b}}; + +const ECCParams_CurveParams ECCParams_Wei25519 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_GEN, + .length = 32, + .prime = Wei25519_prime.byte, + .order = Wei25519_order.byte, + .a = Wei25519_a.byte, + .b = Wei25519_b.byte, + .generatorX = Wei25519_generator.x.byte, + .generatorY = Wei25519_generator.y.byte, + .cofactor = 8}; + +/* + * ======== ECCParams_formatCurve25519PrivateKey ======== + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey) +{ + myPrivateKey->u.plaintext.keyMaterial[31] &= 0xF8; + myPrivateKey->u.plaintext.keyMaterial[0] &= 0x7F; + myPrivateKey->u.plaintext.keyMaterial[0] |= 0x40; + + return ECCParams_STATUS_SUCCESS; +} + +/* + * ======== ECCParams_getUncompressedGeneratorPoint ======== + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length) +{ + + size_t paramLength = curveParams->length; + size_t pointLength = (paramLength * 2) + 1; + + if (length < pointLength) + { + return ECCParams_STATUS_ERROR; + } + + /* Reverse and concatenate x and y */ + uint32_t i = 0; + for (i = 0; i < paramLength; i++) + { + buffer[i + 1] = curveParams->generatorX[paramLength - i - 1]; + buffer[i + 1 + paramLength] = curveParams->generatorY[paramLength - i - 1]; + } + + buffer[0] = 0x04; + /* Fill the remaining buffer with 0 if needed */ + memset(buffer + pointLength, 0, length - pointLength); + + return ECCParams_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_ns.c new file mode 100644 index 00000000..f53d3b9f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_ns.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsCC26X4_ns.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on CC26X4 devices when utilizing the TF-M. + */ + +#include +#include + +#include +#include +#include + +#include + +const ECCParams_CurveParams ECCParams_NISTP224 = {.secureCurve = ECCParams_SecureCurve_NISTP224}; + +const ECCParams_CurveParams ECCParams_NISTP256 = {.secureCurve = ECCParams_SecureCurve_NISTP256}; + +const ECCParams_CurveParams ECCParams_NISTP384 = {.secureCurve = ECCParams_SecureCurve_NISTP384}; + +const ECCParams_CurveParams ECCParams_NISTP521 = {.secureCurve = ECCParams_SecureCurve_NISTP521}; + +const ECCParams_CurveParams ECCParams_BrainpoolP256R1 = {.secureCurve = ECCParams_SecureCurve_BrainpoolP256R1}; + +const ECCParams_CurveParams ECCParams_BrainpoolP384R1 = {.secureCurve = ECCParams_SecureCurve_BrainpoolP384R1}; + +const ECCParams_CurveParams ECCParams_BrainpoolP512R1 = {.secureCurve = ECCParams_SecureCurve_BrainpoolP512R1}; + +const ECCParams_CurveParams ECCParams_Curve25519 = {.secureCurve = ECCParams_SecureCurve_Curve25519}; + +const ECCParams_CurveParams ECCParams_Ed25519 = {.secureCurve = ECCParams_SecureCurve_Ed25519}; + +const ECCParams_CurveParams ECCParams_Wei25519 = {.secureCurve = ECCParams_SecureCurve_Wei25519}; + +/* + * ======== ECCParams_formatCurve25519PrivateKey ======== + */ +int_fast16_t ECCParams_formatCurve25519PrivateKey(CryptoKey *myPrivateKey) +{ + myPrivateKey->u.plaintext.keyMaterial[31] &= 0xF8; + myPrivateKey->u.plaintext.keyMaterial[0] &= 0x7F; + myPrivateKey->u.plaintext.keyMaterial[0] |= 0x40; + + return ECCParams_STATUS_SUCCESS; +} + +/* + * ======== ECCParams_getUncompressedGeneratorPoint ======== + */ +int_fast16_t ECCParams_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length) +{ + int_fast16_t status; + uintptr_t key; + + /* + * Critical section to prevent non-secure task switching while calling + * secure veneer function. + */ + key = HwiP_disable(); + status = ECCParams_s_getUncompressedGeneratorPoint(curveParams, buffer, length); + HwiP_restore(key); + + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.c new file mode 100644 index 00000000..45cbfe42 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== ECCParamsCC26X4_s.c ======== + * + * This file contains structure definitions for various ECC curves for use + * on CC26X4 devices. + */ + +#include +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/pka.h) + +#include +#include +#include /* __tz_c_veneer */ + +#include /* TI CMSE helper functions */ + +static const ECCParams_CurveParams ECCParams_s_NISTP224 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP224_PARAM_SIZE_BYTES, + .prime = NISTP224_prime.byte, + .order = NISTP224_order.byte, + .a = NISTP224_a.byte, + .b = NISTP224_b.byte, + .generatorX = NISTP224_generator.x.byte, + .generatorY = NISTP224_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_NISTP256 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP256_PARAM_SIZE_BYTES, + .prime = NISTP256_prime.byte, + .order = NISTP256_order.byte, + .a = NISTP256_a.byte, + .b = NISTP256_b.byte, + .generatorX = NISTP256_generator.x.byte, + .generatorY = NISTP256_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_NISTP384 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP384_PARAM_SIZE_BYTES, + .prime = NISTP384_prime.byte, + .order = NISTP384_order.byte, + .a = NISTP384_a.byte, + .b = NISTP384_b.byte, + .generatorX = NISTP384_generator.x.byte, + .generatorY = NISTP384_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_NISTP521 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = NISTP521_PARAM_SIZE_BYTES, + .prime = NISTP521_prime.byte, + .order = NISTP521_order.byte, + .a = NISTP521_a.byte, + .b = NISTP521_b.byte, + .generatorX = NISTP521_generator.x.byte, + .generatorY = NISTP521_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_BrainpoolP256R1 = + {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP256R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP256R1_prime.byte, + .order = BrainpoolP256R1_order.byte, + .a = BrainpoolP256R1_a.byte, + .b = BrainpoolP256R1_b.byte, + .generatorX = BrainpoolP256R1_generator.x.byte, + .generatorY = BrainpoolP256R1_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_BrainpoolP384R1 = + {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP384R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP384R1_prime.byte, + .order = BrainpoolP384R1_order.byte, + .a = BrainpoolP384R1_a.byte, + .b = BrainpoolP384R1_b.byte, + .generatorX = BrainpoolP384R1_generator.x.byte, + .generatorY = BrainpoolP384R1_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_BrainpoolP512R1 = + {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3, + .length = BrainpoolP512R1_PARAM_SIZE_BYTES, + .prime = BrainpoolP512R1_prime.byte, + .order = BrainpoolP512R1_order.byte, + .a = BrainpoolP512R1_a.byte, + .b = BrainpoolP512R1_b.byte, + .generatorX = BrainpoolP512R1_generator.x.byte, + .generatorY = BrainpoolP512R1_generator.y.byte, + .cofactor = 1}; + +static const ECCParams_CurveParams ECCParams_s_Curve25519 = {.curveType = ECCParams_CURVE_TYPE_MONTGOMERY, + .length = 32, + .prime = Curve25519_prime.byte, + .order = Curve25519_order.byte, + .a = Curve25519_a.byte, + .b = Curve25519_b.byte, + .generatorX = Curve25519_generator.x.byte, + .generatorY = Curve25519_generator.y.byte, + .cofactor = 1}; + +/* + * Ed25519 constants in little endian format. byte[0] is the least + * significant byte and byte[Ed25519_PARAM_SIZE_BYTES - 1] is the most + * significant. + */ +static const PKA_EccPoint256 Ed25519_generator = { + .x = {.byte = {0x1a, 0xd5, 0x25, 0x8f, 0x60, 0x2d, 0x56, 0xc9, 0xb2, 0xa7, 0x25, 0x95, 0x60, 0xc7, 0x2c, 0x69, + 0x5c, 0xdc, 0xd6, 0xfd, 0x31, 0xe2, 0xa4, 0xc0, 0xfe, 0x53, 0x6e, 0xcd, 0xd3, 0x36, 0x69, 0x21}}, + .y = {.byte = {0x58, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66}}, +}; + +static const PKA_EccParam256 Ed25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +static const PKA_EccParam256 Ed25519_order = {.byte = {0xed, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, + 0xa2, 0xde, 0xf9, 0xde, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10}}; + +static const PKA_EccParam256 Ed25519_a = {.byte = {0xec, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +static const PKA_EccParam256 Ed25519_d = {.byte = {0xa3, 0x78, 0x59, 0x13, 0xca, 0x4d, 0xeb, 0x75, 0xab, 0xd8, 0x41, + 0x41, 0x4d, 0x0a, 0x70, 0x00, 0x98, 0xe8, 0x79, 0x77, 0x79, 0x40, + 0xc7, 0x8c, 0x73, 0xfe, 0x6f, 0x2b, 0xee, 0x6c, 0x03, 0x52}}; + +const ECCParams_CurveParams ECCParams_s_Ed25519 = {.curveType = ECCParams_CURVE_TYPE_EDWARDS, + .length = 32, + .prime = Ed25519_prime.byte, + .order = Ed25519_order.byte, + .a = Ed25519_a.byte, + .b = Ed25519_d.byte, + .generatorX = Ed25519_generator.x.byte, + .generatorY = Ed25519_generator.y.byte, + .cofactor = 8}; + +/* + * Wei25519 constants in little endian format. byte[0] is the least + * significant byte and byte[Wei25519_PARAM_SIZE_BYTES - 1] is the most + * significant. + */ +static const PKA_EccPoint256 Wei25519_generator = { + .x = {.byte = {0x5a, 0x24, 0xad, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x2a}}, + .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, + 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, +}; + +static const PKA_EccParam256 Wei25519_prime = { + .byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; + +static const PKA_EccParam256 Wei25519_order = { + .byte = {0xed, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10}}; + +static const PKA_EccParam256 Wei25519_a = {.byte = {0x44, 0xa1, 0x14, 0x49, 0x98, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x2a}}; + +static const PKA_EccParam256 Wei25519_b = {.byte = {0x64, 0xc8, 0x10, 0x77, 0x9c, 0x5e, 0x0b, 0x26, 0xb4, 0x97, 0xd0, + 0x5e, 0x42, 0x7b, 0x09, 0xed, 0x25, 0xb4, 0x97, 0xd0, 0x5e, 0x42, + 0x7b, 0x09, 0xed, 0x25, 0xb4, 0x97, 0xd0, 0x5e, 0x42, 0x7b}}; + +const ECCParams_CurveParams ECCParams_s_Wei25519 = {.curveType = ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_GEN, + .length = 32, + .prime = Wei25519_prime.byte, + .order = Wei25519_order.byte, + .a = Wei25519_a.byte, + .b = Wei25519_b.byte, + .generatorX = Wei25519_generator.x.byte, + .generatorY = Wei25519_generator.y.byte, + .cofactor = 8}; + +/* Curve param pointer table indexed by the ECCParams_SecureCurve enum value */ +static const ECCParams_CurveParams *const ECCParams_s_curveParamTable[ECCParams_SecureCurve_COUNT] = + {&ECCParams_s_NISTP224, + &ECCParams_s_NISTP256, + &ECCParams_s_NISTP384, + &ECCParams_s_NISTP521, + &ECCParams_s_BrainpoolP256R1, + &ECCParams_s_BrainpoolP384R1, + &ECCParams_s_BrainpoolP512R1, + &ECCParams_s_Curve25519, + &ECCParams_s_Ed25519, + &ECCParams_s_Wei25519}; + +/* + * ======== ECCParams_s_getCurveParams ======== + */ +const ECCParams_CurveParams *ECCParams_s_getCurveParams(const ECCParams_CurveParams *curveParams) +{ + ECCParams_ns_CurveParams params_ns; + const ECCParams_CurveParams *params_s = NULL; + + /* + * Validate curve param address range. Note that 'sizeof(params_ns)' is used + * for the length because ECCParams_CurveParams struct has different sizes + * within the secure and non-secure code. + */ + if (cmse_has_unpriv_nonsecure_read_access((void *)curveParams, sizeof(params_ns)) != NULL) + { + /* Make a secure copy of the param struct to avoid typecast */ + (void)spm_memcpy(¶ms_ns, (void *)curveParams, sizeof(params_ns)); + + if (params_ns.secureCurve < ECCParams_SecureCurve_COUNT) + { + params_s = ECCParams_s_curveParamTable[params_ns.secureCurve]; + } + } + + return params_s; +} + +/* + * ======== ECCParams_getUncompressedGeneratorPoint ======== + */ +__tz_c_veneer int_fast16_t ECCParams_s_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length) +{ + const ECCParams_CurveParams *params_s; + size_t paramLength; + size_t pointLength; + uint_fast8_t i; + + params_s = ECCParams_s_getCurveParams(curveParams); + if (params_s == NULL) + { + return (int_fast16_t)PSA_ERROR_PROGRAMMER_ERROR; + } + + paramLength = params_s->length; + pointLength = (paramLength * 2) + 1; /* Point format: 0x04 || X || Y */ + + /* Validate length */ + if (length < pointLength) + { + return ECCParams_STATUS_ERROR; + } + + /* Validate output buffer address range */ + if (cmse_has_unpriv_nonsecure_rw_access((void *)buffer, length) == NULL) + { + return (int_fast16_t)PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Reverse and concatenate x and y */ + for (i = 0; i < paramLength; i++) + { + buffer[i + 1] = params_s->generatorX[paramLength - i - 1]; + buffer[i + 1 + paramLength] = params_s->generatorY[paramLength - i - 1]; + } + + buffer[0] = 0x04; + /* Fill the remaining buffer with 0 if needed */ + memset(buffer + pointLength, 0, length - pointLength); + + return ECCParams_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.h new file mode 100644 index 00000000..1586b410 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/ecc/ECCParamsCC26X4_s.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_cryptoutils_ecc_ECCParamsCC26X4_s__include +#define ti_drivers_cryptoutils_ecc_ECCParamsCC26X4_s__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Returns a pointer to curve params stored in secure memory + * + * @param curveParams Points to curve param struct provided by non-secure + * code which references a curve by its name. + * @return Pointer to the curve params stored in secure memory. + */ +const ECCParams_CurveParams *ECCParams_s_getCurveParams(const ECCParams_CurveParams *curveParams); + +/*! + * @brief Veneer to extract the curve generator point from an ecliptic curve + * description. + * + * @note See ECCParams_s_getUncompressedGeneratorPoint() in ECCParam.h for full + * description, parameters, and return values. PSA_ERROR_PROGRAMMER_ERROR + * is an additional return value. + * + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +int_fast16_t ECCParams_s_getUncompressedGeneratorPoint(const ECCParams_CurveParams *curveParams, + uint8_t *buffer, + size_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_ecc_ECCParamsCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c new file mode 100644 index 00000000..275e857a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* Crypto driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; +SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; + +volatile bool CryptoResourceCC26XX_pollingFlag = 0; + +HwiP_Struct CryptoResourceCC26XX_hwi; + +static bool isInitialized = false; + +static void errorSpin(uintptr_t arg) +{ + while (1) {} +} + +void CryptoResourceCC26XX_constructRTOSObjects(void) +{ + HwiP_Params hwiParams; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + /* Construct the common Hwi with a dummy ISR function. This should not matter as the function is set + * whenever we start an operation after pending on CryptoResourceCC26XX_accessSemaphore + */ + HwiP_Params_init(&hwiParams); + hwiParams.priority = ~0; + hwiParams.enableInt = false; + HwiP_construct(&(CryptoResourceCC26XX_hwi), INT_CRYPTO_RESULT_AVAIL_IRQ, errorSpin, &hwiParams); + + SemaphoreP_constructBinary(&CryptoResourceCC26XX_accessSemaphore, 1); + SemaphoreP_constructBinary(&CryptoResourceCC26XX_operationSemaphore, 0); + + isInitialized = true; + } + + HwiP_restore(key); +} + +bool CryptoResourceCC26XX_acquireLock(uint32_t timeout) +{ + SemaphoreP_Status resourceAcquired; + + /* Try and obtain access to the crypto module */ + resourceAcquired = SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, timeout); + + return resourceAcquired == SemaphoreP_OK; +} + +void CryptoResourceCC26XX_releaseLock(void) +{ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h new file mode 100644 index 00000000..5a5eed15 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoResourceCC26XX.h + * + * @brief Shared resources to arbitrate access to the keyStore, AES, and SHA2 engine + * + */ + +#ifndef ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include +#define ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Crypto driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +extern SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; + +extern volatile bool CryptoResourceCC26XX_pollingFlag; + +extern HwiP_Struct CryptoResourceCC26XX_hwi; + +void CryptoResourceCC26XX_constructRTOSObjects(void); +void CryptoResourceCC26XX_destructRTOSObjects(void); +bool CryptoResourceCC26XX_acquireLock(uint32_t timeout); +void CryptoResourceCC26XX_releaseLock(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_sharedresources_CryptoResourceCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c new file mode 100644 index 00000000..9701e6db --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2017-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) + +/* PKA driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ +SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; +SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; + +volatile bool PKAResourceCC26XX_pollingFlag = 0; + +HwiP_Struct PKAResourceCC26XX_hwi; + +static bool isInitialized = false; + +static void errorSpin(uintptr_t arg) +{ + while (1) {} +} + +void PKAResourceCC26XX_constructRTOSObjects(void) +{ + HwiP_Params hwiParams; + uint_fast8_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + /* Construct the common Hwi with a dummy ISR function. This should not matter as the function is set + * whenever we start an operation after pending on PKAResourceCC26XX_accessSemaphore + */ + HwiP_Params_init(&hwiParams); + hwiParams.priority = ~0; + hwiParams.enableInt = false; + HwiP_construct(&(PKAResourceCC26XX_hwi), INT_PKA_IRQ, errorSpin, &hwiParams); + + SemaphoreP_constructBinary(&PKAResourceCC26XX_accessSemaphore, 1); + SemaphoreP_constructBinary(&PKAResourceCC26XX_operationSemaphore, 0); + + isInitialized = true; + } + + HwiP_restore(key); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h new file mode 100644 index 00000000..fa4af95a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PKAResourceCC26XX.h + * + * @brief Shared resources to arbitrate access to the PKA engine + * + */ + +#ifndef ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include +#define ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* PKA driver semaphore used to synchronize accesses to the PKA engine */ +extern SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; + +extern volatile bool PKAResourceCC26XX_pollingFlag; + +extern HwiP_Struct PKAResourceCC26XX_hwi; + +void PKAResourceCC26XX_constructRTOSObjects(void); +void PKAResourceCC26XX_destructRTOSObjects(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_sharedresources_PKAResourceCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.c b/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.c new file mode 100644 index 00000000..83f7ffc4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.c @@ -0,0 +1,572 @@ +/* + * Copyright (c) 2019-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include + +#if defined(__GNUC__) || defined(__clang__) + #define CRYPTOUTILS_NOINLINE __attribute__((noinline)) +#else + #define CRYPTOUTILS_NOINLINE +#endif + +#define CryptoUtils_LIMIT_MASK (0xFFFFFFFEu) + +/* + * These constants take values at the very top of the memory map where it is unreasonable + * for an application to have stored a different number value. + */ +#define CryptoUtils_LIMIT_ZERO 0xFFFFFFFEu +#define CryptoUtils_LIMIT_ONE 0xFFFFFFFFu + +const uint8_t *CryptoUtils_limitZero = (uint8_t *)CryptoUtils_LIMIT_ZERO; +const uint8_t *CryptoUtils_limitOne = (uint8_t *)CryptoUtils_LIMIT_ONE; + +/* + * ======== CryptoUtils_buffersMatch ======== + */ +#if defined(__IAR_SYSTEMS_ICC__) + #pragma inline = never +#elif defined(__TI_COMPILER_VERSION__) && !defined(__cplusplus) + #pragma FUNC_CANNOT_INLINE(CryptoUtils_buffersMatch) +#elif defined(__TI_COMPILER_VERSION__) + #pragma FUNC_CANNOT_INLINE +#endif +CRYPTOUTILS_NOINLINE bool CryptoUtils_buffersMatch(const volatile void *volatile buffer0, + const volatile void *volatile buffer1, + size_t bufferByteLength) +{ + volatile uint8_t tempResult = 0; + uint8_t byte0; + uint8_t byte1; + size_t i; + + /* XOR each byte of the buffer together and OR the results. + * If the OR'd result is non-zero, the buffers do not match. + * There is no branch based on the content of the buffers here to avoid + * timing attacks. + */ + for (i = 0; i < bufferByteLength; i++) + { + byte0 = ((uint8_t *)buffer0)[i]; + byte1 = ((uint8_t *)buffer1)[i]; + + tempResult |= byte0 ^ byte1; + } + + return tempResult == 0; +} + +/* + * ======== CryptoUtils_buffersMatchWordAligned ======== + */ +#if defined(__IAR_SYSTEMS_ICC__) + #pragma inline = never +#elif defined(__TI_COMPILER_VERSION__) && !defined(__cplusplus) + #pragma FUNC_CANNOT_INLINE(CryptoUtils_buffersMatchWordAligned) +#elif defined(__TI_COMPILER_VERSION__) + #pragma FUNC_CANNOT_INLINE +#endif +CRYPTOUTILS_NOINLINE bool CryptoUtils_buffersMatchWordAligned(const volatile uint32_t *volatile buffer0, + const volatile uint32_t *volatile buffer1, + size_t bufferByteLength) +{ + volatile uint32_t tempResult = 0; + uint32_t word0; + uint32_t word1; + size_t i; + + /* We could skip the branch and just set tempResult equal to the + * statement below for the same effect but this is more explicit. + */ + if (bufferByteLength % sizeof(uint32_t) != 0) + { + return false; + } + + /* XOR each 32-bit word of the buffer together and OR the results. + * If the OR'd result is non-zero, the buffers do not match. + * There is no branch based on the content of the buffers here to avoid + * timing attacks. + */ + for (i = 0; i < bufferByteLength / sizeof(uint32_t); i++) + { + word0 = buffer0[i]; + word1 = buffer1[i]; + + tempResult |= word0 ^ word1; + } + + return tempResult == 0; +} + +/* + * ======== CryptoUtils_reverseBufferBytewise ======== + */ +void CryptoUtils_reverseBufferBytewise(void *buffer, size_t bufferByteLength) +{ + uint8_t *bufferLow = buffer; + uint8_t *bufferHigh = bufferLow + bufferByteLength - 1; + uint8_t tmp; + + while (bufferLow < bufferHigh) + { + tmp = *bufferLow; + *bufferLow = *bufferHigh; + *bufferHigh = tmp; + bufferLow++; + bufferHigh--; + } +} + +/* + * ======== CryptoUtils_isBufferAllZeros ======== + */ +bool CryptoUtils_isBufferAllZeros(const void *buffer, size_t bufferByteLength) +{ + uint32_t i; + uint8_t bufferBits = 0; + + for (i = 0; i < bufferByteLength; i++) + { + bufferBits |= ((uint8_t *)buffer)[i]; + } + + return bufferBits == 0; +} + +/* + * ======== CryptoUtils_memset ======== + */ +void CryptoUtils_memset(void *dest, size_t destSize, uint8_t val, size_t count) +{ + DebugP_assert(dest); + DebugP_assert(count <= destSize); + + volatile uint8_t *volatile p = (volatile uint8_t *)dest; + + while (destSize-- && count--) + { + *p++ = val; + } +} + +/* + * ======== CryptoUtils_copyPad ======== + */ +void CryptoUtils_copyPad(const void *source, uint32_t *destination, size_t sourceLength) +{ + uint32_t i; + uint8_t remainder; + uint32_t temp; + uint8_t *tempBytePointer; + const uint8_t *sourceBytePointer; + + remainder = sourceLength % sizeof(uint32_t); + temp = 0; + tempBytePointer = (uint8_t *)&temp; + sourceBytePointer = (uint8_t *)source; + + /* Copy source to destination starting at the end of source and the + * beginning of destination. + * We assemble each word in normal order and write one word at a + * time since the PKA_RAM requires word-aligned reads and writes. + */ + + for (i = 0; i < sourceLength / sizeof(uint32_t); i++) + { + uint32_t sourceOffset = sizeof(uint32_t) * i; + + tempBytePointer[0] = sourceBytePointer[sourceOffset + 0]; + tempBytePointer[1] = sourceBytePointer[sourceOffset + 1]; + tempBytePointer[2] = sourceBytePointer[sourceOffset + 2]; + tempBytePointer[3] = sourceBytePointer[sourceOffset + 3]; + + *(destination + i) = temp; + } + + /* Reset to 0 so we do not have to zero-out individual bytes */ + temp = 0; + + /* If sourceLength is not a word-multiple, we need to copy over the + * remaining bytes and zero pad the word we are writing to PKA_RAM. + */ + if (remainder == 1) + { + + tempBytePointer[0] = sourceBytePointer[0]; + + /* i is reused from the loop above. This write zero-pads the + * destination buffer to word-length. + */ + *(destination + i) = temp; + } + else if (remainder == 2) + { + + tempBytePointer[0] = sourceBytePointer[0]; + tempBytePointer[1] = sourceBytePointer[1]; + + *(destination + i) = temp; + } + else if (remainder == 3) + { + + tempBytePointer[0] = sourceBytePointer[0]; + tempBytePointer[1] = sourceBytePointer[1]; + tempBytePointer[2] = sourceBytePointer[2]; + + *(destination + i) = temp; + } +} + +/* + * ======== CryptoUtils_reverseCopyPad ======== + */ +void CryptoUtils_reverseCopyPad(const void *source, uint32_t *destination, size_t sourceLength) +{ + uint32_t i; + uint8_t remainder; + uint32_t temp; + uint8_t *tempBytePointer; + const uint8_t *sourceBytePointer; + + remainder = sourceLength % sizeof(uint32_t); + temp = 0; + tempBytePointer = (uint8_t *)&temp; + sourceBytePointer = (uint8_t *)source; + + /* Copy source to destination starting at the end of source and the + * beginning of destination. + * We assemble each word in byte-reversed order and write one word at a + * time since the PKA_RAM requires word-aligned reads and writes. + */ + + for (i = 0; i < sourceLength / sizeof(uint32_t); i++) + { + uint32_t sourceOffset = sourceLength - 1 - sizeof(uint32_t) * i; + + tempBytePointer[3] = sourceBytePointer[sourceOffset - 3]; + tempBytePointer[2] = sourceBytePointer[sourceOffset - 2]; + tempBytePointer[1] = sourceBytePointer[sourceOffset - 1]; + tempBytePointer[0] = sourceBytePointer[sourceOffset - 0]; + + *(destination + i) = temp; + } + + /* Reset to 0 so we do not have to zero-out individual bytes */ + temp = 0; + + /* If sourceLength is not a word-multiple, we need to copy over the + * remaining bytes and zero pad the word we are writing to PKA_RAM. + */ + if (remainder == 1) + { + + tempBytePointer[0] = sourceBytePointer[0]; + + /* i is reused from the loop above. This write zero-pads the + * destination buffer to word-length. + */ + *(destination + i) = temp; + } + else if (remainder == 2) + { + + tempBytePointer[0] = sourceBytePointer[1]; + tempBytePointer[1] = sourceBytePointer[0]; + + *(destination + i) = temp; + } + else if (remainder == 3) + { + + tempBytePointer[0] = sourceBytePointer[2]; + tempBytePointer[1] = sourceBytePointer[1]; + tempBytePointer[2] = sourceBytePointer[0]; + + *(destination + i) = temp; + } +} + +/* + * ======== CryptoUtils_reverseCopy ======== + */ +void CryptoUtils_reverseCopy(const void *source, void *destination, size_t sourceLength) +{ + /* + * If destination address is word-aligned and source length is a word-multiple, + * use CryptoUtils_reverseCopyPad() for better efficiency. + */ + if ((((uint32_t)destination | sourceLength) & 0x3) == 0) + { + CryptoUtils_reverseCopyPad(source, (uint32_t *)destination, sourceLength); + } + else + { + const uint8_t *sourceBytePtr = (const uint8_t *)source; + uint8_t *dstBytePtr = (uint8_t *)destination + sourceLength - 1; + + /* + * Copy source to destination starting at the end of source and the + * beginning of destination. + */ + while (sourceLength--) + { + *dstBytePtr-- = *sourceBytePtr++; + } + } +} + +/* limitValue must be either CryptoUtils_LIMIT_ZERO or CryptoUtils_LIMIT_ONE */ +static int16_t CryptoUtils_convertLimitValueToInt(const void *limitValue) +{ + int16_t value = 0; + + if (limitValue == CryptoUtils_limitOne) + { + value = 1; + } + + return value; +} + +/* + * Returns number1[offset] - number2[offset]. + * + * Can handle one of number1 or number2 (but not both) being one of the special limit values of + * CryptoUtils_LIMIT_ZERO or CryptoUtils_LIMIT_ONE. + * + * All pointer parameters must be non-NULL. + */ +static int16_t CryptoUtils_diffAtOffset(const uint8_t number1[], + const uint8_t number2[], + size_t offset, + size_t lsbOffset) +{ + + int16_t diff; + + /* Look at number2 first, as it will be more common for number2 to be one of the limit values. */ + if (number2 == CryptoUtils_limitZero) + { + diff = (int16_t)number1[offset]; + } + else if (number2 == CryptoUtils_limitOne) + { + if (offset == lsbOffset) + { + diff = (int16_t)number1[offset] - 1; + } + else + { + diff = (int16_t)number1[offset]; + } + } + else if (number1 == CryptoUtils_limitZero) + { + diff = 0 - (int16_t)number1[offset]; + } + else if (number1 == CryptoUtils_limitOne) + { + if (offset == lsbOffset) + { + diff = 1 - (int16_t)number1[offset]; + } + else + { + diff = 0 - (int16_t)number1[offset]; + } + } + else + { + diff = (int16_t)number1[offset] - (int16_t)number2[offset]; + } + + return diff; +} + +/* Uses a timing constant algorithm to return 0 if value is 0 and return 1 otherwise. */ +static uint16_t CryptoUtils_valueNonZeroTimingConstantCheck(int16_t value) +{ + uint16_t valueNonZero; + + /* Mask and shift bits such that if any bit in value is '1' then the + lsb of valueNonZero is 1 and otherwise valueNonZero is 0. */ + valueNonZero = (((uint16_t)value & 0xFF00u) >> 8u) | ((uint8_t)value & 0xFFu); + valueNonZero = ((valueNonZero & 0xF0u) >> 4u) | (valueNonZero & 0x0Fu); + valueNonZero = ((valueNonZero & 0x0Cu) >> 2u) | (valueNonZero & 0x03u); + valueNonZero = ((valueNonZero & 0x02u) >> 1u) | (valueNonZero & 0x01u); + + return valueNonZero; +} + +/* + * Returns sign of number1 - number2: + * negative value if number2 is larger, positive value if number1 is larger and zero if numbers are equal. + * + * Note that the magnitude of the return value has no meaning. + * + * The comparison is performed with a time-constant algorithm with respect to either of the number + * arguments (number1, number2) when those inputs are not CryptoUtils_limitZero or CryptoUtils_limitOne. + * + * All pointer parameters must be non-NULL. + */ +static int16_t CryptoUtils_compareNumbers(const uint8_t number1[], + const uint8_t number2[], + size_t byteLength, + CryptoUtils_Endianess endianess) +{ + int16_t result = 0x0; + int16_t diff; + uint16_t diffNonZero; + uint16_t diffResultMask; + uint16_t resultUnknown = 0xFFFFu; + uintptr_t number1Address; + uintptr_t number2Address; + size_t i; + + number1Address = (uintptr_t)number1; + number2Address = (uintptr_t)number2; + + /* + * Check if special RNG_limit values are being used for both values. + * This is not expected, but is handled for completeness. + */ + if (((number1Address & CryptoUtils_LIMIT_MASK) == CryptoUtils_LIMIT_MASK) && + ((number2Address & CryptoUtils_LIMIT_MASK) == CryptoUtils_LIMIT_MASK)) + { + + result = CryptoUtils_convertLimitValueToInt(number1) - CryptoUtils_convertLimitValueToInt(number2); + } + else if (number1 != number2) + { + if (endianess == CryptoUtils_ENDIANESS_BIG) + { + i = 0u; + while (i < byteLength) + { + diff = CryptoUtils_diffAtOffset(number1, number2, i, byteLength - 1); + + /* Update result only if result was not known and is thus currently set to 0. */ + result = (int16_t)((uint16_t)result | (resultUnknown & (uint16_t)diff)); + + /* + * Determine if result is now known and update resultUnknown + */ + + diffNonZero = CryptoUtils_valueNonZeroTimingConstantCheck(diff); + + /* Create mask where mask value is 0 if bytes were equal, otherwise mask is all 1s. */ + diffResultMask = diffNonZero - 1u; + + /* Set resultUnknown to 0 (indicating result is known) if bytes were not equal. */ + resultUnknown &= diffResultMask; + + i++; + } + } + else + { + i = byteLength; + while (i > 0u) + { + i--; + + diff = CryptoUtils_diffAtOffset(number1, number2, i, 0); + + /* Update result only if result was not known and is thus currently set to 0. */ + result = (int16_t)((uint16_t)result | (resultUnknown & (uint16_t)diff)); + + /* + * Determine if result is now known and update resultUnknown + */ + diffNonZero = CryptoUtils_valueNonZeroTimingConstantCheck(diff); + + /* Create mask where mask value is 0 if bytes were equal, otherwise mask is all 1s. */ + diffResultMask = diffNonZero - 1u; + + /* Set resultUnknown to 0 (indicating result is known) if bytes were not equal. */ + resultUnknown &= diffResultMask; + } + } + } + else + { + result = 0; + } + + return result; +} + +/* + * ======== CryptoUtils_isNumberInRange ======== + */ +bool CryptoUtils_isNumberInRange(const void *number, + size_t bitLength, + CryptoUtils_Endianess endianess, + const void *lowerLimit, + const void *upperLimit) +{ + int16_t upperResult; + int16_t lowerResult; + bool inUpperLimit = true; + bool inLowerLimit = true; + size_t byteLength; + + byteLength = (bitLength + 7u) >> 3u; + + if (upperLimit != NULL) + { + upperResult = CryptoUtils_compareNumbers(number, upperLimit, byteLength, endianess); + if (upperResult >= 0) + { + inUpperLimit = false; + } + } + + if (lowerLimit != NULL) + { + lowerResult = CryptoUtils_compareNumbers(number, lowerLimit, byteLength, endianess); + if (lowerResult < 0) + { + inLowerLimit = false; + } + } + + return (inUpperLimit && inLowerLimit); +} diff --git a/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.h b/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.h new file mode 100644 index 00000000..0b2350f5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/cryptoutils/utils/CryptoUtils.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file CryptoUtils.h + * + * @brief A collection of utility functions for cryptographic purposes + * + */ + +#ifndef ti_drivers_cryptoutils_utils_CryptoUtils__include +#define ti_drivers_cryptoutils_utils_CryptoUtils__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Indicates the endianess (byte order) of a multi-byte value. + */ +typedef enum +{ + CryptoUtils_ENDIANESS_BIG = 0u, /*!< MSB at lowest address. */ + CryptoUtils_ENDIANESS_LITTLE = 1u, /*!< LSB at highest address. */ +} CryptoUtils_Endianess; + +/*! + * @brief Limit value of 0 + * + * This is a value provided for convenience when checking a value + * against a range. + * + * @sa CryptoUtils_limitOne + * @sa CryptoUtils_isNumberInRange + */ +extern const uint8_t *CryptoUtils_limitZero; + +/*! + * @brief Limit value of 1 + * + * This is a value provided for convenience when checking a value + * against a range. + * + * @sa CryptoUtils_limitZero + * @sa CryptoUtils_isNumberInRange + */ +extern const uint8_t *CryptoUtils_limitOne; + +/** + * @brief Compares two buffers for equality without branching + * + * @note This is not a drop-in replacement for memcmp! + * + * Most memcmp implementations break out of their comparison loop immediately + * once a mismatch is detected to save execution time. For cryptographic + * purposes, this is a flaw. + * + * This function compares two buffers without branching thus requiring a + * an amount of time that does not vary with the content of @c buffer0 and + * @c buffer1. + * + * @param buffer0 Buffer to compare against @c buffer1. + * @param buffer1 Buffer tp compare against @c buffer0 + * @param bufferByteLength Length in bytes of @c buffer0 and @c buffer1. + * @retval true The contents of the buffers match. + * @retval false The contents of the buffers do not match. + */ +bool CryptoUtils_buffersMatch(const volatile void *volatile buffer0, + const volatile void *volatile buffer1, + size_t bufferByteLength); + +/** + * @brief Compares two buffers for equality word-by-word without branching + * + * @note This is not a drop-in replacement for memcmp! + * + * Most memcmp implementations break out of their comparison loop immediately + * once a mismatch is detected to save execution time. For cryptographic + * purposes, this is a flaw. + * + * This function compares two buffers without branching thus requiring a + * an amount of time that does not vary with the content of @c buffer0 and + * @c buffer1. + * + * Unlike #CryptoUtils_buffersMatch(), this function expects @c buffer0 and + * @c buffer1 to be 32-bit aligned. It will only perform 32-bit aligned + * accesses to memory. This is needed to access the registers of certain + * peripherals. + * + * @param buffer0 Buffer to compare against @c buffer1. + * @param buffer1 Buffer tp compare against @c buffer0 + * @param bufferByteLength Length in bytes of @c buffer0 and @c buffer1. + * Must be evenly divisible by sizeof(uint32_t). + * This function will return false if @c + * bufferByteLength is not evenly divisible by + * sizeof(uin32_t). + * @retval true The contents of the buffers match. + * @retval false The contents of the buffers do not match. + */ +bool CryptoUtils_buffersMatchWordAligned(const volatile uint32_t *volatile buffer0, + const volatile uint32_t *volatile buffer1, + size_t bufferByteLength); + +/** + * @brief Check whether the provided buffer only contains 0x00 bytes + * + * @param buffer Buffer to search for non-zero bytes + * @param bufferByteLength Length of @c buffer in bytes + * + * @retval true The buffer contained only bytes with value 0x00 + * @retval false The buffer contained at least one non-zero byte + */ +bool CryptoUtils_isBufferAllZeros(const void *buffer, size_t bufferByteLength); + +/** + * @brief Copies @c val into the first @c count bytes of the buffer + * pointed to by @c dest. + * + * @param dest Pointer to destination buffer + * @param destSize Size of destination buffer in bytes + * @param val Fill byte value + * @param count Number of bytes to fill + * + */ +void CryptoUtils_memset(void *dest, size_t destSize, uint8_t val, size_t count); + +/** + * @brief Reverses the byte order in a buffer of a given length + * + * The left-most byte will become the right-most byte and vice versa. + * + * @param buffer Buffer containing the data to be reversed. + * @param bufferByteLength Length in bytes of @c buffer. + */ +void CryptoUtils_reverseBufferBytewise(void *buffer, size_t bufferByteLength); + +/** + * @brief Copies and pads an array of words. + * + * The \c source array is copied into the \c destination + * array. Writes are done word-wise. If \c sourceLength is not a multiple of 4, + * any remaining bytes up to the next word boundary are padded with 0. + * + * The length of the destination array must be a multiple of 4, rounded up to the + * padded \c sourceLength if required. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_copyPad(const void *source, uint32_t *destination, size_t sourceLength); + +/** + * @brief Reverses, copies, and pads an array of words. + * + * The \c source array is reversed byte-wise and copied into the \c destination + * array. Writes are done word-wise. If \c sourceLength is not a multiple of 4, + * any remaining bytes up to the next word boundary are padded with 0. + * + * The length of the destination array must be a multiple of 4, rounded up to the + * padded \c sourceLength if required. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_reverseCopyPad(const void *source, uint32_t *destination, size_t sourceLength); + +/** + * @brief Reverses and copies an array of bytes. + * + * The \c source array is reversed byte-wise and copied into the \c destination + * array. + * + * @param source Source array + * + * @param destination Destination array + * + * @param sourceLength Length of the source array + */ +void CryptoUtils_reverseCopy(const void *source, void *destination, size_t sourceLength); + +/** + * @brief Checks if number is within the range [lowerLimit, upperLimit) + * + * Checks if the specified number is at greater than or equal to + * the lower limit and less than the upper limit. Note that the boundary + * set by the upper limit is not inclusive. + * + * Note that the special values of #CryptoUtils_limitZero and + * #CryptoUtils_limitOne are available to pass in for the @c lowerLimit. + * (These values can also be used for the @c upperLimit but their use for + * the upperLimit has no practical use.) + * + * If @c lowerLimit is NULL then the lower limit is taken as 0. + * If @c upperLimit is NULL then the upper limit is taken as + * 2(@c bitLength + 1). + * + * The implemented algorithm is timing-constant when the following parameters + * are held constant: @c lowerLimit, @c upperLimit, @c bitLength, + * and @c endianess. Thus, the @c number being checked may change and + * timing will not leak its relation to the limits. However, timing may leak + * the bitLength, the endianess, and the use of #CryptoUtils_limitZero, + * #CryptoUtils_limitOne, and NULL for the limit values. + * + * @param number Pointer to number to check + * @param bitLength Length in bits of @c number, @c lowerLimit, and + * @c upperLimit. + * @param endianess The endianess of @c number, @c lowerLimit, and + * @c upperLimit. + * @param lowerLimit Pointer to lower limit value. + * @param upperLimit Pointer to upper limit value. + * @retval true The randomNumber is within + * [@c lowerLimit, @c upperLimit). + * @retval false The randomNumber is not within + * [@c lowerLimit, @c upperLimit). + */ +bool CryptoUtils_isNumberInRange(const void *number, + size_t bitLength, + CryptoUtils_Endianess endianess, + const void *lowerLimit, + const void *upperLimit); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_cryptoutils_utils_CryptoUtils__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.c b/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.c new file mode 100644 index 00000000..803dd028 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.c @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2021-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* Kernel services */ +#include +#include + +/* TI-RTOS drivers */ +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/aux_dac.h) +#include DeviceFamily_constructPath(driverlib/aux_smph.h) + +#define MICROVOLTS_PER_MILLIVOLT 1000 +#define CALIBRATION_VDDS 3000 + +/* Forward declarations */ +static int_fast16_t DAC_setRange(DAC_Handle handle); + +/* Extern globals */ +extern const DAC_Config DAC_config[]; +extern const uint_least8_t DAC_count; +extern const ADC_Config ADC_config[]; +extern const uint_least8_t ADC_count; +extern const uint_least8_t CONFIG_ADC_AUX_CONST; + +/* Static Globals */ +static bool isInitialized = (bool)false; +static uint16_t dacInstance = 0; +static SemaphoreP_Struct dacSemaphore; + +/* + * ======== DAC_init ======== + */ +void DAC_init(void) +{ + + isInitialized = (bool)true; +} + +/* + * ======== DAC_open ======== + */ +DAC_Handle DAC_open(uint_least8_t index, DAC_Params *params) +{ + + DAC_Handle handle; + DACCC26XX_Object *object; + DACCC26XX_HWAttrs const *hwAttrs; + + /* Get handle and the object */ + handle = (DAC_Handle) & (DAC_config[index]); + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Determine if the driver was already opened */ + uint32_t key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + /* If this is the first handle requested, set up the semaphore as well */ + if (dacInstance == 0) + { + /* Setup semaphore */ + SemaphoreP_constructBinary(&dacSemaphore, 1); + } + dacInstance++; + + /* Initialize DAC Object*/ + object->isOpen = (bool)true; + HwiP_restore(key); + + if (params != NULL) + { + object->currCode = params->initCode; + } + else + { + object->currCode = 0; + } + + GPIO_setConfig(hwAttrs->outputPin, GPIO_CFG_NO_DIR); + + return handle; +} + +/* + * ======== DAC_close ======== + */ +void DAC_close(DAC_Handle handle) +{ + DACCC26XX_Object *object = handle->object; + DACCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + uint32_t key = HwiP_disable(); + + if (object->isOpen) + { + /* Check that the DAC is no longer in use. If it is, disable DAC's output. */ + if (object->isEnabled) + { + DAC_disable(handle); + } + dacInstance--; + if (dacInstance == 0) + { + SemaphoreP_destruct(&dacSemaphore); + } + } + else + { + HwiP_restore(key); + return; + } + + /* Mark the module as available */ + object->isOpen = (bool)false; + HwiP_restore(key); + + /* Deallocate pins */ + GPIO_resetConfig(hwAttrs->outputPin); +} + +/* + * ======== DAC_setVoltage ======== + */ +int_fast16_t DAC_setVoltage(DAC_Handle handle, uint32_t uVoltOutput) +{ + + DACCC26XX_Object *object = handle->object; + int_fast16_t status = DAC_STATUS_ERROR; + uint32_t code; + + /* Get the object */ + object = handle->object; + + /* Verify that the DAC's output is enabled for the handle. This is necessary given that + * the DAC's output range depends on the voltage reference source. + */ + if (object->isEnabled) + { + /* Check that the value is within the DAC's voltage range. */ + if ((uVoltOutput >= object->dacOutputMin) && (uVoltOutput <= object->dacOutputMax)) + { + code = AUXDACCalcCode(uVoltOutput, object->dacOutputMin, object->dacOutputMax); + AUXDACSetCode((uint8_t)code); + object->currCode = code; + status = DAC_STATUS_SUCCESS; + } + else + { + status = DAC_STATUS_INVALID; + } + } + + return status; +} + +/* + * ======== DAC_setCode ======== + */ +int_fast16_t DAC_setCode(DAC_Handle handle, uint32_t code) +{ + + DACCC26XX_Object *object; + int_fast16_t status = DAC_STATUS_ERROR; + + /* Get the object */ + object = handle->object; + + /* Verify that the DAC is currently enabled. */ + if (object->isEnabled) + { + AUXDACSetCode((uint8_t)code); + object->currCode = code; + status = DAC_STATUS_SUCCESS; + } + else + { + /* Even if the DAC is not enabled for this handle, update the DAC code in the object + * so that once the DAC is enabled for the handle, this value will be set and the output + * voltage will depend on the selected voltage reference source. + */ + object->currCode = code; + status = DAC_STATUS_SUCCESS; + } + return status; +} + +/* + * ======== DAC_enable ======== + */ +int_fast16_t DAC_enable(DAC_Handle handle) +{ + + DACCC26XX_Object *object; + DACCC26XX_HWAttrs const *hwAttrs; + int_fast16_t status = DAC_STATUS_ERROR; + + /* Get handle */ + hwAttrs = handle->hwAttrs; + + /* Get the object */ + object = handle->object; + + /* Give control of the peripheral to this DAC handle. Return error if the peripheral has been + * enabled by another handle. + */ + if (SemaphoreP_pend(&dacSemaphore, SemaphoreP_NO_WAIT) != SemaphoreP_OK) + { + object->isEnabled = (bool)false; + status = DAC_STATUS_INUSE; + return status; + } + + /* Acquire the DAC HW semaphore. Return an error if the HW semaphore is not available. */ + if (!AUXSMPHTryAcquire(AUX_SMPH_4)) + { + object->isEnabled = (bool)false; + SemaphoreP_post(&dacSemaphore); + status = DAC_STATUS_INUSE; + return status; + } + + /* Set voltage reference source */ + AUXDACSetVref((uint8_t)hwAttrs->dacVrefSource); + + /* Check the precharge status if DCOUPL has been selected as the voltage reference source. */ + if ((hwAttrs->dacVrefSource == AUXDAC_VREF_SEL_DCOUPL) && (hwAttrs->dacPrecharge)) + { + AUXDACEnablePreCharge(); + } + else + { + AUXDACDisablePreCharge(); + } + + /* Determine DAC's output range */ + if (DAC_setRange(handle) != DAC_STATUS_SUCCESS) + { + object->isEnabled = (bool)false; + SemaphoreP_post(&dacSemaphore); + return status; + } + + /* AUX Bus frequency (24 MHz) divided by (dacSmplClkDivider + 1) determines + * the sample base clock (SBCLK) frequency. The DAC sample clock is configured + * to be high for 4 SBCLK periods, and low for 4 SBCLK periods. This means + * that the DAC sample clock has a frequency of that equal to (SBCLK freq)/8. + */ + AUXDACSetSampleClock(hwAttrs->dacSmplClkDivider); + + /* Set the DAC's output code. */ + AUXDACSetCode((uint8_t)object->currCode); + + /* Enable the DAC's Sample Clock, the DAC's output buffer and the DAC, and connect output. */ + AUXDACEnable(hwAttrs->dacCompAInput); + + /* Set power constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Keep track of the DAC's current state as enabled. */ + object->isEnabled = (bool)true; + + status = DAC_STATUS_SUCCESS; + + return status; +} + +/* + * ======== DAC_disable ======== + */ +int_fast16_t DAC_disable(DAC_Handle handle) +{ + + DACCC26XX_Object *object; + int_fast16_t status = DAC_STATUS_ERROR; + + /* Get the object */ + object = handle->object; + + if (object->isEnabled) + { + /* Disable the DAC's sample clock, the DAC's output buffer, the DAC, and disconnect output. */ + AUXDACDisable(); + + /* Release the DAC HW semaphore */ + AUXSMPHRelease(AUX_SMPH_4); + + /* Allow entering standby again after DAC has been disabled */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Release the lock for this particular DAC handle */ + SemaphoreP_post(&dacSemaphore); + + /* Keep track of the DAC's current state as disabled. */ + object->isEnabled = (bool)false; + status = DAC_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== DAC_setRange ======== + */ +static int_fast16_t DAC_setRange(DAC_Handle handle) +{ + + DACCC26XX_Object *object; + DACCC26XX_HWAttrs const *hwAttrs; + ADC_Handle auxadcHandle; + ADC_Params auxadcParams; + int_fast16_t status = DAC_STATUS_ERROR; + uint16_t vdds; + uint32_t vddsMicroVolt; + + /* Get handle and the object */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + if (hwAttrs->dacVrefSource == AUXDAC_VREF_SEL_VDDS) + { + /* Create and initialize auxiliary ADC handle. + * To account for VDDS variations, it's necessary to measure VDDS with the ADC peripheral. + * This is done in such a way that access to the single ADC peripheral between the + * auxiliary handle and other existing ADC handles is controlled by the semaphore + * defined in the ADC driver. + */ + ADC_init(); + + /* Open auxiliary ADC handle */ + ADC_Params_init(&auxadcParams); + auxadcHandle = ADC_open(CONFIG_ADC_AUX_CONST, &auxadcParams); + if (auxadcHandle == NULL) + { + return status; + } + + /* Measure VDDS using 12-bit ADC */ + if (ADC_convert(auxadcHandle, &vdds) != ADC_STATUS_SUCCESS) + { + return status; + } + vddsMicroVolt = ADC_convertToMicroVolts(auxadcHandle, vdds); + + /* Close auxiliary ADC handle */ + ADC_close(auxadcHandle); + + /* Obtain DAC's output range for the particular handle and scale it to microvolts. + * Calibration values for VDDS are measured at 3.0 V, so it's necessary to scale to the actual VDDS. + */ + object->dacOutputMin = AUXDACCalcMin() * MICROVOLTS_PER_MILLIVOLT; + object->dacOutputMax = ((AUXDACCalcMax() * (vddsMicroVolt / MICROVOLTS_PER_MILLIVOLT)) / CALIBRATION_VDDS) * + MICROVOLTS_PER_MILLIVOLT; + + status = DAC_STATUS_SUCCESS; + } + else + { + /* Calculate DAC's output range for the particular handle and scale it to microvolts. + * No need to measure VDDS since it was not selected as the voltage reference source. + */ + object->dacOutputMin = AUXDACCalcMin() * MICROVOLTS_PER_MILLIVOLT; + object->dacOutputMax = AUXDACCalcMax() * MICROVOLTS_PER_MILLIVOLT; + + status = DAC_STATUS_SUCCESS; + } + + return status; +} diff --git a/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.h b/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.h new file mode 100644 index 00000000..9a1d1025 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dac/DACCC26X2.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file DACCC26X2.h + * @brief DAC driver implementation for the DAC peripheral on CC26X2 + * + * This DAC driver implementation is designed to operate on a DAC peripheral + * for CC26X2. + * + * Refer to @ref DAC.h for a complete description of APIs & example of use. + * + ****************************************************************************** + */ +#ifndef ti_drivers_dac_DACCC26X2__include +#define ti_drivers_dac_DACCC26X2__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief DAC voltage reference setting + * + * The enum defines the DAC voltage reference that the module uses. + */ +typedef enum +{ + /*! Use the Core Voltage Decoupling pin as the DAC's voltage reference source. */ + DAC_VREF_DCOUPL = AUXDAC_VREF_SEL_DCOUPL, + /*! Use the ADC reference voltage as the DAC's voltage reference source. */ + DAC_VREF_ADCREF = AUXDAC_VREF_SEL_ADCREF, + /*! Use the main supply voltage VDDS as the DAC's voltage reference source. */ + DAC_VREF_VDDS = AUXDAC_VREF_SEL_VDDS, +} DAC_VrefSource; + +/*! + * @brief DACCC26XX Hardware attributes + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. + * + */ +typedef struct +{ + /*! Pin used for DAC output */ + uint_least8_t outputPin; + /*! DAC voltage reference source */ + DAC_VrefSource dacVrefSource; + /*! Internal signal routed to COMPA_IN */ + uint8_t dacCompAInput; + /*! Valid divider to set the sample clock for the DAC */ + uint8_t dacSmplClkDivider; + /*! Flag to determine precharge state when DCOUPL has been selected as voltage reference */ + bool dacPrecharge; +} DACCC26XX_HWAttrs; + +/*! + * @brief DACCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /*! Flag to determine current state of the DAC's output */ + bool isEnabled; + /*! Flag if the instance is in use */ + bool isOpen; + /*! Current DAC code set */ + uint32_t currCode; + /*! Minimum DAC output in uV */ + uint32_t dacOutputMin; + /*! Maximum DAC output in uV */ + uint32_t dacOutputMax; +} DACCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_dac_DACCC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.c b/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.c new file mode 100644 index 00000000..8b5be819 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2015-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) + +/* Externs */ +extern const UDMACC26XX_Config UDMACC26XX_config[]; + +static void UDMACC26XX_initHw(UDMACC26XX_Handle handle); + +/* + * ======== UDMACC26XX_errorDMAHwi ======== + */ + +/*! + * @brief Handler called if the DMA gets an error during transfer. + * + * This function will clear the error. + * + * @param arg A user defined argument. + * + * @return none + */ +void UDMACC26XX_hwiIntFxn(uintptr_t arg) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = ((UDMACC26XX_Handle)arg)->hwAttrs; + + /* Log the error and clear it */ + DebugP_log1("DMA error code: %d\n", uDMAErrorStatusGet(hwAttrs->baseAddr)); + uDMAErrorStatusClear(hwAttrs->baseAddr); +} + +/* + * ======== UDMACC26XX_open ======== + * + */ +UDMACC26XX_Handle UDMACC26XX_open(void) +{ + HwiP_Params hwiParams; + unsigned int key; + UDMACC26XX_Object *object; + UDMACC26XX_HWAttrs const *hwAttrs; + UDMACC26XX_Handle handle; + + /* Get the pointer to the object and the hwAttrs */ + handle = (UDMACC26XX_Handle) & (UDMACC26XX_config[0]); + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Power up and enable clocks for uDMA. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Disable preemption while checking if the UDMACC26XX is open. */ + key = HwiP_disable(); + + if (!object->isOpen) + { + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t)handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int)hwAttrs->intNum, UDMACC26XX_hwiIntFxn, &hwiParams); + + /* make sure to mark the uDMA as opened */ + object->isOpen = true; + + /* initialize the UDMACC26XX hardware */ + UDMACC26XX_initHw(handle); + } + + HwiP_restore(key); + return (handle); +} + +/* + * ======== UDMACC26XX_close ======== + * + */ +void UDMACC26XX_close(UDMACC26XX_Handle handle) +{ + unsigned int key; + UDMACC26XX_Object *object; + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Disable preemption while checking if the UDMACC26XX is open. */ + key = HwiP_disable(); + + /* Only consider to take anything down if uDMA is initialized. */ + if (object->isOpen) + { + if (Power_getDependencyCount(hwAttrs->powerMngrId) == 1) + { + uDMADisable(hwAttrs->baseAddr); + HwiP_destruct(&(object->hwi)); + object->isOpen = false; + } + Power_releaseDependency(hwAttrs->powerMngrId); + } + + HwiP_restore(key); +} + +/* + * ======== UDMACC26XX_initHw ======== + * This functions initializes the UDMACC26XX hardware module. + * + */ +static void UDMACC26XX_initHw(UDMACC26XX_Handle handle) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* Disable all channels */ + UDMACC26XX_channelDisable(handle, 0xFFFFFFFF); + + /* Set the base for the channel control table. */ + uDMAControlBaseSet(hwAttrs->baseAddr, (void *)UDMACC26XX_CONFIG_BASE); + + /* Enable uDMA. */ + uDMAEnable(hwAttrs->baseAddr); +} diff --git a/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.h b/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.h new file mode 100644 index 00000000..48aaaaa6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dma/UDMACC26XX.h @@ -0,0 +1,464 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UDMACC26XX.h + * + * @brief UDMACC26XX driver implementation. + * + * # Driver include # + * The UDMACC26XX header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * The UDMACC26XX driver currently only supports internal use by the drivers + * that use the uDMA peripheral (e.g., SPICC26X2DMA). + * In other words, the application should never call any of the functions in this file. + * + * # General Behavior # + * This driver is used implicitly by other drivers (e.g., the SPICC26X2DMA + * driver) so users should not have to interface to this driver from the + * application. + * The uDMA HW makes use of a control table in RAM which must be 1024 bytes aligned. + * The default base address of this control table is 0x20000400, however this + * can be changed by simply changing UDMACC26XX_CONFIG_BASE. + * The SPICC26X2DMA.h supports SPI0 and SPI1, and uses both TX and RX DMA channels. + * Each control table entry is 16 bytes, so if an application uses both SSI0 and SSI1 + * the total RAM usage will be 4*16=64 bytes. If only one SSI module is used + * only 2*16=32 bytes of RAM is used. Please see [Use cases] (@ref UDMA_26XX_USE_CASES) + * for example. + * + * # Error handling # + * Error handling is handled by the overlying driver which uses the DMA. + * + * # Power management # + * Power management is handled by the overlying driver which uses the DMA. + * + * # Supported functions # + * Note that these functions should never be called from the application, they + * are only called from other drivers. They are however included here for completeness: + * + * | API function | Description | + * |------------------------- |----------------------------------------------------------------| + * | UDMACC26XX_open() | Initialize and enable the uDMA HW and set system dependencies. | + * | UDMACC26XX_close() | Disable uDMA HW and release system dependencies | + * + * @note These functions should not be called by code. These functions are called + * by drivers who're using the DMA. + * + * # Unsupported Functionality # + * The DMA peripheral is unable to access flash memory in the address range 0x0000 - 0x2000 + * on devices based on the Cortex M33+ core (CC26X3/CC26X4) due to security constraints. + * + * # Use Cases @anchor UDMA_26XX_USE_CASES # + * The DMA is only used internally by other drivers, so the application + * should never call any of the functions in this driver directly. + * The only thing that the application is allowed to modify is the base address + * of the DMA control table in RAM. (Default value is 0x2000_0400) + * Remember it must be 1024 bytes aligned. + * @code + * #define UDMACC26XX_CONFIG_BASE 0x20000400 + * @endcode + * + * - If only SSI0 is used, this will allocate 2*16=32 RAM bytes at address:\n + * [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels + * - If only SSI1 is used, this will allocate 2*16=32 RAM bytes at address:\n + * [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels + * - If both SSI0 and SSI1 are used, this will allocate 4*16=64 RAM bytes at addresses:\n + * [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels\n + * [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels + * + * ============================================================================ + */ + +#ifndef ti_drivers_UDMACC26XX__include +#define ti_drivers_UDMACC26XX__include + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/udma.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup DMA_STATUS + * UDMACC26XX_STATUS_* macros are command codes only defined in the + * UDMACC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add DMACC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup DMA_CMD + * UDMACC26XX_CMD_* macros are command codes only defined in the + * UDMACC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add DMACC26XX_CMD_* macros here */ + +/** @}*/ + +/*! Base address for the DMA control table, must be 1024 bytes aligned */ +#if !defined(UDMACC26XX_CONFIG_BASE) + #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + /* On CC13X2, CC13X2X7, CC26X2, and CC26X2X7 devices, the uDMA table needs + * to be offset a few kB since the ROM area of SRAM is placed at the start + * of SRAM on those devices. + */ + #define UDMACC26XX_CONFIG_BASE 0x20001800 + #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + /* + * Since there is no ROM area of SRAM on the CC13X1 and CC26X1 devices, we + * can move the uDMA table closer to the start of SRAM. This improves the + * linker efficiency when using dynamically sized heaps. + */ + #define UDMACC26XX_CONFIG_BASE 0x20000400 + #elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /* + * Since there is no ROM area of SRAM on the CC13X4 and CC26X4 devices, we + * can move the uDMA table closer to the start of SRAM. This improves the + * linker efficiency when using dynamically sized heaps. + */ + #if (TFM_ENABLED == 0) + #define UDMACC26XX_CONFIG_BASE 0x20000400 + #else + #define UDMACC26XX_CONFIG_BASE 0x2000C400 + #endif + #else + #define UDMACC26XX_CONFIG_BASE 0x20000400 + #endif +#endif + +/*! Make sure DMA control table base address is 1024 bytes aligned */ +#if (UDMACC26XX_CONFIG_BASE & 0x3FF) + #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned." +#endif + +/*! Compiler specific macros to allocate DMA control table entries */ +#if defined(__IAR_SYSTEMS_ICC__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + __no_init __root static volatile tDMAControlTable ENTRY_NAME @UDMACC26XX_CONFIG_BASE + \ + (CHANNEL_INDEX) * sizeof(tDMAControlTable) +#elif defined(__TI_COMPILER_VERSION__) || defined(__clang__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + static volatile tDMAControlTable ENTRY_NAME \ + __attribute__((retain, location((UDMACC26XX_CONFIG_BASE) + (CHANNEL_INDEX) * sizeof(tDMAControlTable)))) +#elif defined(__GNUC__) + #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + extern int UDMACC26XX_##ENTRY_NAME##_is_placed; \ + __attribute__((section("." #ENTRY_NAME), used)) static volatile tDMAControlTable ENTRY_NAME = { \ + &UDMACC26XX_##ENTRY_NAME##_is_placed} +#else + #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain" +#endif + +/*! Sets the DMA transfer size in number of items */ +#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) +/*! Gets the DMA transfer size in number of items*/ +#define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1) + +/*! + * @brief UDMACC26XX object + */ +typedef struct +{ + bool isOpen; /*!< Flag for open/close status */ + HwiP_Struct hwi; /*!< Embedded Hwi Object */ +} UDMACC26XX_Object; + +/*! + * @brief UDMACC26XX hardware attributes + */ +typedef struct +{ + uint32_t baseAddr; /*!< Base address for UDMACC26XX */ + PowerCC26XX_Resource powerMngrId; /*!< UDMACC26XX Peripheral's power manager ID */ + uint8_t intNum; /*!< UDMACC26XX error interrupt number */ + /*! @brief UDMACC26XX error interrupt priority. + * intPriority is the DMA peripheral's interrupt priority, as + * defined by the underlying OS. It is passed unmodified to the + * underlying OS's interrupt handler creation code, so you need to + * refer to the OS documentation for usage. If the + * driver uses the ti.dpl interface instead of making OS + * calls directly, then the HwiP port handles the interrupt priority + * in an OS specific way. In the case of the SYS/BIOS port, + * intPriority is passed unmodified to Hwi_create(). + * + * The CC26xx uses three of the priority bits, + * meaning ~0 has the same effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + * critical sections in this driver. + */ + uint8_t intPriority; +} UDMACC26XX_HWAttrs; + +/*! + * @brief UDMACC26XX Global configuration + */ +typedef struct +{ + void *object; /*!< Pointer to UDMACC26XX object */ + void const *hwAttrs; /*!< Pointer to hardware attribute */ +} UDMACC26XX_Config; + +/*! + * @brief A handle that is returned from a UDMACC26XX_open() call. + */ +typedef UDMACC26XX_Config *UDMACC26XX_Handle; + +/* Extern'd hwiIntFxn */ +extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks); + +/*! + * @brief Function to initialize the CC26XX DMA driver + * + * The function will set the isOpen flag to false, and should be called prior + * to opening the DMA driver. + * + * @pre Calling context: Hwi, Swi, Task + * + * @return none + * + * @sa UDMACC26XX_open() + */ +__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle) +{ + UDMACC26XX_Object *object; + + /* Get the pointer to the object */ + object = (UDMACC26XX_Object *)(handle->object); + + /* mark the module as available */ + object->isOpen = false; +} + +/*! + * @brief Function to initialize the CC26XX DMA peripheral + * + * The function will set a dependency on the peripheral power domain, i.e. power up the + * module and enable the clock. + * Note this function always uses the first DMA entry in the global UDMACC26XX_config list. + * + * @pre UDMACC26XX_init() has to be called first. + * Calling context: Task + * + * @return UDMACC26XX_Handle on success or NULL if error or if it has been + * already opened + * + * @sa UDMACC26XX_close() + */ +extern UDMACC26XX_Handle UDMACC26XX_open(void); + +/*! + * @internal + * @brief Function to enable a given DMA channel + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelBitMask A 32-bit bitmask of the channels to enable. + * + * @sa UDMACC26XX_channelDisable + */ +__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Enable DMA channel */ + HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask; +} + +/*! + * @internal + * @brief Function to see if a given DMA channel is done. + * + * Will read the request done signal for the give channels + * and return true if all channels are done, otherwise false. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelBitMask A 32-bit bitmask of the channels to check for if are done. + * + * @return True if the channels are done, false otherwise. + * + * @sa UDMACC26XX_open, UDMACC26XX_channelDisable + */ +__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Check if REQDONE is set for a specific channel */ + return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false; +} + +/*! + * @internal + * @brief Function to clear a given DMA channel interrupt. + * + * Will clear the DMA interrupt(s) for the given bitmask provided. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelBitMask A 32-bit bitmask of the channels to clear interrupts for. + * + * @return none + */ +__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs and object */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + /* Clear UDMA done interrupt */ + uDMAIntClear(hwAttrs->baseAddr, channelBitMask); +} + +/*! + * @internal + * @brief Function to disable one or more DMA channels. + * + * Will disable the channel(s) for the given bitmask provided. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelBitMask A 32-bit bitmask of the channels to disable. + * + * @return none + * + * @sa UDMACC26XX_channelEnable + */ +__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask; +} + +/*! + * @internal + * @brief Function to disable a DMA channel's attributes. + * + * Will disable a channel's attributes. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @param channelNum the channel to configure. + * + * @param attr Channel attribute to disable. + * + * + * @return none + * + * @sa UDMACC26XX_channelEnable + */ +__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, uint32_t channelNum, uint32_t attr) +{ + UDMACC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the hwAttrs */ + hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs); + + uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr); +} + +/*! + * @brief Function to close the DMA driver. + * + * Will disable the DMA hardware, release the power dependency and destruct + * the HWI interrupt. + * + * @pre UDMACC26XX_open() has to be called first. + * Calling context: Task + * + * @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open() + * + * @return none + * + * @sa UDMACC26XX_open + */ +extern void UDMACC26XX_close(UDMACC26XX_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UDMACC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/ClockP.h b/simplelink_lpf2/source/ti/drivers/dpl/ClockP.h new file mode 100644 index 00000000..6dac1af8 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/ClockP.h @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2016-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ClockP.h + * + * @brief Clock interface for the RTOS Porting Interface + * + * The ClockP module can be used to schedule functions that run at intervals + * specified in the underlying kernel's system ticks. ClockP instances are + * one-shot. The one-shot function will be run once + * after the specified period has elapsed since calling #ClockP_start(). + * + * The ClockP module can also be used to obtain the period of the kernel's + * system tick in micro seconds. This is useful for determining the number of + * ticks needed for setting a Clock object's period. + * + * When using the TI-RTOS kernel, ClockP functions are run at software + * interrupt level. With FreeRTOS, the ClockP functions are either run by a + * timer service task with priority configured by the application, or in + * hardware interrupt directly, depending on the device platform. + * + * ============================================================================ + */ + +#ifndef ti_dpl_ClockP__include +#define ti_dpl_ClockP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * ClockP object. + * + * NoRTOS: 32 (biggest of the HW-specific ClockP instance structs) + * BIOS 6.x: 40 + * BIOS 7.x: 36 + * FreeRTOS: 68 + */ +#define ClockP_STRUCT_SIZE (68) + +/*! + * @brief ClockP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific ClockP objects. + */ +typedef union ClockP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[ClockP_STRUCT_SIZE]; +} ClockP_Struct; + +/*! + * @brief Frequency-in-hertz struct + */ +typedef struct +{ + uint32_t hi; /*!< most significant 32-bits of frequency */ + uint32_t lo; /*!< least significant 32-bits of frequency */ +} ClockP_FreqHz; + +/*! + * @brief Status codes for ClockP APIs + */ +typedef enum +{ + ClockP_OK = 0, + ClockP_FAILURE = -1 +} ClockP_Status; + +/*! + * @brief Opaque client reference to an instance of a ClockP + * + * A #ClockP_Handle returned from #ClockP_create() or #ClockP_construct() + * represents that instance. It is then is used in the other instance based + * functions (e.g. #ClockP_start(), #ClockP_stop(), etc.). + */ +typedef void *ClockP_Handle; + +#define ClockP_handle(x) ((ClockP_Handle)(x)) + +/*! + * @brief Prototype for a ClockP callback function. + */ +typedef void (*ClockP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic ClockP Parameters + * + * Structure that contains the parameters passed into #ClockP_create() or + * #ClockP_construct() when creating a ClockP instance. The + * #ClockP_Params_init() function should be used to initialize the fields to + * default values before the application sets the fields manually. The ClockP + * default parameters are noted in #ClockP_Params_init(). + * + * The default startFlag is false, meaning the user will have to call + * #ClockP_start(). If startFlag is true, the clock instance will be + * started automatically when it is created. + * + * The default value of period is 0, indicating a one-shot clock object. + * A non-zero period indicates the clock function will be called + * periodically at the period rate (in system clock ticks), after the + * clock is initially started and set to expire with the 'timeout' + * argument. + */ +typedef struct +{ + bool startFlag; /*!< Start immediately after instance is created. */ + uint32_t period; /*!< Period of clock object. */ + uintptr_t arg; /*!< Argument passed to the clock function. */ +} ClockP_Params; + +/*! + * @brief Function to construct a clock object. + * + * @param clockP Pointer to #ClockP_Struct object. + * @param timeout The startup timeout, if supported by the RTOS. + * @param clockFxn Function called when timeout or period expires. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in #ClockP_Params_init(). + * + * @return A #ClockP_Handle on success or NULL on an error. + */ +extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, + ClockP_Fxn clockFxn, + uint32_t timeout, + ClockP_Params *params); + +/*! + * @brief Function to destruct a clock object + * + * @param clockP Pointer to a #ClockP_Struct object that was passed to + * #ClockP_construct(). + * + * The clock object must be stopped before calling destruct. + */ +extern void ClockP_destruct(ClockP_Struct *clockP); + +/*! + * @brief Function to create a clock object. + * + * This function will allocate memory for the instance's #ClockP_Struct. + * + * @param clockFxn Function called when timeout or period expires. + * @param timeout The startup timeout, if supported by the RTOS. + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The ClockP default + * parameters are noted in #ClockP_Params_init(). + * + * @return A #ClockP_Handle on success or NULL on an error. + */ +extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, uint32_t timeout, ClockP_Params *params); + +/*! + * @brief Function to delete a clock. + * + * @param handle A #ClockP_Handle returned from #ClockP_create() + * + * The clock object must be stopped before calling delete. + */ +extern void ClockP_delete(ClockP_Handle handle); + +/*! + * @brief Get CPU frequency in Hertz + * + * @param freq Pointer to the FreqHz structure + */ +extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); + +/*! + * @brief Get the system tick period in number of micro seconds. + * + * @return The kernel's system tick period in micro seconds. + */ +extern uint32_t ClockP_getSystemTickPeriod(void); + +/*! + * @brief Get the current tick value in number of system ticks. + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 32 bits. + * + * @return Time in system clock ticks + */ +extern uint32_t ClockP_getSystemTicks(void); + +/*! + * @brief Get the current tick value in number of system ticks. + * + * The value returned will wrap back to zero after it reaches the max + * value that can be stored in 64 bits. + * + * @return Time in system clock ticks + */ +extern uint64_t ClockP_getSystemTicks64(void); +/*! + * @brief Get number of ClockP tick periods expected to expire between + * now and the next interrupt from the timer peripheral + * + * Returns the number of ClockP tick periods that are expected to expire + * between now and the next interrupt from the timer peripheral. + * + * Used internally by various Power modules + * + * @return Count in ticks + */ +extern uint32_t ClockP_getTicksUntilInterrupt(void); + +/*! + * @brief Get timeout of clock instance. + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * + * Returns the remaining time in clock ticks if the instance has + * been started. If the clock is not active, the initial timeout value + * is returned. + * + * @return Remaining timeout in clock ticks. + */ +extern uint32_t ClockP_getTimeout(ClockP_Handle handle); + +/*! + * @brief Determine if a clock object is currently active (i.e., running) + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * + * Returns true if the clock object is currently active, otherwise + * returns false. + * + * @return active state + */ +extern bool ClockP_isActive(ClockP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - startFlag: false + * - period: 0 + * - arg: 0 + * + * @param params Pointer to the configuration parameters instance. + */ +extern void ClockP_Params_init(ClockP_Params *params); + +/*! + * @brief Function to overwrite ClockP callback function and arg + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * @param clockFxn Function called when timeout or period expires. + * @param arg Argument passed to \c clockFxn + */ +extern void ClockP_setFunc(ClockP_Handle handle, ClockP_Fxn clockFxn, uintptr_t arg); + +/*! + * @brief Set the initial timeout + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * @param timeout Initial timeout in ClockP ticks + * + * Cannot be used to set the initial timeout if the clock has been started. + */ +extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); + +/*! + * @brief Set the clock period + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * @param period Periodic interval in ClockP ticks + * + * Cannot be used to set the clock period to zero. + */ +extern void ClockP_setPeriod(ClockP_Handle handle, uint32_t period); + +/*! + * @brief Function to start a clock. + * + * @remark In some implementations, it may not always be possible to + * to start a ClockP object with maximum timeout. This situation can + * occur when a very fast tick period is used, and when #ClockP_start() + * is called (by another ISR, by a higher-priority SwiP, or within a + * clock function) while ClockP is in-process of servicing its timeout + * queue. In this case the timeout of the newly-started object may + * occur in the near future rather than in the far future. For + * one-shot objects there will be a single early timeout; for periodic + * objects there will be an early timeout, but the next timeout will + * occur correctly offset from the first timeout. This condition is + * due to a ClockP tick count wrap, and only occurs when there is a + * very fast ClockP tick period such that there are virtual ClockP + * tick period increments between the last timer interrupt to the + * invocation of #ClockP_start(). For example, if the ClockP tick + * period is 10 usec, and if the ClockP tick count is 0x10000005 when + * the interrupt occurs, and if there are 3 intervening tick periods + * (30 usec) before the call to #ClockP_start() in a clock function, + * then the future timeout will be computed as + * 0x10000005 + 3 + 0xFFFFFFFF = 0x10000007, only 2 ticks in the + * future. In this case, the maximum timeout should be limited to + * 0xFFFFFFFD to achieve the maximum delay from the last timer + * interrupt. + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + */ +extern void ClockP_start(ClockP_Handle handle); + +/*! + * @brief Function to stop a clock. + * + * @param handle A #ClockP_Handle returned from #ClockP_create() or + * #ClockP_construct() + * + * It is ok to call #ClockP_stop() for a clock that has not been started. + */ +extern void ClockP_stop(ClockP_Handle handle); + +/*! + * @brief Set delay in micro seconds + * + * @param usec A duration in micro seconds + */ +extern void ClockP_usleep(uint32_t usec); + +/*! + * @brief Set delay in seconds + * + * @param sec A duration in seconds + */ +extern void ClockP_sleep(uint32_t sec); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_ClockP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/DebugP.h b/simplelink_lpf2/source/ti/drivers/dpl/DebugP.h new file mode 100644 index 00000000..325798fd --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/DebugP.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file DebugP.h + * + * @brief Debug support + * + * The DebugP module allows application to do logging and assert checking. + * + * DebugP_assert calls can be added into code. If the code + * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + * + * This module sits on top of the assert checking of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * Similarly, DebugP_logN calls can be added into code. If the code + * is compiled with the compiler define DebugP_LOG_ENABLED set to a + * non-zero value, the call is passed onto the underlying assert checking. + * If DebugP_LOG_ENABLED is zero (or not defined), the calls are + * resolved to nothing. + + * This module sits on top of the logging of the underlying + * RTOS. Please refer to the underlying RTOS port implementation for + * more details. + * + * ============================================================================ + */ + +#ifndef ti_dpl_DebugP__include +#define ti_dpl_DebugP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef DebugP_ASSERT_ENABLED + #define DebugP_ASSERT_ENABLED 0 +#endif + +#ifndef DebugP_LOG_ENABLED + #define DebugP_LOG_ENABLED 0 +#endif + +#if DebugP_ASSERT_ENABLED +extern void _DebugP_assert(int expression, const char *file, int line); + /*! + * @brief Assert checking function + * + * If the expression is evaluated to true, the API does nothing. + * If it is evaluated to false, the underlying RTOS port implementation + * handles the assert via its mechanisms. + * + * @param expression Expression to evaluate + */ + #define DebugP_assert(expression) (_DebugP_assert(expression, __FILE__, __LINE__)) +#else + #define DebugP_assert(expression) +#endif + +#if DebugP_LOG_ENABLED +/*! + * @brief Debug log function with 0 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + */ +extern void DebugP_log0(const char *format); + +/*! + * @brief Debug log function with 1 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + */ +extern void DebugP_log1(const char *format, uintptr_t p1); + +/*! + * @brief Debug log function with 2 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + */ +extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); + +/*! + * @brief Debug log function with 3 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + */ +extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); + +/*! + * @brief Debug log function with 4 parameters + * + * The underlying RTOS port implementation handles the + * logging via its mechanisms. + * + * @param format "printf" format string + * @param p1 first parameter to format string + * @param p2 second parameter to format string + * @param p3 third parameter to format string + * @param p4 fourth parameter to format string + */ +extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); +#else + #define DebugP_log0(format) + #define DebugP_log1(format, p1) + #define DebugP_log2(format, p1, p2) + #define DebugP_log3(format, p1, p2, p3) + #define DebugP_log4(format, p1, p2, p3, p4) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_DebugP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/EventP.h b/simplelink_lpf2/source/ti/drivers/dpl/EventP.h new file mode 100644 index 00000000..677e2398 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/EventP.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** ============================================================================ + * @file EventP.h + * + * @brief Event Group support + * + * Events are a collection of bits with an application-defined meaning, + * typically used for messaging or synchronisation. A task may check the state + * of a set of bits or pend on an EventP object to react to changes when they + * are posted from another context. + * + * Only one Task may pend on a single EventP object at any given time. + * + * Events are synchronous in nature, meaning that a receiving task will block or + * pend while waiting for the events to occur. When the desired events are + * received, the pending task continues its execution, as it would after a call + * to Semaphore_pend(), for example. + * + * EventP_pend is used to wait for events. The eventMask determine which + * event(s) must occur before returning from EventP_pend. The timeout parameter + * allows the task to wait until a timeout, wait indefinitely, or not wait at + * all. If waitForAll is true, the pend call will not return until all of the + * bits in eventMask are set. If it is false, any of the bits in eventMask will + * be returned. A return value of zero indicates that a timeout has occurred. A + * non-zero return value is the set of events that were active at the time the + * task was unblocked. Event bits that caused a return (either the whole + * eventMask or any individual bit, depending on waitForAll) will be cleared + * when EventP_pend returns. + * + * ============================================================================ + */ + +#ifndef ti_dpl_EventP__include +#define ti_dpl_EventP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Event object. + * + * BIOS 6.x: 20 + * BIOS 7.x: 20 + * FreeRTOS: 52 + */ +#define EventP_STRUCT_SIZE (52) + +/*! + * @brief EventP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific EventP objects. + */ +typedef union EventP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[EventP_STRUCT_SIZE]; +} EventP_Struct; + +/*! + * @brief Wait forever define + */ +#define EventP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define EventP_NO_WAIT (0) + +/*! + * @brief Opaque client reference to an instance of a EventP + * + * A EventP_Handle returned from create or construct represents that instance. + */ +typedef EventP_Struct *EventP_Handle; + +/*! + * @brief Create an EventP, allocating memory on the heap. + * + * EventP_create creates a new event object. EventP_create returns the + * handle of the new task object or NULL if the event could not be created. + * + * When created, no bits of an event are set. For FreeRTOS, + * configSUPPORT_DYNAMIC_ALLOCATION also has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do + * this. + * + * This API cannot be called from interrupt contexts. + * + * @retval EventP handle (NULL on failure) + */ +extern EventP_Handle EventP_create(void); + +/*! + * @brief Function to delete an EventP. + * + * @param handle A EventP_Handle returned from EventP_create + */ +extern void EventP_delete(EventP_Handle handle); + +/*! + * @brief Construct an EventP, using statically allocated memory. + * + * EventP_construct creates a new event object. EventP_construct returns the + * handle of the new task object or NULL if the event could not be created. + * + * When created, no bits of an event are set. For FreeRTOS, + * configSUPPORT_STATIC_ALLOCATION also has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do + * this. + * + * This API cannot be called from interrupt contexts. + * + * @retval EventP handle (NULL on failure) + */ +extern EventP_Handle EventP_construct(EventP_Struct *obj); + +/*! + * @brief Function to destruct an EventP + * + * @param obj Pointer to a EventP_Struct object that was passed to + * EventP_construct(). + * + * @return + */ +extern void EventP_destruct(EventP_Struct *obj); + +/*! + * @brief Wait for the events listed in eventMask. + * + * EventP_pend is used to wait for events. The eventMask determine which event(s) + * must occur before returning from EventP_pend. The timeout parameter allows the + * task to wait until a timeout, wait indefinitely, or not wait at all. If + * waitForAll is true, the pend call will not return until all of the bits in + * eventMask are set. If it is false, any of the bits in eventMask will be + * returned. A return value of zero indicates that a timeout has occurred. A + * non-zero return value is the set of events in the eventMask that were active + * at the time the task was unblocked. + * + * Event bits that caused a return (either the whole eventMask or any individual + * bit, depending on waitForAll) will be cleared when EventP_pend returns. + * + * A timeout value of EventP_WAIT_FOREVER causes the task to wait indefinitely + * for matching events to be posted. A timeout value of EventP_NO_WAIT causes + * EventP_pend to return immediately. + * + * This API cannot be called from interrupt contexts. + * + * @param event Event handle + * @param eventMask Match against the events in this bitmask. For FreeRTOS, + * only the 24 least significant bits in the event mask may + * be set, meaning the maximum allowed value for FreeRTOS + * is 0x00FFFFFF. + * @param waitForAll If true, only return when all matching bits are set + * @param timeout Return after this many ClockP ticks, even if there is no match + * + * @retval A bitmask containing all consumed events, or zero on timeout. + */ +extern uint32_t EventP_pend(EventP_Handle event, uint32_t eventMask, bool waitForAll, uint32_t timeout); + +/*! + * @brief Post events to an event object. + * + * EventP_post() is used to signal events. If a task is waiting for the event + * and the event conditions are met, EventP_post() unblocks the task. If no + * tasks are waiting, EventP_post() simply registers the event with the event + * object and returns. + * + * @param event Event handle + * @param eventMask Mask of eventIds to post (this must be non-zero). For + * FreeRTOS, only the 24 least significant bits in the + * event mask may be set, meaning the maximum allowed value + * for FreeRTOS is 0x00FFFFFF. + */ +extern void EventP_post(EventP_Handle event, uint32_t eventMask); + +/*! + * @brief Clear events from an event object. + * + * Clears the bits in eventMask from the EventP. + * + * @param event Event handle + * @param eventMask Mask of eventIds to clear (this must be non-zero). For + * FreeRTOS, only the 24 least significant bits in the + * event mask may be set, meaning the maximum allowed value + * for FreeRTOS is 0x00FFFFFF. + */ +extern void EventP_clear(EventP_Handle event, uint32_t eventMask); + +/*! + * @brief Get the current events from an event object. + * + * Returns the currently active events in an EventP without clearing them. + * + * @param event Event handle + * + * @retval Currently active events + */ +extern uint32_t EventP_get(EventP_Handle event); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_EventP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/HwiP.h b/simplelink_lpf2/source/ti/drivers/dpl/HwiP.h new file mode 100644 index 00000000..f8a34230 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/HwiP.h @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file HwiP.h + * + * @brief Hardware Interrupt module for the RTOS Porting Interface + * + * The #HwiP_disable()/#HwiP_restore() APIs can be called recursively. The + * order of the #HwiP_restore() calls, must be in reversed order. For example: + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @anchor ti_drivers_HwiP_Cross_Platform_Considerations + * ## Cross-platform Considerations ## + * The following sections highlight some important items to consider when + * using the HwiP DPL. Due to the nature and intention of different operating + * systems, the HwiP DPL implementation may differ depending on the underlying + * platform and operating system. + * + * ### Arm Cortex-M Interrupt Priorities ### + * On Arm Cortex-M platforms, the highest logical interrupt priority has the + * lowest numerical value. That is, 0 is the highest interrupt priority + * (interrupt level 0 has the highest urgency). The number of interrupt + * priorities is given by the number of interrupt priority bits implemented, + * which is vendor-specific. + * + * For example: + * + * | Device Family | Architecture | Priority Bits | Priority Levels | + * |---------------|--------------|---------------|-----------------| + * | CC23X0 | Armv6-m | 2 | 4 (0-3) | + * | CC13X2_CC26X2 | Armv7-m | 3 | 8 (0-7) | + * | CC13X4_CC26X4 | Armv8-m | 3 | 8 (0-7) | + * | CC27XX | Armv8-m | 4 | 16 (0-15) | + * + * On Arm Cortex-M platforms, interrupt priority values are stored in the most + * significant bits of the 8-bit interrupt priority registers. For example, + * with 3 interrupt priority bits implemented, interrupt priority level 2 + * (0b010) is represented in the interrupt priority registers as + * 0b010 << (8-3) = 0x40. + * This is automatically handled by SysConfig, but may cause some confusion, + * for example, when inspecting the raw value of the #HwiP_Params.priority + * field or the Cortex-M interrupt priority registers. + * + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html for more details. + * + * Arm Cortex-M devices may support 2 methods for masking interrupts + * - \c PRIMASK disables all interrupt levels indiscriminately (with the + * exception of non-maskable interrupts). + * - \c BASEPRI disables interrupts with priority equal to or lower than a + * certain level. Software can set \c BASEPRI to a priority level between 1 + * (second highest priority) and the maximum supported priority level + * (lowest priority). This means that interrupt priority level 0 cannot be + * masked using \c BASEPRI. + * + * The table gives an overview of what interrupt masking controls the different + * Arm platforms support: + * + * | Architecture | PRIMASK | BASEPRI | + * |--------------|:-------:|:-------:| + * | Armv6-m | Yes | No | + * | Armv7-m | Yes | Yes | + * | Armv8-m | Yes | Yes | + * + * ### FreeRTOS ### + * On Cortex-M platforms that support \c BASEPRI, the FreeRTOS kernel does not + * completely disable interrupts even inside critical sections. This is + * achieved by these FreeRTOS configurations: + * + * - \c configMAX_SYSCALL_INTERRUPT_PRIORITY defines the highest logical + priority at which FreeRTOS kernel API calls can be made. + * - \c configKERNEL_INTERRUPT_PRIORITY sets the priority of the FreeRTOS + kernel itself, usually the lowest logical priority possible. + * + * This permits a fully nested model where higher-priority interrupts can + * preempt lower-priority ones. However, interrupts that require FreeRTOS API + * calls must adhere to the \c configMAX_SYSCALL_INTERRUPT_PRIORITY limit to + * avoid corrupting kernel data. + * + * See https://www.freertos.org/a00110.html#kernel_priority for more details. + * + * - #HwiP_disable(): sets \c BASEPRI to \c + * configMAX_SYSCALL_INTERRUPT_PRIORITY. Returns original \c BASEPRI. + * - #HwiP_restore() sets \c BASEPRI to 0 (no interrupts are masked). + * + * ### TI-RTOS ### + * TI-RTOS behaves similar to FreeRTOS, meaning that on Cortex-M platforms that + * support \c BASEPRI, the TI-RTOS kernel does not completely disable + * interrupts even inside critical sections. + * + * - #HwiP_disable() sets \c BASEPRI to \c Hwi_disablePriority. Returns + * original \c BASEPRI. + * - #HwiP_restore() sets \c BASEPRI to the provided argument value. + * + * See TI-RTOS Hwi documentation for more details. + * + * ### NoRTOS ### + * - #HwiP_disable() disables all interrupt levels indiscriminately. + * - #HwiP_restore() globally enables all interrupts. + * + * ============================================================================ + */ + +#ifndef ti_dpl_HwiP__include +#define ti_dpl_HwiP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * HwiP object. + * + * NoRTOS: 12 + * FreeRTOS: 12 + * BIOS 6.x: 28 + * BIOS 7.x: 20 + */ +#define HwiP_STRUCT_SIZE (28) + +/*! + * @brief HwiP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS + * specific HwiP objects. + */ +typedef union HwiP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[HwiP_STRUCT_SIZE]; +} HwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a HwiP + * + * A HwiP_Handle returned from the #HwiP_create() represents that instance. + */ +typedef void *HwiP_Handle; + +/*! + * @brief Status codes for HwiP APIs + */ +typedef enum +{ + HwiP_OK = 0, + HwiP_FAILURE = -1 +} HwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*HwiP_Fxn)(uintptr_t arg); + +/*! + * @brief Basic HwiP Parameters + * + * Structure that contains the parameters passed into #HwiP_create() + * when creating a HwiP instance. The #HwiP_Params_init() function should + * be used to initialize the fields to default values before the application sets + * the fields manually. The HwiP default parameters are noted in + * #HwiP_Params_init(). + * + * Parameter enableInt specifies if the interrupt should be enabled + * upon creation of the HwiP object. The default is true. + */ +typedef struct +{ + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority encoded using the device + * platform's internal priority representation. + * See @ref ti_drivers_HwiP_Cross_Platform_Considerations + */ + bool enableInt; /*!< Enable interrupt on creation. */ +} HwiP_Params; + +/*! + * @brief Interrupt number posted by SwiP + * + * The SwiP module needs its scheduler to run at key points in SwiP + * processing. This is accomplished via an interrupt that is configured + * at the lowest possible interrupt priority level and is plugged with + * the SwiP scheduler. This interrupt must be the *only* interrupt at + * that lowest priority. SwiP will post this interrupt whenever its + * scheduler needs to run. + * + * The default value for your device should suffice, but if a different + * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum + * can be assigned with this interrupt (early on, before HwiPs are created + * and before any SwiP gets posted). + */ +extern int HwiP_swiPIntNum; + +/*! + * @brief Function to construct a hardware interrupt object. + * + * @param hwiP Pointer to HwiP_Struct object. + * @param interruptNum Interrupt Vector Id + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in #HwiP_Params_init(). + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params); + +/*! + * @brief Function to destruct a hardware interrupt object + * + * @param hwiP Pointer to a HwiP_Struct object that was passed to + * #HwiP_construct(). + * + * @return + */ +extern void HwiP_destruct(HwiP_Struct *hwiP); + +/*! + * @brief Function to clear a single interrupt + * + * @param interruptNum interrupt number to clear + */ +extern void HwiP_clearInterrupt(int interruptNum); + +/*! + * @brief Function to create an interrupt on CortexM devices + * + * @note This function may not be available on all implementations + * + * @param interruptNum Interrupt Vector Id + * + * @param hwiFxn entry function of the hardware interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The HwiP default + * parameters are noted in #HwiP_Params_init(). + * + * @return A HwiP_Handle on success or a NULL on an error + */ +extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params); + +/*! + * @brief Function to delete an interrupt on CortexM devices + * + * @note This function may not be available on all implementations + * + * @param handle returned from the HwiP_create call + * + * @return + */ +extern void HwiP_delete(HwiP_Handle handle); + +/*! + * @brief Function to disable interrupts to enter a critical region + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = HwiP_disable(); + * key2 = HwiP_disable(); + * HwiP_restore(key2); + * HwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to #HwiP_restore() to re-enable interrupts. + */ +extern uintptr_t HwiP_disable(void); + +/*! + * @brief Function to enable interrupts + */ +extern void HwiP_enable(void); + +/*! + * @brief Function to disable a single interrupt + * + * @param interruptNum interrupt number to disable + */ +extern void HwiP_disableInterrupt(int interruptNum); + +/*! + * @brief Function to enable a single interrupt + * + * @param interruptNum interrupt number to enable + */ +extern void HwiP_enableInterrupt(int interruptNum); + +/*! + * @brief Function to return a status based on whether it is in an interrupt + * context. + * + * @return A status: indicating whether the function was called in an + * ISR (true) or at thread level (false). + */ +extern bool HwiP_inISR(void); + +/*! + * @brief Function to determine whether interrupts are currently enabled. + * + * @return Current state of interrupts. + * - true Interrupts are currently enabled. + * - false Interrupts are currently disabled. + */ +extern bool HwiP_interruptsEnabled(void); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - arg: 0 + * - priority: ~0 + * - enableInt: true + * + * @param params Pointer to the instance configuration parameters. + */ +extern void HwiP_Params_init(HwiP_Params *params); + +/*! + * @brief Function to plug an interrupt vector + * + * @param interruptNum ID of interrupt to plug + * @param fxn ISR that services plugged interrupt + */ +extern void HwiP_plug(int interruptNum, void *fxn); + +/*! + * @brief Function to generate an interrupt + * + * @param interruptNum ID of interrupt to generate + */ +extern void HwiP_post(int interruptNum); + +/*! + * @brief Function to restore interrupts to exit a critical region + * + * @param key return from HwiP_disable + */ +extern void HwiP_restore(uintptr_t key); + +/*! + * @brief Function to overwrite HwiP function and arg + * + * @param hwiP handle returned from the HwiP_create or construct call + * @param fxn pointer to ISR function + * @param arg argument to ISR function + */ +extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); + +/*! + * @brief Function to set the priority of a hardware interrupt + * + * @param interruptNum id of the interrupt to change + * @param priority new priority + */ +extern void HwiP_setPriority(int interruptNum, uint32_t priority); + +/*! + * @brief Function to call the HW ISR function registered by #HwiP_construct() + * + * @note This function may not be available on all implementations + * + * @param interruptNum Interrupt Vector Id + */ +void HwiP_dispatchInterrupt(int interruptNum); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_HwiP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/MessageQueueP.h b/simplelink_lpf2/source/ti/drivers/dpl/MessageQueueP.h new file mode 100644 index 00000000..fc5d71f6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/MessageQueueP.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2023-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MessageQueueP.h + * + * @brief MessageQueue module for the RTOS Porting Interface + * + * MessageQueueP objects are RTOS message queues backed by OS-specific queue or + * mailbox objects. + * + * Message queues can be used for intertask communication. They support sending + * messages between tasks, and between interrupts and tasks. + * Message queues can either be allocated statically with + * #MessageQueueP_construct() or dynamically with #MessageQueueP_create(). + * + * ============================================================================ + */ + +#ifndef ti_dpl_MessageQueueP__include +#define ti_dpl_MessageQueueP__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Queue/Mailbox data structure. + * + * TI-RTOS7: 104 + * FreeRTOS: 80 + */ +#define MessageQueueP_STRUCT_SIZE (104) + +/*! + * @brief Required number of bytes of a statically allocated message queue buffer. + * + * This macro is defined to support the user in configuring the size of a message queue + * buffer. A pointer to this user defined buffer is one of the arguments of the + * #MessageQueueP_construct() function. + * The macro gives the minimal number of bytes required for the message queue. + * Please note the following for devices supporting TI-RTOS7: + * - The macro takes into account an eight byte message header which is only required + * by TI-RTOS and not by FreeRTOS. For user applications only targeting FreeRTOS, + * SRAM usage can be limited by setting the buffer size to (msgCount * msgSize) + * instead of using this macro. + */ +#if ((DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) || \ + (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4)) + #define MessageQueueP_BUFFER_SIZE(msgSize, msgCount) ((msgCount) * ((msgSize) + 8)) +#else + #define MessageQueueP_BUFFER_SIZE(msgSize, msgCount) ((msgCount) * (msgSize)) +#endif + +/*! + * @brief MessageQueueP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS specific MessageQueueP objects. + */ +typedef union MessageQueueP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[MessageQueueP_STRUCT_SIZE]; +} MessageQueueP_Struct; + +/*! + * @brief Wait forever define + */ +#define MessageQueueP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define MessageQueueP_NO_WAIT (0) + +/*! + * @brief Status codes for MessageQueueP APIs + */ +typedef enum +{ + /*! API completed successfully */ + MessageQueueP_OK = 0, + /*! API failed because of a timeout */ + MessageQueueP_TIMEOUT = -1 +} MessageQueueP_Status; + +/*! + * @brief Opaque client reference to an instance of a MessageQueueP + * + * A MessageQueueP_Handle returned from #MessageQueueP_create() or + * #MessageQueueP_construct() represents that instance. It is then is used + * in the other instance based functions (e.g. #MessageQueueP_pend(), + * #MessageQueueP_post(), etc.). + */ +typedef void *MessageQueueP_Handle; + +/*! + * @brief Create a MessageQueueP, allocating memory on the heap. + * + * #MessageQueueP_create creates a new message queue object. #MessageQueueP_create + * returns the handle of the new message queue object or NULL if the message queue + * could not be created. + * + * The message queue object will be allocated on the heap - make sure you have a + * sufficiently large heap. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, configSUPPORT_DYNAMIC_ALLOCATION has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @param msgSize The size, in bytes, required to hold each item in the message queue + * @param msgCount The maximum number of items the message queue can hold at any one time + * + * @retval MessageQueueP handle (NULL on failure) + */ +extern MessageQueueP_Handle MessageQueueP_create(size_t msgSize, size_t msgCount); + +/*! + * @brief Construct a MessageQueueP from statically allocated memory. + * + * #MessageQueueP_construct creates a new message queue object. #MessageQueueP_construct + * returns the handle of the new message queue object or NULL if the message queue + * could not be created. + * + * To use #MessageQueueP_construct \a msgBuf must point to a valid preallocated memory + * array that is at least large enough to hold the maximum number of items that can be + * in the message queue at any one time. + * - When used with FreeRTOS the array size must be at least ( \a msgCount * \a msgSize) bytes. + * - When used with TI-RTOS the array size must be at least ( \a msgCount * ( \a msgSize + 8)) bytes. + * - Since the buffer must be a aligned properly, it may be necessary to 'round up' the total size + * of the buffer to the next multiple of the alignment for odd sized messages. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, configSUPPORT_STATIC_ALLOCATION has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @param queueStruct Must point to a variable that holds the message queue's data structure + * @param msgSize The size, in bytes, required to hold each item in the message queue + * @param msgCount The maximum number of items the message queue can hold at any one time + * @param msgBuf Pointer to variable that holds the message queue's data buffer + * + * @retval MessageQueueP handle (NULL on failure) + */ +MessageQueueP_Handle MessageQueueP_construct(MessageQueueP_Struct *queueStruct, + size_t msgSize, + size_t msgCount, + void *msgBuf); + +/*! + * @brief Delete a MessageQueueP. + * + * #MessageQueueP_delete finalizes and frees this previously allocated message queue + * object, setting the referenced handle to NULL. + * This function should be used when the message queue was created by the + * #MessageQueueP_create() function. + * + * \note This API cannot be called from interrupt contexts. + * + * @param handle A handle to the message queue to be deleted + */ +extern void MessageQueueP_delete(MessageQueueP_Handle handle); + +/*! + * @brief Destruct a MessageQueueP. + * + * #MessageQueueP_destruct finalizes the message queue object inside the provided structure. + * This function should be used when the message queue was constructed by the + * #MessageQueueP_construct() function. + * + * \note This API cannot be called from interrupt contexts. + * + * @param handle A handle to the message queue to be destructed + */ +extern void MessageQueueP_destruct(MessageQueueP_Handle handle); + +/*! + * @brief Receive an item from a message queue. + * + * #MessageQueueP_pend receives an item from the provided message queue. + * + * @param handle The handle to the message queue from which the item is to be received + * @param message Pointer to the buffer into which the received item will be copied + * @param timeout The maximum duration in system clock ticks a task should block waiting + * for an item to be received. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item recieved + * - #MessageQueueP_TIMEOUT: Timed out. Item was not recieved. + */ +extern MessageQueueP_Status MessageQueueP_pend(MessageQueueP_Handle handle, void *message, uint32_t timeout); + +/*! + * @brief Receive an item from a message queue without removing the item from the queue. + * + * #MessageQueueP_peek receives an item from the provided message queue without removing the + * item from the queue. + * + * @param handle The handle to the message queue from which the item is to be received + * @param message Pointer to the buffer into which the received item will be copied + * @param timeout The maximum duraton in system clock ticks a task should block waiting + * for an item to be received. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item recieved + * - #MessageQueueP_TIMEOUT: Timed out. Item was not recieved. + */ +extern MessageQueueP_Status MessageQueueP_peek(MessageQueueP_Handle handle, void *message, uint32_t timeout); + +/*! + * @brief Post an item on a message queue. + * + * #MessageQueueP_post posts an item on the provided message queue. + * + * @param handle The handle to the message queue to which the item is to be posted + * @param message Pointer to the buffer from which the item to be posted is copied + * @param timeout The maximum duraton in system clock ticks a task should block waiting + * for an item to be posted. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item posted + * - #MessageQueueP_TIMEOUT: Timed out. Item was not posted. + */ +extern MessageQueueP_Status MessageQueueP_post(MessageQueueP_Handle handle, const void *message, uint32_t timeout); + +/*! + * @brief Post an item in the front of a message queue. + * + * #MessageQueueP_postFront posts an item in the front of the provided message queue. + * + * @param handle The handle to the message queue to which the item is to be posted + * @param message Pointer to the buffer from which the item to be posted is copied + * @param timeout The maximum duraton in system clock ticks a task should block waiting + * for an item to be posted. When no wait or wait forever options are + * wanted the #MessageQueueP_NO_WAIT and #MessageQueueP_WAIT_FOREVER defines + * can be used. + * + * @retval Status of the function + * - #MessageQueueP_OK: Item posted + * - #MessageQueueP_TIMEOUT: Timed out. Item was not posted. + */ +extern MessageQueueP_Status MessageQueueP_postFront(MessageQueueP_Handle handle, const void *message, uint32_t timeout); + +/*! + * @brief Get the number of messages stored in a message queue. + * + * Returns the number of messages in the specified message queue. + * + * @param handle A MessageQueueP_Handle returned from #MessageQueueP_create() + * or #MessageQueueP_construct() + * + * @retval Number of stored messages in the specified message queue + */ +extern size_t MessageQueueP_getPendingCount(MessageQueueP_Handle handle); + +/*! + * @brief Get the number of free spaces in a message queue. + * + * Returns the number of free spaces in the specified message queue. + * + * @param handle A MessageQueueP_Handle returned from #MessageQueueP_create() + * or #MessageQueueP_construct() + * + * @retval Number of free spaces in the specified message queue + */ +extern size_t MessageQueueP_getFreeCount(MessageQueueP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MessageQueueP__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/dpl/MutexP.h b/simplelink_lpf2/source/ti/drivers/dpl/MutexP.h new file mode 100644 index 00000000..38d18ed6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/MutexP.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file MutexP.h + * + * @brief Mutex module for the RTOS Porting Interface + * + * The MutexP module allows tasks to maintain critical region segments. The + * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. + * + * The MutexP module supports recursive calls to the MutexP_lock API by a + * single task. The same number of MutexP_unlock calls must be done for the + * mutex to be release. Note: the returned key must be provided in the LIFO + * order. For example: + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_unlock(key2); + * MutexP_unlock(key1); + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_dpl_MutexP__include +#define ti_dpl_MutexP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * MutexP object. + * + * NoRTOS: 12 + * BIOS 6.x: 40 + * BIOS 7.x: 40 + * FreeRTOS: 80 + */ +#define MutexP_STRUCT_SIZE (80) + +/*! + * @brief MutexP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific MutexP objects. + */ +typedef union MutexP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[MutexP_STRUCT_SIZE]; +} MutexP_Struct; + +/*! + * @brief Status codes for MutexP APIs + */ +typedef enum +{ + /*! API completed successfully */ + MutexP_OK = 0, + /*! API failed */ + MutexP_FAILURE = -1 +} MutexP_Status; + +/*! + * @brief Opaque client reference to an instance of a MutexP + * + * A MutexP_Handle returned from the ::MutexP_create represents that instance. + * and then is used in the other instance based functions (e.g. ::MutexP_lock, + * ::MutexP_unlock, etc.). + */ +typedef void *MutexP_Handle; + +/*! + * @brief Basic MutexP Parameters + * + * Structure that contains the parameters are passed into ::MutexP_create + * when creating a MutexP instance. The ::MutexP_Params_init function should + * be used to initialize the fields to default values before the application + * sets the fields manually. The MutexP default parameters are noted in + * ::MutexP_Params_init. + */ +typedef struct +{ + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ +} MutexP_Params; + +/*! + * @brief Function to construct a mutex. + * + * @param handle Pointer to a MutexP_Struct object + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (MutexP default + * parameters as noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, MutexP_Params *params); + +/*! + * @brief Function to destruct a mutex object + * + * @param mutexP Pointer to a MutexP_Struct object that was passed to + * MutexP_construct(). + * + * @return + */ +extern void MutexP_destruct(MutexP_Struct *mutexP); + +/*! + * @brief Function to create a mutex. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The MutexP default + * parameters are noted in ::MutexP_Params_init. + * + * @return A MutexP_Handle on success or a NULL on an error + */ +extern MutexP_Handle MutexP_create(MutexP_Params *params); + +/*! + * @brief Function to delete a mutex. + * + * @param handle A MutexP_Handle returned from MutexP_create + */ +extern void MutexP_delete(MutexP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * callback - NULL. + * + * @param params Pointer to the instance configuration parameters. + */ +extern void MutexP_Params_init(MutexP_Params *params); + +/*! + * @brief Function to lock a mutex. + * + * This function can only be called from a Task. It cannot be called from + * an interrupt. The lock will block until the mutex is available. + * + * Users of a mutex should make every attempt to minimize the duration that + * that they have it locked. This is to minimize latency. It is recommended + * that the users of the mutex do not block while they have the mutex locked. + * + * This function locks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @return A key is returned. This key must be passed into ::MutexP_unlock. + */ +extern uintptr_t MutexP_lock(MutexP_Handle handle); + +/*! + * @brief Function to unlock a mutex + * + * This function unlocks the mutex. If the mutex is locked multiple times + * by the caller, the same number of unlocks must be called. The order of + * the keys must be reversed. For example + * @code + * uintptr_t key1, key2; + * key1 = MutexP_lock(); + * key2 = MutexP_lock(); + * MutexP_unlock(key2); + * MutexP_unlock(key1); + * @endcode + * + * @param handle A MutexP_Handle returned from ::MutexP_create + * + * @param key Return from ::MutexP_lock. + */ +extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_MutexP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/SemaphoreP.h b/simplelink_lpf2/source/ti/drivers/dpl/SemaphoreP.h new file mode 100644 index 00000000..6de02f9c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/SemaphoreP.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SemaphoreP.h + * + * @brief Semaphore module for the RTOS Porting Interface + * + * Semaphores can be counting semaphores or binary semaphores. Counting + * semaphores keep track of the number of times the semaphore has been posted + * with post functions. This is useful, for example, if you have a group of + * resources that are shared between tasks. Such tasks might call pend() to see + * if a resource is available before using one. A count of zero for a counting + * semaphore denotes that it is not available. A positive count denotes + * how many times a SemaphoreP_pend can be called before it is blocked (or + * returns SemaphoreP_TIMEOUT). + * + * Binary semaphores can have only two states: available (count = 1) and + * unavailable (count = 0). They can be used to share a single resource + * between tasks. They can also be used for a basic signalling mechanism, where + * the semaphore can be posted multiple times. Binary semaphores do not keep + * track of the count; they simply track whether the semaphore has been posted + * or not. + * + * ============================================================================ + */ + +#ifndef ti_dpl_SemaphoreP__include +#define ti_dpl_SemaphoreP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SemaphoreP object. + * + * NoRTOS: 16 + * BIOS 6.x: 28 + * BIOS 7.x: 28 + * FreeRTOS: 80 + */ +#define SemaphoreP_STRUCT_SIZE (80) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SemaphoreP objects. + */ +typedef union SemaphoreP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[SemaphoreP_STRUCT_SIZE]; +} SemaphoreP_Struct; + +/*! + * @brief Wait forever define + */ +#define SemaphoreP_WAIT_FOREVER ~(0) + +/*! + * @brief No wait define + */ +#define SemaphoreP_NO_WAIT (0) + +/*! + * @brief Status codes for SemaphoreP APIs (for backwards compatibility) + */ +typedef enum +{ + /*! API completed successfully */ + SemaphoreP_OK = 0, + /*! API failed because of a timeout */ + SemaphoreP_TIMEOUT = -1 +} SemaphoreP_Status; + +/*! + * @brief Opaque client reference to an instance of a SemaphoreP + * + * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that + * instance and is used in the other instance based functions (e.g. + * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). + */ +typedef void *SemaphoreP_Handle; + +/*! + * @brief Mode of the semaphore + */ +typedef enum +{ + SemaphoreP_Mode_COUNTING = 0x0, + SemaphoreP_Mode_BINARY = 0x1 +} SemaphoreP_Mode; + +/*! + * @brief Basic SemaphoreP Parameters + * + * Structure that contains the parameters are passed into ::SemaphoreP_create + * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function + * should be used to initialize the fields to default values before the + * application sets the fields manually. The SemaphoreP default parameters are + * noted in SemaphoreP_Params_init. + */ +typedef struct +{ + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ +} SemaphoreP_Params; + +/*! + * @brief Default SemaphoreP instance parameters + * + * SemaphoreP_defaultParams represents the default parameters that are + * used when creating or constructing a SemaphoreP instance. + * SemaphoreP_Params_init() will use the contents of this structure for + * initializing the SemaphoreP_Params instance. + * + * SemaphoreP_defaultParams is exposed to the application for the purpose + * of allowing the application to change the default parameters for all + * SemaphoreP instances created thereafter. The main intent for allowing + * the default parameters to be changed is for setting a semaphore's + * callback function to Power_idleFunc(), so that the SOC can enter low + * power mode when pending on a semaphore. + */ +extern SemaphoreP_Params SemaphoreP_defaultParams; + +/* + * SemaphoreP construct APIs can only be used if one of the OS's + * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also + * has to be set to 1 in FreeRTOSConfig.h. + */ +extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, unsigned int count, SemaphoreP_Params *params); + +extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, unsigned int count); + +extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); + +/*! + * @brief Function to create a semaphore. + * + * @param count Initial count of the semaphore. For binary semaphores, + * only values of 0 or 1 are valid. + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters (SemaphoreP default + * parameters as noted in ::SemaphoreP_Params_init. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, SemaphoreP_Params *params); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); + +/*! + * @brief Function to create a binary semaphore. + * + * This can be used instead of SemaphoreP_create() to create a binary + * semaphore. + * + * @param count Initial count of the binary semaphore. Only values + * of 0 or 1 are valid. + * @param callback Callback while pending for semaphore post + * + * @return A SemaphoreP_Handle on success or a NULL on an error + */ +extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, void (*callback)(void)); + +/*! + * @brief Function to delete a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_delete(SemaphoreP_Handle handle); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - mode: SemaphoreP_Mode_COUNTING + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SemaphoreP_Params_init(SemaphoreP_Params *params); + +/*! + * @brief Function to pend (wait) on a semaphore. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + * + * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to + * be posted (signalled). + * + * @return Status of the functions + * - SemaphoreP_OK: Obtained the semaphore + * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. + */ +extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout); + +/*! + * @brief Function to post (signal) a semaphore from task of ISR context. + * + * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create + */ +extern void SemaphoreP_post(SemaphoreP_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SemaphoreP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/SwiP.h b/simplelink_lpf2/source/ti/drivers/dpl/SwiP.h new file mode 100644 index 00000000..989acb84 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/SwiP.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SwiP.h + * + * @brief Software Interrupt module for the RTOS Porting Interface + * + * ============================================================================ + */ + +#ifndef ti_dpl_SwiP__include +#define ti_dpl_SwiP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS + * SwiP object. + * + * NoRTOS: 40 + * FreeRTOS: ?? (should same as NoRTOS) + * BIOS 6.x: 52 + * BIOS 7.x: 60 + */ +#define SwiP_STRUCT_SIZE (60) + +/*! + * @brief SemaphoreP structure. + * + * Opaque structure that should be large enough to hold any of the + * RTOS specific SwiP objects. + */ +typedef union SwiP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[SwiP_STRUCT_SIZE]; +} SwiP_Struct; + +/*! + * @brief Opaque client reference to an instance of a SwiP + * + * A SwiP_Handle returned from the ::SwiP_create represents that instance. + */ +typedef void *SwiP_Handle; + +/*! + * @brief Status codes for SwiP APIs + */ +typedef enum +{ + SwiP_OK = 0, + SwiP_FAILURE = -1 +} SwiP_Status; + +/*! + * @brief Prototype for the entry function for a hardware interrupt + */ +typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); + +/*! + * @brief Basic SwiP Parameters + * + * Structure that contains the parameters passed into ::SwiP_create + * and ::SwiP_construct when creating or constructing a SwiP instance. + * The ::SwiP_Params_init function should be used to initialize the + * fields to default values before the application sets the fields + * manually. The SwiP default parameters are noted in ::SwiP_Params_init. + * + * Each SwiP object has a "trigger" used either to determine whether to + * post the SwiP or as a value that can be evaluated within the SwiP's + * function. + * + * The SwiP_andn and SwiP_dec functions post the SwiP + * if the trigger value transitions to 0. The SwiP_or and + * SwiP_inc functions also modify the trigger value. SwiP_or + * sets bits, and SwiP_andn clears bits. + */ +typedef struct +{ + uintptr_t arg0; /*!< Argument passed into the SwiP function. */ + uintptr_t arg1; /*!< Argument passed into the SwiP function. */ + uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ + uint32_t trigger; /*!< Initial SwiP trigger value. */ +} SwiP_Params; + +/*! + * @brief Function to construct a software interrupt object. + * + * @param swiP Pointer to SwiP_Struct object. + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, SwiP_Params *params); + +/*! + * @brief Function to destruct a software interrupt object + * + * @param swiP Pointer to a SwiP_Struct object that was passed to + * SwiP_construct(). + * + * @return + */ +extern void SwiP_destruct(SwiP_Struct *swiP); + +/*! + * @brief Initialize params structure to default values. + * + * The default parameters are: + * - name: NULL + * + * @param params Pointer to the instance configuration parameters. + */ +extern void SwiP_Params_init(SwiP_Params *params); + +/*! + * @brief Function to create a software interrupt object. + * + * @param swiFxn entry function of the software interrupt + * + * @param params Pointer to the instance configuration parameters. NULL + * denotes to use the default parameters. The SwiP default + * parameters are noted in ::SwiP_Params_init. + * + * @return A SwiP_Handle on success or a NULL on an error + */ +extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, SwiP_Params *params); + +/*! + * @brief Function to delete a software interrupt object + * + * @param handle returned from the SwiP_create call + * + */ +extern void SwiP_delete(SwiP_Handle handle); + +/*! + * @brief Function to disable software interrupts + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = SwiP_disable(); + * key2 = SwiP_disable(); + * SwiP_restore(key2); + * SwiP_restore(key1); + * @endcode + * + * @return A key that must be passed to SwiP_restore to re-enable interrupts. + */ +extern uintptr_t SwiP_disable(void); + +/*! + * @brief Function to get the trigger value of the currently running SwiP. + * + */ +extern uint32_t SwiP_getTrigger(void); + +/*! + * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask inverse value to be ANDed + */ +extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_dec(SwiP_Handle handle); + +/*! + * @brief Increment the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_inc(SwiP_Handle handle); + +/*! + * @brief Function to return a status based on whether it is in a + * software interrupt context. + * + * @return A status: indicating whether the function was called in a + * software interrupt routine (true) or not (false). + */ +extern bool SwiP_inISR(void); + +/*! + * @brief Or the mask with the SwiP's trigger value and post the SwiP. + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param mask value to be ORed + */ +extern void SwiP_or(SwiP_Handle handle, uint32_t mask); + +/*! + * @brief Unconditionally post a software interrupt. + * + * @param handle returned from the SwiP_create or SwiP_construct call + */ +extern void SwiP_post(SwiP_Handle handle); + +/*! + * @brief Function to restore software interrupts + * + * @param key return from SwiP_disable + */ +extern void SwiP_restore(uintptr_t key); + +/*! + * @brief Function to set the priority of a software interrupt + * + * @param handle returned from the SwiP_create or SwiP_construct call + * @param priority new priority + */ +extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_SwiP__include */ diff --git a/simplelink_lpf2/source/ti/drivers/dpl/SystemP.h b/simplelink_lpf2/source/ti/drivers/dpl/SystemP.h new file mode 100644 index 00000000..afb9f485 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/SystemP.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file SystemP.h + * + * @brief System module for the RTOS Porting Interface + * + * Basic system services. + * + * =========================================================================== + */ + +#ifndef ti_dpl_SystemP__include +#define ti_dpl_SystemP__include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern int SystemP_snprintf(char *buf, size_t n, const char *format, ...); +extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); + +/*! + * @brief Start command for the RTOS scheduler + * + * This function will never return. Call only once, from the application's + * main function. + */ +extern void SystemP_startScheduler(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/simplelink_lpf2/source/ti/drivers/dpl/TaskP.h b/simplelink_lpf2/source/ti/drivers/dpl/TaskP.h new file mode 100644 index 00000000..f4830d84 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/TaskP.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TaskP.h + * + * @brief Task module for the RTOS Porting Interface + * + * TaskP objects are RTOS threads backed by OS-specific thread or task objects. + * Task functions will run according to the rules of the underlying scheduler, + * with higher priority tasks executing first. + * + * Tasks require a stack and a control struct to operate, which can either be + * allocated statically with TaskP_construct or dynamically with TaskP_create. + * The stack should be large enough to contain at least your deepest call stack + * plus an interrupt frame. + * + * Task Functions: + * The void* argument will be NULL by default, but you can set a value using + * TaskP_Params. Task functions should never return, as the behaviour after a + * task has returned is implementation-dependent and TaskP does not provide a + * mechanism for OS-independent task deletion. See your OS documentation for + * details. + * ============================================================================ + */ + +#ifndef ti_dpl_TaskP__include +#define ti_dpl_TaskP__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Number of bytes greater than or equal to the size of any RTOS Task object. + * + * BIOS 6.x: 80 + * BIOS 7.x: 88 + * FreeRTOS: 104(llvm)/340(gcc) + */ +#if (defined(__ti_version__) && defined(__clang__)) || defined(__IAR_SYSTEMS_ICC__) + #define TaskP_STRUCT_SIZE (104) +#elif defined(__GNUC__) + #define TaskP_STRUCT_SIZE (340) +#endif + +/*! + * @brief Number of bytes for the default stack size of any RTOS Task object. + * + */ +#define TaskP_DEFAULT_STACK_SIZE (512) + +/*! + * @brief TaskP structure. + * + * Opaque structure that should be large enough to hold any of the RTOS specific TaskP objects. + */ +typedef union TaskP_Struct +{ + uint32_t dummy; /*!< Align object */ + uint8_t data[TaskP_STRUCT_SIZE]; +} TaskP_Struct; + +/*! + * @brief Enum returned from TaskP_getState(). + */ +typedef enum +{ + /*! This task is actively running */ + TaskP_State_RUNNING, + /*! The task is ready to run, but not currently running */ + TaskP_State_READY, + /*! The task is blocked */ + TaskP_State_BLOCKED, + /*! The task has been deleted */ + TaskP_State_DELETED, + /*! The task is inactive */ + TaskP_State_INACTIVE, + /*! The task is not found or in an otherwise invalid state */ + TaskP_State_INVALID +} TaskP_State; + +/*! + * @brief Opaque client reference to an instance of a TaskP + * + * A TaskP_Handle returned from create or construct represents that instance. + */ +typedef TaskP_Struct *TaskP_Handle; + +typedef struct +{ + /*! Task name. Default: NAME */ + char *name; + /*! Task function argument. Default: NULL */ + void *arg; + /*! Task priority. Higher values represent higher priorities. Default: 0 */ + int priority; + /*! Task stack size. Default: TaskP_DEFAULT_STACK_SIZE */ + size_t stackSize; + /*! @brief Task stack pointer. NULL should be used when calling TaskP_create. + * A pointer to a current stack should be passed for TaskP_construct. Default: NULL + */ + void *stack; +} TaskP_Params; + +/*! + * @brief Task function definition, passed to create and construct + * + * This function should never return. + */ +typedef void (*TaskP_Function)(void *); + +/*! + * @brief Create a TaskP, allocating memory on the heap. + * + * Creates a new TaskP and registers it with the OS scheduler. The task object + * and the entire stack will be allocated on the heap - make sure you have a + * sufficiently large heap. Stack allocation size is controlled by params. + * + * If the program is already executing a task and the new task has a higher + * priority the new task will be scheduled immediately; in this case + * TaskP_create() will not return until the new task blocks. To avoid this (for + * example when creating interdependent tasks at once) use + * TaskP_disableScheduler() and TaskP_restoreScheduler() to prevent the context + * switch. + * + * \note This API cannot be called from interrupt contexts. + * + * @retval TaskP handle (NULL on failure) + */ +extern TaskP_Handle TaskP_create(TaskP_Function fxn, const TaskP_Params *params); + +/*! + * @brief Delete a TaskP. + * + * Deletes a TaskP. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, INCLUDE_vTaskDelete has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + */ +extern void TaskP_delete(TaskP_Handle task); + +/*! + * @brief Construct a TaskP from statically allocated memory. + * + * TaskP_construct creates a new task object. TaskP_construct returns the handle + * of the new task object or NULL if the task could not be created. + * + * To use TaskP_construct you must set both point @c params.stack to a valid + * preallocated memory location of at least @c params.stackSize. + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS, configSUPPORT_STATIC_ALLOCATION has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @retval TaskP handle (NULL on failure) + */ +extern TaskP_Handle TaskP_construct(TaskP_Struct *obj, TaskP_Function fxn, const TaskP_Params *params); + +/*! + * @brief Destruct a TaskP. + * + * TaskP_destruct destructs a task object. + * + * \note This API cannot be called from interrupt contexts. + */ +extern void TaskP_destruct(TaskP_Struct *obj); + +/*! + * @brief Get the current state of a task handle. + * + * Returns the state of the referenced task at the time this function was + * called. The return value is not guaranteed to match the state of the task + * when the calling function tests the return value. For example, the referenced + * task might have unblocked as a result of an interrupt, but the value may + * still read TaskP_State_BLOCKED. + * + * The conversion of task states between DPL, FreeRTOS and TI-RTOS is: + * DPL: FreeRTOS: TI-RTOS: + * TaskP_State_RUNNING - eRunning - Task_Mode_RUNNING + * TaskP_State_READY - eReady - Task_Mode_READY + * TaskP_State_BLOCKED - eBlocked - Task_Mode_BLOCKED + * TaskP_State_DELETED - eDeleted - Task_Mode_TERMINATED + * TaskP_State_INACTIVE - eSuspended - Task_Mode_INACTIVE + * TaskP_State_INVALID - eInvalid - N.A + * + * For FreeRTOS, INCLUDE_eTaskGetState has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @retval Current state of the task pointed to by the task parameter + */ +extern TaskP_State TaskP_getState(TaskP_Handle task); + +/*! + * @brief Get the currently executing task handle. + * + * \note Must be called from task context. + * + * For FreeRTOS, INCLUDE_xTaskGetCurrentTaskHandle has to be set to 1 in FreeRTOSConfig.h. + * See 'Configuration with FreeRTOS' in the Core SDK User's Guide for how to do this. + * + * @retval The handle for the calling task + */ +extern TaskP_Handle TaskP_getCurrentTask(void); + +/*! + * @brief Function to disable task scheduling + * + * This function can be called multiple times, but must unwound in the reverse + * order. For example + * @code + * uintptr_t key1, key2; + * key1 = TaskP_disableScheduler(); + * key2 = TaskP_disableScheduler(); + * TaskP_restoreScheduler(key2); + * TaskP_restoreScheduler(key1); + * @endcode + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS the key value returned is always 0. + * + * @return A key to pass to TaskP_restoreScheduler to re-enable the scheduler. + */ +extern uintptr_t TaskP_disableScheduler(void); + +/*! + * @brief Function to re-enable task scheduling + * + * \note This API cannot be called from interrupt contexts. + * + * For FreeRTOS the key value is ignored. + * + * @param key returned from TaskP_disableScheduler + */ +extern void TaskP_restoreScheduler(uintptr_t key); + +/*! + * @brief Create a scheduler point, yielding to equal priority tasks. + * + * Task_yield yields the processor to another task of equal priority. A task + * switch occurs when you call Task_yield if there is an equal priority task + * ready to run. + */ +extern void TaskP_yield(void); + +/*! + * @brief Initialize params structure to default values. + * + * Initialize the parameter struct with default values. + * + * @param params pointer to the task parameter struct + * + */ +extern void TaskP_Params_init(TaskP_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_dpl_TaskP__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/dpl/TimestampP.h b/simplelink_lpf2/source/ti/drivers/dpl/TimestampP.h new file mode 100644 index 00000000..f668d8a1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/dpl/TimestampP.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file TimestampP.h + * + * @brief Timestamp module for the RTOS Porting Interface + * + * Utility functions to get device timestamp + * + * =========================================================================== + */ + +#ifndef ti_dpl_TimestampP__include +#define ti_dpl_TimestampP__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define TimestampP_Exponent_Seconds 0 +#define TimestampP_Exponent_Miliseconds 3 +#define TimestampP_Exponent_Microseconds 6 +#define TimestampP_Exponent_Nanoseconds 9 + +/* @brief Specification for parsing native device timestamp + * + * When provided with a native timestamp, however many bits, a peer device + * may perform the calculation: + * + * @code + * double fractional = (ts & ((1 << fracBytes*8) - 1)) / 2^fracBytes*8 + * double integral = (ts >> fracBytes*8) & ((1 << intBytes*8) - 1) + * // if multiplier > 0: + * double time = abs(multiplier) * (integral + fractional) * 10^-exponent + * // if multiplier < 0: + * double time = 1/abs(multiplier) * (integral + fractional) * 10^-exponent + * @endcode + * + * For example, if the native format is a 32-bit wide fixed point fractional + * value with 16 bits for seconds and subseconds, the setting would be: + * fracBytes = 2, intBytes = 2, multiplier = 1, exponent = 0 + * + * On the other hand if the native format is a 32-bit wide integral value + * where each tick is worth 8 microseconds, you get this: + * fracBytes = 0, intBytes = 4, multiplier = 8, exponent = 6 + * + * If the native format is a 48-bit wide 32786 Hz counter where each + * tick is worth 30.5175 etc us, the setting would be: + * fracBytes = 0, intBytes = 6, multiplier = -32768, exponent = 0 + * + * It is expected that if there is a fractional part, it is in the LSB end. + */ +typedef union TimestampP_Format +{ + struct + { + uint32_t fracBytes:4; // +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom.h) +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +/* Defines */ + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +/* Param length needs to be equal to the length of the largest curve supported plus length offset bytes */ +#define ECC_PARAM_LENGTH_WITH_OFFSET_BYTES (ECC_NISTP256_PARAM_LENGTH_BYTES + ECC_LENGTH_OFFSET_BYTES) + +/* Typedefs */ +typedef union +{ + uint32_t word[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES / sizeof(uint32_t)]; + uint8_t byte[ECC_PARAM_LENGTH_WITH_OFFSET_BYTES]; +} ECC_Param; + +/* Externs */ +extern uint8_t ECCSW_X25519_commonKey(ECC_State *state, + const uint32_t *ecdhCommonKey_inScal, + const uint32_t *ecdhCommonKey_inX, + uint32_t *ecdhCommonKey_outX); +/* + * ======== ECDHCC26X1_getKeyResult ======== + */ +static void ECDHCC26X1_getKeyResult(const ECC_Param *x, + const ECC_Param *y, + CryptoKey *key, + const ECCParams_CurveParams *curve, + ECDH_KeyMaterialEndianness keyMaterialEndianness) +{ + /* + * Reverse and copy the X and Y coordinates back to the CryptoKey buffer. + * Octet string format requires big-endian formatting of X and Y coordinates. + * Copy directly for little-endian key material. + */ + if (keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + CryptoUtils_reverseCopy(&x->word[1], key->u.plaintext.keyMaterial + OCTET_STRING_OFFSET, curve->length); + + if (curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + /* Y coordinate is not used. Zero it out. */ + memset(key->u.plaintext.keyMaterial + curve->length + OCTET_STRING_OFFSET, 0x00, curve->length); + } + else + { + CryptoUtils_reverseCopy(&y->word[1], + key->u.plaintext.keyMaterial + curve->length + OCTET_STRING_OFFSET, + curve->length); + } + /* Write the octet string format constant to the CryptoKey buffer */ + key->u.plaintext.keyMaterial[0] = 0x04; + } + else + { + memcpy(key->u.plaintext.keyMaterial, &x->word[1], curve->length); + + if (curve->curveType != ECCParams_CURVE_TYPE_MONTGOMERY) + { + memcpy(key->u.plaintext.keyMaterial + curve->length, &y->word[1], curve->length); + } + } + + /* Mark the CryptoKey as non-empty */ + key->encoding = CryptoKey_PLAINTEXT; +} + +/* + * ======== ECDHCC26X1_getKeyResultMontgomery ======== + */ +static void ECDHCC26X1_getKeyResultMontgomery(const ECC_Param *x, CryptoKey *key, size_t curveLength) +{ + /* Copy the X coordinate back to the CryptoKey buffer. No Y coordinate. + * Montgomery X-only public key format is little-endian. */ + memcpy(key->u.plaintext.keyMaterial, &x->word[1], curveLength); + + /* Mark the CryptoKey as non-empty */ + key->encoding = CryptoKey_PLAINTEXT; +} + +/* + * ======== ECDH_init ======== + */ +void ECDH_init(void) +{} + +/* + * ======== ECDH_Params_init ======== + */ +void ECDH_Params_init(ECDH_Params *params) +{ + *params = ECDH_defaultParams; +} + +/* + * ======== ECDH_construct ======== + */ +ECDH_Handle ECDH_construct(ECDH_Config *config, const ECDH_Params *params) +{ + ECDH_Handle handle; + ECDHCC26X1_Object *object; + uint_fast8_t key; + + handle = (ECDH_Handle)config; + object = handle->object; + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &ECDH_defaultParams; + } + + /* Since CC26X1 ECC is a pure SW implementation, callback mode is not supported */ + if (params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK) + { + return NULL; + } + + key = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + + return handle; +} + +/* + * ======== ECDH_close ======== + */ +void ECDH_close(ECDH_Handle handle) +{ + ECDHCC26X1_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== ECDHCC26X1_formatX25519PrivateKey ======== + */ +static void ECDHCC26X1_formatX25519PrivateKey(uint32_t *myPrivateKey, ECDH_KeyMaterialEndianness KeyMaterialEndianness) +{ + /* + * Per RFC7748: For X25519, in order to decode 32 random bytes as an integer scalar, + * set the three least significant bits of the first byte and the most significant bit + * of the last to zero, set the second most significant bit of the last byte to 1. + */ + + /* Clear bit 0, 1, and 2 */ + myPrivateKey[0] &= 0xFFFFFFF8UL; + /* Clear bit 255 */ + myPrivateKey[7] &= 0x7FFFFFFFUL; + /* Set bit 254 */ + myPrivateKey[7] |= 0x40000000UL; +} + +/* + * ======== ECDH_generatePublicKey ======== + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation) +{ + ECDHCC26X1_Object *object = handle->object; + int_fast16_t returnStatus = ECDH_STATUS_ERROR; + size_t curveLength = operation->curve->length; + uint8_t eccStatus; + + /* Allocate local copies of the private and public keys because + * the ECC in ROM implementation requires the word length to be prepended to + * every array input. + */ + ECC_Param privateKeyUnion; + ECC_Param publicKeyUnionX; + ECC_Param publicKeyUnionY; + + /* Prepend the word length - always 8 words for both P256 and Curve25519 */ + privateKeyUnion.word[0] = 0x08; + publicKeyUnionX.word[0] = 0x08; + publicKeyUnionY.word[0] = 0x08; + + /* Only NISTP256 and Curve25519 curves are supported. Both curves have 32-bytes length. */ + if (curveLength != ECC_NISTP256_PARAM_LENGTH_BYTES) + { + return ECDH_STATUS_ERROR; + } + + /* Validate private key length */ + if (operation->myPrivateKey->u.plaintext.keyLength != curveLength) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + + /* + * Validate public key sizes to ensure X-only public key format if using Montgomery curves + * with little endian key representation. Other cases use both coordinates with additional + * octet string offset byte when using big endian representation + */ + if (operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY) + { + /* X-only public key for Montgomery curves */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + if (operation->myPublicKey->u.plaintext.keyLength != curveLength) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + else /* Little-endian keys for other curves */ + { + if (operation->myPublicKey->u.plaintext.keyLength != 2 * curveLength) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + } + else /* Octet string format for any curve */ + { + if (operation->myPublicKey->u.plaintext.keyLength != (2 * curveLength + OCTET_STRING_OFFSET)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + + /* + * Since we are receiving the private key in octet string format, + * we need to convert them to little-endian form for use with the ECC in + * ROM functions. Length is 32-bytes for both NISTP256 and Curve25519. + * If the private key is already in little-endian form, skip this conversion + * and directly copy the key. + */ + if (operation->keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + CryptoUtils_reverseCopyPad(operation->myPrivateKey->u.plaintext.keyMaterial, + &privateKeyUnion.word[1], + curveLength); + } + else + { + CryptoUtils_copyPad(operation->myPrivateKey->u.plaintext.keyMaterial, &privateKeyUnion.word[1], curveLength); + } + + /* Assume Montgomery curve type is Curve25519 since ECC params for all other curves + * such as NIST are provided as Weierstrass type. + */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + ECDHCC26X1_formatX25519PrivateKey(&privateKeyUnion.word[1], operation->keyMaterialEndianness); + + ECCInitCC26X1_Curve25519(&(object->eccState), ECDH26X1_ECC_WINDOW_SIZE, object->eccWorkZone); + + eccStatus = ECCSW_X25519_commonKey(&(object->eccState), + privateKeyUnion.word, + ECC_Curve25519_generatorX.word, + publicKeyUnionX.word); + } + else /* Weierstrass curve type (assume NIST P256) */ + { + /* Initialize ECC state for NIST P256 with a window size of 3 */ + ECC_initialize(&(object->eccState), object->eccWorkZone); + + /* Check if private key in [1, n-1] */ + eccStatus = ECC_validatePrivateKey(&(object->eccState), privateKeyUnion.word); + + if (eccStatus == STATUS_PRIVATE_VALID) + { + eccStatus = ECC_generateKey(&(object->eccState), + privateKeyUnion.word, + privateKeyUnion.word, + publicKeyUnionX.word, + publicKeyUnionY.word); + } + } + + /* Check the ECC in ROM return code and set the driver status accordingly */ + if (eccStatus == STATUS_ECDH_KEYGEN_OK) + { + returnStatus = ECDH_STATUS_SUCCESS; + + if ((operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) && + (operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY)) + { + ECDHCC26X1_getKeyResultMontgomery(&publicKeyUnionX, operation->myPublicKey, curveLength); + } + else + { + ECDHCC26X1_getKeyResult(&publicKeyUnionX, + &publicKeyUnionY, + operation->myPublicKey, + operation->curve, + operation->keyMaterialEndianness); + } + } + + return returnStatus; +} + +/* + * ======== ECDH_computeSharedSecret ======== + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation) +{ + ECDHCC26X1_Object *object = handle->object; + int_fast16_t returnStatus = ECDH_STATUS_ERROR; + size_t curveLength = operation->curve->length; + uint8_t eccStatus; + + /* We need to allocate local copies of the private key, public key, and + * shared secret because the ECC in ROM implementation requires the word + * length to be prepended to every array input. + * The length word is prepended during initialisation here. + */ + ECC_Param privateKeyUnion; + ECC_Param publicKeyUnionX; + ECC_Param publicKeyUnionY; + ECC_Param sharedSecretUnionX; + ECC_Param sharedSecretUnionY; + + /* Prepend the word length - always 8 words for both P256 and Curve25519 */ + privateKeyUnion.word[0] = 0x08; + publicKeyUnionX.word[0] = 0x08; + publicKeyUnionY.word[0] = 0x08; + sharedSecretUnionX.word[0] = 0x08; + sharedSecretUnionY.word[0] = 0x08; + + /* Only NISTP256 and Curve25519 curves are supported. Both curves have 32-bytes length. */ + if (curveLength != ECC_NISTP256_PARAM_LENGTH_BYTES) + { + return ECDH_STATUS_ERROR; + } + + /* + * Validate public key sizes to ensure X-only public key format if using Montgomery curves + * with little endian key representation. Other cases use both coordinates with additional + * octet string offset byte when using big endian representation + */ + if (operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY) + { + /* X-only public key for Montgomery curves */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + if ((operation->myPrivateKey->u.plaintext.keyLength != curveLength) || + (operation->theirPublicKey->u.plaintext.keyLength != curveLength) || + (operation->sharedSecret->u.plaintext.keyLength != curveLength)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + else /* Little-endian keys for other curves */ + { + if ((operation->myPrivateKey->u.plaintext.keyLength != curveLength) || + (operation->theirPublicKey->u.plaintext.keyLength != 2 * curveLength) || + (operation->sharedSecret->u.plaintext.keyLength != 2 * curveLength)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + } + else /* Octet string format for any curve */ + { + if ((operation->myPrivateKey->u.plaintext.keyLength != curveLength) || + (operation->theirPublicKey->u.plaintext.keyLength != (2 * curveLength + OCTET_STRING_OFFSET)) || + (operation->theirPublicKey->u.plaintext.keyMaterial[0] != 0x04) || + (operation->sharedSecret->u.plaintext.keyLength != (2 * curveLength + OCTET_STRING_OFFSET))) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + + /* + * Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the ECC in + * ROM functions + * If the private key is already in little-endian form, skip this conversion + * and directly copy the key. + */ + if (operation->keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + CryptoUtils_reverseCopyPad(operation->myPrivateKey->u.plaintext.keyMaterial, + &privateKeyUnion.word[1], + curveLength); + + CryptoUtils_reverseCopyPad(operation->theirPublicKey->u.plaintext.keyMaterial + OCTET_STRING_OFFSET, + &publicKeyUnionX.word[1], + curveLength); + + CryptoUtils_reverseCopyPad(operation->theirPublicKey->u.plaintext.keyMaterial + curveLength + + OCTET_STRING_OFFSET, + &publicKeyUnionY.word[1], + curveLength); + } + else + { + CryptoUtils_copyPad(operation->myPrivateKey->u.plaintext.keyMaterial, &privateKeyUnion.word[1], curveLength); + + CryptoUtils_copyPad(operation->theirPublicKey->u.plaintext.keyMaterial, &publicKeyUnionX.word[1], curveLength); + + CryptoUtils_copyPad(operation->theirPublicKey->u.plaintext.keyMaterial + curveLength, + &publicKeyUnionY.word[1], + curveLength); + } + + /* Assume Montgomery curve type is Curve25519 since ECC params for all other curves + * such as NIST are provided as Weierstrass type. + */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + ECDHCC26X1_formatX25519PrivateKey(&privateKeyUnion.word[1], operation->keyMaterialEndianness); + + ECCInitCC26X1_Curve25519(&(object->eccState), ECDH26X1_ECC_WINDOW_SIZE, object->eccWorkZone); + + eccStatus = ECCSW_X25519_commonKey(&(object->eccState), + privateKeyUnion.word, + ECC_Curve25519_generatorX.word, + sharedSecretUnionX.word); + } + else /* Weierstrass curve type (assume NIST P256) */ + { + /* Initialize ECC state for NIST P256 with a window size of 3 */ + ECC_initialize(&(object->eccState), object->eccWorkZone); + + eccStatus = ECC_validatePublicKey(&(object->eccState), publicKeyUnionX.word, publicKeyUnionY.word); + + if (eccStatus == STATUS_ECC_POINT_ON_CURVE) + { + eccStatus = ECC_ECDH_computeSharedSecret(&(object->eccState), + privateKeyUnion.word, + publicKeyUnionX.word, + publicKeyUnionY.word, + sharedSecretUnionX.word, + sharedSecretUnionY.word); + } + } + + /* Check the ECC in ROM return code and set the driver status accordingly */ + if (eccStatus == STATUS_ECDH_COMMON_KEY_OK) + { + returnStatus = ECDH_STATUS_SUCCESS; + + if ((operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY) && + (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY)) + { + ECDHCC26X1_getKeyResultMontgomery(&sharedSecretUnionX, operation->sharedSecret, curveLength); + } + else + { + ECDHCC26X1_getKeyResult(&sharedSecretUnionX, + &sharedSecretUnionY, + operation->sharedSecret, + operation->curve, + operation->keyMaterialEndianness); + } + } + + return returnStatus; +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X1.h b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X1.h new file mode 100644 index 00000000..ec6f25ad --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X1.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2020-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDHCC26X1.h + * + * @brief ECDH driver implementation for the CC26X1 family + * + * This file should only be included in the board file to fill the ECDH_config + * struct. + * + * # Hardware and Implementation Details # + * + * # Supported Curves # + * + * The driver implementation supports the following curves for ECDH: + * + * | Curves Supported | + * |------------------| + * | NISTP256 | + * | Curve25519 | + * + */ + +#ifndef ti_drivers_ecdh_ECDHCC26X1__include +#define ti_drivers_ecdh_ECDHCC26X1__include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief ECDHCC26X1 Hardware Attributes + * + * ECC26XX hardware attributes should be included in the board file + * and pointed to by the ECDH_config struct. + */ +typedef struct +{ + uint8_t dummy; +} ECDHCC26X1_HWAttrs; + +/* + * Performance of the ECC SW library is scaled via the window size parameter + * which defines the number of bits of the scalar that will be processed together + * during the execution of the scalar multiplication. A larger window size + * will have higher performance at the cost of increased memory consumption. + * A window size of 3 was selected for the best trade-off of performance and + * memory consumption. + * + * --------------------------------------------------- + * | | NIST P256 | X25519 | + * | Window Size | WorkZone Size | WorkZone Size | + * | | (words) | (words) | + * |-------------|-----------------|-----------------| + * | 2 or 3 | 171 | 198 | + * | 4 | 225 | 225 | + * | 5 | 333 | 333 | + * --------------------------------------------------- + */ +#define ECDH26X1_ECC_WINDOW_SIZE 3 + +/* + * ECC Workzone size is based on worst case empirical measurement of ECDH + * operations on supported curves with the selected window size. + * NIST P256 (win_size=3): 171 words + * Curve25519 (win_size=3): 198 words + */ +#define ECDH26X1_ECC_WORKZONE_WORDS 198 + +/*! + * @brief ECDHCC26X1 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + ECDH_CallbackFxn callbackFxn; + ECDH_ReturnBehavior returnBehavior; /* Note: Callback return behavior is not supported */ + ECC_State eccState; + uint32_t eccWorkZone[ECDH26X1_ECC_WORKZONE_WORDS]; +} ECDHCC26X1_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdh_ECDHCC26X1__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.c b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.c new file mode 100644 index 00000000..e3ca29f5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.c @@ -0,0 +1,1200 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/aes.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif +#endif + +/* Forward declarations */ +static void ECDHCC26X2_hwiFxn(uintptr_t arg0); +#if (TFM_ENABLED == 0) +static void ECDHCC26X2_internalCallbackFxn(ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); +#endif +static int_fast16_t ECDHCC26X2_waitForAccess(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_waitForResult(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_runFSM(ECDH_Handle handle); +static int_fast16_t ECDHCC26X2_convertReturnValue(int32_t pkaResult); + +/* Static globals */ +static bool isInitialized = false; +static uint32_t resultPKAMemAddr; + +#if (ENABLE_KEY_STORAGE == 1) + /* + * Max key sizes 521b private keys, + * ( 521b) * 2 + 1B for octet offset for public keys + */ + #define ECDH_MAX_KEYSTORE_PUBLIC_KEY_SIZE 133 + #define ECDH_MAX_KEYSTORE_PRIVATE_KEY_SIZE 66 +#endif + +/* Defines */ + +/* We need several scratch buffers as the private and public keys are provided + * in octet string form and thus the components are big-endian. We need to feed + * the PKA with little-endian integers. That means moving them to some scratch + * memory and reversing them. The only exception is X25519 that can either be + * sent in octet string form or x-only little-endian form. + * We are storing them in bytes 512 to 512 + 3 x SCRATCH_BUFFER_SIZE. + * Byte 1024 to 1024 + 66 and 1536 to 1536 + 66 are used by the public key + * validation routine in driverlib. + */ +#define SCRATCH_BUFFER_OFFSET 512 +#define SCRATCH_BUFFER_SIZE 96 + +#define SCRATCH_PRIVATE_KEY ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET)) +#define SCRATCH_PUBLIC_X ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + SCRATCH_BUFFER_SIZE)) +#define SCRATCH_PUBLIC_Y ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 2 * SCRATCH_BUFFER_SIZE)) + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +#if (TFM_ENABLED == 0) +/* + * ======== ECDHCC26X2_internalCallbackFxn ======== + */ +static void ECDHCC26X2_internalCallbackFxn(ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType) +{ + ECDHCC26X2_Object *object = handle->object; + + /* + * This function is only registered when in ECDH_RETURN_BEHAVIOR_BLOCKING + * or ECDH_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else + { + PKAResourceCC26XX_pollingFlag = 1; + } +} +#endif + +#if (ENABLE_KEY_STORAGE == 1) + +/* + * ======== ECDHCC26X2_importSecureKey ======== + */ +static int_fast16_t ECDHCC26X2_importSecureKey(CryptoKey *key, uint8_t *keyingMaterial) +{ + KeyStore_PSA_KeyFileId keyID; + int_fast16_t status; + int_fast16_t pkaResult = ECDH_STATUS_KEYSTORE_ERROR; + KeyStore_PSA_KeyAttributes *attributesPtr; + #if (TFM_ENABLED == 1) + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + #endif + + /* Copy key identifier from CryptoKey */ + GET_KEY_ID(keyID, key->u.keyStore.keyID); + + #if (TFM_ENABLED == 0) + attributesPtr = (KeyStore_PSA_KeyAttributes *)key->u.keyStore.keyAttributes; + #else + attributesPtr = &attributes; + status = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)key->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #endif + status = KeyStore_PSA_importKey(attributesPtr, keyingMaterial, key->u.keyStore.keyLength, &keyID); + + if (status == KEYSTORE_PSA_STATUS_SUCCESS) + { + KeyStore_PSA_initKey(key, keyID, key->u.keyStore.keyLength, attributesPtr); + pkaResult = ECDH_STATUS_SUCCESS; + } + + return pkaResult; +} +#endif + +/* + * ======== ECDHCC26X2_getKeyResult ======== + */ +static int_fast16_t ECDHCC26X2_getKeyResult(CryptoKey *key, + const ECCParams_CurveParams *curve, + ECDH_KeyMaterialEndianness keyMaterialEndianness, + ECDH_OperationType opType) +{ + uint32_t pkaResult; + int_fast16_t status = ECDH_STATUS_ERROR; + uint8_t *keyMaterial; + uint8_t *xCoordinate; + uint8_t *yCoordinate; + size_t keyLength; + size_t bytesToBeWritten; +#if (ENABLE_KEY_STORAGE == 1) + uint8_t KeyStore_keyingMaterial[ECDH_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif + + /* Keep track of number of bytes of key written using driverlib function and check if it does not exceed the length + * of the keyMaterial provided in CryptoKey + */ + bytesToBeWritten = 0; + + /* Initialize the coordinates to NULL */ + xCoordinate = NULL; + yCoordinate = NULL; + + /* + * Support for both Plaintext and KeyStore keys for myPrivateKey + */ + if (key->encoding == CryptoKey_BLANK_PLAINTEXT) + { + keyMaterial = key->u.plaintext.keyMaterial; + keyLength = key->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (key->encoding == CryptoKey_BLANK_KEYSTORE) + { + keyMaterial = KeyStore_keyingMaterial; + keyLength = key->u.keyStore.keyLength; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + if (keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + /* + * Set first byte of output public key to 0x04 to indicate x,y + * big-endian coordinates in octet string format + */ + bytesToBeWritten = OCTET_STRING_OFFSET; + keyMaterial[0] = 0x04; + + /* Get X and Y coordinates with OCTET_STRING_OFFSET for big-endian keys */ + bytesToBeWritten += 2 * curve->length; + if (bytesToBeWritten == keyLength) + { + xCoordinate = keyMaterial + OCTET_STRING_OFFSET; + yCoordinate = keyMaterial + curve->length + OCTET_STRING_OFFSET; + + pkaResult = PKAEccMultiplyGetResult(xCoordinate, yCoordinate, resultPKAMemAddr, curve->length); + + /* Byte-reverse integer X coordinate for octet string format */ + CryptoUtils_reverseBufferBytewise(xCoordinate, curve->length); + + if (curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + /* Zero-out the Y coordinate as it not required for Montgomery curves */ + memset(yCoordinate, 0x00, curve->length); + } + else + { + /* Byte-reverse integer Y coordinate for octet string format */ + CryptoUtils_reverseBufferBytewise(yCoordinate, curve->length); + } + + status = ECDH_STATUS_SUCCESS; + } + } + else + { + if (curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + /* Y coordinate is not required for Montgomery curves */ + bytesToBeWritten = curve->length; + if (bytesToBeWritten == keyLength) + { + xCoordinate = keyMaterial; + + pkaResult = PKAEccMultiplyGetResult(xCoordinate, yCoordinate, resultPKAMemAddr, curve->length); + + status = ECDH_STATUS_SUCCESS; + } + } + else + { + /* + * Get X and Y coordinates without byte-reverse and + * without OCTET_STRING_OFFSET for Weierstrass curves + */ + bytesToBeWritten = 2 * curve->length; + if (bytesToBeWritten == keyLength) + { + xCoordinate = keyMaterial; + yCoordinate = keyMaterial + curve->length; + + pkaResult = PKAEccMultiplyGetResult(xCoordinate, yCoordinate, resultPKAMemAddr, curve->length); + + status = ECDH_STATUS_SUCCESS; + } + } + } + + if (status == ECDH_STATUS_SUCCESS) + { + status = ECDHCC26X2_convertReturnValue(pkaResult); + +#if (ENABLE_KEY_STORAGE == 1) + if ((status == ECDHCC26X2_STATUS_FSM_RUN_FSM) && (key->encoding == CryptoKey_BLANK_KEYSTORE)) + { + status = ECDHCC26X2_importSecureKey(key, KeyStore_keyingMaterial); + } +#endif + } + + return status; +} + +/* + * ======== ECDHCC26X2_formatCurve25519PrivateKeyScratch ======== + */ +static void ECDHCC26X2_formatCurve25519PrivateKeyScratch(uint32_t *myPrivateKey) +{ + /* + * As per RFC 7748, the private key of Curve25519 is pruned so that + * the three LSB's are cleared, bit 255 is cleared, and bit 254 is + * set. + */ + /* Clear bit 0, 1, and 2 */ + myPrivateKey[0] &= 0xFFFFFFF8UL; + /* Clear bit 255 */ + myPrivateKey[7] &= 0x7FFFFFFFUL; + /* Set bit 254 */ + myPrivateKey[7] |= 0x40000000UL; +} + +/* + * ======== ECDHCC26X2_hwiFxn ======== + */ +static void ECDHCC26X2_hwiFxn(uintptr_t arg0) +{ + ECDHCC26X2_Object *object = ((ECDH_Handle)arg0)->object; + int_fast16_t operationStatus; + ECDH_Operation operation; + ECDH_OperationType operationType; + uint32_t key; + + /* Disable interrupt again. It may be reenabled in the FSM function. */ + IntDisable(INT_PKA_IRQ); + + /* Execute next states */ + do + { + object->operationStatus = ECDHCC26X2_runFSM((ECDH_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECDHCC26X2_STATUS_FSM_RUN_FSM); + + /* + * We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if (object->operationCanceled) + { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECDH_STATUS_CANCELED; + } + + switch (object->operationStatus) + { + case ECDHCC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA or TRNG hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECDH_STATUS_SUCCESS: + /* Intentional fall through */ + case ECDH_STATUS_ERROR: + /* Intentional fall through */ + case ECDH_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Save all inputs to the callbackFxn on the stack + * in case a higher priority hwi comes in and + * starts a new operation after we have released the + * access semaphore. + */ + operationStatus = object->operationStatus; + operation = object->operation; + operationType = object->operationType; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. This does have the drawback that another hwi + * can come in and start an operation before the original + * on finished completely. This should be prevented by + * customers only starting operations with the same + * handle from a single context and waiting for + * the callback of the original operation to + * be executed in callback return mode. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + object->callbackFxn((ECDH_Handle)arg0, operationStatus, operation, operationType); + } +} + +/* + * ======== ECDHCC26X2_runFSM ======== + */ +static int_fast16_t ECDHCC26X2_runFSM(ECDH_Handle handle) +{ + ECDHCC26X2_Object *object = handle->object; + int_fast16_t status; + uint32_t pkaResult; + + switch (object->fsmState) + { + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR: + /* + * Complete the verification that private key is in the interval + * [1, n - 1] by verifying that the private key is less than the order of + * the curve. + */ + PKABigNumCmpStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generatePublicKey->curve->order, + object->operation.generatePublicKey->curve->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + return ECDH_STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER; + } + + /* Perform an elliptic curve multiplication on a short Weierstrass curve */ + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generatePublicKey->curve->generatorX, + object->operation.generatePublicKey->curve->generatorY, + object->operation.generatePublicKey->curve->prime, + object->operation.generatePublicKey->curve->a, + object->operation.generatePublicKey->curve->b, + object->operation.generatePublicKey->curve->length, + &resultPKAMemAddr); + break; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT: + + status = ECDHCC26X2_getKeyResult(object->operation.generatePublicKey->myPublicKey, + object->operation.generatePublicKey->curve, + object->operation.generatePublicKey->keyMaterialEndianness, + ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY); + + return status; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_MONTGOMERY: + + /* + * As per RFC 7748, the private key of Curve25519 is pruned so that + * the three LSB's are cleared, bit 255 is cleared, and bit 254 is + * set. + */ + if (object->operation.generatePublicKey->curve->length == ECCParams_CURVE25519_LENGTH) + { + ECDHCC26X2_formatCurve25519PrivateKeyScratch(SCRATCH_PRIVATE_KEY); + } + + /* Perform an elliptic curve multiplication on a Montgomery curve. Likely Curve25519. */ + PKAEccMontgomeryMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generatePublicKey->curve->generatorX, + object->operation.generatePublicKey->curve->prime, + object->operation.generatePublicKey->curve->a, + object->operation.generatePublicKey->curve->length, + &resultPKAMemAddr); + + break; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT_MONTGOMERY: + status = ECDHCC26X2_getKeyResult(object->operation.generatePublicKey->myPublicKey, + object->operation.generatePublicKey->curve, + object->operation.generatePublicKey->keyMaterialEndianness, + ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY); + + return status; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY: + /* If we are using a short Weierstrass curve, we need to validate the public key */ + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart((uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->order, + object->operation.computeSharedSecret->curve->length); + + if (pkaResult != PKA_STATUS_SUCCESS) + { + return ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + } + + /* Perform an elliptic curve multiplication on a short Weierstrass curve */ + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultPKAMemAddr); + + break; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT: + + status = ECDHCC26X2_getKeyResult(object->operation.computeSharedSecret->sharedSecret, + object->operation.computeSharedSecret->curve, + object->operation.computeSharedSecret->keyMaterialEndianness, + ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET); + + return status; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY: + + /* + * As per RFC 7748, Curve25519 will mask the most significant bit + * of the final byte for received u-coordinates. The curve length + * of the Montgomery curve is used as an identifier here. + * + * Furthermore, the private key of Curve25519 is pruned so that + * the three LSB's are cleared, bit 255 is cleared, and bit 254 is + * set. + */ + if (object->operation.computeSharedSecret->curve->length == ECCParams_CURVE25519_LENGTH) + { + /* Since PKA RAM can only be accessed by word, compute the most + * significant word of the received Curve25519 public key and + * mask its MSB. + */ + uint32_t *curve25519PubKeyWord = SCRATCH_PUBLIC_X; + curve25519PubKeyWord[(ECCParams_CURVE25519_LENGTH / sizeof(uint32_t)) - 1U] &= 0x7FFFFFFF; + + /* Prune the private key */ + ECDHCC26X2_formatCurve25519PrivateKeyScratch(SCRATCH_PRIVATE_KEY); + } + + /* Perform an elliptic curve multiplication on a Montgomery curve. Likely Curve25519. */ + PKAEccMontgomeryMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->length, + &resultPKAMemAddr); + + break; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT_MONTGOMERY: + status = ECDHCC26X2_getKeyResult(object->operation.computeSharedSecret->sharedSecret, + object->operation.computeSharedSecret->curve, + object->operation.computeSharedSecret->keyMaterialEndianness, + ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET); + + return status; + + case ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN: + case ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN_MONTGOMERY: + /* Mark the public key CryptoKey as non-empty */ + if (object->operation.generatePublicKey->myPublicKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + object->operation.generatePublicKey->myPublicKey->encoding = CryptoKey_PLAINTEXT; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->operation.generatePublicKey->myPublicKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + object->operation.generatePublicKey->myPublicKey->encoding = CryptoKey_KEYSTORE; + } +#endif + return ECDH_STATUS_SUCCESS; + + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN: + case ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN_MONTGOMERY: + /* Mark the shared secret key CryptoKey as non-empty */ + if (object->operation.computeSharedSecret->sharedSecret->encoding == CryptoKey_BLANK_PLAINTEXT) + { + object->operation.computeSharedSecret->sharedSecret->encoding = CryptoKey_PLAINTEXT; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->operation.computeSharedSecret->sharedSecret->encoding == CryptoKey_BLANK_KEYSTORE) + { + object->operation.computeSharedSecret->sharedSecret->encoding = CryptoKey_KEYSTORE; + } +#endif + return ECDH_STATUS_SUCCESS; + + default: + return ECDH_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDHCC26X2_convertReturnValue ======== + */ +static int_fast16_t ECDHCC26X2_convertReturnValue(int32_t pkaResult) +{ + switch (pkaResult) + { + case PKA_STATUS_SUCCESS: + /* A less than B only comes up when checking private + * key values. It indicates a key within the correct range. + */ + return ECDHCC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that can yield the + * point at infinity. + */ + return ECDH_STATUS_PRIVATE_KEY_ZERO; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + return ECDH_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + return ECDH_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + case PKA_STATUS_POINT_AT_INFINITY: + return ECDH_STATUS_POINT_AT_INFINITY; + + default: + return ECDH_STATUS_ERROR; + } +} + +/* + * ======== ECDH_init ======== + */ +void ECDH_init(void) +{ + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== ECDH_Params_init ======== + */ +void ECDH_Params_init(ECDH_Params *params) +{ + *params = ECDH_defaultParams; +} + +/* + * ======== ECDH_construct ======== + */ +ECDH_Handle ECDH_construct(ECDH_Config *config, const ECDH_Params *params) +{ + ECDH_Handle handle; + ECDHCC26X2_Object *object; + uint_fast8_t key; + + handle = (ECDH_Handle)config; + object = handle->object; + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + // If params are NULL, use defaults + if (params == NULL) + { + params = (ECDH_Params *)&ECDH_defaultParams; + } + + DebugP_assert((params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; +#if (TFM_ENABLED == 1) + /* Always use the secure callback function */ + object->callbackFxn = params->callbackFxn; +#else + object->callbackFxn = (params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn + : ECDHCC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; +#endif + + // Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECDH_close ======== + */ +void ECDH_close(ECDH_Handle handle) +{ + ECDHCC26X2_Object *object; + + DebugP_assert(handle); + + // Get the pointer to the object + object = handle->object; + + // Mark the module as available + object->isOpen = false; + + // Release power dependency on PKA Module. + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== ECDHCC26X2_waitForAccess ======== + */ +static int_fast16_t ECDHCC26X2_waitForAccess(ECDH_Handle handle) +{ + ECDHCC26X2_Object *object = handle->object; + uint32_t timeout; + + // Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context + timeout = object->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECDHCC26X2_waitForResult ======== + */ +static int_fast16_t ECDHCC26X2_waitForResult(ECDH_Handle handle) +{ + ECDHCC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) + { + case ECDH_RETURN_BEHAVIOR_POLLING: + while (!PKAResourceCC26XX_pollingFlag) {} + return object->operationStatus; + + case ECDH_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + + case ECDH_RETURN_BEHAVIOR_CALLBACK: + return ECDH_STATUS_SUCCESS; + + default: + return ECDH_STATUS_ERROR; + } +} + +/* + * ======== ECDH_generatePublicKey ======== + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation) +{ + ECDHCC26X2_Object *object = handle->object; + ECDHCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + uint8_t *myPrivateKeyMaterial; + size_t myPrivateKeyLength; + size_t myPublicKeyLength; + + /* + * Support for both Plaintext and KeyStore keys for myPrivateKey and + * myPublicKey. + */ + if (operation->myPrivateKey->encoding == CryptoKey_PLAINTEXT) + { + myPrivateKeyMaterial = operation->myPrivateKey->u.plaintext.keyMaterial; + myPrivateKeyLength = operation->myPrivateKey->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (operation->myPrivateKey->encoding == CryptoKey_KEYSTORE) + { + int_fast16_t status; + KeyStore_PSA_KeyFileId keyID; + uint8_t KeyStore_myPrivateKeyMaterial[ECDH_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; + + GET_KEY_ID(keyID, operation->myPrivateKey->u.keyStore.keyID); + + status = KeyStore_PSA_getKey(keyID, + KeyStore_myPrivateKeyMaterial, + sizeof(KeyStore_myPrivateKeyMaterial), + &myPrivateKeyLength, + KEYSTORE_PSA_ALG_ECDH, + KEYSTORE_PSA_KEY_USAGE_DECRYPT); + if ((status != KEYSTORE_PSA_STATUS_SUCCESS) || + (myPrivateKeyLength != operation->myPrivateKey->u.keyStore.keyLength)) + { + return ECDH_STATUS_KEYSTORE_ERROR; + } + + myPrivateKeyMaterial = KeyStore_myPrivateKeyMaterial; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + if (operation->myPublicKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + myPublicKeyLength = operation->myPublicKey->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (operation->myPublicKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + myPublicKeyLength = operation->myPublicKey->u.keyStore.keyLength; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + /* + * Validate public key sizes to ensure X-only public key format if using Montgomery curves + * with little endian key representation. Other cases use both coordinates with additional + * octet string format byte when using big endian representation + */ + if (operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY) + { + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + /* X-only public key for Montgomery curves */ + if ((myPrivateKeyLength != operation->curve->length) || (myPublicKeyLength != operation->curve->length)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + else /* Little-endian keys for other curves */ + { + if ((myPrivateKeyLength != operation->curve->length) || (myPublicKeyLength != 2 * operation->curve->length)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + } + else /* Validate key sizes to make sure octet string format is used */ + { + if ((myPrivateKeyLength != operation->curve->length) || + (myPublicKeyLength != 2 * operation->curve->length + OCTET_STRING_OFFSET)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + + /* + * We must verify that the private key is in the interval [1, n -1]. Here we + * will check that the private key is non-zero for the lower bound. Later we + * will check that the private key is less than the order of the curve + * within the FSM since that requires a PKA HW operation. + */ + if (PKAArrayAllZeros(myPrivateKeyMaterial, operation->curve->length)) + { + return ECDH_STATUS_PRIVATE_KEY_ZERO; + } + + if (ECDHCC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + /* + * Since we are receiving the private keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + * If the private key is already in little-endian form, skip this conversion + * and directly copy the key. + */ + if (operation->keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + CryptoUtils_reverseCopyPad(myPrivateKeyMaterial, SCRATCH_PRIVATE_KEY, operation->curve->length); + } + else + { + CryptoUtils_copyPad(myPrivateKeyMaterial, SCRATCH_PRIVATE_KEY, operation->curve->length); + } + + /* + * Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operationStatus = ECDHCC26X2_STATUS_FSM_RUN_FSM; + object->operation.generatePublicKey = operation; + object->operationType = ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY; + object->operationCanceled = false; + + /* Use the correct state chain for the curve type */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3) + { + object->fsmState = ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR; + } + else + { + object->fsmState = ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_MONTGOMERY; + } + + /* + * We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDHCC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Start running FSM to generate public key. The PKA interrupt is level triggered and + * will run immediately once enabled + */ + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_waitForResult(handle); +} + +/* + * ======== ECDH_computeSharedSecret ======== + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation) +{ + ECDHCC26X2_Object *object = handle->object; + ECDHCC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + uint8_t *myPrivateKeyMaterial; + size_t myPrivateKeyLength; + uint8_t *theirPublicKeyMaterial; + size_t theirPublicKeyLength; + size_t sharedSecretKeyLength; +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t status; + KeyStore_PSA_KeyFileId keyID; + uint8_t KeyStore_myPrivateKeyMaterial[ECDH_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; + uint8_t KeyStore_theirPublicKeyMaterial[ECDH_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif + + /* + * Support for both Plaintext and KeyStore keys for myPrivateKey, + * theirPublicKey and shareSecret + */ + if (operation->myPrivateKey->encoding == CryptoKey_PLAINTEXT) + { + myPrivateKeyMaterial = operation->myPrivateKey->u.plaintext.keyMaterial; + myPrivateKeyLength = operation->myPrivateKey->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (operation->myPrivateKey->encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, operation->myPrivateKey->u.keyStore.keyID); + + status = KeyStore_PSA_getKey(keyID, + KeyStore_myPrivateKeyMaterial, + sizeof(KeyStore_myPrivateKeyMaterial), + &myPrivateKeyLength, + KEYSTORE_PSA_ALG_ECDH, + KEYSTORE_PSA_KEY_USAGE_DECRYPT); + + if ((status != KEYSTORE_PSA_STATUS_SUCCESS) || + (myPrivateKeyLength != operation->myPrivateKey->u.keyStore.keyLength)) + { + return ECDH_STATUS_KEYSTORE_ERROR; + } + + myPrivateKeyMaterial = KeyStore_myPrivateKeyMaterial; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + if (operation->theirPublicKey->encoding == CryptoKey_PLAINTEXT) + { + theirPublicKeyMaterial = operation->theirPublicKey->u.plaintext.keyMaterial; + theirPublicKeyLength = operation->theirPublicKey->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (operation->theirPublicKey->encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, operation->theirPublicKey->u.keyStore.keyID); + + status = KeyStore_PSA_getKey(keyID, + KeyStore_theirPublicKeyMaterial, + sizeof(KeyStore_theirPublicKeyMaterial), + &theirPublicKeyLength, + KEYSTORE_PSA_ALG_ECDH, + KEYSTORE_PSA_KEY_USAGE_ENCRYPT | KEYSTORE_PSA_KEY_USAGE_EXPORT); + + if (status != KEYSTORE_PSA_STATUS_SUCCESS) + { + return ECDH_STATUS_KEYSTORE_ERROR; + } + + if (theirPublicKeyLength != operation->theirPublicKey->u.keyStore.keyLength) + { + return ECDH_STATUS_KEYSTORE_ERROR; + } + + theirPublicKeyMaterial = KeyStore_theirPublicKeyMaterial; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + if (operation->sharedSecret->encoding == CryptoKey_BLANK_PLAINTEXT) + { + sharedSecretKeyLength = operation->sharedSecret->u.plaintext.keyLength; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (operation->sharedSecret->encoding == CryptoKey_BLANK_KEYSTORE) + { + sharedSecretKeyLength = operation->sharedSecret->u.keyStore.keyLength; + } +#endif + else + { + return ECDH_STATUS_ERROR; + } + + /* + * Validate public key sizes to ensure X-only public key format if using Montgomery curves + * with little endian key representation. Other cases use both coordinates with additional + * octet string offset byte when using big endian representation + */ + if (operation->keyMaterialEndianness == ECDH_LITTLE_ENDIAN_KEY) + { + /* X-only public key for Montgomery curves */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_MONTGOMERY) + { + if ((myPrivateKeyLength != operation->curve->length) || + (theirPublicKeyLength != operation->curve->length) || + (sharedSecretKeyLength != operation->curve->length)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + else /* Little-endian keys for other curves */ + { + if ((myPrivateKeyLength != operation->curve->length) || + (theirPublicKeyLength != 2 * operation->curve->length) || + (sharedSecretKeyLength != 2 * operation->curve->length)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + } + else /* Validate key sizes to make sure octet string format is used for short Weierstrass curves */ + { + if ((myPrivateKeyLength != operation->curve->length) || + (theirPublicKeyLength != 2 * operation->curve->length + OCTET_STRING_OFFSET) || + (theirPublicKeyMaterial[0] != 0x04) || + (sharedSecretKeyLength != 2 * operation->curve->length + OCTET_STRING_OFFSET)) + { + return ECDH_STATUS_INVALID_KEY_SIZE; + } + } + + if (ECDHCC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + /* + * Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operationStatus = ECDHCC26X2_STATUS_FSM_RUN_FSM; + object->operation.computeSharedSecret = operation; + object->operationType = ECDH_OPERATION_TYPE_COMPUTE_SHARED_SECRET; + object->operationCanceled = false; + + /* + * Convert keys in octet string format to little-endian form for use with the PKA + * If the keys is already in little-endian form, skip this conversion + * and directly copy the key. + */ + if (operation->keyMaterialEndianness == ECDH_BIG_ENDIAN_KEY) + { + CryptoUtils_reverseCopyPad(myPrivateKeyMaterial, SCRATCH_PRIVATE_KEY, operation->curve->length); + + CryptoUtils_reverseCopyPad(theirPublicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + operation->curve->length); + + CryptoUtils_reverseCopyPad(theirPublicKeyMaterial + OCTET_STRING_OFFSET + operation->curve->length, + SCRATCH_PUBLIC_Y, + operation->curve->length); + } + else + { + CryptoUtils_copyPad(myPrivateKeyMaterial, SCRATCH_PRIVATE_KEY, operation->curve->length); + + CryptoUtils_copyPad(theirPublicKeyMaterial, SCRATCH_PUBLIC_X, operation->curve->length); + + /* Montgomery curves in Little-Endian have X-only public keys */ + if (operation->curve->curveType != ECCParams_CURVE_TYPE_MONTGOMERY) + { + CryptoUtils_copyPad(theirPublicKeyMaterial + operation->curve->length, + SCRATCH_PUBLIC_Y, + operation->curve->length); + } + } + + /* Use the correct state chain for the curve type */ + if (operation->curve->curveType == ECCParams_CURVE_TYPE_SHORT_WEIERSTRASS_AN3) + { + object->fsmState = ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY; + } + else + { + object->fsmState = ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY; + } + + /* + * We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDHCC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Start running FSM to generate PMSN. The PKA interrupt is level triggered and + * will run imediately once enabled + */ + IntEnable(INT_PKA_IRQ); + + return ECDHCC26X2_waitForResult(handle); +} + +/* + * ======== ECDH_cancelOperation ======== + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle) +{ + ECDHCC26X2_Object *object = handle->object; + + if (!object->operationInProgress) + { + return ECDH_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + return ECDH_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.h b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.h new file mode 100644 index 00000000..31c5bac0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X2.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2017-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDHCC26X2.h + * + * @brief ECDH driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the ECDH_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECDH: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | Yes | + * | Edwards | No | + * + * # Curve25519 Private Keys # + * + * When using Montgomery Curve25519, the private key must be formatted according to cr.yp.to/ecdh.html + * by the application before passing it to the driver. The driver cannot do so itself as the memory + * location of the keying material may be in flash. + * + * For keying material uint8_t myPrivateKey[32], you must do the following: + * @code + * myPrivateKey[0] &= 0xF8; + * myPrivateKey[31] &= 0x7F; + * myPrivateKey[31] |= 0x40; + * @endcode + * + * Alternatively, you can call ECCParams_FormatCurve25519PrivateKey() in ti/drivers/cryptoutils/ecc/ECCParams.h + * + * # Public Key Validation # + * + * When performing shared secret generation, the foreign public key will always be validated + * when using short Weierstrass curves. The only explicitly supported Montgomery curve is + * Curve25519 which does not require public key validation. + * The implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecdh_ECDHCC26X2__include +#define ti_drivers_ecdh_ECDHCC26X2__include + +#include +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/pka.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECDHCC26X2_STATUS_FSM_RUN_PKA_OP ECDH_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECDHCC26X2_STATUS_FSM_RUN_FSM ECDH_STATUS_RESERVED - 1 + +/*! + * @brief ECDHCC26X2 states + * + * The ECDH operations are implemented using multiple individual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum +{ + ECDHCC26X2_FSM_ERROR = 0, + + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT, + ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN, + + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_MONTGOMERY, + ECDHCC26X2_FSM_GEN_PUB_KEY_MULT_PRIVATE_KEY_BY_GENERATOR_RESULT_MONTGOMERY, + ECDHCC26X2_FSM_GEN_PUB_KEY_RETURN_MONTGOMERY, + + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN, + + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_MONTGOMERY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_MULT_PRIVATE_KEY_BY_PUB_KEY_RESULT_MONTGOMERY, + ECDHCC26X2_FSM_COMPUTE_SHARED_SECRET_RETURN_MONTGOMERY, +} ECDHCC26X2_FsmState; + +/*! + * @brief ECDHCC26X2 Hardware Attributes + * + * ECC26XX hardware attributes should be included in the board file + * and pointed to by the ECDH_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} ECDHCC26X2_HWAttrs; + +/*! + * @brief ECDHCC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDH_CallbackFxn callbackFxn; + ECDH_ReturnBehavior returnBehavior; + ECDH_Operation operation; + ECDH_OperationType operationType; + ECDHCC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; +} ECDHCC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdh_ECDHCC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.c new file mode 100644 index 00000000..fc50df1b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static volatile bool ECDHCC26X4_ns_pollingDone; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern ECDH_s_SecureCallback ecdhSecureCB_ns[]; +extern ECDHCC26X4_ns_Object ecdhObject_ns[]; + +/* + * ======== ECDH_ns_callbackFxn ======== + */ +void ECDH_ns_callbackFxn(uintptr_t arg) +{ + ECDH_s_SecureCallback *secureCallbackObject = (ECDH_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + CryptoPSACC26X4_releaseLock(); + + if (ecdhObject_ns[index].returnBehavior == ECDH_RETURN_BEHAVIOR_POLLING) + { + ECDHCC26X4_ns_pollingDone = true; + } + else if (ecdhObject_ns[index].returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + ecdhObject_ns[index].callbackFxn(ecdhSecureCB_ns[index].handle, + ecdhSecureCB_ns[index].returnStatus, + ecdhSecureCB_ns[index].operation, + ecdhSecureCB_ns[index].operationType); + } +} + +/* + * ======== ECDH_ns_registerCallback ======== + */ +static psa_status_t ECDH_ns_registerCallback(ECDH_Handle handle, const ECDH_Params *params) +{ + ECDH_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&ecdhSecureCB_ns[index].object, ECDH_ns_callbackFxn, (uintptr_t)&ecdhSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &ecdhSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== ECDH_ns_waitForResult ======== + */ +static void ECDH_ns_waitForResult(int_fast16_t *result, uint8_t objectIndex) +{ + if (*result != ECDH_STATUS_SUCCESS) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (ecdhObject_ns[objectIndex].returnBehavior == ECDH_RETURN_BEHAVIOR_POLLING) + { + /* + * Emulate polling mode by spinning on a flag which will be set by + * the callback function + */ + while (!ECDHCC26X4_ns_pollingDone) {} + *result = ecdhSecureCB_ns[objectIndex].returnStatus; + } + else if (ecdhObject_ns[objectIndex].returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + *result = ecdhSecureCB_ns[objectIndex].returnStatus; + } +} + +/* + * ======== ECDH_Params_init ======== + */ +void ECDH_Params_init(ECDH_Params *params) +{ + *params = ECDH_defaultParams; +} + +/* + * ======== ECDH_init ======== + */ +void ECDH_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== ECDH_open ======== + */ +ECDH_Handle ECDH_open(uint_least8_t index, const ECDH_Params *params) +{ + ECDH_Handle handle = NULL; + ECDH_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECDH_Params *)&ECDH_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_OPEN, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECDH_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecdhObject_ns[index].returnBehavior = params->returnBehavior; + ecdhObject_ns[index].callbackFxn = params->callbackFxn; + ecdhObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECDH_construct ======== + */ +ECDH_Handle ECDH_construct(ECDH_Config *config, const ECDH_Params *params) +{ + ECDH_Handle handle = NULL; + ECDH_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECDH_Params *)&ECDH_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECDH_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecdhObject_ns[index].returnBehavior = params->returnBehavior; + ecdhObject_ns[index].callbackFxn = params->callbackFxn; + ecdhObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECDH_close ======== + */ +void ECDH_close(ECDH_Handle handle) +{ + ECDH_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&ecdhSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== ECDH_generatePublicKey ======== + */ +int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, ECDH_OperationGeneratePublicKey *operation) +{ + ECDH_s_GeneratePublicKeyMsg generateMsg; + int_fast16_t result = ECDH_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + generateMsg.handle = handle; + generateMsg.operation = operation; + invecs[0].base = &generateMsg; + invecs[0].len = sizeof(generateMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(ecdhObject_ns[index].semaphoreTimeout) == false) + { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + ECDHCC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDH_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_GENERATE_PUBLIC_KEY, invecs, outvecs); + + ECDH_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== ECDH_computeSharedSecret ======== + */ +int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, ECDH_OperationComputeSharedSecret *operation) +{ + ECDH_s_ComputeSharedSecretMsg computeMsg; + int_fast16_t result = ECDH_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + computeMsg.handle = handle; + computeMsg.operation = operation; + invecs[0].base = &computeMsg; + invecs[0].len = sizeof(computeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(ecdhObject_ns[index].semaphoreTimeout) == false) + { + return ECDH_STATUS_RESOURCE_UNAVAILABLE; + } + + ECDHCC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDH_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_COMPUTE_SHARED_SECRET, invecs, outvecs); + + ECDH_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== ECDH_cancelOperation ======== + */ +int_fast16_t ECDH_cancelOperation(ECDH_Handle handle) +{ + ECDH_s_CancelOperationMsg cancelMsg; + int_fast16_t result = ECDH_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDH_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDH_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.h new file mode 100644 index 00000000..409266e7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDHCC26X4_ns.h + * + * @brief ECDH Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_ecdh_ECDHCC26X4_ns__include +#define ti_drivers_ecdh_ECDHCC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief ECDHCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + ECDH_CallbackFxn callbackFxn; + ECDH_ReturnBehavior returnBehavior; +} ECDHCC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdh_ECDHCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.c new file mode 100644 index 00000000..2a70a0ce --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.c @@ -0,0 +1,926 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "ECDHCC26X4_s.h" + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/*! + * @brief Union containing all supported operation structs. + */ +typedef union +{ + ECDH_OperationGeneratePublicKey generatePublicKey; + ECDH_OperationComputeSharedSecret computeSharedSecret; +} ECDH_OperationUnion; + +/* + * Stores the following: + * - Secure copy of the operation and the original pointer to the non-secure + * operation to return when the HWI callback occurs. + * - Secure copy of the result key and the original pointer to the non-secure + * result key to update the key encoding return when the HWI callback occurs. + * + * Note: Input keys are copied into PKA RAM before starting the ECDH driver + * FSM so it is not required to keep copies of those keys. + */ +typedef struct +{ + ECDH_OperationUnion operation_s; /* Secure copy of operation */ + ECDH_Operation operation_ns; /* Pointer to non-secure operation */ + CryptoKey resultKey_s; /* Secure copy of result key */ + CryptoKey *resultKey_ns; /* Pointer to non-secure result key */ +} ECDH_s_Operation; + +static ECDH_s_Operation ECDH_s_operation; + +/* + * ECDH Secure Dynamic Instance struct. + */ +typedef struct +{ + ECDH_Config config; + ECDHCC26X2_Object object; + ECDHCC26X2_HWAttrs hwAttrs; +} ECDH_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * ECDH_construct. + */ +static ECDH_s_DynamicInstance ECDH_s_dynInstance[CONFIG_ECDH_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure ECDH_s_SecureCallbacks for each driver instance opened or constructed */ +static ECDH_s_SecureCallback *ECDH_s_secureCB[ECDH_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const ECDH_Config ECDH_config[]; + +/* + * ======== ECDH_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t ECDH_s_getCallbackIndex(ECDH_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_ECDH_COUNT; index++) + { + if (handle_s == (ECDH_Handle)&ECDH_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_ECDH_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &ECDH_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_ECDH_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== ECDH_s_hwiCallback ======== + */ +static void ECDH_s_hwiCallback(ECDH_Handle handle_s, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType) +{ + int8_t index; + ECDH_s_SecureCallback *ecdhSecureCB_ns; + + index = ECDH_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < ECDH_SECURE_CALLBACK_COUNT)) + { + ecdhSecureCB_ns = ECDH_s_secureCB[index]; + + if (ecdhSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + ecdhSecureCB_ns->handle = (ECDH_Handle)(CRYPTO_S_HANDLE_ID_ECDH | index); + ecdhSecureCB_ns->returnStatus = returnStatus; + ecdhSecureCB_ns->operation = ECDH_s_operation.operation_ns; + ecdhSecureCB_ns->operationType = operationType; + + /* Copy updated key encoding to the non-secure key struct */ + if (operationType == ECDH_OPERATION_TYPE_GENERATE_PUBLIC_KEY) + { + ECDH_s_operation.resultKey_ns->encoding = operation.generatePublicKey->myPublicKey->encoding; + + if (ECDH_s_operation.resultKey_ns->encoding == CryptoKey_KEYSTORE) + { + /* Copy the updated keyID to the non-secure public key struct */ + ECDH_s_operation.resultKey_ns->u.keyStore.keyID = operation.generatePublicKey->myPublicKey->u + .keyStore.keyID; + } + } + else + { + ECDH_s_operation.resultKey_ns->encoding = operation.computeSharedSecret->sharedSecret->encoding; + + if (ECDH_s_operation.resultKey_ns->encoding == CryptoKey_KEYSTORE) + { + /* Copy the updated keyID to the non-secure shared secret struct */ + ECDH_s_operation.resultKey_ns->u.keyStore.keyID = operation.computeSharedSecret->sharedSecret->u + .keyStore.keyID; + } + } + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&ecdhSecureCB_ns->object); + } + } +} + +/* + * ======== ECDH_s_copyConfig ======== + */ +static inline psa_status_t ECDH_s_copyConfig(ECDH_Config **secureConfig, + const ECDH_Config *config, + ECDH_Handle *retHandle) +{ + ECDH_Config *config_s; + ECDH_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_ECDH_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &ECDH_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECDH_s_secureCB[i + CONFIG_TI_DRIVERS_ECDH_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_ECDH OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (ECDH_Handle)(CRYPTO_S_HANDLE_ID_ECDH | (i + CONFIG_TI_DRIVERS_ECDH_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== ECDH_s_releaseConfig ======== + */ +static inline void ECDH_s_releaseConfig(ECDH_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECDH) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_ECDH_COUNT) && (i < ECDH_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + ECDH_s_dynInstance[i - CONFIG_TI_DRIVERS_ECDH_COUNT].config.object = NULL; + } + } +} + +/* + * ======== ECDH_s_copyGenPublicKeyOperation ======== + */ +static inline psa_status_t ECDH_s_copyGenPublicKeyOperation(ECDH_OperationGeneratePublicKey *secureOperation, + CryptoKey *securePrivateKey, + CryptoKey *securePublicKey, + const ECDH_OperationGeneratePublicKey *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECDH_OperationGeneratePublicKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECDH_OperationGeneratePublicKey)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* + * Make a secure copy of the private key struct and update the operation + * struct to point to the secure key copy. Cast is required since key is + * const data. + */ + status = CryptoKey_copySecureInputKey(securePrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureOutputKey(securePublicKey, &secureOperation->myPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_copyComputeSharedSecretOperation ======== + */ +static inline psa_status_t ECDH_s_copyComputeSharedSecretOperation(ECDH_OperationComputeSharedSecret *secureOperation, + CryptoKey *securePrivateKey, + CryptoKey *securePublicKey, + CryptoKey *secureSharedSecret, + const ECDH_OperationComputeSharedSecret *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECDH_OperationComputeSharedSecret)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECDH_OperationComputeSharedSecret)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* + * Make a secure copy of the private key struct and update the operation + * struct to point to the secure key copy. Cast is required since key is + * const data. + */ + status = CryptoKey_copySecureInputKey(securePrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. Cast is required since key is + * const data. + */ + status = CryptoKey_copySecureInputKey(securePublicKey, &secureOperation->theirPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the shared secret key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureOutputKey(secureSharedSecret, &secureOperation->sharedSecret); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_copyParams ======== + */ +static psa_status_t ECDH_s_copyParams(ECDH_Params *secureParams, const ECDH_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(ECDH_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(ECDH_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == ECDH_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == ECDH_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == ECDH_RETURN_BEHAVIOR_POLLING)) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using ECDH_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = ECDH_s_hwiCallback; + + /* + * The underlying ECDH driver is interrupt-driven regardless of the return + * behavior specified. Since secure partitions cannot process interrupt + * signals while a PSA call is running, callback return behavior must be + * forced for all app-specified return behaviors including polling. + */ + secureParams->returnBehavior = ECDH_RETURN_BEHAVIOR_CALLBACK; + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== ECDH_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static ECDH_Handle ECDH_s_getHandle(ECDH_Handle nsHandle) +{ + ECDH_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECDH) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_ECDH_COUNT) + { + secureHandle = (ECDH_Handle)&ECDH_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_ECDH_COUNT) && (i < ECDH_SECURE_CALLBACK_COUNT)) + { + secureHandle = &ECDH_s_dynInstance[i - CONFIG_TI_DRIVERS_ECDH_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== ECDH_s_registerCallback ======== + */ +static inline psa_status_t ECDH_s_registerCallback(psa_msg_t *msg) +{ + ECDH_Handle handle_s; + ECDH_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = ECDH_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = ECDH_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < ECDH_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(ECDH_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to ECDH_s_SecureCallback located in + * non-secure memory. + */ + ECDH_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== ECDH_s_construct ======== + */ +static inline psa_status_t ECDH_s_construct(psa_msg_t *msg) +{ + ECDH_s_ConstructMsg constructMsg; + ECDH_Handle handle; + ECDH_Params params_s; + const ECDH_Params *paramsPtr_s = NULL; + ECDH_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + ECDH_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = ECDH_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = ECDH_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = ECDH_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_open ======== + */ +static inline psa_status_t ECDH_s_open(psa_msg_t *msg) +{ + ECDH_s_OpenMsg openMsg; + ECDH_Handle handle; + ECDH_Params params_s; + ECDH_Params *paramsPtr_s = NULL; + ECDH_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = ECDH_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = ECDH_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECDH_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_ECDH OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (ECDH_Handle)(CRYPTO_S_HANDLE_ID_ECDH | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_close ======== + */ +static inline psa_status_t ECDH_s_close(psa_msg_t *msg) +{ + ECDH_Handle handle_s; + ECDH_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDH_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ECDH_close(handle_s); + + /* Release the secure config if it is a dynamic */ + ECDH_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + ECDH_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_generatePublicKey ======== + */ +static inline psa_status_t ECDH_s_generatePublicKey(psa_msg_t *msg) +{ + ECDH_s_GeneratePublicKeyMsg genPubKeyMsg; + ECDH_Handle handle_s; + ECDH_OperationGeneratePublicKey *operation_s; + CryptoKey privateKey_s; + CryptoKey *publicKey_s = &ECDH_s_operation.resultKey_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genPubKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genPubKeyMsg, sizeof(genPubKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDH_s_getHandle(genPubKeyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECDH_s_operation.operation_s.generatePublicKey; + + /* Save pointer to non-secure operation struct */ + ECDH_s_operation.operation_ns = (ECDH_Operation)genPubKeyMsg.operation; + + /* Save pointer to non-secure public key */ + ECDH_s_operation.resultKey_ns = genPubKeyMsg.operation->myPublicKey; + + /* Validate and copy operation and key structs */ + status = ECDH_s_copyGenPublicKeyOperation(operation_s, &privateKey_s, publicKey_s, genPubKeyMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECDH_generatePublicKey(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECDH_generatePublicKey(genPubKeyMsg.handle, genPubKeyMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECDH_s_computeSharedSecret ======== + */ +static inline psa_status_t ECDH_s_computeSharedSecret(psa_msg_t *msg) +{ + ECDH_s_ComputeSharedSecretMsg compSharedSecretMsg; + ECDH_Handle handle_s; + ECDH_OperationComputeSharedSecret *operation_s; + CryptoKey privateKey_s; + CryptoKey publicKey_s; + CryptoKey *sharedSecret_s = &ECDH_s_operation.resultKey_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(compSharedSecretMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &compSharedSecretMsg, sizeof(compSharedSecretMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDH_s_getHandle(compSharedSecretMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECDH_s_operation.operation_s.computeSharedSecret; + + /* Save pointer to non-secure operation struct */ + ECDH_s_operation.operation_ns = (ECDH_Operation)compSharedSecretMsg.operation; + + /* Save pointer to non-secure shared secret key */ + ECDH_s_operation.resultKey_ns = compSharedSecretMsg.operation->sharedSecret; + + /* Validate and copy operation and key structs */ + status = ECDH_s_copyComputeSharedSecretOperation(operation_s, + &privateKey_s, + &publicKey_s, + sharedSecret_s, + compSharedSecretMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECDH_computeSharedSecret(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECDH_computeSharedSecret(compSharedSecretMsg.handle, compSharedSecretMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECDH_s_cancelOperation ======== + */ +static inline psa_status_t ECDH_s_cancelOperation(psa_msg_t *msg) +{ + ECDH_Handle handle_s; + ECDH_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = ECDH_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = ECDH_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDH_s_handlePsaMsg ======== + */ +psa_status_t ECDH_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If ECDH_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case ECDH_S_MSG_TYPE_CONSTRUCT: + status = ECDH_s_construct(msg); + break; + + case ECDH_S_MSG_TYPE_OPEN: + status = ECDH_s_open(msg); + break; + + /* + * ECDH_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case ECDH_S_MSG_TYPE_REGISTER_CALLBACK: + status = ECDH_s_registerCallback(msg); + break; + + case ECDH_S_MSG_TYPE_CLOSE: + status = ECDH_s_close(msg); + break; + + case ECDH_S_MSG_TYPE_GENERATE_PUBLIC_KEY: + status = ECDH_s_generatePublicKey(msg); + break; + + case ECDH_S_MSG_TYPE_COMPUTE_SHARED_SECRET: + status = ECDH_s_computeSharedSecret(msg); + break; + + /* + * ECDH_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case ECDH_S_MSG_TYPE_CANCEL_OPERATION: + status = ECDH_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== ECDH_s_init ======== + */ +void ECDH_s_init(void) +{ + ECDH_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.h new file mode 100644 index 00000000..c9af771e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdh/ECDHCC26X4_s.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_ecdh_ECDHCC26X4_s__include +#define ti_drivers_ecdh_ECDHCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDH secure message types + */ +#define ECDH_S_MSG_TYPE_CONSTRUCT ECDH_S_MSG_TYPE(0U) +#define ECDH_S_MSG_TYPE_OPEN ECDH_S_MSG_TYPE(1U) +#define ECDH_S_MSG_TYPE_REGISTER_CALLBACK ECDH_S_MSG_TYPE(2U) +#define ECDH_S_MSG_TYPE_CLOSE ECDH_S_MSG_TYPE(3U) +#define ECDH_S_MSG_TYPE_GENERATE_PUBLIC_KEY ECDH_S_MSG_TYPE(4U) +#define ECDH_S_MSG_TYPE_COMPUTE_SHARED_SECRET ECDH_S_MSG_TYPE(5U) +#define ECDH_S_MSG_TYPE_CANCEL_OPERATION ECDH_S_MSG_TYPE(6U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using ECDH_construct(). + */ +#ifndef CONFIG_ECDH_S_CONFIG_POOL_SIZE + #define CONFIG_ECDH_S_CONFIG_POOL_SIZE 1 +#endif + +#define ECDH_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_ECDH_COUNT + CONFIG_ECDH_S_CONFIG_POOL_SIZE) + +/* + * ========= ECDH Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* ECDH callback fxn parameters */ + ECDH_Handle handle; + int_fast16_t returnStatus; + ECDH_Operation operation; + ECDH_OperationType operationType; +} ECDH_s_SecureCallback; + +/* + * ========= ECDH Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * ECDH secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + ECDH_Config *config; + const ECDH_Params *params; +} ECDH_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const ECDH_Params *params; +} ECDH_s_OpenMsg; + +typedef struct +{ + ECDH_Handle handle; + ECDH_s_SecureCallback *callback; +} ECDH_s_CallbackMsg; + +typedef struct +{ + ECDH_Handle handle; +} ECDH_s_CloseMsg; + +typedef struct +{ + ECDH_Handle handle; + ECDH_OperationGeneratePublicKey *operation; +} ECDH_s_GeneratePublicKeyMsg; + +typedef struct +{ + ECDH_Handle handle; + ECDH_OperationComputeSharedSecret *operation; +} ECDH_s_ComputeSharedSecretMsg; + +typedef struct +{ + ECDH_Handle handle; +} ECDH_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for ECDH secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t ECDH_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the ECDH secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void ECDH_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdh_ECDHCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.c b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.c new file mode 100644 index 00000000..e752e6b5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.c @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) + +/* Defines */ + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +/* + * ======== ECDSA_init ======== + */ +void ECDSA_init(void) +{} + +/* + * ======== ECDSA_close ======== + */ +void ECDSA_close(ECDSA_Handle handle) +{ + ECDSACC26X1_Object *object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== ECDSA_construct ======== + */ +ECDSA_Handle ECDSA_construct(ECDSA_Config *config, const ECDSA_Params *params) +{ + ECDSA_Handle handle = (ECDSA_Handle)config; + ECDSACC26X1_Object *object = handle->object; + uintptr_t key; + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &ECDSA_defaultParams; + } + + /* Since CC26X1 ECC is a pure SW implementation, callback return behavior is not supported */ + if (params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK) + { + return NULL; + } + + key = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + /* Initialize object with NIST-P256 curve */ + ECC_initialize(&(object->eccState), object->eccWorkZone); + + object->returnBehavior = params->returnBehavior; + + return handle; +} + +/* + * ======== ECDSA_sign ======== + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation) +{ + ECDSACC26X1_Object *object = handle->object; + ECDSACC26X1_HWAttrs const *hwAttrs = handle->hwAttrs; + int_fast16_t returnStatus = ECDSA_STATUS_ERROR; + uint8_t eccStatus = STATUS_PRIVATE_KEY_LARGER_EQUAL_ORDER; + TRNGCC26XX_Object trngObject = {0}; + TRNGCC26XX_HWAttrs trngHwAttrs; + TRNG_Config trngConfig; + TRNG_Handle trngHandle; + TRNG_Params trngParams; + int_fast16_t trngStatus; + CryptoKey pmsnKey; + + /* We need to allocate local copies of the private and public keys because + * the ECC in ROM implementation requires the word 0x08 to be prepended to + * every array input. + * The length word is prepended during initialisation here. + */ + ECC_NISTP256_Param privateKeyUnion; + ECC_NISTP256_Param pmsnUnion; + ECC_NISTP256_Param hashUnion; + ECC_NISTP256_Param rUnion; + ECC_NISTP256_Param sUnion; + + /* We need to set the first word to 0x08 in code. Otherwise, the compiler + * will allocate an individual copy of the entire array in the const section + * and copy that in. That is a significant amount of data. + */ + privateKeyUnion.word[0] = 0x08; + pmsnUnion.word[0] = 0x08; + hashUnion.word[0] = 0x08; + rUnion.word[0] = 0x08; + sUnion.word[0] = 0x08; + + /* We want to store the PMSN locally in SRAM */ + CryptoKeyPlaintext_initBlankKey(&pmsnKey, + &pmsnUnion.byte[ECC_LENGTH_OFFSET_BYTES], + ECC_NISTP256_PARAM_LENGTH_BYTES); + + /* We are calling TRNG_init() here to limit references to TRNG_xyz to sign + * operations. + * That means that the linker can remove all TRNG related code if only + * ECDSA_verify functionality is used. + */ + TRNG_init(); + + trngHwAttrs.intPriority = hwAttrs->trngIntPriority; + trngConfig.object = &trngObject; + trngConfig.hwAttrs = &trngHwAttrs; + + TRNG_Params_init(&trngParams); + + if (object->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + { + trngParams.returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING; + } + else + { + trngParams.returnBehavior = TRNG_RETURN_BEHAVIOR_POLLING; + } + + trngHandle = TRNG_construct(&trngConfig, &trngParams); + + if (trngHandle == NULL) + { + return ECDSA_STATUS_ERROR; + } + + /* Generate the PMSN. If it is not in range [1, n-1], generate another + * one. + */ + do + { + trngStatus = TRNG_generateEntropy(trngHandle, &pmsnKey); + + if (trngStatus != TRNG_STATUS_SUCCESS) + { + TRNG_close(trngHandle); + return ECDSA_STATUS_ERROR; + } + + /* Check if pmsn in [1, n-1] */ + eccStatus = ECC_validatePrivateKey(&(object->eccState), pmsnUnion.word); + } while (eccStatus != STATUS_PRIVATE_VALID); + + TRNG_close(trngHandle); + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the ECC in + * ROM functions + */ + CryptoUtils_reverseCopyPad(operation->hash, &hashUnion.word[1], ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopyPad(operation->myPrivateKey->u.plaintext.keyMaterial, + &privateKeyUnion.word[1], + ECC_NISTP256_PARAM_LENGTH_BYTES); + + eccStatus = ECC_ECDSA_sign(&(object->eccState), + privateKeyUnion.word, + hashUnion.word, + pmsnUnion.word, + rUnion.word, + sUnion.word); + + /* Check the ECC in ROM return code and set the driver status accordingly */ + if (eccStatus == STATUS_ECDSA_SIGN_OK) + { + returnStatus = ECDSA_STATUS_SUCCESS; + } + + /* Now that we have created r and s, we need to copy them back and reverse + * them since the ECC in ROM implementation provides little-endian values. + */ + CryptoUtils_reverseCopy(&rUnion.word[1], operation->r, ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopy(&sUnion.word[1], operation->s, ECC_NISTP256_PARAM_LENGTH_BYTES); + + return returnStatus; +} + +/* + * ======== ECDSA_verify ======== + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation) +{ + ECDSACC26X1_Object *object = handle->object; + int_fast16_t returnStatus = ECDSA_STATUS_ERROR; + uint8_t eccStatus; + + /* Validate key sizes to make sure octet string format is used */ + if (operation->theirPublicKey->u.plaintext.keyLength != 2 * operation->curve->length + OCTET_STRING_OFFSET || + operation->theirPublicKey->u.plaintext.keyMaterial[0] != 0x04) + { + return ECDSA_STATUS_INVALID_KEY_SIZE; + } + + /* We need to allocate local copies of the private and public keys because + * the ECC in ROM implementation requires the word 0x08 to be prepended to + * every array input. + * The length word is prepended during initialisation here. + */ + ECC_NISTP256_Param publicKeyUnionX; + ECC_NISTP256_Param publicKeyUnionY; + ECC_NISTP256_Param hashUnion; + ECC_NISTP256_Param rUnion; + ECC_NISTP256_Param sUnion; + + /* We need to set the first word to 0x08 in code. Otherwise, the compiler + * will allocate an individual copy of the entire array in the const section + * and copy that in. That is a significant amount of data. + */ + publicKeyUnionX.word[0] = 0x08; + publicKeyUnionY.word[0] = 0x08; + hashUnion.word[0] = 0x08; + rUnion.word[0] = 0x08; + sUnion.word[0] = 0x08; + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the ECC in + * ROM functions + */ + CryptoUtils_reverseCopyPad(operation->hash, &hashUnion.word[1], ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopyPad(operation->r, &rUnion.word[1], ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopyPad(operation->s, &sUnion.word[1], ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopyPad(operation->theirPublicKey->u.plaintext.keyMaterial + OCTET_STRING_OFFSET, + &publicKeyUnionX.word[1], + ECC_NISTP256_PARAM_LENGTH_BYTES); + + CryptoUtils_reverseCopyPad(operation->theirPublicKey->u.plaintext.keyMaterial + ECC_NISTP256_PARAM_LENGTH_BYTES + + OCTET_STRING_OFFSET, + &publicKeyUnionY.word[1], + ECC_NISTP256_PARAM_LENGTH_BYTES); + + /* Verify r in range [1, n-1] where n is the order of the curve */ + eccStatus = ECC_validatePrivateKey(&object->eccState, rUnion.word); + + if (eccStatus == STATUS_PRIVATE_VALID) + { + /* Verify s in range [1, n-1] where n is the order of the curve */ + eccStatus = ECC_validatePrivateKey(&object->eccState, sUnion.word); + + if (eccStatus != STATUS_PRIVATE_VALID) + { + returnStatus = ECDSA_STATUS_S_LARGER_THAN_ORDER; + } + } + else + { + returnStatus = ECDSA_STATUS_R_LARGER_THAN_ORDER; + } + + if (eccStatus == STATUS_PRIVATE_VALID) + { + eccStatus = ECC_validatePublicKey(&object->eccState, publicKeyUnionX.word, publicKeyUnionY.word); + } + + if (eccStatus == STATUS_ECC_POINT_ON_CURVE) + { + + eccStatus = ECC_ECDSA_verify(&(object->eccState), + publicKeyUnionX.word, + publicKeyUnionY.word, + hashUnion.word, + rUnion.word, + sUnion.word); + + /* Check the ECC in ROM return code and set the driver status accordingly */ + if (eccStatus == STATUS_ECDSA_VALID_SIGNATURE) + { + returnStatus = ECDSA_STATUS_SUCCESS; + } + } + + return returnStatus; +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.h b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.h new file mode 100644 index 00000000..1f22c9d4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X1.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2020-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDSACC26X1.h + * + * @brief ECDSA driver implementation for the CC26X1 family + * + * This file should only be included in the board file to fill the ECDSA_config + * struct. + * + * # Hardware and Implementation Details # + * + * The driver is backed by a software ECC library implementation. + * + * # Supported Curves # + * + * The driver implementation supports the following curves for ECDSA: + * + * | Curves Supported | + * |------------------| + * | NISTP256 | + */ + +#ifndef ti_drivers_ecdsa_ECDSACC26X1__include +#define ti_drivers_ecdsa_ECDSACC26X1__include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_ecc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief ECDSACC26X1 Hardware Attributes + * + * ECDSACC26X1 hardware attributes should be included in the board file + * and pointed to by the ECDSA_config struct. + */ +typedef struct +{ + /*! @brief TRNG Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t trngIntPriority; +} ECDSACC26X1_HWAttrs; + +/*! + * @brief ECDSACC26X1 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + ECDSA_ReturnBehavior returnBehavior; /* Callback mode is not supported */ + ECC_State eccState; + uint32_t eccWorkZone[288]; +} ECDSACC26X1_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdsa_ECDSACC26X1__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.c b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.c new file mode 100644 index 00000000..0952996c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.c @@ -0,0 +1,1247 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_pka.h) +#include DeviceFamily_constructPath(inc/hw_pka_ram.h) +#include DeviceFamily_constructPath(driverlib/pka.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif + + /* + * Since ECDSA driver only supports NIST P-256 curves + * Max key sizes 256b private keys, + * (256b) * 2 + 1B for octet offset for public keys + */ + #define ECDSA_MAX_KEYSTORE_PUBLIC_KEY_SIZE 65 + #define ECDSA_MAX_KEYSTORE_PRIVATE_KEY_SIZE 32 +#endif + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +#define SCRATCH_KEY_OFFSET 512 +#define SCRATCH_KEY_SIZE 96 +#define SCRATCH_PRIVATE_KEY ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET)) +#define SCRATCH_PUBLIC_X ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 1 * SCRATCH_KEY_SIZE)) +#define SCRATCH_PUBLIC_Y ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 2 * SCRATCH_KEY_SIZE)) + +#define SCRATCH_BUFFER_OFFSET 1024 +#define SCRATCH_BUFFER_SIZE 256 +#define SCRATCH_BUFFER_0 ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 0 * SCRATCH_BUFFER_SIZE)) +#define SCRATCH_BUFFER_1 ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 1 * SCRATCH_BUFFER_SIZE)) + +/* Forward declarations */ +static void ECDSACC26X2_hwiFxn(uintptr_t arg0); +#if (TFM_ENABLED == 0) +static void ECDSACC26X2_internalCallbackFxn(ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType); +#endif +static int_fast16_t ECDSACC26X2_waitForAccess(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_waitForResult(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_runSignFSM(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_runVerifyFSM(ECDSA_Handle handle); +static int_fast16_t ECDSACC26X2_convertReturnValue(uint32_t pkaResult); +static void ECDSACC26X2_trngCallback(TRNG_Handle handle, int_fast16_t returnValue, CryptoKey *pmsn); + +/* Static globals */ +static bool isInitialized = false; +static uint32_t resultAddress; + +static uint32_t scratchBuffer0Size = SCRATCH_BUFFER_SIZE; +static uint32_t scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + +#if (ENABLE_KEY_STORAGE == 1) +uint8_t ECDSACC26X2_keyStorePrivateKeyMaterial[ECDSA_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; +uint8_t ECDSACC26X2_keyStorePublicKeyMaterial[ECDSA_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif /* (ENABLE_KEY_STORAGE == 1) */ + +#if (TFM_ENABLED == 0) +/* + * ======== ECDSACC26X2_internalCallbackFxn ======== + */ +static void ECDSACC26X2_internalCallbackFxn(ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType) +{ + ECDSACC26X2_Object *object = handle->object; + + /* This function is only ever registered when in ECDSA_RETURN_BEHAVIOR_BLOCKING + * or ECDSA_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else + { + PKAResourceCC26XX_pollingFlag = 1; + } +} +#endif + +/* + * ======== ECDSACC26X2_hwiFxn ======== + */ +static void ECDSACC26X2_hwiFxn(uintptr_t arg0) +{ + ECDSACC26X2_Object *object = ((ECDSA_Handle)arg0)->object; + uint32_t key; + + /* Disable interrupt again */ + IntDisable(INT_PKA_IRQ); + + /* Execute next states */ + do + { + object->operationStatus = object->fsmFxn((ECDSA_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECDSACC26X2_STATUS_FSM_RUN_FSM); + + /* We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if (object->operationCanceled) + { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECDSA_STATUS_CANCELED; + } + + switch (object->operationStatus) + { + case ECDSACC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECDSA_STATUS_SUCCESS: + /* Intentional fall through */ + case ECDSA_STATUS_ERROR: + /* Intentional fall through */ + case ECDSA_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->callbackFxn((ECDSA_Handle)arg0, object->operationStatus, object->operation, object->operationType); + } +} + +/* + * ======== ECDSACC26X2_trngCallback ======== + */ +static void ECDSACC26X2_trngCallback(TRNG_Handle handle, int_fast16_t returnValue, CryptoKey *pmsn) +{ + ECDSACC26X2_Object *object = ((ECDSACC26X2_Object *)(handle)); + uint32_t pkaResult = 0; + int_fast16_t trngStatus; + uint32_t tmp = 0; + uint8_t i; + + /* Check that PMSN is not zero. If tmp is zero, we need to generate a + * new PMSN. + */ + for (i = 0; i < pmsn->u.plaintext.keyLength / sizeof(uint32_t); i++) + { + tmp |= ((uint32_t *)(pmsn->u.plaintext.keyMaterial))[i]; + } + + /* Check that PMSN < curve order */ + PKABigNumCmpStart(pmsn->u.plaintext.keyMaterial, object->operation.sign->curve->order, pmsn->u.plaintext.keyLength); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + // TODO: fix error handling since the FSM overwrites the error status + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + /* If the randomly generated PMSN is too large, generate another + * one. + */ + trngStatus = TRNG_generateEntropy(handle, &object->pmsnKey); + + /* If the generateEntropy call somehow fails, we need to abort + * and let the ECDSA driver clean up. Trigger the FSM and let that + * code path take care of it. + */ + if (trngStatus != TRNG_STATUS_SUCCESS) + { + object->operationStatus = ECDSA_STATUS_ERROR; + + TRNG_close(object->trngHandle); + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + } + } + else if (tmp == 0 || returnValue != TRNG_STATUS_SUCCESS) + { + object->operationStatus = ECDSA_STATUS_ERROR; + + TRNG_close(object->trngHandle); + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + } + else + { + + TRNG_close(object->trngHandle); + /* Run the FSM by triggering the PKA interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + } +} + +/* + * ======== ECDSA_getPrivateKey ======== + */ +static int_fast16_t ECDSA_getPrivateKey(const CryptoKey *privateKey, + uint8_t **privateKeyMaterial, + size_t *privateKeyLength) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; +#endif + if (privateKey->encoding == CryptoKey_PLAINTEXT) + { + *privateKeyMaterial = privateKey->u.plaintext.keyMaterial; + *privateKeyLength = privateKey->u.plaintext.keyLength; + status = ECDSA_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (privateKey->encoding == CryptoKey_KEYSTORE) + { + memset(ECDSACC26X2_keyStorePrivateKeyMaterial, 0, sizeof(ECDSACC26X2_keyStorePrivateKeyMaterial)); + + GET_KEY_ID(keyID, privateKey->u.keyStore.keyID); + + /* Obtain the private key from keystore. Although the key is used by + * ECDSA to sign a hash, KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE must be + * specified since ECDSA_sign() is used to support both psa_sign_hash() + * and psa_sign_message(). When a key with + * KEYSTORE_PSA_KEY_USAGE_SIGN_HASH flag is retrieved, it's usage + * flags are extended to include KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE + * which allows it to be used for both use cases. + */ + keyStoreStatus = KeyStore_PSA_getKey(keyID, + ECDSACC26X2_keyStorePrivateKeyMaterial, + sizeof(ECDSACC26X2_keyStorePrivateKeyMaterial), + privateKeyLength, + KEYSTORE_PSA_ALG_ECDSA, + KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE); + + if ((keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) || (*privateKeyLength != privateKey->u.keyStore.keyLength)) + { + status = ECDSA_STATUS_KEYSTORE_ERROR; + } + else + { + *privateKeyMaterial = ECDSACC26X2_keyStorePrivateKeyMaterial; + status = ECDSA_STATUS_SUCCESS; + } + } +#endif + else + { + status = ECDSA_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECDSA_getPublicKey ======== + */ +static int_fast16_t ECDSA_getPublicKey(const CryptoKey *publicKey, uint8_t **publicKeyMaterial, size_t *publicKeyLength) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; +#endif + if (publicKey->encoding == CryptoKey_PLAINTEXT) + { + *publicKeyMaterial = publicKey->u.plaintext.keyMaterial; + *publicKeyLength = publicKey->u.plaintext.keyLength; + status = ECDSA_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (publicKey->encoding == CryptoKey_KEYSTORE) + { + memset(ECDSACC26X2_keyStorePublicKeyMaterial, 0, sizeof(ECDSACC26X2_keyStorePublicKeyMaterial)); + + GET_KEY_ID(keyID, publicKey->u.keyStore.keyID); + + /* Obtain the public key from keystore. Although the key is used by + * ECDSA to verify a hash, KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE must be + * specified since ECDSA_verify() is used to support both + * psa_verify_hash() and psa_verify_message(). When a key with + * KEYSTORE_PSA_KEY_USAGE_VERIFY_HASH flag is retrieved, it's usage + * flags are extended to include KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE + * which allows it to be used for both use cases. + */ + keyStoreStatus = KeyStore_PSA_getKey(keyID, + ECDSACC26X2_keyStorePublicKeyMaterial, + sizeof(ECDSACC26X2_keyStorePublicKeyMaterial), + publicKeyLength, + KEYSTORE_PSA_ALG_ECDSA, + KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE); + + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS || (*publicKeyLength != publicKey->u.keyStore.keyLength)) + { + status = ECDSA_STATUS_KEYSTORE_ERROR; + } + else + { + *publicKeyMaterial = ECDSACC26X2_keyStorePublicKeyMaterial; + status = ECDSA_STATUS_SUCCESS; + } + } +#endif + else + { + status = ECDSA_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECDSACC26X2_runSignFSM ======== + */ +static int_fast16_t ECDSACC26X2_runSignFSM(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + + uint8_t *privateKeyMaterial; + size_t privateKeyLength; + int_fast16_t status; + + switch (object->fsmState) + { + case ECDSACC26X2_FSM_SIGN_COMPUTE_R: + + PKAEccMultiplyStart(object->pmsnKey.u.plaintext.keyMaterial, + object->operation.sign->curve->generatorX, + object->operation.sign->curve->generatorY, + object->operation.sign->curve->prime, + object->operation.sign->curve->a, + object->operation.sign->curve->b, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_R_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->operation.sign->r, + NULL, + resultAddress, + object->operation.sign->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_R_MOD_N: + + PKABigNumModStart(object->operation.sign->r, + object->operation.sign->curve->length, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_R_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.sign->r, + object->operation.sign->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE: + + PKABigNumInvModStart(object->pmsnKey.u.plaintext.keyMaterial, + object->operation.sign->curve->length, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE_RESULT: + + pkaResult = PKABigNumInvModGetResult(object->operation.sign->s, + object->operation.sign->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R: + + status = ECDSA_getPrivateKey(object->operation.sign->myPrivateKey, &privateKeyMaterial, &privateKeyLength); + + if (status != ECDSA_STATUS_SUCCESS) + { + return status; + } + + CryptoUtils_reverseCopyPad(privateKeyMaterial, SCRATCH_PRIVATE_KEY, privateKeyLength); + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.sign->curve->length, + object->operation.sign->r, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R_RESULT: + + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBuffer0Size, resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_ADD_HASH: + + /* Convert hash from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->hash, + SCRATCH_BUFFER_1, + object->operation.verify->curve->length); + + PKABigNumAddStart((uint8_t *)SCRATCH_BUFFER_0, + scratchBuffer0Size, + (uint8_t *)SCRATCH_BUFFER_1, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_ADD_HASH_RESULT: + + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumAddGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBuffer0Size, resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE: + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_BUFFER_0, + scratchBuffer0Size, + object->operation.sign->s, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE_RESULT: + + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBuffer0Size, resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_SIGN_MOD_N: + + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + scratchBuffer0Size, + object->operation.sign->curve->order, + object->operation.sign->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_SIGN_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.sign->s, + object->operation.sign->curve->length, + resultAddress); + + /* Convert r from little-endian integer to OS format*/ + CryptoUtils_reverseBufferBytewise(object->operation.sign->r, object->operation.sign->curve->length); + + /* Convert s from little-endian integer to OS format*/ + CryptoUtils_reverseBufferBytewise(object->operation.sign->s, object->operation.sign->curve->length); + + if (pkaResult == PKA_STATUS_SUCCESS) + { + return ECDSA_STATUS_SUCCESS; + } + else + { + return ECDSA_STATUS_ERROR; + } + + default: + return ECDSA_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDSACC26X2_runVerifyFSM ======== + */ +static int_fast16_t ECDSACC26X2_runVerifyFSM(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + + uint8_t *publicKeyMaterial; + size_t publicKeyLength; + int_fast16_t status; + + switch (object->fsmState) + { + case ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE: + + /* Convert r from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->r, + SCRATCH_BUFFER_0, + object->operation.verify->curve->length); + + PKABigNumCmpStart((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + return ECDSA_STATUS_R_LARGER_THAN_ORDER; + } + + /* Convert s from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->s, + SCRATCH_BUFFER_0, + object->operation.verify->curve->length); + + PKABigNumCmpStart((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult == PKA_STATUS_A_LESS_THAN_B) + { + return ECDSACC26X2_STATUS_FSM_RUN_FSM; + } + else + { + return ECDSA_STATUS_S_LARGER_THAN_ORDER; + } + + case ECDSACC26X2_FSM_VERIFY_VALIDATE_PUBLIC_KEY: + + status = ECDSA_getPublicKey(object->operation.verify->theirPublicKey, &publicKeyMaterial, &publicKeyLength); + + if (status != ECDSA_STATUS_SUCCESS) + { + return status; + } + + /* Validate key sizes to make sure octet string format is used */ + if ((publicKeyLength != ((2 * object->operation.verify->curve->length) + OCTET_STRING_OFFSET)) || + (publicKeyMaterial[0] != 0x04)) + { + return ECDSA_STATUS_INVALID_KEY_SIZE; + } + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.verify->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verify->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.verify->curve->length); + + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart((uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->order, + object->operation.verify->curve->length); + + // Break out early since no PKA operation was started by the verify fxn + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV: + + /* Convert s from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->s, + SCRATCH_BUFFER_0, + object->operation.verify->curve->length); + + PKABigNumInvModStart((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->length, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV_RESULT: + + pkaResult = PKABigNumInvModGetResult((uint8_t *)SCRATCH_BUFFER_1, + object->operation.verify->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH: + + /* Convert hash from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->hash, + SCRATCH_BUFFER_0, + object->operation.verify->curve->length); + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_BUFFER_1, + object->operation.verify->curve->length, + (uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH_RESULT: + + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBuffer0Size, resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N: + + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + scratchBuffer0Size, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N_RESULT: + // Check previous result + pkaResult = PKABigNumModGetResult((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->length, + resultAddress); + + scratchBuffer0Size = object->operation.verify->curve->length; + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_G: + + PKAEccMultiplyStart((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->generatorX, + object->operation.verify->curve->generatorY, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_G_RESULT: + + pkaResult = PKAEccMultiplyGetResult((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.verify->curve->length, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R: + + /* Convert r from OS format to little-endian integer */ + CryptoUtils_reverseCopyPad(object->operation.verify->r, + SCRATCH_PRIVATE_KEY, + object->operation.verify->curve->length); + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_BUFFER_1, + object->operation.verify->curve->length, + (uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_RESULT: + + scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_1, &scratchBuffer1Size, resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N: + + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_1, + scratchBuffer1Size, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult((uint8_t *)SCRATCH_BUFFER_1, + object->operation.verify->curve->length, + resultAddress); + + scratchBuffer1Size = object->operation.verify->curve->length; + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY: + + status = ECDSA_getPublicKey(object->operation.verify->theirPublicKey, &publicKeyMaterial, &publicKeyLength); + + if (status != ECDSA_STATUS_SUCCESS) + { + return status; + } + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.verify->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verify->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.verify->curve->length); + + PKAEccMultiplyStart((uint8_t *)SCRATCH_BUFFER_1, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->b, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY_RESULT: + + pkaResult = PKAEccMultiplyGetResult((uint8_t *)SCRATCH_BUFFER_1, + (uint8_t *)SCRATCH_BUFFER_1 + object->operation.verify->curve->length, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS: + + PKAEccAddStart((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.verify->curve->length, + (uint8_t *)SCRATCH_BUFFER_1, + (uint8_t *)SCRATCH_BUFFER_1 + object->operation.verify->curve->length, + object->operation.verify->curve->prime, + object->operation.verify->curve->a, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS_RESULT: + + pkaResult = PKAEccAddGetResult((uint8_t *)SCRATCH_BUFFER_0, + NULL, + resultAddress, + object->operation.verify->curve->length); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N: + + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->length, + object->operation.verify->curve->order, + object->operation.verify->curve->length, + &resultAddress); + + break; + + case ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult((uint8_t *)SCRATCH_BUFFER_0, + object->operation.verify->curve->length, + resultAddress); + + return ECDSACC26X2_convertReturnValue(pkaResult); + + case ECDSACC26X2_FSM_VERIFY_COMPARE_RESULT_R: + + CryptoUtils_reverseCopyPad(object->operation.verify->r, + SCRATCH_PRIVATE_KEY, + object->operation.verify->curve->length); + + /* The CPU will rearrange each word in r to take care of aligned + * access. The scratch buffer location is already word aligned. + */ + if (CryptoUtils_buffersMatchWordAligned(SCRATCH_BUFFER_0, + SCRATCH_PRIVATE_KEY, + object->operation.verify->curve->length)) + { + return ECDSA_STATUS_SUCCESS; + } + else + { + return ECDSA_STATUS_ERROR; + } + + default: + return ECDSA_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECDSACC26X2_convertReturnValue ======== + */ +static int_fast16_t ECDSACC26X2_convertReturnValue(uint32_t pkaResult) +{ + switch (pkaResult) + { + case PKA_STATUS_SUCCESS: + + return ECDSACC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return ECDSA_STATUS_POINT_AT_INFINITY; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + + return ECDSA_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + + return ECDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + default: + return ECDSA_STATUS_ERROR; + } +} + +/* + * ======== ECDSACC26X2_waitForAccess ======== + */ +static int_fast16_t ECDSACC26X2_waitForAccess(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECDSACC26X2_waitForResult ======== + */ +static int_fast16_t ECDSACC26X2_waitForResult(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) + { + case ECDSA_RETURN_BEHAVIOR_POLLING: +#if (TFM_ENABLED == 0) + while (!PKAResourceCC26XX_pollingFlag) {} +#else + /* + * True polling mode must be used because secure partitions cannot + * process interrupt messages while a PSA call is in progress. + */ + + /* Execute next states */ + do + { + object->operationStatus = object->fsmFxn(handle); + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + object->fsmState++; + } while ((object->operationStatus == ECDSACC26X2_STATUS_FSM_RUN_FSM) || + (object->operationStatus == ECDSACC26X2_STATUS_FSM_RUN_PKA_OP)); + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +#endif + return object->operationStatus; + case ECDSA_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + case ECDSA_RETURN_BEHAVIOR_CALLBACK: + return ECDSA_STATUS_SUCCESS; + default: + return ECDSA_STATUS_ERROR; + } +} + +/* + * ======== ECDSA_init ======== + */ +void ECDSA_init(void) +{ + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== ECDSA_close ======== + */ +void ECDSA_close(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on PKA Module. */ + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== ECDSA_construct ======== + */ +ECDSA_Handle ECDSA_construct(ECDSA_Config *config, const ECDSA_Params *params) +{ + ECDSA_Handle handle; + ECDSACC26X2_Object *object; + uintptr_t key; + + handle = (ECDSA_Handle)config; + object = handle->object; + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &ECDSA_defaultParams; + } + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; +#if (TFM_ENABLED == 1) + /* Always use the secure callback function */ + object->callbackFxn = params->callbackFxn; +#else + object->callbackFxn = params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn + : ECDSACC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; +#endif + + /* Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. */ + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECDSA_sign ======== + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation) +{ + ECDSACC26X2_Object *object = handle->object; + ECDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + TRNG_Params trngParams; + int_fast16_t trngStatus; + + if (ECDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operation.sign = operation; + object->operationType = ECDSA_OPERATION_TYPE_SIGN; + object->fsmState = ECDSACC26X2_FSM_SIGN_COMPUTE_R; + object->fsmFxn = ECDSACC26X2_runSignFSM; + object->operationStatus = ECDSACC26X2_STATUS_FSM_RUN_FSM; + object->operationCanceled = false; + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + + /* We want to store the PMSN in a section of PKA RAM that will survive + * several PKA operations. Otherwise we would need to store it in an SRAM + * buffer instead. + */ + CryptoKeyPlaintext_initBlankKey(&object->pmsnKey, (uint8_t *)SCRATCH_BUFFER_0, operation->curve->length); + + /* When using TFM, TRNG is initialized when ECDSA_init is called because + * TRNG power can only be controlled from the NSPE. + */ +#if (TFM_ENABLED == 0) + /* We are calling TRNG_init() here to limit references to TRNG_xyz to sign + * operations. + * That means that the linker can remove all TRNG related code if only + * ECDSA_verify functionality is used. + */ + TRNG_init(); +#endif + + object->trngHwAttrs.intPriority = hwAttrs->trngIntPriority; + object->trngConfig.object = &object->trngObject; + object->trngConfig.hwAttrs = &object->trngHwAttrs; + + trngParams.returnBehavior = TRNG_RETURN_BEHAVIOR_CALLBACK; + trngParams.cryptoKeyCallbackFxn = ECDSACC26X2_trngCallback; + + object->trngHandle = TRNG_construct(&object->trngConfig, &trngParams); + + if (object->trngHandle == NULL) + { + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + return ECDSA_STATUS_ERROR; + } + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + /* Generate the PMSN using the TRNG in callback mode. The TRNG callback + * will kick off the ECDSA sign state machine once the PMSN is in place. + * This is completely transparent to the application. + */ + trngStatus = TRNG_generateEntropy(object->trngHandle, &object->pmsnKey); + + if (trngStatus != TRNG_STATUS_SUCCESS) + { + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + return ECDSA_STATUS_ERROR; + } + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + return ECDSACC26X2_waitForResult(handle); +} + +/* + * ======== ECDSA_verify ======== + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation) +{ + ECDSACC26X2_Object *object = handle->object; + ECDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + object->operation.verify = operation; + object->operationType = ECDSA_OPERATION_TYPE_VERIFY; + object->fsmState = ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE; + object->fsmFxn = ECDSACC26X2_runVerifyFSM; + object->operationStatus = ECDSACC26X2_STATUS_FSM_RUN_FSM; + object->operationCanceled = false; + scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECDSACC26X2_waitForResult(handle); +} + +/* + * ======== ECDSA_cancelOperation ======== + */ +int_fast16_t ECDSA_cancelOperation(ECDSA_Handle handle) +{ + ECDSACC26X2_Object *object = handle->object; + + if (!object->operationInProgress) + { + return ECDSA_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + return ECDSA_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.h b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.h new file mode 100644 index 00000000..9c451a70 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X2.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDSACC26X2.h + * + * @brief ECDSA driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the ECDSA_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input paramter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECDSA: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | No | + * | Edwards | No | + * + * # Public Key Validation # + * + * When performing signature verification, the foreign public key will always be validated. + * However, the implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecdsa_ECDSACC26X2__include +#define ti_drivers_ecdsa_ECDSACC26X2__include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECDSACC26X2_STATUS_FSM_RUN_PKA_OP ECDSA_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECDSACC26X2_STATUS_FSM_RUN_FSM ECDSA_STATUS_RESERVED - 1 + +/*! + * @brief ECDSACC26X2 Sign and Verify states + * + * The sign and verify operations are implemented using multiple invidividual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum +{ + ECDSACC26X2_FSM_ERROR = 0, + + ECDSACC26X2_FSM_SIGN_COMPUTE_R, + ECDSACC26X2_FSM_SIGN_COMPUTE_R_RESULT, + ECDSACC26X2_FSM_SIGN_R_MOD_N, + ECDSACC26X2_FSM_SIGN_R_MOD_N_RESULT, + ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE, + ECDSACC26X2_FSM_SIGN_COMPUTE_PMSN_INVERSE_RESULT, + ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R, + ECDSACC26X2_FSM_SIGN_COMPUTE_PRIVATE_KEY_X_R_RESULT, + ECDSACC26X2_FSM_SIGN_ADD_HASH, + ECDSACC26X2_FSM_SIGN_ADD_HASH_RESULT, + ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE, + ECDSACC26X2_FSM_SIGN_MULT_BY_PMSN_INVERSE_RESULT, + ECDSACC26X2_FSM_SIGN_MOD_N, + ECDSACC26X2_FSM_SIGN_MOD_N_RESULT, + + ECDSACC26X2_FSM_VERIFY_R_S_IN_RANGE, + ECDSACC26X2_FSM_VERIFY_VALIDATE_PUBLIC_KEY, + ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV, + ECDSACC26X2_FSM_VERIFY_COMPUTE_S_INV_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_HASH_RESULT, + ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N, + ECDSACC26X2_FSM_VERIFY_S_INV_MULT_HASH_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_G, + ECDSACC26X2_FSM_VERIFY_MULT_G_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N, + ECDSACC26X2_FSM_VERIFY_MULT_S_INV_R_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY, + ECDSACC26X2_FSM_VERIFY_MULT_PUB_KEY_RESULT, + ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS, + ECDSACC26X2_FSM_VERIFY_ADD_MULT_RESULTS_RESULT, + ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N, + ECDSACC26X2_FSM_VERIFY_POINTX_MOD_N_RESULT, + ECDSACC26X2_FSM_VERIFY_COMPARE_RESULT_R, + +} ECDSACC26X2_FsmState; + +/*! + * @brief ECDSACC26X2 state machine function prototype + * + * The FSM controller in the ECDSACC26X2 SWI executes a state machine function + * containing a switch statement that governs state execution. This function + * pointer is stored in the object at the beginning of the transaction. + * This way, unused state machines are removed at link time. + */ +typedef int_fast16_t (*ECDSACC26X2_stateMachineFxn)(ECDSA_Handle handle); + +/*! + * @brief ECDSACC26X2 Hardware Attributes + * + * ECDSACC26X2 hardware attributes should be included in the board file + * and pointed to by the ECDSA_config struct. + */ +typedef struct +{ + /*! @brief PKA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; + uint8_t trngIntPriority; +} ECDSACC26X2_HWAttrs; + +/*! + * @brief ECDSACC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + TRNG_Config trngConfig; + TRNGCC26XX_Object trngObject; + TRNGCC26XX_HWAttrs trngHwAttrs; + TRNG_Handle trngHandle; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDSA_Operation operation; + ECDSA_OperationType operationType; + ECDSA_CallbackFxn callbackFxn; + ECDSACC26X2_stateMachineFxn fsmFxn; + ECDSA_ReturnBehavior returnBehavior; + ECDSACC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; + uint32_t *scratchNumber1; + uint32_t *scratchNumber2; + CryptoKey pmsnKey; +} ECDSACC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdsa_ECDSACC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.c new file mode 100644 index 00000000..56af1d99 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static volatile bool ECDSACC26X4_ns_pollingDone; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* Extern globals */ +extern const ECDSA_Params ECDSA_defaultParams; +extern ECDSA_s_SecureCallback ecdsaSecureCB_ns[]; +extern ECDSACC26X4_ns_Object ecdsaObject_ns[]; + +/* + * ======== ECDSA_ns_callbackFxn ======== + */ +void ECDSA_ns_callbackFxn(uintptr_t arg) +{ + ECDSA_s_SecureCallback *secureCallbackObject = (ECDSA_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + CryptoPSACC26X4_releaseLock(); + + if (ecdsaObject_ns[index].returnBehavior == ECDSA_RETURN_BEHAVIOR_POLLING) + { + ECDSACC26X4_ns_pollingDone = true; + } + else if (ecdsaObject_ns[index].returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + ecdsaObject_ns[index].callbackFxn(ecdsaSecureCB_ns[index].handle, + ecdsaSecureCB_ns[index].returnStatus, + ecdsaSecureCB_ns[index].operation, + ecdsaSecureCB_ns[index].operationType); + } +} + +/* + * ======== ECDSA_ns_registerCallback ======== + */ +static psa_status_t ECDSA_ns_registerCallback(ECDSA_Handle handle, const ECDSA_Params *params) +{ + ECDSA_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&ecdsaSecureCB_ns[index].object, + ECDSA_ns_callbackFxn, + (uintptr_t)&ecdsaSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &ecdsaSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== ECDSA_ns_waitForResult ======== + */ +static void ECDSA_ns_waitForResult(int_fast16_t *result, uint8_t objectIndex) +{ + if (*result != ECDSA_STATUS_SUCCESS) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (ecdsaObject_ns[objectIndex].returnBehavior == ECDSA_RETURN_BEHAVIOR_POLLING) + { + /* + * Emulate polling mode by spinning on a flag which will be set by + * the callback function + */ + while (!ECDSACC26X4_ns_pollingDone) {} + *result = ecdsaSecureCB_ns[objectIndex].returnStatus; + } + else if (ecdsaObject_ns[objectIndex].returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + *result = ecdsaSecureCB_ns[objectIndex].returnStatus; + } +} + +/* + * ======== ECDSA_init ======== + */ +void ECDSA_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + /* TRNG_init is required to power up the TRNG */ + TRNG_init(); + + isInitialized = true; + } +} + +/* + * ======== ECDSA_open ======== + */ +ECDSA_Handle ECDSA_open(uint_least8_t index, const ECDSA_Params *params) +{ + ECDSA_Handle handle = NULL; + ECDSA_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECDSA_Params *)&ECDSA_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_OPEN, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECDSA_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecdsaObject_ns[index].returnBehavior = params->returnBehavior; + ecdsaObject_ns[index].callbackFxn = params->callbackFxn; + ecdsaObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECDSA_construct ======== + */ +ECDSA_Handle ECDSA_construct(ECDSA_Config *config, const ECDSA_Params *params) +{ + ECDSA_Handle handle = NULL; + ECDSA_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECDSA_Params *)&ECDSA_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECDSA_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecdsaObject_ns[index].returnBehavior = params->returnBehavior; + ecdsaObject_ns[index].callbackFxn = params->callbackFxn; + ecdsaObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECDSA_close ======== + */ +void ECDSA_close(ECDSA_Handle handle) +{ + ECDSA_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&ecdsaSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== ECDSA_sign ======== + */ +int_fast16_t ECDSA_sign(ECDSA_Handle handle, ECDSA_OperationSign *operation) +{ + ECDSA_s_SignMsg signMsg; + int_fast16_t result = ECDSA_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + signMsg.handle = handle; + signMsg.operation = operation; + invecs[0].base = &signMsg; + invecs[0].len = sizeof(signMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(ecdsaObject_ns[index].semaphoreTimeout) == false) + { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + ECDSACC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_SIGN, invecs, outvecs); + + ECDSA_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== ECDSA_verify ======== + */ +int_fast16_t ECDSA_verify(ECDSA_Handle handle, ECDSA_OperationVerify *operation) +{ + ECDSA_s_VerifyMsg verifyMsg; + int_fast16_t result; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(params->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + verifyMsg.handle = handle; + verifyMsg.operation = operation; + invecs[0].base = &verifyMsg; + invecs[0].len = sizeof(verifyMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(ecdsaObject_ns[index].semaphoreTimeout) == false) + { + return ECDSA_STATUS_RESOURCE_UNAVAILABLE; + } + + ECDSACC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_VERIFY, invecs, outvecs); + + ECDSA_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== ECDSA_cancelOperation ======== + */ +int_fast16_t ECDSA_cancelOperation(ECDSA_Handle handle) +{ + ECDSA_s_CancelOperationMsg cancelMsg; + int_fast16_t result = ECDSA_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECDSA_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.h new file mode 100644 index 00000000..335c15be --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECDSACC26X4_ns.h + * + * @brief ECDSA Non-secure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_ecdsa_ECDSACC26X4_ns__include +#define ti_drivers_ecdsa_ECDSACC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief ECDSAC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + ECDSA_CallbackFxn callbackFxn; + ECDSA_ReturnBehavior returnBehavior; +} ECDSACC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdsa_ECDSACC26X4_ns__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.c b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.c new file mode 100644 index 00000000..4ac320b2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.c @@ -0,0 +1,891 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "ECDSACC26X4_s.h" + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include /* TI CMSE helper functions */ + +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +#define ECDSA_SECURE_OPERATION_COUNT ECDSA_SECURE_CALLBACK_COUNT + +/*! + * @brief Union containing all supported operation structs. + */ +typedef union +{ + ECDSA_OperationSign sign; + ECDSA_OperationVerify verify; +} ECDSA_OperationUnion; + +/* + * Stores a secure copy of the operation & key and the original pointer to the + * non-secure operation to return in case of callback return behavior. + */ +typedef struct +{ + ECDSA_Operation operation_ns; /* Pointer to non-secure operation */ + ECDSA_OperationUnion operation_s; /* Secure copy of operation */ + CryptoKey key_s; /* Secure copy of key */ +} ECDSA_s_Operation; + +static ECDSA_s_Operation ECDSA_s_operation; + +/* + * ECDSA Secure Dynamic Instance struct. + */ +typedef struct +{ + ECDSA_Config config; + ECDSACC26X2_Object object; + ECDSACC26X2_HWAttrs hwAttrs; +} ECDSA_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * ECDSA_construct. + */ +static ECDSA_s_DynamicInstance ECDSA_s_dynInstance[CONFIG_ECDSA_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure ECDSA_s_SecureCallbacks for each driver + * instance opened or constructed */ +static ECDSA_s_SecureCallback *ECDSA_s_secureCB[ECDSA_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const ECDSA_Config ECDSA_config[]; + +/* + * ======== ECDSA_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t ECDSA_s_getCallbackIndex(ECDSA_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_ECDSA_COUNT; index++) + { + if (handle_s == (ECDSA_Handle)&ECDSA_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_ECDSA_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &ECDSA_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_ECDSA_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== ECDSA_s_hwiCallback ======== + */ +static void ECDSA_s_hwiCallback(ECDSA_Handle handle_s, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType) +{ + int8_t index; + ECDSA_s_SecureCallback *ecdsaSecureCB_ns; + + index = ECDSA_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < ECDSA_SECURE_CALLBACK_COUNT)) + { + ecdsaSecureCB_ns = ECDSA_s_secureCB[index]; + + if (ecdsaSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler + */ + ecdsaSecureCB_ns->handle = (ECDSA_Handle)(CRYPTO_S_HANDLE_ID_ECDSA | index); + ecdsaSecureCB_ns->returnStatus = returnStatus; + ecdsaSecureCB_ns->operation = ECDSA_s_operation.operation_ns; + ecdsaSecureCB_ns->operationType = operationType; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&ecdsaSecureCB_ns->object); + } + } +} + +/* + * ======== ECDSA_s_copyConfig ======== + */ +static inline psa_status_t ECDSA_s_copyConfig(ECDSA_Config **secureConfig, + const ECDSA_Config *config, + ECDSA_Handle *retHandle) +{ + ECDSA_Config *config_s; + ECDSA_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_ECDSA_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &ECDSA_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECDSA_s_secureCB[i + CONFIG_TI_DRIVERS_ECDSA_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_ECDSA OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (ECDSA_Handle)(CRYPTO_S_HANDLE_ID_ECDSA | (i + CONFIG_TI_DRIVERS_ECDSA_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== ECDSA_s_releaseConfig ======== + */ +static inline void ECDSA_s_releaseConfig(ECDSA_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECDSA) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_ECDSA_COUNT) && (i < ECDSA_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is + * available */ + ECDSA_s_dynInstance[i - CONFIG_TI_DRIVERS_ECDSA_COUNT].config.object = NULL; + } + } +} + +/* + * ======== ECDSA_s_copySignOperation ======== + */ +static inline psa_status_t ECDSA_s_copySignOperation(ECDSA_OperationSign *secureOperation, + CryptoKey *securePrivateKey, + const ECDSA_OperationSign *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECDSA_OperationSign)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECDSA_OperationSign)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate hash address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->hash, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate r component address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->r, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate s component address range */ + if (cmse_has_unpriv_nonsecure_rw_access(secureOperation->s, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the private key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_copyVerifyOperation ======== + */ +static inline psa_status_t ECDSA_s_copyVerifyOperation(ECDSA_OperationVerify *secureOperation, + CryptoKey *securePublicKey, + const ECDSA_OperationVerify *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECDSA_OperationVerify)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECDSA_OperationVerify)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate hash address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->hash, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate r component address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->r, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate s component address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->s, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePublicKey, &secureOperation->theirPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_copyParams ======== + */ +static psa_status_t ECDSA_s_copyParams(ECDSA_Params *secureParams, const ECDSA_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(ECDSA_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(ECDSA_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == ECDSA_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == ECDSA_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == ECDSA_RETURN_BEHAVIOR_POLLING)) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using ECDSA_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = ECDSA_s_hwiCallback; + + /* + * The underlying ECDSA driver is interrupt-driven regardless of the + * return behavior specified. Since secure partitions cannot process + * interrupt signals while a PSA call is running, callback return + * behavior must be forced in all app-specified return behaviors + * including polling. + */ + secureParams->returnBehavior = ECDSA_RETURN_BEHAVIOR_CALLBACK; + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== ECDSA_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static ECDSA_Handle ECDSA_s_getHandle(ECDSA_Handle nsHandle) +{ + ECDSA_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECDSA) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_ECDSA_COUNT) + { + secureHandle = (ECDSA_Handle)&ECDSA_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_ECDSA_COUNT) && (i < ECDSA_SECURE_CALLBACK_COUNT)) + { + secureHandle = &ECDSA_s_dynInstance[i - CONFIG_TI_DRIVERS_ECDSA_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== ECDSA_s_registerCallback ======== + */ +static inline psa_status_t ECDSA_s_registerCallback(psa_msg_t *msg) +{ + ECDSA_Handle handle_s; + ECDSA_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = ECDSA_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = ECDSA_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < ECDSA_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(ECDSA_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to ECDSA_s_SecureCallback located in + * non-secure memory. + */ + ECDSA_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== ECDSA_s_construct ======== + */ +static inline psa_status_t ECDSA_s_construct(psa_msg_t *msg) +{ + ECDSA_s_ConstructMsg constructMsg; + ECDSA_Handle handle; + ECDSA_Params params_s; + const ECDSA_Params *paramsPtr_s = NULL; + ECDSA_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + ECDSA_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = ECDSA_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = ECDSA_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = ECDSA_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is + * available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_open ======== + */ +static inline psa_status_t ECDSA_s_open(psa_msg_t *msg) +{ + ECDSA_s_OpenMsg openMsg; + ECDSA_Handle handle; + ECDSA_Params params_s; + ECDSA_Params *paramsPtr_s = NULL; + ECDSA_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = ECDSA_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = ECDSA_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECDSA_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_ECDSA OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (ECDSA_Handle)(CRYPTO_S_HANDLE_ID_ECDSA | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_close ======== + */ +static inline psa_status_t ECDSA_s_close(psa_msg_t *msg) +{ + ECDSA_Handle handle_s; + ECDSA_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDSA_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ECDSA_close(handle_s); + + /* Release the secure config if it is a dynamic */ + { + ECDSA_s_releaseConfig(closeMsg.handle); + } + } + else /* Secure client */ + { + ECDSA_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_sign ======== + */ +static inline psa_status_t ECDSA_s_sign(psa_msg_t *msg) +{ + ECDSA_s_SignMsg signMsg; + ECDSA_Handle handle_s; + ECDSA_OperationSign *operation_s; + CryptoKey *privateKey_s = &ECDSA_s_operation.key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(signMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &signMsg, sizeof(signMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDSA_s_getHandle(signMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECDSA_s_operation.operation_s.sign; + + /* Save pointer to non-secure operation struct */ + ECDSA_s_operation.operation_ns = (ECDSA_Operation)signMsg.operation; + + /* Validate and copy operation and key structs */ + status = ECDSA_s_copySignOperation(operation_s, privateKey_s, signMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECDSA_sign(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECDSA_sign(signMsg.handle, signMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECDSA_s_verify ======== + */ +static inline psa_status_t ECDSA_s_verify(psa_msg_t *msg) +{ + ECDSA_s_VerifyMsg verifyMsg; + ECDSA_Handle handle_s; + ECDSA_OperationVerify *operation_s; + CryptoKey *publicKey_s = &ECDSA_s_operation.key_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(verifyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &verifyMsg, sizeof(verifyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECDSA_s_getHandle(verifyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECDSA_s_operation.operation_s.verify; + + /* Save pointer to non-secure operation struct */ + ECDSA_s_operation.operation_ns = (ECDSA_Operation)verifyMsg.operation; + + /* Validate and copy operation and key structs */ + status = ECDSA_s_copyVerifyOperation(operation_s, publicKey_s, verifyMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECDSA_verify(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECDSA_verify(verifyMsg.handle, verifyMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECDSA_s_cancelOperation ======== + */ +static inline psa_status_t ECDSA_s_cancelOperation(psa_msg_t *msg) +{ + ECDSA_Handle handle_s; + ECDSA_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = ECDSA_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = ECDSA_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== ECDSA_s_handlePsaMsg ======== + */ +psa_status_t ECDSA_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If ECDSA_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case ECDSA_S_MSG_TYPE_CONSTRUCT: + status = ECDSA_s_construct(msg); + break; + + case ECDSA_S_MSG_TYPE_OPEN: + status = ECDSA_s_open(msg); + break; + + /* + * ECDSA_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case ECDSA_S_MSG_TYPE_REGISTER_CALLBACK: + status = ECDSA_s_registerCallback(msg); + break; + + case ECDSA_S_MSG_TYPE_CLOSE: + status = ECDSA_s_close(msg); + break; + + case ECDSA_S_MSG_TYPE_SIGN: + status = ECDSA_s_sign(msg); + break; + + case ECDSA_S_MSG_TYPE_VERIFY: + status = ECDSA_s_verify(msg); + break; + + /* + * ECDSA_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case ECDSA_S_MSG_TYPE_CANCEL_OPERATION: + status = ECDSA_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== ECDSA_s_init ======== + */ +void ECDSA_s_init(void) +{ + ECDSA_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.h b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.h new file mode 100644 index 00000000..6ab064cd --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecdsa/ECDSACC26X4_s.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_ecdsa_ECDSACC26X4_s__include +#define ti_drivers_ecdsa_ECDSACC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECDSA secure message types + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * ECDSA secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +#define ECDSA_S_MSG_TYPE_CONSTRUCT ECDSA_S_MSG_TYPE(0U) +#define ECDSA_S_MSG_TYPE_OPEN ECDSA_S_MSG_TYPE(1U) +#define ECDSA_S_MSG_TYPE_REGISTER_CALLBACK ECDSA_S_MSG_TYPE(2U) +#define ECDSA_S_MSG_TYPE_CLOSE ECDSA_S_MSG_TYPE(3U) +#define ECDSA_S_MSG_TYPE_SIGN ECDSA_S_MSG_TYPE(4U) +#define ECDSA_S_MSG_TYPE_VERIFY ECDSA_S_MSG_TYPE(5U) +#define ECDSA_S_MSG_TYPE_CANCEL_OPERATION ECDSA_S_MSG_TYPE(6U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using ECDSA_construct(). + */ +#ifndef CONFIG_ECDSA_S_CONFIG_POOL_SIZE + #define CONFIG_ECDSA_S_CONFIG_POOL_SIZE 1 +#endif + +#define ECDSA_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_ECDSA_COUNT + CONFIG_ECDSA_S_CONFIG_POOL_SIZE) + +/* + * ========= ECDSA Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* ECDSA callback fxn parameters */ + ECDSA_Handle handle; + int_fast16_t returnStatus; + ECDSA_Operation operation; + ECDSA_OperationType operationType; +} ECDSA_s_SecureCallback; + +/* + * ========= ECDSA Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * ECDSA secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + ECDSA_Config *config; + const ECDSA_Params *params; +} ECDSA_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const ECDSA_Params *params; +} ECDSA_s_OpenMsg; + +typedef struct +{ + ECDSA_Handle handle; + ECDSA_s_SecureCallback *callback; +} ECDSA_s_CallbackMsg; + +typedef struct +{ + ECDSA_Handle handle; +} ECDSA_s_CloseMsg; + +typedef struct +{ + ECDSA_Handle handle; + ECDSA_OperationSign *operation; +} ECDSA_s_SignMsg; + +typedef struct +{ + ECDSA_Handle handle; + ECDSA_OperationVerify *operation; +} ECDSA_s_VerifyMsg; + +typedef struct +{ + ECDSA_Handle handle; +} ECDSA_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for ECDSA secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t ECDSA_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the ECDSA secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void ECDSA_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecdsa_ECDSACC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.c b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.c new file mode 100644 index 00000000..6b0e108e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.c @@ -0,0 +1,2116 @@ +/* + * Copyright (c) 2017-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_pka.h) +#include DeviceFamily_constructPath(inc/hw_pka_ram.h) +#include DeviceFamily_constructPath(driverlib/pka.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif + + /* + * Max key sizes 521b private keys, + * (521b) * 2 + 1B for octet offset for public keys + */ + #define ECJPAKE_MAX_KEYSTORE_PUBLIC_KEY_SIZE 133 + #define ECJPAKE_MAX_KEYSTORE_PRIVATE_KEY_SIZE 66 +#endif + +#define SCRATCH_BUFFER_0_SIZE 256 + +/* We need several scratch buffers as the private and public keys are provided + * in octet string form and thus the components are big-endian. We need to feed + * the PKA with little-endian integers. That means moving them to some scratch + * memory and reversing them. + * We are storing them in bytes 512 to 512 + 3 x SCRATCH_BUFFER_SIZE. + * Byte 1024 to 1024 + 66 and 1536 to 1536 + 66 are used by the public key + * validation routine in driverlib. + */ +#define SCRATCH_KEY_OFFSET 512 +#define SCRATCH_KEY_SIZE 96 + +#define SCRATCH_PRIVATE_KEY ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET)) +#define SCRATCH_PUBLIC_X ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 1 * SCRATCH_KEY_SIZE)) +#define SCRATCH_PUBLIC_Y ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 2 * SCRATCH_KEY_SIZE)) + +#define SCRATCH_BUFFER_OFFSET 1024 +#define SCRATCH_BUFFER_SIZE 256 + +#define SCRATCH_BUFFER_0 ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 0 * SCRATCH_BUFFER_SIZE)) +#define SCRATCH_BUFFER_2 ((uint32_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 1 * SCRATCH_BUFFER_SIZE)) + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +/* Forward declarations */ +static void ECJPAKECC26X2_hwiFxn(uintptr_t arg0); +#if (TFM_ENABLED == 0) +static void ECJPAKECC26X2_internalCallbackFxn(ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType); +#endif +static int_fast16_t ECJPAKECC26X2_waitForAccess(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_waitForResult(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_runFSM(ECJPAKE_Handle handle); +static int_fast16_t ECJPAKECC26X2_convertReturnValue(uint32_t pkaResult); + +/* Extern globals */ +extern const ECJPAKE_Params ECJPAKE_defaultParams; + +/* Static globals */ +static bool isInitialized = false; + +static uint32_t scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + +#if (ENABLE_KEY_STORAGE == 1) +uint8_t ECJPAKECC26X2_keyStorePrivateKeyMaterial[ECJPAKE_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; +uint8_t ECJPAKECC26X2_keyStorePreSharedSecretMaterial[ECJPAKE_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; +uint8_t ECJPAKECC26X2_keyStorePublicKeyMaterial[ECJPAKE_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +uint8_t ECJPAKECC26X2_keyStoreSharedSecretMaterial[ECJPAKE_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; + +/* + * ======== ECJPAKE_isPersistentLifetime ======== + */ +bool ECJPAKE_isPersistentLifetime(CryptoKey *key) +{ + KeyStore_PSA_KeyAttributes *attributesPtr; + + #if (TFM_ENABLED == 1) + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + attributesPtr = &attributes; + (void)KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *)key->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #else + attributesPtr = (KeyStore_PSA_KeyAttributes *)key->u.keyStore.keyAttributes; + #endif + + if (attributesPtr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) == KEYSTORE_PSA_KEY_LIFETIME_PERSISTENT) + { + return true; + } + else + { + return false; + } +} +#endif + +/* + * ======== ECJPAKE_getPreSharedSecret ======== + */ +int_fast16_t ECJPAKE_getPreSharedSecret(const CryptoKey *preSharedSecret, + uint8_t **preSharedSecretMaterial, + size_t *preSharedSecretLength) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; +#endif + if (preSharedSecret->encoding == CryptoKey_PLAINTEXT) + { + *preSharedSecretMaterial = preSharedSecret->u.plaintext.keyMaterial; + *preSharedSecretLength = preSharedSecret->u.plaintext.keyLength; + status = ECJPAKE_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (preSharedSecret->encoding == CryptoKey_KEYSTORE) + { + memset(ECJPAKECC26X2_keyStorePreSharedSecretMaterial, 0, sizeof(ECJPAKECC26X2_keyStorePreSharedSecretMaterial)); + /* Obtain the private key from keystore */ + GET_KEY_ID(keyID, preSharedSecret->u.keyStore.keyID); + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + ECJPAKECC26X2_keyStorePreSharedSecretMaterial, + sizeof(ECJPAKECC26X2_keyStorePreSharedSecretMaterial), + preSharedSecretLength, + KEYSTORE_PSA_ALG_PAKE, + KEYSTORE_PSA_KEY_USAGE_DERIVE); + if ((keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) || + (*preSharedSecretLength != preSharedSecret->u.keyStore.keyLength)) + { + status = ECJPAKE_STATUS_KEYSTORE_ERROR; + } + else + { + *preSharedSecretMaterial = ECJPAKECC26X2_keyStorePreSharedSecretMaterial; + status = ECJPAKE_STATUS_SUCCESS; + } + } +#endif + else + { + status = ECJPAKE_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECJPAKE_getPrivateKey ======== + */ +int_fast16_t ECJPAKE_getPrivateKey(const CryptoKey *privateKey, uint8_t **privateKeyMaterial, size_t *privateKeyLength) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; +#endif + if (privateKey->encoding == CryptoKey_PLAINTEXT) + { + *privateKeyMaterial = privateKey->u.plaintext.keyMaterial; + *privateKeyLength = privateKey->u.plaintext.keyLength; + status = ECJPAKE_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (privateKey->encoding == CryptoKey_KEYSTORE) + { + memset(ECJPAKECC26X2_keyStorePrivateKeyMaterial, 0, sizeof(ECJPAKECC26X2_keyStorePrivateKeyMaterial)); + /* Obtain the private key from keystore */ + GET_KEY_ID(keyID, privateKey->u.keyStore.keyID); + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + ECJPAKECC26X2_keyStorePrivateKeyMaterial, + sizeof(ECJPAKECC26X2_keyStorePrivateKeyMaterial), + privateKeyLength, + KEYSTORE_PSA_ALG_PAKE, + KEYSTORE_PSA_KEY_USAGE_DERIVE); + if ((keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) || (*privateKeyLength != privateKey->u.keyStore.keyLength)) + { + status = ECJPAKE_STATUS_KEYSTORE_ERROR; + } + else + { + *privateKeyMaterial = ECJPAKECC26X2_keyStorePrivateKeyMaterial; + status = ECJPAKE_STATUS_SUCCESS; + } + } +#endif + else + { + status = ECJPAKE_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECJPAKE_getPublicKey ======== + */ +int_fast16_t ECJPAKE_getPublicKey(const CryptoKey *publicKey, uint8_t **publicKeyMaterial, size_t *publicKeyLength) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; +#endif + if (publicKey->encoding == CryptoKey_PLAINTEXT) + { + *publicKeyMaterial = publicKey->u.plaintext.keyMaterial; + *publicKeyLength = publicKey->u.plaintext.keyLength; + status = ECJPAKE_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (publicKey->encoding == CryptoKey_KEYSTORE) + { + memset(ECJPAKECC26X2_keyStorePublicKeyMaterial, 0, sizeof(ECJPAKECC26X2_keyStorePublicKeyMaterial)); + /* Obtain the public key from keystore */ + GET_KEY_ID(keyID, publicKey->u.keyStore.keyID); + + keyStoreStatus = KeyStore_PSA_getKey(keyID, + ECJPAKECC26X2_keyStorePublicKeyMaterial, + sizeof(ECJPAKECC26X2_keyStorePublicKeyMaterial), + publicKeyLength, + KEYSTORE_PSA_ALG_PAKE, + KEYSTORE_PSA_KEY_USAGE_DERIVE); + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS || (*publicKeyLength != publicKey->u.keyStore.keyLength)) + { + status = ECJPAKE_STATUS_KEYSTORE_ERROR; + } + else + { + *publicKeyMaterial = ECJPAKECC26X2_keyStorePublicKeyMaterial; + status = ECJPAKE_STATUS_SUCCESS; + } + } +#endif + else + { + status = ECJPAKE_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECJPAKE_getSharedSecretBuffer ======== + */ +int_fast16_t ECJPAKE_getSharedSecretBuffer(const CryptoKey *sharedSecret, uint8_t **sharedSecretMaterial) +{ + int_fast16_t status; + if (sharedSecret->encoding == CryptoKey_BLANK_PLAINTEXT) + { + *sharedSecretMaterial = sharedSecret->u.plaintext.keyMaterial; + status = ECJPAKE_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (sharedSecret->encoding == CryptoKey_BLANK_KEYSTORE) + { + *sharedSecretMaterial = ECJPAKECC26X2_keyStoreSharedSecretMaterial; + status = ECJPAKE_STATUS_SUCCESS; + } +#endif + else + { + status = ECJPAKE_STATUS_ERROR; + } + + return status; +} + +/* + * ======== ECJPAKECC26X2_generatePublicKeyStart ======== + */ +int_fast16_t ECJPAKECC26X2_generatePublicKeyStart(const CryptoKey *privateKey, + const ECCParams_CurveParams *curve, + uint32_t *resultAddress) +{ + uint32_t pkaResult; + uint8_t *privateKeyMaterial; + size_t privateKeyLength; + int_fast16_t status; + + status = ECJPAKE_getPrivateKey(privateKey, &privateKeyMaterial, &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + + /* Check if Private Key is all zeros */ + if (PKAArrayAllZeros(privateKeyMaterial, curve->length)) + { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + CryptoUtils_reverseCopyPad(privateKeyMaterial, SCRATCH_PRIVATE_KEY, curve->length); + + /* Check if Private Key is less than order of the curve */ + PKABigNumCmpStart((uint8_t *)SCRATCH_PRIVATE_KEY, curve->order, curve->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + curve->generatorX, + curve->generatorY, + curve->prime, + curve->a, + curve->b, + curve->length, + resultAddress); + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP; +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== ECJPAKECC26X2_importSecureKey ======== + */ +static int_fast16_t ECJPAKECC26X2_importSecureKey(CryptoKey *key, + uint8_t *keyingMaterial, + ECCParams_CurveType curveType) +{ + KeyStore_PSA_KeyFileId keyID; + int_fast16_t status = ECJPAKE_STATUS_KEYSTORE_ERROR; + int_fast16_t keyStoreResult = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + KeyStore_PSA_KeyAttributes *attributesPtr; + #if (TFM_ENABLED == 1) + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + #endif + + /* Copy key identifier from CryptoKey */ + GET_KEY_ID(keyID, key->u.keyStore.keyID); + + #if (TFM_ENABLED == 0) + attributesPtr = (KeyStore_PSA_KeyAttributes *)key->u.keyStore.keyAttributes; + #else + attributesPtr = &attributes; + keyStoreResult = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *) + key->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #endif + keyStoreResult = KeyStore_PSA_importKey(attributesPtr, keyingMaterial, key->u.keyStore.keyLength, &keyID); + + if (keyStoreResult == KEYSTORE_PSA_STATUS_SUCCESS) + { + KeyStore_PSA_initKey(key, keyID, key->u.keyStore.keyLength, attributesPtr); + status = ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + } + else + { + status = ECJPAKE_STATUS_KEYSTORE_ERROR; + } + + return status; +} +#endif + +/* + * ======== ECJPAKECC26X2_getPublicKeyResult ======== + */ +uint32_t ECJPAKECC26X2_getPublicKeyResult(CryptoKey *publicKey, + const ECCParams_CurveParams *curve, + uint32_t resultPKAMemAddr) +{ + uint32_t pkaResult; + uint8_t *keyMaterial; + int_fast16_t status = ECJPAKE_STATUS_KEYSTORE_ERROR; +#if (ENABLE_KEY_STORAGE == 1) + uint8_t publicKeyMaterial[ECJPAKE_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif + + if (publicKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + keyMaterial = publicKey->u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (publicKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + keyMaterial = publicKeyMaterial; + } +#endif + else + { + return ECJPAKE_STATUS_ERROR; + } + + /* Get X and Y coordinates for short Weierstrass curves */ + pkaResult = PKAEccMultiplyGetResult(keyMaterial + OCTET_STRING_OFFSET, + keyMaterial + curve->length + OCTET_STRING_OFFSET, + resultPKAMemAddr, + curve->length); + + /* Set first byte of output public key to 0x04 to indicate x,y + * big-endian coordinates in octet string format + */ + keyMaterial[0] = 0x04; + + /* Byte-reverse integer X coordinate for octet string format */ + CryptoUtils_reverseBufferBytewise(keyMaterial + OCTET_STRING_OFFSET, curve->length); + + /* Byte-reverse integer Y coordinate for octet string format */ + CryptoUtils_reverseBufferBytewise(keyMaterial + curve->length + OCTET_STRING_OFFSET, curve->length); + + status = ECJPAKECC26X2_convertReturnValue(pkaResult); + + if (status == ECJPAKECC26X2_STATUS_FSM_RUN_FSM) + { + if (publicKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + publicKey->encoding = CryptoKey_PLAINTEXT; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (publicKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + status = ECJPAKECC26X2_importSecureKey(publicKey, keyMaterial, curve->curveType); + } +#endif + } + return status; +} + +#if (TFM_ENABLED == 0) +/* + * ======== ECJPAKECC26X2_internalCallbackFxn ======== + */ +static void ECJPAKECC26X2_internalCallbackFxn(ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType) +{ + ECJPAKECC26X2_Object *object = handle->object; + + /* This function is only ever registered when in ECJPAKE_RETURN_BEHAVIOR_BLOCKING + * or ECJPAKE_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else + { + PKAResourceCC26XX_pollingFlag = 1; + } +} +#endif + +/* + * ======== ECJPAKECC26X2_hwiFxn ======== + */ +static void ECJPAKECC26X2_hwiFxn(uintptr_t arg0) +{ + ECJPAKECC26X2_Object *object = ((ECJPAKE_Handle)arg0)->object; + uint32_t key; + + /* Disable interrupt again */ + IntDisable(INT_PKA_IRQ); + + do + { + object->operationStatus = ECJPAKECC26X2_runFSM((ECJPAKE_Handle)arg0); + object->fsmState++; + } while (object->operationStatus == ECJPAKECC26X2_STATUS_FSM_RUN_FSM); + + /* We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if (object->operationCanceled) + { + /* Set function register to 0. This should stop the current operation */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = ECJPAKE_STATUS_CANCELED; + } + + switch (object->operationStatus) + { + case ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* Do nothing. The PKA hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case ECJPAKE_STATUS_SUCCESS: + /* Intentional fall through */ + case ECJPAKE_STATUS_ERROR: + /* Intentional fall through */ + case ECJPAKE_STATUS_CANCELED: + /* Intentional fall through */ + case ECJPAKE_STATUS_KEYSTORE_ERROR: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->callbackFxn((ECJPAKE_Handle)arg0, + object->operationStatus, + object->operation, + object->operationType); + } +} + +/* + * ======== ECJPAKECC26X2_runSignFSM ======== + */ +static int_fast16_t ECJPAKECC26X2_runFSM(ECJPAKE_Handle handle) +{ + static uint32_t resultAddress; + ECJPAKECC26X2_Object *object = handle->object; + uint32_t pkaResult; + + uint8_t *privateKeyMaterial; + size_t privateKeyLength; + uint8_t *publicKeyMaterial; + size_t publicKeyLength; + uint8_t *preSharedSecretMaterial; + size_t preSharedSecretLength; + uint8_t *sharedSecretMaterial; + int_fast16_t status; + + switch (object->fsmState) + { + /* ==================================================================== + * ROUND ONE KEY GENERATION FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1: + + return ECJPAKECC26X2_generatePublicKeyStart(object->operation.generateRoundOneKeys->myPrivateKey1, + object->operation.generateRoundOneKeys->curve, + &resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1_RESULT: + /* Get X and Y coordinates for short Weierstrass curves */ + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundOneKeys->myPublicKey1, + object->operation.generateRoundOneKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2: + + return ECJPAKECC26X2_generatePublicKeyStart(object->operation.generateRoundOneKeys->myPrivateKey2, + object->operation.generateRoundOneKeys->curve, + &resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2_RESULT: + /* Get X and Y coordinates for short Weierstrass curves */ + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundOneKeys->myPublicKey2, + object->operation.generateRoundOneKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1: + + return ECJPAKECC26X2_generatePublicKeyStart(object->operation.generateRoundOneKeys->myPrivateV1, + object->operation.generateRoundOneKeys->curve, + &resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1_RESULT: + /* Get X and Y coordinates for short Weierstrass curves */ + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundOneKeys->myPublicV1, + object->operation.generateRoundOneKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2: + + return ECJPAKECC26X2_generatePublicKeyStart(object->operation.generateRoundOneKeys->myPrivateV2, + object->operation.generateRoundOneKeys->curve, + &resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2_RESULT: + /* Get X and Y coordinates for short Weierstrass curves */ + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundOneKeys->myPublicV2, + object->operation.generateRoundOneKeys->curve, + resultAddress); + + /* ==================================================================== + * GENERATE ZKP FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH: + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + status = ECJPAKE_getPrivateKey(object->operation.generateZKP->myPrivateKey, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.generateZKP->curve->length); + + CryptoUtils_reverseCopyPad(object->operation.generateZKP->hash, + SCRATCH_BUFFER_0, + object->operation.generateZKP->curve->length); + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generateZKP->curve->length, + (uint8_t *)SCRATCH_BUFFER_0, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_RESULT: + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBufferSize, resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateZKP->curve->length > scratchBufferSize) + { + PKAZeroOutArray((uint8_t *)SCRATCH_BUFFER_0 + scratchBufferSize, + object->operation.generateZKP->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + Math_MAX(scratchBufferSize, object->operation.generateZKP->curve->length), + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N: + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + status = ECJPAKE_getPrivateKey(object->operation.generateZKP->myPrivateV, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.generateRoundOneKeys->curve->length); + + PKABigNumAddStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generateZKP->curve->length, + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N_RESULT: + + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + pkaResult = PKABigNumAddGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBufferSize, resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS: + + PKABigNumSubStart((uint8_t *)SCRATCH_BUFFER_0, + scratchBufferSize, + object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS_RESULT: + + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + pkaResult = PKABigNumSubGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBufferSize, resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateZKP->curve->length > scratchBufferSize) + { + PKAZeroOutArray((uint8_t *)SCRATCH_BUFFER_0 + scratchBufferSize, + object->operation.generateZKP->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + Math_MAX(scratchBufferSize, object->operation.generateZKP->curve->length), + object->operation.generateZKP->curve->order, + object->operation.generateZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.generateZKP->r, + object->operation.generateZKP->curve->length, + resultAddress); + + CryptoUtils_reverseBufferBytewise(object->operation.generateZKP->r, + object->operation.generateZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + /* ==================================================================== + * VERIFY ZKP FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY: + + status = ECJPAKE_getPublicKey(object->operation.verifyZKP->theirPublicKey, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.verifyZKP->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verifyZKP->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->length); + + pkaResult = PKAEccVerifyPublicKeyWeierstrassStart((uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->order, + object->operation.verifyZKP->curve->length); + + // Break out early since no PKA operation was started by the verify fxn + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R: + + CryptoUtils_reverseCopyPad(object->operation.verifyZKP->r, + SCRATCH_PRIVATE_KEY, + object->operation.verifyZKP->curve->length); + + /* If the generator was explicitly specified, we need to copy and + * reverse it. + */ + if (object->operation.verifyZKP->theirGenerator != NULL) + { + status = ECJPAKE_getPublicKey(object->operation.verifyZKP->theirGenerator, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.verifyZKP->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verifyZKP->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->length); + + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->length, + &resultAddress); + } + /* Otherwise, we just use the generator of the curve */ + else + { + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.verifyZKP->curve->generatorX, + object->operation.verifyZKP->curve->generatorY, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->length, + &resultAddress); + } + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R_RESULT: + + pkaResult = PKAEccMultiplyGetResult((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N: + + CryptoUtils_reverseCopyPad(object->operation.verifyZKP->hash, + SCRATCH_PRIVATE_KEY, + object->operation.verifyZKP->curve->length); + + PKABigNumModStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->order, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N_RESULT: + + pkaResult = PKABigNumModGetResult((uint8_t *)SCRATCH_BUFFER_2, + object->operation.verifyZKP->curve->length, + resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH: + + status = ECJPAKE_getPublicKey(object->operation.verifyZKP->theirPublicKey, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.verifyZKP->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verifyZKP->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->length); + + PKAEccMultiplyStart((uint8_t *)SCRATCH_BUFFER_2, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->b, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH_RESULT: + + pkaResult = PKAEccMultiplyGetResult((uint8_t *)SCRATCH_BUFFER_2, + (uint8_t *)SCRATCH_BUFFER_2 + + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS: + + PKAEccAddStart((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.verifyZKP->curve->length, + (uint8_t *)SCRATCH_BUFFER_2, + (uint8_t *)SCRATCH_BUFFER_2 + object->operation.verifyZKP->curve->length, + object->operation.verifyZKP->curve->prime, + object->operation.verifyZKP->curve->a, + object->operation.verifyZKP->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS_RESULT: + + pkaResult = PKAEccAddGetResult((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.verifyZKP->curve->length, + resultAddress, + object->operation.verifyZKP->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_VERIFY_ZKP_COMPARE_AGAINST_V: + + status = ECJPAKE_getPublicKey(object->operation.verifyZKP->theirPublicV, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_BUFFER_2, + object->operation.verifyZKP->curve->length); + + /* This requires the implicit assumption that we are using a curve with a word-multiple length. + * The helper function is written with the assumption that the destination is word-aligned. + * In practice, this only affects the NIST-P521 curve that we do not officially support with + * ECJPAKE currently. + */ + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.verifyZKP->curve->length, + (uint32_t *)((uint8_t *)SCRATCH_BUFFER_2 + + object->operation.verifyZKP->curve->length), + object->operation.verifyZKP->curve->length); + + if (CryptoUtils_buffersMatchWordAligned(SCRATCH_BUFFER_2, + SCRATCH_BUFFER_0, + 2 * object->operation.verifyZKP->curve->length)) + { + return ECJPAKE_STATUS_SUCCESS; + } + else + { + return ECJPAKE_STATUS_ERROR; + } + + /* ==================================================================== + * ROUND TWO KEY GENERATION FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET: + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + status = ECJPAKE_getPrivateKey(object->operation.generateRoundTwoKeys->myPrivateKey2, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.generateRoundTwoKeys->curve->length); + + status = ECJPAKE_getPreSharedSecret(object->operation.generateRoundTwoKeys->preSharedSecret, + &preSharedSecretMaterial, + &preSharedSecretLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(preSharedSecretMaterial, SCRATCH_BUFFER_0, preSharedSecretLength); + + PKABigNumMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generateRoundTwoKeys->curve->length, + (uint8_t *)SCRATCH_BUFFER_0, + preSharedSecretLength, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET_RESULT: + + pkaResult = PKABigNumMultGetResult((uint8_t *)SCRATCH_BUFFER_0, &scratchBufferSize, resultAddress); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N: + + /* Zero out the buffer up to the curve length. The PKA hardware cannot + * handle modulus operations where the byte-length of the dividend is smaller + * than the divisor. + */ + if (object->operation.generateRoundTwoKeys->curve->length > scratchBufferSize) + { + PKAZeroOutArray((uint8_t *)SCRATCH_BUFFER_0 + scratchBufferSize, + object->operation.generateRoundTwoKeys->curve->length - scratchBufferSize); + } + + /* The scratch buffer content has a real length of scratchBufferSize but is + * zero-extended until curve->length. We cannot start a modulo operation on + * the PKA where dividend length < divisor length. Hence, the buffer size + * always needs to be >= curve->length. + */ + PKABigNumModStart((uint8_t *)SCRATCH_BUFFER_0, + Math_MAX(scratchBufferSize, object->operation.generateRoundTwoKeys->curve->length), + object->operation.generateRoundTwoKeys->curve->order, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N_RESULT: + + if (object->operation.generateRoundTwoKeys->myCombinedPrivateKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + privateKeyMaterial = object->operation.generateRoundTwoKeys->myCombinedPrivateKey->u.plaintext + .keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->operation.generateRoundTwoKeys->myCombinedPrivateKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + memset(ECJPAKECC26X2_keyStorePrivateKeyMaterial, 0, sizeof(ECJPAKECC26X2_keyStorePrivateKeyMaterial)); + privateKeyMaterial = ECJPAKECC26X2_keyStorePrivateKeyMaterial; + } +#endif + else + { + return ECJPAKE_STATUS_ERROR; + } + pkaResult = PKABigNumModGetResult(privateKeyMaterial, + object->operation.generateRoundTwoKeys->curve->length, + resultAddress); + + /* We just wrote back a little-endian integer. + * We need to turn that output into OS format. + * For a private key, that just means byte-reversing the array. + */ + CryptoUtils_reverseBufferBytewise(privateKeyMaterial, + object->operation.generateRoundTwoKeys->curve->length); + + status = ECJPAKECC26X2_convertReturnValue(pkaResult); + if (status == ECJPAKECC26X2_STATUS_FSM_RUN_FSM) + { + if (object->operation.generateRoundTwoKeys->myCombinedPrivateKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + object->operation.generateRoundTwoKeys->myCombinedPrivateKey->encoding = CryptoKey_PLAINTEXT; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->operation.generateRoundTwoKeys->myCombinedPrivateKey->encoding == + CryptoKey_BLANK_KEYSTORE) + { + status = ECJPAKECC26X2_importSecureKey(object->operation.generateRoundTwoKeys->myCombinedPrivateKey, + privateKeyMaterial, + object->operation.generateRoundTwoKeys->curve->curveType); + } +#endif + } + return status; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1: + + /* Copy myPublicKey1 into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->myPublicKey1, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->length); + + /* Copy theirPublicKey1 into SCRATCH_BUFFER_0 in little-endian form. + * There is the implicit assumption that the curve length is a + * word-multiple here. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->theirPublicKey1, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_BUFFER_0, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + (uint32_t *)((uint8_t *)SCRATCH_BUFFER_0 + + object->operation.generateRoundTwoKeys->curve->length), + object->operation.generateRoundTwoKeys->curve->length); + + PKAEccAddStart((uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + (uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.generateRoundTwoKeys->curve->length, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1_RESULT: + + pkaResult = PKAEccAddGetResult((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + + object->operation.generateRoundTwoKeys->curve->length, + resultAddress, + object->operation.generateRoundTwoKeys->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2: + + /* Copy theirPublicKey2 into the public key scratch area in little-endian + * form. The ECC coordinates resulting from the previous operation + * should still be in SCRATCH_BUFFER_0. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->theirPublicKey2, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->length); + + PKAEccAddStart((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.generateRoundTwoKeys->curve->length, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2_RESULT: + + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundTwoKeys->myNewGenerator, + object->operation.generateRoundTwoKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2: + + /* Copy myPublicKey2 into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->myPublicKey2, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->length); + + PKAEccAddStart((uint8_t *)SCRATCH_BUFFER_0, + (uint8_t *)SCRATCH_BUFFER_0 + object->operation.generateRoundTwoKeys->curve->length, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2_RESULT: + + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundTwoKeys->theirNewGenerator, + object->operation.generateRoundTwoKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR: + + /* Copy myCombinedPrivateKey into the private key scratch area in + * little-endian form. + */ + status = ECJPAKE_getPrivateKey(object->operation.generateRoundTwoKeys->myCombinedPrivateKey, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.generateRoundTwoKeys->curve->length); + + /* Copy myNewGenerator into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->myNewGenerator, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->length); + + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->b, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR_RESULT: + + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundTwoKeys->myCombinedPublicKey, + object->operation.generateRoundTwoKeys->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV: + + status = ECJPAKE_getPrivateKey(object->operation.generateRoundTwoKeys->myPrivateV, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + + if (PKAArrayAllZeros(privateKeyMaterial, object->operation.generateRoundTwoKeys->curve->length)) + { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.generateRoundTwoKeys->curve->length); + + /* Copy myNewGenerator into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPublicKey(object->operation.generateRoundTwoKeys->myNewGenerator, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.generateRoundTwoKeys->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.generateRoundTwoKeys->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->length); + + PKABigNumCmpStart((uint8_t *)SCRATCH_PRIVATE_KEY, + object->operation.generateRoundTwoKeys->curve->order, + object->operation.generateRoundTwoKeys->curve->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) {} + + pkaResult = PKABigNumCmpGetResult(); + + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + return ECJPAKE_STATUS_INVALID_PRIVATE_KEY; + } + + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.generateRoundTwoKeys->curve->prime, + object->operation.generateRoundTwoKeys->curve->a, + object->operation.generateRoundTwoKeys->curve->b, + object->operation.generateRoundTwoKeys->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV_RESULT: + + return ECJPAKECC26X2_getPublicKeyResult(object->operation.generateRoundTwoKeys->myPublicV, + object->operation.generateRoundTwoKeys->curve, + resultAddress); + + /* ==================================================================== + * GENERATE SHARED SECRET FSM STATE IMPLEMENTATIONS + * ==================================================================== + */ + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY: + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + /* Copy myCombinedPrivateKey into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPrivateKey(object->operation.computeSharedSecret->myCombinedPrivateKey, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.computeSharedSecret->curve->length); + + status = ECJPAKE_getPublicKey(object->operation.computeSharedSecret->theirPublicKey2, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.computeSharedSecret->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.computeSharedSecret->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->length); + + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY_RESULT: + + /* While we are copying back an EC point to sharedSecret, we are + * only using it as temp storage. As such, we can let it remain + * in little-endian form. + */ + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + pkaResult = PKAEccMultiplyGetResult(sharedSecretMaterial, + sharedSecretMaterial + + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME: + + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + PKABigNumSubStart(object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->length, + sharedSecretMaterial + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME_RESULT: + + /* Use scratchBufferSize as a dummy length variable since we will not copy the + * result into the SCRATCH_BUFFER_0 + */ + scratchBufferSize = object->operation.computeSharedSecret->curve->length; + + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + pkaResult = PKABigNumSubGetResult(sharedSecretMaterial + + object->operation.computeSharedSecret->curve->length, + &scratchBufferSize, + resultAddress); + + /* Zero out the private key buffer up to the curve length. Otherwise, we may + * have rubbish floating around the buffer instead of being zero sign-extended. + */ + if (object->operation.computeSharedSecret->curve->length > scratchBufferSize) + { + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + PKAZeroOutArray(sharedSecretMaterial + object->operation.computeSharedSecret->curve->length + + scratchBufferSize, + object->operation.computeSharedSecret->curve->length - scratchBufferSize); + } + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY: + + /* Copy theirCombinedPublicKey into the public key scratch area in little-endian + * form. + */ + status = ECJPAKE_getPublicKey(object->operation.computeSharedSecret->theirCombinedPublicKey, + &publicKeyMaterial, + &publicKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET, + SCRATCH_PUBLIC_X, + object->operation.computeSharedSecret->curve->length); + + CryptoUtils_reverseCopyPad(publicKeyMaterial + OCTET_STRING_OFFSET + + object->operation.computeSharedSecret->curve->length, + SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->length); + + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + PKAEccAddStart(sharedSecretMaterial, + sharedSecretMaterial + object->operation.computeSharedSecret->curve->length, + (uint8_t *)SCRATCH_PUBLIC_X, + (uint8_t *)SCRATCH_PUBLIC_Y, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY_RESULT: + + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + pkaResult = PKAEccAddGetResult(sharedSecretMaterial, + sharedSecretMaterial + object->operation.computeSharedSecret->curve->length, + resultAddress, + object->operation.computeSharedSecret->curve->length); + + return ECJPAKECC26X2_convertReturnValue(pkaResult); + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2: + + /* Since we are receiving the private and public keys in octet string format, + * we need to convert them to little-endian form for use with the PKA + */ + status = ECJPAKE_getPrivateKey(object->operation.computeSharedSecret->myPrivateKey2, + &privateKeyMaterial, + &privateKeyLength); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + CryptoUtils_reverseCopyPad(privateKeyMaterial, + SCRATCH_PRIVATE_KEY, + object->operation.computeSharedSecret->curve->length); + + status = ECJPAKE_getSharedSecretBuffer(object->operation.computeSharedSecret->sharedSecret, + &sharedSecretMaterial); + if (status != ECJPAKE_STATUS_SUCCESS) + { + return status; + } + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + sharedSecretMaterial, + sharedSecretMaterial + object->operation.computeSharedSecret->curve->length, + object->operation.computeSharedSecret->curve->prime, + object->operation.computeSharedSecret->curve->a, + object->operation.computeSharedSecret->curve->b, + object->operation.computeSharedSecret->curve->length, + &resultAddress); + + break; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2_RESULT: + return ECJPAKECC26X2_getPublicKeyResult(object->operation.computeSharedSecret->sharedSecret, + object->operation.computeSharedSecret->curve, + resultAddress); + + case ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_RETURN: + return ECJPAKE_STATUS_SUCCESS; + + case ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_RETURN: + return ECJPAKE_STATUS_SUCCESS; + + case ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_RETURN: + return ECJPAKE_STATUS_SUCCESS; + + case ECJPAKECC26X2_FSM_ZKP_GENERATE_RETURN: + return ECJPAKE_STATUS_SUCCESS; + default: + return ECJPAKE_STATUS_ERROR; + } + + // If we get to this point, we want to perform another PKA operation + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP; +} + +/* + * ======== ECJPAKECC26X2_convertReturnValue ======== + */ +static int_fast16_t ECJPAKECC26X2_convertReturnValue(uint32_t pkaResult) +{ + switch (pkaResult) + { + case PKA_STATUS_SUCCESS: + case PKA_STATUS_A_LESS_THAN_B: + case PKA_STATUS_EQUAL: + /* A less than B and equal only come up when checking private + * key values. They indicate a key within the correct range. + */ + return ECJPAKECC26X2_STATUS_FSM_RUN_FSM; + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return ECJPAKE_STATUS_POINT_AT_INFINITY; + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + return ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME; + + case PKA_STATUS_POINT_NOT_ON_CURVE: + return ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE; + + default: + return ECJPAKE_STATUS_ERROR; + } +} + +/* + * ======== ECJPAKECC26X2_waitForAccess ======== + */ +static int_fast16_t ECJPAKECC26X2_waitForAccess(ECJPAKE_Handle handle) +{ + ECJPAKECC26X2_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout + : SemaphoreP_NO_WAIT; + + return SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout); +} + +/* + * ======== ECJPAKECC26X2_waitForResult ======== + */ +static int_fast16_t ECJPAKECC26X2_waitForResult(ECJPAKE_Handle handle) +{ + ECJPAKECC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) + { + case ECJPAKE_RETURN_BEHAVIOR_POLLING: + while (!PKAResourceCC26XX_pollingFlag) {} + return object->operationStatus; + + case ECJPAKE_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return object->operationStatus; + + case ECJPAKE_RETURN_BEHAVIOR_CALLBACK: + return ECJPAKE_STATUS_SUCCESS; + + default: + return ECJPAKE_STATUS_ERROR; + } +} + +/* + * ======== ECJPAKE_init ======== + */ +void ECJPAKE_init(void) +{ + PKAResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== ECJPAKE_construct ======== + */ +ECJPAKE_Handle ECJPAKE_construct(ECJPAKE_Config *config, const ECJPAKE_Params *params) +{ + ECJPAKE_Handle handle; + ECJPAKECC26X2_Object *object; + uint_fast8_t key; + + handle = (ECJPAKE_Handle)config; + object = handle->object; + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (ECJPAKE_Params *)&ECJPAKE_defaultParams; + } + + key = HwiP_disable(); + + if (!isInitialized || object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; +#if (TFM_ENABLED == 1) + /* Always use the secure callback function */ + object->callbackFxn = params->callbackFxn; +#else + object->callbackFxn = (params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK) + ? params->callbackFxn + : ECJPAKECC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; +#endif + + /* Set power dependency - i.e. power up and enable clock for PKA (PKAResourceCC26XX) module. */ + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return handle; +} + +/* + * ======== ECJPAKE_close ======== + */ +void ECJPAKE_close(ECJPAKE_Handle handle) +{ + ECJPAKECC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Release power dependency on PKA Module. */ + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== ECJPAKE_roundOneGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundOneGenerateKeys *operation) +{ + bool isKeyBlank; + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + (void)CryptoKey_isBlank(operation->myPublicKey1, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myPublicKey2, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myPublicV1, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myPublicV2, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateRoundOneKeys = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_ROUND_ONE_GENERATE_KEYS; + object->operationCanceled = false; + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_generateZKP ======== + */ +int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP *operation) +{ + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateZKP = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_GENERATE_ZKP; + object->operationCanceled = false; + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_verifyZKP ======== + */ +int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP *operation) +{ + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.verifyZKP = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_VERIFY_ZKP; + object->operationCanceled = false; + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_roundTwoGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundTwoGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundTwoGenerateKeys *operation) +{ + bool isKeyBlank; + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Ignore return since CryptoKey_isBlank always returns success */ + (void)CryptoKey_isBlank(operation->theirNewGenerator, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myNewGenerator, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myCombinedPrivateKey, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myCombinedPublicKey, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + (void)CryptoKey_isBlank(operation->myPublicV, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.generateRoundTwoKeys = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_ROUND_TWO_GENERATE_KEYS; + object->operationCanceled = false; + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_computeSharedSecret ======== + */ +int_fast16_t ECJPAKE_computeSharedSecret(ECJPAKE_Handle handle, ECJPAKE_OperationComputeSharedSecret *operation) +{ + bool isKeyBlank; + ECJPAKECC26X2_Object *object = handle->object; + ECJPAKECC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Ignore return since CryptoKey_isBlank always returns success */ + (void)CryptoKey_isBlank(operation->sharedSecret, &isKeyBlank); + if (!isKeyBlank) + { + return ECJPAKE_STATUS_OUTPUT_KEY_NOT_BLANK; + } + + if (ECJPAKECC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->fsmState = ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY; + object->operationStatus = ECJPAKE_STATUS_ERROR; + object->operation.computeSharedSecret = operation; + object->operationType = ECJPAKE_OPERATION_TYPE_COMPUTE_SHARED_SECRET; + object->operationCanceled = false; + scratchBufferSize = SCRATCH_BUFFER_0_SIZE; + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, ECJPAKECC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return ECJPAKECC26X2_waitForResult(handle); +} + +/* + * ======== ECJPAKE_cancelOperation ======== + */ +int_fast16_t ECJPAKE_cancelOperation(ECJPAKE_Handle handle) +{ + ECJPAKECC26X2_Object *object = handle->object; + + if (!object->operationInProgress) + { + return ECJPAKE_STATUS_ERROR; + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + return ECJPAKE_STATUS_SUCCESS; +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.h b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.h new file mode 100644 index 00000000..45ea86a7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X2.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECJPAKECC26X2.h + * + * @brief ECJPAKE driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the ECJPAKE_config + * struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC point addition, doubling, + * and scalar multiplication. Only one operation can be carried out on the accelerator + * at a time. Mutual exclusion is implemented at the driver level and coordinated + * between all drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM (PKA RAM) for its operations. + * The operands of the maths operations must be copied into and results out of the PKA ram. + * This necessitates a significant number of reads and writes for each operation. + * The bus interface to the RAM only allows for word-aligned reads and writes. The CPU splits + * the reads and writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as plaintext CryptoKey + * keying material to ECC APIs that are word-aligned will significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input parameters. + * Only values that are likely to have a stochastic element to them are checked (such + * as whether a driver is already open). Higher input parameter validation coverage is + * achieved by turning on assertions when compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curve types for ECJPAKE: + * + * | Curve Type | Supported | + * |-------------------|-----------| + * | Short Weierstrass | Yes | + * | Montgomery | No | + * | Edwards | No | + * + * # Public Key Validation # + * + * When performing Schnorr-ZKP verification, the foreign public key will always be validated. + * The public V is validated implicitly during the operation. + * The implementation assumes that the cofactor, h, of the curve is 1. This lets us + * skip the computationally expensive step of multiplying the foreign key by the order and + * checking if it yields the point at infinity. When the cofactor is 1, this property is + * implied by validating that the point is not already the point at infinity and that it + * validates against the curve equation. + * All curves supplied by default, the NIST and Brainpool curves, have cofactor = 1. While + * the implementation can use arbitrary curves, you should verify that any other curve used + * has a cofactor of 1. + */ + +#ifndef ti_drivers_ecjpake_ECJPAKECC26X2__include +#define ti_drivers_ecjpake_ECJPAKECC26X2__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP ECJPAKE_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define ECJPAKECC26X2_STATUS_FSM_RUN_FSM ECJPAKE_STATUS_RESERVED - 1 + +/*! + * @brief ECJPAKECC26X2 states + * + * The EC-JPAKE operations are implemented using multiple individual + * PKA operations. Since state transitions for these operations are almost + * always predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the state counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum +{ + ECJPAKECC26X2_FSM_ERROR = 0, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY1_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV1_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_MYPUBLICV2_RESULT, + ECJPAKECC26X2_FSM_ROUND_ONE_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_PRIVATEKEY_X_HASH_MOD_N_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_ADD_V_TO_N_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULTS_RESULT, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N, + ECJPAKECC26X2_FSM_GENERATE_ZKP_SUBTRACT_RESULT_MOD_N_RESULT, + ECJPAKECC26X2_FSM_ZKP_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_VERIFY_ZKP_VALIDATE_PUBLIC_KEY, + ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N, + ECJPAKECC26X2_FSM_VERIFY_ZKP_HASH_MOD_N_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_G_BY_R_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH, + ECJPAKECC26X2_FSM_VERIFY_ZKP_MULT_X_BY_HASH_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS, + ECJPAKECC26X2_FSM_VERIFY_ZKP_ADD_RESULTS_RESULT, + ECJPAKECC26X2_FSM_VERIFY_ZKP_COMPARE_AGAINST_V, + + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYPRIVATEKEY2_BY_PRESHAREDSECRET_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N, + ECJPAKECC26X2_FSM_ROUND_TWO_MYCOMBINEDPRIVATEKEY_MOD_N_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY1_TO_THEIRPUBLICKEY1_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_THEIRPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2, + ECJPAKECC26X2_FSM_ROUND_TWO_ADD_MYPUBLICKEY2_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR, + ECJPAKECC26X2_FSM_ROUND_TWO_MULT_MYCOMBINEDPRIVATEKEY_BY_MYNEWGENERATOR_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_MYPUBLICV_RESULT, + ECJPAKECC26X2_FSM_ROUND_TWO_GENERATE_RETURN, + + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_THEIRPUBLICKEY2_BY_MYCOMBINEDPRIVATEKEY_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_SUB_YCOORDINATE_FROM_PRIME_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_ADD_THEIRCOMBINEDPUBLICKEY_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_MULT_BY_MYPRIVATEKEY2_RESULT, + ECJPAKECC26X2_FSM_GENERATE_SHARED_SECRET_RETURN, + +} ECJPAKECC26X2_FsmState; + +/*! + * @brief ECJPAKECC26X2 Hardware Attributes + * + * ECJPAKECC26X2 hardware attributes should be included in the board file + * and pointed to by the ECJPAKE_config struct. + */ +typedef struct +{ + /*! @brief PKA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; +} ECJPAKECC26X2_HWAttrs; + +/*! + * @brief ECJPAKECC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECJPAKE_CallbackFxn callbackFxn; + ECJPAKE_ReturnBehavior returnBehavior; + ECJPAKECC26X2_FsmState fsmState; + ECJPAKE_Operation operation; + ECJPAKE_OperationType operationType; + uint32_t semaphoreTimeout; + uint32_t resultAddress; +} ECJPAKECC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecjpake_ECJPAKECC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.c new file mode 100644 index 00000000..4d15974f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.c @@ -0,0 +1,454 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static volatile bool ECJPAKECC26X4_ns_pollingDone; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* Extern globals */ +extern const ECJPAKE_Params ECJPAKE_defaultParams; +extern ECJPAKE_s_SecureCallback ecjpakeSecureCB_ns[]; +extern ECJPAKECC26X4_ns_Object ecjpakeObject_ns[]; + +/* Forward declarations */ +static int_fast16_t ECJPAKE_ns_operation(ECJPAKE_Handle handle, ECJPAKE_Operation operation, int32_t msgType); +static psa_status_t ECJPAKE_ns_registerCallback(ECJPAKE_Handle handle, const ECJPAKE_Params *params); + +/* + * ======== ECJPAKE_ns_callbackFxn ======== + */ +void ECJPAKE_ns_callbackFxn(uintptr_t arg) +{ + ECJPAKE_s_SecureCallback *secureCallbackObject = (ECJPAKE_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + CryptoPSACC26X4_releaseLock(); + + if (ecjpakeObject_ns[index].returnBehavior == ECJPAKE_RETURN_BEHAVIOR_POLLING) + { + ECJPAKECC26X4_ns_pollingDone = true; + } + else if (ecjpakeObject_ns[index].returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + ecjpakeObject_ns[index].callbackFxn(ecjpakeSecureCB_ns[index].handle, + ecjpakeSecureCB_ns[index].returnStatus, + ecjpakeSecureCB_ns[index].operation, + ecjpakeSecureCB_ns[index].operationType); + } +} + +/* + * ======== ECJPAKE_ns_registerCallback ======== + */ +static psa_status_t ECJPAKE_ns_registerCallback(ECJPAKE_Handle handle, const ECJPAKE_Params *params) +{ + ECJPAKE_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&ecjpakeSecureCB_ns[index].object, + ECJPAKE_ns_callbackFxn, + (uintptr_t)&ecjpakeSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &ecjpakeSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(ECJPAKE_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== ECJPAKE_ns_waitForResult ======== + */ +static void ECJPAKE_ns_waitForResult(int_fast16_t *result, uint8_t objectIndex) +{ + if (*result != ECJPAKE_STATUS_SUCCESS) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (ecjpakeObject_ns[objectIndex].returnBehavior == ECJPAKE_RETURN_BEHAVIOR_POLLING) + { + /* + * Emulate polling mode by spinning on a flag which will be set by + * the callback function + */ + while (!ECJPAKECC26X4_ns_pollingDone) {} + *result = ecjpakeSecureCB_ns[objectIndex].returnStatus; + } + else if (ecjpakeObject_ns[objectIndex].returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + *result = ecjpakeSecureCB_ns[objectIndex].returnStatus; + } +} + +/* + * ======== ECJPAKE_init ======== + */ +void ECJPAKE_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== ECJPAKE_open ======== + */ +ECJPAKE_Handle ECJPAKE_open(uint_least8_t index, const ECJPAKE_Params *params) +{ + ECJPAKE_Handle handle = NULL; + ECJPAKE_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECJPAKE_Params *)&ECJPAKE_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECJPAKE_S_MSG_TYPE_OPEN, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECJPAKE_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecjpakeObject_ns[index].returnBehavior = params->returnBehavior; + ecjpakeObject_ns[index].callbackFxn = params->callbackFxn; + ecjpakeObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECJPAKE_construct ======== + */ +ECJPAKE_Handle ECJPAKE_construct(ECJPAKE_Config *config, const ECJPAKE_Params *params) +{ + ECJPAKE_Handle handle = NULL; + ECJPAKE_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (ECJPAKE_Params *)&ECJPAKE_defaultParams; + } + + DebugP_assert(params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECJPAKE_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (ECJPAKE_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + ecjpakeObject_ns[index].returnBehavior = params->returnBehavior; + ecjpakeObject_ns[index].callbackFxn = params->callbackFxn; + ecjpakeObject_ns[index].semaphoreTimeout = (params->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + } + + return handle; +} + +/* + * ======== ECJPAKE_close ======== + */ +void ECJPAKE_close(ECJPAKE_Handle handle) +{ + ECJPAKE_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&ecjpakeSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(ECJPAKE_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== ECJPAKE_ns_operation ======== + */ +static int_fast16_t ECJPAKE_ns_operation(ECJPAKE_Handle handle, ECJPAKE_Operation operation, int32_t msgType) +{ + ECJPAKE_s_OperationMsg msg; + int_fast16_t result = ECJPAKE_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + DebugP_assert(operation); + + /* Setup interface for input parameters */ + msg.handle = handle; + msg.operation = operation; + invecs[0].base = &msg; + invecs[0].len = sizeof(msg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(ecjpakeObject_ns[index].semaphoreTimeout) == false) + { + return ECJPAKE_STATUS_RESOURCE_UNAVAILABLE; + } + + ECJPAKECC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECJPAKE_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(msgType, invecs, outvecs); + + ECJPAKE_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== ECJPAKE_roundOneGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundOneGenerateKeys *operation) +{ + return ECJPAKE_ns_operation(handle, (ECJPAKE_Operation)operation, ECJPAKE_S_MSG_TYPE_ROUND_ONE_GENERATE_KEYS); +} + +/* + * ======== ECJPAKE_generateZKP ======== + */ +int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP *operation) +{ + return ECJPAKE_ns_operation(handle, (ECJPAKE_Operation)operation, ECJPAKE_S_MSG_TYPE_GENERATE_ZKP); +} + +/* + * ======== ECJPAKE_verifyZKP ======== + */ +int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP *operation) +{ + return ECJPAKE_ns_operation(handle, (ECJPAKE_Operation)operation, ECJPAKE_S_MSG_TYPE_VERIFY_ZKP); +} + +/* + * ======== ECJPAKE_roundTwoGenerateKeys ======== + */ +int_fast16_t ECJPAKE_roundTwoGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_OperationRoundTwoGenerateKeys *operation) +{ + return ECJPAKE_ns_operation(handle, (ECJPAKE_Operation)operation, ECJPAKE_S_MSG_TYPE_ROUND_TWO_GENERATE_KEYS); +} + +/* + * ======== ECJPAKE_computeSharedSecret ======== + */ +int_fast16_t ECJPAKE_computeSharedSecret(ECJPAKE_Handle handle, ECJPAKE_OperationComputeSharedSecret *operation) +{ + return ECJPAKE_ns_operation(handle, (ECJPAKE_Operation)operation, ECJPAKE_S_MSG_TYPE_COMPUTE_SHARED_SECRET); +} + +/* + * ======== ECJPAKE_cancelOperation ======== + */ +int_fast16_t ECJPAKE_cancelOperation(ECJPAKE_Handle handle) +{ + ECJPAKE_s_CancelOperationMsg cancelMsg; + int_fast16_t result = ECJPAKE_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to ECJPAKE_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(ECJPAKE_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.h new file mode 100644 index 00000000..69f83a5b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file ECJPAKECC26X4_ns.h + * + * @brief ECJPAKE Non-secure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_ecjpake_ECJPAKECC26X4_ns__include +#define ti_drivers_ecjpake_ECJPAKECC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief ECJPAKECC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + ECJPAKE_CallbackFxn callbackFxn; + ECJPAKE_ReturnBehavior returnBehavior; +} ECJPAKECC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecjpake_ECJPAKECC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.c b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.c new file mode 100644 index 00000000..9e307bba --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.c @@ -0,0 +1,1535 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "ECJPAKECC26X4_s.h" + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +#define ECJPAKE_SECURE_OPERATION_COUNT ECJPAKE_SECURE_CALLBACK_COUNT + +/* + * Union containing all supported ECJPAKE operation structs. + */ +typedef union +{ + ECJPAKE_OperationRoundOneGenerateKeys generateRoundOneKeys; + ECJPAKE_OperationGenerateZKP generateZKP; + ECJPAKE_OperationVerifyZKP verifyZKP; + ECJPAKE_OperationRoundTwoGenerateKeys generateRoundTwoKeys; + ECJPAKE_OperationComputeSharedSecret computeSharedSecret; +} ECJPAKE_OperationUnion; + +/* + * Struct containing secure copy of all crypto keys for round one generation and + * the original pointers to the non-secure output keys to update the key + * encoding return when the HWI callback occurs. + */ +typedef struct +{ + CryptoKey myPrivateKey1; + CryptoKey myPrivateKey2; + CryptoKey myPublicKey1; + CryptoKey myPublicKey2; + CryptoKey myPrivateV1; + CryptoKey myPrivateV2; + CryptoKey myPublicV1; + CryptoKey myPublicV2; + + CryptoKey *myPublicKey1_ns; + CryptoKey *myPublicKey2_ns; + CryptoKey *myPublicV1_ns; + CryptoKey *myPublicV2_ns; +} ECJPAKE_s_RoundOneCryptoKeys; + +/* + * Struct containing secure copy of all crypto keys for ZKP generation. + */ +typedef struct +{ + CryptoKey myPrivateKey; + CryptoKey myPrivateV; +} ECJPAKE_s_GenerateZKPKeys; + +/* + * Struct containing secure copy of all crypto keys for ZKP verification. + */ +typedef struct +{ + CryptoKey theirGenerator; + CryptoKey theirPublicKey; + CryptoKey theirPublicV; +} ECJPAKE_s_VerifyZKPKeys; + +/* + * Struct containing secure copy of all crypto keys for round two generation and + * the original pointers to the non-secure output keys to update the key + * encoding return when the HWI callback occurs. + */ +typedef struct +{ + CryptoKey myPrivateKey2; + CryptoKey myPublicKey1; + CryptoKey myPublicKey2; + CryptoKey theirPublicKey1; + CryptoKey theirPublicKey2; + CryptoKey preSharedSecret; + + CryptoKey theirNewGenerator; + CryptoKey myNewGenerator; + CryptoKey myCombinedPrivateKey; + CryptoKey myCombinedPublicKey; + CryptoKey myPrivateV; + CryptoKey myPublicV; + + CryptoKey *theirNewGenerator_ns; + CryptoKey *myNewGenerator_ns; + CryptoKey *myCombinedPrivateKey_ns; + CryptoKey *myCombinedPublicKey_ns; + CryptoKey *myPublicV_ns; +} ECJPAKE_s_RoundTwoCryptoKeys; + +/* + * Struct containing secure copy of all crypto keys for shared secret + * computation and the original pointer to the non-secure output key to update + * the key encoding return when the HWI callback occurs. + */ +typedef struct +{ + CryptoKey myCombinedPrivateKey; + CryptoKey theirCombinedPublicKey; + CryptoKey theirPublicKey2; + CryptoKey myPrivateKey2; + CryptoKey sharedSecret; + CryptoKey *sharedSecret_ns; +} ECJPAKE_s_SharedSecretCryptoKeys; + +/* + * A union of secure crypto keys structs for all supported operations. + */ +typedef union +{ + ECJPAKE_s_RoundOneCryptoKeys roundOneKeys; + ECJPAKE_s_GenerateZKPKeys generateZKPKeys; + ECJPAKE_s_VerifyZKPKeys verifyZKPKeys; + ECJPAKE_s_RoundTwoCryptoKeys roundTwoKeys; + ECJPAKE_s_SharedSecretCryptoKeys sharedSecretKeys; +} ECJPAKE_s_CryptoKeys; + +/* + * Stores the following: + * - Secure copy of the operation and the original pointer to the non-secure + * operation to return when the HWI callback occurs. + * - Secure copy of the crypto keys and the original pointer to the non-secure + * output keys to update the key encoding return when the HWI callback occurs. + */ +typedef struct +{ + ECJPAKE_Operation operation_ns; /* Pointer to non-secure operation */ + ECJPAKE_OperationUnion operation_s; /* Secure copy of operation */ + ECJPAKE_s_CryptoKeys keys_s; +} ECJPAKE_s_Operation; + +static ECJPAKE_s_Operation ECJPAKE_s_operation; + +/* + * ECJPAKE Secure Dynamic Instance struct. + */ +typedef struct +{ + ECJPAKE_Config config; + ECJPAKECC26X2_Object object; + ECJPAKECC26X2_HWAttrs hwAttrs; +} ECJPAKE_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * ECJPAKE_construct. + */ +static ECJPAKE_s_DynamicInstance ECJPAKE_s_dynInstance[CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE]; + +/* + * Stores pointers to non-secure ECJPAKE_s_SecureCallbacks for each driver + * instance opened or constructed. + */ +static ECJPAKE_s_SecureCallback *ECJPAKE_s_secureCB[ECJPAKE_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const ECJPAKE_Config ECJPAKE_config[]; + +/* + * ======== ECJPAKE_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t ECJPAKE_s_getCallbackIndex(ECJPAKE_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_ECJPAKE_COUNT; index++) + { + if (handle_s == (ECJPAKE_Handle)&ECJPAKE_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &ECJPAKE_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_ECJPAKE_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== ECJPAKE_s_handleRoundOneKeyResult ======== + */ +static void ECJPAKE_s_handleRoundOneKeyResult(ECJPAKE_OperationRoundOneGenerateKeys *opKeys_s) +{ + ECJPAKE_s_RoundOneCryptoKeys *roundOneKeys_s = &ECJPAKE_s_operation.keys_s.roundOneKeys; + + /* Copy updated key encodings to non-secure CryptoKey structs */ + roundOneKeys_s->myPublicKey1_ns->encoding = opKeys_s->myPublicKey1->encoding; + roundOneKeys_s->myPublicKey2_ns->encoding = opKeys_s->myPublicKey2->encoding; + roundOneKeys_s->myPublicV1_ns->encoding = opKeys_s->myPublicV1->encoding; + roundOneKeys_s->myPublicV2_ns->encoding = opKeys_s->myPublicV2->encoding; + + /* For any keystore CryptoKeys, copy updated KeyIDs to non-secure CryptoKey structs */ + if (roundOneKeys_s->myPublicKey1_ns->encoding == CryptoKey_KEYSTORE) + { + roundOneKeys_s->myPublicKey1_ns->u.keyStore.keyID = opKeys_s->myPublicKey1->u.keyStore.keyID; + } + + if (roundOneKeys_s->myPublicKey2_ns->encoding == CryptoKey_KEYSTORE) + { + roundOneKeys_s->myPublicKey2_ns->u.keyStore.keyID = opKeys_s->myPublicKey2->u.keyStore.keyID; + } + + if (roundOneKeys_s->myPublicV1_ns->encoding == CryptoKey_KEYSTORE) + { + roundOneKeys_s->myPublicV1_ns->u.keyStore.keyID = opKeys_s->myPublicV1->u.keyStore.keyID; + } + + if (roundOneKeys_s->myPublicV2_ns->encoding == CryptoKey_KEYSTORE) + { + roundOneKeys_s->myPublicV2_ns->u.keyStore.keyID = opKeys_s->myPublicV2->u.keyStore.keyID; + } +} + +/* + * ======== ECJPAKE_s_handleRoundTwoKeyResult ======== + */ +static void ECJPAKE_s_handleRoundTwoKeyResult(ECJPAKE_OperationRoundTwoGenerateKeys *opKeys_s) +{ + ECJPAKE_s_RoundTwoCryptoKeys *roundTwoKeys_s = &ECJPAKE_s_operation.keys_s.roundTwoKeys; + + /* Copy updated key encodings to non-secure CryptoKey structs */ + roundTwoKeys_s->theirNewGenerator_ns->encoding = opKeys_s->theirNewGenerator->encoding; + roundTwoKeys_s->myNewGenerator_ns->encoding = opKeys_s->myNewGenerator->encoding; + roundTwoKeys_s->myCombinedPrivateKey_ns->encoding = opKeys_s->myCombinedPrivateKey->encoding; + roundTwoKeys_s->myCombinedPublicKey_ns->encoding = opKeys_s->myCombinedPublicKey->encoding; + roundTwoKeys_s->myPublicV_ns->encoding = opKeys_s->myPublicV->encoding; + + /* For any keystore CryptoKeys, copy updated KeyIDs to non-secure CryptoKey structs */ + if (roundTwoKeys_s->theirNewGenerator_ns->encoding == CryptoKey_KEYSTORE) + { + roundTwoKeys_s->theirNewGenerator_ns->u.keyStore.keyID = opKeys_s->theirNewGenerator->u.keyStore.keyID; + } + + if (roundTwoKeys_s->myNewGenerator_ns->encoding == CryptoKey_KEYSTORE) + { + roundTwoKeys_s->myNewGenerator_ns->u.keyStore.keyID = opKeys_s->myNewGenerator->u.keyStore.keyID; + } + + if (roundTwoKeys_s->myCombinedPrivateKey_ns->encoding == CryptoKey_KEYSTORE) + { + roundTwoKeys_s->myCombinedPrivateKey_ns->u.keyStore.keyID = opKeys_s->myCombinedPrivateKey->u.keyStore.keyID; + } + + if (roundTwoKeys_s->myCombinedPublicKey_ns->encoding == CryptoKey_KEYSTORE) + { + roundTwoKeys_s->myCombinedPublicKey_ns->u.keyStore.keyID = opKeys_s->myCombinedPublicKey->u.keyStore.keyID; + } + + if (roundTwoKeys_s->myPublicV_ns->encoding == CryptoKey_KEYSTORE) + { + roundTwoKeys_s->myPublicV_ns->u.keyStore.keyID = opKeys_s->myPublicV->u.keyStore.keyID; + } +} + +/* + * ======== ECJPAKE_s_hwiCallback ======== + */ +static void ECJPAKE_s_hwiCallback(ECJPAKE_Handle handle_s, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType) +{ + int8_t index; + ECJPAKE_s_SecureCallback *ecjpakeSecureCB_ns; + + index = ECJPAKE_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < ECJPAKE_SECURE_CALLBACK_COUNT)) + { + ecjpakeSecureCB_ns = ECJPAKE_s_secureCB[index]; + + if (ecjpakeSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + ecjpakeSecureCB_ns->handle = (ECJPAKE_Handle)(CRYPTO_S_HANDLE_ID_ECJPAKE | index); + ecjpakeSecureCB_ns->returnStatus = returnStatus; + ecjpakeSecureCB_ns->operation = ECJPAKE_s_operation.operation_ns; + ecjpakeSecureCB_ns->operationType = operationType; + + /* Copy updated key encoding to the non-secure key struct */ + if (operationType == ECJPAKE_OPERATION_TYPE_ROUND_ONE_GENERATE_KEYS) + { + ECJPAKE_s_handleRoundOneKeyResult(operation.generateRoundOneKeys); + } + else if (operationType == ECJPAKE_OPERATION_TYPE_ROUND_TWO_GENERATE_KEYS) + { + ECJPAKE_s_handleRoundTwoKeyResult(operation.generateRoundTwoKeys); + } + else if (operationType == ECJPAKE_OPERATION_TYPE_COMPUTE_SHARED_SECRET) + { + ECJPAKE_s_SharedSecretCryptoKeys *sharedSecretKeys_s = &ECJPAKE_s_operation.keys_s.sharedSecretKeys; + + /* Copy updated key encoding to non-secure CryptoKey struct */ + sharedSecretKeys_s->sharedSecret_ns->encoding = operation.computeSharedSecret->sharedSecret->encoding; + + if (sharedSecretKeys_s->sharedSecret_ns->encoding == CryptoKey_KEYSTORE) + { + /* Copy updated KeyID to non-secure CryptoKey struct */ + sharedSecretKeys_s->sharedSecret_ns->u.keyStore.keyID = operation.computeSharedSecret->sharedSecret + ->u.keyStore.keyID; + } + } + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&ecjpakeSecureCB_ns->object); + } + } +} + +/* + * ======== ECJPAKE_s_copyConfig ======== + */ +static inline psa_status_t ECJPAKE_s_copyConfig(ECJPAKE_Config **secureConfig, + const ECJPAKE_Config *config, + ECJPAKE_Handle *retHandle) +{ + ECJPAKE_Config *config_s; + ECJPAKE_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &ECJPAKE_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECJPAKE_s_secureCB[i + CONFIG_TI_DRIVERS_ECJPAKE_COUNT] = NULL; + + /* Return handle is the CRYPTO_S_HANDLE_ID_ECJPAKE OR'd with the + * the config pool array index plus the size of constant config + * array created by SysConfig. + */ + *retHandle = (ECJPAKE_Handle)(CRYPTO_S_HANDLE_ID_ECJPAKE | (i + CONFIG_TI_DRIVERS_ECJPAKE_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== ECJPAKE_s_releaseConfig ======== + */ +static inline void ECJPAKE_s_releaseConfig(ECJPAKE_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECJPAKE) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_ECJPAKE_COUNT) && (i < ECJPAKE_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + ECJPAKE_s_dynInstance[i - CONFIG_TI_DRIVERS_ECJPAKE_COUNT].config.object = NULL; + } + } +} + +/* + * ======== ECJPAKE_s_copyRoundOneGenKeyOp ======== + */ +static inline psa_status_t ECJPAKE_s_copyRoundOneGenKeyOp(ECJPAKE_OperationRoundOneGenerateKeys *secureOperation, + ECJPAKE_s_RoundOneCryptoKeys *secureKeys, + const ECJPAKE_OperationRoundOneGenerateKeys *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECJPAKE_OperationRoundOneGenerateKeys)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECJPAKE_OperationRoundOneGenerateKeys)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Make a secure copy of all key structs and update the operation struct to + * point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateKey1, &secureOperation->myPrivateKey1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateKey2, &secureOperation->myPrivateKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myPublicKey1, &secureOperation->myPublicKey1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myPublicKey2, &secureOperation->myPublicKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateV1, &secureOperation->myPrivateV1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateV2, &secureOperation->myPrivateV2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myPublicV1, &secureOperation->myPublicV1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myPublicV2, &secureOperation->myPublicV2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_copyGenerateOperation ======== + */ +static inline psa_status_t ECJPAKE_s_copyGenerateZKPOperation(ECJPAKE_OperationGenerateZKP *secureOperation, + ECJPAKE_s_GenerateZKPKeys *secureKeys, + const ECJPAKE_OperationGenerateZKP *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECJPAKE_OperationGenerateZKP)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECJPAKE_OperationGenerateZKP)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate input hash address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->hash, secureOperation->curve->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate output 'r' component address range */ + if (cmse_has_unpriv_nonsecure_read_access(secureOperation->r, secureOperation->curve->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of all key structs and update the operation struct to + * point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateV, &secureOperation->myPrivateV); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_copyVerifyOperation ======== + */ +static inline psa_status_t ECJPAKE_s_copyVerifyZKPOperation(ECJPAKE_OperationVerifyZKP *secureOperation, + ECJPAKE_s_VerifyZKPKeys *secureKeys, + const ECJPAKE_OperationVerifyZKP *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECJPAKE_OperationVerifyZKP)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECJPAKE_OperationVerifyZKP)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate input hash address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->hash, secureOperation->curve->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate input 'r' component address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->r, secureOperation->curve->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of all key structs and update the operation struct to + * point to the secure key copy. + */ + + /* theirGenerator may be NULL in which case default generator point from + * the curve is used and there is no crypto key to copy. + */ + if (secureOperation->theirGenerator != NULL) + { + status = CryptoKey_copySecureInputKey(&secureKeys->theirGenerator, &secureOperation->theirGenerator); + if (status != PSA_SUCCESS) + { + return status; + } + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirPublicKey, &secureOperation->theirPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirPublicV, &secureOperation->theirPublicV); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_copyRoundTwoGenKeyOp ======== + */ +static inline psa_status_t ECJPAKE_s_copyRoundTwoGenKeyOp(ECJPAKE_OperationRoundTwoGenerateKeys *secureOperation, + ECJPAKE_s_RoundTwoCryptoKeys *secureKeys, + const ECJPAKE_OperationRoundTwoGenerateKeys *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECJPAKE_OperationRoundTwoGenerateKeys)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECJPAKE_OperationRoundTwoGenerateKeys)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Make a secure copy of all key structs and update the operation struct to + * point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateKey2, &secureOperation->myPrivateKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPublicKey1, &secureOperation->myPublicKey1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPublicKey2, &secureOperation->myPublicKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirPublicKey1, &secureOperation->theirPublicKey1); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirPublicKey2, &secureOperation->theirPublicKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->preSharedSecret, &secureOperation->preSharedSecret); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->theirNewGenerator, &secureOperation->theirNewGenerator); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myNewGenerator, &secureOperation->myNewGenerator); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myCombinedPrivateKey, &secureOperation->myCombinedPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myCombinedPublicKey, &secureOperation->myCombinedPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateV, &secureOperation->myPrivateV); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->myPublicV, &secureOperation->myPublicV); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_copySharedSecretOp ======== + */ +static inline psa_status_t ECJPAKE_s_copyComputeSharedSecretOp(ECJPAKE_OperationComputeSharedSecret *secureOperation, + ECJPAKE_s_SharedSecretCryptoKeys *secureKeys, + const ECJPAKE_OperationComputeSharedSecret *operation) +{ + const ECCParams_CurveParams *curveParams_s; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(ECJPAKE_OperationComputeSharedSecret)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(ECJPAKE_OperationComputeSharedSecret)); + + /* Get a pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Make a secure copy of all key structs and update the operation struct to + * point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(&secureKeys->myCombinedPrivateKey, &secureOperation->myCombinedPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirCombinedPublicKey, + &secureOperation->theirCombinedPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->theirPublicKey2, &secureOperation->theirPublicKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureInputKey(&secureKeys->myPrivateKey2, &secureOperation->myPrivateKey2); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + status = CryptoKey_copySecureOutputKey(&secureKeys->sharedSecret, &secureOperation->sharedSecret); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_copyParams ======== + */ +static psa_status_t ECJPAKE_s_copyParams(ECJPAKE_Params *secureParams, const ECJPAKE_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(ECJPAKE_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(ECJPAKE_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == ECJPAKE_RETURN_BEHAVIOR_POLLING)) + { + /* Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using ECJPAKE_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = ECJPAKE_s_hwiCallback; + + /* The underlying ECJPAKE driver is interrupt-driven regardless of the return + * behavior specified. Since secure partitions cannot process interrupt + * signals while a PSA call is running, callback return behavior must be + * forced for all app-specified return behaviors including polling. + */ + secureParams->returnBehavior = ECJPAKE_RETURN_BEHAVIOR_CALLBACK; + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== ECJPAKE_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static ECJPAKE_Handle ECJPAKE_s_getHandle(ECJPAKE_Handle nsHandle) +{ + ECJPAKE_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_ECJPAKE) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_ECJPAKE_COUNT) + { + secureHandle = (ECJPAKE_Handle)&ECJPAKE_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_ECJPAKE_COUNT) && (i < ECJPAKE_SECURE_CALLBACK_COUNT)) + { + secureHandle = &ECJPAKE_s_dynInstance[i - CONFIG_TI_DRIVERS_ECJPAKE_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== ECJPAKE_s_registerCallback ======== + */ +static inline psa_status_t ECJPAKE_s_registerCallback(psa_msg_t *msg) +{ + ECJPAKE_Handle handle_s; + ECJPAKE_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = ECJPAKE_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = ECJPAKE_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < ECJPAKE_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(ECJPAKE_s_SecureCallback)) != NULL)) + { + /* Store the pointer to ECJPAKE_s_SecureCallback located in + * non-secure memory. + */ + ECJPAKE_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== ECJPAKE_s_construct ======== + */ +static inline psa_status_t ECJPAKE_s_construct(psa_msg_t *msg) +{ + ECJPAKE_s_ConstructMsg constructMsg; + ECJPAKE_Handle handle; + ECJPAKE_Params params_s; + const ECJPAKE_Params *paramsPtr_s = NULL; + ECJPAKE_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + ECJPAKE_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = ECJPAKE_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = ECJPAKE_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = ECJPAKE_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_open ======== + */ +static inline psa_status_t ECJPAKE_s_open(psa_msg_t *msg) +{ + ECJPAKE_s_OpenMsg openMsg; + ECJPAKE_Handle handle; + ECJPAKE_Params params_s; + ECJPAKE_Params *paramsPtr_s = NULL; + ECJPAKE_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = ECJPAKE_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = ECJPAKE_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + ECJPAKE_s_secureCB[openMsg.index] = NULL; + + /* Return CRYPTO_S_HANDLE_ID_ECJPAKE OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (ECJPAKE_Handle)(CRYPTO_S_HANDLE_ID_ECJPAKE | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_close ======== + */ +static inline psa_status_t ECJPAKE_s_close(psa_msg_t *msg) +{ + ECJPAKE_Handle handle_s; + ECJPAKE_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ECJPAKE_close(handle_s); + + /* Release the secure config if it is a dynamic */ + { + ECJPAKE_s_releaseConfig(closeMsg.handle); + } + } + else /* Secure client */ + { + ECJPAKE_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_roundOneGenerateKeys ======== + */ +static inline psa_status_t ECJPAKE_s_roundOneGenerateKeys(psa_msg_t *msg) +{ + ECJPAKE_s_OperationMsg genKeysMsg; + ECJPAKE_Handle handle_s; + ECJPAKE_OperationRoundOneGenerateKeys *operation_s; + ECJPAKE_OperationRoundOneGenerateKeys *operation_ns; + ECJPAKE_s_RoundOneCryptoKeys *keys_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genKeysMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genKeysMsg, sizeof(genKeysMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(genKeysMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECJPAKE_s_operation.operation_s.generateRoundOneKeys; + keys_s = &ECJPAKE_s_operation.keys_s.roundOneKeys; + + operation_ns = genKeysMsg.operation.generateRoundOneKeys; + + /* Save pointer to non-secure operation struct */ + ECJPAKE_s_operation.operation_ns = genKeysMsg.operation; + + /* Save pointers to NS output crypto keys */ + keys_s->myPublicKey1_ns = operation_ns->myPublicKey1; + keys_s->myPublicKey2_ns = operation_ns->myPublicKey2; + keys_s->myPublicV1_ns = operation_ns->myPublicV1; + keys_s->myPublicV2_ns = operation_ns->myPublicV2; + + /* Validate and copy operation and key structs */ + status = ECJPAKE_s_copyRoundOneGenKeyOp(operation_s, keys_s, operation_ns); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECJPAKE_roundOneGenerateKeys(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECJPAKE_roundOneGenerateKeys(genKeysMsg.handle, genKeysMsg.operation.generateRoundOneKeys); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECJPAKE_s_generateZKP ======== + */ +static inline psa_status_t ECJPAKE_s_generateZKP(psa_msg_t *msg) +{ + ECJPAKE_s_OperationMsg genZKPMsg; + ECJPAKE_Handle handle_s; + ECJPAKE_OperationGenerateZKP *operation_s; + ECJPAKE_s_GenerateZKPKeys *keys_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genZKPMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genZKPMsg, sizeof(genZKPMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(genZKPMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECJPAKE_s_operation.operation_s.generateZKP; + keys_s = &ECJPAKE_s_operation.keys_s.generateZKPKeys; + + /* Save pointer to non-secure operation struct */ + ECJPAKE_s_operation.operation_ns = genZKPMsg.operation; + + /* Validate and copy operation and key structs */ + status = ECJPAKE_s_copyGenerateZKPOperation(operation_s, keys_s, genZKPMsg.operation.generateZKP); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECJPAKE_generateZKP(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECJPAKE_generateZKP(genZKPMsg.handle, genZKPMsg.operation.generateZKP); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECJPAKE_s_verifyZKP ======== + */ +static inline psa_status_t ECJPAKE_s_verifyZKP(psa_msg_t *msg) +{ + ECJPAKE_s_OperationMsg verifyKeysMsg; + ECJPAKE_Handle handle_s; + ECJPAKE_OperationVerifyZKP *operation_s; + ECJPAKE_s_VerifyZKPKeys *keys_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(verifyKeysMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &verifyKeysMsg, sizeof(verifyKeysMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(verifyKeysMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECJPAKE_s_operation.operation_s.verifyZKP; + keys_s = &ECJPAKE_s_operation.keys_s.verifyZKPKeys; + + /* Save pointer to non-secure operation struct */ + ECJPAKE_s_operation.operation_ns = verifyKeysMsg.operation; + + /* Validate and copy operation and key structs */ + status = ECJPAKE_s_copyVerifyZKPOperation(operation_s, keys_s, verifyKeysMsg.operation.verifyZKP); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECJPAKE_verifyZKP(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECJPAKE_verifyZKP(verifyKeysMsg.handle, verifyKeysMsg.operation.verifyZKP); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECJPAKE_s_roundTwoGenerateKeys ======== + */ +static inline psa_status_t ECJPAKE_s_roundTwoGenerateKeys(psa_msg_t *msg) +{ + ECJPAKE_s_OperationMsg genKeysMsg; + ECJPAKE_Handle handle_s; + ECJPAKE_OperationRoundTwoGenerateKeys *operation_s; + ECJPAKE_OperationRoundTwoGenerateKeys *operation_ns; + ECJPAKE_s_RoundTwoCryptoKeys *keys_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genKeysMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genKeysMsg, sizeof(genKeysMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(genKeysMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECJPAKE_s_operation.operation_s.generateRoundTwoKeys; + keys_s = &ECJPAKE_s_operation.keys_s.roundTwoKeys; + + operation_ns = genKeysMsg.operation.generateRoundTwoKeys; + + /* Save pointer to non-secure operation struct */ + ECJPAKE_s_operation.operation_ns = genKeysMsg.operation; + + /* Save pointers to NS output crypto keys */ + keys_s->theirNewGenerator_ns = operation_ns->theirNewGenerator; + keys_s->myNewGenerator_ns = operation_ns->myNewGenerator; + keys_s->myCombinedPrivateKey_ns = operation_ns->myCombinedPrivateKey; + keys_s->myCombinedPublicKey_ns = operation_ns->myCombinedPublicKey; + keys_s->myPublicV_ns = operation_ns->myPublicV; + + /* Validate and copy operation and key structs */ + status = ECJPAKE_s_copyRoundTwoGenKeyOp(operation_s, keys_s, operation_ns); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECJPAKE_roundTwoGenerateKeys(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECJPAKE_roundTwoGenerateKeys(genKeysMsg.handle, genKeysMsg.operation.generateRoundTwoKeys); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECJPAKE_s_computeSharedSecret ======== + */ +static inline psa_status_t ECJPAKE_s_computeSharedSecret(psa_msg_t *msg) +{ + ECJPAKE_s_OperationMsg sharedSecretMsg; + ECJPAKE_Handle handle_s; + ECJPAKE_OperationComputeSharedSecret *operation_s; + ECJPAKE_s_SharedSecretCryptoKeys *keys_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(sharedSecretMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &sharedSecretMsg, sizeof(sharedSecretMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = ECJPAKE_s_getHandle(sharedSecretMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &ECJPAKE_s_operation.operation_s.computeSharedSecret; + keys_s = &ECJPAKE_s_operation.keys_s.sharedSecretKeys; + + /* Save pointer to non-secure operation struct */ + ECJPAKE_s_operation.operation_ns = sharedSecretMsg.operation; + + /* Save pointer to NS output crypto key */ + keys_s->sharedSecret_ns = sharedSecretMsg.operation.computeSharedSecret->sharedSecret; + + /* Validate and copy operation and key structs */ + status = ECJPAKE_s_copyComputeSharedSecretOp(operation_s, + keys_s, + sharedSecretMsg.operation.computeSharedSecret); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = ECJPAKE_computeSharedSecret(handle_s, operation_s); + } + else /* Secure client */ + { + ret = ECJPAKE_computeSharedSecret(sharedSecretMsg.handle, sharedSecretMsg.operation.computeSharedSecret); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== ECJPAKE_s_cancelOperation ======== + */ +static inline psa_status_t ECJPAKE_s_cancelOperation(psa_msg_t *msg) +{ + ECJPAKE_Handle handle_s; + ECJPAKE_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = ECJPAKE_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = ECJPAKE_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== ECJPAKE_s_handlePsaMsg ======== + */ +psa_status_t ECJPAKE_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* If ECJPAKE_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case ECJPAKE_S_MSG_TYPE_CONSTRUCT: + status = ECJPAKE_s_construct(msg); + break; + + case ECJPAKE_S_MSG_TYPE_OPEN: + status = ECJPAKE_s_open(msg); + break; + + /* ECJPAKE_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case ECJPAKE_S_MSG_TYPE_REGISTER_CALLBACK: + status = ECJPAKE_s_registerCallback(msg); + break; + + case ECJPAKE_S_MSG_TYPE_CLOSE: + status = ECJPAKE_s_close(msg); + break; + + case ECJPAKE_S_MSG_TYPE_ROUND_ONE_GENERATE_KEYS: + status = ECJPAKE_s_roundOneGenerateKeys(msg); + break; + + case ECJPAKE_S_MSG_TYPE_GENERATE_ZKP: + status = ECJPAKE_s_generateZKP(msg); + break; + + case ECJPAKE_S_MSG_TYPE_VERIFY_ZKP: + status = ECJPAKE_s_verifyZKP(msg); + break; + + case ECJPAKE_S_MSG_TYPE_ROUND_TWO_GENERATE_KEYS: + status = ECJPAKE_s_roundTwoGenerateKeys(msg); + break; + + case ECJPAKE_S_MSG_TYPE_COMPUTE_SHARED_SECRET: + status = ECJPAKE_s_computeSharedSecret(msg); + break; + + /* ECJPAKE_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case ECJPAKE_S_MSG_TYPE_CANCEL_OPERATION: + status = ECJPAKE_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== ECJPAKE_s_init ======== + */ +void ECJPAKE_s_init(void) +{ + ECJPAKE_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.h b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.h new file mode 100644 index 00000000..0ee3f5e4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/ecjpake/ECJPAKECC26X4_s.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_ecjpake_ECJPAKECC26X4_s__include +#define ti_drivers_ecjpake_ECJPAKECC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ECJPAKE secure message types + */ +#define ECJPAKE_S_MSG_TYPE_CONSTRUCT ECJPAKE_S_MSG_TYPE(0U) +#define ECJPAKE_S_MSG_TYPE_OPEN ECJPAKE_S_MSG_TYPE(1U) +#define ECJPAKE_S_MSG_TYPE_REGISTER_CALLBACK ECJPAKE_S_MSG_TYPE(2U) +#define ECJPAKE_S_MSG_TYPE_CLOSE ECJPAKE_S_MSG_TYPE(3U) +#define ECJPAKE_S_MSG_TYPE_ROUND_ONE_GENERATE_KEYS ECJPAKE_S_MSG_TYPE(4U) +#define ECJPAKE_S_MSG_TYPE_GENERATE_ZKP ECJPAKE_S_MSG_TYPE(5U) +#define ECJPAKE_S_MSG_TYPE_VERIFY_ZKP ECJPAKE_S_MSG_TYPE(6U) +#define ECJPAKE_S_MSG_TYPE_ROUND_TWO_GENERATE_KEYS ECJPAKE_S_MSG_TYPE(7U) +#define ECJPAKE_S_MSG_TYPE_COMPUTE_SHARED_SECRET ECJPAKE_S_MSG_TYPE(8U) +#define ECJPAKE_S_MSG_TYPE_CANCEL_OPERATION ECJPAKE_S_MSG_TYPE(9U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using ECJPAKE_construct(). + */ +#ifndef CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE + #define CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE 1 +#endif + +#define ECJPAKE_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_ECJPAKE_COUNT + CONFIG_ECJPAKE_S_CONFIG_POOL_SIZE) + +/* + * ========= ECJPAKE Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* ECJPAKE callback fxn parameters */ + ECJPAKE_Handle handle; + int_fast16_t returnStatus; + ECJPAKE_Operation operation; + ECJPAKE_OperationType operationType; +} ECJPAKE_s_SecureCallback; + +/* + * ========= ECJPAKE Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * ECJPAKE secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + ECJPAKE_Config *config; + const ECJPAKE_Params *params; +} ECJPAKE_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const ECJPAKE_Params *params; +} ECJPAKE_s_OpenMsg; + +typedef struct +{ + ECJPAKE_Handle handle; + ECJPAKE_s_SecureCallback *callback; +} ECJPAKE_s_CallbackMsg; + +typedef struct +{ + ECJPAKE_Handle handle; +} ECJPAKE_s_CloseMsg; + +/* + * Message struct for the following message types: + * - ECJPAKE_S_MSG_TYPE_ROUND_ONE_GENERATE_KEYS + * - ECJPAKE_S_MSG_TYPE_GENERATE_ZKP + * - ECJPAKE_S_MSG_TYPE_VERIFY_ZKP + * - ECJPAKE_S_MSG_TYPE_ROUND_TWO_GENERATE_KEYS + * - ECJPAKE_S_MSG_TYPE_COMPUTE_SHARED_SECRET + */ +typedef struct +{ + ECJPAKE_Handle handle; + ECJPAKE_Operation operation; +} ECJPAKE_s_OperationMsg; + +typedef struct +{ + ECJPAKE_Handle handle; +} ECJPAKE_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for ECJPAKE secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t ECJPAKE_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the ECJPAKE secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void ECJPAKE_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_ecjpake_ECJPAKECC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.c b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.c new file mode 100644 index 00000000..fe3a4f2b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.c @@ -0,0 +1,3027 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== EDDSACC26X2.c ======== + * + * This file contains the CC26X2 implementation of EdDSA + * + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_pka.h) +#include DeviceFamily_constructPath(inc/hw_pka_ram.h) +#include DeviceFamily_constructPath(driverlib/pka.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#include +#include +#include + +#if (ENABLE_KEY_STORAGE == 1) + #include + #include + #if (TFM_ENABLED == 1) + #include + #endif + + /* + * Since EDDSA driver only supports Curve 25519 curves on CC26X2 + * Max key sizes 256b private keys, + * 256b for public keys as montgomery keys are all in little-endian + */ + #define EDDSA_MAX_KEYSTORE_PUBLIC_KEY_SIZE 32 + #define EDDSA_MAX_KEYSTORE_PRIVATE_KEY_SIZE 32 + +uint8_t EDDSACC26X2_keyStorePrivateKeyMaterial[EDDSA_MAX_KEYSTORE_PRIVATE_KEY_SIZE]; +uint8_t EDDSACC26X2_keyStorePublicKeyMaterial[EDDSA_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif + +/* Operations types supported by EDDSACC26X2 driver */ +typedef enum +{ + EDDSACC26X2_OPTYPE_INVALID = 0, + EDDSACC26X2_OPTYPE_SIGN = 1, + EDDSACC26X2_OPTYPE_VERIFY = 2, + EDDSACC26X2_OPTYPE_DERIVE = 3 +} EDDSACC26X2_OperationType; + +/* Octet string format requires an extra byte at the start of the public key */ +#define OCTET_STRING_OFFSET 1 + +#define SCRATCH_KEY_OFFSET 512 +#define SCRATCH_KEY_SIZE 96 +#define SCRATCH_PRIVATE_KEY ((uint32_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET)) +#define SCRATCH_PUBLIC_X ((uint8_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 1 * SCRATCH_KEY_SIZE)) +#define SCRATCH_PUBLIC_Y ((uint8_t *)(PKA_RAM_BASE + SCRATCH_KEY_OFFSET + 2 * SCRATCH_KEY_SIZE)) + +#define SCRATCH_BUFFER_OFFSET 1024 +#define SCRATCH_BUFFER_SIZE 256 +#define SCRATCH_BUFFER_0 ((uint8_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 0 * SCRATCH_BUFFER_SIZE)) +#define SCRATCH_BUFFER_1 ((uint8_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 1 * SCRATCH_BUFFER_SIZE)) +#define SCRATCH_BUFFER_2 ((uint8_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 2 * SCRATCH_BUFFER_SIZE)) +#define SCRATCH_BUFFER_3 ((uint8_t *)(PKA_RAM_BASE + SCRATCH_BUFFER_OFFSET + 3 * SCRATCH_BUFFER_SIZE)) + +/* Forward declarations */ +static void EDDSACC26X2_hwiFxn(uintptr_t arg0); +#if (TFM_ENABLED == 0) +static void EDDSACC26X2_internalCallbackFxn(EDDSA_Handle handle, + int_fast16_t returnStatus, + EDDSA_Operation operation, + EDDSA_OperationType operationType); +#endif +static int_fast16_t EDDSACC26X2_waitForAccess(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_waitForResult(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_storePublicKey(EDDSA_Handle handle, + const uint8_t *xCoordinate, + const uint8_t *yCoordinate); +static int_fast16_t EDDSACC26X2_encodePublicKey(EDDSA_Handle handle, + uint8_t *outputKey, + const uint8_t *xCoordinate, + const uint8_t *yCoordinate); +static uint32_t EDDSACC26X2_runWeiToEdFSM(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_runGeneratePublicKeyFSM(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_runSignFSM(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_runVerifyFSM(EDDSA_Handle handle); +static int_fast16_t EDDSACC26X2_convertReturnValue(uint32_t pkaResult); + +/* Extern globals */ +extern const EDDSA_Params EDDSA_defaultParams; +#if (TFM_ENABLED == 1) +extern const ECCParams_CurveParams ECCParams_s_Ed25519; +extern const ECCParams_CurveParams ECCParams_s_Wei25519; +#endif + +/* Static globals */ +static bool EDDSACC26X2_isInitialized = false; +static uint32_t EDDSACC26X2_resultAddress; + +static uint32_t EDDSACC26X2_scratchPrivKeySize = SCRATCH_KEY_SIZE; +static uint32_t EDDSACC26X2_scratchPublicXSize = SCRATCH_KEY_SIZE; +static uint32_t EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; +static uint32_t EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; +static uint32_t EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; +static uint32_t EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + +static const ECCParams_CurveParams *curveEd25519; +static const ECCParams_CurveParams *curveWei25519; + +/* Temporary constant for 1 */ +const uint8_t EDDSACC26X2_one[32] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +/* Temporary constant for -1 */ +const uint8_t EDDSACC26X2_negOne[32] = {0xec, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}; + +/* Sqrt(-486664) */ +const uint8_t EDDSACC26X2_isoConst1[32] = {0xe7, 0x81, 0xba, 0x00, 0x55, 0xfb, 0x91, 0x33, 0x7d, 0xe5, 0x82, + 0xb4, 0x2e, 0x2c, 0x5e, 0x3a, 0x81, 0xb0, 0x03, 0xfc, 0x23, 0xf7, + 0x84, 0x2d, 0x44, 0xf9, 0x5f, 0x9f, 0x0b, 0x12, 0xd9, 0x70}; + +/* X25519.A / 3 */ +const uint8_t EDDSACC26X2_isoConst2[32] = {0x51, 0x24, 0xad, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x2a}; + +/* p - X25519.A / 3 */ +const uint8_t EDDSACC26X2_isoConst3[32] = {0x9c, 0xdb, 0x52, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}; + +/* (p - 5) / 8 */ +const uint8_t EDDSACC26X2_decodeConst1[32] = {0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f}; + +/* 2 ^ ((p - 1) / 4) */ +const uint8_t EDDSACC26X2_decodeConst2[32] = {0xb0, 0xa0, 0x0e, 0x4a, 0x27, 0x1b, 0xee, 0xc4, 0x78, 0xe4, 0x2f, + 0xad, 0x06, 0x18, 0x43, 0x2f, 0xa7, 0xd7, 0xfb, 0x3d, 0x99, 0x00, + 0x4d, 0x2b, 0x0b, 0xdf, 0xc1, 0x4f, 0x80, 0x24, 0x83, 0x2b}; + +#if (TFM_ENABLED == 0) +/* + * ======== EDDSACC26X2_internalCallbackFxn ======== + */ +static void EDDSACC26X2_internalCallbackFxn(EDDSA_Handle handle, + int_fast16_t returnStatus, + EDDSA_Operation operation, + EDDSA_OperationType operationType) +{ + EDDSACC26X2_Object *object = handle->object; + + /* + * This function is only ever registered when in + * EDDSA_RETURN_BEHAVIOR_BLOCKING or EDDSA_RETURN_BEHAVIOR_POLLING. + */ + if (object->returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&PKAResourceCC26XX_operationSemaphore); + } + else + { + PKAResourceCC26XX_pollingFlag = 1; + } +} +#endif + +/* + * ======== EDDSACC26X2_hwiFxn ======== + */ +static void EDDSACC26X2_hwiFxn(uintptr_t arg0) +{ + EDDSACC26X2_Object *object = ((EDDSA_Handle)arg0)->object; + uint32_t key; + + /* Disable interrupt again */ + IntDisable(INT_PKA_IRQ); + + /* Execute next states */ + do + { + object->operationStatus = object->fsmFxn((EDDSA_Handle)arg0); + /* Do not increment state FSM if in a substate */ + if ((object->fsmState == EDDSACC26X2_FSM_GEN_PUB_KEY_CONVERT_WEI_TO_ED) || + (object->fsmState == EDDSACC26X2_FSM_SIGN2_CONVERT_WEI_TO_ED) || + (object->fsmState == EDDSACC26X2_FSM_VERIFY2_CONVERT_WEI_TO_ED)) + { + if (object->fsmSubState == EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_X_RESULT) + { + /* + * Increment the state counter if the last substate operation + * was performed + */ + object->fsmState++; + } + else /* Otherwise continue with the substate FSM */ + { + object->fsmSubState++; + } + } + else /* All other states are post-increment */ + { + object->fsmState++; + } + } while (object->operationStatus == EDDSACC26X2_STATUS_FSM_RUN_FSM); + + /* + * We need a critical section here in case the operation is canceled + * asynchronously. + */ + key = HwiP_disable(); + + if (object->operationCanceled) + { + /* + * Set function register to 0. This should stop the current + * operation + */ + HWREG(PKA_BASE + PKA_O_FUNCTION) = 0; + + object->operationStatus = EDDSA_STATUS_CANCELED; + } + + switch (object->operationStatus) + { + case EDDSACC26X2_STATUS_FSM_RUN_PKA_OP: + + HwiP_restore(key); + + /* + * Do nothing. The PKA hardware + * will execute in the background and post + * this SWI when it is done. + */ + break; + case EDDSA_STATUS_SUCCESS: + /* Intentional fall through */ + case EDDSA_STATUS_ERROR: + /* Intentional fall through */ + case EDDSA_STATUS_CANCELED: + /* Intentional fall through */ + default: + + /* Mark this operation as complete */ + object->operationInProgress = false; + + /* + * Clear any pending interrupt in case a transaction kicked off + * above already finished + */ + IntDisable(INT_PKA_IRQ); + IntPendClear(INT_PKA_IRQ); + + /* + * We can end the critical section since the operation may no + * longer be canceled + */ + HwiP_restore(key); + + /* Make sure there is no keying material remaining in PKA RAM */ + PKAClearPkaRam(); + + /* Make sure there are no secrets left in the workspace memory */ + memset(object->EDDSACC26X2_GlobalWorkspace.digestResult, 0x0, SHA2_DIGEST_LENGTH_BYTES_512); + memset(object->EDDSACC26X2_GlobalWorkspace.digestResult2, 0x0, SHA2_DIGEST_LENGTH_BYTES_512); + memset(object->EDDSACC26X2_GlobalWorkspace.publicKey, 0x0, ED25519_LENGTH); + memset(object->EDDSACC26X2_GlobalWorkspace.secretScalar, 0x0, ED25519_LENGTH); + memset(object->EDDSACC26X2_GlobalWorkspace.xResult, 0x0, ED25519_LENGTH); + memset(object->EDDSACC26X2_GlobalWorkspace.yResult, 0x0, ED25519_LENGTH); + object->EDDSACC26X2_GlobalWorkspace.x_0 = 0; + + /* + * Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow + * the chaining of operations. + */ + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->callbackFxn((EDDSA_Handle)arg0, object->operationStatus, object->operation, object->operationType); + } +} + +#if (ENABLE_KEY_STORAGE == 1) +/* + * ======== EDDSA_getKeyStoreKey ======== + */ +static KeyStore_PSA_KeyUsage EDDSA_getKeyStoreUsage(EDDSACC26X2_OperationType opType) +{ + KeyStore_PSA_KeyUsage usage = EDDSACC26X2_OPTYPE_INVALID; + + switch (opType) + { + case EDDSACC26X2_OPTYPE_SIGN: + usage = KEYSTORE_PSA_KEY_USAGE_SIGN_MESSAGE; + break; + case EDDSACC26X2_OPTYPE_VERIFY: + usage = KEYSTORE_PSA_KEY_USAGE_VERIFY_MESSAGE; + break; + case EDDSACC26X2_OPTYPE_DERIVE: + usage = KEYSTORE_PSA_KEY_USAGE_DERIVE; + break; + default: + usage = EDDSACC26X2_OPTYPE_INVALID; + break; + } + + return usage; +} +#endif + +/* + * ======== EDDSA_getPrivateKey ======== + */ +static int_fast16_t EDDSA_getPrivateKey(const CryptoKey *privateKey, + uint8_t **privateKeyMaterial, + size_t *privateKeyLength, + EDDSACC26X2_OperationType opType) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage usage; +#endif + if (privateKey->encoding == CryptoKey_PLAINTEXT) + { + *privateKeyMaterial = privateKey->u.plaintext.keyMaterial; + *privateKeyLength = privateKey->u.plaintext.keyLength; + status = EDDSA_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (privateKey->encoding == CryptoKey_KEYSTORE) + { + /* Since this is a pure EDDSA, there is no pre-hashing. So, the keys + * can only be used for signing/verifying a message and not a hash. + * The private key can also be used to derive public key for EDDSA operations. + */ + usage = EDDSA_getKeyStoreUsage(opType); + if (usage == EDDSACC26X2_OPTYPE_INVALID) + { + return EDDSA_STATUS_ERROR; + } + + memset(EDDSACC26X2_keyStorePrivateKeyMaterial, 0, sizeof(EDDSACC26X2_keyStorePrivateKeyMaterial)); + + GET_KEY_ID(keyID, privateKey->u.keyStore.keyID); + + /* Obtain the private key from keystore */ + keyStoreStatus = KeyStore_PSA_getKey(keyID, + EDDSACC26X2_keyStorePrivateKeyMaterial, + sizeof(EDDSACC26X2_keyStorePrivateKeyMaterial), + privateKeyLength, + KEYSTORE_PSA_ALG_PURE_EDDSA, + usage); + if ((keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS) || (*privateKeyLength != privateKey->u.keyStore.keyLength)) + { + status = EDDSA_STATUS_KEYSTORE_ERROR; + } + else + { + *privateKeyMaterial = EDDSACC26X2_keyStorePrivateKeyMaterial; + status = EDDSA_STATUS_SUCCESS; + } + } +#endif + else + { + status = EDDSA_STATUS_ERROR; + } + + return status; +} + +/* + * ======== EDDSA_getPublicKey ======== + */ +static int_fast16_t EDDSA_getPublicKey(const CryptoKey *publicKey, + uint8_t **publicKeyMaterial, + size_t *publicKeyLength, + EDDSACC26X2_OperationType opType) +{ + int_fast16_t status; + +#if (ENABLE_KEY_STORAGE == 1) + int_fast16_t keyStoreStatus; + KeyStore_PSA_KeyFileId keyID; + KeyStore_PSA_KeyUsage usage; +#endif + if (publicKey->encoding == CryptoKey_PLAINTEXT) + { + *publicKeyMaterial = publicKey->u.plaintext.keyMaterial; + *publicKeyLength = publicKey->u.plaintext.keyLength; + status = EDDSA_STATUS_SUCCESS; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (publicKey->encoding == CryptoKey_KEYSTORE) + { + /* Since this is a pure EDDSA, there is no pre-hashing. So, the keys + * can only be used for signing/verifying a message and not a hash. + * The private key can also be used to derive public key for EDDSA operations. + */ + usage = EDDSA_getKeyStoreUsage(opType); + if (usage == EDDSACC26X2_OPTYPE_INVALID) + { + return EDDSA_STATUS_ERROR; + } + + memset(EDDSACC26X2_keyStorePublicKeyMaterial, 0, sizeof(EDDSACC26X2_keyStorePublicKeyMaterial)); + + GET_KEY_ID(keyID, publicKey->u.keyStore.keyID); + + /* Obtain the public key from keystore */ + keyStoreStatus = KeyStore_PSA_getKey(keyID, + EDDSACC26X2_keyStorePublicKeyMaterial, + sizeof(EDDSACC26X2_keyStorePublicKeyMaterial), + publicKeyLength, + KEYSTORE_PSA_ALG_PURE_EDDSA, + usage); + if (keyStoreStatus != KEYSTORE_PSA_STATUS_SUCCESS || (*publicKeyLength != publicKey->u.keyStore.keyLength)) + { + status = EDDSA_STATUS_KEYSTORE_ERROR; + } + else + { + *publicKeyMaterial = EDDSACC26X2_keyStorePublicKeyMaterial; + status = EDDSA_STATUS_SUCCESS; + } + } +#endif + else + { + status = EDDSA_STATUS_ERROR; + } + + return status; +} + +/* + * ======== EDDSACC26X2_sha2Callback ======== + */ +void EDDSACC26X2_sha2Callback(SHA2_Handle handle, int_fast16_t returnValue) +{ + + EDDSACC26X2_Object *object = ((EDDSACC26X2_Object *)(handle)); + + /* Handle the SHA2 return value */ + if (returnValue != SHA2_STATUS_SUCCESS) + { + /* If SHA2 failed, then return a SHA2 error for EdDSA. */ + object->operationStatus = EDDSA_STATUS_SHA2_HASH_FAILURE; + + SHA2_close(object->sha2Handle); + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + } + else + { + /* + * Run the PKA FSM by triggering the PKA interrupt. It is level + * triggered and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + } +} + +#if (ENABLE_KEY_STORAGE == 1) + +/* + * ======== EDDSACC26X2_importSecureKey ======== + */ +static int_fast16_t EDDSACC26X2_importSecureKey(CryptoKey *key, const uint8_t *keyingMaterial) +{ + KeyStore_PSA_KeyFileId keyID; + int_fast16_t keyStoreResult; + int_fast16_t status = EDDSA_STATUS_KEYSTORE_ERROR; + KeyStore_PSA_KeyAttributes *attributesPtr; + + /* Copy key identifier from CryptoKey */ + GET_KEY_ID(keyID, key->u.keyStore.keyID); + + #if (TFM_ENABLED == 0) + attributesPtr = (KeyStore_PSA_KeyAttributes *)key->u.keyStore.keyAttributes; + #else + KeyStore_PSA_KeyAttributes attributes = KEYSTORE_PSA_KEY_ATTRIBUTES_INIT; + attributesPtr = &attributes; + keyStoreResult = KeyStore_s_copyKeyAttributesFromClient((struct psa_client_key_attributes_s *) + key->u.keyStore.keyAttributes, + KEYSTORE_PSA_DEFAULT_OWNER, + attributesPtr); + #endif + keyStoreResult = KeyStore_PSA_importKey(attributesPtr, + (uint8_t *)keyingMaterial, + key->u.keyStore.keyLength, + &keyID); + + if (keyStoreResult == KEYSTORE_PSA_STATUS_SUCCESS) + { + KeyStore_PSA_initKey(key, keyID, key->u.keyStore.keyLength, attributesPtr); + status = EDDSA_STATUS_SUCCESS; + } + + return status; +} +#endif + +/* + * ======== EDDSACC26X2_storePublicKey ======== + */ +static int_fast16_t EDDSACC26X2_storePublicKey(EDDSA_Handle handle, + const uint8_t *xCoordinate, + const uint8_t *yCoordinate) +{ +#if (ENABLE_KEY_STORAGE == 1) + uint8_t EDDSACC26X2_keyStorePublicKeyMaterial[EDDSA_MAX_KEYSTORE_PUBLIC_KEY_SIZE]; +#endif + EDDSACC26X2_Object *object = handle->object; + int_fast16_t status = EDDSA_STATUS_ERROR; + + if (object->operation.generatePublicKey->myPublicKey->encoding == CryptoKey_BLANK_PLAINTEXT) + { + status = EDDSACC26X2_encodePublicKey(handle, + object->operation.generatePublicKey->myPublicKey->u.plaintext.keyMaterial, + xCoordinate, + yCoordinate); + + /* Mark the public key CryptoKey as non-empty */ + object->operation.generatePublicKey->myPublicKey->encoding = CryptoKey_PLAINTEXT; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (object->operation.generatePublicKey->myPublicKey->encoding == CryptoKey_BLANK_KEYSTORE) + { + /* EDDSACC26X2_encodePublicKey always returns success */ + (void)EDDSACC26X2_encodePublicKey(handle, EDDSACC26X2_keyStorePublicKeyMaterial, xCoordinate, yCoordinate); + + status = EDDSACC26X2_importSecureKey(object->operation.generatePublicKey->myPublicKey, + (const uint8_t *)EDDSACC26X2_keyStorePublicKeyMaterial); + } +#endif + else + { + status = EDDSA_STATUS_ERROR; + } + + return status; +} + +/* + * ======== EDDSACC26X2_encodePublicKey ======== + */ +static int_fast16_t EDDSACC26X2_encodePublicKey(EDDSA_Handle handle, + uint8_t *outputKey, + const uint8_t *xCoordinate, + const uint8_t *yCoordinate) +{ + /* + * Copy the y-coordinate to the buffer. The input and output + * both are little endian. + */ + memcpy(outputKey, yCoordinate, curveEd25519->length); + + /* + * If the least significant bit of the x-coordinate is 0x1, then we set + * the most significant bit of the encoded public key to indicate so. + * This is to compress the public key to {[0x80,0x00] | y } + */ + outputKey[31] |= (xCoordinate[0] & 0x1) ? 0x80 : 0x00; + + return (EDDSA_STATUS_SUCCESS); +} + +static uint32_t EDDSACC26X2_runWeiToEdFSM(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + + switch (object->fsmSubState) + { + case EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION: + /* + * Perform conversion from Ed25519 to Wei25519 + * (u,v) on Wei25519 to (x,y) on Ed25519 + * x = sqrt(-486664) * (u - X25519.A/3) * (v)^-1 + * y = (u - X25519.A/3 - 1) * (u - X25519.A/3 + 1)^-1 + * To only compute one inversion, we compute + * (v * (u - X25519.A/3 + 1))^-1 + */ + /* + * Compute u - X25519.A/3 by performing u + (p - X25519.A/3) to + * stay positive + */ + PKABigNumAddStart(SCRATCH_PUBLIC_X, + curveEd25519->length, + EDDSACC26X2_isoConst3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION_RESULT: + EDDSACC26X2_scratchPublicXSize = SCRATCH_KEY_SIZE; + return ( + PKABigNumAddGetResult(SCRATCH_PUBLIC_X, &EDDSACC26X2_scratchPublicXSize, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_ADD_ONE: + /* Compute u - X25519.A/3 + 1 */ + PKABigNumAddStart(SCRATCH_PUBLIC_X, + curveEd25519->length, + EDDSACC26X2_one, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_ADD_ONE_RESULT: + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumAddGetResult(SCRATCH_BUFFER_0, &EDDSACC26X2_scratchBuffer0Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V: + /* Compute (v * (u - X25519.A/3 + 1)) */ + PKABigNumMultiplyStart(SCRATCH_PUBLIC_Y, + curveEd25519->length, + SCRATCH_BUFFER_0, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_RESULT: + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_1, &EDDSACC26X2_scratchBuffer1Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_MULT_V: + /* Compute (v * (u - X25519.A/3 + 1)) mod p */ + PKABigNumModStart(SCRATCH_BUFFER_1, + EDDSACC26X2_scratchBuffer1Size, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_MULT_V_RESULT: + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + return (PKABigNumModGetResult(SCRATCH_BUFFER_1, EDDSACC26X2_scratchBuffer1Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_INVERSION: + /* Compute (v * (u - X25519.A/3 + 1))^-1 */ + PKABigNumInvModStart(SCRATCH_BUFFER_1, + curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_INVERSION_RESULT: + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumInvModGetResult(SCRATCH_BUFFER_1, EDDSACC26X2_scratchBuffer1Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE1: + /* Compute (v)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_BUFFER_0, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE1_RESULT: + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_2, &EDDSACC26X2_scratchBuffer2Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE2: + /* Compute (u - X25519.A/3 + 1)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_PUBLIC_Y, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE2_RESULT: + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_1, &EDDSACC26X2_scratchBuffer1Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_SUB_ONE: + /* + * Compute u - X25519.A/3 - 1 by performing + * u - X25519.A/3 + (p - 1) + */ + PKABigNumAddStart(SCRATCH_PUBLIC_X, + curveEd25519->length, + EDDSACC26X2_negOne, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_SUB_ONE_RESULT: + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumAddGetResult(SCRATCH_BUFFER_0, &EDDSACC26X2_scratchBuffer0Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_SUB: + /* Compute x mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + EDDSACC26X2_scratchBuffer0Size, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_SUB_RESULT: + EDDSACC26X2_scratchPublicXSize = SCRATCH_KEY_SIZE; + return (PKABigNumModGetResult(SCRATCH_BUFFER_0, curveEd25519->length, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_RETRIEVE_Y: + /* Compute y = (u - X25519.A/3 - 1) * (u - X25519.A/3 + 1)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + curveEd25519->length, + SCRATCH_BUFFER_1, + 2 * curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_RETRIEVE_Y_RESULT: + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_0, &EDDSACC26X2_scratchBuffer0Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_Y: + /* Compute y mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + EDDSACC26X2_scratchBuffer0Size, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_Y_RESULT: + return (PKABigNumModGetResult(object->EDDSACC26X2_GlobalWorkspace.yResult, + curveEd25519->length, + EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_U_MULT_ISO_CONST: + /* Compute sqrt(-486664) * (u - X25519.A/3) */ + PKABigNumMultiplyStart(EDDSACC26X2_isoConst1, + curveEd25519->length, + SCRATCH_PUBLIC_X, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_U_MULT_ISO_CONST_RESULT: + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_0, &EDDSACC26X2_scratchBuffer0Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_INVERSE: + /* Compute x = sqrt(-486664) * (u - X25519.A/3) * (v)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + 2 * curveEd25519->length, + SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_INVERSE_RESULT: + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + return ( + PKABigNumMultGetResult(SCRATCH_BUFFER_0, &EDDSACC26X2_scratchBuffer0Size, EDDSACC26X2_resultAddress)); + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_X: + /* Compute x mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + EDDSACC26X2_scratchBuffer0Size, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_X_RESULT: + EDDSACC26X2_scratchPublicXSize = SCRATCH_KEY_SIZE; + return (PKABigNumModGetResult(object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + EDDSACC26X2_resultAddress)); + + default: + return (PKA_STATUS_FAILURE); + } + /* If we break from the FSM, that means we just started a PKA operation, + * so we want to indicate this to the upstream FSM. + */ + return (EDDSACC26X2_PKA_OPERATION_STARTED); +} + +/* + * ======== EDDSACC26X2_runGeneratePublicKeyFSM ======== + */ +static int_fast16_t EDDSACC26X2_runGeneratePublicKeyFSM(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + uint8_t *privateKeyMaterial; + size_t privateKeyLength; + int_fast16_t status; + + switch (object->fsmState) + { + case EDDSACC26X2_FSM_GEN_PUB_KEY_HASH_PRIVATE_KEY: + + /* Obtain the private key material */ + status = EDDSA_getPrivateKey(object->operation.generatePublicKey->myPrivateKey, + &privateKeyMaterial, + &privateKeyLength, + EDDSACC26X2_OPTYPE_DERIVE); + + if (status != EDDSA_STATUS_SUCCESS) + { + return status; + } + + /* Hash and prune the private key to generate the public key */ + SHA2_hashData(object->sha2Handle, + privateKeyMaterial, + privateKeyLength, + object->EDDSACC26X2_GlobalWorkspace.digestResult); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_GEN_PUB_KEY_MULT_PRIV_KEY_BY_GENER_WEIER: + + /* Close the SHA2 driver as we no longer need it */ + SHA2_close(object->sha2Handle); + + /* Prune the least significant half of the hash digest */ + /* Clear bits 0,1,2 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[0] &= 0xF8; + /* Clear Bit 255 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[31] &= 0x7F; + /* Set bit 254 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[31] |= 0x40; + + /* + * Copy the hashed and pruned private key to generate the public + * key Edwards point + */ + CryptoUtils_copyPad(object->EDDSACC26X2_GlobalWorkspace.digestResult, + SCRATCH_PRIVATE_KEY, + curveEd25519->length); + + /* + * Perform the point multiplication A = s*B to generate the public + * key point in short Weierstrass form + */ + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + curveWei25519->generatorX, + curveWei25519->generatorY, + curveWei25519->prime, + curveWei25519->a, + curveWei25519->b, + curveWei25519->length, + &EDDSACC26X2_resultAddress); + break; + + case EDDSACC26X2_FSM_GEN_PUB_KEY_MULT_PRIV_KEY_BY_GENER_WEIER_RESULT: + + pkaResult = PKAEccMultiplyGetResult(SCRATCH_PUBLIC_X, + SCRATCH_PUBLIC_Y, + EDDSACC26X2_resultAddress, + curveEd25519->length); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_GEN_PUB_KEY_CONVERT_WEI_TO_ED: + /* + * Run through the substate FSM to convert the short Weierstrass + * point to an Edwards point. + */ + pkaResult = EDDSACC26X2_runWeiToEdFSM(handle); + + /* We break if we just started a PKA operation */ + if (pkaResult == EDDSACC26X2_PKA_OPERATION_STARTED) + { + break; + } + else /* Otherwise, convert the return value */ + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + + case EDDSACC26X2_FSM_GEN_PUB_KEY_ENCODE_PUBLIC_KEY: + /* Encode the public key to the output */ + status = EDDSACC26X2_storePublicKey(handle, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.xResult, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.yResult); + + return (status); + + default: + return (EDDSA_STATUS_ERROR); + } + + /* If we get to this point, we want to perform another PKA operation */ + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); +} + +/* + * ======== EDDSACC26X2_runSignFSM ======== + */ +static int_fast16_t EDDSACC26X2_runSignFSM(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + uint8_t *privateKeyMaterial; + size_t privateKeyLength; + uint8_t *publicKeyMaterial; + size_t publicKeyLength; + int_fast16_t status; + + switch (object->fsmState) + { + + case EDDSACC26X2_FSM_SIGN1_HASH_PRIVATE_KEY: + + /* Obtain the private key material */ + status = EDDSA_getPrivateKey(object->operation.sign->myPrivateKey, + &privateKeyMaterial, + &privateKeyLength, + EDDSACC26X2_OPTYPE_SIGN); + + if (status != EDDSA_STATUS_SUCCESS) + { + return status; + } + + /* Hash and prune the private key to sign the message */ + SHA2_hashData(object->sha2Handle, + privateKeyMaterial, + privateKeyLength, + object->EDDSACC26X2_GlobalWorkspace.digestResult); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN1_HASH_UPPER_SECRET_KEY: + + /* + * Generate the secret scalar r by hashing the upper half of the + * previous hash digest as well as the message. + * r = H ( upperHalf(H(sk)) || PH(M)) + */ + SHA2_addData(object->sha2Handle, + &object->EDDSACC26X2_GlobalWorkspace.digestResult[32], + curveEd25519->length); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN1_HASH_MESSAGE1: + + /* + * Perform a first hash so that the following hashes are only in + * preHashedMessage + */ + if ((curveEd25519->length + object->operation.sign->preHashedMessageLength) > SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + object->operation.sign->preHashedMessage, + SHA2_BLOCK_SIZE_BYTES_512 - curveEd25519->length); + } + else + { + SHA2_addData(object->sha2Handle, + object->operation.sign->preHashedMessage, + object->operation.sign->preHashedMessageLength); + } + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN1_HASH_MESSAGE2: + /* + * Perform an additional hash of the remaining preHashedMessage, if + * needed. + */ + if ((curveEd25519->length + object->operation.sign->preHashedMessageLength) > SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + &object->operation.sign + ->preHashedMessage[SHA2_BLOCK_SIZE_BYTES_512 - curveEd25519->length], + object->operation.sign->preHashedMessageLength - + (SHA2_BLOCK_SIZE_BYTES_512 - curveEd25519->length)); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + } + else + { + /* Otherwise just continue to the next FSM state */ + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + } + + case EDDSACC26X2_FSM_SIGN1_HASH_FINALIZE: + + SHA2_finalize(object->sha2Handle, object->EDDSACC26X2_GlobalWorkspace.digestResult2); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN2_MOD_SECRET_HASH: + /* + * Prune the least significant half of the hash digest as this is + * used to generate signature component S. + */ + /* Clear bits 0,1,2 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[0] &= 0xF8; + /* Clear Bit 255 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[31] &= 0x7F; + /* Set bit 254 */ + object->EDDSACC26X2_GlobalWorkspace.digestResult[31] |= 0x40; + + /* + * Copy the private key to scratch memory so that + * we can perform operations with it. + */ + CryptoUtils_copyPad(object->EDDSACC26X2_GlobalWorkspace.digestResult2, + SCRATCH_PRIVATE_KEY, + 2 * curveEd25519->length); + + /* + * Compute r mod n. This is necessary to run the ECC point + * multiplication and also roughly doubles the speed of the point + * multiplication + */ + PKABigNumModStart((uint8_t *)SCRATCH_PRIVATE_KEY, + 2 * curveEd25519->length, + curveEd25519->order, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_SIGN2_MOD_SECRET_HASH_RESULT: + + pkaResult = PKABigNumModGetResult(object->EDDSACC26X2_GlobalWorkspace.secretScalar, + curveEd25519->length, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_SIGN2_MULT_SECRET_HASH_BY_GENERATOR_WEIER: + /* + * Perform the point multiplication R = r*B to generate the public + * key point in short Weierstrass form + */ + PKAEccMultiplyStart(object->EDDSACC26X2_GlobalWorkspace.secretScalar, + curveWei25519->generatorX, + curveWei25519->generatorY, + curveWei25519->prime, + curveWei25519->a, + curveWei25519->b, + curveWei25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_SIGN2_MULT_SECRET_HASH_BY_GENERATOR_WEIER_RESULT: + + pkaResult = PKAEccMultiplyGetResult(SCRATCH_PUBLIC_X, + SCRATCH_PUBLIC_Y, + EDDSACC26X2_resultAddress, + curveWei25519->length); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_SIGN2_CONVERT_WEI_TO_ED: + /* + * Run through the substate FSM to convert the short Weierstrass + * point to an Edwards point. + */ + pkaResult = EDDSACC26X2_runWeiToEdFSM(handle); + + /* We break if we just started a PKA operation */ + if (pkaResult == EDDSACC26X2_PKA_OPERATION_STARTED) + { + break; + } + else /* Otherwise, convert the return value */ + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + + case EDDSACC26X2_FSM_SIGN2_ENCODE_PUBLIC_KEY: + /* Encode the public key to the output */ + EDDSACC26X2_encodePublicKey(handle, + object->operation.sign->R, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.xResult, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.yResult); + + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + + case EDDSACC26X2_FSM_SIGN3_HASH_SIG_R: + /* + * Generate the signature digest by hashing the signature component + * R, + * public key A, and prehashed message PH(M) + * H ( R || A || PH(M)) + */ + SHA2_addData(object->sha2Handle, object->operation.sign->R, curveEd25519->length); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN3_HASH_PUBLIC_KEY: + + /* Obtain the public key material */ + status = EDDSA_getPublicKey(object->operation.sign->myPublicKey, + &publicKeyMaterial, + &publicKeyLength, + EDDSACC26X2_OPTYPE_SIGN); + + if (status != EDDSA_STATUS_SUCCESS) + { + return status; + } + + SHA2_addData(object->sha2Handle, publicKeyMaterial, publicKeyLength); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN3_HASH_MESSAGE1: + + /* + * Perform a first hash so that the following hashes are only in + * preHashedMessage + */ + if (((2 * curveEd25519->length) + object->operation.sign->preHashedMessageLength) > + SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + object->operation.sign->preHashedMessage, + SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length)); + } + else + { + SHA2_addData(object->sha2Handle, + object->operation.sign->preHashedMessage, + object->operation.sign->preHashedMessageLength); + } + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN3_HASH_MESSAGE2: + + /* + * Perform an additional hash of the remaining preHashedMessage, + * if needed. + */ + if (((2 * curveEd25519->length) + object->operation.sign->preHashedMessageLength) > + SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + &object->operation.sign + ->preHashedMessage[SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length)], + object->operation.sign->preHashedMessageLength - + (SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length))); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + } + else + { + /* Otherwise just continue to the next FSM state */ + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + } + + case EDDSACC26X2_FSM_SIGN3_HASH_FINALIZE: + + SHA2_finalize(object->sha2Handle, object->EDDSACC26X2_GlobalWorkspace.digestResult2); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_SIGN4_MULT_SIG_HASH_BY_SECRET_KEY: + /* Close the SHA2 driver as we no longer need it */ + SHA2_close(object->sha2Handle); + /* + * Compute the signature component S + * S = r + H(R || A || M) * s mod n + */ + /* Compute H(R || A || M) * s */ + PKABigNumMultiplyStart(object->EDDSACC26X2_GlobalWorkspace.digestResult2, + 2 * curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.digestResult, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_SIGN4_MULT_SIG_HASH_BY_SECRET_KEY_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_SIGN4_ADD_SECRET_HASH_TO_MULT: + /* Compute S = r + H(R || A || M) * s */ + PKABigNumAddStart(SCRATCH_BUFFER_0, + 3 * curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.secretScalar, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_SIGN4_ADD_SECRET_HASH_TO_MULT_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_SIGN4_MOD_S: + /* Compute S mod n */ + PKABigNumModStart(SCRATCH_BUFFER_0, + 3 * curveEd25519->length, + curveEd25519->order, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_SIGN4_MOD_S_RESULT: + + pkaResult = PKABigNumModGetResult(object->operation.sign->S, + curveEd25519->length, + EDDSACC26X2_resultAddress); + + if (pkaResult == PKA_STATUS_SUCCESS) + { + return (EDDSA_STATUS_SUCCESS); + } + else + { + return (EDDSA_STATUS_ERROR); + } + default: + return (EDDSA_STATUS_ERROR); + } + + /* If we get to this point, we want to perform another PKA operation */ + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); +} + +/* + * ======== EDDSACC26X2_runVerifyFSM ======== + */ +static int_fast16_t EDDSACC26X2_runVerifyFSM(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + uint32_t pkaResult; + uint8_t *publicKeyMaterial; + size_t publicKeyLength; + int_fast16_t status; + + switch (object->fsmState) + { + + case EDDSACC26X2_FSM_VERIFY1_HASH_SIG_R: + /* + * Generate the signature digest by hashing the signature component + * R, public key A, and prehashed message PH(M) + * H ( R || A || PH(M)) + */ + SHA2_addData(object->sha2Handle, object->operation.verify->R, curveEd25519->length); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_VERIFY1_HASH_PUBLIC_KEY: + + /* Obtain the public key material */ + status = EDDSA_getPublicKey(object->operation.verify->theirPublicKey, + &publicKeyMaterial, + &publicKeyLength, + EDDSACC26X2_OPTYPE_VERIFY); + + if (status != EDDSA_STATUS_SUCCESS) + { + return status; + } + + SHA2_addData(object->sha2Handle, publicKeyMaterial, publicKeyLength); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_VERIFY1_HASH_MESSAGE1: + + /* + * Perform a first hash so that the following hashes are only in + * preHashedMessage + */ + if (((2 * curveEd25519->length) + object->operation.verify->preHashedMessageLength) > + SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + object->operation.verify->preHashedMessage, + SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length)); + } + else + { + SHA2_addData(object->sha2Handle, + object->operation.verify->preHashedMessage, + object->operation.verify->preHashedMessageLength); + } + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_VERIFY1_HASH_MESSAGE2: + + /* + * Perform an additional hash of the remaining preHashedMessage, + * if needed. + */ + if (((2 * curveEd25519->length) + object->operation.verify->preHashedMessageLength) > + SHA2_BLOCK_SIZE_BYTES_512) + { + SHA2_addData(object->sha2Handle, + &object->operation.verify + ->preHashedMessage[SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length)], + object->operation.verify->preHashedMessageLength - + (SHA2_BLOCK_SIZE_BYTES_512 - (2 * curveEd25519->length))); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + } + else + { + /* Otherwise just continue to the next FSM state */ + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + } + + case EDDSACC26X2_FSM_VERIFY1_HASH_FINALIZE: + + SHA2_finalize(object->sha2Handle, object->EDDSACC26X2_GlobalWorkspace.digestResult2); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); + + case EDDSACC26X2_FSM_VERIFY1_S_IN_RANGE: + + /* Close the SHA2 driver as we no longer need it */ + SHA2_close(object->sha2Handle); + + /* Check if S < n ? */ + PKABigNumCmpStart(object->operation.verify->S, curveEd25519->order, curveEd25519->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumCmpGetResult(); + + /* If S is not less than n, then it is invalid. */ + if (pkaResult != PKA_STATUS_A_LESS_THAN_B) + { + return (EDDSA_STATUS_S_LARGER_THAN_ORDER); + } + + break; + + case EDDSACC26X2_FSM_VERIFY1_A_IS_NOT_POINT_AT_INFINITY: + + /* Obtain the public key material */ + status = EDDSA_getPublicKey(object->operation.verify->theirPublicKey, + &publicKeyMaterial, + &publicKeyLength, + EDDSACC26X2_OPTYPE_VERIFY); + + if (status != EDDSA_STATUS_SUCCESS) + { + return status; + } + + memcpy(object->EDDSACC26X2_GlobalWorkspace.publicKey, publicKeyMaterial, publicKeyLength); + + /* The MSB of the public key indicates if sqrt(x) is even or odd */ + object->EDDSACC26X2_GlobalWorkspace.x_0 = object->EDDSACC26X2_GlobalWorkspace.publicKey[31] >> 7; + + /* + * Remove the MSB of the public key so that it is only the + * y-coordinate + */ + object->EDDSACC26X2_GlobalWorkspace.publicKey[31] &= 0x7F; + + /* Check if y <= 1 ? */ + PKABigNumCmpStart(object->EDDSACC26X2_GlobalWorkspace.publicKey, EDDSACC26X2_one, curveEd25519->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumCmpGetResult(); + + /* + * If y is 1 or 0, then this is a point of low order which cannot + * be a public key. This also catches an invalid encoded + * representation of the point at infinity. + */ + if (pkaResult != PKA_STATUS_A_GREATER_THAN_B) + { + return (EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE); + } + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_Y_BY_Y: + /* + * Public Key decoding: Retrieve the x-coordinate + * from the compressed public key encoding + * Edwards curve form: a * x^2 + y^2 = 1 + d * x^2 * y^2 + * Solving for x^2: + * x^2 = (y^2 - 1) / (d * y^2 - a) + * To simplify the square root computation, + * we let u = y^2 - 1 and v = d * y^2 + 1 and solve + * (found in RFC 8032 Section 5.1.3) + * x = u * v^3 * (u * v^7) ^ ((p-5)/8) + */ + + /* Compute y^2 */ + PKABigNumMultiplyStart(object->EDDSACC26X2_GlobalWorkspace.publicKey, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.publicKey, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_Y_BY_Y_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_1, + &EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_Y2: + /* Compute y^2 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_1, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_Y2_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_1, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_SUBTRACT_ONE_FROM_Y2: + /* Compute u = y^2 - 1 */ + PKABigNumAddStart(SCRATCH_BUFFER_1, + curveEd25519->length, + EDDSACC26X2_negOne, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_SUBTRACT_ONE_FROM_Y2_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_D_BY_Y2: + /* Compute d * y^2 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + curveEd25519->b, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_D_BY_Y2_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_1, + &EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_D_Y2: + /* Compute d * y^2 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_1, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_D_Y2_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_1, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_ADD_ONE_TO_D_Y2: + /* Compute v = d * y^2 + 1 */ + PKABigNumAddStart(SCRATCH_BUFFER_1, + curveEd25519->length, + EDDSACC26X2_one, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_ADD_ONE_TO_D_Y2_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_1, + &EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_V_BY_V: + /* We need to compute u * v^3 * (u * v^7)^((p - 5) / 8) + * Start by computing u*v^3 and u*v^7 + */ + /* Compute v^2 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_BUFFER_1, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_V_BY_V_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_V2: + /* Compute v^2 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_V2_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_2, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_V2_BY_V: + /* Compute v^3 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_BUFFER_2, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_V2_BY_V_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_V3: + /* Compute v^3 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_V3_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_V3_BY_U: + /* Compute u * v^3 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + curveEd25519->length, + SCRATCH_BUFFER_3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_V3_BY_U_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V3: + /* Compute leftside = u * v^3 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V3_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_2, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_V3: + /* Compute u * v^6 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_3, + curveEd25519->length, + SCRATCH_BUFFER_2, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_V3_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V6: + /* Compute u * v^6 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V6_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V6_BY_V: + /* Compute rightside = u * v^7 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_3, + curveEd25519->length, + SCRATCH_BUFFER_1, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V6_BY_V_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V7: + /* Compute u * v^7 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_V7_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_EXP_U_V7: + /* Compute (u * v^7) ^ ((p - 5) / 8) */ + PKABigNumExpModStart(SCRATCH_BUFFER_3, + curveEd25519->length, + EDDSACC26X2_decodeConst1, + curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_EXP_U_V7_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + /* Exponentiation and inversion have the same kind of result */ + pkaResult = PKABigNumInvModGetResult(SCRATCH_BUFFER_3, + EDDSACC26X2_scratchBuffer3Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_EXP: + /* Compute u * v^3 * (u * v^7) ^ ((p - 5) / 8 ) */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_2, + curveEd25519->length, + SCRATCH_BUFFER_3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_EXP_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_CANDIDATE_X: + /* + * Compute candidate x = u * v^3 * (u * v^7) ^ ((p - 5) / 8 ) mod p + */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_CANDIDATE_X_RESULT: + + pkaResult = PKABigNumModGetResult(object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_X_BY_X: + /* For p = 5 mod 8 (as is the case for Ed25519), we need to check + * for the three following conditions: + * 1. v * x^2 = u mod p, then x is the square root + * 2. v * x^2 = -u mod p, then x * 2^((p - 1) / 4) is the square + * root + * 3. Otherwise no square root exists + */ + + /* Compute candidate x^2 */ + PKABigNumMultiplyStart(object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_X_BY_X_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_X2: + /* Compute candidate x^2 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_X2_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MULT_X2_BY_V: + /* Compute candidate v * x^2 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_BUFFER_3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MULT_X2_BY_V_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_V_X2: + /* Compute candidate v * x^2 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_V_X2_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_MOD_U: + /* Compute u mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_MOD_U_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_0, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_NEGATE_U: + /* + * Compute -u mod p by performing p - u (note that if u = 0, + * then -u = p, but the comparison will either pass or fail if + * v * x^2 = u mod p */ + PKABigNumSubStart(curveEd25519->prime, + curveEd25519->length, + SCRATCH_BUFFER_0, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY1_NEGATE_U_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumSubGetResult(SCRATCH_BUFFER_1, + &EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY1_CHECK_SQUARE_ROOT: + /* For p = 5 mod 8 (as is the case for Ed25519), we need to check + * for the three following conditions: + * 1. v * x^2 = u mod p, then x is the square root + * 2. v * x^2 = -u mod p, then x * 2^((p - 1) / 4) is the square + * root + * 3. Otherwise no square root exists + * + * Since there is conditional logic and these are all quick + * operations, we do these in one FSM state with polling. The + * resulting x-coordinate (if it exists) is moved to the + * object->EDDSACC26X2_GlobalWorkspace.xResult buffer. + */ + /* Check if v * x^2 == u ? */ + PKABigNumCmpStart(SCRATCH_BUFFER_3, SCRATCH_BUFFER_0, curveEd25519->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumCmpGetResult(); + + /* If v * x^2 != u, then we have to check further */ + if (pkaResult != PKA_STATUS_EQUAL) + { + /* Check if condition 2 is true that v * x^2 == -u mod p */ + PKABigNumCmpStart(SCRATCH_BUFFER_3, SCRATCH_BUFFER_1, curveEd25519->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumCmpGetResult(); + if (pkaResult == PKA_STATUS_EQUAL) + { + /* Compute x * 2^((p - 1) / 4) */ + PKABigNumMultiplyStart(object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + EDDSACC26X2_decodeConst2, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + + /* Compute x * 2^((p - 1) / 4) mod p */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumModGetResult(object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + EDDSACC26X2_resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + } + else + { + /* + * x-coordinate square root does not exist so this is not a + * valid point + */ + return (EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE); + } + } + + /* + * Check if the correct square root was chosen by bit x_0. + * The MSB of the public key specifies if the x-coordinate + * should be even or odd. + */ + if (object->EDDSACC26X2_GlobalWorkspace.x_0 != (object->EDDSACC26X2_GlobalWorkspace.xResult[0] & 0x1)) + { + /* Wrong square root result selected, so perform p - x */ + PKABigNumSubStart(curveEd25519->prime, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + EDDSACC26X2_scratchPublicXSize = SCRATCH_KEY_SIZE; + pkaResult = PKABigNumSubGetResult(object->EDDSACC26X2_GlobalWorkspace.xResult, + &EDDSACC26X2_scratchPublicXSize, + EDDSACC26X2_resultAddress); + + if (pkaResult != PKA_STATUS_SUCCESS) + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + } + + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + + case EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_P: + /* + * Perform conversion from Ed25519 to Wei25519 + * (x,y) on Ed25519 to (u,v) on Wei25519 + * um is the x-coordinate on X25519 + * um = (1 + y) / (1 - y) + * u = um + X25519.A/3 + * v = sqrt(-486664) * um * (x)^-1 + * To only compute one inversion, we compute ((1 - y) * (x))^-1 + */ + + /* Compute p + 1 so that we can perform 1 - y */ + PKABigNumAddStart(curveEd25519->prime, + curveEd25519->length, + EDDSACC26X2_one, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_P_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_SUBTRACT_Y_FROM_P_PLUS_ONE: + /* Compute 1 - y + p (positive number) */ + PKABigNumSubStart(SCRATCH_BUFFER_0, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.publicKey, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_SUBTRACT_Y_FROM_P_PLUS_ONE_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumSubGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_BY_X: + /* Compute (1 - y) * x */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_BY_X_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_1, + &EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_X: + /* Compute (1 - y) * x mod p */ + PKABigNumModStart(SCRATCH_BUFFER_1, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_X_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_1, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_INVERSION: + /* Compute ((1 - y) * x) ^ (-1) mod p */ + PKABigNumInvModStart(SCRATCH_BUFFER_1, + curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_INVERSION_RESULT: + + EDDSACC26X2_scratchBuffer1Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumInvModGetResult(SCRATCH_BUFFER_1, + EDDSACC26X2_scratchBuffer1Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_X: + /* Compute (1 - y)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + object->EDDSACC26X2_GlobalWorkspace.xResult, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_X_RESULT: + + EDDSACC26X2_scratchBuffer2Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_2, + &EDDSACC26X2_scratchBuffer2Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_INV: + /* Compute (1 - y)^-1 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_2, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_INV_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_2, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_ONE_MINUS_Y: + /* Compute (x)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_1, + curveEd25519->length, + SCRATCH_BUFFER_0, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_ONE_MINUS_Y_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer3Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_X_INV: + /* Compute (x)^-1 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_X_INV_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_Y: + /* Compute y + 1 */ + PKABigNumAddStart(object->EDDSACC26X2_GlobalWorkspace.publicKey, + curveEd25519->length, + EDDSACC26X2_one, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_Y_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_INV_BY_ONE_PLUS_Y: + /* Compute um = (1 + y) * (1 - y)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + curveEd25519->length, + SCRATCH_BUFFER_2, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_INV_BY_ONE_PLUS_Y_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_UM: + /* Compute um = (1 + y) * (1 - y)^-1 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_UM_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_0, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_UM_BY_X_INV: + + /* Compute um * (x)^-1 */ + PKABigNumMultiplyStart(SCRATCH_BUFFER_0, + curveEd25519->length, + SCRATCH_BUFFER_3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_UM_BY_X_INV_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer3Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_UM_X_INV: + /* Compute um * (x)^-1 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_UM_X_INV_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_BUFFER_3, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_ADD_CONST_TO_UM: + /* Compute u = um + Ed25519.A / 3 */ + PKABigNumAddStart(SCRATCH_BUFFER_0, + curveEd25519->length, + EDDSACC26X2_isoConst2, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_ADD_CONST_TO_UM_RESULT: + + EDDSACC26X2_scratchBuffer0Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumAddGetResult(SCRATCH_BUFFER_0, + &EDDSACC26X2_scratchBuffer0Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_WEIERX: + /* Compute u = um + Ed25519.A / 3 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_0, + curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_WEIERX_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_PUBLIC_X, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_UM_X_INV_BY_CONST: + /* Compute v = sqrt(-486664) * um * (x)^-1 */ + PKABigNumMultiplyStart(EDDSACC26X2_isoConst1, + curveEd25519->length, + SCRATCH_BUFFER_3, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_UM_X_INV_BY_CONST_RESULT: + + EDDSACC26X2_scratchBuffer3Size = SCRATCH_BUFFER_SIZE; + pkaResult = PKABigNumMultGetResult(SCRATCH_BUFFER_3, + &EDDSACC26X2_scratchBuffer3Size, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_WEIERY: + /* Compute v = sqrt(-486664) * um * (x)^-1 mod p */ + PKABigNumModStart(SCRATCH_BUFFER_3, + 2 * curveEd25519->length, + curveEd25519->prime, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_WEIERY_RESULT: + + pkaResult = PKABigNumModGetResult(SCRATCH_PUBLIC_Y, curveEd25519->length, EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MOD_SIG_DIGEST: + /* + * Perform -H(R || A || M) * A by first finding H(R || A || M) mod + * order + */ + PKABigNumModStart(object->EDDSACC26X2_GlobalWorkspace.digestResult2, + 2 * curveEd25519->length, + curveEd25519->order, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MOD_SIG_DIGEST_RESULT: + + pkaResult = PKABigNumModGetResult((uint8_t *)SCRATCH_PRIVATE_KEY, + curveEd25519->length, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_NEGATE_SIG_DIGEST: + /* + * Perform order - H(R || A || M) to get + * -H(R || A || M) mod order + */ + PKABigNumSubStart(curveEd25519->order, + curveEd25519->length, + (uint8_t *)SCRATCH_PRIVATE_KEY, + curveEd25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_NEGATE_SIG_DIGEST_RESULT: + + EDDSACC26X2_scratchPrivKeySize = SCRATCH_KEY_SIZE; + pkaResult = PKABigNumSubGetResult((uint8_t *)SCRATCH_PRIVATE_KEY, + &EDDSACC26X2_scratchPrivKeySize, + EDDSACC26X2_resultAddress); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_PUBLIC_KEY_BY_NEG_SIG_DIGEST: + /* Perform - H(R || A || M) * A using short Weierstrass curves */ + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + SCRATCH_PUBLIC_X, + SCRATCH_PUBLIC_Y, + curveWei25519->prime, + curveWei25519->a, + curveWei25519->b, + curveWei25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_PUBLIC_KEY_BY_NEG_SIG_DIGEST_RESULT: + + pkaResult = PKAEccMultiplyGetResult(object->EDDSACC26X2_GlobalWorkspace.xResult, + object->EDDSACC26X2_GlobalWorkspace.yResult, + EDDSACC26X2_resultAddress, + curveEd25519->length); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_MULT_BASE_POINT_BY_S: + + CryptoUtils_copyPad(object->operation.verify->S, SCRATCH_PRIVATE_KEY, curveWei25519->length); + + /* Perform S * B using short Weierstrass curves */ + PKAEccMultiplyStart((uint8_t *)SCRATCH_PRIVATE_KEY, + curveWei25519->generatorX, + curveWei25519->generatorY, + curveWei25519->prime, + curveWei25519->a, + curveWei25519->b, + curveWei25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_MULT_BASE_POINT_BY_S_RESULT: + + pkaResult = PKAEccMultiplyGetResult(SCRATCH_BUFFER_0, + SCRATCH_BUFFER_1, + EDDSACC26X2_resultAddress, + curveEd25519->length); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_ADD_POINTS: + /* + * Perform S * B - H(R || A || M) * A using short Weierstrass + * curves + */ + PKAEccAddStart(SCRATCH_BUFFER_0, + SCRATCH_BUFFER_1, + object->EDDSACC26X2_GlobalWorkspace.xResult, + object->EDDSACC26X2_GlobalWorkspace.yResult, + curveWei25519->prime, + curveWei25519->a, + curveWei25519->length, + &EDDSACC26X2_resultAddress); + + break; + + case EDDSACC26X2_FSM_VERIFY2_ADD_POINTS_RESULT: + + pkaResult = PKAEccAddGetResult(SCRATCH_PUBLIC_X, + SCRATCH_PUBLIC_Y, + EDDSACC26X2_resultAddress, + curveWei25519->length); + + return (EDDSACC26X2_convertReturnValue(pkaResult)); + + case EDDSACC26X2_FSM_VERIFY2_CONVERT_WEI_TO_ED: + /* + * Run through the substate FSM to convert the short Weierstrass + * point to an Edwards point. + */ + pkaResult = EDDSACC26X2_runWeiToEdFSM(handle); + + /* We break if we just started a PKA operation */ + if (pkaResult == EDDSACC26X2_PKA_OPERATION_STARTED) + { + break; + } + else /* Otherwise, convert the return value */ + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + + case EDDSACC26X2_FSM_VERIFY2_COMPARE_RESULT_R: + /* Encode the public key and check if it matches R */ + EDDSACC26X2_encodePublicKey(handle, + object->EDDSACC26X2_GlobalWorkspace.publicKey, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.xResult, + (const uint8_t *)object->EDDSACC26X2_GlobalWorkspace.yResult); + + /* Check R' == R, which indicates a valid signature */ + PKABigNumCmpStart(object->EDDSACC26X2_GlobalWorkspace.publicKey, + object->operation.verify->R, + curveEd25519->length); + + while (PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY) + { + continue; + } + + pkaResult = PKABigNumCmpGetResult(); + if (pkaResult == PKA_STATUS_EQUAL) + { + return (EDDSA_STATUS_SUCCESS); + } + else + { + return (EDDSACC26X2_convertReturnValue(pkaResult)); + } + default: + return (EDDSA_STATUS_ERROR); + } + + /* If we get to this point, we want to perform another PKA operation */ + IntPendClear(INT_PKA_IRQ); + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_STATUS_FSM_RUN_PKA_OP); +} + +/* + * ======== EDDSACC26X2_convertReturnValue ======== + */ +static int_fast16_t EDDSACC26X2_convertReturnValue(uint32_t pkaResult) +{ + switch (pkaResult) + { + case PKA_STATUS_SUCCESS: + + return (EDDSACC26X2_STATUS_FSM_RUN_FSM); + + case PKA_STATUS_X_ZERO: + case PKA_STATUS_Y_ZERO: + case PKA_STATUS_RESULT_0: + /* + * Theoretically, PKA_STATUS_RESULT_0 might be caused by other + * operations failing but the only one that really should yield + * 0 is ECC multiplication with invalid inputs that yield the + * point at infinity. + */ + return (EDDSA_STATUS_POINT_AT_INFINITY); + + case PKA_STATUS_X_LARGER_THAN_PRIME: + case PKA_STATUS_Y_LARGER_THAN_PRIME: + + return (EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE); + + case PKA_STATUS_POINT_NOT_ON_CURVE: + + return (EDDSA_STATUS_PUBLIC_KEY_NOT_ON_CURVE); + + default: + return (EDDSA_STATUS_ERROR); + } +} + +/* + * ======== EDDSACC26X2_waitForAccess ======== + */ +static int_fast16_t EDDSACC26X2_waitForAccess(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + uint32_t timeout; + + /* Set to SemaphoreP_NO_WAIT to start operations from SWI or HWI context */ + timeout = object->returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING ? object->semaphoreTimeout : SemaphoreP_NO_WAIT; + + return (SemaphoreP_pend(&PKAResourceCC26XX_accessSemaphore, timeout)); +} + +/* + * ======== EDDSACC26X2_waitForResult ======== + */ +static int_fast16_t EDDSACC26X2_waitForResult(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + + object->operationInProgress = true; + + switch (object->returnBehavior) + { + case EDDSA_RETURN_BEHAVIOR_POLLING: + while (!PKAResourceCC26XX_pollingFlag) + { + continue; + } + return (object->operationStatus); + case EDDSA_RETURN_BEHAVIOR_BLOCKING: + SemaphoreP_pend(&PKAResourceCC26XX_operationSemaphore, SemaphoreP_WAIT_FOREVER); + return (object->operationStatus); + case EDDSA_RETURN_BEHAVIOR_CALLBACK: + return (EDDSA_STATUS_SUCCESS); + default: + return (EDDSA_STATUS_ERROR); + } +} + +/* + * ======== EDDSA_init ======== + */ +void EDDSA_init(void) +{ + PKAResourceCC26XX_constructRTOSObjects(); + + EDDSACC26X2_isInitialized = true; +} + +/* + * ======== EDDSA_close ======== + */ +void EDDSA_close(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object; + + DebugP_assert(handle); + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the module as available */ + object->isOpen = false; + + /* Release power dependency on PKA Module. */ + Power_releaseDependency(PowerCC26X2_PERIPH_PKA); +} + +/* + * ======== EDDSA_construct ======== + */ +EDDSA_Handle EDDSA_construct(EDDSA_Config *config, const EDDSA_Params *params) +{ + EDDSA_Handle handle; + EDDSACC26X2_Object *object; + uint_fast8_t key; + + handle = (EDDSA_Handle)config; + object = handle->object; + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = (EDDSA_Params *)&EDDSA_defaultParams; + } + + key = HwiP_disable(); + + if (!EDDSACC26X2_isInitialized || object->isOpen) + { + HwiP_restore(key); + return (NULL); + } + + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK) ? params->callbackFxn : true); + + object->returnBehavior = params->returnBehavior; + +#if (TFM_ENABLED == 1) + curveEd25519 = &ECCParams_s_Ed25519; + curveWei25519 = &ECCParams_s_Wei25519; + + /* Always use the secure callback function */ + object->callbackFxn = params->callbackFxn; +#else + curveEd25519 = &ECCParams_Ed25519; + curveWei25519 = &ECCParams_Wei25519; + + object->callbackFxn = params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn + : EDDSACC26X2_internalCallbackFxn; + object->semaphoreTimeout = params->timeout; +#endif + + /* + * Set power dependency --> power up and enable clock for PKA + * (PKAResourceCC26XX) module. + */ + Power_setDependency(PowerCC26X2_PERIPH_PKA); + + return (handle); +} + +/* + * ======== EDDSA_generatePublicKey ======== + */ +int_fast16_t EDDSA_generatePublicKey(EDDSA_Handle handle, EDDSA_OperationGeneratePublicKey *operation) +{ + EDDSACC26X2_Object *object = handle->object; + EDDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + SHA2_Params sha2Params; + + /* Validate key sizes */ + if (((operation->myPrivateKey->encoding == CryptoKey_PLAINTEXT) && + (operation->myPrivateKey->u.plaintext.keyLength != operation->curve->length)) || + ((operation->myPrivateKey->encoding == CryptoKey_BLANK_KEYSTORE) && + (operation->myPrivateKey->u.keyStore.keyLength != operation->curve->length))) + { + return (EDDSA_STATUS_INVALID_PRIVATE_KEY_SIZE); + } + + if (((operation->myPublicKey->encoding == CryptoKey_BLANK_PLAINTEXT) && + (operation->myPublicKey->u.plaintext.keyLength != operation->curve->length)) || + ((operation->myPublicKey->encoding == CryptoKey_BLANK_KEYSTORE) && + (operation->myPublicKey->u.keyStore.keyLength != operation->curve->length))) + { + return (EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE); + } + + if (EDDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return (EDDSA_STATUS_PKA_UNAVAILABLE); + } + + /* + * Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operation.generatePublicKey = operation; + object->operationType = EDDSA_OPERATION_TYPE_GENERATE_PUBLIC_KEY; + object->fsmState = EDDSACC26X2_FSM_GEN_PUB_KEY_HASH_PRIVATE_KEY; + object->fsmSubState = EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION; + object->fsmFxn = EDDSACC26X2_runGeneratePublicKeyFSM; + object->operationStatus = EDDSACC26X2_STATUS_FSM_RUN_FSM; + object->operationCanceled = false; + + /* Hash and prune the private key */ + SHA2_init(); + + object->sha2HwAttrs.intPriority = hwAttrs->sha2IntPriority; + object->sha2Config.object = &object->sha2Object; + object->sha2Config.hwAttrs = &object->sha2HwAttrs; + + SHA2_Params_init(&sha2Params); + sha2Params.hashType = SHA2_HASH_TYPE_512; + sha2Params.returnBehavior = SHA2_RETURN_BEHAVIOR_CALLBACK; + sha2Params.callbackFxn = EDDSACC26X2_sha2Callback; + object->sha2Handle = SHA2_construct(&object->sha2Config, &sha2Params); + + if (object->sha2Handle == NULL) + { + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + return (EDDSA_STATUS_HASH_UNAVAILABLE); + } + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, EDDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_waitForResult(handle)); +} + +/* + * ======== EDDSA_sign ======== + */ +int_fast16_t EDDSA_sign(EDDSA_Handle handle, EDDSA_OperationSign *operation) +{ + EDDSACC26X2_Object *object = handle->object; + EDDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + SHA2_Params sha2Params; + + /* Validate key sizes */ + if (((operation->myPrivateKey->encoding == CryptoKey_PLAINTEXT) && + (operation->myPrivateKey->u.plaintext.keyLength != operation->curve->length)) || + ((operation->myPrivateKey->encoding == CryptoKey_KEYSTORE) && + (operation->myPrivateKey->u.keyStore.keyLength != operation->curve->length))) + { + return (EDDSA_STATUS_INVALID_PRIVATE_KEY_SIZE); + } + + if (((operation->myPublicKey->encoding == CryptoKey_PLAINTEXT) && + (operation->myPublicKey->u.plaintext.keyLength != operation->curve->length)) || + ((operation->myPublicKey->encoding == CryptoKey_KEYSTORE) && + (operation->myPublicKey->u.keyStore.keyLength != operation->curve->length))) + { + return (EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE); + } + + if (EDDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return (EDDSA_STATUS_PKA_UNAVAILABLE); + } + + /* + * Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operation.sign = operation; + object->operationType = EDDSA_OPERATION_TYPE_SIGN; + object->fsmState = EDDSACC26X2_FSM_SIGN1_HASH_PRIVATE_KEY; + object->fsmSubState = EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION; + object->fsmFxn = EDDSACC26X2_runSignFSM; + object->operationStatus = EDDSACC26X2_STATUS_FSM_RUN_FSM; + object->operationCanceled = false; + + /* Hash and prune the private key */ + SHA2_init(); + + object->sha2HwAttrs.intPriority = hwAttrs->sha2IntPriority; + object->sha2Config.object = &object->sha2Object; + object->sha2Config.hwAttrs = &object->sha2HwAttrs; + + SHA2_Params_init(&sha2Params); + sha2Params.hashType = SHA2_HASH_TYPE_512; + sha2Params.returnBehavior = SHA2_RETURN_BEHAVIOR_CALLBACK; + sha2Params.callbackFxn = EDDSACC26X2_sha2Callback; + object->sha2Handle = SHA2_construct(&object->sha2Config, &sha2Params); + + if (object->sha2Handle == NULL) + { + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + return (EDDSA_STATUS_HASH_UNAVAILABLE); + } + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, EDDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_waitForResult(handle)); +} + +/* + * ======== EDDSA_verify ======== + */ +int_fast16_t EDDSA_verify(EDDSA_Handle handle, EDDSA_OperationVerify *operation) +{ + EDDSACC26X2_Object *object = handle->object; + EDDSACC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + SHA2_Params sha2Params; + + /* Validate key sizes */ + if (((operation->theirPublicKey->encoding == CryptoKey_PLAINTEXT) && + (operation->theirPublicKey->u.plaintext.keyLength != operation->curve->length)) || + ((operation->theirPublicKey->encoding == CryptoKey_KEYSTORE) && + (operation->theirPublicKey->u.keyStore.keyLength != operation->curve->length))) + { + return (EDDSA_STATUS_INVALID_PUBLIC_KEY_SIZE); + } + + if (EDDSACC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return (EDDSA_STATUS_PKA_UNAVAILABLE); + } + + /* + * Copy over all parameters we will need access to in the FSM. + * The FSM runs in SWI context and thus needs to keep track of + * all of them somehow. + */ + object->operation.verify = operation; + object->operationType = EDDSA_OPERATION_TYPE_VERIFY; + object->fsmState = EDDSACC26X2_FSM_VERIFY1_HASH_SIG_R; + object->fsmSubState = EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION; + object->fsmFxn = EDDSACC26X2_runVerifyFSM; + object->operationStatus = EDDSACC26X2_STATUS_FSM_RUN_FSM; + object->operationCanceled = false; + + /* Hash and prune the private key */ + SHA2_init(); + + object->sha2HwAttrs.intPriority = hwAttrs->sha2IntPriority; + object->sha2Config.object = &object->sha2Object; + object->sha2Config.hwAttrs = &object->sha2HwAttrs; + + SHA2_Params_init(&sha2Params); + sha2Params.hashType = SHA2_HASH_TYPE_512; + sha2Params.returnBehavior = SHA2_RETURN_BEHAVIOR_CALLBACK; + sha2Params.callbackFxn = EDDSACC26X2_sha2Callback; + object->sha2Handle = SHA2_construct(&object->sha2Config, &sha2Params); + + if (object->sha2Handle == NULL) + { + SemaphoreP_post(&PKAResourceCC26XX_accessSemaphore); + + return (EDDSA_STATUS_HASH_UNAVAILABLE); + } + + /* + * We need to set the HWI function and priority since the same physical + * interrupt is shared by multiple drivers and they all need to coexist. + * Whenever a driver starts an operation, it registers its HWI callback + * with the OS. + */ + HwiP_setFunc(&PKAResourceCC26XX_hwi, EDDSACC26X2_hwiFxn, (uintptr_t)handle); + HwiP_setPriority(INT_PKA_IRQ, hwAttrs->intPriority); + + PKAResourceCC26XX_pollingFlag = 0; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * Run the FSM by triggering the interrupt. It is level triggered + * and the complement of the RUN bit. + */ + IntEnable(INT_PKA_IRQ); + + return (EDDSACC26X2_waitForResult(handle)); +} + +/* + * ======== EDDSA_cancelOperation ======== + */ +int_fast16_t EDDSA_cancelOperation(EDDSA_Handle handle) +{ + EDDSACC26X2_Object *object = handle->object; + + if (!object->operationInProgress) + { + return (EDDSA_STATUS_ERROR); + } + + object->operationCanceled = true; + + /* Post hwi as if operation finished for cleanup */ + IntEnable(INT_PKA_IRQ); + HwiP_post(INT_PKA_IRQ); + + return (EDDSA_STATUS_SUCCESS); +} diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.h b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.h new file mode 100644 index 00000000..ef0697b4 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X2.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2020-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** =========================================================================== + * @file EDDSACC26X2.h + * + * @brief EdDSA driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the + * EDDSA_config struct. + * + * # Hardware and Implementation Details # + * + * The CC26X2 family has a dedicated public key accelerator. + * It is capable of multiple mathematical operations including dedicated ECC + * point addition, doubling, and scalar multiplication. Only one operation can + * be carried out on the accelerator at a time. Mutual exclusion is + * implemented at the driver level and coordinated between all drivers relying + * on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The large number maths engine (LNME) uses a dedicated 2kB block of RAM + * (PKA RAM) for its operations. The operands of the maths operations must be + * copied into and results out of the PKA RAM. This necessitates a significant + * number of reads and writes for each operation. The bus interface to the RAM + * only allows for word-aligned reads and writes. The CPU splits the reads and + * writes from and to general SRAM from unaligned addresses into multiple + * bus operations while accumulating the data in a register until it is full. + * The result of this hardware process is that providing buffers such as + * plaintext CryptoKey keying material to ECC APIs that are word-aligned will + * significantly speed up the operation and + * reduce power consumption. + * + * The driver implementation does not perform runtime checks for most input + * parameters. Only values that are likely to have a stochastic element to + * them are checked (such as whether a driver is already open). Higher input + * parameter validation coverage is achieved by turning on assertions when + * compiling the driver. + * + * # Supported Curve Types # + * + * The driver implementation supports the following curves for EdDSA: + * + * | Curve | Supported | + * |--------------|-----------| + * | Ed25519 | Yes | + * | Ed448 | No | + * + * # Public Key Validation # + * + * When performing signature verification, the foreign public key will always + * be validated by performing a public key decompression followed by verifying + * that the point is on the Edwards curve. + */ + +#ifndef ti_drivers_eddsa_EDDSACC26X2__include +#define ti_drivers_eddsa_EDDSACC26X2__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exit the SWI and wait until an HWI call posts the SWI again */ +#define EDDSACC26X2_STATUS_FSM_RUN_PKA_OP EDDSA_STATUS_RESERVED - 0 +/* Execute the next FSM state immediately without waiting for the next HWI */ +#define EDDSACC26X2_STATUS_FSM_RUN_FSM EDDSA_STATUS_RESERVED - 1 +/* PKA operation started correctly (needed for subFSM functionality) */ +#define EDDSACC26X2_PKA_OPERATION_STARTED (0xFFFFFFFFUL) + +/*! + * @brief EDDSACC26X2 KeyGen, Sign, and Verify states + * + * The public key generation, sign, and verify operations are implemented + * using multiple individual PKA operations. Since state transitions for these + * operations are almost always predictable, the state transitions are encoded + * linearly in this enum. The FSM controller will increment the state counter + * and iterate through states until it is told to stop or restart. + */ +typedef enum +{ + EDDSACC26X2_FSM_ERROR, + + EDDSACC26X2_FSM_GEN_PUB_KEY_HASH_PRIVATE_KEY, + EDDSACC26X2_FSM_GEN_PUB_KEY_MULT_PRIV_KEY_BY_GENER_WEIER, + EDDSACC26X2_FSM_GEN_PUB_KEY_MULT_PRIV_KEY_BY_GENER_WEIER_RESULT, + EDDSACC26X2_FSM_GEN_PUB_KEY_CONVERT_WEI_TO_ED, + EDDSACC26X2_FSM_GEN_PUB_KEY_ENCODE_PUBLIC_KEY, + + EDDSACC26X2_FSM_SIGN1_HASH_PRIVATE_KEY, + EDDSACC26X2_FSM_SIGN1_HASH_UPPER_SECRET_KEY, + EDDSACC26X2_FSM_SIGN1_HASH_MESSAGE1, + EDDSACC26X2_FSM_SIGN1_HASH_MESSAGE2, + EDDSACC26X2_FSM_SIGN1_HASH_FINALIZE, + + EDDSACC26X2_FSM_SIGN2_MOD_SECRET_HASH, + EDDSACC26X2_FSM_SIGN2_MOD_SECRET_HASH_RESULT, + EDDSACC26X2_FSM_SIGN2_MULT_SECRET_HASH_BY_GENERATOR_WEIER, + EDDSACC26X2_FSM_SIGN2_MULT_SECRET_HASH_BY_GENERATOR_WEIER_RESULT, + EDDSACC26X2_FSM_SIGN2_CONVERT_WEI_TO_ED, + EDDSACC26X2_FSM_SIGN2_ENCODE_PUBLIC_KEY, + + EDDSACC26X2_FSM_SIGN3_HASH_SIG_R, + EDDSACC26X2_FSM_SIGN3_HASH_PUBLIC_KEY, + EDDSACC26X2_FSM_SIGN3_HASH_MESSAGE1, + EDDSACC26X2_FSM_SIGN3_HASH_MESSAGE2, + EDDSACC26X2_FSM_SIGN3_HASH_FINALIZE, + + EDDSACC26X2_FSM_SIGN4_MULT_SIG_HASH_BY_SECRET_KEY, + EDDSACC26X2_FSM_SIGN4_MULT_SIG_HASH_BY_SECRET_KEY_RESULT, + EDDSACC26X2_FSM_SIGN4_ADD_SECRET_HASH_TO_MULT, + EDDSACC26X2_FSM_SIGN4_ADD_SECRET_HASH_TO_MULT_RESULT, + EDDSACC26X2_FSM_SIGN4_MOD_S, + EDDSACC26X2_FSM_SIGN4_MOD_S_RESULT, + + EDDSACC26X2_FSM_VERIFY1_HASH_SIG_R, + EDDSACC26X2_FSM_VERIFY1_HASH_PUBLIC_KEY, + EDDSACC26X2_FSM_VERIFY1_HASH_MESSAGE1, + EDDSACC26X2_FSM_VERIFY1_HASH_MESSAGE2, + EDDSACC26X2_FSM_VERIFY1_HASH_FINALIZE, + + EDDSACC26X2_FSM_VERIFY1_S_IN_RANGE, + EDDSACC26X2_FSM_VERIFY1_A_IS_NOT_POINT_AT_INFINITY, + EDDSACC26X2_FSM_VERIFY1_MULT_Y_BY_Y, + EDDSACC26X2_FSM_VERIFY1_MULT_Y_BY_Y_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_Y2, + EDDSACC26X2_FSM_VERIFY1_MOD_Y2_RESULT, + EDDSACC26X2_FSM_VERIFY1_SUBTRACT_ONE_FROM_Y2, + EDDSACC26X2_FSM_VERIFY1_SUBTRACT_ONE_FROM_Y2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_D_BY_Y2, + EDDSACC26X2_FSM_VERIFY1_MULT_D_BY_Y2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_D_Y2, + EDDSACC26X2_FSM_VERIFY1_MOD_D_Y2_RESULT, + EDDSACC26X2_FSM_VERIFY1_ADD_ONE_TO_D_Y2, + EDDSACC26X2_FSM_VERIFY1_ADD_ONE_TO_D_Y2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_V_BY_V, + EDDSACC26X2_FSM_VERIFY1_MULT_V_BY_V_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_V2, + EDDSACC26X2_FSM_VERIFY1_MOD_V2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_V2_BY_V, + EDDSACC26X2_FSM_VERIFY1_MULT_V2_BY_V_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_V3, + EDDSACC26X2_FSM_VERIFY1_MOD_V3_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_V3_BY_U, + EDDSACC26X2_FSM_VERIFY1_MULT_V3_BY_U_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V3, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V3_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_V3, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_V3_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V6, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V6_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V6_BY_V, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V6_BY_V_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V7, + EDDSACC26X2_FSM_VERIFY1_MOD_U_V7_RESULT, + EDDSACC26X2_FSM_VERIFY1_EXP_U_V7, + EDDSACC26X2_FSM_VERIFY1_EXP_U_V7_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_EXP, + EDDSACC26X2_FSM_VERIFY1_MULT_U_V3_BY_EXP_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_CANDIDATE_X, + EDDSACC26X2_FSM_VERIFY1_MOD_CANDIDATE_X_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_X_BY_X, + EDDSACC26X2_FSM_VERIFY1_MULT_X_BY_X_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_X2, + EDDSACC26X2_FSM_VERIFY1_MOD_X2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MULT_X2_BY_V, + EDDSACC26X2_FSM_VERIFY1_MULT_X2_BY_V_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_V_X2, + EDDSACC26X2_FSM_VERIFY1_MOD_V_X2_RESULT, + EDDSACC26X2_FSM_VERIFY1_MOD_U, + EDDSACC26X2_FSM_VERIFY1_MOD_U_RESULT, + EDDSACC26X2_FSM_VERIFY1_NEGATE_U, + EDDSACC26X2_FSM_VERIFY1_NEGATE_U_RESULT, + EDDSACC26X2_FSM_VERIFY1_CHECK_SQUARE_ROOT, + + EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_P, + EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_P_RESULT, + EDDSACC26X2_FSM_VERIFY2_SUBTRACT_Y_FROM_P_PLUS_ONE, + EDDSACC26X2_FSM_VERIFY2_SUBTRACT_Y_FROM_P_PLUS_ONE_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_BY_X, + EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_BY_X_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_X, + EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_X_RESULT, + EDDSACC26X2_FSM_VERIFY2_INVERSION, + EDDSACC26X2_FSM_VERIFY2_INVERSION_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_X, + EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_X_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_INV, + EDDSACC26X2_FSM_VERIFY2_MOD_ONE_MINUS_Y_INV_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_ONE_MINUS_Y, + EDDSACC26X2_FSM_VERIFY2_MULT_INVERSE_BY_ONE_MINUS_Y_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_X_INV, + EDDSACC26X2_FSM_VERIFY2_MOD_X_INV_RESULT, + EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_Y, + EDDSACC26X2_FSM_VERIFY2_ADD_ONE_TO_Y_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_INV_BY_ONE_PLUS_Y, + EDDSACC26X2_FSM_VERIFY2_MULT_ONE_MINUS_Y_INV_BY_ONE_PLUS_Y_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_UM, + EDDSACC26X2_FSM_VERIFY2_MOD_UM_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_UM_BY_X_INV, + EDDSACC26X2_FSM_VERIFY2_MULT_UM_BY_X_INV_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_UM_X_INV, + EDDSACC26X2_FSM_VERIFY2_MOD_UM_X_INV_RESULT, + EDDSACC26X2_FSM_VERIFY2_ADD_CONST_TO_UM, + EDDSACC26X2_FSM_VERIFY2_ADD_CONST_TO_UM_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_WEIERX, + EDDSACC26X2_FSM_VERIFY2_MOD_WEIERX_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_UM_X_INV_BY_CONST, + EDDSACC26X2_FSM_VERIFY2_MULT_UM_X_INV_BY_CONST_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_WEIERY, + EDDSACC26X2_FSM_VERIFY2_MOD_WEIERY_RESULT, + EDDSACC26X2_FSM_VERIFY2_MOD_SIG_DIGEST, + EDDSACC26X2_FSM_VERIFY2_MOD_SIG_DIGEST_RESULT, + EDDSACC26X2_FSM_VERIFY2_NEGATE_SIG_DIGEST, + EDDSACC26X2_FSM_VERIFY2_NEGATE_SIG_DIGEST_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_PUBLIC_KEY_BY_NEG_SIG_DIGEST, + EDDSACC26X2_FSM_VERIFY2_MULT_PUBLIC_KEY_BY_NEG_SIG_DIGEST_RESULT, + EDDSACC26X2_FSM_VERIFY2_MULT_BASE_POINT_BY_S, + EDDSACC26X2_FSM_VERIFY2_MULT_BASE_POINT_BY_S_RESULT, + EDDSACC26X2_FSM_VERIFY2_ADD_POINTS, + EDDSACC26X2_FSM_VERIFY2_ADD_POINTS_RESULT, + EDDSACC26X2_FSM_VERIFY2_CONVERT_WEI_TO_ED, + EDDSACC26X2_FSM_VERIFY2_COMPARE_RESULT_R, + +} EDDSACC26X2_FsmState; + +/*! + * @brief EDDSACC26X2 Weierstrass to Edwards states + * + * The public key generation, sign, and verify operations all use a common + * subroutine that converts an input point on the short Weierstrass curve + * Wei25519 to an output point on the twisted Edwards curve Ed25519. + * Since state transitions for these operations are almost always + * predictable, the state transitions are encoded linearly in this enum. + * The FSM controller will increment the substate counter and iterate through + * states until it is told to stop or restart. + */ +typedef enum +{ + EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION, + EDDSACC26X2_SUBFSM_WEI_TO_MONT_ADDITION_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_ADD_ONE, + EDDSACC26X2_SUBFSM_MONT_TO_ED_ADD_ONE_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_MULT_V, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_MULT_V_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_INVERSION, + EDDSACC26X2_SUBFSM_MONT_TO_ED_INVERSION_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE1, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE1_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE2, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_INVERSE2_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_SUB_ONE, + EDDSACC26X2_SUBFSM_MONT_TO_ED_SUB_ONE_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_SUB, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_SUB_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_RETRIEVE_Y, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_RETRIEVE_Y_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_Y, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_Y_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_U_MULT_ISO_CONST, + EDDSACC26X2_SUBFSM_MONT_TO_ED_U_MULT_ISO_CONST_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_INVERSE, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MULT_V_INVERSE_RESULT, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_X, + EDDSACC26X2_SUBFSM_MONT_TO_ED_MOD_X_RESULT, +} EDDSACC26X2_FsmSubState; + +/*! + * @brief EDDSACC26X2 state machine function prototype + * + * The FSM controller in the EDDSACC26X2 SWI executes a state machine function + * containing a switch statement that governs state execution. This function + * pointer is stored in the object at the beginning of the transaction. + * This way, unused state machines are removed at link time. + */ +typedef int_fast16_t (*EDDSACC26X2_stateMachineFxn)(EDDSA_Handle handle); + +/*! + * @brief EDDSACC26X2 Hardware Attributes + * + * EDDSACC26X2 hardware attributes should be included in the board file + * and pointed to by the EDDSA_config struct. + */ +typedef struct +{ + /*! + * @brief PKA Peripheral's interrupt priority. + * + * The CC26xx uses three of the priority bits, meaning ~0 has the same + * effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + * interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + uint8_t sha2IntPriority; +} EDDSACC26X2_HWAttrs; + +#define ED25519_LENGTH 32 + +/*! + * @brief EDDSACC26X2 Workspace + * + * Holds intermediate memory to perform Ed25519 operations. Unlike PKA SRAM, + * these values can be easily accessed or modified. + */ +typedef struct +{ + uint8_t digestResult[SHA2_DIGEST_LENGTH_BYTES_512]; + uint8_t digestResult2[SHA2_DIGEST_LENGTH_BYTES_512]; + uint8_t publicKey[ED25519_LENGTH]; + uint8_t secretScalar[ED25519_LENGTH]; + uint8_t xResult[ED25519_LENGTH]; + uint8_t yResult[ED25519_LENGTH]; + uint8_t x_0; +} EDDSACC26X2_Workspace; + +/*! + * @brief EDDSACC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* + * Note that sha2Config must be the first member so that we can use the + * SHA2 callback in the EdDSA driver. + */ + SHA2_Config sha2Config; + SHA2CC26X2_Object sha2Object; + SHA2CC26X2_HWAttrs sha2HwAttrs; + SHA2_Handle sha2Handle; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + EDDSA_Operation operation; + EDDSA_OperationType operationType; + EDDSA_CallbackFxn callbackFxn; + EDDSACC26X2_stateMachineFxn fsmFxn; + EDDSA_ReturnBehavior returnBehavior; + EDDSACC26X2_FsmState fsmState; + EDDSACC26X2_FsmSubState fsmSubState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; + uint32_t *scratchNumber1; + uint32_t *scratchNumber2; + EDDSACC26X2_Workspace EDDSACC26X2_GlobalWorkspace; +} EDDSACC26X2_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_eddsa_EDDSACC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.c new file mode 100644 index 00000000..bf120d1b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.c @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static volatile bool EDDSACC26X4_ns_pollingDone; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +/* Extern globals */ +extern const EDDSA_Params EDDSA_defaultParams; +extern EDDSA_s_SecureCallback eddsaSecureCB_ns[]; +extern EDDSACC26X4_ns_Object eddsaObject_ns[]; + +/* + * ======== EDDSA_ns_callbackFxn ======== + */ +void EDDSA_ns_callbackFxn(uintptr_t arg) +{ + EDDSA_s_SecureCallback *secureCallbackObject = (EDDSA_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + CryptoPSACC26X4_releaseLock(); + + if (eddsaObject_ns[index].returnBehavior == EDDSA_RETURN_BEHAVIOR_POLLING) + { + EDDSACC26X4_ns_pollingDone = true; + } + else if (eddsaObject_ns[index].returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + eddsaObject_ns[index].callbackFxn(eddsaSecureCB_ns[index].handle, + eddsaSecureCB_ns[index].returnStatus, + eddsaSecureCB_ns[index].operation, + eddsaSecureCB_ns[index].operationType); + } +} + +/* + * ======== EDDSA_ns_registerCallback ======== + */ +static psa_status_t EDDSA_ns_registerCallback(EDDSA_Handle handle, const EDDSA_Params *params) +{ + EDDSA_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&eddsaSecureCB_ns[index].object, + EDDSA_ns_callbackFxn, + (uintptr_t)&eddsaSecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &eddsaSecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== EDDSA_ns_waitForResult ======== + */ +static void EDDSA_ns_waitForResult(int_fast16_t *result, uint8_t objectIndex) +{ + if (*result != EDDSA_STATUS_SUCCESS) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (eddsaObject_ns[objectIndex].returnBehavior == EDDSA_RETURN_BEHAVIOR_POLLING) + { + /* + * Emulate polling mode by spinning on a flag which will be set by + * the callback function + */ + while (!EDDSACC26X4_ns_pollingDone) {} + *result = eddsaSecureCB_ns[objectIndex].returnStatus; + } + else if (eddsaObject_ns[objectIndex].returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + *result = eddsaSecureCB_ns[objectIndex].returnStatus; + } +} + +/* + * ======== EDDSA_init ======== + */ +void EDDSA_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== EDDSA_open ======== + */ +EDDSA_Handle EDDSA_open(uint_least8_t index, const EDDSA_Params *params) +{ + EDDSA_Handle handle = NULL; + EDDSA_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (EDDSA_Params *)&EDDSA_defaultParams; + } + + DebugP_assert(params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_OPEN, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (EDDSA_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + eddsaObject_ns[index].returnBehavior = params->returnBehavior; + eddsaObject_ns[index].callbackFxn = params->callbackFxn; + eddsaObject_ns[index].semaphoreTimeout = (params->returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + + /* Set power dependency - i.e. power up and enable clock for Crypto. + * This is required since EdDSA uses SHA-2. + */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== EDDSA_construct ======== + */ +EDDSA_Handle EDDSA_construct(EDDSA_Config *config, const EDDSA_Params *params) +{ + EDDSA_Handle handle = NULL; + EDDSA_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (EDDSA_Params *)&EDDSA_defaultParams; + } + + DebugP_assert(params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if (handle != NULL) + { + /* Register NS callback regardless of return behavior */ + if (EDDSA_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + eddsaObject_ns[index].returnBehavior = params->returnBehavior; + eddsaObject_ns[index].callbackFxn = params->callbackFxn; + eddsaObject_ns[index].semaphoreTimeout = (params->returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency - i.e. power up and enable clock for PKA */ + (void)Power_setDependency(PowerCC26X2_PERIPH_PKA); + + /* Set power dependency - i.e. power up and enable clock for Crypto. + * This is required since EdDSA uses SHA-2. + */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== EDDSA_close ======== + */ +void EDDSA_close(EDDSA_Handle handle) +{ + EDDSA_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&eddsaSecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependencies */ + (void)Power_releaseDependency(PowerCC26X2_PERIPH_PKA); + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== EDDSA_generatePublicKey ======== + */ +int_fast16_t EDDSA_generatePublicKey(EDDSA_Handle handle, EDDSA_OperationGeneratePublicKey *operation) +{ + EDDSA_s_GenPublicKeyMsg genKeyMsg; + int_fast16_t result = EDDSA_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + genKeyMsg.handle = handle; + genKeyMsg.operation = operation; + invecs[0].base = &genKeyMsg; + invecs[0].len = sizeof(genKeyMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(eddsaObject_ns[index].semaphoreTimeout) == false) + { + return EDDSA_STATUS_PKA_UNAVAILABLE; + } + + EDDSACC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to EDDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_GEN_PUBLIC_KEY, invecs, outvecs); + + EDDSA_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== EDDSA_sign ======== + */ +int_fast16_t EDDSA_sign(EDDSA_Handle handle, EDDSA_OperationSign *operation) +{ + EDDSA_s_SignMsg signMsg; + int_fast16_t result = EDDSA_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + signMsg.handle = handle; + signMsg.operation = operation; + invecs[0].base = &signMsg; + invecs[0].len = sizeof(signMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(eddsaObject_ns[index].semaphoreTimeout) == false) + { + return EDDSA_STATUS_PKA_UNAVAILABLE; + } + + EDDSACC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to EDDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_SIGN, invecs, outvecs); + + EDDSA_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== EDDSA_verify ======== + */ +int_fast16_t EDDSA_verify(EDDSA_Handle handle, EDDSA_OperationVerify *operation) +{ + EDDSA_s_VerifyMsg verifyMsg; + int_fast16_t result; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(params->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + verifyMsg.handle = handle; + verifyMsg.operation = operation; + invecs[0].base = &verifyMsg; + invecs[0].len = sizeof(verifyMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(eddsaObject_ns[index].semaphoreTimeout) == false) + { + return EDDSA_STATUS_PKA_UNAVAILABLE; + } + + EDDSACC26X4_ns_pollingDone = false; + + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to EDDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_VERIFY, invecs, outvecs); + + EDDSA_ns_waitForResult(&result, index); + + return (result); +} + +/* + * ======== EDDSA_cancelOperation ======== + */ +int_fast16_t EDDSA_cancelOperation(EDDSA_Handle handle) +{ + EDDSA_s_CancelOperationMsg cancelMsg; + int_fast16_t result = EDDSA_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to EDDSA_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(EDDSA_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.h new file mode 100644 index 00000000..152a0633 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file EDDSACC26X4_ns.h + * + * @brief EdDSA Non-secure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_eddsa_EDDSACC26X4_ns__include +#define ti_drivers_eddsa_EDDSACC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief EDDSAC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + EDDSA_CallbackFxn callbackFxn; + EDDSA_ReturnBehavior returnBehavior; +} EDDSACC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_eddsa_EDDSACC26X4_ns__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.c b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.c new file mode 100644 index 00000000..5abe55c6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.c @@ -0,0 +1,1061 @@ +/* + * Copyright (c) 2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "EDDSACC26X4_s.h" + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include /* TI CMSE helper functions */ + +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +#define EDDSA_SECURE_OPERATION_COUNT EDDSA_SECURE_CALLBACK_COUNT + +/*! + * @brief Union containing all supported operation structs. + */ +typedef union +{ + EDDSA_OperationGeneratePublicKey generatePublicKey; + EDDSA_OperationSign sign; + EDDSA_OperationVerify verify; +} EDDSA_OperationUnion; + +/* + * Stores the following: + * - Secure copy of the operation and the original pointer to the non-secure + * operation to return when the HWI callback occurs. + * - Secure copy of the public & private keys and the original pointer to the non-secure + * public key to update the key encoding return when the HWI callback occurs. + */ +typedef struct +{ + EDDSA_Operation operation_ns; /* Pointer to non-secure operation */ + EDDSA_OperationUnion operation_s; /* Secure copy of operation */ + CryptoKey publicKey_s; /* Secure copy of public key */ + CryptoKey privateKey_s; /* Secure copy of private key (not used for verify operation) */ + CryptoKey *publicKey_ns; /* Pointer to non-secure public key */ +} EDDSA_s_Operation; + +static EDDSA_s_Operation EDDSA_s_operation; + +/* + * EDDSA Secure Dynamic Instance struct. + */ +typedef struct +{ + EDDSA_Config config; + EDDSACC26X2_Object object; + EDDSACC26X2_HWAttrs hwAttrs; +} EDDSA_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * EDDSA_construct. + */ +static EDDSA_s_DynamicInstance EDDSA_s_dynInstance[CONFIG_EDDSA_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure EDDSA_s_SecureCallbacks for each driver instance opened or constructed */ +static EDDSA_s_SecureCallback *EDDSA_s_secureCB[EDDSA_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const EDDSA_Config EDDSA_config[]; + +/* + * ======== EDDSA_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t EDDSA_s_getCallbackIndex(EDDSA_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_EDDSA_COUNT; index++) + { + if (handle_s == (EDDSA_Handle)&EDDSA_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_EDDSA_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &EDDSA_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_EDDSA_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== EDDSA_s_hwiCallback ======== + */ +static void EDDSA_s_hwiCallback(EDDSA_Handle handle_s, + int_fast16_t returnStatus, + EDDSA_Operation operation, + EDDSA_OperationType operationType) +{ + EDDSA_s_SecureCallback *eddsaSecureCB_ns; + int8_t index; + + index = EDDSA_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < EDDSA_SECURE_CALLBACK_COUNT)) + { + eddsaSecureCB_ns = EDDSA_s_secureCB[index]; + + if (eddsaSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler + */ + eddsaSecureCB_ns->handle = (EDDSA_Handle)(CRYPTO_S_HANDLE_ID_EDDSA | index); + eddsaSecureCB_ns->returnStatus = returnStatus; + eddsaSecureCB_ns->operation = EDDSA_s_operation.operation_ns; + eddsaSecureCB_ns->operationType = operationType; + + if (operationType == EDDSA_OPERATION_TYPE_GENERATE_PUBLIC_KEY) + { + /* Copy updated key encoding to the non-secure public key struct */ + EDDSA_s_operation.publicKey_ns->encoding = operation.generatePublicKey->myPublicKey->encoding; + + if (EDDSA_s_operation.publicKey_ns->encoding == CryptoKey_KEYSTORE) + { + /* Copy the updated keyID to the non-secure public key struct */ + EDDSA_s_operation.publicKey_ns->u.keyStore.keyID = operation.generatePublicKey->myPublicKey->u + .keyStore.keyID; + } + } + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&eddsaSecureCB_ns->object); + } + } +} + +/* + * ======== EDDSA_s_copyConfig ======== + */ +static inline psa_status_t EDDSA_s_copyConfig(EDDSA_Config **secureConfig, + const EDDSA_Config *config, + EDDSA_Handle *retHandle) +{ + EDDSA_Config *config_s; + EDDSA_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_EDDSA_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &EDDSA_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + EDDSA_s_secureCB[i + CONFIG_TI_DRIVERS_EDDSA_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_EDDSA OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (EDDSA_Handle)(CRYPTO_S_HANDLE_ID_EDDSA | (i + CONFIG_TI_DRIVERS_EDDSA_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== EDDSA_s_releaseConfig ======== + */ +static inline void EDDSA_s_releaseConfig(EDDSA_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_EDDSA) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_EDDSA_COUNT) && (i < EDDSA_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + EDDSA_s_dynInstance[i - CONFIG_TI_DRIVERS_EDDSA_COUNT].config.object = NULL; + } + } +} + +/* + * ======== EDDSA_s_copyGenPublicKeyOperation ======== + */ +static inline psa_status_t EDDSA_s_copyGenPublicKeyOperation(EDDSA_OperationGeneratePublicKey *secureOperation, + CryptoKey *securePublicKey, + CryptoKey *securePrivateKey, + const EDDSA_OperationGeneratePublicKey *operation) +{ + const ECCParams_CurveParams *curveParams_s; + ECCParams_ns_CurveParams curveParams_ns; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(EDDSA_OperationGeneratePublicKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(EDDSA_OperationGeneratePublicKey)); + + /* Make a local copy of the param struct to avoid typecast */ + (void)spm_memcpy(&curveParams_ns, (void *)secureOperation->curve, sizeof(curveParams_ns)); + + /* Validate curve is Ed25519 */ + if (curveParams_ns.secureCurve != ECCParams_SecureCurve_Ed25519) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Get pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* + * Make a secure copy of the private key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureOutputKey(securePublicKey, &secureOperation->myPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_copySignOperation ======== + */ +static inline psa_status_t EDDSA_s_copySignOperation(EDDSA_OperationSign *secureOperation, + CryptoKey *securePublicKey, + CryptoKey *securePrivateKey, + const EDDSA_OperationSign *operation) +{ + const ECCParams_CurveParams *curveParams_s; + ECCParams_ns_CurveParams curveParams_ns; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(EDDSA_OperationSign)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(EDDSA_OperationSign)); + + /* Make a local copy of the param struct to avoid typecast */ + (void)spm_memcpy(&curveParams_ns, (void *)secureOperation->curve, sizeof(curveParams_ns)); + + /* Validate curve is Ed25519 */ + if (curveParams_ns.secureCurve != ECCParams_SecureCurve_Ed25519) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Get pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate pre-hashed message address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->preHashedMessage, + secureOperation->preHashedMessageLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate signature R component address range */ + if (cmse_has_unpriv_nonsecure_rw_access((void *)secureOperation->R, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate signature S component address range */ + if (cmse_has_unpriv_nonsecure_rw_access((void *)secureOperation->S, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePublicKey, &secureOperation->myPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the private key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePrivateKey, &secureOperation->myPrivateKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_copyVerifyOperation ======== + */ +static inline psa_status_t EDDSA_s_copyVerifyOperation(EDDSA_OperationVerify *secureOperation, + CryptoKey *securePublicKey, + const EDDSA_OperationVerify *operation) +{ + const ECCParams_CurveParams *curveParams_s; + ECCParams_ns_CurveParams curveParams_ns; + int_fast16_t status; + + /* Validate operation struct address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)operation, sizeof(EDDSA_OperationVerify)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the operation struct */ + (void)spm_memcpy(secureOperation, operation, sizeof(EDDSA_OperationVerify)); + + /* Make a local copy of the param struct to avoid typecast */ + (void)spm_memcpy(&curveParams_ns, (void *)secureOperation->curve, sizeof(curveParams_ns)); + + /* Validate curve is Ed25519 */ + if (curveParams_ns.secureCurve != ECCParams_SecureCurve_Ed25519) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Get pointer to secure curve params */ + curveParams_s = ECCParams_s_getCurveParams(secureOperation->curve); + if (curveParams_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Update the operation struct to point to secure curve params */ + secureOperation->curve = curveParams_s; + + /* Validate pre-hashed message address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->preHashedMessage, + secureOperation->preHashedMessageLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate signature R component address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->R, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate signature S component address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)secureOperation->S, curveParams_s->length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* + * Make a secure copy of the public key struct and update the operation + * struct to point to the secure key copy. + */ + status = CryptoKey_copySecureInputKey(securePublicKey, &secureOperation->theirPublicKey); + if (status != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_copyParams ======== + */ +static psa_status_t EDDSA_s_copyParams(EDDSA_Params *secureParams, const EDDSA_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(EDDSA_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(EDDSA_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == EDDSA_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == EDDSA_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == EDDSA_RETURN_BEHAVIOR_POLLING)) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using EDDSA_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = EDDSA_s_hwiCallback; + + /* + * The underlying EDDSA driver is interrupt-driven regardless of the + * return behavior specified. Since secure partitions cannot process + * interrupt signals while a PSA call is running, callback return + * behavior must be forced in all app-specified return behaviors + * including polling. + */ + secureParams->returnBehavior = EDDSA_RETURN_BEHAVIOR_CALLBACK; + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== EDDSA_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static EDDSA_Handle EDDSA_s_getHandle(EDDSA_Handle nsHandle) +{ + EDDSA_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_EDDSA) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_EDDSA_COUNT) + { + secureHandle = (EDDSA_Handle)&EDDSA_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_EDDSA_COUNT) && (i < EDDSA_SECURE_CALLBACK_COUNT)) + { + secureHandle = &EDDSA_s_dynInstance[i - CONFIG_TI_DRIVERS_EDDSA_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== EDDSA_s_registerCallback ======== + */ +static inline psa_status_t EDDSA_s_registerCallback(psa_msg_t *msg) +{ + EDDSA_Handle handle_s; + EDDSA_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = EDDSA_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = EDDSA_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < EDDSA_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(EDDSA_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to EDDSA_s_SecureCallback located in + * non-secure memory. + */ + EDDSA_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== EDDSA_s_construct ======== + */ +static inline psa_status_t EDDSA_s_construct(psa_msg_t *msg) +{ + EDDSA_s_ConstructMsg constructMsg; + EDDSA_Handle handle; + EDDSA_Params params_s; + const EDDSA_Params *paramsPtr_s = NULL; + EDDSA_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + EDDSA_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = EDDSA_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = EDDSA_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = EDDSA_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_open ======== + */ +static inline psa_status_t EDDSA_s_open(psa_msg_t *msg) +{ + EDDSA_s_OpenMsg openMsg; + EDDSA_Handle handle; + EDDSA_Params params_s; + EDDSA_Params *paramsPtr_s = NULL; + EDDSA_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Copy params to secure memory and force callback mode, + * substituting our own callback function. + */ + status = EDDSA_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = EDDSA_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + EDDSA_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_EDDSA OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (EDDSA_Handle)(CRYPTO_S_HANDLE_ID_EDDSA | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_close ======== + */ +static inline psa_status_t EDDSA_s_close(psa_msg_t *msg) +{ + EDDSA_Handle handle_s; + EDDSA_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = EDDSA_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + EDDSA_close(handle_s); + + /* Release the secure config if it is a dynamic */ + EDDSA_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + EDDSA_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_generatePublicKey ======== + */ +static inline psa_status_t EDDSA_s_generatePublicKey(psa_msg_t *msg) +{ + EDDSA_s_GenPublicKeyMsg genPubKeyMsg; + EDDSA_Handle handle_s; + EDDSA_OperationGeneratePublicKey *operation_s; + CryptoKey *publicKey_s = &EDDSA_s_operation.publicKey_s; + CryptoKey *privateKey_s = &EDDSA_s_operation.privateKey_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(genPubKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genPubKeyMsg, sizeof(genPubKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = EDDSA_s_getHandle(genPubKeyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &EDDSA_s_operation.operation_s.generatePublicKey; + + /* Save pointer to non-secure operation struct */ + EDDSA_s_operation.operation_ns = (EDDSA_Operation)genPubKeyMsg.operation; + + /* Save pointer to non-secure public key */ + EDDSA_s_operation.publicKey_ns = genPubKeyMsg.operation->myPublicKey; + + /* Validate and copy operation and key structs */ + status = EDDSA_s_copyGenPublicKeyOperation(operation_s, publicKey_s, privateKey_s, genPubKeyMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = EDDSA_generatePublicKey(handle_s, operation_s); + } + else /* Secure client */ + { + ret = EDDSA_generatePublicKey(genPubKeyMsg.handle, genPubKeyMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== EDDSA_s_sign ======== + */ +static inline psa_status_t EDDSA_s_sign(psa_msg_t *msg) +{ + EDDSA_s_SignMsg signMsg; + EDDSA_Handle handle_s; + EDDSA_OperationSign *operation_s; + CryptoKey *publicKey_s = &EDDSA_s_operation.publicKey_s; + CryptoKey *privateKey_s = &EDDSA_s_operation.privateKey_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(signMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &signMsg, sizeof(signMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = EDDSA_s_getHandle(signMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &EDDSA_s_operation.operation_s.sign; + + /* Save pointer to non-secure operation struct */ + EDDSA_s_operation.operation_ns = (EDDSA_Operation)signMsg.operation; + + /* Validate and copy operation and key structs */ + status = EDDSA_s_copySignOperation(operation_s, publicKey_s, privateKey_s, signMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = EDDSA_sign(handle_s, operation_s); + } + else /* Secure client */ + { + ret = EDDSA_sign(signMsg.handle, signMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== EDDSA_s_verify ======== + */ +static inline psa_status_t EDDSA_s_verify(psa_msg_t *msg) +{ + EDDSA_s_VerifyMsg verifyMsg; + EDDSA_Handle handle_s; + EDDSA_OperationVerify *operation_s; + CryptoKey *publicKey_s = &EDDSA_s_operation.publicKey_s; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + + if ((msg->in_size[0] != sizeof(verifyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &verifyMsg, sizeof(verifyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = EDDSA_s_getHandle(verifyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + operation_s = &EDDSA_s_operation.operation_s.verify; + + /* Save pointer to non-secure operation struct */ + EDDSA_s_operation.operation_ns = (EDDSA_Operation)verifyMsg.operation; + + /* Validate and copy operation and key structs */ + status = EDDSA_s_copyVerifyOperation(operation_s, publicKey_s, verifyMsg.operation); + if (status != PSA_SUCCESS) + { + return status; + } + + ret = EDDSA_verify(handle_s, operation_s); + } + else /* Secure client */ + { + ret = EDDSA_verify(verifyMsg.handle, verifyMsg.operation); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== EDDSA_s_cancelOperation ======== + */ +static inline psa_status_t EDDSA_s_cancelOperation(psa_msg_t *msg) +{ + EDDSA_Handle handle_s; + EDDSA_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = EDDSA_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = EDDSA_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== EDDSA_s_handlePsaMsg ======== + */ +psa_status_t EDDSA_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If EDDSA_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case EDDSA_S_MSG_TYPE_CONSTRUCT: + status = EDDSA_s_construct(msg); + break; + + case EDDSA_S_MSG_TYPE_OPEN: + status = EDDSA_s_open(msg); + break; + + /* + * EDDSA_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case EDDSA_S_MSG_TYPE_REGISTER_CALLBACK: + status = EDDSA_s_registerCallback(msg); + break; + + case EDDSA_S_MSG_TYPE_CLOSE: + status = EDDSA_s_close(msg); + break; + + case EDDSA_S_MSG_TYPE_GEN_PUBLIC_KEY: + status = EDDSA_s_generatePublicKey(msg); + break; + + case EDDSA_S_MSG_TYPE_SIGN: + status = EDDSA_s_sign(msg); + break; + + case EDDSA_S_MSG_TYPE_VERIFY: + status = EDDSA_s_verify(msg); + break; + + /* + * EDDSA_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case EDDSA_S_MSG_TYPE_CANCEL_OPERATION: + status = EDDSA_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== EDDSA_s_init ======== + */ +void EDDSA_s_init(void) +{ + EDDSA_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.h b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.h new file mode 100644 index 00000000..6bf13635 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/eddsa/EDDSACC26X4_s.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_eddsa_EDDSACC26X4_s__include +#define ti_drivers_eddsa_EDDSACC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * EDDSA secure message types + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * EDDSA secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +#define EDDSA_S_MSG_TYPE_CONSTRUCT EDDSA_S_MSG_TYPE(0U) +#define EDDSA_S_MSG_TYPE_OPEN EDDSA_S_MSG_TYPE(1U) +#define EDDSA_S_MSG_TYPE_REGISTER_CALLBACK EDDSA_S_MSG_TYPE(2U) +#define EDDSA_S_MSG_TYPE_CLOSE EDDSA_S_MSG_TYPE(3U) +#define EDDSA_S_MSG_TYPE_GEN_PUBLIC_KEY EDDSA_S_MSG_TYPE(4U) +#define EDDSA_S_MSG_TYPE_SIGN EDDSA_S_MSG_TYPE(5U) +#define EDDSA_S_MSG_TYPE_VERIFY EDDSA_S_MSG_TYPE(6U) +#define EDDSA_S_MSG_TYPE_CANCEL_OPERATION EDDSA_S_MSG_TYPE(7U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using EDDSA_construct(). + */ +#ifndef CONFIG_EDDSA_S_CONFIG_POOL_SIZE + #define CONFIG_EDDSA_S_CONFIG_POOL_SIZE 1 +#endif + +#define EDDSA_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_EDDSA_COUNT + CONFIG_EDDSA_S_CONFIG_POOL_SIZE) + +/* + * ========= EDDSA Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* EDDSA callback fxn parameters */ + EDDSA_Handle handle; + int_fast16_t returnStatus; + EDDSA_Operation operation; + EDDSA_OperationType operationType; +} EDDSA_s_SecureCallback; + +/* + * ========= EDDSA Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * EDDSA secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + EDDSA_Config *config; + const EDDSA_Params *params; +} EDDSA_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const EDDSA_Params *params; +} EDDSA_s_OpenMsg; + +typedef struct +{ + EDDSA_Handle handle; + EDDSA_s_SecureCallback *callback; +} EDDSA_s_CallbackMsg; + +typedef struct +{ + EDDSA_Handle handle; +} EDDSA_s_CloseMsg; + +typedef struct +{ + EDDSA_Handle handle; + EDDSA_OperationGeneratePublicKey *operation; +} EDDSA_s_GenPublicKeyMsg; + +typedef struct +{ + EDDSA_Handle handle; + EDDSA_OperationSign *operation; +} EDDSA_s_SignMsg; + +typedef struct +{ + EDDSA_Handle handle; + EDDSA_OperationVerify *operation; +} EDDSA_s_VerifyMsg; + +typedef struct +{ + EDDSA_Handle handle; +} EDDSA_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for EDDSA secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t EDDSA_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the EDDSA secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void EDDSA_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_eddsa_EDDSACC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X2.c b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X2.c new file mode 100644 index 00000000..ccf31add --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X2.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(inc/hw_gpio.h) +#include DeviceFamily_constructPath(inc/hw_aon_event.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +static bool initCalled = false; + +// HW interrupt structure for I/O interrupt handler +static HwiP_Struct gpioHwi; + +// Link to config values defined by sysconfig +extern GPIO_Config GPIO_config; +extern const uint_least8_t GPIO_pinLowerBound; +extern const uint_least8_t GPIO_pinUpperBound; + +/* + * ======== GPIO_intEnabled ======== + */ +static inline bool GPIO_intEnabled(uint32_t index) +{ + return ((HWREG(IOC_BASE + IOC_O_IOCFG0 + (4 * index)) & IOC_IOCFG0_EDGE_IRQ_EN) ? true : false); +} + +/* + * ======== GPIO_hwiIntFxn ======== + * Hwi function that processes GPIO interrupts. + */ +void GPIO_hwiIntFxn(uintptr_t arg) +{ + uint32_t flagIndex; + uint32_t eventMask = HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0); + + // Clear the interrupt mask + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = eventMask; + + while (eventMask) + { + // MASK_TO_PIN only detects the highest set bit + flagIndex = GPIO_MASK_TO_PIN(eventMask); + + // So it's safe to use PIN_TO_MASK to clear that bit + eventMask &= ~GPIO_PIN_TO_MASK(flagIndex); + + if (GPIO_config.callbacks[flagIndex] != NULL && GPIO_intEnabled(flagIndex)) + { + /* Only invoke callback if this pin has interrupt enabled in IOC + * This is because event-flags (checked above) can be generated independently of interrupts + */ + GPIO_config.callbacks[flagIndex](flagIndex); + } + } +} + +/* + * ======== GPIO_init ======== + */ +void GPIO_init(void) +{ + uintptr_t key; + unsigned int i; + HwiP_Params hwiParams; + uint32_t tempPinConfigs[32]; + uint32_t enableMask = 0x0; + + key = HwiP_disable(); + + if (initCalled) + { + HwiP_restore(key); + return; + } + initCalled = true; + HwiP_restore(key); + + // This is safe even if Power_init has already been called. + Power_init(); + + // Set Power dependecies & constraints + Power_setDependency(PowerCC26XX_PERIPH_GPIO); + + // Setup HWI handler + HwiP_Params_init(&hwiParams); + hwiParams.priority = GPIO_config.intPriority; + HwiP_construct(&gpioHwi, INT_AON_GPIO_EDGE, GPIO_hwiIntFxn, &hwiParams); + + // Note: pinUpperBound is inclusive, so we use <= instead of just < + for (i = GPIO_pinLowerBound; i <= GPIO_pinUpperBound; i++) + { + uint32_t pinConfig = GPIO_config.configs[i]; + + /* Mask off the bits containing non-IOC configuration values */ + tempPinConfigs[i] = pinConfig & GPIOCC26XX_CFG_IOC_M; + + if (!(pinConfig & GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL)) + { + enableMask |= 1 << i; + GPIO_write(i, pinConfig & GPIO_CFG_OUT_HIGH ? 1 : 0); + } + } + + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = enableMask; + + /* If the user has configured a pin as the external clock pin in CCFG, we + * should respect this. Add the mux directly into the temporary pin config. + */ + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) + { + uint32_t externalLfPin = CCFGRead_EXT_LF_CLK_DIO(); + tempPinConfigs[externalLfPin] |= IOC_IOCFG0_PORT_ID_AON_CLK32K; + } + + /* Apply all the masked values directly to IOC + * pinUpperBound is inclusive, so we need to add 1 to get the full range + * Multiply by 4 because each pin config and IOC register is 4 bytes wide + */ + memcpy((void *)(IOC_BASE + IOC_O_IOCFG0 + (4 * GPIO_pinLowerBound)), + (void *)&tempPinConfigs[GPIO_pinLowerBound], + ((GPIO_pinUpperBound + 1) - GPIO_pinLowerBound) * 4); + + // Setup wakeup source to wake up from standby (use MCU_WU1) + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = (HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) & + (~AON_EVENT_MCUWUSEL_WU1_EV_M)) | + AON_EVENT_MCUWUSEL_WU1_EV_PAD; +} diff --git a/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X4.c b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X4.c new file mode 100644 index 00000000..76edded7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26X4.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(inc/hw_gpio.h) +#include DeviceFamily_constructPath(inc/hw_aon_event.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +static bool initCalled = false; + +// HW interrupt structure for I/O interrupt handler +static HwiP_Struct gpioHwi; + +// Link to config values defined by sysconfig +extern GPIO_Config GPIO_config; +extern const uint_least8_t GPIO_pinLowerBound; +extern const uint_least8_t GPIO_pinUpperBound; + +/* + * ======== GPIO_intEnabled ======== + */ +static inline bool GPIO_intEnabled(uint32_t index) +{ + return ((HWREG(IOC_BASE + IOC_O_IOCFG0 + (4 * index)) & IOC_IOCFG0_EDGE_IRQ_EN) ? true : false); +} + +/* + * ======== GPIO_hwiIntFxn ======== + * Hwi function that processes GPIO interrupts. + */ +void GPIO_hwiIntFxn(uintptr_t arg) +{ + uint32_t flagIndex; + + uint32_t eventMask32 = HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0); + uint32_t eventMask64 = HWREG(GPIO_BASE + GPIO_O_EVFLAGS47_32); + + // Get and clear the interrupt mask + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = eventMask32; + HWREG(GPIO_BASE + GPIO_O_EVFLAGS47_32) = eventMask64; + + while (eventMask32) + { + // MASK_TO_PIN only detects the highest set bit + flagIndex = GPIO_MASK_TO_PIN(eventMask32); + + // So it's safe to use PIN_TO_MASK to clear that bit + eventMask32 &= ~GPIO_PIN_TO_MASK(flagIndex); + + /* Only invoke callback if this pin also has interrupts enabled in IOC + * This is because event-flags can be generated independently of interrupts + */ + if (GPIO_config.callbacks[flagIndex] != NULL && GPIO_intEnabled(flagIndex)) + { + GPIO_config.callbacks[flagIndex](flagIndex); + } + } + while (eventMask64) + { + /* MASK_TO_PIN only detects the highest set bit */ + flagIndex = GPIO_MASK_TO_PIN(eventMask64); + + /* So it's safe to use PIN_TO_MASK to clear that bit */ + eventMask64 &= ~GPIO_PIN_TO_MASK(flagIndex); + + /* Only invoke callback if this pin also has interrupts enabled in IOC + * This is because event-flags can be generated independently of interrupts + */ + if (GPIO_config.callbacks[flagIndex + 32] != NULL && GPIO_intEnabled(flagIndex + 32)) + { + GPIO_config.callbacks[flagIndex + 32](flagIndex + 32); + } + } +} + +/* + * ======== GPIO_init ======== + */ +void GPIO_init(void) +{ + uintptr_t key; + unsigned int i; + HwiP_Params hwiParams; + + uint32_t tempPinConfigs[64]; + uint64_t enableMask = 0x0; + + key = HwiP_disable(); + + if (initCalled) + { + HwiP_restore(key); + return; + } + initCalled = true; + HwiP_restore(key); + + // This is safe even if Power_init has already been called. + Power_init(); + + // Set Power dependecies & constraints + Power_setDependency(PowerCC26XX_PERIPH_GPIO); + + // Setup HWI handler + HwiP_Params_init(&hwiParams); + hwiParams.priority = GPIO_config.intPriority; + HwiP_construct(&gpioHwi, INT_AON_GPIO_EDGE, GPIO_hwiIntFxn, &hwiParams); + + // Note: pinUpperBound is inclusive, so we use <= instead of just < + for (i = GPIO_pinLowerBound; i <= GPIO_pinUpperBound; i++) + { + uint32_t pinConfig = GPIO_config.configs[i]; + + /* Mask off the bits containing non-IOC configuration values */ + tempPinConfigs[i] = pinConfig & GPIOCC26XX_CFG_IOC_M; + + if (!(pinConfig & GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL)) + { + enableMask |= ((uint64_t)1) << i; + GPIO_write(i, pinConfig & GPIO_CFG_OUT_HIGH ? 1 : 0); + } + } + + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = enableMask; + HWREG(GPIO_BASE + GPIO_O_DOE47_32) = (uint32_t)(enableMask >> 32); + + /* If the user has configured a pin as the external clock pin in CCFG, we + * should respect this. Add the mux directly into the temporary pin config. + */ + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) + { + uint32_t externalLfPin = CCFGRead_EXT_LF_CLK_DIO(); + tempPinConfigs[externalLfPin] |= IOC_IOCFG0_PORT_ID_AON_CLK32K; + } + + /* Apply all the masked values directly to IOC + * pinUpperBound is inclusive, so we need to add 1 to get the full range + * Multiply by 4 because each pin config and IOC register is 4 bytes wide + */ + memcpy((void *)(IOC_BASE + IOC_O_IOCFG0 + (4 * GPIO_pinLowerBound)), + (void *)&tempPinConfigs[GPIO_pinLowerBound], + ((GPIO_pinUpperBound + 1) - GPIO_pinLowerBound) * 4); + + // Setup wakeup source to wake up from standby (use MCU_WU1) + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = (HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) & + (~AON_EVENT_MCUWUSEL_WU1_EV_M)) | + AON_EVENT_MCUWUSEL_WU1_EV_PAD; +} diff --git a/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.c b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.c new file mode 100644 index 00000000..e327d149 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(inc/hw_gpio.h) +#include DeviceFamily_constructPath(inc/hw_aon_event.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +// Link to config values defined by sysconfig +extern GPIO_Config GPIO_config; + +/* + * ======== GPIO_clearInt ======== + */ +void GPIO_clearInt(uint_least8_t index) +{ + if (index != GPIO_INVALID_INDEX) + { + GPIO_clearEventDio(index); + } +} + +/* + * ======== GPIO_disableInt ======== + */ +void GPIO_disableInt(uint_least8_t index) +{ + /* Interrupt enable is bit 18. Here we mask 0x4 out of byte 2 to disable + * interrupts. Note we cannot just read-write the whole register. + * See the IOCFG comment in setConfig(). + */ + if (index != GPIO_INVALID_INDEX) + { + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index) + 2; + HWREGB(iocfgRegAddr) = HWREGB(iocfgRegAddr) & ~0x4; + } +} + +/* + * ======== GPIO_enableInt ======== + */ +void GPIO_enableInt(uint_least8_t index) +{ + /* Interrupt enable is bit 18. Here we or 0x4 into byte 2 to enable + * interrupts. Note we cannot just read-write the whole register. + * See the IOCFG comment in setConfig(). + */ + if (index != GPIO_INVALID_INDEX) + { + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index) + 2; + HWREGB(iocfgRegAddr) = HWREGB(iocfgRegAddr) | 0x4; + } +} + +/* + * ======== GPIO_read ======== + */ +uint_fast8_t GPIO_read(uint_least8_t index) +{ + return GPIO_readDio(index); +} + +/* + * ======== GPIO_setConfig ======== + */ +int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig) +{ + return GPIO_setConfigAndMux(index, pinConfig, GPIO_MUX_GPIO); +} + +/* + * ======== GPIO_setInterruptConfig ======== + */ +void GPIO_setInterruptConfig(uint_least8_t index, GPIO_PinConfig config) +{ + uintptr_t key; + + if (index != GPIO_INVALID_INDEX) + { + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index) + 2; + + /* Shift down and mask away all non-interrupt configuration */ + uint8_t maskedConfig = (config >> 16) & 0x7; + + key = HwiP_disable(); + + /* Mask out current interrupt config and apply the new one */ + uint8_t currentRegisterConfig = HWREGB(iocfgRegAddr) & 0xF8; + HWREGB(iocfgRegAddr) = currentRegisterConfig | maskedConfig; + HwiP_restore(key); + } +} + +/* + * ======== GPIO_getConfig ======== + */ +void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig) +{ + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index); + + /* Mask off the bits reserved for non-IOC configuration values. + * The non-IOC configuration values will be written further below. + */ + uint32_t configValue = HWREG(iocfgRegAddr) & GPIOCC26XX_CFG_IOC_M; + + if (GPIO_getOutputEnableDio(index)) + { + /* We use XOR here because if INVERT and HIGH are both true, the SW setting is LOW */ + if (GPIO_read(index) ^ ((configValue & GPIO_CFG_INVERT_ON_INTERNAL) != 0)) + { + configValue |= GPIO_CFG_OUT_HIGH; + } + } + else + { + configValue |= GPIO_getOutputEnableDio(index) ? GPIOCC26XX_CFG_PIN_IS_OUTPUT_INTERNAL + : GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL; + } + + *pinConfig = configValue; +} + +/* + * ======== GPIO_getMux ======== + */ +uint32_t GPIO_getMux(uint_least8_t index) +{ + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index); + return HWREG(iocfgRegAddr) & 0xFF; +} + +/* + * ======== GPIO_setConfigAndMux ======== + */ +int_fast16_t GPIO_setConfigAndMux(uint_least8_t index, GPIO_PinConfig pinConfig, uint32_t mux) +{ + uintptr_t key; + + if (index == GPIO_INVALID_INDEX) + { + return GPIO_STATUS_ERROR; + } + + uint32_t iocfgRegAddr = IOC_BASE + IOC_O_IOCFG0 + (4 * index); + uint32_t previousConfig = HWREG(iocfgRegAddr); + + /* Note: Do not change this to check PIN_IS_OUTPUT, because that is 0x0 */ + uint32_t pinWillBeOutput = !(pinConfig & GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL); + + /* Special configurations are stored in the lowest 8 bits and need to be removed + * We can make choices based on these values, but must not write them to hardware */ + GPIO_PinConfig tmpConfig = pinConfig & GPIOCC26XX_CFG_IOC_M; + + if ((previousConfig & 0xFF) != mux) + { + /* If we're changing the mux to GPIO, then we need to change the output + * configuration before changing the mux, to ensure that the correct + * configuration is ready when we change the mux. Otherwise a glitch + * might occur. + */ + if (mux == GPIO_MUX_GPIO) + { + if (pinWillBeOutput) + { + GPIO_write(index, pinConfig & GPIO_CFG_OUT_HIGH ? 1 : 0); + } + GPIO_setOutputEnableDio(index, pinWillBeOutput ? GPIO_OUTPUT_ENABLE : GPIO_OUTPUT_DISABLE); + } + + /* If we're updating mux as well, we can write the whole register */ + HWREG(iocfgRegAddr) = tmpConfig | mux; + } + else + { + /* + * Writes to the first byte of the IOCFG register will cause a glitch + * on the internal IO line. To avoid this, we only want to write + * the upper 24-bits of the IOCFG register when updating the configuration + * bits. We do this 1 byte at a time. + */ + key = HwiP_disable(); + HWREGB(iocfgRegAddr + 1) = (uint8_t)(tmpConfig >> 8); + HWREGB(iocfgRegAddr + 2) = (uint8_t)(tmpConfig >> 16); + HWREGB(iocfgRegAddr + 3) = (uint8_t)(tmpConfig >> 24); + HwiP_restore(key); + + /* The output configuration needs to be changed after changing the IOCFG + * register, to ensure that the output is only enabled/disabled for the + * desired IO configuration. For example if the configuration is changed + * from an input to an open drain output, then we don't want to enable + * the output before the IO has been configured to open drain, since + * driving the signal high might have some undesired side effect. + * Another example is if the IO is changed from a high output to an + * input with a pull-up, then to avoid glitches, we want the pull-up to + * be enabled before we disable the output. + * + * If this pin is being configured to an output, set the new output + * value. It's important to do this before we change from INPUT to + * OUTPUT if applicable. If we're already an output this is fine, and if + * we're input changing to input this statement will not execute. + */ + if (pinWillBeOutput) + { + GPIO_write(index, pinConfig & GPIO_CFG_OUT_HIGH ? 1 : 0); + } + + GPIO_setOutputEnableDio(index, pinWillBeOutput ? GPIO_OUTPUT_ENABLE : GPIO_OUTPUT_DISABLE); + } + + return GPIO_STATUS_SUCCESS; +} + +/* + * ======== GPIO_toggle ======== + */ +void GPIO_toggle(uint_least8_t index) +{ + if (index != GPIO_INVALID_INDEX) + { + GPIO_toggleDio(index); + } +} + +/* + * ======== GPIO_write ======== + */ +void GPIO_write(uint_least8_t index, unsigned int value) +{ + if (index != GPIO_INVALID_INDEX) + { + GPIO_writeDio(index, value); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.h b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.h new file mode 100644 index 00000000..6fdd9768 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/gpio/GPIOCC26XX.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file GPIOCC26XX.h + * + * @brief GPIO driver implementation for CC26xx devices + * + * The GPIO header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref GPIO.h for a complete description of the GPIO + * driver APIs provided and examples of their use. + * + * The definitions in this file should not be used directly. All GPIO_CFG + * macros should be used as-is from GPIO.h. + * + * There are no additional configuration values or platform-specific + * functions for GPIOCC26XX. + */ + +#ifndef ti_drivers_GPIOCC26XX__include +#define ti_drivers_GPIOCC26XX__include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ioc.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* Alternative mux values are defined in hw_ioc.h */ +#define GPIO_MUX_GPIO_INTERNAL IOC_IOCFG0_PORT_ID_GPIO + +/* We don't define this value on purpose - any unsupported values will cause a + * compile-time error. If your compiler tells you that this macro is missing, + * you are trying to use an unsupported option. + * + * See below for which options are unsupported. + */ +#undef GPIOCC26XX_CFG_OPTION_NOT_SUPPORTED + +/* Most configuration values are directly mapped to fields in the IOCFGn + * registers, but the lower 8 bits are reserved for configuration options that + * cannot be directly mapped to the IOCFGn registers. The define below is the + * mask used by the GPIO driver to mask off the non-IOC configuration values. + */ +#define GPIOCC26XX_CFG_IOC_M 0xFFFFFF00 + +/* Low and high value interrupts are not available on CC26XX hardware */ +#define GPIO_CFG_INT_LOW_INTERNAL GPIOCC26XX_CFG_OPTION_NOT_SUPPORTED +#define GPIO_CFG_INT_HIGH_INTERNAL GPIOCC26XX_CFG_OPTION_NOT_SUPPORTED + +/* Support for DO_NOT_CONFIG would break a major initialisation optimisation */ +#define GPIO_CFG_DO_NOT_CONFIG_INTERNAL GPIOCC26XX_CFG_OPTION_NOT_SUPPORTED + +/* See GPIO.h for details about these configuration values */ + +/* General options remapped directly to IOC defines */ +#define GPIO_CFG_NO_DIR_INTERNAL (IOC_IOCFG0_IOMODE_NORMAL | GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL) +#define GPIO_CFG_INPUT_INTERNAL (IOC_IOCFG0_IOMODE_NORMAL | IOC_IOCFG0_IE | GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL) +#define GPIO_CFG_OUTPUT_INTERNAL (IOC_IOCFG0_IOMODE_NORMAL | IOC_IOCFG0_IE | GPIOCC26XX_CFG_PIN_IS_OUTPUT_INTERNAL) +#define GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL \ + (IOC_IOCFG0_IOMODE_OPENDR | IOC_IOCFG0_IE | GPIOCC26XX_CFG_PIN_IS_OUTPUT_INTERNAL) +#define GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL \ + (IOC_IOCFG0_IOMODE_OPENSRC | IOC_IOCFG0_IE | GPIOCC26XX_CFG_PIN_IS_OUTPUT_INTERNAL) + +#define GPIO_CFG_PULL_NONE_INTERNAL IOC_IOCFG0_PULL_CTL_DIS +#define GPIO_CFG_PULL_UP_INTERNAL IOC_IOCFG0_PULL_CTL_UP +#define GPIO_CFG_PULL_DOWN_INTERNAL IOC_IOCFG0_PULL_CTL_DWN + +#define GPIO_CFG_INT_NONE_INTERNAL IOC_IOCFG0_EDGE_DET_NONE +#define GPIO_CFG_INT_FALLING_INTERNAL IOC_IOCFG0_EDGE_DET_NEG +#define GPIO_CFG_INT_RISING_INTERNAL IOC_IOCFG0_EDGE_DET_POS +#define GPIO_CFG_INT_BOTH_EDGES_INTERNAL IOC_IOCFG0_EDGE_DET_BOTH + +#define GPIO_CFG_INT_ENABLE_INTERNAL IOC_IOCFG0_EDGE_IRQ_EN +#define GPIO_CFG_INT_DISABLE_INTERNAL 0 + +/* Value inversion is stored in the low bit of IOMODE */ +#define GPIO_CFG_INVERT_OFF_INTERNAL 0 +#define GPIO_CFG_INVERT_ON_INTERNAL IOC_IOCFG0_IOMODE_INV + +#define GPIO_CFG_HYSTERESIS_OFF_INTERNAL 0 +#define GPIO_CFG_HYSTERESIS_ON_INTERNAL IOC_IOCFG0_HYST_EN + +#define GPIO_CFG_SLEW_NORMAL_INTERNAL 0 +#define GPIO_CFG_SLEW_REDUCED_INTERNAL IOC_IOCFG0_SLEW_RED + +#define GPIO_CFG_DRVSTR_LOW_INTERNAL IOC_IOCFG0_IOCURR_2MA +#define GPIO_CFG_DRVSTR_MED_INTERNAL IOC_IOCFG0_IOCURR_4MA +#define GPIO_CFG_DRVSTR_HIGH_INTERNAL IOC_IOCFG0_IOCURR_4_8MA + +#define GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL 0 +#define GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL IOC_WAKE_ON_HIGH +#define GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL IOC_WAKE_ON_LOW + +/* We can hide some settings inside the MUX byte if they are not part of the + * IOC config, since the mux is applied separately. On CC26XX this is the + * lowest 8 bits. + * + * Do not use these values when calling GPIO_setConfig(). They are for + * internal use only, to provide support for driver functionality that does + * not map directly into the IO config registers. + */ +#define GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL 0x1 +#define GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL 0 + +/* Whether GPIO hardware should have the output enable bit set for this pin */ +#define GPIOCC26XX_CFG_PIN_IS_INPUT_INTERNAL 0x2 +#define GPIOCC26XX_CFG_PIN_IS_OUTPUT_INTERNAL 0 + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_GPIOCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.c b/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.c new file mode 100644 index 00000000..711b03c2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.c @@ -0,0 +1,752 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== I2CCC26XX.c ======== + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +/* Driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/i2c.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) + +/* + * =============================== Macros ===================================== + * + * Specific I2C CMD MACROs that are not defined in I2C.h are defined here. Their + * equivalent values are taken from the existing MACROs in I2C.h + * + */ +#ifndef I2C_CONTROLLER_CMD_BURST_RECEIVE_START_NACK + #define I2C_CONTROLLER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START +#endif + +#ifndef I2C_CONTROLLER_CMD_BURST_RECEIVE_STOP + #define I2C_CONTROLLER_CMD_BURST_RECEIVE_STOP I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP +#endif + +#ifndef I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT_NACK + #define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT +#endif + +/* Prototypes */ +static void I2CCC26XX_blockingCallback(I2C_Handle handle, I2C_Transaction *msg, bool transferStatus); +static inline void I2CCC26XX_completeTransfer(I2C_Handle handle); +static void I2CCC26XX_hwiFxn(uintptr_t arg); +void I2CCC26XX_init(I2C_Handle handle); +static void I2CCC26XX_initHw(I2C_Handle handle); +static int I2CCC26XX_initIO(I2C_Handle handle, void *pinCfg); +static int I2CCC26XX_postNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +static void I2CCC26XX_swiFxn(uintptr_t arg0, uintptr_t arg1); + +/* Default I2C parameters structure */ +extern const I2C_Params I2C_defaultParams; + +/*! + * ======== I2C_close ======== + * @brief Function to close a given CC26XX I2C peripheral specified by the + * I2C handle. + * + * After calling the close function, the I2C is disabled. + * + * @pre I2C_open() has to be called first. + * Calling context: Task + * + * @param handle An I2C_Handle returned by I2C_open() + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * @sa I2C_open(), I2C_close(), I2C_open() + */ +void I2C_close(I2C_Handle handle) +{ + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Check to see if a I2C transaction is in progress */ + DebugP_assert(object->headPtr == NULL); + + /* Mask I2C interrupts */ + I2CMasterIntDisable(hwAttrs->baseAddr); + + /* Disable the I2C Controller */ + I2CMasterDisable(hwAttrs->baseAddr); + + /* Deallocate pins */ + GPIO_resetConfig(object->sclPin); + GPIO_resetConfig(object->sdaPin); + + /* Power off the I2C module */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Destruct modules used in driver */ + HwiP_destruct(&(object->hwi)); + SwiP_destruct(&(object->swi)); + SemaphoreP_destruct(&(object->mutex)); + if (object->transferMode == I2C_MODE_BLOCKING) + { + SemaphoreP_destruct(&(object->transferComplete)); + } + + /* Unregister power post notification object */ + Power_unregisterNotify(&object->i2cPostObj); + + /* Mark the module as available */ + object->isOpen = false; + + return; +} + +/*! + * ======== I2C_control ======== + * @brief Function for setting control parameters of the I2C driver + * after it has been opened. + * + * @pre Function assumes that the handle is not NULL + * + * @note Currently not in use. + */ +int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, void *arg) +{ + /* No implementation */ + return (I2C_STATUS_UNDEFINEDCMD); +} + +/*! + * ======== I2C_open ======== + * @brief Function to initialize a given I2C CC26XX peripheral specified by the + * particular handle. The parameter specifies which mode the I2C + * will operate. + * + * After calling the open function, the I2C is enabled. If there is no active + * I2C transactions, the device can enter standby. + * + * @pre The I2CCC26XX_Config structure must exist and be persistent before this + * function can be called. I2CCC26XX has been initialized with I2CCC26XX_init(). + * Calling context: Task + * + * @param handle An I2C_Handle + * + * @param params Pointer to a parameter block, if NULL it will use default values. + * + * @return A I2C_Handle on success, or a NULL on an error or if it has been + * already opened. + * + * @note The generic I2C API should be used when accessing the I2CCC26XX. + * + * @sa I2C_close(), I2CCC26XX_init(), I2C_open(), I2C_init() + */ +I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params) +{ + I2C_Handle handle = NULL; + union + { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + uintptr_t key; + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + if (index < I2C_count) + { + if (params == NULL) + { + params = (I2C_Params *)&I2C_defaultParams; + } + + handle = (I2C_Handle) & (I2C_config[index]); + hwAttrs = handle->hwAttrs; + object = handle->object; + } + else + { + return (NULL); + } + + /* Check for valid bit rate */ + DebugP_assert(params->bitRate <= I2C_400kHz); + + /* Determine if the device index was already opened */ + key = HwiP_disable(); + if (object->isOpen == true) + { + HwiP_restore(key); + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + HwiP_restore(key); + + /* Power on the I2C module */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Configure the IOs.*/ + if (I2CCC26XX_initIO(handle, params->custom)) + { + /* Mark the module as available */ + key = HwiP_disable(); + object->isOpen = false; + HwiP_restore(key); + /* Release dependency if open fails */ + Power_releaseDependency(hwAttrs->powerMngrId); + /* Signal back to application that I2C driver was not successfully opened */ + return (NULL); + } + + /* Save parameters */ + object->transferMode = params->transferMode; + object->transferCallbackFxn = params->transferCallbackFxn; + object->bitRate = params->bitRate; + + /* Disable and clear interrupts possible from soft resets */ + I2CMasterIntDisable(hwAttrs->baseAddr); + I2CMasterIntClear(hwAttrs->baseAddr); + + /* Create Hwi object for this I2C peripheral */ + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, I2CCC26XX_hwiFxn, ¶msUnion.hwiParams); + + /* Create Swi object for this I2C peripheral */ + SwiP_Params_init(&(paramsUnion.swiParams)); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), I2CCC26XX_swiFxn, &(paramsUnion.swiParams)); + + /* + * Create thread safe handles for this I2C peripheral + * Semaphore to provide exclusive access to the I2C peripheral + */ + SemaphoreP_constructBinary(&(object->mutex), 1); + + /* + * Store a callback function that posts the transfer complete + * semaphore for synchronous mode + */ + if (object->transferMode == I2C_MODE_BLOCKING) + { + /* Semaphore to cause the waiting task to block for the I2C to finish */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + + /* Store internal callback function */ + object->transferCallbackFxn = I2CCC26XX_blockingCallback; + } + else + { + /* Check to see if a callback function was defined for async mode */ + DebugP_assert(object->transferCallbackFxn != NULL); + } + + /* Clear the head pointer */ + object->headPtr = NULL; + object->tailPtr = NULL; + + /* Initialize the I2C hardware module */ + I2CCC26XX_initHw(handle); + + /* Register notification functions */ + Power_registerNotify(&object->i2cPostObj, + PowerCC26XX_AWAKE_STANDBY, + (Power_NotifyFxn)I2CCC26XX_postNotify, + (uint32_t)handle); + + /* Return the address of the handle */ + return (handle); +} + +/* + * ======== I2CCC26XX_hwiFxn ======== + * Hwi interrupt handler to service the I2C peripheral + * + * The handler is a generic handler for a I2C object. + */ +static void I2CCC26XX_hwiFxn(uintptr_t arg) +{ + I2C_Handle handle = (I2C_Handle)arg; + I2CCC26XX_Object *object = handle->object; + I2CCC26XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + uint32_t command = I2C_MCTRL_RUN; + + /* Clear the interrupt */ + I2CMasterIntClear(hwAttrs->baseAddr); + + /* + * Check if the Controller is busy. If busy, the MSTAT is invalid as + * the controller is still transmitting or receiving. In that case, + * we should wait for the next interrupt. + */ + if (I2CMasterBusy(hwAttrs->baseAddr)) + { + return; + } + + uint32_t status = HWREG(hwAttrs->baseAddr + I2C_O_MSTAT); + + /* Current transaction is cancelled */ + if (object->currentTransaction->status == I2C_STATUS_CANCEL) + { + I2CMasterControl(hwAttrs->baseAddr, I2C_MCTRL_STOP); + I2CCC26XX_completeTransfer(handle); + return; + } + + /* Handle errors. ERR bit is not set if arbitration lost. + * The I2C peripheral has an issue where the DATACK_N bit + * is not updated if the previous command sets the ACK bit + * (Controller automatically ACK's received data). This condition + * can be detected by the state of writeCount, readCount, and + * the status register. If the condition is true, don't enter + * the error-handling block, but carry on reading instead. + */ + if ((status & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) && + !(object->writeCount == 0 && ((status & 0x1F) == (I2C_MSTAT_ERR | I2C_MSTAT_DATACK_N)))) + { + /* Decode interrupt status */ + if (status & I2C_MSTAT_ARBLST) + { + object->currentTransaction->status = I2C_STATUS_ARB_LOST; + } + /* + * The I2C peripheral has an issue where the first data byte + * is always transmitted, regardless of the ADDR NACK. Therefore, + * we should check this error condition first. + */ + else if (status & I2C_MSTAT_ADRACK_N) + { + object->currentTransaction->status = I2C_STATUS_ADDR_NACK; + } + else + { + /* Last possible bit is the I2C_MSTAT_DATACK_N */ + object->currentTransaction->status = I2C_STATUS_DATA_NACK; + } + + /* + * The CC13X2 / CC26X2 I2C peripheral does not have an explicit STOP + * interrupt bit. Therefore, if an error occurred, we send the STOP + * bit and complete the transfer immediately. + */ + I2CMasterControl(hwAttrs->baseAddr, I2C_MCTRL_STOP); + I2CCC26XX_completeTransfer(handle); + } + else if (object->writeCount) + { + object->writeCount--; + + /* Is there more to transmit */ + if (object->writeCount) + { + I2CMasterDataPut(hwAttrs->baseAddr, *(object->writeBuf++)); + } + /* If we need to receive */ + else if (object->readCount) + { + /* Place controller in receive mode */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, object->currentTransaction->targetAddress, true); + + if (object->readCount > 1) + { + /* RUN and generate ACK to target */ + command |= I2C_MCTRL_ACK; + } + + /* RUN and generate a repeated START */ + command |= I2C_MCTRL_START; + } + else + { + /* Send STOP */ + command = I2C_MCTRL_STOP; + } + + I2CMasterControl(hwAttrs->baseAddr, command); + } + else if (object->readCount) + { + object->readCount--; + + /* Read data */ + *(object->readBuf++) = I2CMasterDataGet(hwAttrs->baseAddr); + + if (object->readCount > 1) + { + /* Send ACK and RUN */ + command |= I2C_MCTRL_ACK; + } + else if (object->readCount < 1) + { + /* Send STOP */ + command = I2C_MCTRL_STOP; + } + else + { + /* Send RUN */ + } + + I2CMasterControl(hwAttrs->baseAddr, command); + } + else + { + I2CMasterControl(hwAttrs->baseAddr, I2C_MCTRL_STOP); + object->currentTransaction->status = I2C_STATUS_SUCCESS; + I2CCC26XX_completeTransfer(handle); + } + + return; +} + +/* + * ======== I2C_setClockTimeout ======== + */ +int_fast16_t I2C_setClockTimeout(I2C_Handle handle, uint32_t timeout) +{ + return (I2C_STATUS_ERROR); +} + +/* + * ======== I2CCC26XX_swiFxn ======== + * SWI interrupt handler to service the I2C peripheral + * + * Takes care of cleanup and the callback in SWI context after an I2C transfer + */ +static void I2CCC26XX_swiFxn(uintptr_t arg0, uintptr_t arg1) +{ + I2C_Handle handle = (I2C_Handle)arg0; + I2CCC26XX_Object *object = handle->object; + int_fast16_t status; + + /* + * If this current transaction was canceled, we need to cancel + * any queued transactions + */ + if (object->currentTransaction->status == I2C_STATUS_CANCEL) + { + /* + * Allow callback to run. If in CALLBACK mode, the application + * may initiate a transfer in the callback which will call + * primeTransfer(). + */ + object->transferCallbackFxn(handle, object->currentTransaction, false); + object->currentTransaction->status = I2C_STATUS_CANCEL; + + /* release the constraint to disallow standby */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* also dequeue and call the transfer callbacks for any queued transfers */ + while (object->headPtr != object->tailPtr) + { + object->headPtr = object->headPtr->nextPtr; + object->headPtr->status = I2C_STATUS_CANCEL; + object->transferCallbackFxn(handle, object->headPtr, false); + object->headPtr->status = I2C_STATUS_CANCEL; + } + + /* clean up object */ + object->currentTransaction = NULL; + object->headPtr = NULL; + object->tailPtr = NULL; + } + else if (object->currentTransaction->status == I2C_STATUS_TIMEOUT) + { + /* + * This can only occur in BLOCKING mode. No need to call the blocking + * callback as the Semaphore has already timed out. + */ + object->headPtr = NULL; + object->tailPtr = NULL; + + /* Release standby disallow constraint. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + /* See if we need to process any other transactions */ + else if (object->headPtr == object->tailPtr) + { + + /* No other transactions need to occur */ + object->headPtr = NULL; + object->tailPtr = NULL; + + /* + * Allow callback to run. If in CALLBACK mode, the application + * may initiate a transfer in the callback which will call + * primeTransfer(). + */ + object->transferCallbackFxn(handle, + object->currentTransaction, + (object->currentTransaction->status == I2C_STATUS_SUCCESS)); + + /* Release standby disallow constraint. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else + { + /* Another transfer needs to take place */ + object->headPtr = object->headPtr->nextPtr; + + /* + * Allow application callback to run. The application may + * initiate a transfer in the callback which will add an + * additional transfer to the queue. + */ + object->transferCallbackFxn(handle, + object->currentTransaction, + (object->currentTransaction->status == I2C_STATUS_SUCCESS)); + + status = I2CSupport_primeTransfer(handle, object->headPtr); + + /* Call back now if not able to start transfer */ + if (status != I2C_STATUS_SUCCESS) + { + /* Transaction status set in primeTransfer() */ + SwiP_post(&(object->swi)); + } + } +} + +/* + * ======== I2CSupport_controllerFinish ======== + */ +void I2CSupport_controllerFinish(I2C_HWAttrs const *hwAttrs) +{ + /* Asynchronously generate a STOP condition. */ + I2CMasterControl(hwAttrs->baseAddr, I2C_MCTRL_STOP); +} + +/* + * ======== I2CSupport_powerRelConstraint ======= + */ +void I2CSupport_powerRelConstraint(void) +{ + /* Release standby disallow constraint. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== I2CSupport_powerSetConstraint ======= + */ +void I2CSupport_powerSetConstraint(void) +{ + /* Set standby disallow constraint. */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== I2CSupport_primeTransfer ======= + */ +int_fast16_t I2CSupport_primeTransfer(I2C_Handle handle, I2C_Transaction *transaction) +{ + I2CCC26XX_Object *object = handle->object; + I2CCC26XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + int_fast16_t status = I2C_STATUS_SUCCESS; + + /* Store the new internal counters and pointers */ + object->currentTransaction = transaction; + + object->writeBuf = transaction->writeBuf; + object->writeCount = transaction->writeCount; + object->readBuf = transaction->readBuf; + object->readCount = transaction->readCount; + + /* + * Transaction is incomplete unless the stop condition occurs AND + * all bytes have been sent and received. This condition is checked + * in the hardware interrupt. + */ + object->currentTransaction->status = I2C_STATUS_INCOMPLETE; + + /* Determine if the bus is in use by another I2C Controller */ + if (I2CMasterBusBusy(hwAttrs->baseAddr)) + { + transaction->status = I2C_STATUS_BUS_BUSY; + status = I2C_STATUS_BUS_BUSY; + } + /* Start transfer in Transmit */ + else if (object->writeCount) + { + I2CMasterIntEnable(hwAttrs->baseAddr); + + /* Specify target address and transmit mode */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, object->currentTransaction->targetAddress, false); + + I2CMasterDataPut(hwAttrs->baseAddr, *((object->writeBuf)++)); + I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_START); + } + else + { + I2CMasterIntEnable(hwAttrs->baseAddr); + + /* Specify target address and receive mode */ + I2CMasterSlaveAddrSet(hwAttrs->baseAddr, object->currentTransaction->targetAddress, true); + + if (object->readCount == 1) + { + /* Send START, read 1 data byte, and NACK */ + I2CMasterControl(hwAttrs->baseAddr, I2C_CONTROLLER_CMD_BURST_RECEIVE_START_NACK); + } + else + { + /* Start the I2C transfer in controller receive mode */ + I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_RECEIVE_START); + } + } + + return (status); +} + +/* + * ======== I2CCC26XX_completeTransfer ======== + * This function may be invoked in the context of the HWI. + */ +static inline void I2CCC26XX_completeTransfer(I2C_Handle handle) +{ + I2CCC26XX_Object *object = handle->object; + I2CCC26XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + + /* Disable and clear any interrupts */ + I2CMasterIntDisable(hwAttrs->baseAddr); + I2CMasterIntClear(hwAttrs->baseAddr); + + SwiP_post(&(object->swi)); +} + +/* + * ======== I2CCC26XX_blockingCallback ======== + */ +static void I2CCC26XX_blockingCallback(I2C_Handle handle, I2C_Transaction *msg, bool transferStatus) +{ + I2CCC26XX_Object *object = handle->object; + + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== I2CCC26XX_initHw ======== + * This functions initializes the I2C hardware module. + * + * @pre Function assumes that the I2C handle is pointing to a hardware + * module which has already been opened. + */ +static void I2CCC26XX_initHw(I2C_Handle handle) +{ + I2CCC26XX_Object *object = handle->object; + I2CCC26XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; + ClockP_FreqHz freq; + + /* Disable and clear interrupts */ + I2CMasterIntDisable(hwAttrs->baseAddr); + I2CMasterIntClear(hwAttrs->baseAddr); + + /* Set the I2C configuration */ + ClockP_getCpuFreq(&freq); + I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo, object->bitRate > I2C_100kHz); + + /* Enable the I2C Controller for operation */ + I2CMasterEnable(hwAttrs->baseAddr); +} + +/* + * ======== I2CCC26XX_initIO ======== + * This functions initializes the I2C IOs. + * + * @pre Function assumes that the I2C handle is pointing to a hardware + * module which has already been opened. + */ +static int I2CCC26XX_initIO(I2C_Handle handle, void *pinCfg) +{ + I2CCC26XX_Object *object; + I2CCC26XX_HWAttrsV1 const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* If the pinCfg pointer is NULL, use hwAttrs pins */ + if (pinCfg == NULL) + { + object->sdaPin = hwAttrs->sdaPin; + object->sclPin = hwAttrs->sclPin; + } + else + { + object->sdaPin = ((I2CCC26XX_I2CPinCfg *)pinCfg)->pinSDA; + object->sclPin = ((I2CCC26XX_I2CPinCfg *)pinCfg)->pinSCL; + } + + /* Configure I2C pins SDA and SCL and set their muxes */ + GPIO_setConfigAndMux(object->sdaPin, GPIO_CFG_OUT_OD_PU, hwAttrs->sdaPinMux); + GPIO_setConfigAndMux(object->sclPin, GPIO_CFG_OUT_OD_PU, hwAttrs->sclPinMux); + + return I2C_STATUS_SUCCESS; +} + +/* + * ======== I2CCC26XX_postNotify ======== + * This functions is called to notify the I2C driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the I2C handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int I2CCC26XX_postNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + /* reconfigure the hardware if returning from sleep*/ + if (eventType == PowerCC26XX_AWAKE_STANDBY) + { + I2CCC26XX_initHw((I2C_Handle)clientArg); + } + + return (Power_NOTIFYDONE); +} diff --git a/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.h b/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.h new file mode 100644 index 00000000..ca45928e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/i2c/I2CCC26XX.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file I2CCC26XX.h + * + * @brief I2C driver implementation for a CC26XX I2C controller. + * + * # Driver Include # + * The I2C header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref I2C.h for a complete description of APIs. + * + * # Overview # + * Refer to @ref I2C.h for a complete description of APIs. + * + * ## General Behavior # + * Before using the I2C in CC26XX: + * - The I2C driver is initialized by calling I2C_init(). + * - The I2C HW is configured and system dependencies are declared (e.g. IOs, + * power, etc.) by calling I2C_open(). + * . + * The following is true for receive operation: + * - RX is enabled by calling I2C_transfer(). + * The readCount of the ::I2C_Transaction must be set to a non-zero value. + * - If the I2C_transfer() succeeds, the I2C remains enabled. + * - The application must check the return value from I2C_transfer() + * to verify that the transfer succeeded. + * . + * The following apply for transmit operation: + * - TX is enabled by calling I2C_transfer(). + * The writeCount of the ::I2C_Transaction must be set to a non-zero value. + * - If the I2C_transfer() succeeds, the I2C remains enabled. + * - The application must check the return value from I2C_transfer() + * to verify that the transfer succeeded. + * . + * After I2C operation has ended: + * - Release system dependencies for I2C by calling I2C_close(). + * + * ### Known Issue # + * @warning The I2C will transmit a single data byte in the event that the + * I2C target address is not acknowledged (NACK'd). This is due to a known + * hardware bug. + * + * ## Error handling # + * If an error occurs during operation: + * - The I2C Controller transmits a stop bit and remains enabled. + * . + * + * ## Power Management # + * The I2CCC26XX driver sets a power constraint during transactions to keep + * the device out of standby; so when all tasks are blocked, the device will + * enter idle mode instead of standby. When the transactions have finished, + * the power constraint to prohibit standby is released. + * The following statements are valid: + * - After I2C_open() call: I2C is enabled, there are no active I2C + * transactions, the device can enter standby. + * - After I2C_transfer() call: active I2C transactions exist, the device + * might enter idle, but not standby. + * - When I2C_transfer() completes, either after success or error, I2C + * remains enabled, and the device can enter standby. + * - After I2C_close() call: I2C is disabled + * - If the device goes into idle during a transaction, the state of + * SDA is undefined in the time between the transaction completing and + * the device waking up. SCL will go low until the device wakes up and + * starts another transaction or releases the bus. If this is a problem + * for another device on the I2C bus, you can set a power constraint for + * #PowerCC26XX_DISALLOW_IDLE before the transaction and release it + * when the transaction completes. + * + * ## Supported Functions ## + * | Generic API Function | Description | + * |------------------------|---------------------------------------------------| + * | #I2C_init() | Initialize I2C driver | + * | #I2C_Params_init() | Initialize an #I2C_Params structure | + * | #I2C_open() | Initialize I2C HW and set system dependencies | + * | #I2C_close() | Disable I2C HW and release system dependencies | + * | #I2C_transfer() | Start I2C transfer | + * | #I2C_transferTimeout() | Start I2C transfer with a timeout | + * | #I2C_cancel() | Cancels all I2C transfers | + * + * ## Supported Bit Rates ## + * - #I2C_100kHz + * - #I2C_400kHz + * + * ## Supported Address Modes ## + * - #I2C_ADDRESS_MODE_7_BIT + * + * ## Unsupported Functionality # + * The CC26XX I2C driver currently does not support: + * - Multi-controller mode + * - I2C target mode + * + * # Instrumentation # + * The I2C driver interface produces log statements if instrumentation is + * enabled. + * + * Diagnostics Mask | Log details | + * ---------------- | ----------- | + * Diags_USER1 | basic I2C operations performed | + * Diags_USER2 | detailed I2C operations performed | + * + ****************************************************************************** + */ + +#ifndef ti_drivers_i2c_I2CCC26XX__include +#define ti_drivers_i2c_I2CCC26XX__include + +#include +#include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief I2CCC26XX Pin Configuration + * + * Pin configuration that holds non-default pins. The default pin configuration + * is typically defined in ::I2CCC26XX_HWAttrsV1 placed in the board file. + * The pin configuration structure is used by setting the custom void + * pointer in the ::I2C_Params to point to this struct. If the custom + * void pointer is NULL, the ::I2CCC26XX_HWAttrsV1 pin mapping will be used. + * @code + * I2C_Handle handle; + * I2C_Params i2cParams; + * I2CCC26XX_I2CPinCfg pinCfg; + * + * I2C_Params_init(&i2cParams); // sets custom to NULL + * pinCfg.pinSDA = CONFIG_I2C0_SDA1; + * pinCfg.pinSCL = CONFIG_I2C0_SCL1; + * i2cParams.custom = &pinCfg; + * + * handle = I2C_open(CONFIG_I2C, &i2cParams); + * @endcode + */ +typedef struct +{ + uint8_t pinSDA; + uint8_t pinSCL; +} I2CCC26XX_I2CPinCfg; + +/*! + * @brief I2CCC26XX Hardware attributes + * + * The baseAddr and intNum fields define the base address and the interrupt + * number of the I2C peripheral. These values are passed to driverlib APIs + * and therefore must be populated by driverlib macro definitions. These + * macros are found in the header files: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * The powerMngrId is the Power driver resource ID for the I2C peripheral. + * These macros are defined in PowerCC26XX.h + + * intPriority is the I2C peripheral's interrupt priority, as defined by the + * TI-RTOS kernel. This value is passed unmodified to Hwi_create(). + * + * swiPriority is the priority of a TI-RTOS kernel Swi that the I2C driver + * creates to finalize I2C transfers. See the documentation for the + * ti.sysbios.knl.Swi module for a description of Swi priorities. + * + * sdaPin and sclPin define the SDA and SCL pin mapping, respectively. These + * are typically defined with a macro in a header file, which maps to an + * IOID. For example, CC1350_LAUNCHXL.h defines BOARD_I2C0_SDA0 to be IOID_5. + * + * sdaPinMux and sclPinMux are values drawn from driverlib's IOC module, and + * map directly to a pin hardware code that selects I2C mode. + * + * A sample structure is shown below: + * @code + * const I2CCC26XX_HWAttrsV1 i2cCC26xxHWAttrs[CC1350_LAUNCHXL_I2CCOUNT] = { + * { + * .baseAddr = I2C0_BASE, + * .powerMngrId = PowerCC26XX_PERIPH_I2C0, + * .intNum = INT_I2C_IRQ, + * .intPriority = ~0, + * .swiPriority = 0, + * .sdaPin = CONFIG_I2C0_SDA0, + * .sdaPinMux = IOC_PORT_MCU_I2C_MSSDA, + * .sclPin = CONFIG_I2C0_SCL0, + * .sclPinMux = IOC_PORT_MCU_I2C_MSSCL, + * }, + * }; + * @endcode + */ +typedef struct +{ + I2C_BASE_HWATTRS + + /* + * I2C Swi priority. + * The higher the number, the higher the priority. + * The minimum is 0 and the maximum is 15 by default. + * The maximum can be reduced to save RAM by adding or modifying + * Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + + /* I2C peripheral's Power driver ID */ + PowerCC26XX_Resource powerMngrId; + + /* SDA pin index and mux */ + uint8_t sdaPin; + uint8_t sdaPinMux; + /* SCL pin index and mux */ + uint8_t sclPin; + uint8_t sclPinMux; +} I2CCC26XX_HWAttrsV1; + +/*! + * @brief I2CCC26XX Object. + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + I2C_BASE_OBJECT + + /* Swi object */ + SwiP_Struct swi; + + /* Bitrate of the I2C module */ + uint32_t bitRate; + + /* Pin indexes. We need to cache these because we might have custom pins */ + uint8_t sdaPin; + uint8_t sclPin; + + /* I2C power notification */ + void *i2cPostFxn; + Power_NotifyObj i2cPostObj; +} I2CCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2c_I2CCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/i2c/I2CSupport.h b/simplelink_lpf2/source/ti/drivers/i2c/I2CSupport.h new file mode 100644 index 00000000..86c7814d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/i2c/I2CSupport.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file I2CSupport.h + * + * @brief Holder of common helper functions for the I2C driver + * + * ============================================================================ + */ + +#ifndef ti_drivers_I2CSupport__include +#define ti_drivers_I2CSupport__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Function to send a finish command to the controller module + * + * @param[in] hwAttrs A pointer to an I2C_HWAttrs structure + */ +extern void I2CSupport_controllerFinish(I2C_HWAttrs const *hwAttrs); + +/*! + * @brief Function to set power constraint + */ +extern void I2CSupport_powerSetConstraint(void); + +/*! + * @brief Function to release power constraint + */ +extern void I2CSupport_powerRelConstraint(void); + +/*! + * @brief Function to initialize transfers + * + * @param[in] handle An I2C_Handle returned from I2C_open() + * @param[in] transaction A pointer to an I2C_Transaction + * + * @return Returns a status indicating success or failure of the transfer + * + * @retval I2C_STATUS_SUCCESS The transfer was successful + * @retval I2C_STATUS_INCOMPLETE I2C transaction is in progress or returned + * without completing + * @retval I2C_STATUS_BUS_BUSY I2C bus already in use by another I2C Controller + */ +extern int_fast16_t I2CSupport_primeTransfer(I2C_Handle handle, I2C_Transaction *transaction); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_I2CSupport__include */ diff --git a/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.c b/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.c new file mode 100644 index 00000000..c8caa0ba --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.c @@ -0,0 +1,1132 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include + +#include +#include DeviceFamily_constructPath(driverlib/i2s.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) + +#include +#include +#include +#include +#include +#include + +#define I2S_CLOCK_DIVIDER_MAX 1024U +#define I2S_CLOCK_DIVIDER_MIN 2U +#define I2S_NB_CHANNELS_MAX 8U +#define I2S_RAW_CLOCK_48MHZ 48000000U /* Clock if not divided (48 MHz) */ + +/* Forward declarations */ +static bool initObject(I2S_Handle handle, I2S_Params *params); +static void initIO(I2S_Handle handle); +static void finalizeIO(I2S_Handle handle); +static void initHw(I2S_Handle handle); +static void I2S_hwiIntFxn(uintptr_t arg); +static int i2sPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); + +static void configSerialFormat(I2S_Handle handle); +static void configChannels(I2S_Handle handle); +static void configClocks(I2S_Handle handle); +static void enableClocks(I2S_Handle handle); + +static bool computeSCKDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result); +static bool computeWSDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result); +static uint8_t getNumberOfChannels(const uint8_t channelsList); +static uint32_t getBitRate(I2S_Handle handle, const I2S_Params *params); +static uint16_t computeMemoryStep(I2S_Handle handle, + I2S_DataInterfaceUse expectedUseSD0, + I2S_DataInterfaceUse expectedUseSD1); +static void updatePointer(I2S_Handle handle, I2SCC26XX_Interface *interface); + +/* Extern globals */ +extern const I2S_Config I2S_config[]; +extern const uint_least8_t I2S_count; + +/* Static globals */ +static bool isInitialized = (bool)false; + +/* + * ======== I2S_init ======== + */ +void I2S_init(void) +{ + uint_least8_t i; + + if (!isInitialized) + { + /* Call each instances' driver init function */ + for (i = 0; i < I2S_count; i++) + { + I2S_Handle handle = (I2S_Handle) & (I2S_config[i]); + I2SCC26XX_Object *object = (I2SCC26XX_Object *)handle->object; + object->isOpen = (bool)false; + } + + isInitialized = (bool)true; + } +} + +/* + * ======== I2S_open ======== + */ +I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params) +{ + I2S_Handle handle; + I2SCC26XX_Object *object; + + handle = (I2S_Handle) & (I2S_config[index]); + object = handle->object; + + DebugP_assert(index < I2S_count); + + /* Check if module is initialized. */ + if (!isInitialized || object->isOpen) + { + handle = NULL; + } + + /* Initialization of the I2S-object and verification of the parameters. */ + else if (!initObject(handle, params)) + { + /* The parameters provided are not correct. */ + handle = NULL; + } + else + { + /* Configure IOs, always succeeds */ + initIO(handle); + + object->isOpen = (bool)true; + + /* Register power dependency - i.e. power up and enable clock for I2S. */ + Power_setDependency(PowerCC26XX_PERIPH_I2S); + + /* Register notification functions */ + Power_registerNotify(&object->i2sPostObj, + PowerCC26XX_AWAKE_STANDBY, + (Power_NotifyFxn)i2sPostNotify, + (uintptr_t)handle); + + HwiP_Params hwiParams; + I2SCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Register HW interrupt */ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t)handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), INT_I2S_IRQ, (HwiP_Fxn)I2S_hwiIntFxn, &hwiParams); + + HwiP_clearInterrupt(INT_I2S_IRQ); + } + + return handle; +} + +/* + * ======== I2S_close ======== + */ +void I2S_close(I2S_Handle handle) +{ + I2SCC26XX_Object *object = handle->object; + + /* Disable I2S interrupts. */ + I2SIntDisable(I2S0_BASE, I2S_INT_ALL); + HwiP_destruct(&(object->hwi)); + + /* Wait for end of started transactions */ + while ((I2SInPointerNextGet(I2S0_BASE) != 0U) || (I2SOutPointerNextGet(I2S0_BASE) != 0U)) {} + + while ((I2SInPointerGet(I2S0_BASE) != 0U) || (I2SOutPointerGet(I2S0_BASE) != 0U)) {} + + I2SInPointerSet(I2S0_BASE, 0U); + I2SOutPointerSet(I2S0_BASE, 0U); + + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); + + /* Disable I2S module */ + I2SStop(I2S0_BASE); + I2SSampleStampDisable(I2S0_BASE); + + /* Disable internal clocks */ + PRCMAudioClockDisable(); + + /* Deallocate pins */ + finalizeIO(handle); + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->i2sPostObj); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(PowerCC26XX_PERIPH_I2S); + + /* Mark the module as available */ + object->isOpen = (bool)false; +} + +/* + * ======== I2S_setReadQueueHead ======== + */ +void I2S_setReadQueueHead(I2S_Handle handle, I2S_Transaction *transaction) +{ + + DebugP_assert(&transaction != 0x0); + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_Interface *interface = &object->read; + + interface->activeTransfer = transaction; +} + +/* + * ======== I2S_setWriteQueueHead ======== + */ +void I2S_setWriteQueueHead(I2S_Handle handle, I2S_Transaction *transaction) +{ + + DebugP_assert(&transaction != 0x0); + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_Interface *interface = &object->write; + + interface->activeTransfer = transaction; +} + +/* + * ======== I2S_startClocks ======== + */ +void I2S_startClocks(I2S_Handle handle) +{ + + Power_setConstraint(PowerCC26XX_SB_DISALLOW); + + initHw(handle); + enableClocks(handle); +} + +/* + * ======== I2S_stopClocks ======== + */ +void I2S_stopClocks(I2S_Handle handle) +{ + + I2SIntClear(I2S0_BASE, I2S_INT_ALL); + + I2SIntDisable(I2S0_BASE, + (uint32_t)I2S_INT_TIMEOUT | (uint32_t)I2S_INT_BUS_ERR | (uint32_t)I2S_INT_WCLK_ERR | + (uint32_t)I2S_INT_PTR_ERR); + + I2SStop(I2S0_BASE); + I2SSampleStampDisable(I2S0_BASE); + + PRCMAudioClockDisable(); + PRCMLoadSet(); + + Power_releaseConstraint(PowerCC26XX_SB_DISALLOW); +} + +/* + * ======== I2S_startRead ======== + */ +void I2S_startRead(I2S_Handle handle) +{ + I2SCC26XX_Object *object = handle->object; + + /* If a read interface is activated */ + if (object->read.memoryStep != 0) + { + + /* Enable I2S Hardware Interrupts */ + I2SIntEnable(I2S0_BASE, + (uint32_t)I2S_INT_DMA_IN | (uint32_t)I2S_INT_TIMEOUT | (uint32_t)I2S_INT_BUS_ERR | + (uint32_t)I2S_INT_WCLK_ERR | (uint32_t)I2S_INT_PTR_ERR); + + /* At startup, INPTRNEXT must be written twice. The first value will be directly copy to INPTR */ + object->ptrUpdateFxn(handle, &object->read); + object->ptrUpdateFxn(handle, &object->read); + + /* Configuring sample stamp generator will trigger the audio stream to start */ + I2SSampleStampInConfigure(I2S0_BASE, (HWREGH(I2S0_BASE + I2S_O_STMPWCNT) + object->startUpDelay)); + } +} + +/* + * ======== I2S_startWrite ======== + */ +void I2S_startWrite(I2S_Handle handle) +{ + + I2SCC26XX_Object *object = handle->object; + + /* If a write interface is activated */ + if (object->write.memoryStep != 0) + { + + /* Enable I2S Hardware Interrupts */ + I2SIntEnable(I2S0_BASE, + (uint32_t)I2S_INT_DMA_OUT | (uint32_t)I2S_INT_TIMEOUT | (uint32_t)I2S_INT_BUS_ERR | + (uint32_t)I2S_INT_WCLK_ERR | (uint32_t)I2S_INT_PTR_ERR); + + /* At startup, OUTPTRNEXT must be written twice. The first value will be directly copy to OUTPTR */ + object->ptrUpdateFxn(handle, &object->write); + object->ptrUpdateFxn(handle, &object->write); + + /* Configuring sample stamp generator will trigger the audio stream to start */ + I2SSampleStampOutConfigure(I2S0_BASE, (HWREGH(I2S0_BASE + I2S_O_STMPWCNT) + object->startUpDelay)); + } +} + +/* + * ======== I2S_stopRead ======== + */ +void I2S_stopRead(I2S_Handle handle) +{ + + I2SCC26XX_Object *object = handle->object; + + /* If a read interface is activated */ + if (object->read.memoryStep != 0) + { + + /* Disable DMA_IN interrupts: we do not need anymore to refresh IN_PTR */ + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_IN); + + /* Wait for end of started transfers */ + while (I2SInPointerNextGet(I2S0_BASE) != 0U) {} + while (I2SInPointerGet(I2S0_BASE) != 0U) {} + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_IN); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + + I2SInPointerSet(I2S0_BASE, 0U); + } +} + +/* + * ======== I2S_stopWrite ======== + */ +void I2S_stopWrite(I2S_Handle handle) +{ + + I2SCC26XX_Object *object = handle->object; + + /* If a write interface is activated */ + if (object->write.memoryStep != 0) + { + + /* Disable DMA_OUT interrupts: we do not need anymore to refresh OUT_PTR */ + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_OUT); + + /* Wait for end of started transactions */ + while (I2SOutPointerNextGet(I2S0_BASE) != 0U) {} + while (I2SOutPointerGet(I2S0_BASE) != 0U) {} + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_OUT); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); + + I2SOutPointerSet(I2S0_BASE, 0U); + } +} + +/* + * ======== I2S_hwiIntFxn ======== + * Hwi function that processes I2S interrupts. + */ +static void I2S_hwiIntFxn(uintptr_t arg) +{ + + I2S_Handle handle = (I2S_Handle)arg; + I2SCC26XX_Object *object = handle->object; + uint16_t errStatus = 0U; + + uint32_t interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + + /* I2S_INT_PTR_ERR flag should be consider if and only if I2S_INT_DMA_IN or I2S_INT_DMA_OUT is raised at the same + * time */ + if ((((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && + ((((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U)) || + ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U)))) + { + + if ((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U) + { + /* Try to update IN_PTR */ + object->ptrUpdateFxn(handle, &object->read); + /* Check if we could clear I2S_INT_DMA_IN flag */ + interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + /* I2S_INT_PTR_ERR is confirmed if we could not clear I2S_INT_DMA_IN flag */ + if (((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && + ((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U)) + { + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + errStatus = errStatus | I2S_PTR_READ_ERROR; + } + } + + if ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U) + { + /* Try to update OUT_PTR */ + object->ptrUpdateFxn(handle, &object->write); + /* Check if we could clear I2S_INT_DMA_OUT flag */ + interruptStatus = I2SIntStatus(I2S0_BASE, (bool)true); + /* I2S_INT_PTR_ERR is confirmed if we could not clear I2S_INT_DMA_OUT flag */ + if (((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) && + ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U)) + { + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + errStatus = errStatus | I2S_PTR_WRITE_ERROR; + } + } + } + else if ((interruptStatus & (uint32_t)I2S_INT_PTR_ERR) != 0U) + { + /* I2S_INT_PTR_ERR must not be considered as no I2S_INT_DMA_xxx flag is set */ + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + } + + if ((interruptStatus & (uint32_t)I2S_INT_DMA_IN) != 0U) + { + object->ptrUpdateFxn(handle, &object->read); + } + + if ((interruptStatus & (uint32_t)I2S_INT_DMA_OUT) != 0U) + { + object->ptrUpdateFxn(handle, &object->write); + } + + if ((interruptStatus & (uint32_t)I2S_INT_TIMEOUT) != 0U) + { + I2SIntClear(I2S0_BASE, I2S_INT_TIMEOUT); + errStatus = errStatus | I2S_TIMEOUT_ERROR; + } + + if ((interruptStatus & (uint32_t)I2S_INT_BUS_ERR) != 0U) + { + I2SIntClear(I2S0_BASE, I2S_INT_BUS_ERR); + errStatus = errStatus | I2S_BUS_ERROR; + } + + if ((interruptStatus & (uint32_t)I2S_INT_WCLK_ERR) != 0U) + { + I2SIntClear(I2S0_BASE, I2S_INT_WCLK_ERR); + errStatus = errStatus | I2S_WS_ERROR; + } + + if (errStatus != 0U) + { + object->errorCallback(handle, errStatus, NULL); + } +} + +/* + * ======== initHw ======== + * This functions initializes the I2S hardware module. + * + * @pre Function assumes that the I2S handle is pointing to a hardware + * module which has already been opened. + */ +static void initHw(I2S_Handle handle) +{ + + /* Configure serial format. */ + configSerialFormat(handle); + /* Configure the channels used on each data interface. */ + configChannels(handle); + /* Configure the clocks for the CCLK, SCK and WS signals. */ + configClocks(handle); +} + +/* + * ======== updatePointer ======== + */ +static void updatePointer(I2S_Handle handle, I2SCC26XX_Interface *interface) +{ + + I2S_Transaction *transaction = interface->activeTransfer; + + if (transaction != NULL) + { + + /* Critical section to prevent any modification or deletion of the current transaction */ + uintptr_t key; + key = HwiP_disable(); + + /* Transaction */ + if ((transaction->bytesTransferred + interface->memoryStep) > transaction->bufSize) + { + /* The current transaction is over */ + I2S_Transaction *transactionFinished = transaction; + transaction = (I2S_Transaction *)List_next(&transactionFinished->queueElement); + interface->activeTransfer = transaction; + + transactionFinished->numberOfCompletions++; + transactionFinished->untransferredBytes = transactionFinished->bufSize - + transactionFinished->bytesTransferred; + transactionFinished->bytesTransferred = 0; + + if (transaction != NULL) + { + interface->pointerSet(I2S0_BASE, ((uint32_t)transaction->bufPtr + transaction->bytesTransferred)); + transaction->bytesTransferred += interface->memoryStep; + interface->callback(handle, I2S_TRANSACTION_SUCCESS, transactionFinished); + } + else + { + /* Not anymore transaction */ + interface->callback(handle, I2S_ALL_TRANSACTIONS_SUCCESS, transactionFinished); + + /* If needed the interface must be stopped */ + if (interface->activeTransfer != NULL) + { + /* Application called I2S_setXxxxQueueHead() + * -> new transfers can be executed next time */ + } + else if ((I2S_Transaction *)List_next(&transactionFinished->queueElement) != NULL) + { + /* Application queued transactions after the transaction finished + * -> activeTransfer must be modified and transfers can be executed next time */ + interface->activeTransfer = (I2S_Transaction *)List_next(&transactionFinished->queueElement); + } + else + { + /* Application did nothing, we need to stop the interface to avoid errors + * However, we cannot spin here while the hardware stops, this is an ISR context! + */ + if (interface->stopInterface == I2S_stopRead) + { + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_IN); + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_IN); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + + I2SInPointerSet(I2S0_BASE, 0U); + } + + if (interface->stopInterface == I2S_stopWrite) + { + I2SIntDisable(I2S0_BASE, I2S_INT_DMA_OUT); + + I2SIntClear(I2S0_BASE, I2S_INT_DMA_OUT); + I2SIntClear(I2S0_BASE, I2S_INT_PTR_ERR); + + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); + + I2SOutPointerSet(I2S0_BASE, 0U); + } + } + } + } + else + { + interface->pointerSet(I2S0_BASE, ((uint32_t)transaction->bufPtr + transaction->bytesTransferred)); + transaction->bytesTransferred += interface->memoryStep; + } + + HwiP_restore(key); + } + else + { + /* No element in the queue: do nothing */ + } +} + +/* + * ======== initObject ======== + */ +static bool initObject(I2S_Handle handle, I2S_Params *params) +{ + + I2SCC26XX_Object *object = handle->object; + I2SCC26XX_DataInterface *SD0; + I2SCC26XX_DataInterface *SD1; + + bool retVal = (bool)true; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + if (params == NULL) + { + /* This module cannot be open if the user does not provide the expected pointers callback */ + /* So it is no point to try to load the default value here. */ + retVal = (bool)false; + } + else + { + object->moduleRole = params->moduleRole; + object->invertWS = params->invertWS; + object->samplingEdge = params->samplingEdge; + object->beforeWordPadding = params->beforeWordPadding; + object->afterWordPadding = params->afterWordPadding; + object->phaseType = params->phaseType; + object->bitsPerWord = params->bitsPerWord; + object->startUpDelay = params->startUpDelay; + + object->dataShift = (params->trueI2sFormat) ? 1 : 0; + + if (params->memorySlotLength == I2S_MEMORY_LENGTH_16BITS) + { + object->memorySlotLength = I2S_MEM_LENGTH_16; + } + else if (params->memorySlotLength == I2S_MEMORY_LENGTH_24BITS) + { + object->memorySlotLength = I2S_MEM_LENGTH_24; + } + else + { + retVal = (bool)false; + } + object->read.pointerSet = I2SInPointerSet; + object->read.stopInterface = I2S_stopRead; + object->write.pointerSet = I2SOutPointerSet; + object->write.stopInterface = I2S_stopWrite; + object->ptrUpdateFxn = updatePointer; + + SD0->interfaceConfig = params->SD0Use; + SD0->channelsUsed = params->SD0Channels; + SD0->numberOfChannelsUsed = getNumberOfChannels((uint8_t)SD0->channelsUsed); + SD1->interfaceConfig = params->SD1Use; + SD1->channelsUsed = params->SD1Channels; + SD1->numberOfChannelsUsed = getNumberOfChannels((uint8_t)SD1->channelsUsed); + + if (params->CCLKDivider == 1U) + { + retVal = (bool)false; + } + object->CCLKDivider = params->CCLKDivider; + uint16_t SCKDivider = 0U; + if (!computeSCKDivider(handle, params, &SCKDivider)) + { + retVal = (bool)false; + } + object->SCKDivider = SCKDivider; + uint16_t WSDivider = 0U; + if (!computeWSDivider(handle, params, &WSDivider)) + { + retVal = (bool)false; + } + object->WSDivider = WSDivider; + + object->read.memoryStep = computeMemoryStep(handle, I2S_SD0_INPUT, I2S_SD1_INPUT); + object->write.memoryStep = computeMemoryStep(handle, I2S_SD0_OUTPUT, I2S_SD1_OUTPUT); + + /* If the user set a fixed length of the buffers, we can optimize the runtime by setting the DMA buffer length + */ + if (params->fixedBufferLength == 0U) + { + retVal = (bool)false; + } + else + { + if (params->fixedBufferLength != 1U) + { + uint16_t memoryStep = ((object->read.memoryStep > object->write.memoryStep) ? object->read.memoryStep + : object->write.memoryStep); + if (memoryStep != 0U) + { + uint8_t dmaBuffSizeDivider = 1U; + uint16_t dmaBuffSizeConfig = (uint16_t)(((((params->fixedBufferLength) / memoryStep) * 2U) - 1U) / + dmaBuffSizeDivider); + + /* The value of the DMA buffer size is limited to 255 */ + while (dmaBuffSizeConfig > 255U) + { + dmaBuffSizeDivider = dmaBuffSizeDivider * 2; + dmaBuffSizeConfig = (uint16_t)(((((params->fixedBufferLength) / memoryStep) * 2U) - 1U) / + dmaBuffSizeDivider); + } + + object->dmaBuffSizeConfig = (uint8_t)dmaBuffSizeConfig; /* dmaBuffSizeConfig < 255 */ + + object->read.memoryStep = (object->read.memoryStep != 0U) + ? (uint16_t)(params->fixedBufferLength / dmaBuffSizeDivider) + : 0U; + object->write.memoryStep = (object->write.memoryStep != 0U) + ? (uint16_t)(params->fixedBufferLength / dmaBuffSizeDivider) + : 0U; + } + } + else + { + object->dmaBuffSizeConfig = 1U; + } + } + + object->read.callback = params->readCallback; + if ((object->read.callback == NULL) && (object->read.memoryStep != 0U)) + { + retVal = (bool)false; + } + object->write.callback = params->writeCallback; + if ((object->write.callback == NULL) && (object->write.memoryStep != 0U)) + { + retVal = (bool)false; + } + object->errorCallback = params->errorCallback; + if (object->errorCallback == NULL) + { + retVal = (bool)false; + } + + object->read.activeTransfer = NULL; + object->write.activeTransfer = NULL; + } + + return retVal; +} + +/* + * ======== initIO ======== + */ +static void initIO(I2S_Handle handle) +{ + I2SCC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + + /* Make sure all pins have their input buffers enabled */ + GPIO_setConfigAndMux(hwAttrs->pinWS, GPIO_CFG_INPUT, IOC_PORT_MCU_I2S_WCLK); + GPIO_setConfigAndMux(hwAttrs->pinSCK, GPIO_CFG_INPUT, IOC_PORT_MCU_I2S_BCLK); + GPIO_setConfigAndMux(hwAttrs->pinCCLK, GPIO_CFG_INPUT, IOC_PORT_MCU_I2S_MCLK); + GPIO_setConfigAndMux(hwAttrs->pinSD0, GPIO_CFG_INPUT, IOC_PORT_MCU_I2S_AD0); + GPIO_setConfigAndMux(hwAttrs->pinSD1, GPIO_CFG_INPUT, IOC_PORT_MCU_I2S_AD1); +} + +/* + * ======== finalizeIO ======== + */ +static void finalizeIO(I2S_Handle handle) +{ + I2SCC26XX_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + + GPIO_resetConfig(hwAttrs->pinWS); + GPIO_resetConfig(hwAttrs->pinSCK); + GPIO_resetConfig(hwAttrs->pinCCLK); + GPIO_resetConfig(hwAttrs->pinSD0); + GPIO_resetConfig(hwAttrs->pinSD1); +} + +/* + * ======== getNumberOfChannels ======== + */ +static uint8_t getNumberOfChannels(const uint8_t channelsList) +{ + + uint8_t i = 0; + uint8_t nbChannelsUsed = 0; + for (i = 0; i <= (I2S_NB_CHANNELS_MAX - 1U); i++) + { + if (((channelsList >> i) & 1U) == 1U) + { + nbChannelsUsed++; + } + } + return nbChannelsUsed; +} + +/* + * ======== computeSCKDivider ======== + */ +static bool computeSCKDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result) +{ + + uint32_t expectedBitRate = getBitRate(handle, params); + uint32_t freqDividerSCK = 0U; + + bool retVal = (bool)true; + + *result = 0; + + if (expectedBitRate == 0U) + { + retVal = (bool)false; + } + else + { + /* We want to round the integer division: ROUND(a/b)=(a+b/2)/b */ + freqDividerSCK = ((I2S_RAW_CLOCK_48MHZ + expectedBitRate / 2) / expectedBitRate); + + if ((freqDividerSCK < I2S_CLOCK_DIVIDER_MIN) || (freqDividerSCK > I2S_CLOCK_DIVIDER_MAX)) + { + retVal = (bool)false; + } + else + { + /* If we reach this code it means we have freqDividerSCK <= 1024 */ + uint16_t u16FreqDividerSCK = (uint16_t)freqDividerSCK; + *result = u16FreqDividerSCK; + } + } + return retVal; +} + +/* + * ======== computeWSDivider ======== + */ +static bool computeWSDivider(I2S_Handle handle, const I2S_Params *params, uint16_t *result) +{ + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + bool retVal = (bool)true; + uint8_t numbOfChannels = 0U; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + *result = 0x0000; + + if (SD0->interfaceConfig) + { + numbOfChannels = (numbOfChannels > SD0->numberOfChannelsUsed) ? numbOfChannels : SD0->numberOfChannelsUsed; + } + if (SD1->interfaceConfig) + { + numbOfChannels = (numbOfChannels > SD1->numberOfChannelsUsed) ? numbOfChannels : SD1->numberOfChannelsUsed; + } + + uint16_t sampleLength = 0U; + + switch (object->phaseType) + { + + case (I2S_PHASE_TYPE_DUAL): + + /* In dual-phase format, each phase represents a channel and is divided into the three intervals: + * + * Data delay (optional): BCLK periods between the first WCLK edge and MSB of the audio channel + * data transfered during the phase. + * + * Word: BCLK periods during which one sample word (a single channel) is transfered. + * + * Idle (optional): BCLK periods between the word interval and the next phase. + */ + sampleLength += object->beforeWordPadding; + sampleLength += object->bitsPerWord; + sampleLength += object->afterWordPadding; + + /* WS is high for WDIV[9:0] (1 to 1023) SCK periods and low for WDIV[9:0] (1 to 1023) SCK periods. + * WS frequency = SCK frequency / (2 x WDIV[9:0]) + * Dual phase protocols don't accept more than two channels + */ + if (numbOfChannels <= 2U) + { + *result = sampleLength; + } + else + { + retVal = (bool)false; + } + break; + + case (I2S_PHASE_TYPE_SINGLE): + + /* In single phase format, from 1 to 8 sample words (channels) are transfered back-to-back using + * a single phase. The phase is divided into the three intervals: + * + * Data delay (optional) : BCLK periods between the first WCLK edge and MSB of the FIRST audio channel + * data transfered. + * + * Word: BCLK periods during which from 1 to 8 channels are transfered back-to-back. + * + * Idle (optional): BCLK periods between the word interval and the next phase. + */ + sampleLength += object->beforeWordPadding; + sampleLength += (object->bitsPerWord * numbOfChannels); + sampleLength += object->afterWordPadding; + + /* WS is high for 1 SCK period and low for WDIV[9:0] (1 to 1023) SCK periods. + * WS frequency = SCK frequency / (1 + PRCM:I2SWCLKDIV.WDIV[9:0]) + * Single phase protocols don't accept more than 8 channels + */ + if (numbOfChannels <= 8U) + { + *result = sampleLength; + } + else + { + retVal = (bool)false; + } + break; + + default: + retVal = (bool)false; + } + return retVal; +} + +/* + * ======== getBitRate ======== + */ +static uint32_t getBitRate(I2S_Handle handle, const I2S_Params *params) +{ + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + uint32_t dataLength = 0U; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + uint16_t sampleLength = 0U; + sampleLength += object->beforeWordPadding; + sampleLength += object->bitsPerWord; + sampleLength += object->afterWordPadding; + + uint32_t samplePerChannelPerSecond = params->samplingFrequency; + uint8_t numbOfChannels = 0U; + if (SD0->interfaceConfig) + { + uint8_t numbOfChannelsSD0 = (object->phaseType == I2S_PHASE_TYPE_DUAL) ? 2U : SD0->numberOfChannelsUsed; + numbOfChannels = (numbOfChannelsSD0 > numbOfChannels) ? numbOfChannelsSD0 : numbOfChannels; + } + if (SD1->interfaceConfig) + { + uint8_t numbOfChannelsSD1 = (object->phaseType == I2S_PHASE_TYPE_DUAL) ? 2U : SD1->numberOfChannelsUsed; + numbOfChannels = (numbOfChannelsSD1 > numbOfChannels) ? numbOfChannelsSD1 : numbOfChannels; + } + + /* No risk of overflow: highest possible value is 24 000 000 (any higher value has no sense) */ + dataLength = (uint32_t)((uint32_t)numbOfChannels * (uint32_t)sampleLength); + return (dataLength * samplePerChannelPerSecond); +} + +/* + * ======== configSerialFormat ======== + */ +static void configSerialFormat(I2S_Handle handle) +{ + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + /* + * Word length depends on the phase type: + * For dual-phase format (I2S, LJF, RJF) this is the maximum number of bits per + * word (object->bitsPerWord + object->afterWordPadding). + * For single-phase format (DSP) this is the exact number of bits per word (object->bitsPerWord). + */ + + I2SFormatConfigure(I2S0_BASE, + (object->beforeWordPadding + object->dataShift), + (uint8_t)object->memorySlotLength, + ((object->samplingEdge == I2S_SAMPLING_EDGE_RISING) ? I2S_POS_EDGE : I2S_NEG_EDGE), + (bool)(object->phaseType == I2S_PHASE_TYPE_DUAL), + ((object->phaseType == I2S_PHASE_TYPE_DUAL) ? (object->bitsPerWord + object->afterWordPadding) + : object->bitsPerWord), + (object->dmaBuffSizeConfig + 1)); + + /* To avoid false start-up triggers, I2S:STMPINTRIG and I2S:STMPOUTTRIG must + * initially be equal to or higher than I2S:STMPWPER, which is set as + * (object->dmaBuffSizeConfig + 1) above. Since, 0xFFFFU > UINT8_MAX + 1 + * this should prevent false triggers. UINT8_MAX is used above because it + * matches the type of dmaBuffSizeConfig, and is the width of the + * corresponding register in hardware. + */ + I2SSampleStampInConfigure(I2S0_BASE, 0xFFFFU); + I2SSampleStampOutConfigure(I2S0_BASE, 0xFFFFU); +} + +/* + * ======== configChannels ======== + */ +static void configChannels(I2S_Handle handle) +{ + + I2SCC26XX_Object const *object; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + /* Get the pointer to the SD0 and SD1 interfaces*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + I2SFrameConfigure(I2S0_BASE, + (uint8_t)SD0->interfaceConfig, + (uint8_t)SD0->channelsUsed, + (uint8_t)SD1->interfaceConfig, + (uint8_t)SD1->channelsUsed); +} + +/* + * ======== configClocks ======== + */ +static void configClocks(I2S_Handle handle) +{ + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + I2SWclkConfigure(I2S0_BASE, (bool)object->moduleRole, object->invertWS); + + /* Set internal audio clock source */ + if (object->moduleRole) + { + + PRCMAudioClockInternalSource(); + PRCMAudioClockConfigOverride((uint8_t)object->samplingEdge, + (uint8_t)object->phaseType, + (uint32_t)object->CCLKDivider, + (uint32_t)object->SCKDivider, + (uint32_t)object->WSDivider); + } + + /* Set external audio clock source */ + else + { + PRCMAudioClockExternalSource(); + } +} + +/* + * ======== enableClocks ======== + */ +static void enableClocks(I2S_Handle handle) +{ + + I2SCC26XX_Object const *object; + + /* Get the pointer to the object*/ + object = handle->object; + + I2SStart(I2S0_BASE, object->dmaBuffSizeConfig); + + /* Enable sample stamps */ + I2SSampleStampEnable(I2S0_BASE); + + /* Reset WCLK counter */ + I2SWclkCounterReset(I2S0_BASE); + + /* Enable internal clocks */ + PRCMAudioClockEnable(); + + /* Activate clocks (no clock is running before this call) + * (clocks must be correctly set before) + */ + PRCMLoadSet(); +} + +/* + * ======== computeMemoryStep ======== + */ +static uint16_t computeMemoryStep(I2S_Handle handle, + I2S_DataInterfaceUse expectedUseSD0, + I2S_DataInterfaceUse expectedUseSD1) +{ + + I2SCC26XX_Object const *object; + uint8_t numbOfChannels = 0; + uint8_t sampleMemoryLength = 16; + uint16_t memoryNeeded = 0; + I2SCC26XX_DataInterface const *SD0; + I2SCC26XX_DataInterface const *SD1; + + const uint8_t byteLength = 8U; + + /* Get the pointer to the object*/ + object = handle->object; + SD0 = &object->dataInterfaceSD0; + SD1 = &object->dataInterfaceSD1; + + if (SD0->interfaceConfig == expectedUseSD0) + { + numbOfChannels += SD0->numberOfChannelsUsed; + } + + if (SD1->interfaceConfig == expectedUseSD1) + { + numbOfChannels += SD1->numberOfChannelsUsed; + } + + if (object->memorySlotLength == I2S_MEM_LENGTH_24) + { + sampleMemoryLength = 24; + } + + /*In the worst case we have 16x24x2=768 < 2^16 */ + memoryNeeded = (uint16_t)((uint16_t)numbOfChannels * (uint16_t)sampleMemoryLength * (uint16_t)2U); + + /* bits to byte conversion: we manage to have full bytes */ + if ((memoryNeeded % byteLength) != 0U) + { + memoryNeeded += (byteLength - (memoryNeeded % byteLength)); + } + memoryNeeded = memoryNeeded / byteLength; + + return memoryNeeded; +} + +/* + * ======== i2sPostNotify ======== + * This functions is called to notify the I2S driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the I2S handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +static int i2sPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + + /* Reconfigure the hardware if returning from sleep */ + if (eventType == (uint32_t)PowerCC26XX_AWAKE_STANDBY) + { + initHw((I2S_Handle)clientArg); + } + + return Power_NOTIFYDONE; +} diff --git a/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.h b/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.h new file mode 100644 index 00000000..9d5079e6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/i2s/I2SCC26XX.h @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2019-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*! ============================================================================ + * @file I2SCC26XX.h + * + * @brief I2S driver implementation for a CC26XX I2S controller + * + * # Limitations # + * + * ## Flash Memory range ## + * + * The I2S driver is unable to access flash memory in the address range + * 0x0000 - 0x2000 on devices based on the Cortex M33+ core (CC26X3/CC26X4) due + * to security constraints. + * + * ## Supported #I2S_MemoryLength values ## + * Only the following memory lengths are supported: + * - #I2S_MEMORY_LENGTH_16BITS + * - #I2S_MEMORY_LENGTH_24BITS + * + * ## #I2S_Params Attributes Limitations ## + * + * Some attributes in the #I2S_Params structure have a limited set of supported + * values. These limitations are described below: + * - #I2S_Params.samplingFrequency + * - The SCK frequency resulting from the selected sampling frequency should + * be between 47 kHz and 4 MHz. + * - #I2S_Params.isDMAUnused + * - Must be false. All transmissions are always performed by the I2S module's + * own DMA. + * - #I2S_Params.isMSBFirst + * - Must be true. All samples are always transmitted MSB first. + * - #I2S_Params.memorySlotLength + * - Must be one of the suported #I2S_MemoryLength values listed in the above + * section. + * - #I2S_Params.fixedBufferLength + * - Additional restriction: Must be an even multiple of the number of bytes + * in a frame. + * + *
+ * # Sample Buffers # + * + * This section describes the structure and requirements for the sample buffers + * used in the #I2S_Transaction objects. + * + * Sample words are read from or written to the sample buffers in little-endian + * byte order, meaning that the least significant byte (LSByte) is stored at the + * lower byte address, and the most significant byte (MSByte) is stored at the + * higher byte address. + * + * The sample buffers are divided into frames which are further subdivided into + * channels, and if a channel is used by both SD0 and SD1 (where the direction + * of the two pins are the same), then that channel is further subdivided into a + * sample word for first SD0 and then SD1. + * + * ## Buffer Size Requirements ## + * + * The size of the buffers used in #I2S_Transaction objects must be an even + * multiple of the number of bytes per frame. I.e. the number of bytes in the + * buffers must be of the form: 2*n*k, where k is the size of a frame in bytes + * and n is an integer satisfying n>=2. 2*n is the number of frames in the + * buffer. + * + * ## General Sample Buffer Structure ## + * + * Below code describes the general structure of a sample buffer if SD0 and SD1 + * are configured to the same direction. + * + * @code + * struct + * { + * #if SD0_USE_CHANNEL_0 || SD1_USE_CHANNEL_0 + * struct + * { + * #if SD0_USE_CHANNEL_0 + * uint8_t sd0SampleWord[BYTES_PER_WORD]; + * #endif + * #if SD1_USE_CHANNEL_0 + * uint8_t sd1SampleWord[BYTES_PER_WORD]; + * #endif + * } channel0; + * #endif + * #if SD0_USE_CHANNEL_1 || SD1_USE_CHANNEL_1 + * struct + * { + * #if SD0_USE_CHANNEL_1 + * uint8_t sd0SampleWord[BYTES_PER_WORD]; + * #endif + * #if SD1_USE_CHANNEL_1 + * uint8_t sd1SampleWord[BYTES_PER_WORD]; + * #endif + * } channel1; + * #endif + * // ... + * #if SD0_USE_CHANNEL_8 || SD1_USE_CHANNEL_8 + * struct + * { + * #if SD0_USE_CHANNEL_8 + * uint8_t sd0SampleWord[BYTES_PER_WORD]; + * #endif + * #if SD1_USE_CHANNEL_8 + * uint8_t sd1SampleWord[BYTES_PER_WORD]; + * #endif + * } channel8; + * #endif + * } sampleBufferFrames[FRAMES_PER_BUFFER]; + * @endcode + * + * Notes: + * - \c SD0_USE_CHANNEL_n should be true if SD0 uses channel n, otherwise false. + * - \c SD1_USE_CHANNEL_n should be true if SD1 uses channel n, otherwise false. + * - \c BYTES_PER_WORD is based on the configured memory length: + * - #I2S_MEMORY_LENGTH_16BITS: 2 + * - #I2S_MEMORY_LENGTH_24BITS: 3 + * - \c FRAMES_PER_BUFFER must be divisible by 2 + * - \c sampleBufferFrames needs to be cast to an \c uint8_t pointer to be used + * with the I2S driver. + * + * If SD0 and SD1 are not configured to the same direction (or only one is used) + * then the structure can be simplified as below: + * @code + * struct + * { + * #if USE_CHANNEL_0 + * uint8_t channel0SampleWord[BYTES_PER_WORD]; + * #endif + * #if USE_CHANNEL_1 + * uint8_t channel1SampleWord[BYTES_PER_WORD]; + * #endif + * // ... + * #if USE_CHANNEL_8 + * uint8_t channel8SampleWord[BYTES_PER_WORD]; + * #endif + * } sampleBufferFrames[FRAMES_PER_BUFFER]; + * @endcode + * + * Notes: + * - \c USE_CHANNEL_n should be true if channel n is used, otherwise false. + * + * + * ### Sample Buffer Structure Example ### + * + * If for example SD0 and SD1 are configured to the same direction and if + * channel 0 and 1 are used for SD0 and channel 0 is used for SD1, then the + * sample buffer would be structured as in the code below. + * + * @code + * struct + * { + * struct + * { + * uint8_t sd0SampleWord[BYTES_PER_WORD]; + * uint8_t sd1SampleWord[BYTES_PER_WORD]; + * } channel0; + * struct + * { + * uint8_t sd0SampleWord[BYTES_PER_WORD]; + * } channel1; + * } sampleBufferFrames[FRAMES_PER_BUFFER]; + * + * // Access LSB of sample 10 of channel 0 on SD1 + * uint8_t tmp = sampleBufferFrames[10].channel0.sd1SampleWord[0]; + * + * @endcode + * + * ============================================================================ + */ +#ifndef ti_drivers_i2s_I2SCC26XX__include +#define ti_drivers_i2s_I2SCC26XX__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief I2S Hardware attributes + * + * intPriority is the I2S peripheral's interrupt priority, as defined by the + * RTOS kernel. This value is passed unmodified to HwiP_construct(). + * + * pinSD1 and pinSD0 define the SD0 and SD1 data pin mapping, respectively. + * pinSCK, pinCCLK and pinWS define the SCK, CCLK and WS clock pin mapping, respectively. + * All these pins are typically defined with a macro in a header file, which maps to an IOID. + * + * A sample structure is shown below: + * @code + * const I2SCC26XX_HWAttrs i2sHWAttrs[CC26X2R1_LAUNCHXL_I2SCOUNT] = { + * { + * .pinSD1 = CONFIG_I2S_ADI, + * .pinSD0 = CONFIG_I2S_ADO, + * .pinSCK = CONFIG_I2S_BCLK, + * .pinCCLK = CONFIG_I2S_CCLK, + * .pinWS = CONFIG_I2S_WCLK, + * .intPriority = ~0, + * }, + * }; + * @endcode + */ +typedef struct +{ + uint_least8_t pinSD1; /*!< Pin used for SD1 signal. */ + uint_least8_t pinSD0; /*!< Pin used for SD0 signal. */ + uint_least8_t pinSCK; /*!< Pin used for SCK signal. */ + uint_least8_t pinCCLK; /*!< Pin used for CCLK signal. Not used in most of the applications. */ + uint_least8_t pinWS; /*!< Pin used for WS signal. */ + uint8_t intPriority; /*!< I2S Peripheral's interrupt priority. */ +} I2SCC26XX_HWAttrs; + +/*! + * @cond NODOC + * I2S data-interface + * + * This enum defines how the physical I2S interface (SD0/SD1) behaves. + * Do not modify. + */ +typedef struct +{ + uint8_t numberOfChannelsUsed; /*!< Number of channels used on SDx. */ + I2S_ChannelConfig channelsUsed; /*!< List of the used channels. */ + I2S_DataInterfaceUse interfaceConfig; /*!< IN / OUT / UNUSED */ +} I2SCC26XX_DataInterface; +/*! @endcond */ + +/*! + * @cond NODOC + * I2S interface + * + * This enum defines one of the interfaces (READ or WRITE) of the I2S module. + * Do not modify. + */ +typedef struct +{ + /*! Size of the memory step to access the following sample */ + uint16_t memoryStep; + + /*! Number of WS cycles to wait before starting the first transfer. + * This value is mostly used when performing constant latency transfers. + */ + uint16_t delay; + + /*! Pointer to callback */ + I2S_Callback callback; + + /*! Pointer on the function used to update PTR-NEXT */ + I2S_RegUpdate pointerSet; + + /*! Pointer on the function used to stop the interface */ + I2S_StopInterface stopInterface; + + /*! Pointer on the ongoing transfer */ + I2S_Transaction *activeTransfer; +} I2SCC26XX_Interface; +/*! @endcond */ + +/*! + * @brief The definition of a function used by the I2S driver + * to refresh the pointer + * + * @param I2S_Handle I2S_Handle + * + * @param I2SCC26XX_Interface *interface Pointer on the interface to update + * + */ +typedef void (*I2SCC26XX_PtrUpdate)(I2S_Handle handle, I2SCC26XX_Interface *interface); + +/*! + * @cond NODOC + * I2S Object. The application must not access any member variables + * of this structure! + */ +typedef struct +{ + + /*! To avoid multiple openings of the I2S. */ + bool isOpen; + + /*! WS inversion. + * - false: The WS signal is not internally inverted. + * - true: The WS signal is internally inverted. + */ + bool invertWS; + + /*! Select the size of the memory used using DriverLib defines. + * The two options are 16 bits and 24 bits. Any value can be selected, + * whatever the value of #bitsPerWord. + * - I2S_MEM_LENGTH_16: Memory length is 16 bits. + * - I2S_MEM_LENGTH_24: Memory length is 24 bits. + */ + uint8_t memorySlotLength; + + /*! When dataShift is set to 0, data are read/write on the data lines from + * the first SCK period of the half WS period to the last SCK edge of the + * WS half period. By setting dataShift to a value different from zero, you + * can postpone the moment when data are read/write during the WS half + * period. For example, by setting dataShift to 1, data are read/write on + * the data lines from the second SCK period of the half WS period to the + * first SCK edge of the next WS half period. If no padding is activated, + * this corresponds to the I2S standard. + */ + uint8_t dataShift; + + /*! Number of bits per word (must be between 8 and 24 bits). */ + uint8_t bitsPerWord; + + /*! Number of SCK periods between the first WS edge and the MSB of the first + * audio channel data transferred during the phase. + */ + uint8_t beforeWordPadding; + + /*! Number of SCK periods between the LSB of the last audio channel data + * transferred during the phase and the following WS edge. + */ + uint8_t afterWordPadding; + + /*! Number of consecutive frames (minus 1) in the samples buffers to be + * handled during one DMA transfer. This field must be set to a value x - 1 + * where x is between 1 and 255, both included. All the data buffers used + * must contain N*x frames or N*x*b bytes (with N an integer satisfying + * N>0, and b being the number of bytes per frame). + */ + uint8_t dmaBuffSizeConfig; + + /*! Select edge sampling type. */ + I2S_SamplingEdge samplingEdge; + + /*! Select if the current device is a Target or a Controller. */ + I2S_Role moduleRole; + + /*! Select phase type. */ + I2S_PhaseType phaseType; + + /*! Frequency divider for the CCLK signal. */ + uint16_t CCLKDivider; + + /*! Frequency divider for the SCK signal. */ + uint16_t SCKDivider; + + /*! Frequency divider for the WS signal. */ + uint16_t WSDivider; + + /*! Time (in number of WS cycles) to wait before the first transfer. */ + uint16_t startUpDelay; + + /*! Structure to describe the SD0 interface */ + I2SCC26XX_DataInterface dataInterfaceSD0; + + /*! Structure to describe the SD1 interface */ + I2SCC26XX_DataInterface dataInterfaceSD1; + + /* + * I2S SYS/BIOS objects + */ + /*! Hwi object for interrupts */ + HwiP_Struct hwi; + + /*! Pointer on the function used to update IN and OUT PTR-NEXT */ + I2SCC26XX_PtrUpdate ptrUpdateFxn; + + /*! Structure to describe the read (in) interface */ + I2SCC26XX_Interface read; + + /*! Structure to describe the write (out) interface */ + I2SCC26XX_Interface write; + + /*! Pointer to error callback */ + I2S_Callback errorCallback; + + /* + * I2S pre and post notification functions + */ + /*! I2S pre-notification function pointer */ + void *i2sPreFxn; + + /*! I2S post-notification function pointer */ + void *i2sPostFxn; + + /*! I2S pre-notification object */ + Power_NotifyObj i2sPreObj; + + /*! I2S post-notification object */ + Power_NotifyObj i2sPostObj; + + /*! I2S power constraint flag, guard to avoid power constraints getting out + * of sync + */ + volatile bool i2sPowerConstraint; + +} I2SCC26XX_Object; +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2s_I2SCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.c b/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.c new file mode 100644 index 00000000..2a25481d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/ioc.h) + +/* This enables the device specific hwAttrs to be case as the generic ones + * The hwAttrs will be generated by syscfg + */ +extern void *itmHwAttrs; + +/* + * ======== ITM_applyPinMux ======== + */ +bool ITM_applyPinMux(void) +{ + ITMCC26XX_HWAttrs *hwAttrs = (ITMCC26XX_HWAttrs *)itmHwAttrs; + + GPIO_setConfigAndMux(hwAttrs->swoPin, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_HIGH, IOC_PORT_MCU_SWV); + + return (bool)true; +} + +/* + * ======== ITM_clearPinMux ======== + */ +void ITM_clearPinMux(void) +{ + ITMCC26XX_HWAttrs *hwAttrs = (ITMCC26XX_HWAttrs *)itmHwAttrs; + GPIO_resetConfig(hwAttrs->swoPin); +} + +/* + * ======== ITMCC26XX_Flush ======== + */ +void ITMCC26XX_flush(void) +{ + ITMCC26XX_HWAttrs *hwAttrs = (ITMCC26XX_HWAttrs *)itmHwAttrs; + /* Release the SWO pin from the ITM */ + GPIO_setConfigAndMux(hwAttrs->swoPin, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_HIGH, GPIO_MUX_GPIO); +} + +/* + * ======== ITMCC26XX_restore ======== + */ +void ITMCC26XX_restore(void) +{ + ITMCC26XX_HWAttrs *hwAttrs = (ITMCC26XX_HWAttrs *)itmHwAttrs; + /* Return SWO pin to the ITM hardware*/ + GPIO_setConfigAndMux(hwAttrs->swoPin, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_HIGH, IOC_PORT_MCU_SWV); +} diff --git a/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.h b/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.h new file mode 100644 index 00000000..faf33831 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/ITMCC26XX.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file ITMCC26XX.h + * + * @brief CC26XX specific ITM implementation + * + * This file should only be included in the board file to fill out the object + * and hwAttrs structures + * + * # CC26XX specific members # + * The CC26XX is capable of treating the pins used by the SWO interface as + * GPIOs. This means that the pins must be managed by the ITM driver when not + * in use by the TPIU. + * + */ + +#ifndef ti_drivers_itm_ITMCC26XX__include +#define ti_drivers_itm_ITMCC26XX__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + ITM_BASE_HWATTRS + uint8_t swoPin; /*!< IOID number of SWO pin */ +} ITMCC26XX_HWAttrs; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_itm_ITMCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_dwt.h b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_dwt.h new file mode 100644 index 00000000..8cfaf47a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_dwt.h @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2018-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HW_CPU_DWT_H__ +#define __HW_CPU_DWT_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_DWT component +// +//***************************************************************************** +// Control +#define CPU_DWT_O_CTRL 0x00000000 + +// Current PC Sampler Cycle Count +#define CPU_DWT_O_CYCCNT 0x00000004 + +// CPI Count +#define CPU_DWT_O_CPICNT 0x00000008 + +// Exception Overhead Count +#define CPU_DWT_O_EXCCNT 0x0000000C + +// Sleep Count +#define CPU_DWT_O_SLEEPCNT 0x00000010 + +// LSU Count +#define CPU_DWT_O_LSUCNT 0x00000014 + +// Fold Count +#define CPU_DWT_O_FOLDCNT 0x00000018 + +// Program Counter Sample +#define CPU_DWT_O_PCSR 0x0000001C + +// Comparator 0 +#define CPU_DWT_O_COMP0 0x00000020 + +// Mask 0 +#define CPU_DWT_O_MASK0 0x00000024 + +// Function 0 +#define CPU_DWT_O_FUNCTION0 0x00000028 + +// Comparator 1 +#define CPU_DWT_O_COMP1 0x00000030 + +// Mask 1 +#define CPU_DWT_O_MASK1 0x00000034 + +// Function 1 +#define CPU_DWT_O_FUNCTION1 0x00000038 + +// Comparator 2 +#define CPU_DWT_O_COMP2 0x00000040 + +// Mask 2 +#define CPU_DWT_O_MASK2 0x00000044 + +// Function 2 +#define CPU_DWT_O_FUNCTION2 0x00000048 + +// Comparator 3 +#define CPU_DWT_O_COMP3 0x00000050 + +// Mask 3 +#define CPU_DWT_O_MASK3 0x00000054 + +// Function 3 +#define CPU_DWT_O_FUNCTION3 0x00000058 + +// Lock Access Register +#define CPU_DWT_O_LAR 0x00000FB0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CTRL +// +//***************************************************************************** + +// Field: [28] NUMCOMP +// +// Number of comparators implemented +#define CPU_DWT_CTRL_NUMCOMP 0xF0000000 +#define CPU_DWT_CTRL_NUMCOMP_BITN 28 +#define CPU_DWT_CTRL_NUMCOMP_M 0xF0000000 +#define CPU_DWT_CTRL_NUMCOMP_S 28 + +// Field: [25] NOCYCCNT +// +// When set, CYCCNT is not supported. +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 + +// Field: [24] NOPRFCNT +// +// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 + +// Field: [22] CYCEVTENA +// +// Enables Cycle count event. Emits an event when the POSTCNT counter triggers +// it. See CYCTAP and POSTPRESET for details. This event is only emitted if +// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. +// +// 0: Cycle count events disabled +// 1: Cycle count events enabled +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 + +// Field: [21] FOLDEVTENA +// +// Enables Folded instruction count event. Emits an event when FOLDCNT +// overflows (every 256 cycles of folded instructions). A folded instruction is +// one that does not incur even one cycle to execute. For example, an IT +// instruction is folded away and so does not use up one cycle. +// +// 0: Folded instruction count events disabled. +// 1: Folded instruction count events enabled. +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 + +// Field: [20] LSUEVTENA +// +// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 +// cycles of LSU operation). LSU counts include all LSU costs after the initial +// cycle for the instruction. +// +// 0: LSU count events disabled. +// 1: LSU count events enabled. +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 + +// Field: [19] SLEEPEVTENA +// +// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 +// cycles that the processor is sleeping). +// +// 0: Sleep count events disabled. +// 1: Sleep count events enabled. +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 + +// Field: [18] EXCEVTENA +// +// Enables Interrupt overhead event. Emits an event when EXCCNT overflows +// (every 256 cycles of interrupt overhead). +// +// 0x0: Interrupt overhead event disabled. +// 0x1: Interrupt overhead event enabled. +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 + +// Field: [17] CPIEVTENA +// +// Enables CPI count event. Emits an event when CPICNT overflows (every 256 +// cycles of multi-cycle instructions). +// +// 0: CPI counter events disabled. +// 1: CPI counter events enabled. +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 + +// Field: [16] EXCTRCENA +// +// Enables Interrupt event tracing. +// +// 0: Interrupt event trace disabled. +// 1: Interrupt event trace enabled. +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 + +// Field: [12] PCSAMPLEENA +// +// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT +// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this +// bit overrides CYCEVTENA. +// +// 0: PC Sampling event disabled. +// 1: Sampling event enabled. +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 + +// Field: [11:10] SYNCTAP +// +// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA +// must also be enabled for this feature. +// Synchronization packets (if enabled) are generated on tap transitions (0 to1 +// or 1 to 0). +// ENUMs: +// BIT28 Tap at bit 28 of CYCCNT +// BIT26 Tap at bit 26 of CYCCNT +// BIT24 Tap at bit 24 of CYCCNT +// DIS Disabled. No synchronization packets +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 + +// Field: [9] CYCTAP +// +// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the +// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the +// POSTCNT, post-scalar counter. That counter then counts down. On a bit change +// when post-scalar is 0, it triggers an event for PC sampling or cycle count +// event (see details in CYCEVTENA). +// ENUMs: +// BIT10 Selects bit [10] to tap +// BIT6 Selects bit [6] to tap +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 + +// Field: [8:5] POSTCNT +// +// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 +// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it +// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the +// value from POSTPRESET. +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 + +// Field: [4:1] POSTPRESET +// +// Reload value for post-scalar counter POSTCNT. When 0, events are triggered +// on each tap change (a power of 2). If this field has a non-0 value, it forms +// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For +// example, a value 1 in this register means an event is formed every other tap +// change. +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 + +// Field: [0] CYCCNTENA +// +// Enable CYCCNT, allowing it to increment and generate synchronization and +// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CYCCNT +// +//***************************************************************************** +// Field: [31:0] CYCCNT +// +// Current PC Sampler Cycle Counter count value. When enabled, this counter +// counts the number of core cycles, except when the core is halted. The cycle +// counter is a free running counter, counting upwards (this counter will not +// advance in power modes where free-running clock to CPU stops). It wraps +// around to 0 on overflow. The debugger must initialize this to 0 when first +// enabling. +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_CPICNT +// +//***************************************************************************** +// Field: [7:0] CPICNT +// +// Current CPI counter value. Increments on the additional cycles (the first +// cycle is not counted) required to execute all instructions except those +// recorded by LSUCNT. This counter also increments on all instruction fetch +// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter +// overflows. This counter initializes to 0 when it is enabled using +// CTRL.CPIEVTENA. +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_EXCCNT +// +//***************************************************************************** +// Field: [7:0] EXCCNT +// +// Current interrupt overhead counter value. Counts the total cycles spent in +// interrupt processing (for example entry stacking, return unstacking, +// pre-emption). An event is emitted on counter overflow (every 256 cycles). +// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_SLEEPCNT +// +//***************************************************************************** +// Field: [7:0] SLEEPCNT +// +// Sleep counter. Counts the number of cycles during which the processor is +// sleeping. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note +// that the sleep counter is clocked using CPU's free-running clock. In some +// power modes the free-running clock to CPU is gated to minimize power +// consumption. This means that the sleep counter will be invalid in these +// power modes. +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_LSUCNT +// +//***************************************************************************** +// Field: [7:0] LSUCNT +// +// LSU counter. This counts the total number of cycles that the processor is +// processing an LSU operation. The initial execution cost of the instruction +// is not counted. For example, an LDR that takes two cycles to complete +// increments this counter one cycle. Equivalently, an LDR that stalls for two +// cycles (i.e. takes four cycles to execute), increments this counter three +// times. An event is emitted on counter overflow (every 256 cycles). This +// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FOLDCNT +// +//***************************************************************************** +// Field: [7:0] FOLDCNT +// +// This counts the total number folded instructions. This counter initializes +// to 0 when it is enabled using CTRL.FOLDEVTENA. +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_PCSR +// +//***************************************************************************** +// Field: [31:0] EIASAMPLE +// +// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP0 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler +// Counter (CYCCNT). +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK0 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP0. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP0. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION0 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 + +// Field: [7] CYCMATCH +// +// This bit is only available in comparator 0. When set, COMP0 will compare +// against the cycle counter (CYCCNT). +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP1 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION1. +// Comparator 1 can also compare data values. So this register can contain +// reference values for data matching. +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK1 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP1. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP1. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION1 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 + +// Field: [19:16] DATAVADDR1 +// +// Identity of a second linked address comparator for data value matching when +// DATAVMATCH == 1 and LNK1ENA == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 + +// Field: [15:12] DATAVADDR0 +// +// Identity of a linked address comparator for data value matching when +// DATAVMATCH == 1. +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 + +// Field: [11:10] DATAVSIZE +// +// Defines the size of the data in the COMP1 register that is to be matched: +// +// 0x0: Byte +// 0x1: Halfword +// 0x2: Word +// 0x3: Unpredictable. +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 + +// Field: [9] LNK1ENA +// +// Read only bit-field only supported in comparator 1. +// +// 0: DATAVADDR1 not supported +// 1: DATAVADDR1 supported (enabled) +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 + +// Field: [8] DATAVMATCH +// +// Data match feature: +// +// 0: Perform address comparison +// 1: Perform data value compare. The comparators given by DATAVADDR0 and +// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting +// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and +// those comparators only provide the address match for the data comparison. +// +// This bit is only available in comparator 1. +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings: +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and +// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 +// and DATAVADDR1 can then only perform address comparator matches for +// comparator 1 data matches. +// Note 4: If the data matching functionality is not included during +// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or +// DATAVMATCH. This means that the data matching functionality is not available +// in the implementation. Test the availability of data matching by writing and +// reading DATAVMATCH. If it is not settable then data matching is unavailable. +// Note 5: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP2 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION2. +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK2 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP2. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP2. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION2 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_COMP3 +// +//***************************************************************************** +// Field: [31:0] COMP +// +// Reference value to compare against PC or the data address as given by +// FUNCTION3. +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_MASK3 +// +//***************************************************************************** +// Field: [3:0] MASK +// +// Mask on data address when matching against COMP3. This is the size of the +// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF +// left bit-shifted by MASK)) == COMP3. However, the actual comparison is +// slightly more complex to enable matching an address wherever it appears on a +// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be +// within the word. +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 + +//***************************************************************************** +// +// Register: CPU_DWT_O_FUNCTION3 +// +//***************************************************************************** +// Field: [24] MATCHED +// +// This bit is set when the comparator matches, and indicates that the +// operation defined by FUNCTION has occurred since this bit was last read. +// This bit is cleared on read. +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 + +// Field: [5] EMITRANGE +// +// Emit range field. This bit permits emitting offset when range match occurs. +// PC sampling is not supported when emit range is enabled. +// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 + +// Field: [3:0] FUNCTION +// +// Function settings. +// +// 0x0: Disabled +// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit +// address offset through ITM +// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, +// emit data and address offset through ITM on read or write. +// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. +// EMITRANGE = 1, emit address offset and data value through ITM on read or +// write. +// 0x4: Watchpoint on PC match. +// 0x5: Watchpoint on read. +// 0x6: Watchpoint on write. +// 0x7: Watchpoint on read or write. +// 0x8: ETM trigger on PC match +// 0x9: ETM trigger on read +// 0xA: ETM trigger on write +// 0xB: ETM trigger on read or write +// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for read transfers +// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample +// Daddr (lower 16 bits) for write transfers +// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for read transfers +// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, +// sample Daddr (lower 16 bits) + data for write transfers +// +// Note 1: If the ETM is not fitted, then ETM trigger is not possible. +// Note 2: Data value is only sampled for accesses that do not fault (MPU or +// bus fault). The PC is sampled irrespective of any faults. The PC is only +// sampled for the first address of a burst. +// Note 3: PC match is not recommended for watchpoints because it stops after +// the instruction. It mainly guards and triggers the ETM. +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 + +#endif // __CPU_DWT__ diff --git a/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_itm.h b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_itm.h new file mode 100644 index 00000000..026abbf0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_itm.h @@ -0,0 +1,1117 @@ +/* + * Copyright (c) 2018-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HW_CPU_ITM_H__ +#define __HW_CPU_ITM_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_ITM component +// +//***************************************************************************** +// Stimulus Port 0 +#define CPU_ITM_O_STIM0 0x00000000 + +// Stimulus Port 1 +#define CPU_ITM_O_STIM1 0x00000004 + +// Stimulus Port 2 +#define CPU_ITM_O_STIM2 0x00000008 + +// Stimulus Port 3 +#define CPU_ITM_O_STIM3 0x0000000C + +// Stimulus Port 4 +#define CPU_ITM_O_STIM4 0x00000010 + +// Stimulus Port 5 +#define CPU_ITM_O_STIM5 0x00000014 + +// Stimulus Port 6 +#define CPU_ITM_O_STIM6 0x00000018 + +// Stimulus Port 7 +#define CPU_ITM_O_STIM7 0x0000001C + +// Stimulus Port 8 +#define CPU_ITM_O_STIM8 0x00000020 + +// Stimulus Port 9 +#define CPU_ITM_O_STIM9 0x00000024 + +// Stimulus Port 10 +#define CPU_ITM_O_STIM10 0x00000028 + +// Stimulus Port 11 +#define CPU_ITM_O_STIM11 0x0000002C + +// Stimulus Port 12 +#define CPU_ITM_O_STIM12 0x00000030 + +// Stimulus Port 13 +#define CPU_ITM_O_STIM13 0x00000034 + +// Stimulus Port 14 +#define CPU_ITM_O_STIM14 0x00000038 + +// Stimulus Port 15 +#define CPU_ITM_O_STIM15 0x0000003C + +// Stimulus Port 16 +#define CPU_ITM_O_STIM16 0x00000040 + +// Stimulus Port 17 +#define CPU_ITM_O_STIM17 0x00000044 + +// Stimulus Port 18 +#define CPU_ITM_O_STIM18 0x00000048 + +// Stimulus Port 19 +#define CPU_ITM_O_STIM19 0x0000004C + +// Stimulus Port 20 +#define CPU_ITM_O_STIM20 0x00000050 + +// Stimulus Port 21 +#define CPU_ITM_O_STIM21 0x00000054 + +// Stimulus Port 22 +#define CPU_ITM_O_STIM22 0x00000058 + +// Stimulus Port 23 +#define CPU_ITM_O_STIM23 0x0000005C + +// Stimulus Port 24 +#define CPU_ITM_O_STIM24 0x00000060 + +// Stimulus Port 25 +#define CPU_ITM_O_STIM25 0x00000064 + +// Stimulus Port 26 +#define CPU_ITM_O_STIM26 0x00000068 + +// Stimulus Port 27 +#define CPU_ITM_O_STIM27 0x0000006C + +// Stimulus Port 28 +#define CPU_ITM_O_STIM28 0x00000070 + +// Stimulus Port 29 +#define CPU_ITM_O_STIM29 0x00000074 + +// Stimulus Port 30 +#define CPU_ITM_O_STIM30 0x00000078 + +// Stimulus Port 31 +#define CPU_ITM_O_STIM31 0x0000007C + +// Trace Enable +#define CPU_ITM_O_TER 0x00000E00 + +// Trace Privilege +#define CPU_ITM_O_TPR 0x00000E40 + +// Trace Control +#define CPU_ITM_O_TCR 0x00000E80 + +// Lock Access +#define CPU_ITM_O_LAR 0x00000FB0 + +// Lock Status +#define CPU_ITM_O_LSR 0x00000FB4 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM0 +// +//***************************************************************************** +// Field: [31:0] STIM0 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM1 +// +//***************************************************************************** +// Field: [31:0] STIM1 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM2 +// +//***************************************************************************** +// Field: [31:0] STIM2 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM3 +// +//***************************************************************************** +// Field: [31:0] STIM3 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM4 +// +//***************************************************************************** +// Field: [31:0] STIM4 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM5 +// +//***************************************************************************** +// Field: [31:0] STIM5 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM6 +// +//***************************************************************************** +// Field: [31:0] STIM6 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM7 +// +//***************************************************************************** +// Field: [31:0] STIM7 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM8 +// +//***************************************************************************** +// Field: [31:0] STIM8 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM9 +// +//***************************************************************************** +// Field: [31:0] STIM9 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM10 +// +//***************************************************************************** +// Field: [31:0] STIM10 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM11 +// +//***************************************************************************** +// Field: [31:0] STIM11 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM12 +// +//***************************************************************************** +// Field: [31:0] STIM12 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM13 +// +//***************************************************************************** +// Field: [31:0] STIM13 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM14 +// +//***************************************************************************** +// Field: [31:0] STIM14 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM15 +// +//***************************************************************************** +// Field: [31:0] STIM15 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM16 +// +//***************************************************************************** +// Field: [31:0] STIM16 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM17 +// +//***************************************************************************** +// Field: [31:0] STIM17 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM18 +// +//***************************************************************************** +// Field: [31:0] STIM18 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM19 +// +//***************************************************************************** +// Field: [31:0] STIM19 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM20 +// +//***************************************************************************** +// Field: [31:0] STIM20 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM21 +// +//***************************************************************************** +// Field: [31:0] STIM21 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM22 +// +//***************************************************************************** +// Field: [31:0] STIM22 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM23 +// +//***************************************************************************** +// Field: [31:0] STIM23 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM24 +// +//***************************************************************************** +// Field: [31:0] STIM24 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM25 +// +//***************************************************************************** +// Field: [31:0] STIM25 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM26 +// +//***************************************************************************** +// Field: [31:0] STIM26 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM27 +// +//***************************************************************************** +// Field: [31:0] STIM27 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM28 +// +//***************************************************************************** +// Field: [31:0] STIM28 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM29 +// +//***************************************************************************** +// Field: [31:0] STIM29 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM30 +// +//***************************************************************************** +// Field: [31:0] STIM30 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_STIM31 +// +//***************************************************************************** +// Field: [31:0] STIM31 +// +// A write to this location causes data to be written into the FIFO if +// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status +// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not +// provide an atomic read-modify-write, so it's users responsibility to ensure +// exclusive read-modify-write if this ITM port is used concurrently by +// interrupts or other threads. +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TER +// +//***************************************************************************** +// Field: [31] STIMENA31 +// +// Bit mask to enable tracing on ITM stimulus port 31. +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 + +// Field: [30] STIMENA30 +// +// Bit mask to enable tracing on ITM stimulus port 30. +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 + +// Field: [29] STIMENA29 +// +// Bit mask to enable tracing on ITM stimulus port 29. +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 + +// Field: [28] STIMENA28 +// +// Bit mask to enable tracing on ITM stimulus port 28. +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 + +// Field: [27] STIMENA27 +// +// Bit mask to enable tracing on ITM stimulus port 27. +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 + +// Field: [26] STIMENA26 +// +// Bit mask to enable tracing on ITM stimulus port 26. +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 + +// Field: [25] STIMENA25 +// +// Bit mask to enable tracing on ITM stimulus port 25. +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 + +// Field: [24] STIMENA24 +// +// Bit mask to enable tracing on ITM stimulus port 24. +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 + +// Field: [23] STIMENA23 +// +// Bit mask to enable tracing on ITM stimulus port 23. +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 + +// Field: [22] STIMENA22 +// +// Bit mask to enable tracing on ITM stimulus port 22. +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 + +// Field: [21] STIMENA21 +// +// Bit mask to enable tracing on ITM stimulus port 21. +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 + +// Field: [20] STIMENA20 +// +// Bit mask to enable tracing on ITM stimulus port 20. +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 + +// Field: [19] STIMENA19 +// +// Bit mask to enable tracing on ITM stimulus port 19. +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 + +// Field: [18] STIMENA18 +// +// Bit mask to enable tracing on ITM stimulus port 18. +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 + +// Field: [17] STIMENA17 +// +// Bit mask to enable tracing on ITM stimulus port 17. +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 + +// Field: [16] STIMENA16 +// +// Bit mask to enable tracing on ITM stimulus port 16. +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 + +// Field: [15] STIMENA15 +// +// Bit mask to enable tracing on ITM stimulus port 15. +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 + +// Field: [14] STIMENA14 +// +// Bit mask to enable tracing on ITM stimulus port 14. +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 + +// Field: [13] STIMENA13 +// +// Bit mask to enable tracing on ITM stimulus port 13. +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 + +// Field: [12] STIMENA12 +// +// Bit mask to enable tracing on ITM stimulus port 12. +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 + +// Field: [11] STIMENA11 +// +// Bit mask to enable tracing on ITM stimulus port 11. +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 + +// Field: [10] STIMENA10 +// +// Bit mask to enable tracing on ITM stimulus port 10. +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 + +// Field: [9] STIMENA9 +// +// Bit mask to enable tracing on ITM stimulus port 9. +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 + +// Field: [8] STIMENA8 +// +// Bit mask to enable tracing on ITM stimulus port 8. +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 + +// Field: [7] STIMENA7 +// +// Bit mask to enable tracing on ITM stimulus port 7. +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 + +// Field: [6] STIMENA6 +// +// Bit mask to enable tracing on ITM stimulus port 6. +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 + +// Field: [5] STIMENA5 +// +// Bit mask to enable tracing on ITM stimulus port 5. +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 + +// Field: [4] STIMENA4 +// +// Bit mask to enable tracing on ITM stimulus port 4. +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 + +// Field: [3] STIMENA3 +// +// Bit mask to enable tracing on ITM stimulus port 3. +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 + +// Field: [2] STIMENA2 +// +// Bit mask to enable tracing on ITM stimulus port 2. +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 + +// Field: [1] STIMENA1 +// +// Bit mask to enable tracing on ITM stimulus port 1. +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 + +// Field: [0] STIMENA0 +// +// Bit mask to enable tracing on ITM stimulus port 0. +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TPR +// +//***************************************************************************** +// Field: [3:0] PRIVMASK +// +// Bit mask to enable unprivileged (User) access to ITM stimulus ports: +// +// Bit [0] enables stimulus ports 0, 1, ..., and 7. +// Bit [1] enables stimulus ports 8, 9, ..., and 15. +// Bit [2] enables stimulus ports 16, 17, ..., and 23. +// Bit [3] enables stimulus ports 24, 25, ..., and 31. +// +// 0: User access allowed to stimulus ports +// 1: Privileged access only to stimulus ports +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_TCR +// +//***************************************************************************** +// Field: [23] BUSY +// +// Set when ITM events present and being drained. +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 + +// Field: [22:16] ATBID +// +// Trace Bus ID for CoreSight system. Optional identifier for multi-source +// trace stream formatting. If multi-source trace is in use, this field must be +// written with a non-zero value. +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 + +// Field: [9:8] TSPRESCALE +// +// Timestamp prescaler +// ENUMs: +// DIV64 Divide by 64 +// DIV16 Divide by 16 +// DIV4 Divide by 4 +// NOPRESCALING No prescaling +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 + +// Field: [4] SWOENA +// +// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If +// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of +// the timestamp counter. +// +// 0x0: Mode disabled. Timestamp counter uses system clock from the core and +// counts continuously. +// 0x1: Timestamp counter uses lineout (data related) clock from TPIU +// interface. The timestamp counter is held in reset while the output line is +// idle. +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 + +// Field: [3] DWTENA +// +// Enables the DWT stimulus (hardware event packet emission to the TPIU from +// the DWT) +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 + +// Field: [2] SYNCENA +// +// Enables synchronization packet transmission for a synchronous TPIU. +// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization +// speed. +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 + +// Field: [1] TSENA +// +// Enables differential timestamps. Differential timestamps are emitted when a +// packet is written to the FIFO with a non-zero timestamp counter, and when +// the timestamp counter overflows. Timestamps are emitted during idle times +// after a fixed number of two million cycles. This provides a time reference +// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps +// are triggered by activity on the internal trace bus only. In this case there +// is no regular timestamp output when the ITM is idle. +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 + +// Field: [0] ITMENA +// +// Enables ITM. This is the master enable, and must be set before ITM Stimulus +// and Trace Enable registers can be written. +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LAR +// +//***************************************************************************** +// Field: [31:0] LOCK_ACCESS +// +// A privileged write of 0xC5ACCE55 enables more write access to Control +// Registers TER, TPR and TCR. An invalid write removes write access. +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 + +//***************************************************************************** +// +// Register: CPU_ITM_O_LSR +// +//***************************************************************************** +// Field: [2] BYTEACC +// +// Reads 0 which means 8-bit lock access is not be implemented. +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 + +// Field: [1] ACCESS +// +// Write access to component is blocked. All writes are ignored, reads are +// permitted. +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 + +// Field: [0] PRESENT +// +// Indicates that a lock mechanism exists for this component. +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 + +#endif // __CPU_ITM__ diff --git a/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_scs.h b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_scs.h new file mode 100644 index 00000000..b4f893e6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_scs.h @@ -0,0 +1,4784 @@ +/* + * Copyright (c) 2018-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HW_CPU_SCS_H__ +#define __HW_CPU_SCS_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_SCS component +// +//***************************************************************************** +// Interrupt Control Type +#define CPU_SCS_O_ICTR 0x00000004 + +// Auxiliary Control +#define CPU_SCS_O_ACTLR 0x00000008 + +// SysTick Control and Status +#define CPU_SCS_O_STCSR 0x00000010 + +// SysTick Reload Value +#define CPU_SCS_O_STRVR 0x00000014 + +// SysTick Current Value +#define CPU_SCS_O_STCVR 0x00000018 + +// SysTick Calibration Value +#define CPU_SCS_O_STCR 0x0000001C + +// Irq 0 to 31 Set Enable +#define CPU_SCS_O_NVIC_ISER0 0x00000100 + +// Irq 32 to 63 Set Enable +#define CPU_SCS_O_NVIC_ISER1 0x00000104 + +// Irq 0 to 31 Clear Enable +#define CPU_SCS_O_NVIC_ICER0 0x00000180 + +// Irq 32 to 63 Clear Enable +#define CPU_SCS_O_NVIC_ICER1 0x00000184 + +// Irq 0 to 31 Set Pending +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 + +// Irq 32 to 63 Set Pending +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 + +// Irq 0 to 31 Clear Pending +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 + +// Irq 32 to 63 Clear Pending +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 + +// Irq 0 to 31 Active Bit +#define CPU_SCS_O_NVIC_IABR0 0x00000300 + +// Irq 32 to 63 Active Bit +#define CPU_SCS_O_NVIC_IABR1 0x00000304 + +// Irq 0 to 3 Priority +#define CPU_SCS_O_NVIC_IPR0 0x00000400 + +// Irq 4 to 7 Priority +#define CPU_SCS_O_NVIC_IPR1 0x00000404 + +// Irq 8 to 11 Priority +#define CPU_SCS_O_NVIC_IPR2 0x00000408 + +// Irq 12 to 15 Priority +#define CPU_SCS_O_NVIC_IPR3 0x0000040C + +// Irq 16 to 19 Priority +#define CPU_SCS_O_NVIC_IPR4 0x00000410 + +// Irq 20 to 23 Priority +#define CPU_SCS_O_NVIC_IPR5 0x00000414 + +// Irq 24 to 27 Priority +#define CPU_SCS_O_NVIC_IPR6 0x00000418 + +// Irq 28 to 31 Priority +#define CPU_SCS_O_NVIC_IPR7 0x0000041C + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR8 0x00000420 + +// Irq 32 to 35 Priority +#define CPU_SCS_O_NVIC_IPR9 0x00000424 + +// CPUID Base +#define CPU_SCS_O_CPUID 0x00000D00 + +// Interrupt Control State +#define CPU_SCS_O_ICSR 0x00000D04 + +// Vector Table Offset +#define CPU_SCS_O_VTOR 0x00000D08 + +// Application Interrupt/Reset Control +#define CPU_SCS_O_AIRCR 0x00000D0C + +// System Control +#define CPU_SCS_O_SCR 0x00000D10 + +// Configuration Control +#define CPU_SCS_O_CCR 0x00000D14 + +// System Handlers 4-7 Priority +#define CPU_SCS_O_SHPR1 0x00000D18 + +// System Handlers 8-11 Priority +#define CPU_SCS_O_SHPR2 0x00000D1C + +// System Handlers 12-15 Priority +#define CPU_SCS_O_SHPR3 0x00000D20 + +// System Handler Control and State +#define CPU_SCS_O_SHCSR 0x00000D24 + +// Configurable Fault Status +#define CPU_SCS_O_CFSR 0x00000D28 + +// Hard Fault Status +#define CPU_SCS_O_HFSR 0x00000D2C + +// Debug Fault Status +#define CPU_SCS_O_DFSR 0x00000D30 + +// Mem Manage Fault Address +#define CPU_SCS_O_MMFAR 0x00000D34 + +// Bus Fault Address +#define CPU_SCS_O_BFAR 0x00000D38 + +// Auxiliary Fault Status +#define CPU_SCS_O_AFSR 0x00000D3C + +// Processor Feature 0 +#define CPU_SCS_O_ID_PFR0 0x00000D40 + +// Processor Feature 1 +#define CPU_SCS_O_ID_PFR1 0x00000D44 + +// Debug Feature 0 +#define CPU_SCS_O_ID_DFR0 0x00000D48 + +// Auxiliary Feature 0 +#define CPU_SCS_O_ID_AFR0 0x00000D4C + +// Memory Model Feature 0 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 + +// Memory Model Feature 1 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 + +// Memory Model Feature 2 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 + +// Memory Model Feature 3 +#define CPU_SCS_O_ID_MMFR3 0x00000D5C + +// ISA Feature 0 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 + +// ISA Feature 1 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 + +// ISA Feature 2 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 + +// ISA Feature 3 +#define CPU_SCS_O_ID_ISAR3 0x00000D6C + +// ISA Feature 4 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 + +// Coprocessor Access Control +#define CPU_SCS_O_CPACR 0x00000D88 + +// MPU Type +#define CPU_SCS_O_MPU_TYPE 0x00000D90 + +// MPU Control +#define CPU_SCS_O_MPU_CTRL 0x00000D94 + +// MPU Region Number +#define CPU_SCS_O_MPU_RNR 0x00000D98 + +// MPU Region Base Address +#define CPU_SCS_O_MPU_RBAR 0x00000D9C + +// MPU Region Attribute and Size +#define CPU_SCS_O_MPU_RASR 0x00000DA0 + +// MPU Alias 1 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 + +// MPU Alias 1 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 + +// MPU Alias 2 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC + +// MPU Alias 2 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 + +// MPU Alias 3 Region Base Address +#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 + +// MPU Alias 3 Region Attribute and Size +#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 + +// Debug Halting Control and Status +#define CPU_SCS_O_DHCSR 0x00000DF0 + +// Deubg Core Register Selector +#define CPU_SCS_O_DCRSR 0x00000DF4 + +// Debug Core Register Data +#define CPU_SCS_O_DCRDR 0x00000DF8 + +// Debug Exception and Monitor Control +#define CPU_SCS_O_DEMCR 0x00000DFC + +// Software Trigger Interrupt +#define CPU_SCS_O_STIR 0x00000F00 + +// Floating Point Context Control +#define CPU_SCS_O_FPCCR 0x00000F34 + +// Floating-Point Context Address +#define CPU_SCS_O_FPCAR 0x00000F38 + +// Floating Point Default Status Control +#define CPU_SCS_O_FPDSCR 0x00000F3C + +// Media and FP Feature 0 +#define CPU_SCS_O_MVFR0 0x00000F40 + +// Media and FP Feature 1 +#define CPU_SCS_O_MVFR1 0x00000F44 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICTR +// +//***************************************************************************** +// Field: [2:0] INTLINESNUM +// +// Total number of interrupt lines in groups of 32. +// +// 0: 0...32 +// 1: 33...64 +// 2: 65...96 +// 3: 97...128 +// 4: 129...160 +// 5: 161...192 +// 6: 193...224 +// 7: 225...256 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ACTLR +// +//***************************************************************************** +// Field: [9] DISOOFP +// +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define CPU_SCS_ACTLR_DISOOFP 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_BITN 9 +#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_S 9 + +// Field: [8] DISFPCA +// +// Disable automatic update of CONTROL.FPCA +#define CPU_SCS_ACTLR_DISFPCA 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_BITN 8 +#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_S 8 + +// Field: [2] DISFOLD +// +// Disables folding of IT instruction. +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 + +// Field: [1] DISDEFWBUF +// +// Disables write buffer use during default memory map accesses. This causes +// all bus faults to be precise bus faults but decreases the performance of the +// processor because the stores to memory have to complete before the next +// instruction can be executed. +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 + +// Field: [0] DISMCYCINT +// +// Disables interruption of multi-cycle instructions. This increases the +// interrupt latency of the processor becuase LDM/STM completes before +// interrupt stacking occurs. +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCSR +// +//***************************************************************************** +// Field: [16] COUNTFLAG +// +// Returns 1 if timer counted to 0 since last time this was read. Clears on +// read by application of any part of the SysTick Control and Status Register. +// If read by the debugger using the DAP, this bit is cleared on read-only if +// the MasterType bit in the **AHB-AP** Control Register is set to 0. +// Otherwise, COUNTFLAG is not changed by the debugger read. +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 + +// Field: [2] CLKSOURCE +// +// Clock source: +// +// 0: External reference clock. +// 1: Core clock +// +// External clock is not available in this device. Writes to this field will be +// ignored. +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 + +// Field: [1] TICKINT +// +// 0: Counting down to zero does not pend the SysTick handler. Software can use +// COUNTFLAG to determine if the SysTick handler has ever counted to zero. +// 1: Counting down to zero pends the SysTick handler. +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 + +// Field: [0] ENABLE +// +// Enable SysTick counter +// +// 0: Counter disabled +// 1: Counter operates in a multi-shot way. That is, counter loads with the +// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it +// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on +// TICKINT. It then loads STRVR.RELOAD again, and begins counting. +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STRVR +// +//***************************************************************************** +// Field: [23:0] RELOAD +// +// Value to load into the SysTick Current Value Register STCVR.CURRENT when the +// counter reaches 0. +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCVR +// +//***************************************************************************** +// Field: [23:0] CURRENT +// +// Current value at the time the register is accessed. No read-modify-write +// protection is provided, so change with care. Writing to it with any value +// clears the register to 0. Clearing this register also clears +// STCSR.COUNTFLAG. +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STCR +// +//***************************************************************************** +// Field: [31] NOREF +// +// Reads as one. Indicates that no separate reference clock is provided. +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 + +// Field: [30] SKEW +// +// Reads as one. The calibration value is not exactly 10ms because of clock +// frequency. This could affect its suitability as a software real time clock. +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 + +// Field: [23:0] TENMS +// +// An optional Reload value to be used for 10ms (100Hz) timing, subject to +// system clock skew errors. The value read is valid only when core clock is at +// 48MHz. +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER0 +// +//***************************************************************************** +// Field: [31] SETENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 + +// Field: [30] SETENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 + +// Field: [29] SETENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 + +// Field: [28] SETENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 + +// Field: [27] SETENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 + +// Field: [26] SETENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 + +// Field: [25] SETENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 + +// Field: [24] SETENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 + +// Field: [23] SETENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 + +// Field: [22] SETENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 + +// Field: [21] SETENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 + +// Field: [20] SETENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 + +// Field: [19] SETENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 + +// Field: [18] SETENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 + +// Field: [17] SETENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 + +// Field: [16] SETENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 + +// Field: [15] SETENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 + +// Field: [14] SETENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 + +// Field: [13] SETENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 + +// Field: [12] SETENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 + +// Field: [11] SETENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 + +// Field: [10] SETENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 + +// Field: [9] SETENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 + +// Field: [8] SETENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 + +// Field: [7] SETENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 + +// Field: [6] SETENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 + +// Field: [5] SETENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 + +// Field: [4] SETENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 + +// Field: [3] SETENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 + +// Field: [2] SETENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 + +// Field: [1] SETENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 + +// Field: [0] SETENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISER1 +// +//***************************************************************************** +// Field: [5] SETENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 +#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 + +// Field: [4] SETENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 +#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 + +// Field: [3] SETENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 +#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 + +// Field: [2] SETENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 +#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 + +// Field: [1] SETENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 + +// Field: [0] SETENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit enables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER0 +// +//***************************************************************************** +// Field: [31] CLRENA31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 + +// Field: [30] CLRENA30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 + +// Field: [29] CLRENA29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 + +// Field: [28] CLRENA28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 + +// Field: [27] CLRENA27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 + +// Field: [26] CLRENA26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 + +// Field: [25] CLRENA25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 + +// Field: [24] CLRENA24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 + +// Field: [23] CLRENA23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 + +// Field: [22] CLRENA22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 + +// Field: [21] CLRENA21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 + +// Field: [20] CLRENA20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 + +// Field: [19] CLRENA19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 + +// Field: [18] CLRENA18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 + +// Field: [17] CLRENA17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 + +// Field: [16] CLRENA16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 + +// Field: [15] CLRENA15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 + +// Field: [14] CLRENA14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 + +// Field: [13] CLRENA13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 + +// Field: [12] CLRENA12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 + +// Field: [11] CLRENA11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 + +// Field: [10] CLRENA10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 + +// Field: [9] CLRENA9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 + +// Field: [8] CLRENA8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 + +// Field: [7] CLRENA7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 + +// Field: [6] CLRENA6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 + +// Field: [5] CLRENA5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 + +// Field: [4] CLRENA4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 + +// Field: [3] CLRENA3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 + +// Field: [2] CLRENA2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 + +// Field: [1] CLRENA1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 + +// Field: [0] CLRENA0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICER1 +// +//***************************************************************************** +// Field: [5] CLRENA37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 +#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 + +// Field: [4] CLRENA36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 +#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 + +// Field: [3] CLRENA35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 +#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 + +// Field: [2] CLRENA34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 +#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 + +// Field: [1] CLRENA33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 + +// Field: [0] CLRENA32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit disables the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current enable state. +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR0 +// +//***************************************************************************** +// Field: [31] SETPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 + +// Field: [30] SETPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 + +// Field: [29] SETPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 + +// Field: [28] SETPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 + +// Field: [27] SETPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 + +// Field: [26] SETPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 + +// Field: [25] SETPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 + +// Field: [24] SETPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 + +// Field: [23] SETPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 + +// Field: [22] SETPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 + +// Field: [21] SETPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 + +// Field: [20] SETPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 + +// Field: [19] SETPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 + +// Field: [18] SETPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 + +// Field: [17] SETPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 + +// Field: [16] SETPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 + +// Field: [15] SETPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 + +// Field: [14] SETPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 + +// Field: [13] SETPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 + +// Field: [12] SETPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 + +// Field: [11] SETPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 + +// Field: [10] SETPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 + +// Field: [9] SETPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 + +// Field: [8] SETPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 + +// Field: [7] SETPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 + +// Field: [6] SETPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 + +// Field: [5] SETPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 + +// Field: [4] SETPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 + +// Field: [3] SETPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 + +// Field: [2] SETPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 + +// Field: [1] SETPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 + +// Field: [0] SETPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ISPR1 +// +//***************************************************************************** +// Field: [5] SETPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 + +// Field: [4] SETPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 + +// Field: [3] SETPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 + +// Field: [2] SETPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 + +// Field: [1] SETPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 + +// Field: [0] SETPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit pends the +// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit +// returns its current state. +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR0 +// +//***************************************************************************** +// Field: [31] CLRPEND31 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 + +// Field: [30] CLRPEND30 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 + +// Field: [29] CLRPEND29 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 + +// Field: [28] CLRPEND28 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 + +// Field: [27] CLRPEND27 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 + +// Field: [26] CLRPEND26 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 + +// Field: [25] CLRPEND25 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 + +// Field: [24] CLRPEND24 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 + +// Field: [23] CLRPEND23 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 + +// Field: [22] CLRPEND22 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 + +// Field: [21] CLRPEND21 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 + +// Field: [20] CLRPEND20 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 + +// Field: [19] CLRPEND19 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 + +// Field: [18] CLRPEND18 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 + +// Field: [17] CLRPEND17 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 + +// Field: [16] CLRPEND16 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 + +// Field: [15] CLRPEND15 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 + +// Field: [14] CLRPEND14 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 + +// Field: [13] CLRPEND13 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 + +// Field: [12] CLRPEND12 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 + +// Field: [11] CLRPEND11 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 + +// Field: [10] CLRPEND10 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 + +// Field: [9] CLRPEND9 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 + +// Field: [8] CLRPEND8 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 + +// Field: [7] CLRPEND7 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 + +// Field: [6] CLRPEND6 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 + +// Field: [5] CLRPEND5 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 + +// Field: [4] CLRPEND4 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 + +// Field: [3] CLRPEND3 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 + +// Field: [2] CLRPEND2 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 + +// Field: [1] CLRPEND1 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 + +// Field: [0] CLRPEND0 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_ICPR1 +// +//***************************************************************************** +// Field: [5] CLRPEND37 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 + +// Field: [4] CLRPEND36 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 + +// Field: [3] CLRPEND35 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 + +// Field: [2] CLRPEND34 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 + +// Field: [1] CLRPEND33 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 + +// Field: [0] CLRPEND32 +// +// Writing 0 to this bit has no effect, writing 1 to this bit clears the +// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +// Reading the bit returns its current state. +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR0 +// +//***************************************************************************** +// Field: [31] ACTIVE31 +// +// Reading 0 from this bit implies that interrupt line 31 is not active. +// Reading 1 from this bit implies that the interrupt line 31 is active (See +// EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 + +// Field: [30] ACTIVE30 +// +// Reading 0 from this bit implies that interrupt line 30 is not active. +// Reading 1 from this bit implies that the interrupt line 30 is active (See +// EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 + +// Field: [29] ACTIVE29 +// +// Reading 0 from this bit implies that interrupt line 29 is not active. +// Reading 1 from this bit implies that the interrupt line 29 is active (See +// EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 + +// Field: [28] ACTIVE28 +// +// Reading 0 from this bit implies that interrupt line 28 is not active. +// Reading 1 from this bit implies that the interrupt line 28 is active (See +// EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 + +// Field: [27] ACTIVE27 +// +// Reading 0 from this bit implies that interrupt line 27 is not active. +// Reading 1 from this bit implies that the interrupt line 27 is active (See +// EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 + +// Field: [26] ACTIVE26 +// +// Reading 0 from this bit implies that interrupt line 26 is not active. +// Reading 1 from this bit implies that the interrupt line 26 is active (See +// EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 + +// Field: [25] ACTIVE25 +// +// Reading 0 from this bit implies that interrupt line 25 is not active. +// Reading 1 from this bit implies that the interrupt line 25 is active (See +// EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 + +// Field: [24] ACTIVE24 +// +// Reading 0 from this bit implies that interrupt line 24 is not active. +// Reading 1 from this bit implies that the interrupt line 24 is active (See +// EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 + +// Field: [23] ACTIVE23 +// +// Reading 0 from this bit implies that interrupt line 23 is not active. +// Reading 1 from this bit implies that the interrupt line 23 is active (See +// EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 + +// Field: [22] ACTIVE22 +// +// Reading 0 from this bit implies that interrupt line 22 is not active. +// Reading 1 from this bit implies that the interrupt line 22 is active (See +// EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 + +// Field: [21] ACTIVE21 +// +// Reading 0 from this bit implies that interrupt line 21 is not active. +// Reading 1 from this bit implies that the interrupt line 21 is active (See +// EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 + +// Field: [20] ACTIVE20 +// +// Reading 0 from this bit implies that interrupt line 20 is not active. +// Reading 1 from this bit implies that the interrupt line 20 is active (See +// EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 + +// Field: [19] ACTIVE19 +// +// Reading 0 from this bit implies that interrupt line 19 is not active. +// Reading 1 from this bit implies that the interrupt line 19 is active (See +// EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 + +// Field: [18] ACTIVE18 +// +// Reading 0 from this bit implies that interrupt line 18 is not active. +// Reading 1 from this bit implies that the interrupt line 18 is active (See +// EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 + +// Field: [17] ACTIVE17 +// +// Reading 0 from this bit implies that interrupt line 17 is not active. +// Reading 1 from this bit implies that the interrupt line 17 is active (See +// EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 + +// Field: [16] ACTIVE16 +// +// Reading 0 from this bit implies that interrupt line 16 is not active. +// Reading 1 from this bit implies that the interrupt line 16 is active (See +// EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 + +// Field: [15] ACTIVE15 +// +// Reading 0 from this bit implies that interrupt line 15 is not active. +// Reading 1 from this bit implies that the interrupt line 15 is active (See +// EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 + +// Field: [14] ACTIVE14 +// +// Reading 0 from this bit implies that interrupt line 14 is not active. +// Reading 1 from this bit implies that the interrupt line 14 is active (See +// EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 + +// Field: [13] ACTIVE13 +// +// Reading 0 from this bit implies that interrupt line 13 is not active. +// Reading 1 from this bit implies that the interrupt line 13 is active (See +// EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 + +// Field: [12] ACTIVE12 +// +// Reading 0 from this bit implies that interrupt line 12 is not active. +// Reading 1 from this bit implies that the interrupt line 12 is active (See +// EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 + +// Field: [11] ACTIVE11 +// +// Reading 0 from this bit implies that interrupt line 11 is not active. +// Reading 1 from this bit implies that the interrupt line 11 is active (See +// EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 + +// Field: [10] ACTIVE10 +// +// Reading 0 from this bit implies that interrupt line 10 is not active. +// Reading 1 from this bit implies that the interrupt line 10 is active (See +// EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 + +// Field: [9] ACTIVE9 +// +// Reading 0 from this bit implies that interrupt line 9 is not active. Reading +// 1 from this bit implies that the interrupt line 9 is active (See +// EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 + +// Field: [8] ACTIVE8 +// +// Reading 0 from this bit implies that interrupt line 8 is not active. Reading +// 1 from this bit implies that the interrupt line 8 is active (See +// EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 + +// Field: [7] ACTIVE7 +// +// Reading 0 from this bit implies that interrupt line 7 is not active. Reading +// 1 from this bit implies that the interrupt line 7 is active (See +// EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 + +// Field: [6] ACTIVE6 +// +// Reading 0 from this bit implies that interrupt line 6 is not active. Reading +// 1 from this bit implies that the interrupt line 6 is active (See +// EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 + +// Field: [5] ACTIVE5 +// +// Reading 0 from this bit implies that interrupt line 5 is not active. Reading +// 1 from this bit implies that the interrupt line 5 is active (See +// EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 + +// Field: [4] ACTIVE4 +// +// Reading 0 from this bit implies that interrupt line 4 is not active. Reading +// 1 from this bit implies that the interrupt line 4 is active (See +// EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 + +// Field: [3] ACTIVE3 +// +// Reading 0 from this bit implies that interrupt line 3 is not active. Reading +// 1 from this bit implies that the interrupt line 3 is active (See +// EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 + +// Field: [2] ACTIVE2 +// +// Reading 0 from this bit implies that interrupt line 2 is not active. Reading +// 1 from this bit implies that the interrupt line 2 is active (See +// EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 + +// Field: [1] ACTIVE1 +// +// Reading 0 from this bit implies that interrupt line 1 is not active. Reading +// 1 from this bit implies that the interrupt line 1 is active (See +// EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 + +// Field: [0] ACTIVE0 +// +// Reading 0 from this bit implies that interrupt line 0 is not active. Reading +// 1 from this bit implies that the interrupt line 0 is active (See +// EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IABR1 +// +//***************************************************************************** +// Field: [5] ACTIVE37 +// +// Reading 0 from this bit implies that interrupt line 37 is not active. +// Reading 1 from this bit implies that the interrupt line 37 is active (See +// EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 + +// Field: [4] ACTIVE36 +// +// Reading 0 from this bit implies that interrupt line 36 is not active. +// Reading 1 from this bit implies that the interrupt line 36 is active (See +// EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 + +// Field: [3] ACTIVE35 +// +// Reading 0 from this bit implies that interrupt line 35 is not active. +// Reading 1 from this bit implies that the interrupt line 35 is active (See +// EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 + +// Field: [2] ACTIVE34 +// +// Reading 0 from this bit implies that interrupt line 34 is not active. +// Reading 1 from this bit implies that the interrupt line 34 is active (See +// EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 + +// Field: [1] ACTIVE33 +// +// Reading 0 from this bit implies that interrupt line 33 is not active. +// Reading 1 from this bit implies that the interrupt line 33 is active (See +// EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 + +// Field: [0] ACTIVE32 +// +// Reading 0 from this bit implies that interrupt line 32 is not active. +// Reading 1 from this bit implies that the interrupt line 32 is active (See +// EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR0 +// +//***************************************************************************** +// Field: [31:24] PRI_3 +// +// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 + +// Field: [23:16] PRI_2 +// +// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 + +// Field: [15:8] PRI_1 +// +// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 + +// Field: [7:0] PRI_0 +// +// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR1 +// +//***************************************************************************** +// Field: [31:24] PRI_7 +// +// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 + +// Field: [23:16] PRI_6 +// +// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 + +// Field: [23:16] PRI_10 +// +// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 + +// Field: [15:8] PRI_9 +// +// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 + +// Field: [7:0] PRI_8 +// +// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 + +// Field: [15:8] PRI_13 +// +// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 + +// Field: [7:0] PRI_12 +// +// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR4 +// +//***************************************************************************** +// Field: [31:24] PRI_19 +// +// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 + +// Field: [23:16] PRI_18 +// +// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 + +// Field: [15:8] PRI_17 +// +// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 + +// Field: [7:0] PRI_16 +// +// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR5 +// +//***************************************************************************** +// Field: [31:24] PRI_23 +// +// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 + +// Field: [23:16] PRI_22 +// +// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 + +// Field: [15:8] PRI_21 +// +// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 + +// Field: [7:0] PRI_20 +// +// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR6 +// +//***************************************************************************** +// Field: [31:24] PRI_27 +// +// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 + +// Field: [23:16] PRI_26 +// +// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 + +// Field: [15:8] PRI_25 +// +// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 + +// Field: [7:0] PRI_24 +// +// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR7 +// +//***************************************************************************** +// Field: [31:24] PRI_31 +// +// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 + +// Field: [23:16] PRI_30 +// +// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 + +// Field: [15:8] PRI_29 +// +// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 + +// Field: [7:0] PRI_28 +// +// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR8 +// +//***************************************************************************** +// Field: [31:24] PRI_35 +// +// Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 +#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 + +// Field: [23:16] PRI_34 +// +// Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 + +// Field: [15:8] PRI_33 +// +// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 + +// Field: [7:0] PRI_32 +// +// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_NVIC_IPR9 +// +//***************************************************************************** +// Field: [15:8] PRI_37 +// +// Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 + +// Field: [7:0] PRI_36 +// +// Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). +#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF +#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CPUID +// +//***************************************************************************** +// Field: [31:24] IMPLEMENTER +// +// Implementor code. +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 + +// Field: [23:20] VARIANT +// +// Implementation defined variant number. +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 + +// Field: [19:16] CONSTANT +// +// Reads as 0xF +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 + +// Field: [15:4] PARTNO +// +// Number of processor within family. +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 + +// Field: [3:0] REVISION +// +// Implementation defined revision number. +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ICSR +// +//***************************************************************************** +// Field: [31] NMIPENDSET +// +// Set pending NMI bit. Setting this bit pends and activates an NMI. Because +// NMI is the highest-priority interrupt, it takes effect as soon as it +// registers. +// +// 0: No action +// 1: Set pending NMI +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 + +// Field: [28] PENDSVSET +// +// Set pending pendSV bit. +// +// 0: No action +// 1: Set pending PendSV +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 + +// Field: [27] PENDSVCLR +// +// Clear pending pendSV bit +// +// 0: No action +// 1: Clear pending pendSV +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 + +// Field: [26] PENDSTSET +// +// Set a pending SysTick bit. +// +// 0: No action +// 1: Set pending SysTick +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 + +// Field: [25] PENDSTCLR +// +// Clear pending SysTick bit +// +// 0: No action +// 1: Clear pending SysTick +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 + +// Field: [23] ISRPREEMPT +// +// This field can only be used at debug time. It indicates that a pending +// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, +// the interrupt is serviced. +// +// 0: A pending exception is not serviced. +// 1: A pending exception is serviced on exit from the debug halt state +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 + +// Field: [22] ISRPENDING +// +// Interrupt pending flag. Excludes NMI and faults. +// +// 0x0: Interrupt not pending +// 0x1: Interrupt pending +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 + +// Field: [17:12] VECTPENDING +// +// Pending ISR number field. This field contains the interrupt number of the +// highest priority pending ISR. +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 + +// Field: [11] RETTOBASE +// +// Indicates whether there are preempted active exceptions: +// +// 0: There are preempted active exceptions to execute +// 1: There are no active exceptions, or the currently-executing exception is +// the only active exception. +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 + +// Field: [8:0] VECTACTIVE +// +// Active ISR number field. Reset clears this field. +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_VTOR +// +//***************************************************************************** +// Field: [29:7] TBLOFF +// +// Bits 29 down to 7 of the vector table base offset. +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AIRCR +// +//***************************************************************************** +// Field: [31:16] VECTKEY +// +// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. +// Otherwise the write value is ignored. Read always returns 0xFA05. +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 + +// Field: [15] ENDIANESS +// +// Data endianness bit +// ENUMs: +// BIG Big endian +// LITTLE Little endian +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 + +// Field: [10:8] PRIGROUP +// +// Interrupt priority grouping field. This field is a binary point position +// indicator for creating subpriorities for exceptions that share the same +// pre-emption level. It divides the PRI_n field in the Interrupt Priority +// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption +// level and a subpriority level. The binary point is a left-of value. This +// means that the PRIGROUP value represents a point starting at the left of the +// Least Significant Bit (LSB). The lowest value might not be 0 depending on +// the number of bits allocated for priorities, and implementation choices. +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 + +// Field: [2] SYSRESETREQ +// +// Requests a warm reset. Setting this bit does not prevent Halting Debug from +// running. +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 + +// Field: [1] VECTCLRACTIVE +// +// Clears all active state information for active NMI, fault, and interrupts. +// It is the responsibility of the application to reinitialize the stack. This +// bit is for returning to a known state during debug. The bit self-clears. +// IPSR is not cleared by this operation. So, if used by an application, it +// must only be used at the base level of activation, or within a system +// handler whose active bit can be set. +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 + +// Field: [0] VECTRESET +// +// System Reset bit. Resets the system, with the exception of debug components. +// This bit is reserved for debug use and can be written to 1 only when the +// core is halted. The bit self-clears. Writing this bit to 1 while core is not +// halted may result in unpredictable behavior. +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SCR +// +//***************************************************************************** +// Field: [4] SEVONPEND +// +// Send Event on Pending bit: +// +// 0: Only enabled interrupts or events can wakeup the processor, disabled +// interrupts are excluded +// 1: Enabled events and all interrupts, including disabled interrupts, can +// wakeup the processor. +// +// When an event or interrupt enters pending state, the event signal wakes up +// the processor from WFE. If +// the processor is not waiting for an event, the event is registered and +// affects the next WFE. +// The processor also wakes up on execution of an SEV instruction. +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 + +// Field: [2] SLEEPDEEP +// +// Controls whether the processor uses sleep or deep sleep as its low power +// mode +// ENUMs: +// DEEPSLEEP Deep sleep +// SLEEP Sleep +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 + +// Field: [1] SLEEPONEXIT +// +// Sleep on exit when returning from Handler mode to Thread mode. Enables +// interrupt driven applications to avoid returning to empty main application. +// +// 0: Do not sleep when returning to thread mode +// 1: Sleep on ISR exit +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CCR +// +//***************************************************************************** +// Field: [9] STKALIGN +// +// Stack alignment bit. +// +// 0: Only 4-byte alignment is guaranteed for the SP used prior to the +// exception on exception entry. +// 1: On exception entry, the SP used prior to the exception is adjusted to be +// 8-byte aligned and the context to restore it is saved. The SP is restored on +// the associated exception return. +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 + +// Field: [8] BFHFNMIGN +// +// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by +// load and store instructions. This applies to the HardFault, NMI, and +// FAULTMASK escalated handlers: +// +// 0: Data BusFaults caused by load and store instructions cause a lock-up +// 1: Data BusFaults caused by load and store instructions are ignored. +// +// Set this bit to 1 only when the handler and its data are in absolutely safe +// memory. The normal use +// of this bit is to probe system devices and bridges to detect problems. +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 + +// Field: [4] DIV_0_TRP +// +// Enables faulting or halting when the processor executes an SDIV or UDIV +// instruction with a divisor of 0: +// +// 0: Do not trap divide by 0. In this mode, a divide by zero returns a +// quotient of 0. +// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is +// CFSR.DIVBYZERO. +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 + +// Field: [3] UNALIGN_TRP +// +// Enables unaligned access traps: +// +// 0: Do not trap unaligned halfword and word accesses +// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault +// Status Register bit is CFSR.UNALIGNED. +// +// If this bit is set to 1, an unaligned access generates a UsageFault. +// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of +// the value in UNALIGN_TRP. +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 + +// Field: [1] USERSETMPEND +// +// Enables unprivileged software access to STIR: +// +// 0: User code is not allowed to write to the Software Trigger Interrupt +// register (STIR). +// 1: User code can write the Software Trigger Interrupt register (STIR) to +// trigger (pend) a Main exception, which is associated with the Main stack +// pointer. +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 + +// Field: [0] NONBASETHREDENA +// +// Indicates how the processor enters Thread mode: +// +// 0: Processor can enter Thread mode only when no exception is active. +// 1: Processor can enter Thread mode from any level using the appropriate +// return value (EXC_RETURN). +// +// Exception returns occur when one of the following instructions loads a value +// of 0xFXXXXXXX into the PC while in Handler mode: +// - POP/LDM which includes loading the PC. +// - LDR with PC as a destination. +// - BX with any register. +// The value written to the PC is intercepted and is referred to as the +// EXC_RETURN value. +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR1 +// +//***************************************************************************** +// Field: [23:16] PRI_6 +// +// Priority of system handler 6. UsageFault +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 + +// Field: [15:8] PRI_5 +// +// Priority of system handler 5: BusFault +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 + +// Field: [7:0] PRI_4 +// +// Priority of system handler 4: MemManage +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR2 +// +//***************************************************************************** +// Field: [31:24] PRI_11 +// +// Priority of system handler 11. SVCall +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHPR3 +// +//***************************************************************************** +// Field: [31:24] PRI_15 +// +// Priority of system handler 15. SysTick exception +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 + +// Field: [23:16] PRI_14 +// +// Priority of system handler 14. Pend SV +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 + +// Field: [7:0] PRI_12 +// +// Priority of system handler 12. Debug Monitor +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_SHCSR +// +//***************************************************************************** +// Field: [18] USGFAULTENA +// +// Usage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 + +// Field: [17] BUSFAULTENA +// +// Bus fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 + +// Field: [16] MEMFAULTENA +// +// MemManage fault system handler enable +// ENUMs: +// EN Exception enabled +// DIS Exception disabled +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 + +// Field: [15] SVCALLPENDED +// +// SVCall pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 + +// Field: [14] BUSFAULTPENDED +// +// BusFault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [13] MEMFAULTPENDED +// +// MemManage exception pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [12] USGFAULTPENDED +// +// Usage fault pending +// ENUMs: +// PENDING Exception is pending. +// NOTPENDING Exception is not active +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 + +// Field: [11] SYSTICKACT +// +// SysTick active flag. +// +// 0x0: Not active +// 0x1: Active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 + +// Field: [10] PENDSVACT +// +// PendSV active +// +// 0x0: Not active +// 0x1: Active +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 + +// Field: [8] MONITORACT +// +// Debug monitor active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 + +// Field: [7] SVCALLACT +// +// SVCall active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 + +// Field: [3] USGFAULTACT +// +// UsageFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 + +// Field: [1] BUSFAULTACT +// +// BusFault exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 + +// Field: [0] MEMFAULTACT +// +// MemManage exception active +// ENUMs: +// ACTIVE Exception is active +// NOTACTIVE Exception is not active +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 + +//***************************************************************************** +// +// Register: CPU_SCS_O_CFSR +// +//***************************************************************************** +// Field: [25] DIVBYZERO +// +// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is +// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this +// fault occurs The instruction is executed and the return PC points to it. If +// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 + +// Field: [24] UNALIGNED +// +// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an +// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD +// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 + +// Field: [19] NOCP +// +// Attempt to use a coprocessor instruction. The processor does not support +// coprocessor instructions. +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 + +// Field: [18] INVPC +// +// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid +// context, invalid value. The return PC points to the instruction that tried +// to set the PC. +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 + +// Field: [17] INVSTATE +// +// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX +// type instruction has changed state). This includes state change after entry +// to or return from exception, as well as from inter-working instructions. +// Return PC points to faulting instruction, with the invalid state. +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 + +// Field: [16] UNDEFINSTR +// +// This bit is set when the processor attempts to execute an undefined +// instruction. This is an instruction that the processor cannot decode. The +// return PC points to the undefined instruction. +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 + +// Field: [15] BFARVALID +// +// This bit is set if the Bus Fault Address Register (BFAR) contains a valid +// address. This is true after a bus fault where the address is known. Other +// faults can clear this bit, such as a Mem Manage fault occurring later. If a +// Bus fault occurs that is escalated to a Hard Fault because of priority, the +// Hard Fault handler must clear this bit. This prevents problems if returning +// to a stacked active Bus fault handler whose BFAR value has been overwritten. +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 + +// Field: [12] STKERR +// +// Stacking from exception has caused one or more bus faults. The SP is still +// adjusted and the values in the context area on the stack might be incorrect. +// BFAR is not written. +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 + +// Field: [11] UNSTKERR +// +// Unstack from exception return has caused one or more bus faults. This is +// chained to the handler, so that the original return stack is still present. +// SP is not adjusted from failing return and new save is not performed. BFAR +// is not written. +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 + +// Field: [10] IMPRECISERR +// +// Imprecise data bus error. It is a BusFault, but the Return PC is not related +// to the causing instruction. This is not a synchronous fault. So, if detected +// when the priority of the current activation is higher than the Bus Fault, it +// only pends. Bus fault activates when returning to a lower priority +// activation. If a precise fault occurs before returning to a lower priority +// exception, the handler detects both IMPRECISERR set and one of the precise +// fault status bits set at the same time. BFAR is not written. +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 + +// Field: [9] PRECISERR +// +// Precise data bus error return. +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 + +// Field: [8] IBUSERR +// +// Instruction bus error flag. This flag is set by a prefetch error. The fault +// stops on the instruction, so if the error occurs under a branch shadow, no +// fault occurs. BFAR is not written. +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 + +// Field: [7] MMARVALID +// +// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving +// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage +// fault occurs that is escalated to a Hard Fault because of priority, the Hard +// Fault handler must clear this bit. This prevents problems on return to a +// stacked active MemManage handler whose MMFAR value has been overwritten. +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 + +// Field: [4] MSTKERR +// +// Stacking from exception has caused one or more access violations. The SP is +// still adjusted and the values in the context area on the stack might be +// incorrect. MMFAR is not written. +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 + +// Field: [3] MUNSTKERR +// +// Unstack from exception return has caused one or more access violations. This +// is chained to the handler, so that the original return stack is still +// present. SP is not adjusted from failing return and new save is not +// performed. MMFAR is not written. +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 + +// Field: [1] DACCVIOL +// +// Data access violation flag. Attempting to load or store at a location that +// does not permit the operation sets this flag. The return PC points to the +// faulting instruction. This error loads MMFAR with the address of the +// attempted access. +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 + +// Field: [0] IACCVIOL +// +// Instruction access violation flag. Attempting to fetch an instruction from a +// location that does not permit execution sets this flag. This occurs on any +// access to an XN region, even when the MPU is disabled or not present. The +// return PC points to the faulting instruction. MMFAR is not written. +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_HFSR +// +//***************************************************************************** +// Field: [31] DEBUGEVT +// +// This bit is set if there is a fault related to debug. This is only possible +// when halting debug is not enabled. For monitor enabled debug, it only +// happens for BKPT when the current priority is higher than the monitor. When +// both halting and monitor debug are disabled, it only happens for debug +// events that are not ignored (minimally, BKPT). The Debug Fault Status +// Register is updated. +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 + +// Field: [30] FORCED +// +// Hard Fault activated because a Configurable Fault was received and cannot +// activate because of priority or because the Configurable Fault is disabled. +// The Hard Fault handler then has to read the other fault status registers to +// determine cause. +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 + +// Field: [1] VECTTBL +// +// This bit is set if there is a fault because of vector table read on +// exception processing (Bus Fault). This case is always a Hard Fault. The +// return PC points to the pre-empted instruction. +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DFSR +// +//***************************************************************************** +// Field: [4] EXTERNAL +// +// External debug request flag. The processor stops on next instruction +// boundary. +// +// 0x0: External debug request signal not asserted +// 0x1: External debug request signal asserted +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 + +// Field: [3] VCATCH +// +// Vector catch flag. When this flag is set, a flag in one of the local fault +// status registers is also set to indicate the type of fault. +// +// 0x0: No vector catch occurred +// 0x1: Vector catch occurred +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 + +// Field: [2] DWTTRAP +// +// Data Watchpoint and Trace (DWT) flag. The processor stops at the current +// instruction or at the next instruction. +// +// 0x0: No DWT match +// 0x1: DWT match +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 + +// Field: [1] BKPT +// +// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, +// and also by normal code. Return PC points to breakpoint containing +// instruction. +// +// 0x0: No BKPT instruction execution +// 0x1: BKPT instruction execution +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 + +// Field: [0] HALTED +// +// Halt request flag. The processor is halted on the next instruction. +// +// 0x0: No halt request +// 0x1: Halt requested by NVIC, including step +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MMFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Mem Manage fault address field. +// This field is the data address of a faulted load or store attempt. When an +// unaligned access faults, the address is the actual address that faulted. +// Because an access can be split into multiple parts, each aligned, this +// address can be any offset in the range of the requested size. Flags +// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination +// with CFSR.MMARVALIDindicate the cause of the fault. +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_BFAR +// +//***************************************************************************** +// Field: [31:0] ADDRESS +// +// Bus fault address field. This field is the data address of a faulted load or +// store attempt. When an unaligned access faults, the address is the address +// requested by the instruction, even if that is not the address that faulted. +// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and +// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the +// fault. +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_AFSR +// +//***************************************************************************** +// Field: [31:0] IMPDEF +// +// Implementation defined. The bits map directly onto the signal assignment to +// the auxiliary fault inputs. Tied to 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR0 +// +//***************************************************************************** +// Field: [7:4] STATE1 +// +// State1 (T-bit == 1) +// +// 0x0: N/A +// 0x1: N/A +// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit +// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit +// instructions can be added using the appropriate instruction attribute, but +// other 32-bit basic instructions cannot.) +// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 + +// Field: [3:0] STATE0 +// +// State0 (T-bit == 0) +// +// 0x0: No ARM encoding +// 0x1: N/A +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_PFR1 +// +//***************************************************************************** +// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL +// +// Microcontroller programmer's model +// +// 0x0: Not supported +// 0x2: Two-stack support +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_DFR0 +// +//***************************************************************************** +// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL +// +// Microcontroller Debug Model - memory mapped +// +// 0x0: Not supported +// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_AFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR2 +// +//***************************************************************************** +// Field: [24] WAIT_FOR_INTERRUPT_STALLING +// +// wait for interrupt stalling +// +// 0x0: Not supported +// 0x1: Wait for interrupt supported +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 + +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_MMFR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR0 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR1 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR2 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR3 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_ID_ISAR4 +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_CPACR +// +//***************************************************************************** +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_TYPE +// +//***************************************************************************** +// Field: [23:16] IREGION +// +// The processor core uses only a unified MPU, this field always reads 0x0. +#define CPU_SCS_MPU_TYPE_IREGION_W 8 +#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 +#define CPU_SCS_MPU_TYPE_IREGION_S 16 + +// Field: [15:8] DREGION +// +// Number of supported MPU regions field. This field reads 0x08 indicating +// eight MPU regions. +#define CPU_SCS_MPU_TYPE_DREGION_W 8 +#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 +#define CPU_SCS_MPU_TYPE_DREGION_S 8 + +// Field: [0] SEPARATE +// +// The processor core uses only a unified MPU, thus this field is always 0. +#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 +#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_CTRL +// +//***************************************************************************** +// Field: [2] PRIVDEFENA +// +// This bit enables the default memory map for privileged access, as a +// background region, when the MPU is enabled. The background region acts as if +// it was region number 1 before any settable regions. Any region that is set +// up overlays this default map, and overrides it. If this bit is not set, the +// default memory map is disabled, and memory not covered by a region faults. +// This applies to memory type, Execute Never (XN), cache and shareable rules. +// However, this only applies to privileged mode (fetch and data access). User +// mode code faults unless a region has been set up for its code and data. When +// the MPU is disabled, the default map acts on both privileged and user mode +// code. XN and SO rules always apply to the system partition whether this +// enable is set or not. If the MPU is disabled, this bit is ignored. +#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 + +// Field: [1] HFNMIENA +// +// This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated +// handlers. If this bit and ENABLE are set, the MPU is enabled when in these +// handlers. If this bit is not set, the MPU is disabled when in these +// handlers, regardless of the value of ENABLE bit. If this bit is set and +// ENABLE is not set, behavior is unpredictable. +#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 +#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 + +// Field: [0] ENABLE +// +// Enable MPU +// +// 0: MPU disabled +// 1: MPU enabled +#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 +#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RNR +// +//***************************************************************************** +// Field: [7:0] REGION +// +// Region select field. +// This field selects the region to operate on when using the MPU_RASR and +// MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID +// and MPU_RBAR.REGION fields are written, which overwrites this. +#define CPU_SCS_MPU_RNR_REGION_W 8 +#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF +#define CPU_SCS_MPU_RNR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR +// +//***************************************************************************** +// Field: [31:5] ADDR +// +// Region base address field. +// The position of the LSB depends on the region size, so that the base address +// is aligned according to an even multiple of size. The power of 2 size +// specified by the SZENABLE field of the MPU Region Attribute and Size +// Register defines how many bits of base address are used. +#define CPU_SCS_MPU_RBAR_ADDR_W 27 +#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 +#define CPU_SCS_MPU_RBAR_ADDR_S 5 + +// Field: [4] VALID +// +// MPU region number valid: +// 0: MPU_RNR remains unchanged and is interpreted. +// 1: MPU_RNR is overwritten by REGION. +#define CPU_SCS_MPU_RBAR_VALID 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_BITN 4 +#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_S 4 + +// Field: [3:0] REGION +// +// MPU region override field +#define CPU_SCS_MPU_RBAR_REGION_W 4 +#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F +#define CPU_SCS_MPU_RBAR_REGION_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR +// +//***************************************************************************** +// Field: [28] XN +// +// Instruction access disable: +// 0: Enable instruction fetches +// 1: Disable instruction fetches +#define CPU_SCS_MPU_RASR_XN 0x10000000 +#define CPU_SCS_MPU_RASR_XN_BITN 28 +#define CPU_SCS_MPU_RASR_XN_M 0x10000000 +#define CPU_SCS_MPU_RASR_XN_S 28 + +// Field: [26:24] AP +// +// Data access permission: +// 0x0: Priviliged permissions: No access. User permissions: No access. +// 0x1: Priviliged permissions: Read-write. User permissions: No access. +// 0x2: Priviliged permissions: Read-write. User permissions: Read-only. +// 0x3: Priviliged permissions: Read-write. User permissions: Read-write. +// 0x4: Reserved +// 0x5: Priviliged permissions: Read-only. User permissions: No access. +// 0x6: Priviliged permissions: Read-only. User permissions: Read-only. +// 0x7: Priviliged permissions: Read-only. User permissions: Read-only. +#define CPU_SCS_MPU_RASR_AP_W 3 +#define CPU_SCS_MPU_RASR_AP_M 0x07000000 +#define CPU_SCS_MPU_RASR_AP_S 24 + +// Field: [21:19] TEX +// +// Type extension +#define CPU_SCS_MPU_RASR_TEX_W 3 +#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 +#define CPU_SCS_MPU_RASR_TEX_S 19 + +// Field: [18] S +// +// Shareable bit: +// 0: Not shareable +// 1: Shareable +#define CPU_SCS_MPU_RASR_S 0x00040000 +#define CPU_SCS_MPU_RASR_S_BITN 18 +#define CPU_SCS_MPU_RASR_S_M 0x00040000 +#define CPU_SCS_MPU_RASR_S_S 18 + +// Field: [17] C +// +// Cacheable bit: +// 0: Not cacheable +// 1: Cacheable +#define CPU_SCS_MPU_RASR_C 0x00020000 +#define CPU_SCS_MPU_RASR_C_BITN 17 +#define CPU_SCS_MPU_RASR_C_M 0x00020000 +#define CPU_SCS_MPU_RASR_C_S 17 + +// Field: [16] B +// +// Bufferable bit: +// 0: Not bufferable +// 1: Bufferable +#define CPU_SCS_MPU_RASR_B 0x00010000 +#define CPU_SCS_MPU_RASR_B_BITN 16 +#define CPU_SCS_MPU_RASR_B_M 0x00010000 +#define CPU_SCS_MPU_RASR_B_S 16 + +// Field: [15:8] SRD +// +// Sub-Region Disable field: +// Setting a bit in this field disables the corresponding sub-region. Regions +// are split into eight equal-sized sub-regions. Sub-regions are not supported +// for region sizes of 128 bytes and less. +#define CPU_SCS_MPU_RASR_SRD_W 8 +#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 +#define CPU_SCS_MPU_RASR_SRD_S 8 + +// Field: [5:1] SIZE +// +// MPU Protection Region Size Field: +// 0x04: 32B +// 0x05: 64B +// 0x06: 128B +// 0x07: 256B +// 0x08: 512B +// 0x09: 1KB +// 0x0A: 2KB +// 0x0B: 4KB +// 0x0C: 8KB +// 0x0D: 16KB +// 0x0E: 32KB +// 0x0F: 64KB +// 0x10: 128KB +// 0x11: 256KB +// 0x12: 512KB +// 0x13: 1MB +// 0x14: 2MB +// 0x15: 4MB +// 0x16: 8MB +// 0x17: 16MB +// 0x18: 32MB +// 0x19: 64MB +// 0x1A: 128MB +// 0x1B: 256MB +// 0x1C: 512MB +// 0x1D: 1GB +// 0x1E: 2GB +// 0x1F: 4GB +#define CPU_SCS_MPU_RASR_SIZE_W 5 +#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E +#define CPU_SCS_MPU_RASR_SIZE_S 1 + +// Field: [0] ENABLE +// +// Region enable bit: +// 0: Disable region +// 1: Enable region +#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 +#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A1 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A1 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A1 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A2 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A2 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A2 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RBAR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RBAR_A3 +// +// Alias for MPU_RBAR +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MPU_RASR_A3 +// +//***************************************************************************** +// Field: [31:0] MPU_RASR_A3 +// +// Alias for MPU_RASR +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DHCSR +// +//***************************************************************************** +// Field: [25] S_RESET_ST +// +// Indicates that the core has been reset, or is now being reset, since the +// last time this bit was read. This a sticky bit that clears on read. So, +// reading twice and getting 1 then 0 means it was reset in the past. Reading +// twice and getting 1 both times means that it is being reset now (held in +// reset still). +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 + +// Field: [24] S_RETIRE_ST +// +// Indicates that an instruction has completed since last read. This is a +// sticky bit that clears on read. This determines if the core is stalled on a +// load/store or fetch. +// When writing to this register, 0 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 + +// Field: [19] S_LOCKUP +// +// Reads as one if the core is running (not halted) and a lockup condition is +// present. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 + +// Field: [18] S_SLEEP +// +// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must +// use C_HALT to gain control or wait for interrupt to wake-up. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 + +// Field: [17] S_HALT +// +// The core is in debug state when this bit is set. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 + +// Field: [16] S_REGRDY +// +// Register Read/Write on the Debug Core Register Selector register is +// available. Last transfer is complete. +// When writing to this register, 1 must be written this bit-field, otherwise +// the write operation is ignored and no bits are written into the register. +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 + +// Field: [5] C_SNAPSTALL +// +// If the core is stalled on a load/store operation the stall ceases and the +// instruction is forced to complete. This enables Halting debug to gain +// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. +// The core reads S_RETIRE_ST as 0. This indicates that no instruction has +// advanced. This prevents misuse. The bus state is Unpredictable when this is +// used. S_RETIRE_ST can detect core stalls on load/store operations. +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 + +// Field: [3] C_MASKINTS +// +// Mask interrupts when stepping or running in halted debug. This masking does +// not affect NMI, fault exceptions and SVC caused by execution of the +// instructions. This bit must only be modified when the processor is halted +// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released +// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must +// be separate). Modifying C_MASKINTS while the system is running with halting +// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable +// behavior. +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 + +// Field: [2] C_STEP +// +// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. +// Must only be modified when the processor is halted (S_HALT == 1). +// Modifying C_STEP while the system is running with halting debug support +// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 + +// Field: [1] C_HALT +// +// Halts the core. This bit is set automatically when the core Halts. For +// example Breakpoint. This bit clears on core reset. +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 + +// Field: [0] C_DEBUGEN +// +// Enables debug. This can only be written by AHB-AP and not by the core. It is +// ignored when written by the core, which cannot set or clear it. The core +// must write a 1 to it when writing C_HALT to halt itself. +// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when +// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will +// be unknown to software when C_DEBUGEN = 0. +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRSR +// +//***************************************************************************** +// Field: [16] REGWNR +// +// 1: Write +// 0: Read +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 + +// Field: [4:0] REGSEL +// +// Register select +// +// 0x00: R0 +// 0x01: R1 +// 0x02: R2 +// 0x03: R3 +// 0x04: R4 +// 0x05: R5 +// 0x06: R6 +// 0x07: R7 +// 0x08: R8 +// 0x09: R9 +// 0x0A: R10 +// 0x0B: R11 +// 0x0C: R12 +// 0x0D: Current SP +// 0x0E: LR +// 0x0F: DebugReturnAddress +// 0x10: XPSR/flags, execution state information, and exception number +// 0x11: MSP (Main SP) +// 0x12: PSP (Process SP) +// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DCRDR +// +//***************************************************************************** +// Field: [31:0] DCRDR +// +// This register holds data for reading and writing registers to and from the +// processor. This is the data value written to the register selected by DCRSR. +// When the processor receives a request from DCRSR, this register is read or +// written by the processor using a normal load-store unit operation. If core +// register transfers are not being performed, software-based debug monitors +// can use this register for communication in non-halting debug. This enables +// flags and bits to acknowledge state and indicate if commands have been +// accepted to, replied to, or accepted and replied to. +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_DEMCR +// +//***************************************************************************** +// Field: [24] TRCENA +// +// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, +// ITM, ETM and TPIU. This enables control of power usage unless tracing is +// required. The application can enable this, for ITM use, or use by a +// debugger. +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 + +// Field: [19] MON_REQ +// +// This enables the monitor to identify how it wakes up. This bit clears on a +// Core Reset. +// +// 0x0: Woken up by debug exception. +// 0x1: Woken up by MON_PEND +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 + +// Field: [18] MON_STEP +// +// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. +// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped +// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, +// or BASEPRI. +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 + +// Field: [17] MON_PEND +// +// Pend the monitor to activate when priority permits. This can wake up the +// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for +// Monitor debug. This register does not reset on a system reset. It is only +// reset by a power-on reset. Software in the reset handler or later, or by the +// DAP must enable the debug monitor. +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 + +// Field: [16] MON_EN +// +// Enable the debug monitor. +// When enabled, the System handler priority register controls its priority +// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN +// overrides this bit. Vector catching is semi-synchronous. When a matching +// event is seen, a Halt is requested. Because the processor can only halt on +// an instruction boundary, it must wait until the next instruction boundary. +// As a result, it stops on the first instruction of the exception handler. +// However, two special cases exist when a vector catch has triggered: 1. If a +// fault is taken during vectoring, vector read or stack push error, the halt +// occurs on the corresponding fault handler, for the vector error or stack +// push. 2. If a late arriving interrupt comes in during vectoring, it is not +// taken. That is, an implementation that supports the late arrival +// optimization must suppress it in this case. +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 + +// Field: [10] VC_HARDERR +// +// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 + +// Field: [9] VC_INTERR +// +// Debug trap on a fault occurring during an exception entry or return +// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 + +// Field: [8] VC_BUSERR +// +// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 + +// Field: [7] VC_STATERR +// +// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 + +// Field: [6] VC_CHKERR +// +// Debug trap on Usage Fault enabled checking errors. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 + +// Field: [5] VC_NOCPERR +// +// Debug trap on a UsageFault access to a Coprocessor. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 + +// Field: [4] VC_MMERR +// +// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is +// cleared. +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 + +// Field: [0] VC_CORERESET +// +// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when +// DHCSR.C_DEBUGEN is cleared. +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_STIR +// +//***************************************************************************** +// Field: [8:0] INTID +// +// Interrupt ID field. Writing a value to this bit-field is the same as +// manually pending an interrupt by setting the corresponding interrupt bit in +// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCCR +// +//***************************************************************************** +// Field: [31] ASPEN +// +// Automatic State Preservation enable. +// When this bit is set is will cause bit [2] of the Special CONTROL register +// to be set (FPCA) on execution of a floating point instruction which results +// in the floating point state automatically being preserved on exception +// entry. +#define CPU_SCS_FPCCR_ASPEN 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_BITN 31 +#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_S 31 + +// Field: [30] LSPEN +// +// Lazy State Preservation enable. +// Lazy state preservation is when the processor performs a context save, space +// on the stack is reserved for the floating point state but it is not stacked +// until the new context performs a floating point operation. +// 0: Disable automatic lazy state preservation for floating-point context. +// 1: Enable automatic lazy state preservation for floating-point context. +#define CPU_SCS_FPCCR_LSPEN 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_BITN 30 +#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_S 30 + +// Field: [8] MONRDY +// +// Indicates whether the the software executing when the processor allocated +// the FP stack frame was able to set the DebugMonitor exception to pending. +// 0: DebugMonitor is disabled or priority did not permit setting +// DEMCR.MON_PEND when the floating-point stack frame was allocated. +// 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when +// the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MONRDY 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_BITN 8 +#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_S 8 + +// Field: [6] BFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the BusFault exception to pending. +// 0: BusFault is disabled or priority did not permit setting the BusFault +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: BusFault is enabled and priority permitted setting the BusFault handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_BFRDY 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_BITN 6 +#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_S 6 + +// Field: [5] MMRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the MemManage exception to pending. +// 0: MemManage is disabled or priority did not permit setting the MemManage +// handler to the pending state when the floating-point stack frame was +// allocated. +// 1: MemManage is enabled and priority permitted setting the MemManage handler +// to the pending state when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_MMRDY 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_BITN 5 +#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_S 5 + +// Field: [4] HFRDY +// +// Indicates whether the software executing when the processor allocated the FP +// stack frame was able to set the HardFault exception to pending. +// 0: Priority did not permit setting the HardFault handler to the pending +// state when the floating-point stack frame was allocated. +// 1: Priority permitted setting the HardFault handler to the pending state +// when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_HFRDY 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_BITN 4 +#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_S 4 + +// Field: [3] THREAD +// +// Indicates the processor mode was Thread when it allocated the FP stack +// frame. +// 0: Mode was not Thread Mode when the floating-point stack frame was +// allocated. +// 1: Mode was Thread Mode when the floating-point stack frame was allocated. +#define CPU_SCS_FPCCR_THREAD 0x00000008 +#define CPU_SCS_FPCCR_THREAD_BITN 3 +#define CPU_SCS_FPCCR_THREAD_M 0x00000008 +#define CPU_SCS_FPCCR_THREAD_S 3 + +// Field: [1] USER +// +// Indicates the privilege level of the software executing was User +// (Unpriviledged) when the processor allocated the FP stack frame: +// 0: Privilege level was not user when the floating-point stack frame was +// allocated. +// 1: Privilege level was user when the floating-point stack frame was +// allocated. +#define CPU_SCS_FPCCR_USER 0x00000002 +#define CPU_SCS_FPCCR_USER_BITN 1 +#define CPU_SCS_FPCCR_USER_M 0x00000002 +#define CPU_SCS_FPCCR_USER_S 1 + +// Field: [0] LSPACT +// +// Indicates whether Lazy preservation of the FP state is active: +// 0: Lazy state preservation is not active. +// 1: Lazy state preservation is active. floating-point stack frame has been +// allocated but saving state to it has been deferred. +#define CPU_SCS_FPCCR_LSPACT 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_BITN 0 +#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPCAR +// +//***************************************************************************** +// Field: [31:2] ADDRESS +// +// Holds the (double-word-aligned) location of the unpopulated floating-point +// register space allocated on an exception stack frame. +#define CPU_SCS_FPCAR_ADDRESS_W 30 +#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC +#define CPU_SCS_FPCAR_ADDRESS_S 2 + +//***************************************************************************** +// +// Register: CPU_SCS_O_FPDSCR +// +//***************************************************************************** +// Field: [26] AHP +// +// Default value for Alternative Half Precision bit. (If this bit is set to 1 +// then Alternative half-precision format is selected). +#define CPU_SCS_FPDSCR_AHP 0x04000000 +#define CPU_SCS_FPDSCR_AHP_BITN 26 +#define CPU_SCS_FPDSCR_AHP_M 0x04000000 +#define CPU_SCS_FPDSCR_AHP_S 26 + +// Field: [25] DN +// +// Default value for Default NaN mode bit. (If this bit is set to 1 then any +// operation involving one or more NaNs returns the Default NaN). +#define CPU_SCS_FPDSCR_DN 0x02000000 +#define CPU_SCS_FPDSCR_DN_BITN 25 +#define CPU_SCS_FPDSCR_DN_M 0x02000000 +#define CPU_SCS_FPDSCR_DN_S 25 + +// Field: [24] FZ +// +// Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then +// Flush-to-zero mode is enabled). +#define CPU_SCS_FPDSCR_FZ 0x01000000 +#define CPU_SCS_FPDSCR_FZ_BITN 24 +#define CPU_SCS_FPDSCR_FZ_M 0x01000000 +#define CPU_SCS_FPDSCR_FZ_S 24 + +// Field: [23:22] RMODE +// +// Default value for Rounding Mode control field. (The encoding for this field +// is: +// 0b00 Round to Nearest (RN) mode +// 0b01 Round towards Plus Infinity (RP) mode +// 0b10 Round towards Minus Infinity (RM) mode +// 0b11 Round towards Zero (RZ) mode. +// The specified rounding mode is used by almost all floating-point +// instructions). +#define CPU_SCS_FPDSCR_RMODE_W 2 +#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 +#define CPU_SCS_FPDSCR_RMODE_S 22 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR0 +// +//***************************************************************************** +// Field: [31:28] FP_ROUNDING_MODES +// +// Indicates the rounding modes supported by the FP floating-point hardware. +// The value of this field is: 0b0001 - all rounding modes supported. +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 + +// Field: [27:24] SHORT_VECTORS +// +// Indicates the hardware support for FP short vectors. The value of this field +// is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 +#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 +#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 + +// Field: [23:20] SQUARE_ROOT +// +// Indicates the hardware support for FP square root operations. The value of +// this field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 +#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 +#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 + +// Field: [19:16] DIVIDE +// +// Indicates the hardware support for FP divide operations. The value of this +// field is: 0b0001 - supported. +#define CPU_SCS_MVFR0_DIVIDE_W 4 +#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 +#define CPU_SCS_MVFR0_DIVIDE_S 16 + +// Field: [15:12] FP_EXCEPTION_TRAPPING +// +// Indicates whether the FP hardware implementation supports exception +// trapping. The value of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 + +// Field: [11:8] DOUBLE_PRECISION +// +// Indicates the hardware support for FP double-precision operations. The value +// of this field is: 0b0000 - not supported. +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 + +// Field: [7:4] SINGLE_PRECISION +// +// Indicates the hardware support for FP single-precision operations. The value +// of this field is: 0b0010 - supported. +#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 + +// Field: [3:0] A_SIMD +// +// Indicates the size of the FP register bank. The value of this field is: +// 0b0001 - supported, 16 x 64-bit registers. +#define CPU_SCS_MVFR0_A_SIMD_W 4 +#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F +#define CPU_SCS_MVFR0_A_SIMD_S 0 + +//***************************************************************************** +// +// Register: CPU_SCS_O_MVFR1 +// +//***************************************************************************** +// Field: [31:28] FP_FUSED_MAC +// +// Indicates whether the FP supports fused multiply accumulate operations. The +// value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 + +// Field: [27:24] FP_HPFP +// +// Indicates whether the FP supports half-precision floating-point conversion +// operations. The value of this field is: 0b0001 - supported. +#define CPU_SCS_MVFR1_FP_HPFP_W 4 +#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 +#define CPU_SCS_MVFR1_FP_HPFP_S 24 + +// Field: [7:4] D_NAN_MODE +// +// Indicates whether the FP hardware implementation supports only the Default +// NaN mode. The value of this field is: 0b0001 - hardware supports propagation +// of NaN values. +#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 +#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 +#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 + +// Field: [3:0] FTZ_MODE +// +// Indicates whether the FP hardware implementation supports only the +// Flush-to-Zero mode of operation. The value of this field is: 0b0001 - +// hardware supports full denormalized number arithmetic. +#define CPU_SCS_MVFR1_FTZ_MODE_W 4 +#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F +#define CPU_SCS_MVFR1_FTZ_MODE_S 0 + +#endif // __CPU_SCS__ diff --git a/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_tpiu.h b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_tpiu.h new file mode 100644 index 00000000..e216395e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/itm/hw_cpu_tpiu.h @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2018-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HW_CPU_TPIU_H__ +#define __HW_CPU_TPIU_H__ + +//***************************************************************************** +// +// This section defines the register offsets of +// CPU_TPIU component +// +//***************************************************************************** +// Supported Sync Port Sizes +#define CPU_TPIU_O_SSPSR 0x00000000 + +// Current Sync Port Size +#define CPU_TPIU_O_CSPSR 0x00000004 + +// Async Clock Prescaler +#define CPU_TPIU_O_ACPR 0x00000010 + +// Selected Pin Protocol +#define CPU_TPIU_O_SPPR 0x000000F0 + +// Formatter and Flush Status +#define CPU_TPIU_O_FFSR 0x00000300 + +// Formatter and Flush Control +#define CPU_TPIU_O_FFCR 0x00000304 + +// Formatter Synchronization Counter +#define CPU_TPIU_O_FSCR 0x00000308 + +// Claim Tag Mask +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 + +// Claim Tag Set +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 + +// Current Claim Tag +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 + +// Claim Tag Clear +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 + +// Lock Access Register +#define CPU_TPIU_O_LAR 0x00000FB0 + +// Device ID +#define CPU_TPIU_O_DEVID 0x00000FC8 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port size support +// +// 0x0: Not supported +// 0x1: Supported +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CSPSR +// +//***************************************************************************** +// Field: [3] FOUR +// +// 4-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 + +// Field: [2] THREE +// +// 3-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 + +// Field: [1] TWO +// +// 2-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 + +// Field: [0] ONE +// +// 1-bit port enable +// Writing values with more than one bit set in CSPSR, or setting a bit that is +// not indicated as supported in SSPSR can cause Unpredictable behavior. +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_ACPR +// +//***************************************************************************** +// Field: [12:0] PRESCALER +// +// Divisor for input trace clock is (PRESCALER + 1). +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_SPPR +// +//***************************************************************************** +// Field: [1:0] PROTOCOL +// +// Trace output protocol +// ENUMs: +// SWO_NRZ SerialWire Output (NRZ) +// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset +// value. +// TRACEPORT TracePort mode +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFSR +// +//***************************************************************************** +// Field: [3] FTNONSTOP +// +// 0: Formatter can be stopped +// 1: Formatter cannot be stopped +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FFCR +// +//***************************************************************************** +// Field: [8] TRIGIN +// +// Indicates that triggers are inserted when a trigger pin is asserted. +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 + +// Field: [1] ENFCONT +// +// Enable continuous formatting: +// +// 0: Continuous formatting disabled +// 1: Continuous formatting enabled +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_FSCR +// +//***************************************************************************** +// Field: [31:0] FSCR +// +// The global synchronization trigger is generated by the Program Counter (PC) +// Sampler block. This means that there is no synchronization counter in the +// TPIU. +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMMASK +// +//***************************************************************************** +// Field: [31:0] CLAIMMASK +// +// This register forms one half of the Claim Tag value. When reading this +// register returns the number of bits that can be set (each bit is considered +// separately): +// +// 0: This claim tag bit is not implemented +// 1: This claim tag bit is not implemented +// +// The behavior when writing to this register is described in CLAIMSET. +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMSET +// +//***************************************************************************** +// Field: [31:0] CLAIMSET +// +// This register forms one half of the Claim Tag value. Writing to this +// location allows individual bits to be set (each bit is considered +// separately): +// +// 0: No effect +// 1: Set this bit in the claim tag +// +// The behavior when reading from this location is described in CLAIMMASK. +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMTAG +// +//***************************************************************************** +// Field: [31:0] CLAIMTAG +// +// This register forms one half of the Claim Tag value. Reading this register +// returns the current Claim Tag value. +// Reading CLAIMMASK determines how many bits from this register must be used. +// +// The behavior when writing to this register is described in CLAIMCLR. +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_CLAIMCLR +// +//***************************************************************************** +// Field: [31:0] CLAIMCLR +// +// This register forms one half of the Claim Tag value. Writing to this +// location enables individual bits to be cleared (each bit is considered +// separately): +// +// 0: No effect +// 1: Clear this bit in the claim tag. +// +// The behavior when reading from this location is described in CLAIMTAG. +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 + +//***************************************************************************** +// +// Register: CPU_TPIU_O_DEVID +// +//***************************************************************************** +// The definition of this register's fields can be found here: +// https://developer.arm.com/docs/100165/0201/trace-port-interface-unit/tpiu-programmers-model/tpiu_devid +// Field: [11] NRZ_SWO +// +// This bit Reads-As-One (RAO), indicating that the output is supported. +#define CPU_TPIU_DEVID_NRZ_SWO 0x00000400 +#define CPU_TPIU_DEVID_NRZ_SWO_BITN 11 +#define CPU_TPIU_DEVID_NRZ_SWO_M 0x00000400 +#define CPU_TPIU_DEVID_NRZ_SWO_S 11 + +// Field: [10] MANCHESTER_SWO +// +// This bit Reads-As-One (RAO), indicating that the output is supported. +#define CPU_TPIU_DEVID_MANCHESTER_SWO 0x00000200 +#define CPU_TPIU_DEVID_MANCHESTER_SWO_BITN 10 +#define CPU_TPIU_DEVID_MANCHESTER_SWO_M 0x00000200 +#define CPU_TPIU_DEVID_MANCHESTER_SWO_S 10 + +// Field: [9] PARALLEL_TRACE +// +// This bit Reads-As-Zero (RAZ), indicating that parallel trace port mode is +// not supported. +#define CPU_TPIU_DEVID_PARALLEL_TRACE 0x00000100 +#define CPU_TPIU_DEVID_PARALLEL_TRACE_BITN 9 +#define CPU_TPIU_DEVID_PARALLEL_TRACE_M 0x00000100 +#define CPU_TPIU_DEVID_PARALLEL_TRACE_S 9 + +// Field: [8:6] FIFO_SIZE +// +// Specifies the minimum TPIU buffer size +#define CPU_TPIU_DEVID_FIFO_SIZE_W 2 +#define CPU_TPIU_DEVID_FIFO_SIZE_M 0x000001C0 +#define CPU_TPIU_DEVID_FIFO_SIZE_S 6 + +// Field: [5] ASYNC_TRACECLKIN +// +// Specifies whether TRACECLKIN can be asynchronous to CLK: +// 0b1 = TRACECLKIN can be asynchronous to CLK. +#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN 0x00000020 +#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_BITN 5 +#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_M 0x00000020 +#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_S 5 + +// Field: [4:0] NUM_INPUTS +// +// Numer of trace inputs +// Specifies the number of trace inputs: +// 0b00000 = 1 input +// 0b00001 = 2 inputs +// If the implementation includes an ETM, the value of this field is 0b00001. +#define CPU_TPIU_DEVID_NUM_INPUTS_W 5 +#define CPU_TPIU_DEVID_NUM_INPUTS_M 0x0000001F +#define CPU_TPIU_DEVID_NUM_INPUTS_S 0 +#define CPU_TPIU_DEVID_NUM_INPUTS_ONE 0x00000000 +#define CPU_TPIU_DEVID_NUM_INPUTS_TWO 0x00000001 + +#endif // __CPU_TPIU__ diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.c b/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.c new file mode 100644 index 00000000..870dc013 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.c @@ -0,0 +1,614 @@ +/* + * Copyright (c) 2015-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSCC26XX.c ======== + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +/* + * If TFM_ENABLED is defined, use the Secure Flash Client Interface to + * access the Flash driver. In a Secure-Only environment use flash.h + * directly to access Flash driver. + * + * This is possible due to the driverlib not containing symbols for the + * Flash API itself. The driverlib only contains the ROM and NOROM Flash + * symbols. As a result, when TFM_ENABLED is defined, the Flash API + * symbols are only defined by FlashCC26X4_ns.h, therefore there is no + * overlap of symbols. + */ +#if TFM_ENABLED + #include +#else + #include DeviceFamily_constructPath(driverlib/flash.h) +#endif +#include DeviceFamily_constructPath(driverlib/vims.h) + +/* max number of bytes to write at a time to minimize interrupt latency */ +#define MAX_WRITE_INCREMENT 8 + +/* Max number of writes per row of memory */ +#define MAX_WRITES_PER_FLASH_ROW (83) + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); +static uint8_t disableFlashCache(void); +static void restoreFlashCache(uint8_t mode); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSCC26XX implementation */ +const NVS_FxnTable NVSCC26XX_fxnTable = {NVSCC26XX_close, + NVSCC26XX_control, + NVSCC26XX_erase, + NVSCC26XX_getAttrs, + NVSCC26XX_init, + NVSCC26XX_lock, + NVSCC26XX_open, + NVSCC26XX_read, + NVSCC26XX_unlock, + NVSCC26XX_write}; + +/* + * Semaphore to synchronize access to flash region. + */ +static SemaphoreP_Handle writeSem; + +static size_t sectorSize; /* fetched during init() */ +static size_t sectorBaseMask; /* for efficient argument checking */ + +/* + * ======== NVSCC26XX_close ======== + */ +void NVSCC26XX_close(NVS_Handle handle) +{ + NVSCC26XX_Object *object; + + object = handle->object; + object->opened = false; +} + +/* + * ======== NVSCC26XX_control ======== + */ +int_fast16_t NVSCC26XX_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + return (NVS_STATUS_UNDEFINEDCMD); +} + +/* + * ======== NVSCC26XX_erase ======== + */ +int_fast16_t NVSCC26XX_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSCC26XX_getAttrs ======== + */ +void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + /* FlashSectorSizeGet() returns the size of a flash sector in bytes. */ + attrs->regionBase = hwAttrs->regionBase; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = FlashSectorSizeGet(); +} + +/* + * ======== NVSCC26XX_init ======== + */ +void NVSCC26XX_init(void) +{ + unsigned int key; + SemaphoreP_Handle sem; + +#if TFM_ENABLED + FlashOpen(); +#endif + + /* initialize energy saving variables */ + sectorSize = FlashSectorSizeGet(); + sectorBaseMask = ~(sectorSize - 1); + + /* speculatively create a binary semaphore for thread safety */ + sem = SemaphoreP_createBinary(1); + /* sem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) + { + /* use the binary sem created above */ + writeSem = sem; + HwiP_restore(key); + } + else + { + /* init already called */ + HwiP_restore(key); + /* delete unused Semaphore */ + if (sem) + { + SemaphoreP_delete(sem); + } + } +} + +/* + * ======== NVSCC26XX_lock ======= + */ +int_fast16_t NVSCC26XX_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) + { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSCC26XX_open ======= + */ +NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params *params) +{ + NVSCC26XX_Object *object; + NVSCC26XX_HWAttrs const *hwAttrs; + NVS_Handle handle; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) + { + NVSCC26XX_init(); + if (writeSem == NULL) + { + return (NULL); + } + } + + /* verify NVS region index */ + if (index >= NVS_count) + { + return (NULL); + } + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + if (object->opened == true) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The regionBase must be aligned on a flash page boundary */ + if ((size_t)(hwAttrs->regionBase) & (sectorSize - 1)) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < sectorSize) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != (hwAttrs->regionSize & sectorBaseMask)) + { + SemaphoreP_post(writeSem); + return (NULL); + } + +#if defined(NVSCC26XX_INSTRUMENTED) + /* Check scoreboard parameters are defined & correct */ + if (hwAttrs->scoreboard && + (hwAttrs->flashPageSize == 0 || hwAttrs->scoreboardSize < (hwAttrs->regionSize / hwAttrs->flashPageSize))) + { + SemaphoreP_post(writeSem); + return (NULL); + } +#endif + + object->opened = true; + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSCC26XX_read ======= + */ +int_fast16_t NVSCC26XX_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + memcpy(buffer, (char *)(hwAttrs->regionBase) + offset, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSCC26XX_unlock ======= + */ +void NVSCC26XX_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSCC26XX_write ======= + */ +int_fast16_t NVSCC26XX_write(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags) +{ + NVSCC26XX_HWAttrs const *hwAttrs; + unsigned int key; + unsigned int size; + uint32_t status = 0; + int i; + uint8_t mode; + uint8_t *srcBuf, *dstBuf; + size_t writeIncrement; + int retval = NVS_STATUS_SUCCESS; + +#if defined(NVSCC26XX_INSTRUMENTED) + size_t bytesWritten; + uint32_t sbIndex, writeOffset; +#endif + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) + { + size = bufferSize & sectorBaseMask; + if (bufferSize & (~sectorBaseMask)) + { + size += sectorSize; + } + + retval = doErase(handle, offset & sectorBaseMask, size); + if (retval != NVS_STATUS_SUCCESS) + { + SemaphoreP_post(writeSem); + return (retval); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) + { + /* + * If pre-verify, each destination byte must be able to be changed to the + * source byte (1s to 0s, not 0s to 1s). + * this is satisfied by the following test: + * src == (src & dst) + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + for (i = 0; i < bufferSize; i++) + { + if (srcBuf[i] != (srcBuf[i] & dstBuf[i])) + { + SemaphoreP_post(writeSem); + return (NVS_STATUS_INV_WRITE); + } + } + } + + srcBuf = buffer; + size = bufferSize; + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + + mode = disableFlashCache(); + + while (size) + { + if (size > MAX_WRITE_INCREMENT) + { + writeIncrement = MAX_WRITE_INCREMENT; + } + else + { + writeIncrement = size; + } + key = HwiP_disable(); + status = FlashProgram((uint8_t *)srcBuf, (uint32_t)dstBuf, writeIncrement); + HwiP_restore(key); + + if (status != 0) + { + break; + } + else + { + size -= writeIncrement; + srcBuf += writeIncrement; + dstBuf += writeIncrement; + } + } + + restoreFlashCache(mode); + +#if defined(NVSCC26XX_INSTRUMENTED) + if (hwAttrs->scoreboard) + { + /* + * Write counts are updated even if an error occurs & not all data was + * written. + */ + bytesWritten = bufferSize - size; + writeOffset = offset; + + while (bytesWritten) + { + if (bytesWritten > MAX_WRITE_INCREMENT) + { + writeIncrement = MAX_WRITE_INCREMENT; + } + else + { + writeIncrement = bytesWritten; + } + + sbIndex = writeOffset / hwAttrs->flashPageSize; + hwAttrs->scoreboard[sbIndex]++; + + /* Spin forever if the write limit is exceeded */ + if (hwAttrs->scoreboard[sbIndex] > MAX_WRITES_PER_FLASH_ROW) + { + while (1) {} + } + + writeOffset += writeIncrement; + bytesWritten -= writeIncrement; + } + } +#endif + + if (status != 0) + { + retval = NVS_STATUS_ERROR; + } + else if (flags & NVS_WRITE_POST_VERIFY) + { + /* + * Note: This validates the entire region even on erase mode. + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + + for (i = 0; i < bufferSize; i++) + { + if (srcBuf[i] != dstBuf[i]) + { + retval = NVS_STATUS_ERROR; + break; + } + } + } + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) +{ + NVSCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (offset != (offset & sectorBaseMask)) + { + return (NVS_STATUS_INV_ALIGNMENT); /* poorly aligned start */ + /* address */ + } + + if (offset >= hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); /* offset is past end of region */ + } + + if (offset + size > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_SIZE); /* size is too big */ + } + + if (size != (size & sectorBaseMask)) + { + return (NVS_STATUS_INV_SIZE); /* size is not a multiple of */ + /* sector size */ + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + NVSCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + unsigned int key; + uint8_t mode; + uint32_t status = 0; + uint32_t sectorBase; + int_fast16_t rangeStatus; + +#if defined(NVSCC26XX_INSTRUMENTED) + uint32_t i; + uint32_t sbIndex; +#endif + + /* sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + + if (rangeStatus != NVS_STATUS_SUCCESS) + { + return (rangeStatus); + } + + sectorBase = (uint32_t)hwAttrs->regionBase + offset; + + mode = disableFlashCache(); + + while (size) + { + key = HwiP_disable(); + status = FlashSectorErase(sectorBase); + HwiP_restore(key); + + if (status != FAPI_STATUS_SUCCESS) + { + break; + } + +#if defined(NVSCC26XX_INSTRUMENTED) + if (hwAttrs->scoreboard) + { + /* + * Sector successfully erased; now we must clear scoreboard write + * counts for all pages in the sector. + */ + sbIndex = (sectorBase - (uint32_t)hwAttrs->regionBase) / hwAttrs->flashPageSize; + + for (i = 0; i < (sectorSize / hwAttrs->flashPageSize); i++) + { + hwAttrs->scoreboard[sbIndex + i] = 0; + } + } +#endif + + sectorBase += sectorSize; + size -= sectorSize; + } + + restoreFlashCache(mode); + + if (status != FAPI_STATUS_SUCCESS) + { + return (NVS_STATUS_ERROR); + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== disableFlashCache ======== + * When updating the Flash, the VIMS (Vesatile Instruction Memory System) + * mode must be set to GPRAM or OFF, before programming, and both VIMS + * flash line buffers must be set to disabled. + */ +static uint8_t disableFlashCache(void) +{ + uint8_t mode = VIMSModeGet(VIMS_BASE); + + VIMSLineBufDisable(VIMS_BASE); + + if (mode != VIMS_MODE_DISABLED) + { + VIMSModeSet(VIMS_BASE, VIMS_MODE_DISABLED); + while (VIMSModeGet(VIMS_BASE) != VIMS_MODE_DISABLED) {} + } + + return (mode); +} + +/* + * ======== restoreFlashCache ======== + */ +static void restoreFlashCache(uint8_t mode) +{ + if (mode != VIMS_MODE_DISABLED) + { + VIMSModeSet(VIMS_BASE, VIMS_MODE_ENABLED); + } + + VIMSLineBufEnable(VIMS_BASE); +} diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.h b/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.h new file mode 100644 index 00000000..b37e7b35 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSCC26XX.h @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file NVSCC26XX.h + * @brief Non-Volatile Storage driver for CC13XX/CC26XX devices. + * + * ## Interrupt Latency During Flash Operations # + * + * When writing or erasing flash, interrupts must be disabled to avoid + * executing code in flash while the flash is being reprogrammed. This + * constraint is handled by the driver. Application code does not need + * to safeguard against this. + * + * Additionally, to avoid extremely large interrupt latencies that would be + * incurred if entire blocks were written with interrupts disabled, block + * writes to flash are broken into multiple smaller sizes. + * + * Even with this scheme in place, latencies of roughly 64 microseconds will + * be incurred while flash is being written to. + * + * A similar caveat applies to flash erase operations. Erasing an entire + * flash sector (the minimal amount that can be erased at a time) can take + * roughly 8 milliseconds. This entire operation must be performed with + * interrupts disabled. Here again, this requirement is met internally + * by the driver and flash region erases are performed one sector at a + * time to minimize this significant latency impact. + * + * Care must be taken by the user to not perform flash write or erase + * operations during latency critical phases of an application. See the + * NVS_lock() and NVS_unlock() API descriptions for more information. + * + * ## Maximum flash writes before erase # + * + * On CC13XX & CC26XX memory rows can be 128 or 256 bytes in length; refer to + * the device datasheet for the exact size. A maximum of 83 write operations + * can be performed on a memory row. Once the limit is reached, the row must + * be erased before it is written to again. It is the developer's + * responsibility to ensure that this limit is not exceeded in their + * applications. The developer may also opt to use the third party SPIFFS + * library implementation supported by TIRTOS which does track writes. + * + * \note The 83 write limit persists through device reset & power cycles. + * If 60 write operations were performed on a memory row & the device is + * reset; the page can still only be written to 23 more times before it must + * be erased. + * + * A write "Scoreboard" can be enabled in this driver; the scoreboard keeps + * track of how many times a page has been written to. It is provided as a + * debug tool to ensure the 83 write limit is not exceeded. If a page is + * written to more than 83 times, the NVSCC26XX driver will spin forever. + * Each byte in the scoreboard corresponds to a memory page in the NVS region. + * The byte is incremented when the memory is written to & set to 0 when + * erased. + * + * To enable the "scoreboard" the "NVSCC26XX_INSTRUMENTED" symbol must be + * defined when the driver is compiled. Three new fields are added to the + * #NVSCC26XX_HWAttrs structure: + * * scoreboard - a buffer provided by the application where each byte + * represents how many times a page has been written to. + * * scoreboardSize - number of bytes in the scoreboard. + * * flashPageSize - number of bytes in a flash page (i.e. 128 or 256) + * + * When configured correctly, the scoreboard can be viewed in a memory browser. + * + * \note The scoreboard will only keep track of writes to flash within a + * NVS region using a NVS driver. Writes performed outside the NVS + * region or without the NVS driver are untracked. + * + * \note The scoreboard is in RAM & will be lost on reset or power cycle. + * + * + * ============================================================================ + */ + +#ifndef ti_drivers_nvs_NVSCC26XX__include +#define ti_drivers_nvs_NVSCC26XX__include + +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Error status code returned by NVS_erase(), NVS_write(). + * + * This error status is returned if the system voltage is too low to safely + * perform the flash operation. Voltage must be 1.5V or greater. + */ +#define NVSCC26XX_STATUS_LOW_VOLTAGE (NVS_STATUS_RESERVED - 1) + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSCC26XX_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + * + * An example of a custom NVS function table is shown below: + * @code + * // + * // Since the application does not use the + * // NVS_control(), NVS_lock(), and NVS_unlock() APIs, + * // these APIs are removed from the function + * // pointer table and replaced with NULL + * // + * const NVS_FxnTable myNVS_fxnTable = { + * NVSCC26XX_close, + * NULL, // remove NVSCC26XX_control(), + * NVSCC26XX_erase, + * NVSCC26XX_getAttrs, + * NVSCC26XX_init, + * NULL, // remove NVSCC26XX_lock(), + * NVSCC26XX_open, + * NVSCC26XX_read, + * NULL, // remove NVSCC26XX_unlock(), + * NVSCC26XX_write + * }; + * @endcode + */ +extern const NVS_FxnTable NVSCC26XX_fxnTable; + +/*! + * @brief NVSCC26XX hardware attributes + * + * The NVSCC26XX hardware attributes define hardware specific settings + * for a NVS driver instance. + * + * \note Care must be taken to ensure that the linker does not place application + * content (such as .text or .const) in the flash regions defined by the + * this hardware attributes structure. + * + * For CCS and IAR tools, defining and reserving flash memory regions can be + * done entirely within the ti_drivers_config.c file. For GCC, additional + * content is required in the application's linker script to achieve the same + * result. + * + * The example below defines a char array @p flashBuf. Preprocessor logic is + * used so that this example will work with either the TI, IAR or GCC tools. + * For the TI and IAR tools, pragmas are used to place @p flashBuf at the + * flash location specified by #NVSCC26XX_HWAttrs.regionBase. + * + * For the GCC tool, the @p flashBuf array is placed into a named linker output + * section, @p .nvs. This section is defined in the application's linker + * script. The section placement command is carefully chosen to only RESERVE + * space for the @p flashBuf array, and not to actually initialize it during + * the application load process, thus preserving the content of flash. + * + * Regardless of tool chain, the @p flashBuf array in the example below is + * placed at the @p NVS_REGIONS_BASE address and has an overall size of + * @p REGIONSIZE bytes. Theoretically, the memory reserved by @p flashBuf can + * be divided into four separate regions, each having a size of @p SECTORSIZE + * bytes. Each region must always be aligned to the flash sector size, + * @p SECTORSIZE. This example below shows two regions defined. + * + * An array of two #NVSCC26XX_HWAttrs structures is defined. Each index + * of this structure defines a region of on-chip flash memory. Both regions + * utilize memory reserved by the @p flashBuf array. The two regions do not + * overlap or share the same physical memory locations. The two regions do + * however exist adjacent to each other in physical memory. The first + * region is defined as starting at the @p NVS_REGIONS_BASE address and has a + * size equal to the flash sector size, as defined by @p SECTORSIZE. The second + * region is defined as starting at (NVS_REGIONS_BASE + SECTORSIZE), that is, + * the @p NVS_REGIONS_BASE address offset by @p SECTORSIZE bytes. The second region + * has a size equal to (3 * SECTORSIZE) bytes. These regions together fully + * occupy @p REGIONSIZE bytes of physical on-chip flash memory as reserved by + * the @p flashBuf array. + * + * @code + * #define NVS_REGIONS_BASE 0x1B000 + * #define SECTORSIZE 0x1000 + * #define REGIONSIZE (SECTORSIZE * 4) + * + * // + * // Reserve flash sectors for NVS driver use + * // by placing an uninitialized byte array + * // at the desired flash address. + * // + * #if defined(__TI_COMPILER_VERSION__) + * + * // + * // Place uninitialized array at FLASH_REGION_BASE + * // + * #pragma LOCATION(flashBuf, FLASH_REGION_BASE); + * #pragma NOINIT(flashBuf); + * char flashBuf[REGIONSIZE]; + * + * #elif defined(__IAR_SYSTEMS_ICC__) + * + * // + * // Place uninitialized array at FLASH_REGION_BASE + * // + * __no_init char flashBuf[REGIONSIZE] @ FLASH_REGION_BASE; + * + * #elif defined(__GNUC__) + * + * // + * // Place the flash buffers in the .nvs section created in the gcc linker file. + * // The .nvs section enforces alignment on a sector boundary but may + * // be placed anywhere in flash memory. If desired the .nvs section can be set + * // to a fixed address by changing the following in the gcc linker file: + * // + * // .nvs (FIXED_FLASH_ADDR) (NOLOAD) : AT (FIXED_FLASH_ADDR) { + * // *(.nvs) + * // } > REGION_TEXT + * // + * + * __attribute__ ((section (".nvs"))) + * char flashBuf[REGIONSIZE]; + * + * #endif + * + * NVSCC26XX_HWAttrs nvsCC26XXHWAttrs[2] = { + * // + * // region 0 is 1 flash sector in length. + * // + * { + * .regionBase = (void *)flashBuf, + * .regionSize = SECTORSIZE, + * }, + * // + * // region 1 is 3 flash sectors in length. + * // + * { + * .regionBase = (void *)(flashBuf + SECTORSIZE), + * .regionSize = SECTORSIZE * 3, + * } + * }; + * @endcode + * + * Example GCC linker script file content. This example places an output + * section, @p .nvs, at the memory address @p 0x1B000. The @p NOLOAD directive + * is used so that this memory is not initialized during program load to the + * target. + * + * @code + * MEMORY + * { + * FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x0001ffa8 + * FLASH_CCFG (R) : ORIGIN = 0x0001ffa8, LENGTH = 0x00000058 + * SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000 + * } + * + * .nvs (0x1b000) (NOLOAD) : AT (0x1b000) { + * *(.nvs) + * } > REGION_TEXT + * @endcode + * + * If the write "scoreboard" is enabled, three new fields are added to the + * NVSCC26XX_HWAttrs structure: + * * scoreboard - a buffer provided by the application where each byte + * represents how many times a page has been written to. It is important + * that this buffer be large enough such that there is a byte for each + * page of memory in the NVS region. For example: + * - 64k NVS region + * - 256 byte page size + * - 64k / 256 = 256; the scoreboard buffer must be 256 bytes in length + * + * * scoreboardSize - number of bytes in the scoreboard. + * + * * flashPageSize - number of bytes in a flash page (i.e. 128 or 256) + */ +typedef struct +{ + void *regionBase; /*!< The regionBase field specifies the base + address of the on-chip flash memory to be + managed. The regionBase must be aligned + to the flash sector size. This memory + cannot be shared and must be for exclusive + use by one NVS driver instance. */ + + size_t regionSize; /*!< The regionSize field specifies the + overall size of the on-chip flash memory + to be managed. The regionSize must be at + least 1 flash sector size AND an integer + multiple of the flash sector size. For most + CC26XX/CC13XX devices, the flash sector + size is 4096 bytes. The NVSCC26XX driver + will determine the device's actual sector + size by reading internal system + configuration registers. */ + +#if defined(NVSCC26XX_INSTRUMENTED) + uint8_t *scoreboard; /*!< Pointer to scoreboard */ + size_t scoreboardSize; /*!< Scoreboard size in bytes */ + uint32_t flashPageSize; /*!< Size of a memory page in bytes */ +#endif +} NVSCC26XX_HWAttrs; + +/* + * @brief NVSCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool opened; /* Has this region been opened */ +} NVSCC26XX_Object; + +/*! + * @cond NODOC + * NVSCC26XX driver public APIs + */ + +extern void NVSCC26XX_close(NVS_Handle handle); + +extern int_fast16_t NVSCC26XX_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); + +extern int_fast16_t NVSCC26XX_erase(NVS_Handle handle, size_t offset, size_t size); + +extern void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); + +extern void NVSCC26XX_init(void); + +extern int_fast16_t NVSCC26XX_lock(NVS_Handle handle, uint32_t timeout); + +extern NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params *params); + +extern int_fast16_t NVSCC26XX_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); + +extern void NVSCC26XX_unlock(NVS_Handle handle); + +extern int_fast16_t NVSCC26XX_write(NVS_Handle handle, + size_t offset, + void *buffer, + size_t bufferSize, + uint_fast16_t flags); +/*! @endcond */ + +#if defined(__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_nvs_NVSCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.c b/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.c new file mode 100644 index 00000000..c875d4d9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.c @@ -0,0 +1,388 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSRAM.c ======== + */ + +#include +#include +#include + +#include +#include + +#include +#include + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSRAM implementation */ +const NVS_FxnTable NVSRAM_fxnTable = {NVSRAM_close, + NVSRAM_control, + NVSRAM_erase, + NVSRAM_getAttrs, + NVSRAM_init, + NVSRAM_lock, + NVSRAM_open, + NVSRAM_read, + NVSRAM_unlock, + NVSRAM_write}; + +/* + * Semaphore to synchronize access to the region. + */ +static SemaphoreP_Handle writeSem; + +/* + * ======== NVSRAM_close ======== + */ +void NVSRAM_close(NVS_Handle handle) +{ + ((NVSRAM_Object *)handle->object)->isOpen = false; +} + +/* + * ======== NVSRAM_control ======== + */ +int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + return (NVS_STATUS_UNDEFINEDCMD); +} + +/* + * ======== NVSRAM_erase ======== + */ +int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSRAM_getAttrs ======== + */ +void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + attrs->regionBase = hwAttrs->regionBase; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = hwAttrs->sectorSize; +} + +/* + * ======== NVSRAM_init ======== + */ +void NVSRAM_init(void) +{ + uintptr_t key; + SemaphoreP_Handle sem; + + /* speculatively create a binary semaphore for thread safety */ + sem = SemaphoreP_createBinary(1); + /* sem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) + { + /* use the binary sem created above */ + writeSem = sem; + HwiP_restore(key); + } + else + { + /* init already called */ + HwiP_restore(key); + + /* delete unused Semaphore */ + if (sem) + { + SemaphoreP_delete(sem); + } + } +} + +/* + * ======== NVSRAM_lock ======= + */ +int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) + { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSRAM_open ======= + */ +NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params) +{ + NVS_Handle handle; + NVSRAM_Object *object; + NVSRAM_HWAttrs const *hwAttrs; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) + { + NVSRAM_init(); + if (writeSem == NULL) + { + return (NULL); + } + } + + /* verify NVS region index */ + if (index >= NVS_count) + { + return (NULL); + } + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + /* for efficient argument checking */ + object->sectorBaseMask = ~(hwAttrs->sectorSize - 1); + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + if (object->isOpen) + { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The regionBase must be aligned on a page boundary */ + if ((size_t)(hwAttrs->regionBase) & (hwAttrs->sectorSize - 1)) + { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < hwAttrs->sectorSize) + { + SemaphoreP_post(writeSem); + + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != (hwAttrs->regionSize & object->sectorBaseMask)) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + object->isOpen = true; + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSRAM_read ======= + */ +int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize) +{ + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + memcpy(buffer, (char *)(hwAttrs->regionBase) + offset, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSRAM_unlock ======= + */ +void NVSRAM_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSRAM_write ======= + */ +int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags) +{ + size_t i; + uint8_t *dstBuf; + uint8_t *srcBuf; + int_fast16_t result; + size_t size; + NVSRAM_Object *object = handle->object; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) + { + size = bufferSize & object->sectorBaseMask; + if (bufferSize & (~object->sectorBaseMask)) + { + size += hwAttrs->sectorSize; + } + + result = doErase(handle, offset & object->sectorBaseMask, size); + if (result != NVS_STATUS_SUCCESS) + { + SemaphoreP_post(writeSem); + + return (result); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) + { + /* + * If pre-verify, each destination byte must be able to be changed to the + * source byte (1s to 0s, not 0s to 1s). + * this is satisfied by the following test: + * src == (src & dst) + */ + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + for (i = 0; i < bufferSize; i++) + { + if (srcBuf[i] != (srcBuf[i] & dstBuf[i])) + { + SemaphoreP_post(writeSem); + return (NVS_STATUS_INV_WRITE); + } + } + } + + dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); + srcBuf = buffer; + memcpy((void *)dstBuf, (void *)srcBuf, bufferSize); + + SemaphoreP_post(writeSem); + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) +{ + NVSRAM_Object *object = handle->object; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (offset != (offset & object->sectorBaseMask)) + { + /* poorly aligned start address */ + return (NVS_STATUS_INV_ALIGNMENT); + } + + if (offset >= hwAttrs->regionSize) + { + /* offset is past end of region */ + return (NVS_STATUS_INV_OFFSET); + } + + if (offset + size > hwAttrs->regionSize) + { + /* size is too big */ + return (NVS_STATUS_INV_SIZE); + } + + if (size != (size & object->sectorBaseMask)) + { + /* size is not a multiple of sector size */ + return (NVS_STATUS_INV_SIZE); + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + void *sectorBase; + int_fast16_t rangeStatus; + NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + if (rangeStatus != NVS_STATUS_SUCCESS) + { + return (rangeStatus); + } + + sectorBase = (void *)((uint32_t)hwAttrs->regionBase + offset); + + memset(sectorBase, 0xFF, size); + + return (NVS_STATUS_SUCCESS); +} diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.h b/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.h new file mode 100644 index 00000000..f446e24e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSRAM.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file NVSRAM.h + * + * @brief RAM implementation of the NVS driver + * + * This NVS driver implementation makes use of RAM instead of FLASH memory. + * It can be used for developing code which relies the NVS driver without + * wearing down FLASH memory. + * + * The NVS header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_nvs_NVSRAM__include +#define ti_drivers_nvs_NVSRAM__include + +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSRAM_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + * + * An example of a custom NVS function table is shown below: + * @code + * // + * // Since the application does not use the + * // NVS_control(), NVS_lock(), and NVS_unlock() APIs, + * // these APIs are removed from the function + * // pointer table and replaced with NULL + * // + * const NVS_FxnTable myNVS_fxnTable = { + * NVSRAM_close, + * NULL, // remove NVSRAM_control(), + * NVSRAM_erase, + * NVSRAM_getAttrs, + * NVSRAM_init, + * NULL, // remove NVSRAM_lock(), + * NVSRAM_open, + * NVSRAM_read, + * NULL, // remove NVSRAM_unlock(), + * NVSRAM_write + * }; + * @endcode + */ +extern const NVS_FxnTable NVSRAM_fxnTable; + +/*! + * @brief NVSRAM Hardware Attributes + * + * The 'sectorSize' is the minimal amount of data to that is cleared on an + * erase operation. Devices which feature internal FLASH memory usually + * have a 4096 byte sector size (refer to device specific documentation). It + * is recommended that the 'sectorSize' used match the FLASH memory sector + * size. + * + * The 'regionBase' field must point to the base address of the region + * to be managed. It is also required that the region be aligned on a + * sectorSize boundary (example below to demonstrate how to do this). + * + * The 'regionSize' must be an integer multiple of the 'sectorSize'. + * + * Defining and reserving RAM memory regions can be done entirely within the + * ti_drivers_config.c file. + * + * The example below defines a char array, 'ramBuf' and uses compiler + * pragmas to place 'ramBuf' at an aligned address within RAM. + * + * @code + * #define SECTORSIZE (4096) + * + * static char ramBuf[SECTORSIZE * 4] __attribute__ ((aligned (4096))); + * + * NVSRAM_HWAttrs NVSRAMHWAttrs[1] = { + * { + * .regionBase = (void *) ramBuf, + * .regionSize = SECTORSIZE * 4, + * .sectorSize = SECTORSIZE + * } + * }; + * + * + * @endcode + */ +typedef struct +{ + void *regionBase; /*!< Base address of RAM region */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Sector size in bytes */ +} NVSRAM_HWAttrs; + +/* + * @brief NVSRAM Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + size_t sectorBaseMask; + bool isOpen; +} NVSRAM_Object; + +/* + * @cond NODOC + * NVSRAM driver public APIs + */ + +extern void NVSRAM_close(NVS_Handle handle); +extern int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); +extern int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, size_t size); +extern void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); +extern void NVSRAM_init(void); +extern int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout); +extern NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params); +extern int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); +extern void NVSRAM_unlock(NVS_Handle handle); +extern int_fast16_t NVSRAM_write(NVS_Handle handle, + size_t offset, + void *buffer, + size_t bufferSize, + uint_fast16_t flags); + +/*! @endcond */ + +#if defined(__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/*@}*/ +#endif /* ti_drivers_nvs_NVSRAM__include */ diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.c b/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.c new file mode 100644 index 00000000..3a45c630 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.c @@ -0,0 +1,1013 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== NVSSPI25X.c ======== + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +/* Instruction codes */ +#define SPIFLASH_WRITE 0x02 /**< Page Program */ +#define SPIFLASH_READ 0x03 /**< Read Data */ +#define SPIFLASH_READ_STATUS 0x05 /**< Read Status Register */ +#define SPIFLASH_WRITE_ENABLE 0x06 /**< Write Enable */ +#define SPIFLASH_SUBSECTOR_ERASE 0x20 /**< SubSector (4K Byte) Erase */ +#define SPIFLASH_SECTOR_ERASE 0xD8 /**< Sector (64K Byte) Erase */ +#define SPIFLASH_MASS_ERASE 0xC7 /**< Erase entire flash */ + +#define SPIFLASH_RDP 0xAB /**< Release from Deep Power Down */ +#define SPIFLASH_DP 0xB9 /**< Deep Power Down */ + +/* Bitmasks of the status register */ +#define SPIFLASH_STATUS_BIT_BUSY 0x01 /**< Busy bit of status register */ + +/* Write page size assumed by this driver */ +#define SPIFLASH_PROGRAM_PAGE_SIZE 256 + +/* Highest supported SPI instance index */ +#define MAX_SPI_INDEX 3 + +/* Size of hardware sector erased by SPIFLASH_SECTOR_ERASE */ +#define SPIFLASH_SECTOR_SIZE 0x10000 + +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); +static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); +static int_fast16_t doWriteVerify(NVS_Handle handle, + size_t offset, + void *src, + size_t srcBufSize, + void *dst, + size_t dstBufSize, + bool preFlag); + +static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len); +static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len); +static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle); +static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle); +static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle); +static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle); +static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle); + +extern NVS_Config NVS_config[]; +extern const uint8_t NVS_count; + +/* NVS function table for NVSSPI25X implementation */ +const NVS_FxnTable NVSSPI25X_fxnTable = {NVSSPI25X_close, + NVSSPI25X_control, + NVSSPI25X_erase, + NVSSPI25X_getAttrs, + NVSSPI25X_init, + NVSSPI25X_lock, + NVSSPI25X_open, + NVSSPI25X_read, + NVSSPI25X_unlock, + NVSSPI25X_write}; + +/* Manage SPI indexes */ +static SPI_Handle spiHandles[MAX_SPI_INDEX + 1]; +static uint8_t spiHandleUsers[MAX_SPI_INDEX + 1]; + +/* + * Currently active (protected within Semaphore_pend() block) + * SPI handle, and CSN pin + */ +static SPI_Handle spiHandle; +static uint32_t spiCsnGpioIndex; + +/* + * Semaphore to synchronize access to flash region. + */ +static SemaphoreP_Handle writeSem; + +/* + * ======== NVSSPI25X_close ======== + */ +void NVSSPI25X_close(NVS_Handle handle) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + hwAttrs = handle->hwAttrs; + object = handle->object; + + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* Close the SPI if we opened it */ + if (hwAttrs->spiHandle == NULL) + { + spiHandleUsers[hwAttrs->spiIndex] -= 1; + + /* Close SPI if this is the last region that uses it */ + if (spiHandleUsers[hwAttrs->spiIndex] == 0) + { + /* Ensure part is responsive */ + extFlashWaitReady(handle); + + /* Put the part in low power mode */ + extFlashPowerDown(handle); + + SPI_close(object->spiHandle); + spiHandles[hwAttrs->spiIndex] = NULL; + } + } + + NVSSPI25X_deinitSpiCs(handle, spiCsnGpioIndex); + + object->opened = false; + + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSSPI25X_control ======== + */ +int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + + if (cmd != NVSSPI25X_CMD_MASS_ERASE) + { + return (NVS_STATUS_UNDEFINEDCMD); + } + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + return (extFlashMassErase(handle)); +} + +/* + * ======== NVSSPI25X_erase ======== + */ +int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, size_t size) +{ + int_fast16_t status; + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + status = doErase(handle, offset, size); + + SemaphoreP_post(writeSem); + + return (status); +} + +/* + * ======== NVSSPI25X_getAttrs ======== + */ +void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + + hwAttrs = handle->hwAttrs; + + attrs->regionBase = NVS_REGION_NOT_ADDRESSABLE; + attrs->regionSize = hwAttrs->regionSize; + attrs->sectorSize = hwAttrs->sectorSize; +} + +/* + * ======== NVSSPI25X_init ======== + */ +void NVSSPI25X_init(void) +{ + unsigned int key; + SemaphoreP_Handle tempSem; + + SPI_init(); + + /* Speculatively create semaphore so critical section is faster */ + tempSem = SemaphoreP_createBinary(1); + /* tempSem == NULL will be detected in 'open' */ + + key = HwiP_disable(); + + if (writeSem == NULL) + { + /* First time init, assign handle */ + writeSem = tempSem; + + HwiP_restore(key); + } + else + { + /* Init already called */ + HwiP_restore(key); + + /* Delete unused Semaphores */ + if (tempSem) + { + SemaphoreP_delete(tempSem); + } + } +} + +/* + * ======== NVSSPI25X_lock ======= + */ +int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout) +{ + if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) + { + return (NVS_STATUS_TIMEOUT); + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== NVSSPI25X_open ======= + */ +NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t sectorSize; + NVS_Handle handle; + SPI_Params spiParams; + + /* Confirm that 'init' has successfully completed */ + if (writeSem == NULL) + { + NVSSPI25X_init(); + if (writeSem == NULL) + { + return (NULL); + } + } + + /* Verify NVS region index */ + if (index >= NVS_count) + { + return (NULL); + } + + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + handle = &NVS_config[index]; + object = NVS_config[index].object; + hwAttrs = NVS_config[index].hwAttrs; + + if (object->opened == true) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + sectorSize = hwAttrs->sectorSize; + object->sectorBaseMask = ~(sectorSize - 1); + + /* The regionBase must be aligned on a flash page boundary */ + if ((hwAttrs->regionBaseOffset) & (sectorSize - 1)) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region cannot be smaller than a sector size */ + if (hwAttrs->regionSize < sectorSize) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + /* The region size must be a multiple of sector size */ + if (hwAttrs->regionSize != (hwAttrs->regionSize & object->sectorBaseMask)) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + if (hwAttrs->spiHandle) + { + /* Use the provided SPI Handle */ + object->spiHandle = *hwAttrs->spiHandle; + } + else + { + if (hwAttrs->spiIndex > MAX_SPI_INDEX) + { + SemaphoreP_post(writeSem); + return (NULL); + } + /* Open SPI if this driver hasn't already opened this SPI instance */ + if (spiHandles[hwAttrs->spiIndex] == NULL) + { + SPI_Handle spi; + + SPI_Params_init(&spiParams); + spiParams.bitRate = hwAttrs->spiBitRate; + spiParams.mode = SPI_CONTROLLER; + spiParams.transferMode = SPI_MODE_BLOCKING; + + /* Attempt to open SPI. */ + spi = SPI_open(hwAttrs->spiIndex, &spiParams); + + if (spi == NULL) + { + SemaphoreP_post(writeSem); + return (NULL); + } + + spiHandles[hwAttrs->spiIndex] = spi; + } + object->spiHandle = spiHandles[hwAttrs->spiIndex]; + /* Keep track of how many regions use the same SPI handle */ + spiHandleUsers[hwAttrs->spiIndex] += 1; + } + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* Initialize chip select output */ + NVSSPI25X_initSpiCs(handle, spiCsnGpioIndex); + + object->opened = true; + + /* Put the part in standby mode */ + extFlashPowerStandby(handle); + + SemaphoreP_post(writeSem); + + return (handle); +} + +/* + * ======== NVSSPI25X_read ======= + */ +int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + int retval = NVS_STATUS_SUCCESS; + + hwAttrs = handle->hwAttrs; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* + * Get exclusive access to the region. We don't want someone + * else to erase the region while we are reading it. + */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + retval = doRead(handle, offset, buffer, bufferSize); + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== NVSSPI25X_unlock ======= + */ +void NVSSPI25X_unlock(NVS_Handle handle) +{ + SemaphoreP_post(writeSem); +} + +/* + * ======== NVSSPI25X_write ======= + */ +int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize, uint_fast16_t flags) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t length, foffset; + uint32_t status = true; + uint8_t *srcBuf; + int retval = NVS_STATUS_SUCCESS; + uint8_t wbuf[4]; + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Validate offset and bufferSize */ + if (offset + bufferSize > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); + } + + /* Get exclusive access to the Flash region */ + SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* If erase is set, erase destination sector(s) first */ + if (flags & NVS_WRITE_ERASE) + { + length = bufferSize & object->sectorBaseMask; + if (bufferSize & (~object->sectorBaseMask)) + { + length += hwAttrs->sectorSize; + } + + retval = doErase(handle, offset & object->sectorBaseMask, length); + if (retval != NVS_STATUS_SUCCESS) + { + SemaphoreP_post(writeSem); + return (retval); + } + } + else if (flags & NVS_WRITE_PRE_VERIFY) + { + if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) + { + SemaphoreP_post(writeSem); + return (NVS_STATUS_VERIFYBUFFER); + } + + retval = doWriteVerify(handle, offset, buffer, bufferSize, hwAttrs->verifyBuf, hwAttrs->verifyBufSize, true); + + if (retval != NVS_STATUS_SUCCESS) + { + SemaphoreP_post(writeSem); + return (retval); + } + } + + srcBuf = buffer; + length = bufferSize; + foffset = (size_t)hwAttrs->regionBaseOffset + offset; + + while (length > 0) + { + size_t ilen; /* Interim length per instruction */ + + /* Wait till previous erase/program operation completes */ + int ret = extFlashWaitReady(handle); + + if (ret) + { + status = false; + break; + } + + ret = extFlashWriteEnable(handle); + + if (ret) + { + status = false; + break; + } + + ilen = SPIFLASH_PROGRAM_PAGE_SIZE - (foffset % SPIFLASH_PROGRAM_PAGE_SIZE); + if (length < ilen) + { + ilen = length; + } + + wbuf[0] = SPIFLASH_WRITE; + wbuf[1] = (foffset >> 16) & 0xff; + wbuf[2] = (foffset >> 8) & 0xff; + wbuf[3] = foffset & 0xff; + + foffset += ilen; + length -= ilen; + + /* + * Up to 100ns CS hold time (which is not clear + * whether it's application only in between reads) + * is not imposed here since above instructions + * should be enough to delay + * as much. + */ + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + + if (extFlashSpiWrite(wbuf, sizeof(wbuf)) != NVS_STATUS_SUCCESS) + { + status = false; + break; + } + + if (extFlashSpiWrite(srcBuf, ilen) != NVS_STATUS_SUCCESS) + { + status = false; + break; + } + + srcBuf += ilen; + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + } + + if (status == false) + { + retval = NVS_STATUS_ERROR; + } + else if (flags & NVS_WRITE_POST_VERIFY) + { + if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) + { + SemaphoreP_post(writeSem); + return (NVS_STATUS_VERIFYBUFFER); + } + + retval = doWriteVerify(handle, offset, buffer, bufferSize, hwAttrs->verifyBuf, hwAttrs->verifyBufSize, false); + } + + SemaphoreP_post(writeSem); + + return (retval); +} + +/* + * ======== doWriteVerify ======= + */ +static int_fast16_t doWriteVerify(NVS_Handle handle, + size_t offset, + void *src, + size_t srcBufSize, + void *dst, + size_t dstBufSize, + bool preFlag) +{ + size_t i, j; + uint8_t *srcBuf, *dstBuf; + bool bad; + int_fast16_t retval; + + srcBuf = src; + dstBuf = dst; + + j = dstBufSize; + + for (i = 0; i < srcBufSize; i++, j++) + { + if (j == dstBufSize) + { + retval = doRead(handle, offset + i, dstBuf, j); + if (retval != NVS_STATUS_SUCCESS) + { + break; + } + j = 0; + } + if (preFlag) + { + bad = srcBuf[i] != (srcBuf[i] & dstBuf[j]); + } + else + { + bad = srcBuf[i] != dstBuf[j]; + } + if (bad) + { + return (NVS_STATUS_INV_WRITE); + } + } + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== checkEraseRange ======== + */ +static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + + object = handle->object; + hwAttrs = handle->hwAttrs; + + if (offset != (offset & object->sectorBaseMask)) + { + return (NVS_STATUS_INV_ALIGNMENT); /* Poorly aligned start address */ + } + + if (offset >= hwAttrs->regionSize) + { + return (NVS_STATUS_INV_OFFSET); /* Offset is past end of region */ + } + + if (offset + size > hwAttrs->regionSize) + { + return (NVS_STATUS_INV_SIZE); /* Size is too big */ + } + + if (size != (size & object->sectorBaseMask)) + { + return (NVS_STATUS_INV_SIZE); /* Size is not a multiple of sector size */ + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doErase ======== + */ +static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) +{ + NVSSPI25X_HWAttrs const *hwAttrs; + NVSSPI25X_Object *object; + uint32_t sectorBase; + size_t eraseSize; + int_fast16_t rangeStatus; + uint8_t wbuf[4]; + + /* Sanity test the erase args */ + rangeStatus = checkEraseRange(handle, offset, size); + + if (rangeStatus != NVS_STATUS_SUCCESS) + { + return (rangeStatus); + } + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + /* Start erase at this address */ + sectorBase = (uint32_t)hwAttrs->regionBaseOffset + offset; + + while (size) + { + /* Wait till previous erase/program operation completes */ + int ret = extFlashWaitReady(handle); + if (ret) + { + return (NVS_STATUS_ERROR); + } + + ret = extFlashWriteEnable(handle); + if (ret) + { + return (NVS_STATUS_ERROR); + } + + /* Determine which erase command to use */ + if (size >= SPIFLASH_SECTOR_SIZE && ((sectorBase & (SPIFLASH_SECTOR_SIZE - 1)) == 0)) + { + /* Erase size is one sector (64kB) */ + eraseSize = SPIFLASH_SECTOR_SIZE; + wbuf[0] = SPIFLASH_SECTOR_ERASE; + } + else + { + /* Erase size is one sub-sector (4kB)*/ + eraseSize = hwAttrs->sectorSize; + wbuf[0] = SPIFLASH_SUBSECTOR_ERASE; + } + + /* Format command to send over SPI */ + wbuf[1] = (sectorBase >> 16) & 0xff; + wbuf[2] = (sectorBase >> 8) & 0xff; + wbuf[3] = sectorBase & 0xff; + + /* Send erase command to external flash */ + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + if (extFlashSpiWrite(wbuf, sizeof(wbuf))) + { + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + return (NVS_STATUS_ERROR); + } + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + + sectorBase += eraseSize; + size -= eraseSize; + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== doRead ======= + */ +static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize) +{ + NVSSPI25X_Object *object; + NVSSPI25X_HWAttrs const *hwAttrs; + size_t loffset; + uint8_t wbuf[4]; + int retval = NVS_STATUS_SUCCESS; + + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Set protected global variables */ + spiHandle = object->spiHandle; + spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; + + loffset = offset + hwAttrs->regionBaseOffset; + + /* Wait till previous erase/program operation completes */ + retval = extFlashWaitReady(handle); + if (retval) + { + return (retval); + } + + /* + * SPI is driven with very low frequency (1MHz < 33MHz fR spec) + * in this temporary implementation. + * and hence it is not necessary to use fast read. + */ + wbuf[0] = SPIFLASH_READ; + wbuf[1] = (loffset >> 16) & 0xff; + wbuf[2] = (loffset >> 8) & 0xff; + wbuf[3] = loffset & 0xff; + + NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); + + if (extFlashSpiWrite(wbuf, sizeof(wbuf))) + { + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + return (NVS_STATUS_ERROR); + } + + retval = extFlashSpiRead(buffer, bufferSize); + + NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); + + return (retval); +} + +/* + * ======== extFlashPowerDown ======= + * Issue power down command + */ +static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + cmd = SPIFLASH_DP; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd, sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + return (status); +} + +/* + * ======== extFlashPowerStandby ======= + * Issue standby command + */ +static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + cmd = SPIFLASH_RDP; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd, sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (status == NVS_STATUS_SUCCESS) + { + status = extFlashWaitReady(nvsHandle); + } + + return (status); +} + +/* + * ======== extFlashMassErase ======= + * Issue mass erase command + */ +static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle) +{ + uint8_t cmd; + int_fast16_t status; + + /* Wait for previous operation to complete */ + if (extFlashWaitReady(nvsHandle)) + { + return (NVS_STATUS_ERROR); + } + + cmd = SPIFLASH_MASS_ERASE; + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + status = extFlashSpiWrite(&cmd, sizeof(cmd)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (status != NVS_STATUS_SUCCESS) + { + return (status); + } + + /* Wait for mass erase to complete */ + return (extFlashWaitReady(nvsHandle)); +} + +/* + * ======== extFlashWaitReady ======= + * Wait for any previous job to complete. + */ +static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle) +{ + const uint8_t wbuf[1] = {SPIFLASH_READ_STATUS}; + int_fast16_t ret; + uint8_t buf; + + NVSSPI25X_HWAttrs const *hwAttrs; + hwAttrs = nvsHandle->hwAttrs; + + for (;;) + { + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + extFlashSpiWrite(wbuf, sizeof(wbuf)); + ret = extFlashSpiRead(&buf, sizeof(buf)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + if (ret != NVS_STATUS_SUCCESS) + { + /* Error */ + return (ret); + } + if (!(buf & SPIFLASH_STATUS_BIT_BUSY)) + { + /* Now ready */ + break; + } + if (hwAttrs->statusPollDelayUs) + { + /* Sleep to avoid excessive polling and starvation */ + ClockP_usleep(hwAttrs->statusPollDelayUs); + } + } + + return (NVS_STATUS_SUCCESS); +} + +/* + * ======== extFlashWriteEnable ======= + * Issue SPIFLASH_WRITE_ENABLE command + */ +static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle) +{ + const uint8_t wbuf[] = {SPIFLASH_WRITE_ENABLE}; + int_fast16_t ret; + + NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); + ret = extFlashSpiWrite(wbuf, sizeof(wbuf)); + NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); + + return (ret); +} + +/* + * ======== extFlashSpiWrite ======= + */ +static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len) +{ + SPI_Transaction controllerTransaction; + + controllerTransaction.rxBuf = NULL; + + /* + * Work around SPI transfer from address 0x0 + * transfer first byte from local buffer + */ + if (buf == NULL) + { + uint8_t byte0; + byte0 = *buf++; + controllerTransaction.count = 1; + controllerTransaction.txBuf = (void *)&byte0; + if (!SPI_transfer(spiHandle, &controllerTransaction)) + { + return (NVS_STATUS_ERROR); + } + len = len - 1; + if (len == 0) + { + return (NVS_STATUS_SUCCESS); + } + } + + controllerTransaction.count = len; + controllerTransaction.txBuf = (void *)buf; + + return (SPI_transfer(spiHandle, &controllerTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); +} + +/* + * ======== extFlashSpiRead ======= + */ +static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len) +{ + SPI_Transaction controllerTransaction; + + controllerTransaction.txBuf = NULL; + controllerTransaction.count = len; + controllerTransaction.rxBuf = buf; + + return (SPI_transfer(spiHandle, &controllerTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); +} + +/* + * Below are the default (weak) GPIO-driver based implementations of: + * NVSSPI25X_initSpiCs() + * NVSSPI25X_deinitSpiCs() + * NVSSPI25X_assertSpiCs() + * NVSSPI25X_deassertSpiCs() + */ + +/* + * ======== NVSSPI25X_initSpiCs ======= + */ +void __attribute__((weak)) NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) + { + GPIO_init(); + + /* + * Make SPI Chip Select GPIO an output, and set it high. + * Since the same device may be used for multiple regions, configuring + * the same Chip Select pin may be done multiple times. No harm done. + */ + GPIO_setConfig(csId, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); + } +} + +/* + * ======== NVSSPI25X_deinitSpiCs ======= + */ +void __attribute__((weak)) NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) +{} + +/* + * ======== NVSSPI25X_assertSpiCs ======= + * Assert SPI flash /CS + */ +void __attribute__((weak)) NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) + { + GPIO_write(csId, 0); + } +} + +/* + * ======== NVSSPI25X_deassertSpiCs ======= + * De-assert SPI flash /CS + */ +void __attribute__((weak)) NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) +{ + if (csId != NVSSPI25X_SPI_MANAGES_CS) + { + GPIO_write(csId, 1); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.h b/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.h new file mode 100644 index 00000000..f90691bf --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/NVSSPI25X.h @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2017-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file NVSSPI25X.h + * @brief Non-Volatile Storage driver implementation + * for SPI flash peripherals + * + * # Overview # + * + * The NVSSPI25X module allows you to manage SPI flash memory. + * This driver works with most 256 byte/page SPI flash memory devices + * such as: + * + * Winbond W25xx family + * Macronics MX25Rxx family + * Micron N25Qxx family + * + * The SPI flash commands used by this driver are as follows: + * + * @code + * #define SPIFLASH_PAGE_WRITE 0x02 // Page Program (up to 256 bytes) + * #define SPIFLASH_READ 0x03 // Read Data + * #define SPIFLASH_READ_STATUS 0x05 // Read Status Register + * #define SPIFLASH_WRITE_ENABLE 0x06 // Write Enable + * #define SPIFLASH_SUBSECTOR_ERASE 0x20 // SubSector (4K bytes) Erase + * #define SPIFLASH_SECTOR_ERASE 0xD8 // Sector (usually 64K bytes) Erase + * #define SPIFLASH_RDP 0xAB // Release from Deep Power Down + * #define SPIFLASH_DP 0xB9 // Deep Power Down + * #define SPIFLASH_MASS_ERASE 0xC7 // Erase entire flash. + * @endcode + * + * It is assumed that the SPI flash device used by this driver supports + * the byte programmability of the SPIFLASH_PAGE_WRITE command and that + * write page size is 256 bytes. The erase sector and subsector sizes are + * assumed to be 64K and 4K respectively. + * + * The NVS_erase() command will issue a sector or subsector erase command + * based on the input size and offset. + * + * The driver must query the SPI flash to ensure that the part is ready before + * commands are issued. If the part responds as busy, the poll function sleeps + * for a number of microseconds determined by the + * #NVSSPI25X_HWAttrs.statusPollDelayUs field. A value of 0 means that the + * driver will continuously poll the external flash until it is ready, which + * may affect other threads ability to execute. + * + * ## SPI Interface Management ## + * + * For each managed flash region, a corresponding SPI instance must be + * provided to the NVSSPI25X driver. + * + * The SPI instance can be opened and closed + * internally by the NVSSPI25X driver, or alternatively, a SPI handle can be + * provided to the NVSSPI25X driver, indicating that the SPI instance is being + * opened and closed elsewhere within the application. This mode is useful + * when the SPI bus is share by more than just the SPI flash device. + * + * If the SPI instance is to be managed internally by the NVSSPI25X driver, a SPI + * instance index and bit rate must be configured in the region's HWAttrs. + * If the same SPI instance is referenced by multiple flash regions + * the driver will ensure that SPI_open() is invoked only once, and that + * SPI_close() will only be invoked when all flash regions using the SPI + * instance have been closed. + * + * If the SPI bus that the SPI flash device is on is shared with other + * devices accessed by an application, then the SPI handle used to manage + * a SPI flash region can be provided in the region's HWAttrs "spiHandle" + * field. Keep in mind that the "spiHandle" field is a POINTER to a + * SPI Handle, NOT a SPI Handle. This allows the user to simply initialize + * this field with the name of the global variable used for the SPI handle. + * In this mode, the user MUST open the SPI instance prior to opening the NVS + * region instance so that the referenced spiHandle is valid. + * + * By default, the "spiHandle" field is set to NULL, indicating that the user + * expects the NVS driver to open and close the SPI instance internally using + * the 'spiIndex' and 'spiBitRate' provided in the HWAttrs. + * + * ## @anchor SPI_CS_MGMT SPI Flash Chip Select Management ## + * + * ### Option 1: NVSSPI25X Driver Manages Chip Select ### + * By default, the NVSSPI25X driver will assert and de-assert a GPIO + * driver managed pin to select the SPI flash device before and after + * each SPI transfer to and from the device. + * + * To enable this behavior, a valid GPIO driver instance index must be + * provided in the NVS region's [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the + * NVSSPI25X_HWAttrs structure. The corresponding GPIO pin will be + * configured at runtime by the NVSSPI25X driver as "GPIO_CFG_OUT_STD" + * and assertion of this pin is assumed to be active LOW. + * + * ### Option 2: SPI Driver Manages Chip Select ### + * Some SPI peripherals can be configured to manage their own chip + * select. Setting the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs + * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver + * that the SPI peripheral used by the NVS driver has been configured + * that way. + * + * ### Option 3: User Manages Chip Select ### + * Alternatively, the user can manage the assertion and de-assertion of + * the SPI flash chip select entirely themselves by providing implementations + * of the following 4 APIs in their application code: + * + * @code + * void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is invoked within the NVS_open() API and is where the + * user should do whatever is required to initialize the hardware + * used for asserting and de-assering the SPI chip select signal. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is invoked within the NVS_close() API and is where the + * user should do whatever is required to de-initialize the hardware + * used for asserting and de-assering the SPI chip select signal. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is called PRIOR to every SPI transfer to and from the SPI + * flash device performed by the NVSSPI25X driver. The user code should + * perform the corresponding action required to select the SPI flash + * device to prepare for the SPI transfer. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @code + * void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId); + * @endcode + * - This function is called AFTER every SPI transfer to and from the SPI + * flash device performed by the NVSSPI25X driver. The user code should + * perform the corresponding action required to de-select the SPI flash + * device. + * following the SPI transfer. + * - The 'nvsHandle` argument is the NVS handle associated with the + * corresponding NVS region. + * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) + * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. + * + * @warning All 4 of the above APIs must be provided by the user if this + * option is used, otherwise default internal implementations of the APIs + * will be called that will likely lead to application failure. + */ + +#ifndef ti_drivers_nvs_NVSSPI25X__include +#define ti_drivers_nvs_NVSSPI25X__include + +#include +#include + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Command to perform mass erase of entire flash + * + * As this command can erase flash memory outside the region associated + * with the NVS_Handle passed to the control command, the user must + * carefully orchestrate the use of the command. + * + * Mass Erase is the only control command supported. + */ +#define NVSSPI25X_CMD_MASS_ERASE (NVS_CMD_RESERVED + 0) + +/*! + * @brief Disable internal management of SPI chip select + * + * Some SPI peripherals can be configured to manage their own chip + * select. Setting the [spiCsnGpioIndex] + * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs + * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver + * that the SPI peripheral used by the NVS driver is configured + * to manage its own chip select signal. + */ +#define NVSSPI25X_SPI_MANAGES_CS ((uint16_t)(~0)) + +/*! + * @internal @brief NVS function pointer table + * + * 'NVSSPI25X_fxnTable' is a fully populated function pointer table + * that can be referenced in the NVS_config[] array entries. + * + * Users can minimize their application code size by providing their + * own custom NVS function pointer table that contains only those APIs + * used by the application. + */ +extern const NVS_FxnTable NVSSPI25X_fxnTable; + +/*! + * @brief NVSSPI25X attributes + * + * The 'regionBaseOffset' is the offset, in bytes, from the base of the + * SPI flash, of the flash region to be managed. + * + * The 'regionSize' must be an integer multiple of the flash sector size. + * + * The 'sectorSize' is SPI flash device specific. This parameter should + * correspond to the number of bytes erased when the + * 'SPIFLASH_SUBSECTOR_ERASE' (0x20) command is issued to the device. + * + * The 'verifyBuf' and 'verifyBufSize' parameters are used by the + * NVS_write() command when either 'NVS_WRITE_PRE_VERIFY' or + * 'NVS_WRITE_POST_VERIFY' functions are requested in the 'flags' + * argument. The 'verifyBuf' is used to successively read back portions + * of the flash to compare with the data being written to it. + * + * @code + * // + * // Only one region write operation is performed at a time + * // so a single verifyBuf can be shared by all the regions. + * // + * uint8_t verifyBuf[256]; + * + * NVSSPI25X_HWAttrs nvsSPIHWAttrs[2] = { + * // + * // region 0 is 1 flash sector in length. + * // + * { + * .regionBaseOffset = 0, + * .regionSize = 4096, + * .sectorSize = 4096, + * .verifyBuf = verifyBuf; + * .verifyBufSize = 256; + * .spiHandle = NULL, + * .spiIndex = 0, + * .spiBitRate = 40000000, + * .spiCsnGpioIndex = 12, + * }, + * // + * // region 1 is 3 flash sectors in length. + * // + * { + * .regionBaseOffset = 4096, + * .regionSize = 4096 * 3, + * .sectorSize = 4096, + * .verifyBuf = verifyBuf; // use shared verifyBuf + * .verifyBufSize = 256; + * .spiHandle = NULL, + * .spiIndex = 0, + * .spiBitRate = 40000000, + * .spiCsnGpioIndex = 12, + * } + * }; + * @endcode + */ +typedef struct +{ + size_t regionBaseOffset; /*!< Offset from base of SPI flash */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Erase sector size */ + uint8_t *verifyBuf; /*!< Write Pre/Post verify buffer */ + size_t verifyBufSize; /*!< Write Pre/Post verify buffer size */ + SPI_Handle *spiHandle; /*!< ptr to SPI handle if provided by user. */ + uint16_t spiIndex; /*!< SPI instance index from Board file */ + uint32_t spiBitRate; /*!< SPI bit rate in Hz */ + /*! @brief SPI Flash Chip Select GPIO index + + This field should be set to either an index within the + GPIO driver's GPIO_Config table, or to #NVSSPI25X_SPI_MANAGES_CS. + see [SPI Flash Chip Select Management] (@ref SPI_CS_MGMT) for more + details. + */ + uint16_t spiCsnGpioIndex; + /*! @brief External Flash Status Poll Delay + * + * This field determines how many microseconds the driver waits after + * querying the external flash status. Increasing this value can help + * mitigate CPU starvation if the external flash is busy for long periods + * of time, but may also result in increased latency. + */ + uint32_t statusPollDelayUs; +} NVSSPI25X_HWAttrs; + +/* + * @brief NVSSPI25X Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool opened; /* Has this region been opened */ + SPI_Handle spiHandle; + size_t sectorBaseMask; +} NVSSPI25X_Object; + +/* + * @cond NODOC + * NVSSPI25X driver public APIs + */ + +extern void NVSSPI25X_close(NVS_Handle handle); +extern int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); +extern int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, size_t size); +extern void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); +extern void NVSSPI25X_init(void); +extern int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout); +extern NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params); +extern int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, void *buffer, size_t bufferSize); +extern void NVSSPI25X_unlock(NVS_Handle handle); +extern int_fast16_t NVSSPI25X_write(NVS_Handle handle, + size_t offset, + void *buffer, + size_t bufferSize, + uint_fast16_t flags); +/* + * Weakly defined APIs that can be overridden by the user + */ +extern void NVSSPI25X_initSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deinitSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_assertSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deassertSpiCs(NVS_Handle spiHandle, uint16_t csId); + +/*! @endcond */ + +#if defined(__cplusplus) +} +#endif /* defined (__cplusplus) */ + +/** @}*/ +#endif /* ti_drivers_nvs_NVSSPI25X__include */ diff --git a/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.c new file mode 100644 index 00000000..ae19a6dd --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.c @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== FlashCC26X4_ns.c ======== + */ +#include "FlashCC26X4_ns.h" + +#include "FlashCC26X4_s.h" + +#include +#include + +static psa_handle_t spHandle = 0; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +static struct FlashCC26X4_s_program flashProgramArgs; + +/* + * ======== FlashOpen ======== + */ +int_fast16_t FlashOpen(void) +{ + int_fast16_t status = 0; + + /* if no connection exists, connect */ + if (spHandle <= 0) + { + /* Connect to the Flash Service */ + spHandle = psa_connect(TI_FLASH_SERVICE_SID, psa_version(TI_FLASH_SERVICE_SID)); + + if (spHandle <= 0) + { + /* error connecting */ + status = (int_fast16_t)spHandle; + } + } + + return (status); +} + +/* + * ======== FlashClose ======== + */ +void FlashClose(void) +{ + /* if connection handle exists, close handle */ + if (spHandle > 0) + { + psa_close(spHandle); + spHandle = 0; + } +} + +/* + * ======== FlashProtectionGet ======== + */ +uint32_t FlashProtectionGet(uint32_t ui32SectorAddress) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* set the input vector */ + invecs[0].base = &ui32SectorAddress; + invecs[0].len = sizeof(uint32_t); + + /* set the output vector */ + uint32_t ui32SectorProtect = 0; + outvecs[0].base = &ui32SectorProtect; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashProtectionGet command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_PROTECTION_GET, invecs, 1, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashProtectionGet status code */ + return (ui32SectorProtect); + } +} + +/* + * ======== FlashSectorErase ======== + */ +uint32_t FlashSectorErase(uint32_t ui32SectorAddress) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* set the input vector */ + invecs[0].base = &ui32SectorAddress; + invecs[0].len = sizeof(uint32_t); + + /* set the output vector */ + uint32_t status = 0; + outvecs[0].base = &status; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashSectorErase command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_SECTOR_ERASE, invecs, 1, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashSectorErase status code */ + return (status); + } +} + +/* + * ======== FlashProgram ======== + */ +uint32_t FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* construct structure containing all input arguments */ + flashProgramArgs.dataBuffer = pui8DataBuffer; + flashProgramArgs.sectorAddress = ui32Address; + flashProgramArgs.count = ui32Count; + + /* set the input vector */ + invecs[0].base = &flashProgramArgs; + invecs[0].len = sizeof(flashProgramArgs); + + /* set the output vector */ + uint32_t status = 0; + outvecs[0].base = &status; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashProgram command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_PROGRAM, invecs, 1, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashProgram status code */ + return (status); + } +} + +/* + * ======== FlashProgram4X ======== + */ +uint32_t FlashProgram4X(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* construct structure containing all input arguments */ + flashProgramArgs.dataBuffer = pui8DataBuffer; + flashProgramArgs.sectorAddress = ui32Address; + flashProgramArgs.count = ui32Count; + + /* set the input vector */ + invecs[0].base = &flashProgramArgs; + invecs[0].len = sizeof(flashProgramArgs); + + /* set the output vector */ + uint32_t status = 0; + outvecs[0].base = &status; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashProgram4X command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_PROGRAM_4X, invecs, 1, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashProgram4X status code */ + return (status); + } +} + +/* + * ======== FlashSectorSizeGet ======== + */ +uint32_t FlashSectorSizeGet(void) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* set the output vector */ + uint32_t status = 0; + outvecs[0].base = &status; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashSectorSizeGet command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_SECTOR_SIZE_GET, invecs, 0, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashSectorSizeGet status code */ + return (status); + } +} + +/* + * ======== FlashSizeGet ======== + */ +uint32_t FlashSizeGet(void) +{ + /* if there is no PSA Connection, connect */ + if (spHandle <= 0) + { + FlashOpen(); + if (spHandle <= 0) + { + return (spHandle); + } + } + + /* set the output vector */ + uint32_t status = 0; + outvecs[0].base = &status; + outvecs[0].len = sizeof(uint32_t); + + /* call FlashSizeGet command */ + psa_status_t err = psa_call(spHandle, FLASH_SP_MSG_TYPE_FLASH_SIZE_GET, invecs, 0, outvecs, 1); + + if (err) + { + /* return PSA error code */ + return (err); + } + else + { + /* return FlashSizeGet status code */ + return (status); + } +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.h new file mode 100644 index 00000000..9d0d497f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_ns.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file FlashCC26X4_ns.h + * @brief Non-Secure Flash Client Interface for CC26X4 devices. + * + * The defined APIs are identical to the function calls in flash.c. This client + * interface allows the access to the Secure Flash Service. + * + * # Initialization # + * Users will need to call FlashOpen() once prior to any other function calls. + * FlashOpen() will only need to be called again if FlashClose() is called. + * + * # Error Codes # + * Typically the Flash Driver (flash.c) returns either a FAPI_STATUS code + * or a valid value greater than the FAPI_STATUS code range. FAPI_STATUS codes + * are positive and are defined below in FlashCC26X4_ns.h. The Non-Secure Flash + * Client Interface is responsible for interfacing with the Secure Partition + * Manager (SPM). Requests to the SPM may result in Platform Security + * Architecture (PSA) error codes. These error codes are referred to as + * PSA_ERROR codes. PSA_ERROR codes are negative values and are defined in + * "error.h". Due to the FAPI_STATUS and PSA_ERROR codes not overlapping, + * API's of the Non-Secure Flash Client Interface can dynamically return either + * value type. PSA_ERROR codes are considered higher priority and will take + * precedence. Therefore, if a PSA_ERROR occurs, a PSA_ERROR is returned. + * Otherwise, a valid Flash driver value will be returned. Each API will follow + * this guideline but please reference each API individually for specific + * return characteristics. + * + * # PSA_ERROR_PROGRAMMER_ERROR # + * A PSA_ERROR_PROGRAMMER_ERROR is a strict error code returned by the SPM. + * Once this error code is returned, the SPM will terminate the connection + * to the service. All subsequent requests to the service from the same client + * will not be processed and will continue to return a + * PSA_ERROR_PROGRAMMER_ERROR. The client must close the connection to the SPM + * and then re-establish the connection to continue. This can be accomplished + * in the Non-Secure Flash Client Interface by calling FlashClose() followed by + * FlashOpen(). In the Non-Secure Flash Client Interface, + * PSA_ERROR_PROGRAMMER_ERROR codes will primarily be returned due to requests + * trying to read from or write to secure memory regions. Please reference the + * PSA Firmware Framework specification for more details regarding the + * PSA_ERROR_PROGRAMMER_ERROR code. + * + * ============================================================================ + */ + +#ifndef ti_drivers_nvs_flash_FlashCC26X4_ns_H__ +#define ti_drivers_nvs_flash_FlashCC26X4_ns_H__ + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_nvmnw.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(cmsis/core/cmsis_compiler.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* *************************************************************************** */ +/* Values that can be returned from the API functions */ +/* *************************************************************************** */ +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed +#define FAPI_STATUS_ADDRESS_ERROR 0x00000005 // Operation failed +#define FAPI_STATUS_ADDRESS_ALIGN_ERROR 0x00000006 // addr alignment error +#define FAPI_STATUS_BANK_NUM_ERROR 0x00000007 // bank number error +#define FAPI_STATUS_NOSUPPORT_ERROR 0x00000008 // Flash API is not supported +#define FAPI_STATUS_UNPROTECT_ERROR 0x00000009 // can't unprotect for saved setting + +/*! + * @brief Initialize a PSA connection to the Secure Flash Service + * + * @pre None + * + * @return A value greater than 0 indicates the value of a successfuly + * established connection handle. On failure a PSA_ERROR code + * will be returned. + */ +int_fast16_t FlashOpen(void); + +/*! + * @brief End the PSA connection to the Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @return void + */ +void FlashClose(void); + +/*! + * @brief Call FlashProtectionGet API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @param[in] ui32SectorAddress The start address of the sector to protect. + * + * @return Returns the sector protection value (0 or 1) on success or FAPI_STATUS + * code on failure. If a PSA error occurs this will take precedence and + * a PSA_ERROR code will be returned instead. + */ +uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); + +/*! + * @brief Call FlashSectorErase API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @param[in] ui32SectorAddress The start address of the sector to erase. + * + * @return Returns an FAPI_STATUS status code based on status of erase operation. + * If a PSA error occurs this will take precedence and a PSA_ERROR code + * will be returned instead. + */ +uint32_t FlashSectorErase(uint32_t ui32SectorAddress); + +/*! + * @brief Call FlashProgram API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @param[in] pui8DataBuffer Pointer to the data to be programmed. + * @param[in] ui32Address Starting address in flash to be programmed. + * @param[in] ui32Count Number of bytes to be programmed. + * + * @return Returns an FAPI_STATUS status code based on status of flash operation. + * If a PSA error occurs this will take precedence and a PSA_ERROR code + * will be returned instead. + */ +uint32_t FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count); + +/*! + * @brief Call FlashProgram4X API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @param[in] pui8DataBuffer Pointer to the data to be programmed. + * @param[in] ui32Address Starting address in flash to be programmed. + * @param[in] ui32Count Number of bytes to be programmed. + * + * @return Returns an FAPI_STATUS status code based on status of flash operation. + * If a PSA error occurs this will take precedence and a PSA_ERROR code + * will be returned instead. + */ +uint32_t FlashProgram4X(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count); + +/*! + * @brief Call FlashSectorSizeGet API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @return Returns the size of Flash Sector on success or an FAPI_STATUS status + * code on failure. Values greater than FAPI_STATUS_UNPROTECT_ERROR will + * be considered a valid Flash Sector size. If a PSA error occurs this + * will take precedence and a PSA_ERROR code will be returned instead. + */ +uint32_t FlashSectorSizeGet(void); + +/*! + * @brief Call FlashSizeGet API using Secure Flash Service + * + * @pre FlashOpen() was called. + * + * @return Returns the size of Flash on success or an FAPI_STATUS status + * code on failure. Values greater than FAPI_STATUS_UNPROTECT_ERROR will + * be considered a valid Flash size. If a PSA error occurs this + * will take precedence and a PSA_ERROR code will be returned instead. + */ +uint32_t FlashSizeGet(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_nvs_flash_FlashCC26X4_ns_H__ */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.c new file mode 100644 index 00000000..d2360ea3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.c @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/* + * ======== FlashCC26X4_s.c ======== + */ +#include +#include "FlashCC26X4_s.h" + +#include /* Auto-generated header */ + +#include +#include +#include /* TI CMSE helper functions */ + +#include +#include DeviceFamily_constructPath(driverlib/flash.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +#include + +/*! + * @brief Process a PSA Command + * + * @pre psa_call() was called. + * + * @param[in] msg PSA message + * + * @return A zero status on success. + */ +__attribute__((noinline)) static psa_status_t FlashCC26X4_s_processPsaMsg(psa_msg_t *msg) +{ + struct FlashCC26X4_s_program flashProgramSecureArgs; + + uint32_t sectorAddress; + uint32_t output; + uintptr_t key; + + /* set default PSA Status */ + psa_status_t psaStatus = PSA_ERROR_PROGRAMMER_ERROR; + + switch (msg->type) + { + + case FLASH_SP_MSG_TYPE_PROTECTION_GET: + if ((msg->in_size[0] == sizeof(uint32_t)) && (msg->out_size[0] == sizeof(uint32_t))) + { + psa_read(msg->handle, 0, §orAddress, sizeof(uint32_t)); + + /* Non-secure callers have negative client ID */ + /* validate the sectorAddress to be read is Non-secure */ + if ((msg->client_id < 0) && (!cmse_has_unpriv_nonsecure_read_access((void *)sectorAddress, 0x4))) + { + break; + } + + output = FlashProtectionGet(sectorAddress); + psa_write(msg->handle, 0, &output, msg->out_size[0]); + psaStatus = PSA_SUCCESS; + } + break; + + case FLASH_SP_MSG_TYPE_SECTOR_ERASE: + if ((msg->in_size[0] == sizeof(uint32_t)) && (msg->out_size[0] == sizeof(uint32_t))) + { + psa_read(msg->handle, 0, §orAddress, sizeof(uint32_t)); + + /* Non-secure callers have negative client ID */ + /* validate the sectorAddress to be erased is Non-secure */ + if ((msg->client_id < 0) && + (!cmse_has_unpriv_nonsecure_rw_access((void *)sectorAddress, FlashSectorSizeGet()))) + { + break; + } + + /* Disable interrupts */ + key = HwiP_disable(); + output = HapiSectorErase(sectorAddress); + /* Re-enable the interrupts if required */ + HwiP_restore(key); + + psa_write(msg->handle, 0, &output, msg->out_size[0]); + psaStatus = PSA_SUCCESS; + } + break; + + case FLASH_SP_MSG_TYPE_PROGRAM: + case FLASH_SP_MSG_TYPE_PROGRAM_4X: + if ((msg->in_size[0] == sizeof(flashProgramSecureArgs)) && (msg->out_size[0] == sizeof(uint32_t))) + { + psa_read(msg->handle, 0, &flashProgramSecureArgs, sizeof(flashProgramSecureArgs)); + + /* Non-secure callers have negative client ID */ + /* check the dataBuffer address to ensure its not secure memory */ + /* check the sectorAddress to esnure the destination is not secure memory */ + if ((msg->client_id < 0) && + ((!cmse_has_unpriv_nonsecure_read_access(flashProgramSecureArgs.dataBuffer, + flashProgramSecureArgs.count)) || + (!cmse_has_unpriv_nonsecure_rw_access((void *)flashProgramSecureArgs.sectorAddress, + flashProgramSecureArgs.count)))) + { + break; + } + + /* Disable interrupts */ + key = HwiP_disable(); + output = HapiProgramFlash((uint8_t *)flashProgramSecureArgs.dataBuffer, + flashProgramSecureArgs.sectorAddress, + flashProgramSecureArgs.count); + /* Re-enable the interrupts if required */ + HwiP_restore(key); + + psa_write(msg->handle, 0, &output, msg->out_size[0]); + psaStatus = PSA_SUCCESS; + } + break; + + case FLASH_SP_MSG_TYPE_SECTOR_SIZE_GET: + if ((msg->out_size[0] == sizeof(uint32_t))) + { + output = FlashSectorSizeGet(); + psa_write(msg->handle, 0, &output, msg->out_size[0]); + psaStatus = PSA_SUCCESS; + } + break; + + case FLASH_SP_MSG_TYPE_FLASH_SIZE_GET: + if ((msg->out_size[0] == sizeof(uint32_t))) + { + output = FlashSizeGet(); + psa_write(msg->handle, 0, &output, msg->out_size[0]); + psaStatus = PSA_SUCCESS; + } + break; + + default: + /* Unknown message type */ + break; + } + + return (psaStatus); +} + +/*! + * @brief Main Secure Flash Service Loop + * + * @pre Secure Flash Service was started + * + * @param[in] param Optional startup parameters + * + * @return A zero status on success. + */ +void FlashCC26X4_s_main(void) +{ + uint32_t signals = 0; + psa_msg_t msg; + + while (1) + { + /* pend on next PSA message */ + signals = psa_wait(PSA_WAIT_ANY, PSA_BLOCK); + + if (signals & TI_FLASH_SERVICE_SIGNAL) + { + psa_get(TI_FLASH_SERVICE_SIGNAL, &msg); + + switch (msg.type) + { + case PSA_IPC_CONNECT: + psa_reply(msg.handle, PSA_SUCCESS); + break; + + case PSA_IPC_DISCONNECT: + psa_reply(msg.handle, PSA_SUCCESS); + break; + + default: + if (msg.type >= 0) + { + psa_reply(msg.handle, FlashCC26X4_s_processPsaMsg(&msg)); + } + else + { + psa_reply(msg.handle, PSA_ERROR_PROGRAMMER_ERROR); + } + break; + } + } + } + + return; +} diff --git a/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.h new file mode 100644 index 00000000..15d6e370 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/nvs/flash/FlashCC26X4_s.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*!***************************************************************************** + * @file FlashCC26X4_s.h + * @brief Secure Flash Service + * + * @anchor ti_drivers_nvs_FlashCC26X4_s_Overview + * # Overview + * The Secure Flash Service is used to access the flash driver when using + * TF-M configuration. + * + ******************************************************************************* + */ + +#ifndef ti_drivers_nvs_flash_FlashCC26X4_s__include +#define ti_drivers_nvs_flash_FlashCC26X4_s__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * message types >= 16 are reserved for + * non-standard message types begin here + */ +#define TI_SP_MSG_TYPE_USER 16 + +#define FLASH_SP_MSG_TYPE_PROTECTION_GET (TI_SP_MSG_TYPE_USER + 0) +#define FLASH_SP_MSG_TYPE_SECTOR_ERASE (TI_SP_MSG_TYPE_USER + 1) +#define FLASH_SP_MSG_TYPE_PROGRAM (TI_SP_MSG_TYPE_USER + 2) +#define FLASH_SP_MSG_TYPE_PROGRAM_4X (TI_SP_MSG_TYPE_USER + 3) +#define FLASH_SP_MSG_TYPE_SECTOR_SIZE_GET (TI_SP_MSG_TYPE_USER + 4) +#define FLASH_SP_MSG_TYPE_FLASH_SIZE_GET (TI_SP_MSG_TYPE_USER + 5) + +struct FlashCC26X4_s_program +{ + uint8_t *dataBuffer; + uint32_t sectorAddress; + uint32_t count; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_nvs_flash_FlashCC26X4_s__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/pdm/Codec1.c b/simplelink_lpf2/source/ti/drivers/pdm/Codec1.c new file mode 100644 index 00000000..e0b556d7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/Codec1.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2014-2022, Texas Instruments Incorporated + * + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell + * ("Utilize") this software subject to the terms herein. With respect to the + * foregoing patent license, such license is granted solely to the extent that + * any such patent is necessary to Utilize the software alone. The patent + * license shall not apply to any combinations which include this software, + * other than combinations with devices manufactured by or for TI + * ("TI Devices"). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce + * this license (including the above copyright notice and the disclaimer and + * (if applicable) source code license limitations below) in the documentation + * and/or other materials provided with the distribution + * + * Redistribution and use in binary form, without modification, are permitted + * provided that the following conditions are met: + * + * * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * + * * any redistribution and use are licensed by TI for use only with TI Devices. + * + * * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution + * of the source code are permitted provided that the following conditions are + * met: + * + * * any redistribution and use of the source code, including any resulting + * derivative works, are licensed by TI for use only with TI Devices. + * + * * any redistribution and use of any object code compiled from the source + * code and any resulting derivative works, are licensed by TI for use only + * with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its + * suppliers may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*********************************************************************************** + * INCLUDES + */ +#include +#include + +/************************************************************************************************** + * Global Variables + */ + +static int16_t Codec1_pvEnc; +static int16_t Codec1_pvDec; +static int8_t Codec1_siEnc; +static int8_t Codec1_siDec; + +static const uint16_t Codec1_stepsizeLut[89] = {7, 8, 9, 10, 11, 12, 13, 14, 16, 17, + 19, 21, 23, 25, 28, 31, 34, 37, 41, 45, + 50, 55, 60, 66, 73, 80, 88, 97, 107, 118, + 130, 143, 157, 173, 190, 209, 230, 253, 279, 307, + 337, 371, 408, 449, 494, 544, 598, 658, 724, 796, + 876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066, + 2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358, + 5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899, + 15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767}; + +static const int8_t Codec1_IndexLut[16] = {-1, -1, -1, -1, 2, 4, 6, 8, -1, -1, -1, -1, 2, 4, 6, 8}; + +/* + * ======== Codec1_encodeSingle ======== + */ +uint8_t Codec1_encodeSingle(int16_t audSample) +{ + // Difference between samples and previous predicted value. + // This difference will be encoded + int16_t difference = audSample - Codec1_pvEnc; + // Final nibble value + uint8_t tic1_nibble_4bits = 0; + // Step size to quantisize the difference, + int16_t step = Codec1_stepsizeLut[Codec1_siEnc]; + // cumulated difference from samples. + int16_t cum_diff = step >> 3; + + if (difference < 0) + { + tic1_nibble_4bits = 8; + difference = -difference; + } + + if (difference >= step) + { + tic1_nibble_4bits |= 4; + difference -= step; + cum_diff += step; + } + step >>= 1; + if (difference >= step) + { + tic1_nibble_4bits |= 2; + difference -= step; + cum_diff += step; + } + step >>= 1; + if (difference >= step) + { + tic1_nibble_4bits |= 1; + cum_diff += step; + } + + if (tic1_nibble_4bits & 8) + { + if (Codec1_pvEnc < (-32768 + cum_diff)) + { + (Codec1_pvEnc) = -32768; + } + else + { + Codec1_pvEnc -= cum_diff; + } + } + else + { + if (Codec1_pvEnc > (0x7fff - cum_diff)) + { + (Codec1_pvEnc) = 0x7fff; + } + else + { + Codec1_pvEnc += cum_diff; + } + } + + Codec1_siEnc += Codec1_IndexLut[tic1_nibble_4bits]; + + if (Codec1_siEnc < 0) + { + Codec1_siEnc = 0; + } + else if (Codec1_siEnc > 88) + { + Codec1_siEnc = 88; + } + + return tic1_nibble_4bits; +} + +/* + * ======== Codec1_decodeSingle ======== + */ +int16_t Codec1_decodeSingle(uint8_t nibble_4bits) +{ + int16_t step = Codec1_stepsizeLut[Codec1_siDec]; + int16_t cum_diff = step >> 3; + + Codec1_siDec += Codec1_IndexLut[nibble_4bits]; + if (Codec1_siDec < 0) + { + Codec1_siDec = 0; + } + else if (Codec1_siDec > 88) + { + Codec1_siDec = 88; + } + + if (nibble_4bits & 4) + { + cum_diff += step; + } + if (nibble_4bits & 2) + { + cum_diff += step >> 1; + } + if (nibble_4bits & 1) + { + cum_diff += step >> 2; + } + + if (nibble_4bits & 8) + { + if (Codec1_pvDec < (-32767 + cum_diff)) + { + (Codec1_pvDec) = -32767; + } + else + { + Codec1_pvDec -= cum_diff; + } + } + else + { + if (Codec1_pvDec > (0x7fff - cum_diff)) + { + (Codec1_pvDec) = 0x7fff; + } + else + { + Codec1_pvDec += cum_diff; + } + } + return Codec1_pvDec; +} + +/* + * ======== Codec1_encodeBuff ======== + */ +uint8_t Codec1_encodeBuff(uint8_t *dst, int16_t *src, int16_t srcSize, int8_t *si, int16_t *pv) +{ + Codec1_pvEnc = *pv; + Codec1_siEnc = *si; + int16_t *end = (src + srcSize); + int8_t len = 0; + + while (src < end) + { + // encode a pcm value from input buffer + uint8_t nibble = Codec1_encodeSingle(*src++); + + nibble |= (Codec1_encodeSingle(*src++) << 4); + + *dst++ = nibble; + + len++; + } + + *pv = Codec1_pvEnc; + *si = Codec1_siEnc; + return len; +} + +/* + * ======== Codec1_decodeBuff ======== + */ +void Codec1_decodeBuff(int16_t *dst, uint8_t *src, unsigned srcSize, int8_t *si, int16_t *pv) +{ + Codec1_pvDec = *pv; + Codec1_siDec = *si; + + // calculate pointers to iterate output buffer + int16_t *out = dst; + int16_t *end = out + (srcSize >> 1); + + while (out < end) + { + // get byte from src + uint8_t nibble = *src; + *out++ = Codec1_decodeSingle((nibble & 0xF)); // decode value and store it + nibble >>= 4; // use high nibble of byte + nibble &= 0xF; // use high nibble of byte + *out++ = Codec1_decodeSingle(nibble); // decode value and store it + ++src; // move on a byte for next sample + } + + *pv = Codec1_pvDec; + *si = Codec1_siDec; +} diff --git a/simplelink_lpf2/source/ti/drivers/pdm/Codec1.h b/simplelink_lpf2/source/ti/drivers/pdm/Codec1.h new file mode 100644 index 00000000..9dcabb62 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/Codec1.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2014-2019, Texas Instruments Incorporated + * + * All rights reserved not granted herein. + * + * Limited License. + * + * Texas Instruments Incorporated grants a world-wide, royalty-free, + * non-exclusive license under copyrights and patents it now or hereafter + * owns or controls to make, have made, use, import, offer to sell and sell + * ("Utilize") this software subject to the terms herein. With respect to the + * foregoing patent license, such license is granted solely to the extent that + * any such patent is necessary to Utilize the software alone. The patent + * license shall not apply to any combinations which include this software, + * other than combinations with devices manufactured by or for TI + * ("TI Devices"). No hardware patent is licensed hereunder. + * + * Redistributions must preserve existing copyright notices and reproduce + * this license (including the above copyright notice and the disclaimer and + * (if applicable) source code license limitations below) in the documentation + * and/or other materials provided with the distribution + * + * Redistribution and use in binary form, without modification, are permitted + * provided that the following conditions are met: + * + * * No reverse engineering, decompilation, or disassembly of this software is + * permitted with respect to any software provided in binary form. + * + * * any redistribution and use are licensed by TI for use only with TI Devices. + * + * * Nothing shall obligate TI to provide you with source code for the software + * licensed and provided to you in object code. + * + * If software source code is provided to you, modification and redistribution + * of the source code are permitted provided that the following conditions are + * met: + * + * * any redistribution and use of the source code, including any resulting + * derivative works, are licensed by TI for use only with TI Devices. + * + * * any redistribution and use of any object code compiled from the source + * code and any resulting derivative works, are licensed by TI for use only + * with TI Devices. + * + * Neither the name of Texas Instruments Incorporated nor the names of its + * suppliers may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * DISCLAIMER. + * + * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** ============================================================================ + * @file Codec1.h + * + * @brief Implementation of TI Codec Type 1 (IMA ADPCM) encoding and decoding. + * + * This module provides functions for encoding and decoding data using ADPCM encoding. + * + * ============================================================================ + */ + +#ifndef ti_drivers_pdm_Codec1__include +#define ti_drivers_pdm_Codec1__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief This routine encodes one int16 sample with TI Codec Type 1. + * + * @param audSample The audtion sample to encode + * + * @return The encoded result as a 4-bit nibble + */ +extern uint8_t Codec1_encodeSingle(int16_t audSample); + +/*! + * @brief This routine decode a 4-bit nibble sample to a uint16 PCM audio sample. + * + * @param nibble_4bits A 4-bit nibble to decode + * + * @return The decoded value as a 16-bit PCM sample + */ +extern int16_t Codec1_decodeSingle(uint8_t nibble_4bits); + +/*! + * @brief This routine encode a buffer with TI codec Type 1. + * + * @param dst Pointer to the buffer where encoding result will be written to + * + * @param src Pointer to the buffer that should be encoded. + * Must be a multiple of 4 bytes + * + * @param srcSize The number of samples (int16) in the src buffer. + * Must be a multiple of 2. + * + * @param si Pointer to the current step index + * + * @param pv Pointer to the current predicted-value + * + * @return Number of bytes written to the destination buffer + */ +extern uint8_t Codec1_encodeBuff(uint8_t *dst, int16_t *src, int16_t srcSize, int8_t *si, int16_t *pv); + +/*! + * @brief This routine decodes a buffer with TI codec Type 1. + * + * @param dst Pointer to the buffer where decoded result will be written to + * + * @param src Pointer to the buffer that should be decoded. + * Must be a multiple of 4 bytes + * + * @param srcSize Number of byte that will be generated by + * the encoder (4* (src buffer size in byte)) + * + * @param si Pointer to the current step index + * + * @param pv Pointer to the current predicted-value + */ +extern void Codec1_decodeBuff(int16_t *dst, uint8_t *src, unsigned srcSize, int8_t *si, int16_t *pv); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_pdm_Codec1__include */ diff --git a/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.c b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.c new file mode 100644 index 00000000..e63cc47d --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.c @@ -0,0 +1,1284 @@ +/* + * Copyright (c) 2015-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/********************************************************************* + * INCLUDES + */ +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/********************************************************************* + * LOCAL DEFINES + */ + +/*! Use both word clock phases to get continuous PDM stream */ +#define PDM_NUM_OF_CHANNELS 2 + +/*! PDM block size in number of 16bit samples. Each PDM sample actually consumes + * 64 bits, assuming ankHz sampling rate. */ +#define PDM_BLOCK_SIZE_IN_SAMPLES_8K 128 + +/*! PDM block size in number of 16bit samples. Each PDM sample actually consumes + * 64 bits, assuming ankHz sampling rate. */ +#define PDM_BLOCK_SIZE_IN_SAMPLES_16K 64 + +/*! Number of GPIOs used. */ +#define PDM_NUMBER_OF_PINS 1 // Only one pin to control microphone power + +/*! Number of compressed bytes produced by each PDM->PCM conversion and compression */ +#define PDMCC26XX_COMPR_ITER_OUTPUT_SIZE 16 + +/*! Number of uncompressed bytes produced by each PDM->PCM conversion and memcpy */ +#define PDMCC26XX_CPY_ITER_OUTPUT_SIZE 64 + +/*! This value defines how many samples are discarded at minimum each time the PDM stream starts. + * The first few samples that are processed by the driver will not be representative of their actual value + * as the decimation filter has not sufficiently updated its internal state. A value < 8 is not reccomended, as the + * distortion of the signal is greatest there. */ +#define PDM_DECIMATION_STARTUP_DELAY_IN_SAMPLES 32 + +/*! PDM sample size. Although there are 32 bits per sample at 16kHz we need to + * set it to 16 as part of the PDMCC26XX module configuration. */ +#define PDM_SAMPLE_SIZE 16 // 24 + +/* Events handled in the PDM task */ +/*! PDM event set in the callback from the PDMCC26XX driver every time a block + * is ready for PDM2PCM conversion. */ +#define PDM_EVT_BLK_RDY Event_Id_00 + +/*! PDM event set to kick off stream from PDM thread context. + * */ +#define PDM_EVT_START Event_Id_01 + +/*! PDM event set in PDMCC26XX_stopStream that synchronously stops the I2S stream. + This synchronous event is needed to make sure we properly deallocate all memory + passed between the I2S module and the PDM driver */ +#define PDM_EVT_STOP Event_Id_02 + +/*! PDM event set in the callback from the PDMCC26XX driver in case an error + * occurs. */ +#define PDM_EVT_BLK_ERROR Event_Id_03 + +/*! PDM event set in the callback from the PDMCC26XX driver when the application + * calls ::PDMCC26XX_close(). */ +#define PDM_EVT_CLOSE Event_Id_04 + +/*! PDM event that causes the driver to drop the current PCMBuffer and throw samples + * because the I2S module could not get an empty buffer. + */ +#define PDM_EVT_I2S_DATA_DROPPED Event_Id_05 + +/* PDM rollback vector bit masks. Each bit mask corresponds to an action that PDMCC26XX_rollbackDriverInitialisation() + * commits */ +/*! Reverses the driver being set to open in the object */ +#define PDM_ROLLBACK_OPEN 1 << 0 +/*! Reverses the allocation of the decimationState */ +#define PDM_ROLLBACK_DECIMATION_STATE 1 << 1 +/*! Reverses the allocation of the activePcmBuffer */ +#define PDM_ROLLBACK_ACTIVE_PCM_BUFFER 1 << 2 +/*! Reverses the opening of the I2S driver */ +#define PDM_ROLLBACK_I2S_DRIVER 1 << 3 +/*! Reverses the allocation of the PDM pin in the PIN driver */ +#define PDM_ROLLBACK_PIN 1 << 4 + +/********************************************************************* + * TYPEDEFS + */ + +/*! Struct that contains a PCM queue element and a pointer to the data buffer it is responsible for */ +typedef struct +{ + Queue_Elem queueElement; /*!< Queue element */ + PDMCC26XX_pcmBuffer *pBufferPCM; /*!< Pointer to a ::PDMCC26XX_pcmBuffer */ +} PDMCC26XX_queueNodePCM; + +/*! PDM sample type. Prepared for future support of 24 sample size. + * @note Internal use only */ +#if (defined PDM_SAMPLE_SIZE) && (PDM_SAMPLE_SIZE == 24) +typedef __packed struct +{ + uint8_t pdmSampleLsb; + uint16_t pdmSampleMsb; +} pdmSample; +#elif (defined PDM_SAMPLE_SIZE) && (PDM_SAMPLE_SIZE == 16) +typedef uint16_t pdmSample; +#else + #error Unsupported PDM samples size (16 or 24) +#endif +/*! PCM sample type. @note Internal use only */ +#if (defined PCM_SAMPLE_SIZE) && (PCM_SAMPLE_SIZE == 16) +typedef int16_t pcmSample; +#else + #error Unsupported PCM samples size (16) +#endif + +/********************************************************************* + * LOCAL VARIABLES + */ + +/*! PDMCC26XX_Config struct defined in the board file */ +extern const PDMCC26XX_Config PDMCC26XX_config[]; + +/*! PDMCC26XX_I2S_Config struct defined in the board file */ +extern const PDMCC26XX_I2S_Config PDMCC26XX_I2S_config[]; + +/* PDM Task Configuration */ +Task_Struct pdmTask; +Char pdmTaskStack[PDM_TASK_STACK_SIZE]; + +/* Keep track of compression variables */ +PDMCC26XX_metaData metaDataForNextFrame = {0}; + +Queue_Struct pcmMsgReady; +Queue_Handle pcmMsgReadyQueue; + +Event_Struct sPDMEvents; +Event_Handle pdmEvents; + +/* This semaphore synchronises calls to PDMCC26XX_startStream, PDMCC26XX_stopStream, PDMCC26XX_open, and PDMCC26XX_close + * between the application and the driver */ +static SemaphoreP_Struct synchronisationSemaphore; + +static PDMCC26XX_Handle pdmHandle = NULL; + +PDMCC26XX_queueNodePCM *activePcmBuffer; + +PDMCC26XX_StreamNotification streamNotification = {.arg = NULL, .status = PDMCC26XX_STREAM_IDLE}; + +volatile uint32_t droppedPdmBlockCount = 0; + +static PDMCC26XX_I2S_StreamNotification pdmStream; +static PDMCC26XX_I2S_Handle i2sHandle; + +/* Gain coefficient of the first filter stage. We cannot make it part of the object + * as the default filter coefficients must be able to encode a pointer to the variable + * in the first entry and the location of the object is not known within this compilation + * unit at compile time. + */ +static int32_t gainCoefficient; + +/********************************************************************* + * CONSTANTS + */ + +/* Default filter coefficients. Includes configurable gain setting in first + * filter stage. In order to allow for dynamic gain control, the first coefficient + * may be a pointer to a RAM (!) address. The value at that address is then used + * as initial gain coeffiencient. The default filter points to a coeffiecient + * configured via PDMCC26XX_Params.defaultFilterGain. + */ +static const int32_t PDMCC26XX_aBqCoeffs[] = { + //--v-- Adjust overall gain by changing this coefficient + (int32_t)(&gainCoefficient), + 0, + -1024, + -1356, + 342, // DC-notch, halfband LP filter (@32 kHz) + 200, + 789, + 934, + -994, + 508, + 538, + 381, + 944, + -519, + 722, + 732, + 124, + 987, + -386, + 886, + 763, + 11, + 1014, + -386, + 886, + 0, // Terminate first filter + // Insert optional second filter here (@16 kHz). Some examples: + // 1147,-1516, 522, -1699, 708, // +5dB peak filter (F0=500 Hz, BW=3 octaves) + // 1313, -565, -6, -725, 281, // +5dB peak filter (F0=2.5 kHz, BW=2 octaves) + // 1335, 532, -66, 694, 225, // +5 dB peak filter (F0=5.5 kHz, BW=1 octave) + 0, // Terminate second filter +}; + +const PDMCC26XX_Params PDMCC26XX_defaultParams = {.callbackFxn = NULL, + .decimationFilter = PDMCC26XX_aBqCoeffs, + .decimationFilterStateSize = sizeof(uint32_t) * (6 + 5 * 2), + .defaultFilterGain = PDMCC26XX_GAIN_6, + .micPowerActiveHigh = true, + .applyCompression = true, + .startupDelayWithClockInSamples = 0, + .retBufSizeInBytes = 260, + .mallocFxn = NULL, + .freeFxn = NULL, + .pcmSampleRate = PDMCC26XX_PCM_SAMPLE_RATE_16K, + .pdmBufferQueueDepth = MINIMUM_PDM_BUFFER_QUEUE_DEPTH, + .custom = (uintptr_t)NULL}; + +/* Lookup table of pdm block sizes. Use PDMCC26XX_PcmSampleRate as index */ +const uint8_t pdmBlockSizeLut[] = { + PDM_BLOCK_SIZE_IN_SAMPLES_16K, + PDM_BLOCK_SIZE_IN_SAMPLES_8K, +}; + +/********************************************************************* + * LOCAL FUNCTIONS + */ +static void PDMCC26XX_taskFxn(UArg a0, UArg a1); +static void PDMCC26XX_initIO(PDMCC26XX_Handle handle); +static void PDMCC26XX_finalizeIO(PDMCC26XX_Handle handle); +static void PDMCC26XX_setPcmBufferReady(PDMCC26XX_Handle handle, + PDMCC26XX_queueNodePCM *pcmBuffer, + PDMCC26XX_I2S_BufferRequest *bufReq); +static PDMCC26XX_queueNodePCM *PDMCC26XX_getNewPcmBuffer(PDMCC26XX_Handle handle); +static void PDMCC26XX_i2sCallbackFxn(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_StreamNotification *notification); +static void PDMCC26XX_rollbackDriverInitialisation(PDMCC26XX_Handle handle, uint32_t rollbackVector); +static inline uint32_t PDMCC26XX_maxUInt32(uint32_t a, uint32_t b); + +/********************************************************************* + * EXTERNAL FUNCTIONS + */ +extern uint8_t tic1_EncodeBuff(uint8_t *dst, int16_t *src, int16_t srcSize, int8_t *si, int16_t *pv); +extern bool pdm2pcm16k(const void *pIn, uint32_t *pState, const int32_t *pBqCoeffs, int16_t *pOut); +extern bool pdm2pcm8k(const void *pIn, uint32_t *pState, const int32_t *pBqCoeffs, int16_t *pOut); + +/********************************************************************* + * PUBLIC FUNCTIONS + */ +void PDMCC26XX_init(PDMCC26XX_Handle handle); +PDMCC26XX_Handle PDMCC26XX_open(PDMCC26XX_Params *params); +void PDMCC26XX_close(PDMCC26XX_Handle handle); +bool PDMCC26XX_startStream(PDMCC26XX_Handle handle); +bool PDMCC26XX_stopStream(PDMCC26XX_Handle handle); +bool PDMCC26XX_requestBuffer(PDMCC26XX_Handle handle, PDMCC26XX_BufferRequest *bufferRequest); + +/* + * ======== PDMCC26XX_init ======== + * @pre Function assumes that it is called *once* on startup before BIOS init + * + * @param handle handle to the PDM object + */ +void PDMCC26XX_init(PDMCC26XX_Handle handle) +{ + /* Locals */ + PDMCC26XX_Object *object; + PDMCC26XX_HWAttrs const *pdmCC26XXHWAttrs; + Task_Params taskParams; + + /* Set local reference to return to callers */ + pdmHandle = handle; + + /* Get object for this handle */ + object = handle->object; + pdmCC26XXHWAttrs = handle->hwAttrs; + + /* Mark the objects as available */ + object->isOpen = false; + + /* Then initialize I2S driver */ + i2sHandle = (PDMCC26XX_I2S_Handle) & (PDMCC26XX_I2S_config); + PDMCC26XX_I2S_init(i2sHandle); + + /* Configure task */ + Task_Params_init(&taskParams); + taskParams.stack = pdmTaskStack; + taskParams.stackSize = PDM_TASK_STACK_SIZE; + taskParams.priority = pdmCC26XXHWAttrs->taskPriority; + + /* Construct task */ + Task_construct(&pdmTask, PDMCC26XX_taskFxn, &taskParams, NULL); +} + +/* + * ======== PDMCC26XX_open ======== + * @brief Function for opening the PDM driver on CC26XX devices + * + * @param params Parameters needed to configure the driver + * + * @return handle to the opened PDM driver + */ +PDMCC26XX_Handle PDMCC26XX_open(PDMCC26XX_Params *params) +{ + PDMCC26XX_Handle handle; + PDMCC26XX_Object *object; + PDMCC26XX_I2S_Params i2sParams = {0}; + + Assert_isTrue(params, NULL); + Assert_isTrue(params->callbackFxn, NULL); + Assert_isTrue(params->mallocFxn, NULL); + Assert_isTrue(params->freeFxn, NULL); + Assert_isTrue((params->retBufSizeInBytes - PCM_METADATA_SIZE) >= + (params->applyCompression ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE : PDMCC26XX_CPY_ITER_OUTPUT_SIZE), + NULL); + Assert_isTrue(params->pdmBufferQueueDepth >= MINIMUM_PDM_BUFFER_QUEUE_DEPTH, NULL); + + /* Get handle for this driver instance */ + handle = pdmHandle; + /* Get the pointer to the object */ + object = handle->object; + + /* Disable preemption while checking if the PDM is open. */ + uint32_t key = HwiP_disable(); + /* Check if the PDM is open already with the base addr. */ + if (object->isOpen == true) + { + HwiP_restore(key); + + return (NULL); + } + + /* Mark the handle as being used */ + object->isOpen = true; + HwiP_restore(key); + + /* Initialize the PDM object */ + object->callbackFxn = params->callbackFxn; + object->micPowerActiveHigh = params->micPowerActiveHigh; + object->applyCompression = params->applyCompression; + object->startupDelayWithClockInSamples = params->startupDelayWithClockInSamples; + object->streamStarted = false; + object->streamNotification = &streamNotification; + object->mallocFxn = params->mallocFxn; + object->freeFxn = params->freeFxn; + object->pdm2pcmFxn = params->pcmSampleRate == PDMCC26XX_PCM_SAMPLE_RATE_16K ? pdm2pcm16k : pdm2pcm8k; + object->retBufSizeInBytes = params->retBufSizeInBytes; + object->pcmBufferSizeInBytes = params->retBufSizeInBytes - PCM_METADATA_SIZE; + object->decimationFilter = params->decimationFilter ? params->decimationFilter : PDMCC26XX_aBqCoeffs; + gainCoefficient = params->defaultFilterGain; + + object->decimationFilterStateSize = params->decimationFilterStateSize; + object->decimationFilterState = object->mallocFxn(params->decimationFilterStateSize); + if (!object->decimationFilterState) + { + /* We didn't manage to allocate enough space on the heap for the decimationFilterState. + * Exit with return value NULL to prevent the driver running with decimationFilterState == NULL + */ + PDMCC26XX_rollbackDriverInitialisation(handle, PDM_ROLLBACK_OPEN); + } + + /* Get first buffer for PCM data so that we don't get NULL + * pointer exception. + */ + activePcmBuffer = PDMCC26XX_getNewPcmBuffer(pdmHandle); + if (!activePcmBuffer) + { + /* We didn't manage to allocate enough space on the heap for the activePcmBuffer. + * Exit with return value NULL to prevent the driver running with activePcmBuffer == NULL + */ + PDMCC26XX_rollbackDriverInitialisation(handle, PDM_ROLLBACK_OPEN | PDM_ROLLBACK_DECIMATION_STATE); + + return (NULL); + } + + i2sParams.requestMode = PDMCC26XX_I2S_CALLBACK_MODE; + i2sParams.requestTimeout = BIOS_WAIT_FOREVER; + i2sParams.callbackFxn = PDMCC26XX_i2sCallbackFxn; + i2sParams.mallocFxn = params->mallocFxn; + i2sParams.freeFxn = params->freeFxn; + i2sParams.blockCount = params->pdmBufferQueueDepth; + i2sParams.currentStream = &pdmStream; + i2sParams.blockSizeInSamples = pdmBlockSizeLut[params->pcmSampleRate]; + + /* Init IOs */ + PDMCC26XX_initIO(handle); + + /* Then open the interface with these parameters */ + i2sHandle = PDMCC26XX_I2S_open(i2sHandle, &i2sParams); + if (!i2sHandle) + { + PDMCC26XX_rollbackDriverInitialisation(pdmHandle, + (PDM_ROLLBACK_OPEN | PDM_ROLLBACK_DECIMATION_STATE | + PDM_ROLLBACK_ACTIVE_PCM_BUFFER | PDM_ROLLBACK_PIN)); + + return (NULL); + } + + /* Construct ready and available queues */ + Queue_construct(&pcmMsgReady, NULL); + pcmMsgReadyQueue = Queue_handle(&pcmMsgReady); + + return (handle); +} + +/* + * ======== PDMCC26XX_close ======== + * @brief Function for closing the PDM driver on CC26XX devices + * + * @param handle Handle to the PDM object + */ +void PDMCC26XX_close(PDMCC26XX_Handle handle) +{ + Assert_isTrue(handle, NULL); + + /* Post close event to shutdown synchronously and prevent resetting settings and datastructures in the middle of a + * block ready event */ + Event_post(pdmEvents, PDM_EVT_CLOSE); + + /* Wait for PDM_EVT_CLOSE to take effect */ + SemaphoreP_pend(&synchronisationSemaphore, BIOS_WAIT_FOREVER); +} + +/* + * ======== PDMCC26XX_startStream ======== + * @brief Function for starting a PDM stream + * + * @param handle Handle to the PDM object + * + * @pre ::PDMCC26XX_open() must be called first and there must not already be a stream in progress. + * + * @return true if stream started, false if something went wrong. + */ +bool PDMCC26XX_startStream(PDMCC26XX_Handle handle) +{ + PDMCC26XX_Object *object; + PDMCC26XX_HWAttrs const *hwAttrs; + + Assert_isTrue(handle, NULL); + + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if a transfer is in progress */ + uint32_t key = HwiP_disable(); + if (object->streamStarted) + { + HwiP_restore(key); + + /* Stream is in progress */ + return (false); + } + + /* Reset decimation states */ + memset(object->decimationFilterState, 0x00, object->decimationFilterStateSize); + + /* Free ready elements*/ + while (!Queue_empty(pcmMsgReadyQueue)) + { + PDMCC26XX_queueNodePCM *readyNode = Queue_dequeue(pcmMsgReadyQueue); + /* Free up memory used for PCM data buffer */ + object->freeFxn(readyNode->pBufferPCM, object->retBufSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(readyNode, sizeof(PDMCC26XX_queueNodePCM)); + } + + /* Reset compression data */ + metaDataForNextFrame.seqNum = 0; + metaDataForNextFrame.si = 0; + metaDataForNextFrame.pv = 0; + + /* Then start stream */ + if (PDMCC26XX_I2S_startStream(i2sHandle)) + { + /* Power microphone --> It typically requires some startup time */ + GPIO_write(hwAttrs->micPower, (object->micPowerActiveHigh) ? 1 : 0); + + /* The starting of stream succeeded, don't allow the device to enter + * standby. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Make sure to flag that a stream is now active */ + object->streamStarted = true; + + HwiP_restore(key); + + /* Let thread prepare to throw the first PDM_DECIMATION_STARTUP_DELAY_IN_SAMPLES samples */ + Event_post(pdmEvents, PDM_EVT_START); + + return true; + } + else + { + /* If the starting of stream failed, return false*/ + HwiP_restore(key); + return false; + } +} + +/* + * ======== PDMCC26XX_stopStream ======== + * @brief Function for stopping a PDM stream + * + * @param handle Handle to the PDM object + * + * @pre ::PDMCC26XX_startStream must have been called first. + * + * @return true if stream stopped correctly, false if something went wrong. + */ +bool PDMCC26XX_stopStream(PDMCC26XX_Handle handle) +{ + PDMCC26XX_Object *object; + + Assert_isTrue(handle, NULL); + + /* Get the pointer to the object */ + object = handle->object; + + /* Disable preemption while checking if a transfer is in progress */ + uint32_t key = HwiP_disable(); + if (!(object->streamStarted)) + { + HwiP_restore(key); + + /* Stream is not in progress */ + return (false); + } + HwiP_restore(key); + + /* Post event to synchronously shut down the stream. */ + Event_post(pdmEvents, PDM_EVT_STOP); + + /* Wait for PDM_EVT_STOP to take effect */ + SemaphoreP_pend(&synchronisationSemaphore, BIOS_WAIT_FOREVER); + + return true; +} + +/* + * ======== PDMCC26XX_Params_init ======== + * @brief Function for initialising a PDMCC26XX_Params instance to its default value + * + * @param params Pointer to a set of uninitialised params + * + */ +void PDMCC26XX_Params_init(PDMCC26XX_Params *params) +{ + *params = PDMCC26XX_defaultParams; +} + +/********************************************************************* + * @fn PDMCC26XX_taskFxn + * + * @brief PDM task function which is processing the PDM events from the + * driver (e.g. callback). + * + * @param none + * + * @return none + */ +static void PDMCC26XX_taskFxn(UArg a0, UArg a1) +{ + Event_Params eventParams; + PDMCC26XX_Object *object = pdmHandle->object; + PDMCC26XX_HWAttrs const *hwAttrs = pdmHandle->hwAttrs; + uint32_t events = 0; + int16_t tempPcmBuf[32] = {0}; + uint32_t throwAwayCount = 0; /* Number of bytes the driver should drop from the processed PCM data stream */ + uint32_t byteCount = 0; /* Index of the PCMBuffer currently being filled specifying how many bytes have been filled + */ + uint32_t currTempBufIndex = 0; /* Index of the tempPcmBuf specifying how many bytes have been filled */ + bool pcmBufferFull = false; + bool tempBufActive = false; + PDMCC26XX_I2S_BufferRequest bufferRequest = {0}; + PDMCC26XX_I2S_BufferRelease bufferRelease = {0}; + + /* Semaphore and event for the task */ + Event_Params_init(&eventParams); + Event_construct(&sPDMEvents, &eventParams); + pdmEvents = Event_handle(&sPDMEvents); + + /* Setup semaphore */ + SemaphoreP_constructBinary(&synchronisationSemaphore, 0); + + /* Loop forever */ + while (true) + { + events = Event_pend(pdmEvents, + Event_Id_NONE, + (PDM_EVT_BLK_RDY | PDM_EVT_START | PDM_EVT_STOP | PDM_EVT_BLK_ERROR | PDM_EVT_CLOSE | + PDM_EVT_I2S_DATA_DROPPED), + BIOS_WAIT_FOREVER); + + if (events & PDM_EVT_STOP) + { + + if (!PDMCC26XX_I2S_stopStream(i2sHandle)) + { + /* We failed to stop!! */ + object->streamStarted = true; + } + else + { + /* Make sure to flag that a stream is no longer active */ + object->streamStarted = false; + + /* Allow system to enter standby again */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* Unpower microphone */ + GPIO_write(hwAttrs->micPower, (object->micPowerActiveHigh) ? 0 : 1); + } + + SemaphoreP_post(&synchronisationSemaphore); + } + + if (events & PDM_EVT_CLOSE) + { + /* Move unused ready elements to available queue */ + while (!Queue_empty(pcmMsgReadyQueue)) + { + PDMCC26XX_queueNodePCM *readyNode = Queue_dequeue(pcmMsgReadyQueue); + /* Free up memory used for PCM data buffer */ + object->freeFxn(readyNode->pBufferPCM, object->retBufSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(readyNode, sizeof(PDMCC26XX_queueNodePCM)); + } + Queue_destruct(&pcmMsgReady); + + /* + * Deallocate the activePcmBuffer, close down the I2S driver, release the pins back to the PIN driver, and + * set the PDM driver to closed. + */ + PDMCC26XX_rollbackDriverInitialisation(pdmHandle, + (PDM_ROLLBACK_OPEN | PDM_ROLLBACK_DECIMATION_STATE | + PDM_ROLLBACK_ACTIVE_PCM_BUFFER | PDM_ROLLBACK_I2S_DRIVER | + PDM_ROLLBACK_PIN)); + + /* Cancel all other queued events. After closed is called, we don't want the driver to do anything else + * without being reopened. */ + events = 0; + + SemaphoreP_post(&synchronisationSemaphore); + } + + if (events & PDM_EVT_START) + { + + pcmBufferFull = false; + byteCount = 0; + tempBufActive = false; + currTempBufIndex = 0; + + /* Some microphones require a startup delay with clock applied. The + * throw counter is used for this. + */ + if (object->applyCompression) + { + /* If compression is enabled, the throwAwayCount is decremented + * with respect to compressed data output. This number is the half + * of the number of samples: + */ + throwAwayCount = PDMCC26XX_maxUInt32(PDM_DECIMATION_STARTUP_DELAY_IN_SAMPLES / 2, + object->startupDelayWithClockInSamples / 2); + } + else + { + /* If compression is disabled, the throwAwayCount is decremented + * with respect to raw data, but in bytes not samples. Each sample + * is two bytes and the throwAwayCount is operating + * in bytes, this gives us: + */ + throwAwayCount = PDMCC26XX_maxUInt32(PDM_DECIMATION_STARTUP_DELAY_IN_SAMPLES * 2, + object->startupDelayWithClockInSamples * 2); + } + } + + if (events & PDM_EVT_BLK_ERROR) + { + /* Notify caller of error */ + streamNotification.status = PDMCC26XX_STREAM_ERROR; + object->callbackFxn(pdmHandle, &streamNotification); + events &= ~PDM_EVT_BLK_ERROR; + } + + if (events & PDM_EVT_I2S_DATA_DROPPED) + { + uint32_t key = HwiP_disable(); + /* The total number of PCM bytes that were dropped from the system. Includes those in the blocks dropped + * by the I2S module and those already in the PCM buffer + */ + uint32_t pcmBytesDropped = byteCount + droppedPdmBlockCount * (object->applyCompression + ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE + : PDMCC26XX_CPY_ITER_OUTPUT_SIZE); + droppedPdmBlockCount = 0; + + HwiP_restore(key); + + /* Throw away enough PCM bytes to synchronise the PDM data stream with the PCMBuffer sequence number */ + if (pcmBytesDropped != object->pcmBufferSizeInBytes) + { + throwAwayCount += object->pcmBufferSizeInBytes - (pcmBytesDropped % object->pcmBufferSizeInBytes); + } + else + { + throwAwayCount = 0; + } + + /* Since we must drop the current PCM buffer, we are dropping at minimum 1. That is taken care of by + * dropping new samples though. If it has been long enough since we last processed PDM data, we may need to + * drop more buffers. */ + metaDataForNextFrame.seqNum += pcmBytesDropped / object->pcmBufferSizeInBytes; + + byteCount = 0; + tempBufActive = false; + currTempBufIndex = 0; + } + + if (events & PDM_EVT_BLK_RDY) + { + + /* Request PDM data from I2S driver */ + while (PDMCC26XX_I2S_requestBuffer(i2sHandle, &bufferRequest)) + { + /* Buffer is available as long as it returns true */ + if (throwAwayCount == 0) + { + /* Get new buffer from queue if active PCM buffer + * is full. + */ + if (pcmBufferFull) + { + /* PDMCC26XX_getNewPcmBuffer() + * Get new container from available queue and allocate + * memory for new buffer. + */ + activePcmBuffer = PDMCC26XX_getNewPcmBuffer(pdmHandle); + if (activePcmBuffer) + { + pcmBufferFull = false; + byteCount = 0; + } + else + { + /* If we did not succeed getting a new pcm buffer, we + * need to start throwing data. + * + * Update throwAwayCount + * In this case throw bytes equal to the size of the + * PCM buffer minus the data output size of one iteration + * (which is dependent on compression/no compression). + * + * Note: Assuming that the (object->retBufSizeInBytes-PCM_METADATA_SIZE) is + * larger than the data output of one iteration. + */ + throwAwayCount = object->pcmBufferSizeInBytes - (object->applyCompression + ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE + : PDMCC26XX_CPY_ITER_OUTPUT_SIZE); + } + } + /* Decimate PDM data to PCM, result is stored in tempPcmBuf */ + object->pdm2pcmFxn(bufferRequest.bufferIn, + object->decimationFilterState, + object->decimationFilter, + (int16_t *)&tempPcmBuf); + + /* Mark the temp buf as active */ + tempBufActive = true; + /* Since the tempPcmBuffer might fill up the current pcm + * buffer, we might have to perform the operation (compression + * or memcpy) on the tempPcmBuffer in more than one iteration. + * + * If we did not allocate a new buffer succesfully above, we + * are about to throw away data. In that case we should not + * perform an operation on the PDM data. + */ + while (tempBufActive && !pcmBufferFull) + { + int srcSize; + + /* Next step is to handle the data in the tempPcmBuffer + * - If compression is enabled, the compression function + * will read in data from tempPcmBuffer and output the + * compressed data to the dynamically allocated pcmBuffer. + * - If compression is disabled, we use memcpy to move the pcm + * data from the tempPcmBuffer to the dynamically allocated + * pcmBuffer. + */ + if (object->applyCompression) + { + /* Prepare metadata. + * This is done before the first compression into the + * allocated PCM buffer. + */ + if (byteCount == 0) + { + activePcmBuffer->pBufferPCM->metaData.si = metaDataForNextFrame.si; + activePcmBuffer->pBufferPCM->metaData.pv = metaDataForNextFrame.pv; + } + /* If the current PCM buffer can fit the output of a + * compression of what is left in tempPcmBuf, set srcSize + * to that size. If not, set the srcSize to whatever will + * fit and mark the current pcm buffer as full. + * + * Note: currTempBufIndex will always be multiple of 2. + */ + if ((object->pcmBufferSizeInBytes - byteCount) > + PDMCC26XX_COMPR_ITER_OUTPUT_SIZE - (currTempBufIndex / 2)) + { + /* srcSize set to whatever is left in the tempPcmBuffer. */ + srcSize = (PDMCC26XX_COMPR_ITER_OUTPUT_SIZE * 2) - currTempBufIndex; + } + else + { + /* This is the last compression into the current data buffer, + * mark it as full. + */ + pcmBufferFull = true; + srcSize = ((object->retBufSizeInBytes - PCM_METADATA_SIZE) - byteCount) * 2; + } + + /* Perform compression + * + * Since the source (tempPcmBuf) is operated as int16_t, + * while the output as uint8_t srcSize is size in samples + * (int16), it must be multiple of 2. + */ + Codec1_encodeBuff((uint8_t *)&(activePcmBuffer->pBufferPCM->pBuffer[byteCount]), + (int16_t *)&(tempPcmBuf[currTempBufIndex]), + srcSize, + (int8_t *)&metaDataForNextFrame.si, + (int16_t *)&metaDataForNextFrame.pv); + + /* Update byteCount for next iteration. + * + * Since the compression is reducing the size with a factor 4, + * and the pcm output buffer and the tempPcm buffer are of + * different types, the byteCount will be incremented with + * half the size of srcSize. + */ + byteCount += srcSize / 2; + + /* Prepare currTempBufIndex for next iteration */ + currTempBufIndex += srcSize; + } + else + { + /* Compression is disabled */ + /* Compression will not be performed, so we copy data from + * temporary pcm buffer to allocated memory. Uncompressed + * PCM data buffer is 64 Bytes wide. + * + * Output and input are handled as bytes. + */ + if ((object->pcmBufferSizeInBytes - byteCount) > + (PDMCC26XX_CPY_ITER_OUTPUT_SIZE - (currTempBufIndex * 2))) + { + srcSize = PDMCC26XX_CPY_ITER_OUTPUT_SIZE - (currTempBufIndex * 2); + } + else + { + /* This is the last compression into the current data buffer, + * mark it as full. + */ + pcmBufferFull = true; + srcSize = object->pcmBufferSizeInBytes - byteCount; + } + + /* Copy PCM data from temp buffer to allocated memory */ + memcpy(&(activePcmBuffer->pBufferPCM->pBuffer[byteCount]), + &tempPcmBuf[currTempBufIndex], + srcSize); /* <- size in bytes */ + + /* Prepare byteCount for next iteration, for memcpy the + * byteCount is equal to the srcSize. + */ + byteCount += srcSize; + + /* Prepare currTempBufIndex for next iteration. + * Since the srcSize is byte aligned, but the tempBuffer + * is sample (int16_t) aligned, divide srcSize with 2. + */ + currTempBufIndex += srcSize / 2; + } + + /* Is all the data in the tempPcmBuffer consumed? + * If so, reset the index count and clear active flag. + * + */ + if (currTempBufIndex >= (sizeof(tempPcmBuf) / sizeof(tempPcmBuf[0]))) + { + tempBufActive = false; + currTempBufIndex = 0; + } + + if (pcmBufferFull) + { + /* If the allocated PCM buffer is full, we need to flag + * that the PCM buffer is ready (and making the callback). + * + * And last, allocate a new PCM buffer to be used. + */ + PDMCC26XX_setPcmBufferReady(pdmHandle, + activePcmBuffer, + (PDMCC26XX_I2S_BufferRequest *)&bufferRequest); + + /* Get new PCM buffer from available queue and allocate + * memory for new buffer. + */ + if ((activePcmBuffer = PDMCC26XX_getNewPcmBuffer(pdmHandle)) != NULL) + { + pcmBufferFull = false; + byteCount = 0; + } + else + { + + /* if we did not succeed getting a new pcm buffer, + * we need to start throwing data. + * + * Update ThrowCount + * In this case throw count is equal to data fitting + * in one allocated PCM buffer minus the output data + * which will be thrown in this iteration. + * Data thrown amount is data size of one iteration (which is dependent on + * compression/no compression), minus the data already + * consumed by the previous buffer. + */ + throwAwayCount = object->pcmBufferSizeInBytes - + ((object->applyCompression ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE + : PDMCC26XX_CPY_ITER_OUTPUT_SIZE) - + currTempBufIndex); + + /* Mark the tempBuf as no longer active */ + tempBufActive = false; + } + } + } + } + else + { + /* Still throwing away data */ + if (throwAwayCount <= + (object->applyCompression ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE : PDMCC26XX_CPY_ITER_OUTPUT_SIZE)) + { + /* if the amount to be thrown away is less than or equal to + * the output of one iteration of the data operation, the + * count must be set to zero, the sequence number must be + * incremented, and the index to be used by next data operation + * must be updated correspondingly. + */ + + /* Note: Currently the startup delay will use the throwAwayCount + * and that means the sequence number will be incremented + * after the startup throwing has finished. + */ + metaDataForNextFrame.seqNum++; + /* tempPcmBuf is int16 array, but the throwAwayCount is + * count in bytes. + */ + if (object->applyCompression) + { + /* If compression is enabled, the throwAwayCount number + * is the half of the number of samples: + */ + currTempBufIndex = throwAwayCount * 2; + } + else + { + /* If compression is disabled, the throwAwayCount is decremented + * with respect to raw data, but in bytes not samples. Since + * the currTempBufIndex is sample oriented, we need to divide + * that number with 2. + */ + currTempBufIndex = (throwAwayCount + 1) / 2; + } + throwAwayCount = 0; + } + else + { + /* Decrement the throw counter with amount corresponding to + * output data size of one iteration. + */ + throwAwayCount -= (object->applyCompression ? PDMCC26XX_COMPR_ITER_OUTPUT_SIZE + : PDMCC26XX_CPY_ITER_OUTPUT_SIZE); + } + } + /* Release PDM buffer */ + bufferRelease.bufferHandleIn = bufferRequest.bufferHandleIn; + PDMCC26XX_I2S_releaseBuffer(i2sHandle, &bufferRelease); + } + } + } +} + +/* + * ======== PDMCC26XX_requestBuffer ======== + * @pre Function assumes that the stream has started and that bufferRequest is not NULL. + */ +bool PDMCC26XX_requestBuffer(PDMCC26XX_Handle handle, PDMCC26XX_BufferRequest *bufferRequest) +{ + PDMCC26XX_Object *object; + + Assert_isTrue(handle, NULL); + Assert_isTrue(bufferRequest, NULL); + + /* Get the pointer to the object */ + object = pdmHandle->object; + + /* We expect the user to call this after being notified of available + * buffers. Hence we may directly check queue and dequeue buffer + */ + if (!Queue_empty(pcmMsgReadyQueue)) + { + PDMCC26XX_queueNodePCM *readyNode = Queue_get(pcmMsgReadyQueue); + /* Provide pointer to buffer including 4 byte metadata */ + bufferRequest->buffer = readyNode->pBufferPCM; + bufferRequest->status = streamNotification.status; + /* free up memory used by queue element */ + object->freeFxn(readyNode, sizeof(PDMCC26XX_queueNodePCM)); + } + else + { + return false; + } + + return true; +} + +static void PDMCC26XX_i2sCallbackFxn(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_StreamNotification *notification) +{ + uint32_t event = 0; + + switch (notification->status) + { + case PDMCC26XX_I2S_STREAM_BUFFER_READY: + event = PDM_EVT_BLK_RDY; + break; + case PDMCC26XX_I2S_STREAM_ERROR: + event = PDM_EVT_BLK_ERROR; + break; + case PDMCC26XX_I2S_STREAM_BUFFER_DROPPED: + /* A block of old PDM data was dropped to make space for new data */ + event = PDM_EVT_I2S_DATA_DROPPED; + /* This function is called in a hwi context. Hence, there is not need for a critical + * section to guard against accesses by the PDM task */ + droppedPdmBlockCount++; + break; + default: + break; + } + + Event_post(pdmEvents, event); +} + +/* + * ======== PDMCC26XX_initIO ======== + * This functions initializes the PDM IOs. + * + * @pre Function assumes that the PDM handle is pointing to a hardware + * module which has already been opened. + */ +static void PDMCC26XX_initIO(PDMCC26XX_Handle handle) +{ + Assert_isTrue(handle, NULL); + PDMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Configure IOs */ + GPIO_setConfig(hwAttrs->micPower, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_HIGH); +} + +/* + * ======== PDMCC26XX_finalizeIO ======== + * This functions releases the PDM IOs. + * + * @pre Function assumes that the PDM handle is pointing to a hardware + * module which has already been opened. + */ +static void PDMCC26XX_finalizeIO(PDMCC26XX_Handle handle) +{ + Assert_isTrue(handle, NULL); + PDMCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Configure IOs */ + GPIO_resetConfig(hwAttrs->micPower); +} + +/* + * ======== PDMCC26XX_setPcmBufferReady ======== + * This function prepares metadata, puts the buffer in ready queue, sets stream + * status and makes the callback. + * + * @pre Function assumes that the PDM handle is pointing to a hardware + * module which has already been opened. + */ +static void PDMCC26XX_setPcmBufferReady(PDMCC26XX_Handle handle, + PDMCC26XX_queueNodePCM *pcmBuffer, + PDMCC26XX_I2S_BufferRequest *bufReq) +{ + PDMCC26XX_Object *object; + object = handle->object; + + Assert_isTrue(handle, NULL); + Assert_isTrue(pcmBuffer, NULL); + Assert_isTrue(bufReq, NULL); + + /* Update sequence number */ + pcmBuffer->pBufferPCM->metaData.seqNum = metaDataForNextFrame.seqNum++; + /* Place PCM buffer in ready queue */ + Queue_put(pcmMsgReadyQueue, &pcmBuffer->queueElement); + + /* Notify caller by updating the stream status */ + if (bufReq->status == PDMCC26XX_I2S_STREAM_BUFFER_READY) + { + streamNotification.status = PDMCC26XX_STREAM_BLOCK_READY; + } + else if (bufReq->status == PDMCC26XX_I2S_STREAM_BUFFER_DROPPED) + { + streamNotification.status = PDMCC26XX_STREAM_BLOCK_READY_BUT_PDM_OVERFLOW; + } + else + { + streamNotification.status = PDMCC26XX_STREAM_STOPPING; + } + /* Only notify when PCM buffer is complete */ + object->callbackFxn(pdmHandle, &streamNotification); +} + +/* + * ======== PDMCC26XX_getNewPcmBuffer ======== + * This function gets a new queue element from the available queue and then + * tries to allocate the memory space needed for a new buffer. + * + * @return true if a new PCM buffer was succesfully allocated, false if the + * available queue was empty or the memory allocation function did not + * succeed. + */ +static PDMCC26XX_queueNodePCM *PDMCC26XX_getNewPcmBuffer(PDMCC26XX_Handle handle) +{ + PDMCC26XX_Object *object; + PDMCC26XX_queueNodePCM *buf; + + Assert_isTrue(handle, NULL); + + object = handle->object; + + /* Allocate memory for a new queue element */ + buf = object->mallocFxn(sizeof(PDMCC26XX_queueNodePCM)); + /* If allocation went OK, allocate more... */ + if (buf != NULL) + { + /* Dynamically allocated memory for new pcm buffer */ + buf->pBufferPCM = object->mallocFxn(object->retBufSizeInBytes); + /* If new memory was allocated correctly, return pointer. */ + if (buf->pBufferPCM != NULL) + { + return buf; + } + else + { + /* Was not able to allocate memory for the pcm buffer, deallocate + * the memory used by queue element. + */ + object->freeFxn(buf, sizeof(PDMCC26XX_queueNodePCM)); + } + } + + return NULL; +} + +/* + * ======== PDMCC26XX_rollbackDriverInitialisation ======== + * This function rolls back different parts of the PDM driver initialisation depending on the rollbackVector. + * Passing ~0 as the rollbackVector will reverse all failable initialisations. + * Only those parts of the driver that can fail when calling PDMCC26XX_open can be included as entries in the + * rollbackVector. + */ +static void PDMCC26XX_rollbackDriverInitialisation(PDMCC26XX_Handle handle, uint32_t rollbackVector) +{ + unsigned int key; + PDMCC26XX_Object *object; + + Assert_isTrue(handle, NULL); + Assert_isTrue(rollbackVector, NULL); + + object = handle->object; + + if (rollbackVector & PDM_ROLLBACK_I2S_DRIVER) + { + /* Release ownership and revert to init settings. */ + PDMCC26XX_I2S_close(i2sHandle); + } + + if (rollbackVector & PDM_ROLLBACK_PIN) + { + /* Release the allocated pins back to the pin driver */ + PDMCC26XX_finalizeIO(handle); + } + + if (rollbackVector & PDM_ROLLBACK_DECIMATION_STATE) + { + /* Free up memory used for decimationFilterState */ + object->freeFxn(object->decimationFilterState, object->decimationFilterStateSize); + } + + if (rollbackVector & PDM_ROLLBACK_ACTIVE_PCM_BUFFER) + { + /* + * Free the activePcmBuffer if it is not NULL. It can be NULL if either insufficient time was provided after + * PDMCC26XX_open for the open event in the task function to run and allocate the memory or if we ran out of + * heap space earlier and the PDMCC26XX_getNewPcmBuffer function returned NULL. + */ + if (activePcmBuffer != NULL) + { + /* Free up memory used for activePcmBuffer */ + object->freeFxn(activePcmBuffer->pBufferPCM, object->retBufSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(activePcmBuffer, sizeof(PDMCC26XX_queueNodePCM)); + /* Make sure the activePcmBuffer doesn't point anywhere anymore as the target no longer exists. */ + activePcmBuffer = NULL; + } + } + + if (rollbackVector & PDM_ROLLBACK_OPEN) + { + /* Mark the module as available */ + key = HwiP_disable(); + object->isOpen = false; + HwiP_restore(key); + } +} + +static inline uint32_t PDMCC26XX_maxUInt32(uint32_t a, uint32_t b) +{ + return ((a > b) ? a : b); +} diff --git a/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.h b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.h new file mode 100644 index 00000000..bee6f509 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX.h @@ -0,0 +1,767 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PDMCC26XX.h + * + * @brief PDM driver implementation for a CC26XX PDM controller. + * + * The PDM header file should be included in an application as follows: + * @code + * #include + * @endcode + * + * # Overview # + * This driver is written to be able to perform continuous audio streaming + * of PDM data from a microphone. It also controls one DIO to be able + * to turn on power to the microphone. + * + * This PDM driver performs two operations that requires processing + * - PDM to PCM conversion + * - PCM compression (optional) + * + * When producing 16kHz output, the driver is configured to process 256 bytes + * of PDM data provided by the I2S hardware module at a time, sampled at + * 1.024 Mbps. The PDM driver consequently receives such a buffer approximately + * every 2ms. + * A frame of ::PDMCC26XX_Params.retBufSizeInBytes PCM data bytes minus four + * metadata bytes is provided to the application after being filled by all or + * part of one or more 64 byte buffers of PCM data derived from the 256 bytes + * of PDM data. The resulting PCM frame provided to the application is a 16bit + * PCM signal sampled at 16kHz. + * + * When providing 8kHz PCM output, the driver processes 512 bytes of PDM data + * at a time. At a sample rate of 1.024 Mbps, this yields a PDM buffer to + * process ever 4ms. These 512 bytes of PDM data are filtered and decimated + * to yield 64 bytes of PCM output. + * + * The driver creates a separate task to run in. + * + * @note The application must allow for the PDM driver task to run often enough to process the data received from + * I2S driver approximately every 2ms in 16kHz PCM output mode or 4ms in 8kHz PCM output mode. + * The amount of processing is approximately equal but the latency requirements differ. + * + * The driver currently only samples on a single edge of the I2S clock. + * + * # General Behaviour # + * Before using PDM on CC26XX: + * - The PDM driver is initialized by calling ::PDMCC26XX_init(). This should + * be done in main before BIOS_start() is called. + * - The PDM system dependencies are set by calling ::PDMCC26XX_open(). + * The driver is also marked as taken. Prior to this the system should call ::PDMCC26XX_init(). + * The driver also automatically allocates the first PDMCC26XX_pcmBuffer of the size + * specified by the application in ::PDMCC26XX_Params.retBufSizeInBytes. + * This call also reserves the pins for the microphone signal and power specified in the board file. + * - Do not start steaming data until the device is running off of the high frequency external oscilator (XOSC_HF). + * The XOSC_HF is required to generate a jitter-free I2S audio clock. When switching to XOSC_HF, several SCLK_HF +clock + * cycles and thus audio clock cycles are missed. Both jitter and missing audio clock cycles causes severe +degredation + * in audio noise performance! + * After booting, the device runs off of the high frequency RC oscillator (RCOSC_HF) by default. Set a dependency + * on the XOSC_HF to turn it on and switch to it when it is ready. Register a power notification for the XOSC_HF +having switched. + * Wait until after this notification occurs to call PDMCC26XX_startStream(). When waking up from standby, the +XOSC_HF will automatically + * be turned on and switched to if the dependency was set before going into standby. Again, only call +PDMCC26XX_startStream() + * after the application was notified of the switch to XOSC_HF. PDMCC26XX_open() may be called before running off of +XOSC_HF. + * + * While using PDM on CC26XX: + * - When PDMCC26XX_open() is called, the driver allocates one PCM buffer on the heap and the I2S module tries to +allocate enough memory for its PDM buffers. + * - When PDMCC26XX_startStream() is called, the I2S driver starts processing the pdm stream, + * the PDM driver resets the internal state of the decimation filter, sets the driver to drop the first + * MAX(PDM_DECIMATION_STARTUP_DELAY_IN_SAMPLES, ::PDMCC26XX_Params.startupDelayWithClockInSamples), + * and resets the metaData (including the sequence number). The driver will keep allocating PDMCC26XX_pcmBuffers on +the heap + * and keep them in a queue until they are requested by the application. + * From now on, callbacks are generated every time a buffer is ready; if callbacks are asked for. + * - Data is acquired by the application by calling ::PDMCC26XX_requestBuffer(). + * After processing the buffer, the application is responsible for freeing the memory allocated + * for the buffer in a timely manner. + * - The stream is stopped when ::PDMCC26XX_stopStream() is called. Note that + * this is a blocking call that will wait until the I2S hardware has gracefully + * shut down. This will take at most 4ms, unless an error occurs. + * Any PCM buffers remaining must be released by the application as usual. + * The system is allowed to enter standby again after PDMCC26XX_stopStream() is called. + * - The memory held by the I2S module is freed upon calling PDMCC26XX_close(). Any completed PCM buffers must be +processed and freed by the application. + * + * After PDM operation has ended: + * - Release system dependencies and free up all memory on the heap allocated for the PDM driver by calling +PDMCC26XX_close(). + * + * # Error Handling # + * The application is notified of errors via the registered callback function. + * + * ## Heap Full # + * If the application fails to consume PCM buffers fast enough and the heap is full + * when driver tries to allocate a new buffer, the driver will drop all new incoming data until a buffer + * can be allocated to store it. Data is dropped one PCM data buffer at a time , even though it is streamed + * into the device and copied into the buffer in smaller chunks. + * This is done to keep the data expected in any buffer in sync with the sequence number + * of the buffer that keeps incrementing even when the buffer is dopped. The application may keep track + * of lost frames by comparing sequence numbers. + * + * Hence, the PDM stream will never have a buffer overflow, but if the memory available in the + * heap is too low it may lose frames because because there is nowhere to put the incoming + * + * If the heap frees up again and the PDM task runs, it will automatically resume normal operation again. + * The only application-observable difference is the incremented version number. + * + * ## PDM Task Not Serviced In Time # + * The application must permit the PDM task to run often enough that it can process a PDM buffer every 2ms on average. + * If the application requires a larger contiguous segment of processing time, the I2S hwi may run out of empty buffers +to fill + * with new PDM data. When the I2S driver runs out of empty PDM buffers it will pop a buffer from the full buffer queue +and overwrite + * its old data. The I2S driver notifies the PDM driver that it has dropped a PDM buffer. Once it runs again, the PDM +driver will drop + * enough additional PCM samples such that the sequence numbers of the PCM buffers remain aligned with the data in the +audio stream. + * The latency between when the PDM task was last serviced and when it must be serviced again to avoid losing data is +specified by + * ::PDMCC26XX_Params::pdmBufferQueueDepth. This permitted latency increases by 2ms or 4ms for each increment of +pdmBufferQueueDepth. + * + * ## PDMCC26XX_open Failing # + * ::PDMCC26XX_open() returns NULL and rolls back all prior parts of the initialisation if any part of the +initialisation fails. + * The following can cause ::PDMCC26XX_open() to fail: + * - The driver is already open + * - The heap is full when the application calls ::PDMCC26XX_open() + * - The PIN driver could not allocate the requested pins for the PDM driver + * - The I2S driver failed to initialise + * + * ## PDMCC26XX_startStream Failing # + * ::PDMCC26XX_startStream() returns false if it fails. + * The following can cause ::PDMCC26XX_startStream() to fail: + * - The driver is already streaming + * - The I2S driver could not successfully start reading the pdm stream + * - The I2S driver could not allocate enough memory for the specified + * number of PDM buffers + * + * ## PDMCC26XX_stopStream Failing # + * ::PDMCC26XX_stopStream() returns false if it fails. + * The following can cause ::PDMCC26XX_stopStream() to fail: + * - The driver is not currently streaming + * + * # Power Management # + * The PDMCC26XX driver sets a power constraint while streaming to keep + * the device out of standby. When the stream has ended, the power constraint + * is released. + * + * The following statements are valid: + * - After ::PDMCC26XX_open(): the device is still allowed to enter standby. + * - During ::PDMCC26XX_startStream(): the device cannot enter standby. + * - After ::PDMCC26XX_stopStream() succeeds: the device can enter standby. + * - If ::PDMCC26XX_close() is called: the device can enter standby. + * + * # Standard Use Case # + * The standard use case involves calling PDMCC26XX_open() once and calling PDMCC26XX_startStream() and +PDMCC26XX_stopStream() + * to start and stop the stream as needed. PDMCC26XX_close() is called when the PDM driver will no longer be needed +again. + * In order for the PDM driver task to run, the application pends on a semaphore that is posted in the +::PDMCC26XX_Params::callbackFxn. + * In this example, the application requests 128 buffers. In a real application, the process of pending on a semaphore, +requesting a buffer, + * and freeing it would be repeated as often as required by the use case before stopping the stream. + * @code + * + * void bufRdy_callback(PDMCC26XX_Handle handle, PDMCC26XX_StreamNotification *streamNotification) + * { + * if (streamNotification->status == PDMCC26XX_STREAM_BLOCK_READY || streamNotification->status == +PDMCC26XX_STREAM_BLOCK_READY_BUT_PDM_OVERFLOW){ + * SemaphoreP_post(SemaphoreP_handle(&bufferReadySemaphore)); + * } + * else { + * // Handle the error + * } + * } + * + * static void applicationTask(UArg a0, UArg a1){ + * SemaphoreP_Params semParams; + * PDMCC26XX_BufferRequest bufferRequest; + * PDMCC26XX_Params pdmParams; + * const uint16_t returnBufferSize = 64; + * const uint8_t numberOfPcmBuffersToRequest = 128; + * + * // Initialize semaphore + * SemaphoreP_Params_init(&semParams); + * semParams.mode = SemaphoreP_Mode_BINARY; + * SemaphoreP_construct(&bufferReadySemaphore, 0, &semParams); + * + * // Set up parameters for PDM streaming with compression + * PDMCC26XX_Params_init(&pdmParams); + * pdmParams.callbackFxn = bufRdy_callback; + * pdmParams.micPowerActiveHigh = true; + * pdmParams.applyCompression = true; + * pdmParams.retBufSizeInBytes = returnBufferSize; + * pdmParams.mallocFxn = &malloc; + * pdmParams.freeFxn = &free; + * + * // Try to open the PDM driver + * if(pdmHandle = PDMCC26XX_open(&pdmParams) == NULL){ + * // Handle PDMCC26XX_open() failing + * } + * + * // Try to start streaming + * if(PDMCC26XX_startStream(pdmHandle)){ + * uint8_t pcmBuffersRequestedSoFar; + * + * // Request numberOfPcmBuffersToRequest buffers and then stop the stream + * for (pcmBuffersRequestedSoFar = 0; pcmBuffersRequestedSoFar < numberOfPcmBuffersToRequest; +pcmBuffersRequestedSoFar++){ + * // Pend on the semaphore until a buffer is available from the PDM driver + * SemaphoreP_pend(SemaphoreP_handle(&bufferReadySemaphore), BIOS_WAIT_FOREVER); + * + * // Now request a buffer as it was indicated that one is available + * PDMCC26XX_requestBuffer(pdmHandle, &bufferRequest); + * + * // Process bufferRequest + * + * // Free the buffer + * my_free(bufferRequest.buffer, returnBufferSize); + * } + * + * // Try to stop the stream + * if(!PDMCC26XX_stopStream(pdmHandle)){ + * // Handle PDMCC26XX_stopStream() failing + * } + * } + * else{ + * // Handle PDMCC26XX_startStream() failing + * } + * } + * + * @endcode + +# 8kHz PCM output # +By default, the PCM output of the driver has a sampling frequency of fs = 16kHz. +There is an alternate signal processing chain that returns PCM output with fs = 8kHz. +This example shows how to alter the standard use-case to set this up. +@code + * void bufRdy_callback(PDMCC26XX_Handle handle, PDMCC26XX_StreamNotification *streamNotification) + * { + * if (streamNotification->status == PDMCC26XX_STREAM_BLOCK_READY || streamNotification->status == +PDMCC26XX_STREAM_BLOCK_READY_BUT_PDM_OVERFLOW){ + * SemaphoreP_post(SemaphoreP_handle(&bufferReadySemaphore)); + * } + * else { + * // Handle the error + * } + * } + * + * static void applicationTask(UArg a0, UArg a1){ + * SemaphoreP_Params semParams; + * PDMCC26XX_BufferRequest bufferRequest; + * PDMCC26XX_Params pdmParams; + * const uint16_t returnBufferSize = 64; + * const uint8_t numberOfPcmBuffersToRequest = 128; + * + * // Initialize semaphore + * SemaphoreP_Params_init(&semParams); + * semParams.mode = SemaphoreP_Mode_BINARY; + * SemaphoreP_construct(&bufferReadySemaphore, 0, &semParams); + * + * // Set up parameters for PDM streaming with compression + * PDMCC26XX_Params_init(&pdmParams); + * pdmParams.callbackFxn = bufRdy_callback; + * pdmParams.micPowerActiveHigh = true; + * pdmParams.applyCompression = true; + * pdmParams.retBufSizeInBytes = returnBufferSize; + * pdmParams.mallocFxn = &malloc; + * pdmParams.freeFxn = &free; + * + * // Configure the params to use 8kHz PCM output + * pdmParams.pcmSampleRate = PDMCC26XX_PCM_SAMPLE_RATE_8K + * + * // Try to open the PDM driver + * if(pdmHandle = PDMCC26XX_open(&pdmParams) == NULL){ + * // Handle PDMCC26XX_open() failing + * } + * + * // Try to start streaming + * if(PDMCC26XX_startStream(pdmHandle)){ + * uint8_t pcmBuffersRequestedSoFar; + * + * // Request numberOfPcmBuffersToRequest buffers and then stop the stream + * for (pcmBuffersRequestedSoFar = 0; pcmBuffersRequestedSoFar < numberOfPcmBuffersToRequest; +pcmBuffersRequestedSoFar++){ + * // Pend on the semaphore until a buffer is available from the PDM driver + * SemaphoreP_pend(SemaphoreP_handle(&bufferReadySemaphore), BIOS_WAIT_FOREVER); + * + * // Now request a buffer as it was indicated that one is available + * PDMCC26XX_requestBuffer(pdmHandle, &bufferRequest); + * + * // Process bufferRequest + * + * // Free the buffer + * my_free(bufferRequest.buffer, returnBufferSize); + * } + * + * // Try to stop the stream + * if(!PDMCC26XX_stopStream(pdmHandle)){ + * // Handle PDMCC26XX_stopStream() failing + * } + * } + * else{ + * // Handle PDMCC26XX_startStream() failing + * } + * } +@endcode + + + */ + +#ifndef ti_drivers_pdm_PDMCC26XX__include +#define ti_drivers_pdm_PDMCC26XX__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************************* + * CONSTANTS + */ + +/*! Defines TI-RTOS stack size allocation. It is a conservative estimate. + * Change this to save a few bytes of RAM on stack allocation. The stack usage + * is independent of the PCM return buffer size specified by the application. + * When using logging, increase this value. + * This value is also dependent on the malloc and free function implementations + * provided by the application as both are called from PDM task context. + */ +#ifndef PDM_TASK_STACK_SIZE + #define PDM_TASK_STACK_SIZE 850 +#endif + +/*! Uncompressed PCM sample size in bits @note Internal use only since only 16 bits are supported */ +#define PCM_SAMPLE_SIZE 16 // Only 16 bits supported for now + +/*! Compression rate if compression is enabled */ +#define PCM_COMPRESSION_RATE 4 + +/*! Minimum number of PDM buffers required by the driver to safely use the I2S module */ +#define MINIMUM_PDM_BUFFER_QUEUE_DEPTH 3 + +/*! PCM data metadata size. When a buffer is requested there will be metadata + * prepended. In other words the pointer returned points to the metadata header. + * Depending on the mode, this contains different information. The first byte is always + * an 8-bit sequence number. */ +#define PCM_METADATA_SIZE sizeof(PDMCC26XX_metaData) + +/********************************************************************* + * TYPEDEFS + */ + +/*! @brief Metadata associated with an array of PCM data */ +typedef struct +{ + uint8_t seqNum; /*!< Sequence number of a ::PDMCC26XX_pcmBuffer */ + int8_t si; /*!< Step index of a ::PDMCC26XX_pcmBuffer */ + int16_t pv; /*!< Next predicted value of a ::PDMCC26XX_pcmBuffer */ +} PDMCC26XX_metaData; + +/*! @brief PCM buffer pointed to in a PDMCC26XX_BufferRequest */ +typedef struct +{ + PDMCC26XX_metaData metaData; /*!< Metadata for the buffer */ + uint8_t pBuffer[]; /*!< PCM data buffer */ +} PDMCC26XX_pcmBuffer; + +/*! + * @brief + * PDMCC26XX_MallocFxn is a function pointer for the malloc function to + * be used by the driver. + */ +typedef void *(*PDMCC26XX_MallocFxn)(size_t memSize); + +/*! + * @brief + * PDMCC26XX_FreeFxn is a function pointer for the free function to + * be used by the driver. This is needed for memory clean up, if something goes + * wrong. + */ +typedef void (*PDMCC26XX_FreeFxn)(void *ptr, size_t memSize); + +/*! + * @brief Function that converts PDM input buffer to PCM output + * + * @param pdmInBuffer Input PDM buffer + * + * @param decimationState CIC decimator state + * + * @param biquadCoefficients Coefficient table for the n-stage biquad IIR filter + * + * @param pcmOutBuffer Output PCM buffer + */ +typedef bool (*PDMCC26XX_Pdm2PcmFxn)(const void *pdmInBuffer, + uint32_t *decimationState, + const int32_t *biquadCoefficients, + int16_t *pcmOutBuffer); + +/*! + * @brief + * The PDMCC26XX_Config structure contains a set of pointers used to + * characterize the PDMCC26XX driver implementation. + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PDMCC26XX_Config; + +/*! PDMCC26XX_Config struct defined in the board file */ +extern const PDMCC26XX_Config PDMCC26XX_config[]; + +/*! + * @brief PDMCC26XX Hardware attributes + * + * These fields are used by the PDM driver + * + */ +typedef struct +{ + /*! Microphone power pin */ + uint32_t micPower; + /*! PDM task priority pin */ + int taskPriority; +} PDMCC26XX_HWAttrs; + +/*! + * @brief A handle that is returned from a PDMCC26XX_open() call. + */ +typedef PDMCC26XX_Config *PDMCC26XX_Handle; + +/*! + * @brief Status codes that are set by the PDM driver. + */ +typedef enum +{ + PDMCC26XX_STREAM_IDLE, /*!< Idle mode. Stream not started */ + PDMCC26XX_STREAM_BLOCK_READY, /*!< Buffer ready */ + PDMCC26XX_STREAM_BLOCK_READY_BUT_PDM_OVERFLOW, /*!< Buffer ready, but + * the I2S module has had to drop data . */ + PDMCC26XX_STREAM_ERROR, /*!< The I2S module encountered a hardware error. Likely + * because the target address for the I2S DMA was NULL + */ + PDMCC26XX_STREAM_STOPPING, /*!< A stop was requested and this is the + * last buffer to be produced.*/ + PDMCC26XX_STREAM_STOPPED, /*!< Unused */ + PDMCC26XX_STREAM_FAILED_TO_STOP /*!< Buffer ready */ +} PDMCC26XX_Status; + +/*! + * @brief PCM output sample rates supported by the driver + * + * The driver will default to 16kHz output. Switching to 8kHz switches the signal + * processing chain used internally. + */ +typedef enum +{ + PDMCC26XX_PCM_SAMPLE_RATE_16K = 0, + PDMCC26XX_PCM_SAMPLE_RATE_8K +} PDMCC26XX_PcmSampleRate; + +/*! + * @brief Predefined gain settings. + * + * Gain is controlled by modifying the first coefficient of the PDM filter. + * Use these defines to set the correct gain setting in the default filter. + * This setting does not affect any non-default filters! + * All values are in dB. Default prefilter stages will add 12dB gain. + * PDM2PCM algorithm returns false if any of the samples decimated goes + * above 2^16 - 1, i.e. the sample clipped during decimation. + * This information can be used for automatic gain control. + */ +typedef enum +{ + PDMCC26XX_GAIN_24 = 1318, /*!< 24dB gain */ + PDMCC26XX_GAIN_18 = 660, /*!< 18dB gain */ + PDMCC26XX_GAIN_12 = 331, /*!< 12dB gain. Default */ + PDMCC26XX_GAIN_6 = 166, /*!< 6dB gain */ + PDMCC26XX_GAIN_0 = 83, /*!< 0dB gain */ + PDMCC26XX_GAIN_END /*!< Internal use only */ +} PDMCC26XX_Gain; + +/*! + * @brief + * A ::PDMCC26XX_StreamNotification data structure is used with PDMCC26XX_CallbackFxn(). + * Provides notification about available buffers and potential errors + */ +typedef struct +{ + void *arg; /*!< Argument to be passed to the callback function */ + PDMCC26XX_Status status; /*!< Status code set by PDMCC26XX driver */ +} PDMCC26XX_StreamNotification; + +/*! + * @brief The definition of a callback function used when buffers are ready + * + * @param PDMCC26XX_Handle PDMCC26XX_Handle + */ +typedef void (*PDMCC26XX_CallbackFxn)(PDMCC26XX_Handle handle, PDMCC26XX_StreamNotification *streamNotification); + +/*! + * @brief + * A ::PDMCC26XX_BufferRequest data structure is used with PDMCC26XX_requestBuffer(). + * + * buffer is a pointer to the requested buffer. It is NULL if no buffer is available. + * Each buffer contains a metadata header of size PCM_METADATA_SIZE. The first + * byte of the metadata is always an 8 bit sequence number. The other bytes + * depends on mode. + * + * Mode | Interpretation of bufferIn being NULL after returning | + * --------------------|-------------------------------------------------------| + * Blocking mode | Request timed out and still no buffer available | + * Non-Blocking mode | No buffer available | + * + */ +typedef struct +{ + PDMCC26XX_pcmBuffer *buffer; /*!< Pointer to requested buffer. Note that this + * includes PCM_METADATA_SIZE bytes of metadata + * as a header */ + PDMCC26XX_Status status; /*!< Status code set by PDMCC26XX_requestBuffer */ +} PDMCC26XX_BufferRequest; + +/*! + * @brief + * PDMCC26XX Parameters are used to with the PDMCC26XX_open() call. Default values for + * these parameters are set using PDMCC26XX_Params_init(). + * + * @sa PDMCC26XX_Params_init + */ +typedef struct +{ + /* PDM control variables */ + bool micPowerActiveHigh; /*!< Set to TRUE if setting the GPIO high powers the microphone */ + bool applyCompression; /*!< Set to TRUE to apply compression. Setting it to FALSE allows + * user to apply own compression scheme. + */ + uint8_t pdmBufferQueueDepth; /*!< PDM buffer queue depth in number of blocks. We assume that we will be able to + * consume approximately one buffer per 2ms. This allows us to use the minium + * number of blocks (3) for the PDMCC26XX driver. + * If the application can not service the PDM task within the 2ms time window, + * increase this value to permit more latency in processing incoming PDM data + * at the cost of increased RAM useage. + */ + uint16_t retBufSizeInBytes; /*!< Size of returned buffers. It is not reccomended to make this value + * less than 64, the driver will not crash, but the sequence numbers may + * become unaligned with the data in the buffer. */ + const int32_t *decimationFilter; /*!< Filter applied during PDM to PCM conversion. Will use default filter if NULL. + */ + size_t decimationFilterStateSize; /*!< Size of the decimation filter state information in bytes. Should be + * (6 + 2 * N) * sizeof(uint32_t) bytes long, + * where N is the number of filter stages in ::PDMCC26XX_Params.decimationFilter + * for the default signal processing chain. The decimation state will be allocated + * using the + * ::PDMCC26XX_Params.mallocFxn. + */ + PDMCC26XX_Gain defaultFilterGain; /*!< Gain of the signal chain before filtering. The decimation stage adds 12dB + itself. */ + PDMCC26XX_PcmSampleRate pcmSampleRate; /*!< Sample rate of the PCM output */ + uint32_t startupDelayWithClockInSamples; /*!< Some digital microphones have a startup delay. + * Set the number of samples to discard after powering the microphone + * starting to clock in data. + */ + PDMCC26XX_CallbackFxn callbackFxn; /*!< Callback function pointer */ + PDMCC26XX_MallocFxn mallocFxn; /*!< Malloc function pointer */ + PDMCC26XX_FreeFxn freeFxn; /*!< Free function pointer */ + uintptr_t custom; /*!< Custom argument used by driver implementation */ +} PDMCC26XX_Params; + +/*! + * @brief PDMCC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + /* PDM control variables */ + bool streamStarted; /*!< Stream started flag */ + bool micPowerActiveHigh; /*!< Set to TRUE if setting the GPIO high powers the microphone */ + bool applyCompression; /*!< Set to TRUE to apply compression. Setting it to FALSE allows + * user to apply own compression scheme. + */ + bool isOpen; /*!< Has the object been opened */ + uint16_t retBufSizeInBytes; /*!< Size of returned buffers */ + uint16_t pcmBufferSizeInBytes; /*!< Size of the pcm buffer inside the returnBuffer is equal to retBufSizeInBytes - + PCM_METADATA_SIZE */ + uint32_t startupDelayWithClockInSamples; /*!< Some digital microphones have a startup delay. + * Set the number of samples to discard after powering the microphone + * starting to clock in data. + */ + const int32_t *decimationFilter; /*!< Filter applied during PDM to PCM conversion. Will use default filter if NULL. + */ + uint32_t *decimationFilterState; /*!< Decimation filter state information. */ + size_t decimationFilterStateSize; /*!< Size of the decimation filter state information in bytes. Should be 6 + 2 * N + * words long, where N is the number of filter stages in + * ::PDMCC26XX_Params.decimationFilter for the default filter. + */ + PDMCC26XX_StreamNotification *streamNotification; /*!< Stream state variable */ + PDMCC26XX_CallbackFxn callbackFxn; /*!< Callback function pointer */ + PDMCC26XX_MallocFxn mallocFxn; /*!< Malloc function pointer */ + PDMCC26XX_FreeFxn freeFxn; /*!< Free function pointer */ + PDMCC26XX_Pdm2PcmFxn pdm2pcmFxn; /*!< Function that converts PDM input to PCM output */ + HwiP_Struct hwi; /*!< Hwi object handle */ +} PDMCC26XX_Object; + +/*! + * @brief PDM CC26XX initialization + * + */ +extern void PDMCC26XX_init(PDMCC26XX_Handle handle); + +/*! + * @brief Function to initialize the CC26XX PDM peripheral specified by the + * particular handle. The parameter specifies which mode the PDM + * will operate. + * + * The function will set a dependency on the PDM module, which in turn powers up the module and enables the clock. + * IOs are also allocated, however the PDM driver will not begin streaming audio until PDMCC26XX_startStream() is + * called. + * + * @pre PDM controller has been initialized + * + * @param params Pointer to a parameter block. Will use default parameters if NULL + * + * @return A PDMCC26XX_Handle on success or a NULL on an error or if it has been + * already opened + * + * @sa PDMCC26XX_close() + */ +extern PDMCC26XX_Handle PDMCC26XX_open(PDMCC26XX_Params *params); + +/*! + * @brief Function to close a given CC26XX PDM peripheral specified by the + * PDM handle. + * + * Posts an event that shuts down the I2S hardware, frees all memory used by the driver on the heap, + * releases the pins back to the PIN driver, and releases the dependency on the corresponding power domain. + * + * @pre PDMCC26XX_open() has to be called first. + * + * @post The PDM task must be allowed to run to synchronously shut down the driver + * + * @param handle A PDMCC26XX_Handle returned from PDMCC26XX_open() + * + * @sa PDMCC26XX_open + */ +extern void PDMCC26XX_close(PDMCC26XX_Handle handle); + +/*! + * @brief Function to start streaming PDM data. + * + * Posts an event that tells the I2S hardware to start streaming and the PDM task to start processing incoming data. + * + * @pre PDMCC26XX_open() has to be called first. + * + * @pre The device must be deriving SCLK_HF from XOSC_HF or noise performance will be significantly degraded. + * + * @post The PDM task must be allowed to run (by e.g. pending on a semaphore in the application task) + * to process incoming PDM data from the I2S module. + * + * @param handle A PDM handle returned from PDMCC26XX_open() + * + * @return true if transfer is successful and false if not + * + * @sa PDMCC26XX_open(), PDMCC26XX_stopStream() + */ +extern bool PDMCC26XX_startStream(PDMCC26XX_Handle handle); + +/*! + * @brief Function to stop streaming PDM data. + * + * Blocks while the I2S module shuts down gracefully. Subsequently posts an event to let the PDM task process any + * remaining data. + * + * @pre PDMCC26XX_startStream() has to be called first. + * + * @param handle A PDM handle returned from PDMCC26XX_open() + * + * @return True if stream stopped successfully and false if not + * + * @post Process all available PCM buffers by calling PDMCC26XX_requestBuffer() until it returns false. + * Otherwise, the available PCM buffers will take up space on the heap until PDMCC26XX_close() or + * PDMCC26XX_startStream() are called. + * + * @sa PDMCC26XX_open(), PDMCC26XX_startStream() + */ +extern bool PDMCC26XX_stopStream(PDMCC26XX_Handle handle); + +/*! + * @brief Function for requesting buffer. + * + * PDMCC26XX_requestBuffer returns immediately even if no buffer is available. + * The caller is notified through events each time a buffer is available. + * However, more than one buffer may be available. Hence, the caller should + * request even without notification if the caller is ready to process. + * + * @pre PDMCC26XX_open() and PDMCC26XX_startStream() has to be called first. + * + * @param handle A PDM handle returned from PDMCC26XX_open() + * + * @param *bufferRequest Pointer to PDMCC26XX_BufferRequest struct + * + * @return True if request is successful and false if not + * + * @sa PDMCC26XX_open(), PDMCC26XX_startStream() + */ +extern bool PDMCC26XX_requestBuffer(PDMCC26XX_Handle handle, PDMCC26XX_BufferRequest *bufferRequest); + +/* + * ======== PDMCC26XX_Params_init ======== + * @brief Function for initialising a PDMCC26XX_Params instance to its default value + * + * @param params Pointer to a set of uninitialised params + * + */ +extern void PDMCC26XX_Params_init(PDMCC26XX_Params *params); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_pdm_PDMCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.c b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.c new file mode 100644 index 00000000..f8b6116b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.c @@ -0,0 +1,909 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/rom.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/i2s.h) + +/* PDMCC26XX_I2S functions */ +void PDMCC26XX_I2S_init(PDMCC26XX_I2S_Handle handle); +PDMCC26XX_I2S_Handle PDMCC26XX_I2S_open(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_Params *params); +void PDMCC26XX_I2S_close(PDMCC26XX_I2S_Handle handle); +bool PDMCC26XX_I2S_startStream(PDMCC26XX_I2S_Handle handle); +bool PDMCC26XX_I2S_stopStream(PDMCC26XX_I2S_Handle handle); +bool PDMCC26XX_I2S_requestBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRequest *bufferRequest); +void PDMCC26XX_I2S_releaseBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRelease *bufferRelease); + +/* Internal functions */ +static void PDMCC26XX_I2S_initHw(PDMCC26XX_I2S_Handle handle); +static void PDMCC26XX_I2S_initIO(PDMCC26XX_I2S_Handle handle); +static void PDMCC26XX_I2S_finalizeIO(PDMCC26XX_I2S_Handle handle); +static void PDMCC26XX_I2S_hwiFxn(UArg arg); +static void PDMCC26XX_I2S_callback(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_StreamNotification *msg); +static void PDMCC26XX_I2S_deallocateBuffers(PDMCC26XX_I2S_Handle handle); +static bool PDMCC26XX_I2S_allocateBuffers(PDMCC26XX_I2S_Handle handle); + +/*! Struct that contains an I2S queue element and a pointer to the PDM buffer it is responsible for */ +typedef struct +{ + Queue_Elem queueElement; /*!< Queue element */ + void *buffer; /*!< Buffer pointer */ +} PDMCC26XX_I2S_QueueNode; + +/*! PDMCC26XX_I2S_Config struct defined in the board file */ +extern const PDMCC26XX_I2S_Config PDMCC26XX_I2S_config[]; + +PDMCC26XX_I2S_QueueNode *i2sBlockActive = NULL; /* Reference to the element which is currently being filled by I2S DMA + In */ +PDMCC26XX_I2S_QueueNode *i2sBlockNext = NULL; /* Reference to the next element which will be filled by I2S DMA In */ + +Queue_Struct i2sBlockEmptyQueueStruct; +Queue_Handle i2sBlockEmptyQueue; + +Queue_Struct i2sBlockFullQueueStruct; +Queue_Handle i2sBlockFullQueue; + +I2SControlTable g_ControlTable; + +/* + * ======== PDMCC26XX_I2S_init ======== + * @pre Function assumes that the handle is not NULL + */ +void PDMCC26XX_I2S_init(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + + Assert_isTrue(handle, NULL); + + /* Get the pointer to the object */ + object = handle->object; + + /* Mark the object as available */ + object->isOpen = false; + + /* Make sure struct in driverlib I2S driver is initialized */ + g_pControlTable = &g_ControlTable; +} + +/* + * ======== PDMCC26XX_I2S_open ======== + * @pre Function assumes that the handle is not NULL + */ +PDMCC26XX_I2S_Handle PDMCC26XX_I2S_open(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_Params *params) +{ + /* Use union to save on stack allocation */ + HwiP_Params hwiParams; + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + Assert_isTrue(params->blockCount >= 3, NULL); + Assert_isTrue(handle, NULL); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable preemption while checking if the I2S is open. */ + uint32_t key = HwiP_disable(); + /* Check if the I2S is open already with the base addr. */ + if (object->isOpen == true) + { + HwiP_restore(key); + + return (NULL); + } + /* Mark the handle as in use */ + object->isOpen = true; + HwiP_restore(key); + + /* Initialize the I2S object */ + object->requestMode = params->requestMode; + object->requestTimeout = params->requestTimeout; + object->mallocFxn = params->mallocFxn; + object->freeFxn = params->freeFxn; + object->blockCount = params->blockCount; + object->blockSizeInSamples = params->blockSizeInSamples; + object->currentStream = params->currentStream; + object->currentStream->status = PDMCC26XX_I2S_STREAM_IDLE; + + /* The following are constants that apply to PDM */ + object->sampleRate = -1; /* If negative then use user configured clock division */ + object->audioClkCfg.wclkDiv = 16; /* I2S Word Clock divider override*/ + object->audioClkCfg.sampleOnPositiveEdge = PDMCC26XX_I2S_SampleEdge_Postive; /* I2S Sample Edge */ + object->audioClkCfg.wclkPhase = PDMCC26XX_I2S_WordClockPhase_Dual; /* I2S Word Clock Phase */ + object->audioClkCfg.wclkInverted = PDMCC26XX_I2S_ClockSource_Normal; /* I2S Invert Word Clock */ + object->audioClkCfg.wclkSource = PDMCC26XX_I2S_WordClockSource_Int; /* I2S Word Clock source */ + object->audioClkCfg.bclkDiv = 47; /* I2S Bit Clock divider override */ + object->audioClkCfg.reserved = 0; + object->audioClkCfg.bclkSource = PDMCC26XX_I2S_BitClockSource_Int; /* I2S Bit Clock source */ + object->audioClkCfg.cclkDiv = 6; /* I2S Controller Clock divider override */ + + object->audioPinCfg.bitFields.ad1Usage = PDMCC26XX_I2S_ADUsageDisabled; /* I2S AD1 usage (0: Disabled, 1: Input, 2: + Output) */ + object->audioPinCfg.bitFields.enableCclkPin = PDMCC26XX_I2S_GENERIC_DISABLED; /* I2S Enable Controller clock output + on pin */ + object->audioPinCfg.bitFields.reserved = 0; + object->audioPinCfg.bitFields.ad1NumOfChannels = 0; /* I2S AD1 number of channels (1 - 8). !Must match channel mask + */ + object->audioPinCfg.bitFields.ad1ChannelMask = PDMCC26XX_I2S_DISABLED_MODE; /* I2S AD1 Channel Mask */ + object->audioPinCfg.bitFields.ad0Usage = PDMCC26XX_I2S_ADUsageInput; /* I2S AD0 usage (0: Disabled, 1: Input, 2: + Output) */ + object->audioPinCfg.bitFields.enableWclkPin = PDMCC26XX_I2S_GENERIC_DISABLED; /* I2S Enable Word clock output on pin + */ + object->audioPinCfg.bitFields.enableBclkPin = PDMCC26XX_I2S_GENERIC_ENABLED; /* I2S Enable Bit clock output on pin + */ + object->audioPinCfg.bitFields.ad0NumOfChannels = 2; /* I2S AD0 number of channels (1 - 8). !Must match channel mask. + \sa PDM_NUM_OF_CHANNELS */ + object->audioPinCfg.bitFields.ad0ChannelMask = PDMCC26XX_I2S_STEREO_MODE; /* I2S AD0 Channel Mask */ + + object->audioFmtCfg.wordLength = PDMCC26XX_I2S_WordLength16; /* Number of bits per word (8-24). Exact for single + phase, max for dual phase */ + object->audioFmtCfg.sampleEdge = PDMCC26XX_I2S_PositiveEdge; /* Data and Word clock is samples, and clocked out, on + opposite edges of BCLK */ + object->audioFmtCfg.dualPhase = PDMCC26XX_I2S_SinglePhase; /* Selects dual- or single phase format (0: Single, 1: + Dual) */ + object->audioFmtCfg.memLen = PDMCC26XX_I2S_MemLen16bit; /* Size of each word stored to or loaded from memory (0: 16, + 1: 24) */ + object->audioFmtCfg.dataDelay = PDMCC26XX_I2S_FormatLJF; /* Number of BCLK perids between a WCLK edge and MSB of the + first word in a phase */ + + /* Find out how many channels are In and Out respectively */ + uint8_t totalNumberOfChannelsIn = 0; + totalNumberOfChannelsIn += object->audioPinCfg.bitFields.ad0NumOfChannels; + + object->blockSizeInBytes = (object->blockSizeInSamples * ((object->audioFmtCfg.memLen) ? 3 : 2) * + totalNumberOfChannelsIn); + + /* Setup queues now that we now whether they are needed */ + Queue_construct(&i2sBlockFullQueueStruct, NULL); + i2sBlockFullQueue = Queue_handle(&i2sBlockFullQueueStruct); + + Queue_construct(&i2sBlockEmptyQueueStruct, NULL); + i2sBlockEmptyQueue = Queue_handle(&i2sBlockEmptyQueueStruct); + + /* Try to allocate memory for the PDM buffers */ + if (!PDMCC26XX_I2S_allocateBuffers(handle)) + { + HwiP_restore(key); + + return NULL; + } + + /* Register power dependency - i.e. power up and enable clock for I2S. */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Configure IOs after hardware has been initialized */ + PDMCC26XX_I2S_initIO(handle); + + /* Create the Hwi for this I2S peripheral. */ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (UArg)handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int)hwAttrs->intNum, PDMCC26XX_I2S_hwiFxn, &hwiParams); + + /* Create a semaphore to block task execution while stopping the stream */ + SemaphoreP_constructBinary(&(object->semStopping), 0); + + /* Check the transfer mode */ + if (object->requestMode == PDMCC26XX_I2S_MODE_BLOCKING) + { + /* + * Create a semaphore to block task execution for the duration of the + * I2S transfer. This is a counting semaphore. + */ + SemaphoreP_construct(&(object->blockComplete), 0, NULL); + + /* Store internal callback function */ + object->callbackFxn = PDMCC26XX_I2S_callback; + } + else + { + /* Check to see if a callback function was defined for async mode */ + Assert_isTrue(params->callbackFxn != NULL, NULL); + + /* Save the callback function pointer */ + object->callbackFxn = params->callbackFxn; + } + + return (handle); +} + +/* + * ======== PDMCC26XX_I2S_deallocateBuffers ======== + * @pre Function assumes that the handle is not NULL + */ +static void PDMCC26XX_I2S_deallocateBuffers(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + + Assert_isTrue(handle, NULL); + Assert_isTrue(i2sBlockEmptyQueue, NULL); + Assert_isTrue(i2sBlockFullQueue, NULL); + + /* Get the pointer to the object */ + object = handle->object; + + /* If we do not use a critical section, the thread may be pre-empted between the Queue_empty() check and the + * Queue_dequeue call. */ + uint32_t key = HwiP_disable(); + + /* Empty the available queue and free the memory of the queue elements and the buffers */ + while (!Queue_empty(i2sBlockEmptyQueue)) + { + PDMCC26XX_I2S_QueueNode *availableNode = Queue_dequeue(i2sBlockEmptyQueue); + /* Free up memory used for PCM data buffer */ + object->freeFxn(availableNode->buffer, object->blockSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(availableNode, sizeof(PDMCC26XX_I2S_QueueNode)); + } + + /* Empty the ready queue and free the memory of the queue elements and the buffers */ + while (!Queue_empty(i2sBlockFullQueue)) + { + PDMCC26XX_I2S_QueueNode *readyNode = Queue_dequeue(i2sBlockFullQueue); + /* Free up memory used for PCM data buffer */ + object->freeFxn(readyNode->buffer, object->blockSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(readyNode, sizeof(PDMCC26XX_I2S_QueueNode)); + } + + /* Make sure we do not keep dangling pointers alive */ + if (i2sBlockActive) + { + /* Free up memory used for PCM data buffer */ + object->freeFxn(i2sBlockActive->buffer, object->blockSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(i2sBlockActive, sizeof(PDMCC26XX_I2S_QueueNode)); + i2sBlockActive = NULL; + } + + /* Make sure we do not keep dangling pointers alive */ + if (i2sBlockNext) + { + /* Free up memory used for PCM data buffer */ + object->freeFxn(i2sBlockNext->buffer, object->blockSizeInBytes); + /* Then free up memory used by the queue element */ + object->freeFxn(i2sBlockNext, sizeof(PDMCC26XX_I2S_QueueNode)); + i2sBlockNext = NULL; + } + + HwiP_restore(key); +} + +/* + * ======== PDMCC26XX_I2S_allocateBuffers ======== + * @pre Function assumes that the handle is not NULL + */ +static bool PDMCC26XX_I2S_allocateBuffers(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + + Assert_isTrue(handle, NULL); + Assert_isTrue(i2sBlockEmptyQueue, NULL); + Assert_isTrue(i2sBlockFullQueue, NULL); + + /* Get the pointer to the object */ + object = handle->object; + + Assert_isTrue(object->isOpen, NULL); + + /* Allocate the PDM block buffers and queue elements. The application provided malloc and free functions permit for + * both static and dynamic allocation. The PDM block buffers are allocated individually. Despite the increased + * book-keeping overhead incurred for this in the malloc function, the reduced likelyhood of heap fragmentation is + * worth it. When using a static allocation malloc implementation, there should be no extra cost incurred from + * requesting block buffers individually. The same code that will be in the allocation function, would otherwise + * reside in this driver. + */ + uint8_t i = 0; + for (i = 0; i < object->blockCount; i++) + { + PDMCC26XX_I2S_QueueNode *tmpNode; + tmpNode = object->mallocFxn(sizeof(PDMCC26XX_I2S_QueueNode)); + + if (tmpNode) + { + tmpNode->buffer = object->mallocFxn(object->blockSizeInBytes); + if (tmpNode->buffer) + { + /* Enqueue the PDM block in the available queue if the allocation was successful */ + Queue_put(i2sBlockEmptyQueue, &tmpNode->queueElement); + } + else + { + /* Otherwise, free the node memory, unravel all other allocations, and fail the driver initialsation */ + object->freeFxn(tmpNode, sizeof(PDMCC26XX_I2S_QueueNode)); + PDMCC26XX_I2S_deallocateBuffers(handle); + return false; + } + } + else + { + /* Unravel all other allocations and fail the function */ + PDMCC26XX_I2S_deallocateBuffers(handle); + return false; + } + } + + return true; +} + +/* + * ======== PDMCC26XX_I2S_close ======== + * @pre Function assumes that the handle is not NULL + */ +void PDMCC26XX_I2S_close(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + hwAttrs = handle->hwAttrs; + object = handle->object; + + /* Deallocate pins */ + PDMCC26XX_I2S_finalizeIO(handle); + + /* Disable the I2S */ + I2SDisable(hwAttrs->baseAddr); + + /* Destroy the Hwi */ + HwiP_destruct(&(object->hwi)); + + /* Release power dependency on I2S. */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Destroy the stopping semaphore */ + SemaphoreP_destruct(&(object->semStopping)); + + if (object->requestMode == PDMCC26XX_I2S_MODE_BLOCKING) + { + /* Destroy the block complete semaphore */ + SemaphoreP_destruct(&(object->blockComplete)); + } + + /* Flush any unprocessed I2S data */ + PDMCC26XX_I2S_deallocateBuffers(handle); + + Queue_destruct(&i2sBlockFullQueueStruct); + Queue_destruct(&i2sBlockEmptyQueueStruct); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== PDMCC26XX_I2S_hwiFxn ======== + * ISR for the I2S + */ +static void PDMCC26XX_I2S_hwiFxn(UArg arg) +{ + PDMCC26XX_I2S_StreamNotification *notification; + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + uint32_t intStatus; + + /* Get the pointer to the object and hwAttrs */ + object = ((PDMCC26XX_I2S_Handle)arg)->object; + hwAttrs = ((PDMCC26XX_I2S_Handle)arg)->hwAttrs; + + Assert_isTrue(i2sBlockEmptyQueue, NULL); + Assert_isTrue(i2sBlockFullQueue, NULL); + + /* Get the interrupt status of the I2S controller */ + intStatus = I2SIntStatus(hwAttrs->baseAddr, true); + I2SIntClear(hwAttrs->baseAddr, intStatus); + + if (intStatus & I2S_IRQMASK_AIF_DMA_IN) + { + Assert_isTrue(i2sBlockActive, NULL); + + /* Move completed buffer to ready queue */ + Queue_put(i2sBlockFullQueue, &i2sBlockActive->queueElement); + /* Setup next active buffer */ + i2sBlockActive = i2sBlockNext; + /* Mark next buffer as empty*/ + i2sBlockNext = NULL; + + if (object->currentStream->status == PDMCC26XX_I2S_STREAM_STOPPING) + { + /* Part of shut down sequence*/ + object->currentStream->status = PDMCC26XX_I2S_STREAM_STOPPED; + } + else if (object->currentStream->status != PDMCC26XX_I2S_STREAM_STOPPED) + { + if (!Queue_empty(i2sBlockEmptyQueue)) + { + /* There is an empty buffer available. */ + i2sBlockNext = Queue_get(i2sBlockEmptyQueue); + object->currentStream->status = PDMCC26XX_I2S_STREAM_BUFFER_READY; + } + else + { + /* If there is no empty buffer available, there should be full buffers we could drop. */ + Assert_isTrue(!Queue_empty(i2sBlockFullQueue), NULL); + /* The PDM driver did not process the buffers in time. The I2S module needs to drop + * some old data and notify the PDM driver that it did so. + */ + i2sBlockNext = Queue_get(i2sBlockFullQueue); + object->currentStream->status = PDMCC26XX_I2S_STREAM_BUFFER_DROPPED; + } + Assert_isTrue(i2sBlockNext, NULL); + + I2SPointerSet(hwAttrs->baseAddr, true, (uint32_t *)i2sBlockNext->buffer); + + /* Use a temporary stream pointer in case the callback function + * attempts to perform another PDMCC26XX_I2S_bufferRequest call + */ + notification = object->currentStream; + + /* Notify caller about availability of buffer */ + object->callbackFxn((PDMCC26XX_I2S_Handle)arg, notification); + } + } + + /* Error handling: + * Overrun in the RX Fifo -> at least one sample in the shift + * register has been discarded */ + if (intStatus & I2S_IRQMASK_PTR_ERR) + { + /* disable the interrupt */ + I2SIntDisable(hwAttrs->baseAddr, I2S_INT_PTR_ERR); + /* Check if we are expecting this interrupt as part of stopping */ + if (object->currentStream->status == PDMCC26XX_I2S_STREAM_STOPPED) + { + /* This happened because PDMCC26XX_I2S_stopStream was called for some reason + * Post the semaphore + */ + SemaphoreP_post(&(object->semStopping)); + } + else + { + __asm(" NOP"); + object->currentStream->status = PDMCC26XX_I2S_STREAM_ERROR; + /* Use a temporary stream pointer in case the callback function + * attempts to perform another PDMCC26XX_I2S_bufferRequest call + */ + notification = object->currentStream; + /* Notify caller about availability of buffer */ + object->callbackFxn((PDMCC26XX_I2S_Handle)arg, notification); + } + } +} + +/* + * ======== PDMCC26XX_I2S_startStream ======== + * @pre Function assumes that handle is not NULL + */ +bool PDMCC26XX_I2S_startStream(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + Assert_isTrue(handle, NULL); + Assert_isTrue(i2sBlockFullQueue, NULL); + Assert_isTrue(i2sBlockEmptyQueue, NULL); + + /* Get the pointer to the object and hwAttr*/ + object = handle->object; + hwAttrs = handle->hwAttrs; + + Assert_isTrue(object->isOpen, NULL); + + /* Disable preemption while checking if a transfer is in progress */ + uint32_t key = HwiP_disable(); + if (object->currentStream->status != PDMCC26XX_I2S_STREAM_IDLE) + { + HwiP_restore(key); + + /* Flag that the transfer failed to start */ + object->currentStream->status = PDMCC26XX_I2S_STREAM_FAILED; + + /* Transfer is in progress */ + return false; + } + + /* Make sure to flag that a stream is now active */ + object->currentStream->status = PDMCC26XX_I2S_STREAM_STARTED; + + i2sBlockActive = Queue_dequeue(i2sBlockEmptyQueue); + i2sBlockNext = Queue_dequeue(i2sBlockEmptyQueue); + + /* Configure the hardware module */ + PDMCC26XX_I2S_initHw(handle); + + key = HwiP_disable(); + /* Configuring sample stamp generator will trigger the audio stream to start */ + I2SSampleStampConfigure(hwAttrs->baseAddr, true, false); + HwiP_restore(key); + + /* Configure buffers */ + I2SBufferConfig(hwAttrs->baseAddr, + (uint32_t)(i2sBlockActive->buffer), + 0U, + object->blockSizeInSamples, + PDMCC26XX_I2S_DEFAULT_SAMPLE_STAMP_MOD); + /* Enable the I2S module. This will set first buffer and DMA length */ + I2SEnable(hwAttrs->baseAddr); + + /* Kick off clocks */ + PRCMAudioClockEnable(); + PRCMLoadSet(); + + /* Second buffer is then set in hardware after DMA length is set */ + I2SPointerSet(hwAttrs->baseAddr, true, (uint32_t *)i2sBlockNext->buffer); + + HwiP_restore(key); + + /* Enable the RX overrun interrupt in the I2S module */ + I2SIntEnable(hwAttrs->baseAddr, I2S_INT_DMA_IN | I2S_INT_PTR_ERR); + + /* Clear internal pending interrupt flags */ + I2SIntClear(I2S0_BASE, I2S_INT_ALL); + + /* Enable samplestamp */ + I2SSampleStampEnable(hwAttrs->baseAddr); + + /* Clear potential pending I2S interrupt to CM3 */ + HwiP_clearInterrupt(INT_I2S_IRQ); + + /* Enable I2S interrupt to CM3 */ + HwiP_enableInterrupt(INT_I2S_IRQ); + + return true; +} + +/* + * ======== PDMCC26XX_I2S_stopStream ======== + * @pre Function assumes that handle is not NULL + */ +bool PDMCC26XX_I2S_stopStream(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + Assert_isTrue(handle, NULL); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + Assert_isTrue(object->isOpen, NULL); + + /* Check if a transfer is in progress */ + uint32_t key = HwiP_disable(); + + /* Check if there is an active stream */ + if ((object->currentStream->status == PDMCC26XX_I2S_STREAM_STOPPING) || + (object->currentStream->status == PDMCC26XX_I2S_STREAM_STOPPED) || + (object->currentStream->status == PDMCC26XX_I2S_STREAM_IDLE)) + { + + HwiP_restore(key); + return false; + } + + /* Begin stopping sequence, if not stopped because of error */ + if (object->currentStream->status != PDMCC26XX_I2S_STREAM_ERROR) + { + object->currentStream->status = PDMCC26XX_I2S_STREAM_STOPPING; + + /* Reenable the interrupt as it may have been disabled during an error*/ + I2SIntEnable(hwAttrs->baseAddr, I2S_INT_PTR_ERR); + + HwiP_restore(key); + + /* Wait for I2S module to complete all buffers*/ + if (SemaphoreP_OK != SemaphoreP_pend(&(object->semStopping), 40000)) + { + object->currentStream->status = PDMCC26XX_I2S_STREAM_FAILED_TO_STOP; + return false; + } + } + + /* restore HWI */ + HwiP_restore(key); + + /* Flush the blockFullQueue and move those elements to the blockEmptyQueue. + * Since this function shuts down the driver synchronously by letting it run out + * of buffers, we do not need to worry about losing interesting data. + */ + while (!Queue_empty(i2sBlockFullQueue)) + { + PDMCC26XX_I2S_QueueNode *tmpNode = Queue_get(i2sBlockFullQueue); + Queue_put(i2sBlockEmptyQueue, &tmpNode->queueElement); + } + + /* Disable the I2S module */ + I2SDisable(hwAttrs->baseAddr); + + /* Turn off clocks */ + PRCMAudioClockDisable(); + PRCMLoadSet(); + + /* Disable and clear any pending interrupts */ + I2SIntDisable(hwAttrs->baseAddr, I2S_INT_ALL); + I2SIntClear(hwAttrs->baseAddr, I2S_INT_ALL); + HwiP_clearInterrupt(INT_I2S_IRQ); + HwiP_disableInterrupt(INT_I2S_IRQ); + + /* Indicate we are done with this stream */ + object->currentStream->status = PDMCC26XX_I2S_STREAM_IDLE; + + /* Stream was successfully stopped */ + return true; +} + +/* + * ======== PDMCC26XX_I2S_requestBuffer ======== + * @pre Function assumes that stream has started and that bufferRequest is not NULL + */ +bool PDMCC26XX_I2S_requestBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRequest *bufferRequest) +{ + PDMCC26XX_I2S_Object *object; + bool retVal = false; + + Assert_isTrue(handle, NULL); + Assert_isTrue(bufferRequest, NULL); + + /* Get the pointer to the object */ + object = handle->object; + + Assert_isTrue(object->isOpen, NULL); + + if (object->requestMode == PDMCC26XX_I2S_MODE_BLOCKING) + { + if (SemaphoreP_OK != SemaphoreP_pend(&(object->blockComplete), object->requestTimeout)) + { + /* Stop stream, if we experience a timeout */ + PDMCC26XX_I2S_stopStream(handle); + + bufferRequest->status = object->currentStream->status; + + return false; + } + }; + bufferRequest->bufferHandleIn = NULL; + /* When in callback mode we typically expect the user to call this + * after being notified of available buffers. Hence we may directly + * check queue and dequeue buffer + */ + if (!Queue_empty(i2sBlockFullQueue)) + { + PDMCC26XX_I2S_QueueNode *readyNode = Queue_get(i2sBlockFullQueue); + bufferRequest->bufferIn = readyNode->buffer; + bufferRequest->status = object->currentStream->status; + bufferRequest->bufferHandleIn = readyNode; + retVal = true; + } + + return retVal; +} + +/* + * ======== PDMCC26XX_I2S_releaseBuffer ======== + * @pre Function assumes bufferRelease contains a valid bufferHandle (identical to + * the one provided in the bufferRequest in PDMCC26XX_I2S_requestBuffer + */ +void PDMCC26XX_I2S_releaseBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRelease *bufferRelease) +{ + Assert_isTrue(handle, NULL); + Assert_isTrue(bufferRelease, NULL); + Assert_isTrue(bufferRelease->bufferHandleIn, NULL); + Assert_isTrue(i2sBlockEmptyQueue, NULL); + + /* Place released buffer back in available queue */ + Queue_put(i2sBlockEmptyQueue, &((PDMCC26XX_I2S_QueueNode *)bufferRelease->bufferHandleIn)->queueElement); +} + +/* + * ======== PDMCC26XX_I2S_callback ======== + * Callback function for when the I2S is in PDMCC26XX_I2S_MODE_BLOCKING + * + * @pre Function assumes that the handle is not NULL + */ +static void PDMCC26XX_I2S_callback(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_StreamNotification *msg) +{ + PDMCC26XX_I2S_Object *object; + + /* Get the pointer to the object */ + object = handle->object; + + /* Post the semaphore */ + SemaphoreP_post(&(object->blockComplete)); +} + +/* + * ======== PDMCC26XX_I2S_hwInit ======== + * This functions initializes the I2S hardware module. + * + * @pre Function assumes that the I2S handle is pointing to a hardware + * module which has already been opened. + */ +static void PDMCC26XX_I2S_initHw(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Disable I2S operation */ + I2SDisable(hwAttrs->baseAddr); + + /* Configure Audio format */ + I2SAudioFormatConfigure(hwAttrs->baseAddr, *(uint32_t *)&object->audioFmtCfg, object->audioFmtCfg.dataDelay); + + /* Configure Channels */ + I2SChannelConfigure(hwAttrs->baseAddr, + object->audioPinCfg.driverLibParams.ad0, + object->audioPinCfg.driverLibParams.ad1); + + /* Configure Clocks*/ + uint32_t clkCfg = object->audioClkCfg.wclkSource; + clkCfg |= (object->audioClkCfg.wclkInverted) ? I2S_INVERT_WCLK : 0; + I2SClockConfigure(hwAttrs->baseAddr, clkCfg); + uint32_t ctlDiv = object->audioClkCfg.cclkDiv; + uint32_t bitDiv = object->audioClkCfg.bclkDiv; + uint32_t wordDiv = object->audioClkCfg.wclkDiv; + clkCfg = (object->audioClkCfg.wclkPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S); + clkCfg |= (object->audioClkCfg.sampleOnPositiveEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S); + if ((object->sampleRate >= I2S_SAMPLE_RATE_16K) && (object->sampleRate <= I2S_SAMPLE_RATE_48K)) + { + PRCMAudioClockConfigSet(clkCfg, object->sampleRate); + } + else + { + PRCMAudioClockConfigSetOverride(clkCfg, ctlDiv, bitDiv, wordDiv); + } + /* TODO: Replace this with Driverlib code */ + HWREG(PRCM_BASE + PRCM_O_I2SBCLKSEL) = (object->audioClkCfg.bclkSource & PRCM_I2SBCLKSEL_SRC_M); + /* Apply configuration */ + PRCMLoadSet(); + + /* Disable I2S module interrupts */ + I2SIntDisable(hwAttrs->baseAddr, I2S_INT_ALL); +} + +/* + * ======== PDMCC26XX_I2S_initIO ======== + * This functions initializes the I2S IOs. + * + * @pre Function assumes that the I2S handle is pointing to a hardware + * module which has already been opened. + */ +static void PDMCC26XX_I2S_initIO(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Configure IOs */ + /* Build local list of pins, allocate through PIN driver and map HW ports */ + if (object->audioPinCfg.bitFields.enableCclkPin) + { + GPIO_setConfigAndMux(hwAttrs->cclkPin, GPIO_CFG_OUTPUT, IOC_PORT_MCU_I2S_MCLK); + } + if (object->audioPinCfg.bitFields.enableWclkPin) + { + GPIO_setConfigAndMux(hwAttrs->wclkPin, GPIO_CFG_OUTPUT, IOC_PORT_MCU_I2S_WCLK); + } + if (object->audioPinCfg.bitFields.enableBclkPin) + { + GPIO_setConfigAndMux(hwAttrs->bclkPin, GPIO_CFG_OUTPUT, IOC_PORT_MCU_I2S_BCLK); + } + if (object->audioPinCfg.bitFields.ad0Usage == PDMCC26XX_I2S_ADUsageInput) + { + GPIO_setConfigAndMux(hwAttrs->ad0Pin, GPIO_CFG_IN_NOPULL, IOC_PORT_MCU_I2S_AD0); + } + else if (object->audioPinCfg.bitFields.ad0Usage == PDMCC26XX_I2S_ADUsageOutput) + { + GPIO_setConfigAndMux(hwAttrs->ad0Pin, GPIO_CFG_OUTPUT, IOC_PORT_MCU_I2S_AD0); + } +} + +static void PDMCC26XX_I2S_finalizeIO(PDMCC26XX_I2S_Handle handle) +{ + PDMCC26XX_I2S_Object *object; + PDMCC26XX_I2S_HWAttrs const *hwAttrs; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* Configure IOs */ + /* Build local list of pins, allocate through PIN driver and map HW ports */ + if (object->audioPinCfg.bitFields.enableCclkPin) + { + GPIO_resetConfig(hwAttrs->cclkPin); + } + if (object->audioPinCfg.bitFields.enableWclkPin) + { + GPIO_resetConfig(hwAttrs->wclkPin); + } + if (object->audioPinCfg.bitFields.enableBclkPin) + { + GPIO_resetConfig(hwAttrs->bclkPin); + } + if (object->audioPinCfg.bitFields.ad0Usage != PDMCC26XX_I2S_ADUsageDisabled) + { + GPIO_resetConfig(hwAttrs->ad0Pin); + } +} + +/* + * ======== i2sPostNotify ======== + * This functions is called to notify the I2S driver of an ongoing transition + * out of sleep mode. + * + * @pre Function assumes that the I2S handle (clientArg) is pointing to a + * hardware module which has already been opened. + */ +int i2sPostNotify(char eventType, uint32_t clientArg) +{ + PDMCC26XX_I2S_Handle i2sHandle; + + /* Get the pointers to I2S objects */ + i2sHandle = (PDMCC26XX_I2S_Handle)clientArg; + + /* Reconfigure the hardware when returning from standby */ + PDMCC26XX_I2S_initHw(i2sHandle); + + return Power_NOTIFYDONE; +} diff --git a/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.h b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.h new file mode 100644 index 00000000..cb2ab34c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pdm/PDMCC26XX_util.h @@ -0,0 +1,884 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PDMCC26XX_util.h + * + * @brief PDM utility includes helper functions for configuring the CC26XX I2S + * controller. + * + * The PDMCC26XX utility header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * # Overview # + * This utility file is written specifically for the I2S module on CC26XX. The + * user should be aware that although this HW module is called I2S it is a + * highly configurable audio interface module. I2S is only one of many + * configurations. + * + * + * ============================================================================ + */ + +#ifndef ti_drivers_i2s_PDMCC26XX_I2S__include +#define ti_drivers_i2s_PDMCC26XX_I2S__include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Define to control debug mode + * + * Production code should set this to xI2S_DEBUG. To enable debug mode + * rename the define to \b I2S_DEBUG. + */ +#define xI2S_DEBUG + +/*! + * At least three elements must exist for good flow in driver + */ +#define PDMCC26XX_I2S_MIN_ALLOWED_QUEUE_SIZE 3 + +/*! + * PDM block overhead size in number of bytes --> sizeof(PDMCC26XX_I2S_QueueNode) + */ +#ifdef I2S_DEBUG + #define I2S_BLOCK_OVERHEAD_IN_BYTES 16 +#else // I2S_DEBUG + #define I2S_BLOCK_OVERHEAD_IN_BYTES 12 +#endif // I2S_DEBUG + +/*! Return code when PDMCC26XX_I2S_control() was successful. */ +#define PDMCC26XX_I2S_CMD_SUCCESS 0 +/*! Return code when a I2S command or function is undefined/not-implemented. */ +#define PDMCC26XX_I2S_CMD_UNDEFINED -1 +/*! Return code when PDMCC26XX_I2S_control() was unsuccessful. */ +#define PDMCC26XX_I2S_CMD_NO_SUCCESS -2 + +/*! Generic macro for disabled */ +#define PDMCC26XX_I2S_GENERIC_DISABLED 0 +/*! Generic macro for enabled */ +#define PDMCC26XX_I2S_GENERIC_ENABLED 1 + +/*! + * @brief + * PDMCC26XX_I2S_MallocFxn is a function pointer for the malloc function to + * be used by the driver. + */ +typedef void *(*PDMCC26XX_I2S_MallocFxn)(size_t memSize); + +/*! + * @brief + * PDMCC26XX_I2S_FreeFxn is a function pointer for the free function to + * be used by the driver. This is needed for memory clean up, if something goes + * wrong. + */ +typedef void (*PDMCC26XX_I2S_FreeFxn)(void *ptr, size_t memSize); + +/*! + * @brief + * The PDMCC26XX_I2S_Config structure contains a set of pointers used to characterize + * the PDMCC26XX_I2S driver implementation. + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} PDMCC26XX_I2S_Config; + +/*! + * @brief A handle that is returned from a PDMCC26XX_I2S_open() call. + */ +typedef PDMCC26XX_I2S_Config *PDMCC26XX_I2S_Handle; + +/*! + * @brief Status codes that are set by the I2S driver. + */ +typedef enum +{ + PDMCC26XX_I2S_STREAM_IDLE = 0, /*!< Idle mode. Stream not started */ + PDMCC26XX_I2S_STREAM_STARTED, /*!< Stream started, no buffer yet available */ + PDMCC26XX_I2S_STREAM_CANCELED, /*!< Unused state. */ + PDMCC26XX_I2S_STREAM_FAILED, /*!< PDMCC26XX_I2S_startStream() called while stream + * is already running + */ + PDMCC26XX_I2S_STREAM_ERROR, /*!< No pointer available when one was expected, + * meaning the driver failed to provide new + * pointer and PDMCC26XX_I2S_stopStream() was not + * called + */ + PDMCC26XX_I2S_STREAM_BUFFER_READY, /*!< Buffer ready, either IN or OUT or + * both, whichever are expected + */ + PDMCC26XX_I2S_STREAM_BUFFER_DROPPED, /*!< A new buffer is ready but the old ones were not + * processed in time. The oldest buffer was dropped + * to provide space for newer data. + */ + PDMCC26XX_I2S_STREAM_STOPPING, /*!< PDMCC26XX_I2S_stopStream() is called, a + * graceful shutdown procedure is started + */ + PDMCC26XX_I2S_STREAM_STOPPED, /*!< Driver transitioned from Stopping to + * Stopped state during graceful shutdown. Now + * a pointer error is expected, and upon it a + * semaphore is set allowing + * PDMCC26XX_I2S_stopStream() to return + */ + PDMCC26XX_I2S_STREAM_FAILED_TO_STOP /*!< PDMCC26XX_I2S_stopStream() was called, + * but driver timed out trying to gracefully + * shutdown + */ +} PDMCC26XX_I2S_Status; + +/*! + * @brief + * Definitions for various PDMCC26XX_I2S modes of operation. + */ +typedef enum +{ + PDMCC26XX_I2S_PDM = 0, /*!< PDMCC26XX_I2S in PDM microphone mode */ + PDMCC26XX_I2S_I2S = 1 /*!< PDMCC26XX_I2S in I2S mode */ +} PDMCC26XX_I2S_Mode; + +/*! + * We don't use sample stamp generator, but we can't start without + * enabling it and configuring the trigger. This is because the + * trigger also starts the audio stream + * Since we don't use it we keep the word period at its max 2^16 + * For the driverlib which runs a modulo on the word period we can + * set the modulo to 0xFFFF to avoid issues with division by zero. + */ +#define PDMCC26XX_I2S_DEFAULT_SAMPLE_STAMP_MOD 0x0000FFFF + +/*! + * Definitions for different I2S Word Clock phase settings. + * + * Defines how WCLK division ratio is calculated to generate different + * duty cycles. + * \sa I2SWCLKDIV.WDIV + * + * Macro | Value | + * ------------------------------------------- | ------| + * PDMCC26XX_I2S_WordClockPhase_Single | 0 | + * PDMCC26XX_I2S_WordClockPhase_Dual | 1 | + * PDMCC26XX_I2S_WordClockPhase_UserDefined | 2 | + */ +#define PDMCC26XX_I2S_WordClockPhase_Single 0 +/*! + * \sa PDMCC26XX_I2S_WordClockPhase_Single + */ +#define PDMCC26XX_I2S_WordClockPhase_Dual 1 +/*! + * \sa PDMCC26XX_I2S_WordClockPhase_Single + */ +#define PDMCC26XX_I2S_WordClockPhase_UserDefined 2 + +/*! + * Definitions to set sample edge + * + * Macro | Value | + * ----------------------------------- | ------| + * PDMCC26XX_I2S_SampleEdge_Negative | 0 | + * PDMCC26XX_I2S_SampleEdge_Postive | 1 | + */ +#define PDMCC26XX_I2S_SampleEdge_Negative 0 +/*! + * \sa PDMCC26XX_I2S_SampleEdge_Negative + */ +#define PDMCC26XX_I2S_SampleEdge_Postive 1 + +/*! + * Definitions different I2S Word Clock source settings. + * + * Macro | Value | + * ----------------------------------- | ------| + * PDMCC26XX_I2S_WordClockSource_Ext | 0 | + * PDMCC26XX_I2S_WordClockSource_Int | 1 | + */ +#define PDMCC26XX_I2S_WordClockSource_Ext 1 +/*! + * \sa PDMCC26XX_I2S_WordClockSource_Ext + */ +#define PDMCC26XX_I2S_WordClockSource_Int 2 + +/*! + * Definitions different I2S Bit Clock source settings. + * + * Macro | Value | + * ----------------------------------- | ------| + * PDMCC26XX_I2S_BitClockSource_Ext | 0 | + * PDMCC26XX_I2S_BitClockSource_Int | 1 | + */ +#define PDMCC26XX_I2S_BitClockSource_Ext 0 +/*! + * \sa PDMCC26XX_I2S_BitClockSource_Ext + */ +#define PDMCC26XX_I2S_BitClockSource_Int 1 + +/*! + * Definitions to either invert I2S word or bit clock or not + * + * Macro | Value | + * ----------------------------------- | ------| + * PDMCC26XX_I2S_ClockSource_Normal | 0 | + * PDMCC26XX_I2S_ClockSource_Inverted | 1 | + */ +#define PDMCC26XX_I2S_ClockSource_Normal 0 +/*! + * \sa PDMCC26XX_I2S_ClockSource_Normal + */ +#define PDMCC26XX_I2S_ClockSource_Inverted 1 + +/*! + * PDMCC26XX_I2S Audio Data Pin Usage. + * + * Macro | Details | + * --------------------------- | --------------| + * PDMCC26XX_I2S_ADUsageDisabled | Disabled | + * PDMCC26XX_I2S_ADUsageInput | Input | + * PDMCC26XX_I2S_ADUsageOutput | Output | + */ +#define PDMCC26XX_I2S_ADUsageDisabled 0 +/*! + * \sa PDMCC26XX_I2S_ADUsageDisabled + */ +#define PDMCC26XX_I2S_ADUsageInput 1 +/*! + * \sa PDMCC26XX_I2S_ADUsageDisabled + */ +#define PDMCC26XX_I2S_ADUsageOutput 2 + +/*! + * PDMCC26XX_I2S Audio Channel Masks. + * + * Macro | Value | Usage | + * --------------------------- | --------------|-------------------------------| + * PDMCC26XX_I2S_CHAN0_ACT | 0x00000001 | OR in to enable channel 0 | + * PDMCC26XX_I2S_CHAN1_ACT | 0x00000002 | OR in to enable channel 1 | + * PDMCC26XX_I2S_CHAN2_ACT | 0x00000004 | OR in to enable channel 2 | + * PDMCC26XX_I2S_CHAN3_ACT | 0x00000008 | OR in to enable channel 3 | + * PDMCC26XX_I2S_CHAN4_ACT | 0x00000010 | OR in to enable channel 4 | + * PDMCC26XX_I2S_CHAN5_ACT | 0x00000020 | OR in to enable channel 5 | + * PDMCC26XX_I2S_CHAN6_ACT | 0x00000040 | OR in to enable channel 6 | + * PDMCC26XX_I2S_CHAN7_ACT | 0x00000080 | OR in to enable channel 7 | + * PDMCC26XX_I2S_MONO_MODE | 0x00000001 | Use to set Mono mode | + * PDMCC26XX_I2S_STEREO_MODE | 0x00000003 | Use to set Stereo mode | + * PDMCC26XX_I2S_DISABLED_MODE | 0x00000000 | Use to disable | + * PDMCC26XX_I2S_CHAN_CFG_MASK | 0x000000FF | Use to mask out invalid | + */ +#define PDMCC26XX_I2S_CHAN0_ACT 0x00000001 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN1_ACT 0x00000002 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN2_ACT 0x00000004 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN3_ACT 0x00000008 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN4_ACT 0x00000010 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN5_ACT 0x00000020 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN6_ACT 0x00000040 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN7_ACT 0x00000080 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_MONO_MODE 0x00000001 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_STEREO_MODE 0x00000003 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_DISABLED_MODE 0x00000000 +/*! \sa PDMCC26XX_I2S_CHAN0_ACT */ +#define PDMCC26XX_I2S_CHAN_CFG_MASK 0x000000FF + +/*! + * PDMCC26XX_I2S data word length is used to determine how bits to transfer per word. + * + * Macro | Value | Usage | + * --------------------------- | ------|---------------------------------------| + * PDMCC26XX_I2S_WordLengthMin | 8 | Minimum transfer length is 8 bits | + * PDMCC26XX_I2S_WordLength16 | 16 | A typical transfer length is 16 bits | + * PDMCC26XX_I2S_WordLengthMax | 24 | Maximum transfer length is 24 bits | + */ +#define PDMCC26XX_I2S_WordLengthMin 8 +/*! \sa PDMCC26XX_I2S_WordLengthMin */ +#define PDMCC26XX_I2S_WordLength16 16 +/*! \sa PDMCC26XX_I2S_WordLengthMin */ +#define PDMCC26XX_I2S_WordLengthMax 24 + +/*! + * PDMCC26XX_I2S Phase is set to select Dual or Single phase format + * + * Macro | Value | + * --------------------------- | ------| + * PDMCC26XX_I2S_SinglePhase | 0 | + * PDMCC26XX_I2S_DualPhase | 1 | + */ +#define PDMCC26XX_I2S_SinglePhase 0 +/*! \sa PDMCC26XX_I2S_SinglePhase */ +#define PDMCC26XX_I2S_DualPhase 1 + +/*! + * PDMCC26XX_I2S Sample Edge is set to control what edge to sample and clock out + * data on. + * + * Macro | Value | + * --------------------------- | ------| + * PDMCC26XX_I2S_NegativeEdge | 0 | + * PDMCC26XX_I2S_PositiveEdge | 1 | + */ +#define PDMCC26XX_I2S_NegativeEdge 0 +/*! \sa PDMCC26XX_I2S_NegativeEdge */ +#define PDMCC26XX_I2S_PositiveEdge 1 + +/*! + * PDMCC26XX_I2S data word size is used to determine how to configure the + * I2S data transfers to/from memory. + * + * Macro | Value | Usage | + * --------------------------- | ------|-------------------------------| + * PDMCC26XX_I2S_MemLen16bit | 0 | sample 16 bits per word | + * PDMCC26XX_I2S_MemLen24bit | 1 | sample 24 bits per word | + * + * PDMCC26XX_I2S_MemLen16bit: sample 16 bits per word + * PDMCC26XX_I2S_MemLen24bit: sample 24 bits per word + */ +#define PDMCC26XX_I2S_MemLen16bit 0 +/*! \sa PDMCC26XX_I2S_MemLen16bit */ +#define PDMCC26XX_I2S_MemLen24bit 1 + +/*! + * PDMCC26XX_I2S Data Delay, which translates into format (LJF, I2S/DSP, RJF). + * + * This field can be set to any 8 bit value. The macros are just defined + * for convenience. Left justified mode means that sampling should start + * immediately. For right justified mode the data delay depends on how + * many samples should be taken per word. It is an alignment. + * + * I2S is a special mode that defines that no sample occur on first edge, + * hence there is one period data delay. + * + * Macro | Value | Usage | + * --------------------------- | ------|-------------------------------| + * PDMCC26XX_I2S_FormatLJF | 0 | no data delay | + * PDMCC26XX_I2S_FormatI2SandDSP | 1 | one period data delay | + * PDMCC26XX_I2S_FormatRJFmin | 2 | two periods data delay | + * PDMCC26XX_I2S_FormatRJFmax | 255 | 255 periods data delay | + */ +#define PDMCC26XX_I2S_FormatLJF 0 +/*! \sa PDMCC26XX_I2S_FormatLJF */ +#define PDMCC26XX_I2S_FormatI2SandDSP 1 +/*! \sa PDMCC26XX_I2S_FormatLJF */ +#define PDMCC26XX_I2S_FormatRJFmin 2 +/*! \sa PDMCC26XX_I2S_FormatLJF */ +#define PDMCC26XX_I2S_FormatRJFmax 255 + +/*! Number of samples (16 or 24 bits) per queue element buffer */ +typedef uint32_t PDMCC26XX_I2S_TransferSize; + +/*! + * @brief PDMCC26XX_I2S Hardware attributes + * + * These fields are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * + * A sample structure is shown below: + * @code + * const PDMCC26XX_I2S_HWAttrs PDMCC26XX_I2SHWAttrs = { + * { + * I2S0_BASE, + * INT_I2S, + * PERIPH_I2S, + * CONFIG_I2S_CCLK, + * CONFIG_I2S_BCLK, + * CONFIG_I2S_WCLK, + * CONFIG_I2S_ADI, + * CONFIG_I2S_ADO + * }, + * }; + * @endcode + */ +typedef struct +{ + /*! I2S Peripheral's interrupt vector */ + uint8_t intNum; + /*! I2S Peripheral's interrupt priority */ + uint8_t intPriority; + /*! I2S Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! I2S CCLK pin */ + uint_least8_t cclkPin; + /*! I2S BCLK pin */ + uint_least8_t bclkPin; + /*! I2S WCLK pin */ + uint_least8_t wclkPin; + /*! I2S AD0 pin */ + uint_least8_t ad0Pin; + /*! I2S Peripheral's base address */ + uint32_t baseAddr; +} PDMCC26XX_I2S_HWAttrs; + +/*! + * @brief PDMCC26XX_I2S Audio Clock configuration + * + * These fields are used by the driver to set up the I2S module + * + * A sample structure is shown below (single PDM microphone): + * @code + * const PDMCC26XX_I2S_AudioClockConfig PDMCC26XX_I2Sobjects[] = { + * 16, // Word clock division + * PDMCC26XX_I2S_SampleEdge_Negative, + * PDMCC26XX_I2S_WordClockPhase_Dual, + * PDMCC26XX_I2S_ClockSource_Inverted, + * PDMCC26XX_I2S_WordClockSource_Int, + * 47, // Bit clock division + * 0, // Reserved + * PDMCC26XX_I2S_BitClockSource_Int + * 6, // Controller clock division + * }; + * @endcode + */ +typedef struct +{ + /*! I2S Word Clock divider override */ + uint16_t wclkDiv; + /*! I2S Sample Edge. + * 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. + * 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge */ + uint16_t sampleOnPositiveEdge:1; + /*! I2S Word Clock Phase(PDMCC26XX_I2S_WordClockPhase_Dual, PDMCC26XX_I2S_WordClockPhase_Single or + * PDMCC26XX_I2S_WordClockPhase_UserDefined) */ + uint16_t wclkPhase:2; + /*! I2S Invert Word Clock (PDMCC26XX_I2S_ClockSource_Inverted or PDMCC26XX_I2S_ClockSource_Normal) */ + uint16_t wclkInverted:1; + /*! I2S Word Clock source (PDMCC26XX_I2S_WordClockSource_Ext or PDMCC26XX_I2S_WordClockSource_Int) */ + uint16_t wclkSource:2; + /*! I2S Bit Clock divider override */ + uint16_t bclkDiv:10; + /*! Reserved bit field */ + uint16_t reserved:5; + /*! I2S Bit Clock source (PDMCC26XX_I2S_BitClockSource_Ext or PDMCC26XX_I2S_BitClockSource_Int) */ + uint16_t bclkSource:1; + /*! I2S Controller Clock divider override */ + uint16_t cclkDiv:10; +} PDMCC26XX_I2S_AudioClockConfig; + +/*! + * @brief PDMCC26XX_I2S Audio Pin configuration + * + * These fields are used by the driver to set up the I2S module + * + * A sample structure is shown below (single PDM microphone): + * @code + * const PDMCC26XX_I2S_AudioPinConfig PDMCC26XX_I2Sobjects[] = { + * PDMCC26XX_I2S_ADUsageDisabled, + * 0, + * 0, + * 0, + * 0, + * PDMCC26XX_I2S_ADUsageInput, + * 0, + * 1, + * 2, + * I2S_MONO_MODE + * }; + * @endcode + */ +typedef union PDMCC26XX_I2S_AudioPinConfig +{ + /*! Can be used to set pin configurations in DriverLib*/ + struct + { + /*! Field that can be used to set pin configuration in DriverLib */ + uint16_t ad1; + /*! Field that can be used to set pin configuration in DriverLib */ + uint16_t ad0; + } driverLibParams; + /*! Used to configure various aspects of the I2S hardware during initialisation */ + struct + { + /*! I2S AD1 usage (0: Disabled, 1: Input, 2: Output) */ + uint8_t ad1Usage:2; + /*! I2S Enable Controller clock output on pin (0: Disabled, 1: Enabled) */ + uint8_t enableCclkPin:1; + /*! Reserved bit field */ + uint8_t reserved:1; + /*! I2S AD1 number of channels (1 - 8). !Must match channel mask */ + uint8_t ad1NumOfChannels:4; + /*! I2S AD1 Channel Mask bitwise 0:Disabled, 1:Enabled) E.g. Mono: 0x01, Stereo: 0x03 */ + uint8_t ad1ChannelMask; + /*! I2S AD0 usage (0: Disabled, 1: Input, 2: Output) */ + uint8_t ad0Usage:2; + /*! I2S Enable Word clock output on pin (0: Disabled, 1: Enabled) */ + uint8_t enableWclkPin:1; + /*! I2S Enable Bit clock output on pin (0: Disabled, 1: Enabled) */ + uint8_t enableBclkPin:1; + /*! I2S AD0 number of channels (1 - 8). !Must match channel mask*/ + uint8_t ad0NumOfChannels:4; + /*! I2S AD0 Channel Mask bitwise(0:Disabled, 1:Enabled) E.g. Mono: 0x01, Stereo: 0x03 */ + uint8_t ad0ChannelMask; + } bitFields; +} PDMCC26XX_I2S_AudioPinConfig; +/*! Mask to use with PDMCC26XX_I2S_AudioPinConfig.driverLibParams when calling + * DriverLib. + */ +#define PDMCC26XX_I2S_DIR_CHA_M (I2S_LINE_MASK | I2S_CHAN_CFG_MASK) + +/*! + * @brief PDMCC26XX_I2S Hardware configuration + * + * These fields are used by the driver to set up the I2S module + * + * A sample structure is shown below (single PDM microphone): + * @code + * const PDMCC26XX_I2S_AudioFormatConfig PDMCC26XX_I2Sobjects[] = { + * PDMCC26XX_I2S_WordLength16, + * PDMCC26XX_I2S_PositiveEdge, + * PDMCC26XX_I2S_DualPhase, + * PDMCC26XX_I2S_MemLen16bit, + * PDMCC26XX_I2S_FormatI2SandDSP + * }; + * @endcode + */ +typedef struct +{ + /*! Number of bits per word (8-24). Exact for single phase, max for dual phase */ + uint8_t wordLength:5; + /*! Sample edge. Data and Word clock is samples, and clocked out, on opposite edges of BCLK. + * 0: NEG (Data is sample on the negative edge and clocked out on the positive edge) + * 1: POS (Data is sample on the positive edge and clocked out on the negative edge)*/ + uint8_t sampleEdge:1; + /*! Selects dual- or single phase format (0: Single, 1: Dual) */ + uint8_t dualPhase:1; + /*! Size of each word stored to or loaded from memory (0: 16, 1: 24) */ + uint8_t memLen:1; + /*! Number of BCLK perids between a WCLK edge and MSB of the first word in a phase */ + uint8_t dataDelay; +} PDMCC26XX_I2S_AudioFormatConfig; + +/*! + * @brief PDMCC26XX_I2S Object + * + * The application must not access any member variables of this structure! + */ +typedef enum +{ + /*! + * PDMCC26XX_I2S_requestBuffer() blocks execution. This mode can only be used when called + * within a Task context. + */ + PDMCC26XX_I2S_MODE_BLOCKING, + /*! + * PDMCC26XX_I2S_requestBuffer returns immediately + * if no buffer is available. The caller is notified through events each time + * a buffer is available. This mode can be used in a Task, Swi, or Hwi context. + */ + PDMCC26XX_I2S_CALLBACK_MODE +} PDMCC26XX_I2S_RequestMode; + +/*! + * @brief + * A ::PDMCC26XX_I2S_StreamNotification data structure is used with PDMCC26XX_I2S_CallbackFxn(). + * Provides notification about available buffers and potential errors + */ +typedef struct +{ + void *arg; /*!< Argument to be passed to the callback function */ + PDMCC26XX_I2S_Status status; /*!< Status code set by PDMCC26XX_I2S driver */ +} PDMCC26XX_I2S_StreamNotification; + +/*! + * @brief + * A ::PDMCC26XX_I2S_BufferRequest data structure is used with PDMCC26XX_I2S_requestBuffer(). + * + * bufferIn is a pointer to the requested buffer. It is NULL if no buffer is + * available\n + * + * Input Mode | Interpretation of bufferIn being NULL after returning | + * --------------------|-------------------------------------------------------| + * Blocking mode | Request timed out and still no buffer available | + * Non-Blocking mode | No buffer available | + * + * PDMCC26XX_I2S_requestBuffer will also return \b false if there are no buffers + * available. + * + * \sa PDMCC26XX_I2S_requestBuffer + */ +typedef struct +{ + void *bufferIn; /*!< Pointer to requested In buffer */ + void *bufferHandleIn; /*!< Pointer to requested In buffers handle */ + PDMCC26XX_I2S_Status status; /*!< Status code set by PDMCC26XX_I2S_requestBuffer */ +} PDMCC26XX_I2S_BufferRequest; + +/*! + * @brief + * A ::PDMCC26XX_I2S_BufferRelease data structure is used with PDMCC26XX_I2S_releaseBuffer(). + * + * bufferHandleIn and bufferHandleOut allows the driver to take back and + * reuse memory. + */ +typedef struct +{ + void *bufferHandleIn; /*!< Pointer to requested In buffers handle that we now release */ +} PDMCC26XX_I2S_BufferRelease; + +/*! + * @brief The definition of a callback function used when wakeup on + * chip select is enabled + * + * @param PDMCC26XX_I2S_Handle PDMCC26XX_I2S_Handle + */ +typedef void (*PDMCC26XX_I2S_CallbackFxn)(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_StreamNotification *notification); + +/*! + * @brief + * PDMCC26XX I2S Parameters are used when calling ::PDMCC26XX_I2S_open(). + */ +typedef struct +{ + uint8_t blockCount; /*!< Number of PDM buffers the I2S driver can fill without the PDM driver processing them. Must + be larger than 3. */ + uint32_t requestTimeout; /*!< Timeout for the request when in blocking mode */ + PDMCC26XX_I2S_RequestMode requestMode; /*!< Blocking or Callback mode */ + PDMCC26XX_I2S_TransferSize blockSizeInSamples; /*!< I2S DMA transfer size in number of samples. Each + * sample consumes either 16 or 24 bits per channel, + * set by ::PDMCC26XX_I2S_AudioFormatConfig.memLen. Number + * of channels are set in + * ::PDMCC26XX_I2S_AudioPinConfig.ad0NumOfChannels and + * ::PDMCC26XX_I2S_AudioPinConfig.ad1NumOfChannels + */ + PDMCC26XX_I2S_CallbackFxn callbackFxn; /*!< Callback function pointer */ + + PDMCC26XX_I2S_MallocFxn mallocFxn; /*!< Malloc function pointer */ + PDMCC26XX_I2S_FreeFxn freeFxn; /*!< Free function pointer */ + PDMCC26XX_I2S_StreamNotification *currentStream; /*!< Pointer to information about the current state of the stream + */ +} PDMCC26XX_I2S_Params; + +/*! + * @brief PDMCC26XX_I2S Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; /*!< Has the object been opened */ + uint8_t blockCount; /*!< Number of PDM buffers the I2S driver can fill without the PDM driver processing them. Must + be larger than 3. */ + uint16_t blockSizeInBytes; /*!< Size of an individual PDM block buffer in bytes */ + PDMCC26XX_I2S_RequestMode requestMode; /*!< Blocking or return mode */ + uint32_t requestTimeout; /*!< Timeout for the request when in blocking mode */ + int32_t sampleRate; /*!< I2S bit clock frequency in Hz. If negative, or not one of + I2S_SAMPLE_RATE_16K/_24K/_32K/_48K then use user configured clock division.*/ + PDMCC26XX_I2S_TransferSize blockSizeInSamples; /*!< I2S DMA transfer size, determines the block size in number of + * samples. Each sample consumes either 16 or 24 bits, set by + * ::PDMCC26XX_I2S_AudioFormatConfig.memLen + */ + PDMCC26XX_I2S_CallbackFxn callbackFxn; /*!< Callback function pointer */ + PDMCC26XX_I2S_MallocFxn mallocFxn; /*!< Malloc function pointer */ + PDMCC26XX_I2S_FreeFxn freeFxn; /*!< Free function pointer */ + PDMCC26XX_I2S_StreamNotification *currentStream; /*!< Ptr to information about the current transaction*/ + PDMCC26XX_I2S_AudioFormatConfig audioFmtCfg; /*!< I2S audio format configuration */ + PDMCC26XX_I2S_AudioPinConfig audioPinCfg; /*!< I2S pin configuration*/ + HwiP_Struct hwi; /*!< Hwi object handle */ + SemaphoreP_Struct blockComplete; /*!< Notify complete PDMCC26XX_I2S block transfer */ + SemaphoreP_Struct semStopping; /*!< PDMCC26XX_I2S stopping sequence semaphore */ + PDMCC26XX_I2S_AudioClockConfig audioClkCfg; /*!< I2S clock division override and clock config */ +} PDMCC26XX_I2S_Object; + +/*! + * @brief I2S CC26XX initialization + * + * @param handle A PDMCC26XX_I2S_Handle + * + */ +extern void PDMCC26XX_I2S_init(PDMCC26XX_I2S_Handle handle); + +/*! + * @brief Function to open a given CC26XX I2S peripheral specified by the + * I2S handle. + * + * The function will set a dependency on its power domain, i.e. power up the + * module and enable the clock. The IOs are allocated. The I2S will not be + * enabled. + * + * \b params must point a correctly initialized PDMCC26XX_I2S_Params struct. + * + * @pre I2S controller has been initialized + * + * @param handle A PDMCC26XX_I2S_Handle + * + * @param params Pointer to a parameter block, if NULL it will use + * default values + * + * @return A PDMCC26XX_I2S_Handle on success or a NULL on an error or if it has been + * already opened + * + * @sa PDMCC26XX_I2S_close() + */ +extern PDMCC26XX_I2S_Handle PDMCC26XX_I2S_open(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_Params *params); + +/*! + * @brief Function to close a given CC26XX I2S peripheral specified by the + * I2S handle. + * + * Will disable the I2S, disable all I2S interrupts and release the + * dependency on the corresponding power domain. It will also destroy all + * semaphores and queues that have been used. + * + * @pre PDMCC26XX_I2S_open() has to be called first. + * + * @param handle A PDMCC26XX_I2S_Handle returned from PDMCC26XX_I2S_open() + * + * @sa PDMCC26XX_I2S_open + */ +extern void PDMCC26XX_I2S_close(PDMCC26XX_I2S_Handle handle); + +/*! + * @brief Function for starting an I2S interface. + * + * Calling this function will prevent the device from sleeping, as the + * stream is continuous and thus require power to the audio interface module + * from start to end. + * This function will configure all hardware registers that does not have + * retention. Hence, one may call PDMCC26XX_I2S_open then go to sleep before this + * function is called. + * + * If non-blocking mode is selected then the PDMCC26XX_I2S module will begin + * calling the provided callback function every time a new buffer is ready. + * + * @pre PDMCC26XX_I2S_open() has to be called first. + * + * @param handle An I2S handle returned from PDMCC26XX_I2S_open() + * + * @return True if transfer is successful and false if not + * + * @sa PDMCC26XX_I2S_open(), PDMCC26XX_I2S_stopStream() + */ +extern bool PDMCC26XX_I2S_startStream(PDMCC26XX_I2S_Handle handle); + +/*! + * @brief Function for stopping an I2S interface. + * + * This function will initiate the shut down sequence. The audio interface + * module is designed with a graceful shutdown. What this means is that the + * current buffer is filled before stopping. This function will block while + * the last buffer is completing. The maximum blocking delay is a function + * of the configured DMA transfer size, and the word clock rate. + * + * When this function returns it is recommended to complete processing of + * all pending ready buffers. If the caller is not interested in the last + * audio data it may simply call PDMCC26XX_I2S_requestBuffer() and + * PDMCC26XX_I2S_releaseBuffer() in a loop until PDMCC26XX_I2S_requestBuffer() returns + * false. + * + * Will disable the I2S, disable all I2S interrupts and release the + * dependency on the corresponding power domain. + * + * @pre PDMCC26XX_I2S_startStream() has to be called first. + * + * @param handle An I2S handle returned from PDMCC26XX_I2S_open() + * + * @return True if stream stopped successfully and false if not + * + * @sa PDMCC26XX_I2S_open(), PDMCC26XX_I2S_startStream() + */ +extern bool PDMCC26XX_I2S_stopStream(PDMCC26XX_I2S_Handle handle); + +/*! + * @brief Function for requesting buffer. + * + * In ::PDMCC26XX_I2S_MODE_BLOCKING, PDMCC26XX_I2S_requestBuffer will block task + * execution until at least one buffer is ready. + * + * In ::PDMCC26XX_I2S_CALLBACK_MODE, PDMCC26XX_I2S_requestBuffer returns immediately + * if no buffer is available. The caller is notified through events each time + * a buffer is available. + * + * This function takes as an argument a pointer to a struct which contains + * 4 pointers. There are two pairs; one for Input and one for Output. + * If input is defined then the input buffer pointer will point to the + * new input buffer. Same goes for output and the output buffer pointer. + * The caller is not expected to allocate memory for the buffer as no copy + * is performed. The other two pointers must be maintained by the caller until + * it is ready to call PDMCC26XX_I2S_releaseBuffer(). + * + * @pre PDMCC26XX_I2S_open() and PDMCC26XX_I2S_startStream() has to be called first. + * + * @param handle A I2S handle returned from PDMCC26XX_I2S_open() + * + * @param *bufferRequest Pointer to PDMCC26XX_I2S_BufferRequest struct + * + * @return True if a buffer is available, false if not. + * + * @sa PDMCC26XX_I2S_open(), PDMCC26XX_I2S_startStream(), PDMCC26XX_I2S_releaseBuffer() + */ +extern bool PDMCC26XX_I2S_requestBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRequest *bufferRequest); + +/*! + * @brief Function for releasing buffer. + * + * The caller of PDMCC26XX_I2S_requestBuffer() must call this function when it is + * finished working on the buffer. This function takes as an argument a pointer + * to a struct which contains two other pointers. These pointers must be set + * the pointers received in PDMCC26XX_I2S_requestBuffer(). + * + * @pre PDMCC26XX_I2S_requestBuffer() has to be called first. + * + * @param handle A I2S handle returned from PDMCC26XX_I2S_open() + * + * @param *bufferRelease Pointer to PDMCC26XX_I2S_BufferRelease struct + * + * @return True if release is successful and false if not + * + * @sa PDMCC26XX_I2S_open(), PDMCC26XX_I2S_startStream(), PDMCC26XX_I2S_requestBuffer() + */ +extern void PDMCC26XX_I2S_releaseBuffer(PDMCC26XX_I2S_Handle handle, PDMCC26XX_I2S_BufferRelease *bufferRelease); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_i2s_PDMCC26XX_I2S__include */ diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.c new file mode 100644 index 00000000..90004bc1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.c @@ -0,0 +1,1795 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2.c ======== + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_prcm.h) +#include DeviceFamily_constructPath(inc/hw_nvic.h) +#include DeviceFamily_constructPath(inc/hw_aux_sysif.h) +#include DeviceFamily_constructPath(inc/hw_aon_rtc.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_memmap_common.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(inc/hw_rfc_pwr.h) +#include DeviceFamily_constructPath(inc/hw_aon_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_fcfg1.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(driverlib/pwr_ctrl.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/vims.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/setup.h) +#include DeviceFamily_constructPath(driverlib/setup_rom.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +#include + +static unsigned int configureXOSCHF(unsigned int action); +static unsigned int nopResourceHandler(unsigned int action); +static unsigned int configureRFCoreClocks(unsigned int action); +static void switchXOSCHF(void); +static void disableLFClockQualifiers(void); +static void emptyClockFunc(uintptr_t arg); +static int_fast16_t notify(uint_fast16_t eventType); +static void oscillatorISR(uintptr_t arg); +static void switchToTCXO(void); +static void hposcRtcCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); +static void xosclfRtcCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); + +/* RCOSC calibration functions functions */ +extern void PowerCC26X2_calibrate(void); +extern bool PowerCC26X2_initiateCalibration(void); +extern void PowerCC26X2_auxISR(uintptr_t arg); +extern void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern const PowerCC26X2_Config PowerCC26X2_config; + +/* Macro for weak definition of the Power Log module */ +Log_MODULE_DEFINE_WEAK(LogModule_Power, {0}); + +/* Module_State */ +PowerCC26X2_ModuleState PowerCC26X2_module = { + .notifyList = {0}, /* list of registered notifications */ + .constraintMask = 0, /* the constraint mask */ + .clockObj = {0}, /* Clock object for scheduling wakeups */ + .calibrationClock = {0}, /* Clock object for RCOSC calibration */ + .tcxoEnableClock = {0}, /* Clock object for TCXO startup */ + .tdcHwi = {0}, /* hwi object for calibration */ + .oscHwi = {0}, /* hwi object for oscillators */ + .nDeltaFreqCurr = 0, /* RCOSC calibration variable */ + .nCtrimCurr = 0, /* RCOSC calibration variable */ + .nCtrimFractCurr = 0, /* RCOSC calibration variable */ + .nCtrimNew = 0, /* RCOSC calibration variable */ + .nCtrimFractNew = 0, /* RCOSC calibration variable */ + .nRtrimNew = 0, /* RCOSC calibration variable */ + .nRtrimCurr = 0, /* RCOSC calibration variable */ + .nDeltaFreqNew = 0, /* RCOSC calibration variable */ + .bRefine = false, /* RCOSC calibration variable */ + .state = Power_ACTIVE, /* current transition state */ + .xoscPending = false, /* is XOSC_HF activation in progress? */ + .calLF = false, /* calibrate RCOSC_LF? */ + .auxHwiState = 0, /* calibration AUX ISR state */ + .busyCal = false, /* already busy calibrating */ + .calStep = 0, /* current calibration step */ + .firstLF = true, /* is this first LF calibration? */ + .enablePolicy = false, /* default value is false */ + .initialized = false, /* whether Power_init has been called */ + .constraintCounts = {0, 0, 0, 0, 0, 0, 0}, + .resourceHandlers = {configureRFCoreClocks, configureXOSCHF, nopResourceHandler}, /* special resource handler + functions */ + .policyFxn = 0, /* power policyFxn */ +}; + +/*! Temperature notification to compensate the RTC when SCLK_LF is derived + * from SCLK_HF when SCLK_HF is configured as HPOSC. + */ +static Temperature_NotifyObj PowerCC26X2_hposcRtcCompNotifyObj = {0}; + +/*! Temperature notification to compensate the RTC when SCLK_LF is derived + * from XOSC_LF + */ +static Temperature_NotifyObj PowerCC26X2_xosclfRtcCompNotifyObj = {0}; + +/*! Default RTC subsecond increment corresponding to precisely 32768 Hz + * increment frequency + */ +#define RTC_SUBSECINC_32768_HZ 0x800000 + +/*! This internal variable to the power-driver keeps track of the most recent + * RTC increment value, whenever it is compensated due to temperature drift. + * In case of a clock-switch from XOSC_LF to RCOSC_LF or vice versa, this + * value is used to reprogram the RTC with a correct compensated value. + */ +static volatile uint32_t PowerCC26X2_rtcSubSecInc = RTC_SUBSECINC_32768_HZ; + +/* resource database */ +const PowerCC26XX_ResourceRecord resourceDB[PowerCC26X2_NUMRESOURCES] = { + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER0}, /* PERIPH_GPT0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER1}, /* PERIPH_GPT1 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER2}, /* PERIPH_GPT2 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER3}, /* PERIPH_GPT3 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_SSI0}, /* PERIPH_SSI0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_UART0}, /* PERIPH_UART0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_I2C0}, /* PERIPH_I2C0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TRNG}, /* PERIPH_TRNG */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_GPIO}, /* PERIPH_GPIO */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UDMA}, /* PERIPH_UDMA */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_CRYPTO}, /* PERIPH_CRYPTO */ + {PowerCC26XX_PERIPH | PowerCC26XX_PERIPH_UDMA, PRCM_PERIPH_I2S}, /* PERIPH_I2S */ + {PowerCC26XX_SPECIAL | PowerCC26XX_DOMAIN_RFCORE, 0}, /* PERIPH_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 1}, /* XOSC_HF */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_PERIPH}, /* DOMAIN_PERIPH */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_SERIAL}, /* DOMAIN_SERIAL */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_RFCORE}, /* DOMAIN_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 2}, /* DOMAIN_SYSBUS */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_PKA}, /* PERIPH_PKA */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UART1}, /* PERIPH_UART1 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI1}, /* PERIPH_SSI1 */ +#endif +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UART2}, /* PERIPH_UART2 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UART3}, /* PERIPH_UART3 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI2}, /* PERIPH_SSI2 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI3}, /* PERIPH_SSI3 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_I2C1}, /* PERIPH_I2C1 */ +#endif +}; + +/* Defines */ +#define TCXO_RAMP_DELAY 10 +#define CC26X2_CLOCK_FREQUENCY 48000000 + +/* This is an approximate scaling factor previously used in test firmware. */ +#define DELAY_SCALING_FACTOR 6000000 + +/* ****************** Power APIs ******************** */ + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool enablePolicy = PowerCC26X2_module.enablePolicy; + PowerCC26X2_module.enablePolicy = false; + + return (enablePolicy); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC26X2_module.enablePolicy = true; +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC26X2_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(Power_Resource resourceId) +{ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + return ((int_fast16_t)PowerCC26X2_module.resourceCounts[resourceId]); +} + +/* + * ======== Power_getConstraintCount ======== + * Get the count of constraints that are currently set on a certain + * operational transition + */ +int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId) +{ + DebugP_assert(constraintId < PowerCC26X2_NUMCONSTRAINTS); + + if (constraintId < PowerCC26X2_NUMCONSTRAINTS) + { + return (int_fast16_t)PowerCC26X2_module.constraintCounts[constraintId]; + } + else + { + return (int_fast16_t)Power_EINVALIDINPUT; + } +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) + { + if (sleepState == PowerCC26XX_STANDBY) + { + latency = PowerCC26X2_RESUMETIMESTANDBY; + } + } + else + { + if (sleepState == PowerCC26XX_STANDBY) + { + latency = PowerCC26X2_TOTALTIMESTANDBY; + } + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC26X2_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc(void) +{ + if (PowerCC26X2_module.enablePolicy) + { + if (PowerCC26X2_module.policyFxn != NULL) + { + (*(PowerCC26X2_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init(void) +{ + ClockP_Params clockParams; + uint32_t ccfgLfClkSrc; + + /* if this function has already been called, just return */ + if (PowerCC26X2_module.initialized) + { + return (Power_SOK); + } + + /* set module state field 'initialized' to true */ + PowerCC26X2_module.initialized = true; + + PowerCC26X2_module.lastResetReason = (PowerCC26X2_ResetReason)PowerCC26X2_sysCtrlGetResetSource(); + + /* set the module state enablePolicy field */ + PowerCC26X2_module.enablePolicy = PowerCC26X2_config.enablePolicy; + + /* copy the Power policy function to module state */ + PowerCC26X2_module.policyFxn = PowerCC26X2_config.policyFxn; + + /* Check if TCXO is selected in CCFG and in addition configured to be + * enabled by the function pointed to by PowerCC26X2_config.enableTCXOFxn + */ + if ((CCFGRead_XOSC_FREQ() == CCFGREAD_XOSC_FREQ_TCXO) && (PowerCC26X2_config.enableTCXOFxn != NULL)) + { + /* Construct the Clock object for TCXO startup time. + * Set timeout to TCXO startup time as specified in CCFG. + */ + ClockP_construct(&PowerCC26X2_module.tcxoEnableClock, + (ClockP_Fxn)&switchToTCXO, + (CCFGRead_TCXO_MAX_START() * 100) / ClockP_getSystemTickPeriod(), + NULL); + + PowerCC26X2_oscCtlClearXtal(); + } + + /* construct the Clock object for scheduling of wakeups */ + /* initiated and started by the power policy */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26X2_module.clockObj, &emptyClockFunc, 0, &clockParams); + + /* + * If RCOSC calibration is enabled, construct a Clock object for + * delays. Set timeout to 8 Clock tick periods to get + * ceil(8x10us/30.5us/SCLK_LF_period)*30.5us/SCLK_LF_period = ~90us. + * The total time we need to wait for AUX_SYSIF_TDCREFCLKCTL_ACK + * is about 105us and the ClockP_start() call needs about 21us. + * All together, that makes ~111us. A decent approximation of the + * ideal wait duration. + * In practice, the COMPARE_MARGIN that is currently still in + * the kernel Timer.c implementation may make it take longer + * than 90us to time out. + */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26X2_module.calibrationClock, &PowerCC26X2_RCOSC_clockFunc, 8, &clockParams); + + HwiP_construct(&PowerCC26X2_module.oscHwi, INT_OSC_COMB, oscillatorISR, NULL); + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC) = 0; + + /* construct the TDC hwi */ + HwiP_construct(&PowerCC26X2_module.tdcHwi, INT_AUX_COMB, PowerCC26X2_auxISR, NULL); + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* check if should calibrate RCOSC_LF */ + if (PowerCC26X2_config.calibrateRCOSC_LF) + { + /* verify RCOSC_LF is the LF clock source */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) + { + PowerCC26X2_module.calLF = true; + } + } + + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF || ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF || + ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF) + { + /* Turn on oscillator interrupt for SCLK_LF switching. + * When using HPOSC-derived LF, the LF clock will already have switched + * and the interrupt will fire once interrupts are enabled + * again when the OS starts. + * When using a regular HF crystal to derive the LF source, it may take + * up to a few hundred microseconds for the crystal to start up. + * When using RCOSC_LF, the clock switch will happen very fast and + * the interrupt will often immediately trigger once interrupts are + * enabled again when the OS starts. + */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_LFSRCDONEIM_M; + + /* Disallow STANDBY pending LF clock quailifier disabling */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) + { + /* If the LF clock source is external, can disable clock qualifiers + * now; no need to assert DISALLOW_STANDBY + */ + + /* yes, disable the LF clock qualifiers */ + PowerCC26X2_oscDisableQualifiers(); + } + + /* if VIMS RAM is configured as GPRAM: set retention constraint */ + if (!CCFGRead_DIS_GPRAM()) + { + Power_setConstraint(PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY); + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + * + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) + { + Log_printf(LogModule_Power, Log_WARNING, + "Power_registerNotify: Notify registration failed due to NULL pointer"); + + status = Power_EINVALIDPOINTER; + } + + else + { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + Log_printf(LogModule_Power, + Log_INFO, + "Power_registerNotify: Register fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + notifyFxn, + eventTypes, + clientArg); + + /* place notify object on event notification queue */ + List_put(&PowerCC26X2_module.notifyList, (List_Elem *)pNotifyObj); + } + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + uint8_t count; + + /* assert constraintId is valid */ + DebugP_assert(constraintId < PowerCC26X2_NUMCONSTRAINTS); + + /* forward constraint release to Zephyr */ + switch (constraintId) { + case PowerCC26XX_DISALLOW_STANDBY: + pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + break; + case PowerCC26XX_DISALLOW_IDLE: + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + break; + default: + break; + } + + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC26X2_module.constraintCounts[constraintId]; + + DebugP_assert(count != 0); + + count--; + + /* save the updated count */ + PowerCC26X2_module.constraintCounts[constraintId] = count; + + if (count == 0) + { + PowerCC26X2_module.constraintMask &= ~(1 << constraintId); + } + + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId) +{ + PowerCC26XX_Resource parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and decrement the reference count */ + count = PowerCC26X2_module.resourceCounts[resourceId]; + + DebugP_assert(count != 0); + + count--; + + /* save the reference count */ + PowerCC26X2_module.resourceCounts[resourceId] = count; + + /* if this was the last dependency being released.., */ + if (count == 0) + { + /* deactivate this resource ... */ + id = resourceDB[resourceId].driverlibID; + +/* Conditional compile required since CC26X1 does not define PRCM_PERIPH_PKA */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /* + * Special handling for the Crypto, TRNG, PKA, and DMA peripherals + * which are on the secure side for CC26X3/X4. + */ + if ((id == PRCM_PERIPH_CRYPTO) || (id == PRCM_PERIPH_TRNG) || (id == PRCM_PERIPH_PKA) || + (id == PRCM_PERIPH_UDMA)) + { + PowerCC26X2_releasePeriphDependency(id); + } + else + { +#endif + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) + { + PRCMPeripheralRunDisable(id); + PRCMPeripheralSleepDisable(id); + PRCMPeripheralDeepSleepDisable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) {} + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) + { + /* call the special handler */ + PowerCC26X2_module.resourceHandlers[id](PowerCC26XX_DISABLE); + } + /* else resource is a power domain */ + else + { + PRCMPowerDomainOff(id); + while (PRCMPowerDomainsAllOff(id) != PRCM_DOMAIN_POWER_OFF) {} + } + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + } +#endif + /* propagate release up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if 1st parent, make recursive call to release that dependency */ + if (parent < PowerCC26X2_NUMRESOURCES) + { + Power_releaseDependency(parent); + } + } + + Log_printf(LogModule_Power, + Log_INFO, + "Power_releaseDependency: Updated resource counter = %d for resource ID = 0x%x", + PowerCC26X2_module.resourceCounts[resourceId], resourceId); + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + + /* assert constraint id is valid */ + DebugP_assert(constraintId < PowerCC26X2_NUMCONSTRAINTS); + + /* forward constraint set to Zephyr */ + switch (constraintId) { + case PowerCC26XX_DISALLOW_STANDBY: + pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES); + break; + case PowerCC26XX_DISALLOW_IDLE: + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); + break; + default: + break; + } + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC26X2_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC26X2_module.constraintCounts[constraintId]++; + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(Power_Resource resourceId) +{ + PowerCC26XX_Resource parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26X2_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC26X2_module.resourceCounts[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) + { + /* propagate set up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if first parent, make recursive call to set that dependency */ + if (parent < PowerCC26X2_NUMRESOURCES) + { + Power_setDependency(parent); + } + + /* now activate this resource ... */ + id = resourceDB[resourceId].driverlibID; + +/* Conditional compile required since CC26X1 does not define PRCM_PERIPH_PKA */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /* + * Special handling for the Crypto, TRNG, PKA, and DMA peripherals + * which are on the secure side for CC26X3/X4. + */ + if ((id == PRCM_PERIPH_CRYPTO) || (id == PRCM_PERIPH_TRNG) || (id == PRCM_PERIPH_PKA) || + (id == PRCM_PERIPH_UDMA)) + { + PowerCC26X2_setPeriphDependency(id); + } + else + { +#endif + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) + { + PRCMPeripheralRunEnable(id); + PRCMPeripheralSleepEnable(id); + PRCMPeripheralDeepSleepEnable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) {} + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) + { + /* call the special handler */ + PowerCC26X2_module.resourceHandlers[id](PowerCC26XX_ENABLE); + } + /* else resource is a power domain */ + else + { + PRCMPowerDomainOn(id); + while (PRCMPowerDomainsAllOn(id) != PRCM_DOMAIN_POWER_ON) {} + } +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + } +#endif + } + + Log_printf(LogModule_Power, + Log_INFO, + "Power_setDependency: Updated resource counter = %d for resource ID = 0x%x", + PowerCC26X2_module.resourceCounts[resourceId], resourceId); + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC26X2_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + unsigned int constraints; + unsigned int hwiKey; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* check if there is a constraint to prohibit shutdown */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_DISALLOW_SHUTDOWN)) + { + status = Power_ECHANGE_NOT_ALLOWED; + } + + /* OK to shutdown ... */ + else if (PowerCC26X2_module.state == Power_ACTIVE) + { + /* set new transition state to entering shutdown */ + PowerCC26X2_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC26XX_ENTERING_SHUTDOWN); + + /* check for any error */ + if (status != Power_SOK) + { + PowerCC26X2_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + + /* Ensure the JTAG domain is turned off + * otherwise MCU domain can't be turned off. + */ + PowerCC26X2_pmctlDisableJtag(); + + SysCtrlAonSync(); + + /* now proceed with shutdown sequence ... */ + PowerCC26X2_sysctrlShutdownWithAbort(); + } + else + { + status = Power_EBUSY; + } + + /* NOTE: if shutdown succeeded, should never get here */ + + /* return failure status */ + PowerCC26X2_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + int_fast16_t notifyStatus = Power_SOK; + int_fast16_t lateNotifyStatus = Power_SOK; + unsigned int xosc_hf_active = false; + uint_fast16_t postEventLate; + uint32_t poweredDomains = 0; + uint_fast16_t preEvent; + uint_fast16_t postEvent; + unsigned int constraints; + bool retainCache = false; + uint32_t modeVIMS; + + /* first validate the sleep code */ + if (sleepState != PowerCC26XX_STANDBY) + { + status = Power_EINVALIDINPUT; + + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed with status = 0x%x", + status); + } + else + { + /* check to make sure Power is not busy with another transition */ + if (PowerCC26X2_module.state == Power_ACTIVE) + { + /* set transition state to entering sleep */ + PowerCC26X2_module.state = Power_ENTERING_SLEEP; + } + else + { + status = Power_EBUSY; + + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed with status = 0x%x", + status); + } + + if (status == Power_SOK) + { + /* setup sleep vars */ + preEvent = PowerCC26XX_ENTERING_STANDBY; + postEvent = PowerCC26XX_AWAKE_STANDBY; + postEventLate = PowerCC26XX_AWAKE_STANDBY_LATE; + + /* disable scheduling */ + PowerCC26XX_schedulerDisable(); + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for any error */ + if (status != Power_SOK) + { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed due to pre-sleep notification status = 0x%x", + status); + + PowerCC26X2_module.state = Power_ACTIVE; + PowerCC26XX_schedulerRestore(); + return (status); + } + + /* 1. Query and save domain states before powering them off */ + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_RFCORE)) + { + poweredDomains |= PRCM_DOMAIN_RFCORE; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_SERIAL)) + { + poweredDomains |= PRCM_DOMAIN_SERIAL; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_PERIPH)) + { + poweredDomains |= PRCM_DOMAIN_PERIPH; + } + + /* 2. If XOSC_HF is active or we are waiting to switch + * to it, force it off. Otherwise, the XOSC_HF may be + * automatically turned on by the hardware without + * a call to configureXOSCHF(PowerCC26XX_ENABLE) + * This is not necessarily a problem. However exactly + * what the cutoff point is where the hardware considers + * the XOSC_HF "on" without having switched to is not + * considered by this driver. + */ + if (PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF || PowerCC26X2_module.xoscPending == true) + { + Log_printf(LogModule_Power, Log_VERBOSE, "Power_sleep: Forcing XOSC_HF off"); + + xosc_hf_active = true; + configureXOSCHF(PowerCC26XX_DISABLE); + } + + /* query constraints to determine if cache should be retained */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY)) + { + retainCache = true; + } + else + { + retainCache = false; + + // Get the current VIMS mode + do + { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + } + + /* 3. + * - Freeze the IOs on the boundary between MCU and AON + * - Make sure AON writes take effect + * - Request power off of every PD in the MCU voltage domain + * - Ensure that no clocks are forced on in Crypto, DMA and I2S + * - Gate running deep sleep clocks for Crypto, DMA and I2S + * - Load the new clock settings + * - Configure the VIMS power domain mode to power up flash + * again after coming out of standby. + * - Request uLDO during standby + * - Use recharge comparator + * - Ensure all writes have taken effect + * - Ensure UDMA, Crypto and I2C clocks are turned off + * - Ensure all non-CPU power domains are turned off + * - Turn off cache retention if requested + * - Invoke deep sleep to go to standby + */ + PowerCC26X2_sysCtrlStandby(retainCache); + + /* 4. If didn't retain VIMS in standby, re-enable retention now */ + if (retainCache == false) + { + /* 5.1 If previously in a cache mode, restore the mode now */ + if (modeVIMS == VIMS_MODE_ENABLED) + { + VIMSModeSet(VIMS_BASE, modeVIMS); + } + + /* 5.2 Re-enable retention */ + PowerCC26X2_prcmEnableCacheRetention(); + } + + /* 6. Start re-powering power domains */ + PRCMPowerDomainOn(poweredDomains); + + /* 7. Restore deep sleep clocks of Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) + { + PowerCC26X2_setPeriphDeepSleepEnable(resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) + { + PowerCC26X2_setPeriphDeepSleepEnable(resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + + /* 8. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 9. Release request for uLDO */ + PRCMMcuUldoConfigure(false); + + /* 10. Set transition state to EXITING_SLEEP */ + PowerCC26X2_module.state = Power_EXITING_SLEEP; + + /* 11. Wait until all power domains are back on */ + while (PRCMPowerDomainsAllOn(poweredDomains) != PRCM_DOMAIN_POWER_ON) {} + + /* 12. Wait for the RTC shadow values to be updated so that + * the early notification callbacks can read out valid RTC values. + * This can likely be removed as the 2MHz MF clock will have ticked by now. + */ + SysCtrlAonSync(); + + /* + * 13. Signal clients registered for early post-sleep notification; + * this should be used to initialize any timing critical or IO + * dependent hardware + */ + notifyStatus = notify(postEvent); + + /* 14. Disable IO freeze and ensure RTC shadow value is updated */ + AONIOCFreezeDisable(); + SysCtrlAonSync(); + + /* 15. If XOSC_HF was forced off above, initiate switch back */ + if (xosc_hf_active == true) + { + Log_printf(LogModule_Power, + Log_VERBOSE, + "Power_sleep: Forcing XOSC_HF back on"); + + configureXOSCHF(PowerCC26XX_ENABLE); + } + + /* 16. Re-enable interrupts */ + /* For Zephyr, post suspend hooks need to run with interrupts + * disabled after Power_sleep returns. So we need to leave + * interrupts disabled. + */ + /* CPUcpsie(); */ + + /* + * 17. Signal all clients registered for late post-sleep + * notification + */ + lateNotifyStatus = notify(postEventLate); + + /* + * 18. Now clear the transition state before re-enabling + * scheduler + */ + PowerCC26X2_module.state = Power_ACTIVE; + + /* 19. Re-enable scheduling */ + PowerCC26XX_schedulerRestore(); + + /* if there was a notification error, set return status */ + if ((notifyStatus != Power_SOK) || (lateNotifyStatus != Power_SOK)) + { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Notification error leaving standby. Status = 0x%x and late status = 0x%x", + notifyStatus, + lateNotifyStatus); + + status = Power_EFAIL; + } + } + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj) +{ + unsigned int key; + + /* remove notify object from its event queue */ + key = HwiP_disable(); + + Log_printf(LogModule_Power, + Log_INFO, + "Power_unregisterNotify: Unregister fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + pNotifyObj->notifyFxn, + pNotifyObj->eventTypes, + pNotifyObj->clientArg); + + /* remove notify object from its event queue */ + List_remove(&PowerCC26X2_module.notifyList, (List_Elem *)pNotifyObj); + + HwiP_restore(key); +} + +/* + * ======== Power_reset ======== + */ +void Power_reset(void) +{ + PowerCC26X2_sysCtrlReset(); +} + +/* ****************** CC26XX specific APIs ******************** */ + +/* + * ======== PowerCC26X2_enableHposcRtcCompensation ======== + * This function enabled temperature based compensation of the RTC when + * SCLK_LF is derived from HPOSC. + */ +void PowerCC26X2_enableHposcRtcCompensation(void) +{ + /* If we are using HPOSC and SCLK_LF is derived from it, we need to + * compensate the RTC to account for HPOSC frequency drift over temperature. + */ + if (PowerCC26X2_oscIsHPOSCEnabledWithHfDerivedLfClock()) + { + Log_printf(LogModule_Power, + Log_INFO, + "PowerCC26X2_enableHposcRtcCompensation: Enable HPOSC RTC compensation"); + + Temperature_init(); + + int16_t currentTemperature = Temperature_getTemperature(); + + OSC_HPOSCInitializeFrequencyOffsetParameters(); + + /* The compensation fxn will register itself with updated thresholds + * based on the current temperature each time it is invoked. If we + * call it from the init function, it will register itself for the + * first time and handle initial RTC compensation. + */ + hposcRtcCompensateFxn(currentTemperature, + currentTemperature + PowerCC26X2_HPOSC_RTC_COMPENSATION_DELTA, + (uintptr_t)NULL, + &PowerCC26X2_hposcRtcCompNotifyObj); + } +} + +/* + * ======== PowerCC26X2_enableXoscLfRtcCompensation ======== + * This function enables temperature based compensation of the RTC when + * SCLK_LF is derived from XOSC_LF. + */ +void PowerCC26X2_enableXoscLfRtcCompensation(void) +{ + /* Check that SCLK_LF is derived from XOSC_LF */ + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_XOSC_LF) + { + Log_printf(LogModule_Power, + Log_INFO, + "PowerCC26X2_enableXoscLfRtcCompensation: Enable XOSC_LF RTC compensation"); + + Temperature_init(); + + int16_t currentTemperature = Temperature_getTemperature(); + + /* This must be called before xosclfRtcCompensateFxn, as the compensation parameters must be initialised + * with respect to device-specifc temperature trim values. + */ + OSC_LFXOSCInitStaticOffset(); + + /* The compensation fxn will register itself with updated thresholds + * based on the current temperature each time it is invoked. If we + * call it from the init function, it will register itself for the + * first time and handle initial RTC compensation. + */ + xosclfRtcCompensateFxn(currentTemperature, 0, (uintptr_t)NULL, &PowerCC26X2_xosclfRtcCompNotifyObj); + } +} + +/* + * ======== PowerCC26XX_calibrate ======== + * Plug this function into the PowerCC26X2_Config structure + * if calibration is needed. + */ +bool PowerCC26XX_calibrate(unsigned int arg) +{ + bool retVal = false; + + switch (arg) + { + case PowerCC26X2_INITIATE_CALIBRATE: + retVal = PowerCC26X2_initiateCalibration(); + break; + + case PowerCC26X2_DO_CALIBRATE: + PowerCC26X2_calibrate(); + break; + default: + while (1) {} + } + + return (retVal); +} + +/* + * ======== PowerCC26XX_doWFI ======== + */ +void PowerCC26XX_doWFI(void) +{ + __asm(" wfi"); +} + +/* + * ======== PowerCC26X2_getClockHandle ======== + */ +ClockP_Handle PowerCC26XX_getClockHandle(void) +{ + return ((ClockP_Handle)&PowerCC26X2_module.clockObj); +} + +/* + * ======== PowerCC26XX_noCalibrate ======== + * Plug this function into the PowerCC26X2 config structure if calibration + * is not needed. + */ +bool PowerCC26XX_noCalibrate(unsigned int arg) +{ + return (0); +} + +/* + * ======== PowerCC26XX_getXoscStartupTime ======== + * Get the estimated crystal oscillator startup time + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs) +{ + return (OSCHF_GetStartupTime(timeUntilWakeupInMs)); +} + +/* + * ======== PowerCC26X2_injectCalibration ======== + * Explicitly trigger RCOSC calibration + */ +bool PowerCC26XX_injectCalibration(void) +{ + if ((*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE)) + { + /* here if AUX SMPH was available, start calibration now ... */ + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + return (true); + } + + return (false); +} + +/* + * ======== PowerCC26XX_isStableXOSC_HF ======== + * Check if XOSC_HF has stabilized. + */ +bool PowerCC26XX_isStableXOSC_HF(void) +{ + bool ready = true; + unsigned int key; + + key = HwiP_disable(); + + /* only query if HF source is ready if there is a pending change */ + if (PowerCC26X2_module.xoscPending) + { + ready = PowerCC26X2_getOscHfSourceReady(); + } + + HwiP_restore(key); + + return (ready); +} + +/* + * ======== PowerCC26XX_switchXOSC_HF ======== + * Switch to enable XOSC_HF. + * May only be called when using the PowerCC26XX_SWITCH_XOSC_HF_MANUALLY + * constraint. + * May only be called after ensuring the XOSC_HF is stable by calling + * PowerCC26XX_isStableXOSC_HF(). + */ +void PowerCC26XX_switchXOSC_HF(void) +{ + bool readyToCal; + unsigned int key; + + key = HwiP_disable(); + + Log_printf(LogModule_Power, + Log_INFO, + "PowerCC26XX_switchXOSC_HF: Switch to enable XOSC_HF"); + + /* Since PowerCC26X2_isStableXOSC_HF() should have been called before this + * function, we can just switch without handling the case when the XOSC_HF + * is not ready or PowerCC26X2_module.xoscPending is not true. + */ + PowerCC26X2_oschfTrySwitchToXosc(); + + /* Since configureXOSCHF() was called prior to this function to turn + * on the XOSC_HF, PowerCC26X2_module.xoscPending will be true and + * we can safely set it to false. + */ + PowerCC26X2_module.xoscPending = false; + + /* Allow going into IDLE again since we sucessfully switched + * to XOSC_HF + */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + HwiP_restore(key); + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) + { + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + } +} + +/* + * ======== PowerCC26XX_getResetReason ======== + * Returns the root for latest reset. + */ +PowerCC26X2_ResetReason PowerCC26X2_getResetReason(void) +{ + return PowerCC26X2_module.lastResetReason; +} + +/* * * * * * * * * * * internal and support functions * * * * * * * * * * */ + +/* + * ======== hposcRtcCompensateFxn ======== + */ +static void hposcRtcCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject) +{ + int_fast16_t status; + int32_t relFreqOffset; + + Log_printf(LogModule_Power, + Log_INFO, + "hposcRtcCompensateFxn: HPOSC RTC compensation"); + + relFreqOffset = OSC_HPOSCRelativeFrequencyOffsetGet(currentTemperature); + + OSC_HPOSCRtcCompensate(relFreqOffset); + + /* Register the notification again with updated thresholds */ + status = Temperature_registerNotifyRange(notifyObject, + currentTemperature + PowerCC26X2_HPOSC_RTC_COMPENSATION_DELTA, + currentTemperature - PowerCC26X2_HPOSC_RTC_COMPENSATION_DELTA, + hposcRtcCompensateFxn, + (uintptr_t)NULL); + + if (status != Temperature_STATUS_SUCCESS) + { + Log_printf(LogModule_Power, + Log_ERROR, + "hposcRtcCompensateFxn: Notification registgration faild with status = 0x%x", + status); + + while (1) {} + } +} + +/* + * ======== xosclfRtcCompensateFxn ======== + */ +static void xosclfRtcCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject) +{ + int_fast16_t status; + int32_t xoscLfTemperatureOffset; + int32_t subsecIncCompensated; + + Log_printf(LogModule_Power, + Log_INFO, + "xosclfRtcCompensateFxn: XOSC RTC compensation"); + + /* Get PPM offset of crystal */ + xoscLfTemperatureOffset = OSC_LFXOSCRelativeFrequencyOffsetGet(currentTemperature); + + /* Calculate new subsecond increment, given offset value */ + subsecIncCompensated = RTC_SUBSECINC_32768_HZ - + (int32_t)((RTC_SUBSECINC_32768_HZ * (int64_t)xoscLfTemperatureOffset) / 1000000LL); + + /* Update global RTC subsecond increment value, used by the Oscillator ISR when switching clocks */ + PowerCC26X2_rtcSubSecInc = subsecIncCompensated; + + /* Apply new RTC increment value */ + PowerCC26X2_setSubSecIncToXoscLf(subsecIncCompensated); + + /* Register the notification again with updated thresholds */ + status = Temperature_registerNotifyRange(notifyObject, + currentTemperature + PowerCC26X2_XOSC_LF_RTC_COMPENSATION_DELTA, + currentTemperature - PowerCC26X2_XOSC_LF_RTC_COMPENSATION_DELTA, + xosclfRtcCompensateFxn, + (uintptr_t)NULL); + + if (status != Temperature_STATUS_SUCCESS) + { + Log_printf(LogModule_Power, + Log_ERROR, + "xosclfRtcCompensateFxn: Notification registration faild with status = 0x%x", + status); + + while (1) {} + } +} + +/* + * ======== oscillatorISR ======== + */ +static void oscillatorISR(uintptr_t arg) +{ + uint32_t rawStatus = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCRIS); + uint32_t intStatusMask = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC); + + /* Turn off mask for all flags we will handle */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC) = intStatusMask & ~rawStatus; + + /* XOSC_LF or RCOSC_LF qualified */ + if (rawStatus & PRCM_OSCRIS_LFSRCDONERIS_M & intStatusMask) + { + /* Only switch SubSecInc for XOSC_LF. + * XOSC_HF_DLF and RCOSC_LF do not spend enough time waiting for the + * clock switch after enabling interrupts to accumulate any notable + * drift. + * External LF is just driven immediately and has no transition period. + */ + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_XOSC_LF) + { + /* Set SubSecInc back to 32.768 kHz now that we have switched to + * the RCOSC_LF or XOSC_LF target clock. + */ + PowerCC26X2_setSubSecIncToXoscLf(PowerCC26X2_rtcSubSecInc); + } + + disableLFClockQualifiers(); + + /* Call all registered callback functions waiting on LF clock switch */ + Log_printf(LogModule_Power, + Log_INFO, + "oscillatorISR: Call all registered callback functions waiting on LF clock switch"); + + notify(PowerCC26XX_SCLK_LF_SWITCHED); + } + + /* XOSC_HF ready to switch to */ + if (rawStatus & PRCM_OSCIMSC_HFSRCPENDIM_M & intStatusMask) + { + Log_printf(LogModule_Power, + Log_INFO, + "oscillatorISR: Switch to XOSC_HF"); + + switchXOSCHF(); + } + + /* Clear flags we will handle. Does not really work as expected as + * the flags seem to level-detect and not edge-detect. Until the + * underlying trigger is taken care of, the flag will not deassert + * even when cleared. + * We're clearing at the end in order to prevent the flag from + * immediately asserting again if the underlying trigger was + * not handled yet. + * SCLK_LF switched can never be cleared after triggering + * only masked out. XOSC_HF ready to switch can be cleared + * after switching to XOSC_HF. + */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCICR) = intStatusMask & rawStatus; +} + +/* + * ======== emptyClockFunc ======== + * Clock function used by power policy to schedule early wakeups. + */ +static void emptyClockFunc(uintptr_t arg) +{} + +/* + * ======== disableLFClockQualifiers ======== + * Clock function used for delayed disable of LF clock qualifiers. + */ +static void disableLFClockQualifiers(void) +{ + uint32_t sourceLF; + + /* query LF clock source */ + sourceLF = PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_LF); + + /* is LF source either RCOSC_LF or XOSC_LF yet? */ + if ((sourceLF == OSC_RCOSC_LF) || (sourceLF == OSC_XOSC_LF)) + { + + /* yes, disable the LF clock qualifiers */ + PowerCC26X2_oscDisableQualifiers(); + + /* now finish by releasing the standby disallow constraint */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + else if (sourceLF == OSC_XOSC_HF) + { + /* yes, disable the LF clock qualifiers */ + PowerCC26X2_oscDisableQualifiers(); + + /* do not allow standby since the LF clock is HF derived */ + } +} + +/* + * ======== nopResourceHandler ======== + * special resource handler + */ +static unsigned int nopResourceHandler(unsigned int action) +{ + return (0); +} + +/* + * ======== delayUs ======== + * Polls for an approximate number of us. Not very accurate. + * In this use case we only care about waiting 'at least X' + * and a few extra microseconds will only allow additional + * stabilisation time. + */ +static void delayUs(uint32_t us) +{ + CPUdelay((CC26X2_CLOCK_FREQUENCY / DELAY_SCALING_FACTOR) * us); +} + +/* + * ======== notify ======== + * Send notifications to registered clients. + * Note: Task scheduling is disabled when this function is called. + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC26X2_module.notifyList)) + { + /* point to first client notify object */ + elem = List_head(&PowerCC26X2_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do + { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) + { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + Log_printf(LogModule_Power, + Log_VERBOSE, + "notify: Invoking notification fxn at address 0x%x with event type 0x%x and clientArg 0x%x", + notifyFxn, + eventType, + clientArg); + + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)(eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) + { + Log_printf(LogModule_Power, + Log_WARNING, + "notify: Notification fxn reported error, fxn at address 0x%x with event type 0x%x and notifyStatus 0x%x", + notifyFxn, + eventType, + notifyStatus); + + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== configureRFCoreClocks ======== + * Special dependency function for controlling RF core clocks. + * This function does nothing, but is kept for legacy reasons. + * All functionality has been integrated into the RF driver. + */ +static unsigned int configureRFCoreClocks(unsigned int action) +{ + return (0); +} + +/* + * ======== switchXOSCHF ======== + * Switching to XOSC_HF when it has stabilized. + */ +static void switchXOSCHF(void) +{ + bool readyToCal; + unsigned int key; + + key = HwiP_disable(); + + /* Attempt to switch to XOSC_HF. The call will check whether the + * PENDINGSCLKHFSWITCHING bit is set before initiating the + * switch. + * - XOSC_HF xtal: This should succeed on first try since the OSC + * interrupt is triggered only when the XOSC_HF is ready to switch. + * - XOSC_HF TCXO: At this point, the last stage of the clock qualification + * initiated by setting XOSCHFCTL_BYPASS is still ongoing and + * PENDINGSCLKHFSWITCHING is not set. It will take variable amount of + * time, but at least 10us, before the XOSC_HF is ready to switch. + * The loop ensures that we wait until it is ready. + */ + while (PowerCC26X2_oschfTrySwitchToXosc() == false) {} + + /* The only time we should get here is when PowerCC26X2_module.xoscPending == true + * holds. + * Allow going into IDLE again since we sucessfully switched + * to XOSC_HF + */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + PowerCC26X2_module.xoscPending = false; + + HwiP_restore(key); + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) + { + (*(PowerCC26X2_config.calibrateFxn))(PowerCC26X2_DO_CALIBRATE); + } +} + +/* + * ======== configureXOSCHF ======== + */ +static unsigned int configureXOSCHF(unsigned int action) +{ + /* By checking action == PowerCC26XX_ENABLE and PowerCC26X2_module.xoscPending + * carefully, the function should be idempotent. Calling it with the same + * action more than once will not have any effect until the hardware triggers + * a software state change. + */ + if (action == PowerCC26XX_ENABLE && PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF && + PowerCC26X2_module.xoscPending == false) + { + /* Check if TCXO is selected in CCFG and in addition configured to be enabled + * by the function pointed to by PowerCC26X2_config.enableTCXOFxn. + */ + if ((CCFGRead_XOSC_FREQ() == CCFGREAD_XOSC_FREQ_TCXO) && (PowerCC26X2_config.enableTCXOFxn != NULL)) + { + Log_printf(LogModule_Power, + Log_INFO, + "configureXOSCHF: Enable TCXO qualification"); + + PowerCC26X2_enableTCXOQual(); + + /* Wait for ~10 us for common mode bias to stabilise and clock qual to take effect. */ + delayUs(TCXO_RAMP_DELAY); + + /* Enable power on TCXO */ + (*(PowerCC26X2_config.enableTCXOFxn))(true); + + /* Start clock to wait for TCXO startup time before clock switch + * can be attempted. + */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.tcxoEnableClock)); + } + else + { + /* Turn on and request XOSC_HF from the hardware for regular + * XOSC and HPOSC. TCXO does not require this call until right + * before switching since we do not rely on the harware to + * interrupt the system once the XOSC is stable. + */ + Log_printf(LogModule_Power, + Log_INFO, + "configureXOSCHF: Turn on XOSC_HF"); + + PowerCC26X2_turnOnXosc(); + } + + PowerCC26X2_module.xoscPending = true; + + /* Unless it is disallowed, unmask the XOSC_HF ready to switch flag */ + if (!((CCFGRead_XOSC_FREQ() == CCFGREAD_XOSC_FREQ_TCXO) && (PowerCC26X2_config.enableTCXOFxn != NULL))) + { + if (!(Power_getConstraintMask() & (1 << PowerCC26XX_SWITCH_XOSC_HF_MANUALLY))) + { + + /* Clearing the flag in the ISR does not always work. Clear it + * again just in case + * */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCICR) = PRCM_OSCICR_HFSRCPENDC_M; + + /* Turn on oscillator interrupt for SCLK_HF switching */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_HFSRCPENDIM_M; + } + } + + /* If the device goes into IDLE in between turning on XOSC_HF and + * and switching SCLK_HF to XOSC_HF, the INT_OSC_COMB HFSRCPEND + * trigger will be suppressed. + * The DISALLOW_IDLE constraint should only ever be set whenever + * we transition from xoscPending == false to true. + */ + Power_setConstraint(PowerCC26XX_DISALLOW_IDLE); + } + + /* when release XOSC_HF, auto switch to RCOSC_HF */ + else if (action == PowerCC26XX_DISABLE) + { + Log_printf(LogModule_Power, Log_INFO, "configureXOSCHF: Switch to RCOSC_HF"); + + PowerCC26X2_oschfSwitchToRcosc(); + + /* Handle TCXO if selected in CCFG */ + if ((CCFGRead_XOSC_FREQ() == CCFGREAD_XOSC_FREQ_TCXO) && (PowerCC26X2_config.enableTCXOFxn != NULL)) + { + /* Disable Clock in case we have started it and are waiting for + * the TCXO to stabilise. + * If the Clock is not currently active, this should do nothing. + */ + ClockP_stop(ClockP_handle(&PowerCC26X2_module.tcxoEnableClock)); + + PowerCC26X2_disableTCXOQual(); + + /* Check if function for enabling/disabling TCXO is supported */ + if (PowerCC26X2_config.enableTCXOFxn != NULL) + { + + /* Disable TCXO by turning off power */ + Log_printf(LogModule_Power, Log_INFO, "configureXOSCHF: Disable TCXO"); + + (*(PowerCC26X2_config.enableTCXOFxn))(false); + } + } + + /* If we have not actually switched to XOSC_HF yet, we need to + * undo what we did above when turning on XOSC_HF. Otherwise, + * we may not balance the constraints correctly or get + * unexpected interrupts. + */ + if (PowerCC26X2_module.xoscPending) + { + /* Remove HFSRCPEND from the OSC_COMB interrupt mask */ + uint32_t oscMask = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC); + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCIMSC) = oscMask & ~PRCM_OSCIMSC_HFSRCPENDIM_M; + + /* Clear any residual trigger for HFSRCPEND */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_OSCICR) = PRCM_OSCICR_HFSRCPENDC; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_IDLE); + + PowerCC26X2_module.xoscPending = false; + } + } + return (0); +} + +/* + * ======== switchToTCXO ======== + * Switching to TCXO after TCXO startup time has expired. + */ +static void switchToTCXO(void) +{ + /* Request XOSC_HF. In this instance, that is the TCXO and it will + * immediately be ready to switch to after requesting since we turned it on + * earlier with a GPIO and waited for it to stabilise. + */ + Log_printf(LogModule_Power, Log_INFO, "switchToTCXO: Switch to TCXO"); + + PowerCC26X2_switchToTCXO(); + + /* Switch to TCXO */ + switchXOSCHF(); +} diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.h b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.h new file mode 100644 index 00000000..84a05e30 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC26X2.h + * + * @brief Power manager interface for CC26X2 + * + * The Power header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This header file defines the power resources, constraints, events, sleep + * states and transition latencies for CC26X2. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC26X2_ +#define ti_drivers_power_PowerCC26X2_ + +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! The latency to reserve for resume from STANDBY (usec). */ +#define PowerCC26X2_RESUMETIMESTANDBY 750 + +/*! The total latency to reserve for entry to and exit from STANDBY (usec). */ +#define PowerCC26X2_TOTALTIMESTANDBY 1000 + +/*! The initial delay when waking from STANDBY (usec). */ +#define PowerCC26X2_WAKEDELAYSTANDBY 240 + +/*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ +#define PowerCC26X2_INITIALWAITRCOSC_LF 1000 + +/*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ +#define PowerCC26X2_RETRYWAITRCOSC_LF 1000 + +/*! The initial wait time (usec) before checking if XOSC_HF is stable. */ +#define PowerCC26X2_INITIALWAITXOSC_HF 50 + +/*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ +#define PowerCC26X2_RETRYWAITXOSC_HF 50 + +/*! The initial wait time (usec) before checking if XOSC_LF is stable. */ +#define PowerCC26X2_INITIALWAITXOSC_LF 10000 + +/*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ +#define PowerCC26X2_RETRYWAITXOSC_LF 5000 + +/* Power peripheral IDs. + * See PowerCC26XX.h for peripheral IDs. Some are redefined here for compatibility. + */ + +/* The PKA, UART1 and SSI1 peripherals are not available on CC13X1 and CC26X1 devices */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + /*! Resource ID: PKA Module */ + #define PowerCC26X2_PERIPH_PKA PowerCC26XX_PERIPH_PKA + + /*! Resource ID: UART1 */ + #define PowerCC26X2_PERIPH_UART1 PowerCC26XX_PERIPH_UART1 + + /*! Resource ID: SSI1 */ + #define PowerCC26X2_PERIPH_SSI1 PowerCC26XX_PERIPH_SSI1 + #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /*! Resource ID: SPI1 */ + #define PowerCC26X2_PERIPH_SPI1 PowerCC26X2_PERIPH_SSI1 + #endif + +#endif + +/* The peripherals below are only available on CC13X4, CC26X3 and CC26X4 devices */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + /*! Resource ID: UART2 */ + #define PowerCC26X2_PERIPH_UART2 PowerCC26XX_PERIPH_UART2 + + /*! Resource ID: UART3 */ + #define PowerCC26X2_PERIPH_UART3 PowerCC26XX_PERIPH_UART3 + + /*! Resource ID: SPI2 */ + #define PowerCC26X2_PERIPH_SPI2 PowerCC26XX_PERIPH_SPI2 + /*! Included for compatibility. Please use \ref PowerCC26X2_PERIPH_SPI2 */ + #define PowerCC26X2_PERIPH_SSI2 PowerCC26X2_PERIPH_SPI2 + + /*! Resource ID: SPI3 */ + #define PowerCC26X2_PERIPH_SPI3 PowerCC26XX_PERIPH_SPI3 + /*! Included for compatibility. Please use \ref PowerCC26X2_PERIPH_SPI3 */ + #define PowerCC26X2_PERIPH_SSI3 PowerCC26X2_PERIPH_SPI3 + + /*! Resource ID: I2C1 */ + #define PowerCC26X2_PERIPH_I2C1 PowerCC26XX_PERIPH_I2C1 + +#endif + +/*! The temperature delta in degrees C before the RTC is re-compensated when + * SCLK_LF is derived from SCLK_HF and SCLK_HF is supplied by HPOSC. + */ +#define PowerCC26X2_HPOSC_RTC_COMPENSATION_DELTA 3 + +/*! The temperature delta in degrees C before the RTC is re-compensated when + * SCLK_LF is derived from XOSC_LF + */ +#define PowerCC26X2_XOSC_LF_RTC_COMPENSATION_DELTA 2 + +/* \cond */ +#define PowerCC26X2_NUMRESOURCES PowerCC26XX_NUMRESOURCES +/* \endcond */ + +/* \cond */ +#define PowerCC26X2_NUMCONSTRAINTS (PowerCC26XX_NUMCONSTRAINTS + 0) /* Number of constraints supported */ +/* \endcond */ + +/* \cond */ +/* + * Calibration stages + */ +#define PowerCC26X2_SETUP_CALIBRATE 1 +#define PowerCC26X2_INITIATE_CALIBRATE 2 +#define PowerCC26X2_DO_CALIBRATE 3 +/* \endcond */ + +/*! + * @brief Reasons the device has booted or rebooted. + */ +typedef enum +{ + /*! Device woke up from shutdown due to an IO event */ + PowerCC26X2_RESET_SHUTDOWN_IO = RSTSRC_WAKEUP_FROM_SHUTDOWN, + /*! Device woke up from noise on the JTAG TCK line */ + PowerCC26X2_RESET_TCK_NOISE = RSTSRC_WAKEUP_FROM_TCK_NOISE, + /*! Device reset trggered by software or watchdog timeout */ + PowerCC26X2_RESET_SYSTEM = RSTSRC_SYSRESET, + /*! Device woke up due to warm reset event. Usually debugger related. */ + PowerCC26X2_RESET_WARM_RESET = RSTSRC_WARMRESET, + /*! Device reset due to clock loss */ + PowerCC26X2_RESET_CLK = RSTSRC_CLK_LOSS, + /*! Device reset due to VDDR brownout event */ + PowerCC26X2_RESET_VDDR = RSTSRC_VDDR_LOSS, + /*! Device reset due to VDDS brownout event */ + PowerCC26X2_RESET_VDDS = RSTSRC_VDDS_LOSS, + /*! Device reset due to pin reset */ + PowerCC26X2_RESET_PIN = RSTSRC_PIN_RESET, + /*! Device booted due to power on reset */ + PowerCC26X2_RESET_POR = RSTSRC_PWR_ON, +} PowerCC26X2_ResetReason; + +/*! @brief Global configuration structure */ +typedef struct +{ + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26X2_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26X2_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26X2_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26X2_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int calibrationStage); + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; + /*! + * @brief The function to be used for enabling or disabling the TCXO + * + * If TCXO is configured to be enabled in CCFG this function will + * enable or disable the TCXO by asserting or deasserting power to it. + */ + void (*enableTCXOFxn)(bool arg); +} PowerCC26X2_Config; + +/*! + * @brief PowerCC26X2_ModuleState + * + * Power manager state structure. The application must not access any members + * of this structure! + */ +typedef struct +{ + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct calibrationClock; /*!< Clock object for scheduling wakeups */ + ClockP_Struct tcxoEnableClock; /*!< Clock object for TCXO startup time */ + HwiP_Struct oscHwi; /*!< Hwi object for oscillator stabilisation */ + HwiP_Struct tdcHwi; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t auxHwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint32_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ + uint8_t constraintCounts[PowerCC26X2_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26X2_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int arg); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ + PowerCC26X2_ResetReason lastResetReason; /*!< Reason for the last device reset */ +} PowerCC26X2_ModuleState; + +/*! + * @brief Enable RTC compensation when SCLK_LF is derived from HPOSC + * + * Enables automatic compensation for temperature based clock drift of the RTC + * when SCLK_LF is derived from HPOSC. + * + * It only needs to be called once after the system boots. + * + * This function should only be called when SCLK_LF is configured to be derived + * from HPOSC. + */ +void PowerCC26X2_enableHposcRtcCompensation(void); + +/*! + * @brief Enable RTC compensation when SCLK_LF is derived from XOSC_LF + * + * Enables automatic compensation for temperature-based clock drift of the RTC + * when SCLK_LF is derived from XOSC_LF. + * + * It only needs to be called once after the system boots. + * + * This function should only be called when SCLK_LF is configured to be derived + * from XOSC_LF. + */ +void PowerCC26X2_enableXoscLfRtcCompensation(void); + +/*! + * @brief Returns the reason for the most recent reset + * + * @pre Power_init() + * @post PowerCC26X2_releaseLatches() + * @return #PowerCC26X2_ResetReason + */ +PowerCC26X2_ResetReason PowerCC26X2_getResetReason(void); + +/*! + * @brief Unlatch all IOs + * + * This function releases the latches on all frozen IOs. This function should + * be called after waking up from shutdown and reconfiguring the IO state so + * as not to cause glitches. + * + * @note Calling this function will clear the reset reason register if it was + * #PowerCC26X2_RESET_SHUTDOWN_IO and cause #PowerCC26X2_getResetReason + * not to return the true reset reason. + * + * @pre Power_shutdown() + * @pre PowerCC26X2_getResetReason() + */ +static inline void PowerCC26X2_releaseLatches(void) +{ + PowerCtrlPadSleepDisable(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* POWER_CC26X2_ */ diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c new file mode 100644 index 00000000..a1c01e32 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC.c @@ -0,0 +1,688 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2_calibrateRCOSC.c ======== + */ + +#include + +#include + +#include +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_aux_smph.h) +#include DeviceFamily_constructPath(inc/hw_aux_sysif.h) +#include DeviceFamily_constructPath(inc/hw_aux_tdc.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/ddi.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) + +#define AUX_TDC_SEMAPHORE_NUMBER 1 /* semaphore 1 protects TDC */ +#define NUM_RCOSC_LF_PERIODS_TO_MEASURE 32 /* x RCOSC_LF periods vs XOSC_HF */ +#define NUM_RCOSC_HF_PERIODS_TO_MEASURE 1 /* x RCOSC_HF periods vs XOSC_HF */ +#define ACLK_REF_SRC_RCOSC_HF 0 /* Use RCOSC_HF for ACLK REF */ +#define ACLK_REF_SRC_RCOSC_LF 2 /* Use RCOSC_LF for ACLK REF */ +#define SCLK_LF_OPTION_RCOSC_LF 3 /* defined in cc26_ccfg.xls */ +#define RCOSC_HF_LOW_THRESHOLD_TDC_VALUE \ + 1535 /* If TDC value is within threshold range, no need for another TDC measurement */ +#define RCOSC_HF_PERFECT_TDC_VALUE 1536 /* RCOSC_HF runs at perfect 48 MHz when ending up with this TDC value */ +#define RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE \ + 1537 /* If TDC value is within threshold range, no need for another TDC measurement */ + +/* AUX ISR states */ +#define WAIT_SMPH 0 /* just took SMPH, start RCOSC_LF */ +#define CAL_RCOSC_LF 1 /* just finished RCOSC_LF, start first RCOSC_HF */ +#define CAL_RCOSC_HF1 2 /* just finished 1st RCOSC_HF, start 2nd */ +#define CAL_RCOSC_HF2 3 /* just finished 2nd RCOSC_HF, decide best */ + +/* calibration states */ +#define PowerCC26X2_STATE_TDC_INIT 0 +#define PowerCC26X2_STATE_CAL_LF_1 1 +#define PowerCC26X2_STATE_CAL_LF_2 2 +#define PowerCC26X2_STATE_CAL_HF1_1 3 +#define PowerCC26X2_STATE_CAL_HF1_2 4 +#define PowerCC26X2_STATE_CAL_HF2 5 +#define PowerCC26X2_STATE_CLEANUP 6 + +/* FSM results */ +typedef enum +{ + PowerCC26X2_FSM_RESULT_RUN_FSM, + PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC, + PowerCC26X2_FSM_RESULT_DONE, + PowerCC26X2_FSM_RESULT_ERROR, +} PowerCC26X2_FsmResult; + +/* macros */ +#define Scale_rndInf(x) ((3 * (x) + (((x) < 0) ? -2 : 2)) / 4) + +#ifndef PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + #define PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION 0 +#endif + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION +volatile unsigned int gotSEM = 0; +volatile unsigned int calLFi = 0; +volatile unsigned int calHF1i = 0; +volatile unsigned int calHF2i = 0; +volatile bool doneCal = false; +unsigned int tdcResult_LF = 0; +unsigned int tdcResult_HF1 = 0; +unsigned int tdcResult_HF2 = 0; +unsigned int numISRs = 0; +#endif + +/* Forward declarations */ +static bool getTdcSemaphore(void); +static void calibrateRcoscHf1(int32_t tdcResult); +static void calibrateRcoscHf2(int32_t tdcResult); +static PowerCC26X2_FsmResult runCalibrateFsm(void); +void PowerCC26X2_calibrate(void); +void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern PowerCC26X2_ModuleState PowerCC26X2_module; +extern const PowerCC26X2_Config PowerCC26X2_config; + +/* + * ======== PowerCC26X2_initiateCalibration ======== + * Initiate calibration of RCOSC_LF and RCOSCHF + */ +bool PowerCC26X2_initiateCalibration(void) +{ + unsigned int hwiKey; + bool busy = false; + bool status; + bool gotSem; + + if ((PowerCC26X2_module.calLF == false) && (PowerCC26X2_config.calibrateRCOSC_HF == false)) + { + return (false); + } + + /* make sure calibration is not already in progress */ + hwiKey = HwiP_disable(); + + if (PowerCC26X2_module.busyCal == false) + { + PowerCC26X2_module.busyCal = true; + } + else + { + busy = true; + } + + HwiP_restore(hwiKey); + + if (busy == true) + { + return (false); + } + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 0; + calLFi = 0; + calHF1i = 0; + calHF2i = 0; + doneCal = false; +#endif + + /* set contraint to prohibit standby during calibration sequence */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set dependency to keep XOSC_HF active during calibration sequence */ + Power_setDependency(PowerCC26XX_XOSC_HF); + + /* initiate acquisition of semaphore protecting TDC */ + gotSem = getTdcSemaphore(); + + /* if didn't acquire semaphore, must wait for autotake ISR */ + if (gotSem == false) + { + PowerCC26X2_module.auxHwiState = WAIT_SMPH; + status = false; /* false: don't do anything else until acquire SMPH */ + } + + /* else, semaphore acquired, OK to proceed with first measurement */ + else + { +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 1; +#endif + status = true; /* true: OK to start first measurement */ + } + + return (status); +} + +/* + * ======== PowerCC26X2_auxISR ======== + * ISR for the AUX combo interrupt event. Implements Hwi state machine to + * step through the RCOSC calibration steps. + */ +void PowerCC26X2_auxISR(uintptr_t arg) +{ + uint32_t tdcResult; + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + numISRs++; +#endif + + /* + * disable all events that are part of AUX_COMBINED_INTERRUPT. + * This interrupt is reserved for use during RCOSC calibration. + * Other AUX perihperals that want to generate interrupts to CM3 + * must use dedicated interrupt lines or go through AON combined. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* ****** state = WAIT_SMPH: arrive here if just took the SMPH ****** */ + if (PowerCC26X2_module.auxHwiState == WAIT_SMPH) + { +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + gotSEM = 1; +#endif + } + + /* **** state = CAL_RCOSC_LF: here when just finished LF counting **** */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_LF) + { + /* update the RTC SUBSECINC register based on LF measurement result */ + PowerCC26X2_updateSubSecInc(PowerCC26X2_module.firstLF); + /* No longer first measurement */ + PowerCC26X2_module.firstLF = false; + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + calLFi = 1; +#endif + /* if doing HF calibration initiate it now */ + if (PowerCC26X2_config.calibrateRCOSC_HF) + { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_LF_2; /* next: trigger LF */ + } + + /* else, start cleanup */ + else + { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + } + + /* ****** state = CAL_RCOSC_HF1: here when just finished 1st RCOSC_HF */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_HF1) + { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + tdcResult_HF1 = tdcResult; + calHF1i = 1; +#endif + + /* use first HF measurement to setup new trim values */ + calibrateRcoscHf1(tdcResult); + + /* if HF setting perfect, nothing more to do, calibration is done */ + if ((tdcResult >= RCOSC_HF_LOW_THRESHOLD_TDC_VALUE) && (tdcResult <= RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE)) + { + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + + /* else, tweak trims, initiate another HF measurement */ + else + { + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_2; /* next: HF meas. #2 */ + } + } + + /* ****** state = just finished second RCOSC_HF measurement ****** */ + else if (PowerCC26X2_module.auxHwiState == CAL_RCOSC_HF2) + { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + tdcResult_HF2 = tdcResult; +#endif + /* look for improvement on #2, else revert to previous trim values */ + calibrateRcoscHf2(tdcResult); + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CLEANUP; /* next: cleanup */ + } + + /* do the next calibration step... */ + PowerCC26X2_calibrate(); +} + +/* + * ======== PowerCC26X2_calibrate ======== + */ +void PowerCC26X2_calibrate(void) +{ + PowerCC26X2_FsmResult fsmResult; + + do + { + fsmResult = runCalibrateFsm(); + } while (fsmResult == PowerCC26X2_FSM_RESULT_RUN_FSM); + + switch (fsmResult) + { + case PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC: + /* Intentional fall-through */ + case PowerCC26X2_FSM_RESULT_DONE: + /* Do nothing. Calibration is complete or the + * TDC harware will execute in the background + * and continue the operation. */ + break; + default: + /* Something went wrong. No good way to recover. */ + while (1) {} + } +} + +/* + * ======== runCalibrateFsm ======== + * Execute one state of the clock calibration FSM. + */ +static PowerCC26X2_FsmResult runCalibrateFsm(void) +{ + + switch (PowerCC26X2_module.calStep) + { + + case PowerCC26X2_STATE_TDC_INIT: + + /* set saturation config to 2^24 */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_SATCFG) = AUX_TDC_SATCFG_LIMIT_R24; + + /* set start and stop trigger sources and polarity */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGSRC) = (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF | AUX_TDC_TRIGSRC_STOP_POL_HIGH) | + (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF | AUX_TDC_TRIGSRC_START_POL_HIGH); + + /* set TDC_SRC clock to be XOSC_HF/2 = 24 MHz */ + PowerCC26X2_setTdcClkSrc24M(); + + /* set AUX_SYSIF:TDCCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCCLKCTL) = AUX_SYSIF_TDCCLKCTL_REQ; + + /* finish wait for AUX_SYSIF:TDCCLKCTL.ACK to be set ... */ + while (!(HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCCLKCTL) & AUX_SYSIF_TDCCLKCTL_ACK)) {} + + /* Enable trig count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + /* if LF calibration enabled start LF measurement */ + if (PowerCC26X2_module.calLF) + { + + /* clear UPD_REQ, new sub-second increment is NOT available */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_RTCSUBSECINCCTL) = 0; + + /* set next Swi state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_LF_1; + } + + /* else, start first HF measurement */ + else + { + /* set next Swi state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_1; + } + + /* abort TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* finish wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK) {} + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_LF_1: + + /* set next Hwi state before triggering TDC */ + PowerCC26X2_module.auxHwiState = CAL_RCOSC_LF; + + /* set the ACLK reference clock */ + PowerCC26X2_setAclkRefSrc(ACLK_REF_SRC_RCOSC_LF); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CAL_LF_2: + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF1_1; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK) {} + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_HF1_1: + + PowerCC26X2_module.auxHwiState = CAL_RCOSC_HF1; + + /* set the ACLK reference clock */ + PowerCC26X2_setAclkRefSrc(ACLK_REF_SRC_RCOSC_HF); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CAL_HF1_2: + + PowerCC26X2_module.calStep = PowerCC26X2_STATE_CAL_HF2; + + /* clear AUX_SYSIFTDCREFCLKCTL.REQ... */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK) {} + + return PowerCC26X2_FSM_RESULT_RUN_FSM; + + case PowerCC26X2_STATE_CAL_HF2: + + PowerCC26X2_module.auxHwiState = CAL_RCOSC_HF2; + + /* set the ACLK reference clock */ + PowerCC26X2_setAclkRefSrc(ACLK_REF_SRC_RCOSC_HF); + + /* set AUX_SYSIFTDCREFCLKCTL.REQ */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = AUX_SYSIF_TDCREFCLKCTL_REQ; + + /* Delay for ~110us total until TDCRECLKCTL_ACK is ready */ + ClockP_start(ClockP_handle(&PowerCC26X2_module.calibrationClock)); + + return PowerCC26X2_FSM_RESULT_WAIT_FOR_TDC; + + case PowerCC26X2_STATE_CLEANUP: + + /* release the TDC clock request */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCCLKCTL) = 0; + + /* release the TDC reference clock request */ + HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) = 0; + + /* wait for AUX_SYSIF:TDCCLKCTL.ACK to be cleared ... */ + while ((HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCCLKCTL) & AUX_SYSIF_TDCCLKCTL_ACK)) {} + /* wait for AUX_SYSIFTDCREFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK) {} + + /* + * Disable all interrupts as part of AUX_COMBINED interrupt + * Once we release semaphore, the sensor controller is allowed + * to use the TDC. When it does, we must ensure that this + * does not cause any unexpected interrupts to the CM3. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* release AUX semaphore */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1) = 1; + + /* release the power down constraints and XOSC_HF dependency */ + Power_releaseDependency(PowerCC26XX_XOSC_HF); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set next state */ + PowerCC26X2_module.calStep = PowerCC26X2_STATE_TDC_INIT; + +#if PowerCC26X2_INSTRUMENT_RCOSC_CALIBRATION + doneCal = true; + calHF2i = 1; +#endif + PowerCC26X2_module.busyCal = false; + + return PowerCC26X2_FSM_RESULT_DONE; + + default: + return PowerCC26X2_FSM_RESULT_ERROR; + } +} + +void PowerCC26X2_RCOSC_clockFunc(uintptr_t arg) +{ + + /* Wait any remaining time for TDCREFCLKCTL_ACK. Should not spin here at all. */ + while (!(HWREG(AUX_SYSIF_BASE + NONSECURE_OFFSET + AUX_SYSIF_O_TDCREFCLKCTL) & AUX_SYSIF_TDCREFCLKCTL_ACK)) {} + + /* Set number of periods of ACLK to count */ + if (PowerCC26X2_module.calStep == PowerCC26X2_STATE_CAL_LF_1) + { + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_LF_PERIODS_TO_MEASURE; + } + else + { + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_HF_PERIODS_TO_MEASURE; + } + + /* Reset/clear result of TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_CLR_RESULT; + + /* Clear possible pending interrupt source */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE; + + /* Enable TDC done interrupt as part of AUX_COMBINED interrupt */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE; + + /* Run TDC (start synchronously) */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_RUN_SYNC_START; +} + +/* + * ======== getTdcSemaphore ======== + * Get TDC semaphore (number 1) + */ +static bool getTdcSemaphore(void) +{ + unsigned int own; + + /* try to acquire SMPH */ + own = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1); + + /* if acquired SMPH: done */ + if (own != 0) + { + return (true); + } + + /* clear the interrupt source, can only be cleared when we don't have semaphore */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE; + + /* + * else, did not acquire the semaphore, enable SMPH_AUTOTAKE_DONE event + * (don't OR, write entire register, no other interrupts can be enabled!) + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE; + + /* start AUTOTAKE of semaphore for TDC access */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_AUTOTAKE) = AUX_TDC_SEMAPHORE_NUMBER; + + return (false); +} + +/* + * ======== PowerCC26X2_calibrateRcoscHf1 ======== + * Calibrate RCOSC_HF agains XOSC_HF: compute and setup new trims + */ +static void calibrateRcoscHf1(int32_t tdcResult) +{ + /* *** STEP 1: Find RCOSC_HF-XOSC_HF frequency offset with current trim settings */ + /* Read in current trim settings */ + PowerCC26X2_module.nCtrimCurr = PowerCC26X2_readCtrim(); + PowerCC26X2_module.nCtrimFractCurr = PowerCC26X2_readCtrimFract(); + PowerCC26X2_module.nRtrimCurr = PowerCC26X2_readRtrim(); + + /* + * Find RCOSC_HF-XOSC_HF frequency offset with current trim settings + * Positive value => RCOSC_HF runs slow, CTRIM(FRACT) should be increased + * Negative value => RCOSC_HF runs fast, CTRIM(FRACT) should be decreased + * Resolution: 31.25 kHz; CTRIMFRACT resolution ~30 kHz + */ + PowerCC26X2_module.nDeltaFreqCurr = (int32_t)tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + + /* *** STEP 2: Attempt to calculate more optimal settings */ + if (PowerCC26X2_module.nDeltaFreqCurr == 0) + { + /* If perfect, don't perform second measurement and keep current settings */ + PowerCC26X2_module.bRefine = false; + return; + } + if (PowerCC26X2_module.bRefine) + { + /* + * Trying to find better match across CTRIM/RTRIM. Due to mismatches the + * first try might not have been more optimal than the current setting. + * Continue refining, starting from stored values + */ + } + else + { + /* Start from current values */ + PowerCC26X2_module.nCtrimFractNew = PowerCC26X2_module.nCtrimFractCurr; + PowerCC26X2_module.nCtrimNew = PowerCC26X2_module.nCtrimCurr; + PowerCC26X2_module.nRtrimNew = PowerCC26X2_module.nRtrimCurr; + PowerCC26X2_module.nDeltaFreqNew = PowerCC26X2_module.nDeltaFreqCurr; + } + + /* + * Calculate change to CTRIMFRACT with safe assumptions of gain, + * apply delta to current CTRIMFRACT and convert to valid CTRIM/CTRIMFRACT + */ + PowerCC26X2_module.nCtrimFractNew = PowerCC26X2_module.nCtrimFractNew + + Scale_rndInf(PowerCC26X2_module.nDeltaFreqNew); + PowerCC26X2_module.nCtrimNew = PowerCC26X2_module.nCtrimCurr; + + /* One step of CTRIM is about 500 kHz, so limit to one CTRIM step */ + if (PowerCC26X2_module.nCtrimFractNew < 1) + { + if (PowerCC26X2_module.nRtrimNew == 3) + { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26X2_module.nCtrimFractNew = Math_MAX(1, PowerCC26X2_module.nCtrimFractNew + 21); + PowerCC26X2_module.nRtrimNew = 0; + } + else + { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26X2_module.nCtrimFractNew = Math_MAX(1, PowerCC26X2_module.nCtrimFractNew + 32 - 21); + PowerCC26X2_module.nCtrimNew = Math_MAX(0, PowerCC26X2_module.nCtrimNew - 1); + PowerCC26X2_module.nRtrimNew = 3; + } + } + else if (PowerCC26X2_module.nCtrimFractNew > 30) + { + if (PowerCC26X2_module.nRtrimNew == 0) + { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26X2_module.nCtrimFractNew = Math_MIN(30, PowerCC26X2_module.nCtrimFractNew - 21); + PowerCC26X2_module.nRtrimNew = 3; + } + else + { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26X2_module.nCtrimFractNew = Math_MIN(30, PowerCC26X2_module.nCtrimFractNew - 32 + 21); + PowerCC26X2_module.nCtrimNew = Math_MIN(0x3F, PowerCC26X2_module.nCtrimNew + 1); + PowerCC26X2_module.nRtrimNew = 0; + } + } + else + { + /* We're within sweet spot of current CTRIM => no change */ + } + + /* Find RCOSC_HF vs XOSC_HF frequency offset with new trim settings */ + PowerCC26X2_writeCtrim(PowerCC26X2_module.nCtrimNew); + + /* Enable RCOSCHFCTRIMFRACT_EN */ + PowerCC26X2_writeCtrimFractEn(1); + + /* Modify CTRIM_FRACT */ + PowerCC26X2_writeCtrimFract(PowerCC26X2_module.nCtrimFractNew); + + /* Modify RTRIM */ + PowerCC26X2_writeRtrim(PowerCC26X2_module.nRtrimNew); +} + +/* + * ======== Power_calibrateRcoscHf2 ======== + * Calibrate RCOSC_HF agains XOSC_HF: determine better result, set new trims + */ +static void calibrateRcoscHf2(int32_t tdcResult) +{ + PowerCC26X2_module.nDeltaFreqNew = (int32_t)tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + /* Calculate new delta freq */ + + /* *** STEP 4: Determine whether the new settings are better or worse */ + if (Math_ABS(PowerCC26X2_module.nDeltaFreqNew) <= Math_ABS(PowerCC26X2_module.nDeltaFreqCurr)) + { + /* New settings are better or same -> make current by keeping in registers */ + PowerCC26X2_module.bRefine = false; + } + else + { + /* First measurement was better than second, restore current settings */ + PowerCC26X2_writeCtrim(PowerCC26X2_module.nCtrimCurr); + PowerCC26X2_writeCtrimFract(PowerCC26X2_module.nCtrimFractCurr); + PowerCC26X2_writeRtrim(PowerCC26X2_module.nRtrimCurr); + + /* Enter a refinement mode where we keep searching for better matches */ + PowerCC26X2_module.bRefine = true; + } +} diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC_helpers.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC_helpers.c new file mode 100644 index 00000000..a513417c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_calibrateRCOSC_helpers.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X2_calibrateRCOSC_helpers.c ======== + */ + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(inc/hw_aux_tdc.h) +#include DeviceFamily_constructPath(inc/hw_aux_sysif.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(driverlib/ddi.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/setup_rom.h) + +#define DDI_0_OSC_O_CTL1_LOCAL 0x00000004 /* offset */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M 0x007C0000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S 18 /* shift */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M 0x00020000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S 17 /* shift */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M 0x00000C00 /* mask */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S 10 /* shift */ + +#define ACLK_REF_SRC_RCOSC_HF 0 /* Use RCOSC_HF for ACLK REF */ +#define ACLK_REF_SRC_RCOSC_LF 2 /* Use RCOSC_LF for ACLK REF */ + +#if TFM_ENABLED + #include +#else + /* Define the gateway attributes to nothing instead of ifdefs on each function */ + #define __tz_c_veneer +#endif + +/* + * ======== PowerCC26X2_updateSubSecInc ======== + * Update the SUBSECINC register based on measured RCOSC_LF frequency + * Reads measured result directly from TDC to guard againse injection + */ +__tz_c_veneer void PowerCC26X2_updateSubSecInc(bool firstLF) +{ + int32_t newSubSecInc; + uint32_t oldSubSecInc; + uint32_t subSecInc; + int32_t hposcOffset; + int32_t hposcOffsetInv; + + uint32_t tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + + /* + * Calculate the new SUBSECINC + * Here's the formula: AON_RTC:SUBSECINC = (45813 * NR) / 256 + * Based on measuring 32 LF clock periods + */ + newSubSecInc = (45813 * tdcResult) / 256; + + /* Compensate HPOSC drift if HPOSC is in use */ + if (OSC_IsHPOSCEnabled()) + { + /* Get the HPOSC relative offset at this temperature */ + hposcOffset = OSC_HPOSCRelativeFrequencyOffsetGet(AONBatMonTemperatureGetDegC()); + /* Convert to RF core format */ + hposcOffsetInv = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(hposcOffset); + /* Adjust SUBSECINC */ + newSubSecInc += (((newSubSecInc >> 4) * (hposcOffsetInv >> 3)) >> 15); + } + + /* Apply filter, but not for first calibration */ + if (firstLF) + { + /* Don't apply filter first time, to converge faster */ + subSecInc = newSubSecInc; + } + else + { + /* Read old SUBSECINC value */ + oldSubSecInc = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC) & AON_RTC_SUBSECINC_VALUEINC_M; + /* Apply filter, 0.5 times old value, 0.5 times new value */ + subSecInc = (oldSubSecInc * 1 + newSubSecInc * 1) / 2; + } + + /* Update SUBSECINC values */ + SetupSetAonRtcSubSecInc(subSecInc); +} + +/* + * ======== PowerCC26X2_readCtrim ======== + */ +__tz_c_veneer int32_t PowerCC26X2_readCtrim(void) +{ + return (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL) & DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M) >> + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S; +} + +/* + * ======== PowerCC26X2_readCtrimFract ======== + */ +__tz_c_veneer int32_t PowerCC26X2_readCtrimFract(void) +{ + return (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL) & DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M) >> + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S; +} + +/* + * ======== PowerCC26X2_readRtrim ======== + */ +__tz_c_veneer int32_t PowerCC26X2_readRtrim(void) +{ + return (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL) & + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M) >> + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S; +} + +/* + * ======== PowerCC26X2_writeCtrim ======== + */ +__tz_c_veneer void PowerCC26X2_writeCtrim(int32_t newValue) +{ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + newValue); +} + +/* + * ======== PowerCC26X2_writeCtrimFract ======== + */ +__tz_c_veneer void PowerCC26X2_writeCtrimFract(int32_t newValue) +{ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + newValue); +} + +/* + * ======== PowerCC26X2_writeCtrimFractEn ======== + */ +__tz_c_veneer void PowerCC26X2_writeCtrimFractEn(int32_t newValue) +{ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S, + newValue); +} + +/* + * ======== PowerCC26X2_writeRtrim ======== + */ +__tz_c_veneer void PowerCC26X2_writeRtrim(int32_t newValue) +{ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + newValue); +} + +/* + * ======== PowerCC26X2_setTdcClkSrc24M ======== + */ +__tz_c_veneer void PowerCC26X2_setTdcClkSrc24M(void) +{ + /* set TDC_SRC clock to be XOSC_HF/2 = 24 MHz */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S, + 2); + + /* read back to ensure no race condition between OSC_DIG and AUX_SYSIF */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S); +} + +/* + * ======== PowerCC26X2_setAclkRefSrc ======== + */ +__tz_c_veneer void PowerCC26X2_setAclkRefSrc(uint32_t source) +{ + if (source == ACLK_REF_SRC_RCOSC_HF || source == ACLK_REF_SRC_RCOSC_LF) + { + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + source); + + /* read back to ensure no race condition between OSC_DIG and AUX_SYSIF */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.c new file mode 100644 index 00000000..b5eadfd8 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_aon_pmctl.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/setup_rom.h) + +#if TFM_ENABLED + #include /* __tz_c_veneer */ + #include /* tfm_core_panic() */ +#else + /* Define the gateway attributes to nothing instead of ifdefs on each function */ + #define __tz_c_veneer +#endif + +/* Constants for SubSecInc values at different SCLK_LF frequencies */ +#define SUBSECINC_31250_HZ 0x8637BD +#define SUBSECINC_32768_HZ 0x800000 + +/* + * ======== PowerCC26X2_oscCtlClearXtal ======== + * Clears the XTAL bit in OSC_CTL0 + */ +__tz_c_veneer void PowerCC26X2_oscCtlClearXtal(void) +{ + HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0) = DDI_0_OSC_CTL0_XTAL_IS_24M; +} + +/* + * ======== PowerCC26X2_pmctlDisableJtag ======== + * Disables the JTAG power domain + */ +__tz_c_veneer void PowerCC26X2_pmctlDisableJtag(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; +} + +/* + * ======== PowerCC26X2_sysctrlShutdownWithAbort ======== + * Shuts down the device while + */ +__tz_c_veneer void PowerCC26X2_sysctrlShutdownWithAbort(void) +{ + SysCtrlShutdownWithAbort(); +} + +/* + * ======== PowerCC26X2_prcmEnableCacheRetention ======== + */ +__tz_c_veneer void PowerCC26X2_prcmEnableCacheRetention(void) +{ + PRCMCacheRetentionEnable(); +} + +/* + * ======== PowerCC26X2_oschfSwitchToRcosc ======== + */ +__tz_c_veneer void PowerCC26X2_oschfSwitchToRcosc(void) +{ + OSCHF_SwitchToRcOscTurnOffXosc(); +} + +/* + * ======== PowerCC26X2_oscClockSourceGet ======== + */ +__tz_c_veneer uint32_t PowerCC26X2_oscClockSourceGet(uint32_t ui32SrcClk) +{ + return OSCClockSourceGet(ui32SrcClk); +} + +/* + * ======== PowerCC26X2_oscDisableQualifiers ======== + */ +__tz_c_veneer void PowerCC26X2_oscDisableQualifiers(void) +{ + /* yes, disable the LF clock qualifiers */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M | DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, + 0x3); + + /* enable clock loss detection */ + OSCClockLossEventEnable(); +} + +/* + * ======== PowerCC26X2_getOscHfSourceReady ======== + */ +__tz_c_veneer bool PowerCC26X2_getOscHfSourceReady(void) +{ + return OSCHfSourceReady(); +} + +/* + * ======== PowerCC26X2_oschfTrySwitchToXosc ======== + */ +__tz_c_veneer uint32_t PowerCC26X2_oschfTrySwitchToXosc(void) +{ + /* Switch to the XOSC_HF. Since this function is only called after we get an + * interrupt signifying it is ready to switch, it should always succeed. If + * it does not succeed, the caller should retry. + */ + return OSCHF_AttemptToSwitchToXosc(); +} + +/* + * ======== PowerCC26X2_oscIsHPOSCEnabledWithHfDerivedLfClock ======== + */ +__tz_c_veneer bool PowerCC26X2_oscIsHPOSCEnabledWithHfDerivedLfClock(void) +{ + return OSC_IsHPOSCEnabledWithHfDerivedLfClock(); +} + +/* + * ======== PowerCC26X2_enableTCXOQual ======== + */ +__tz_c_veneer void PowerCC26X2_enableTCXOQual(void) +{ + /* Enable clock qualification on 48MHz signal from TCXO */ + if (CCFGRead_TCXO_TYPE() == 0x1) + { + /* If the selected TCXO type is clipped-sine, also enable internal common-mode bias */ + HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN | + DDI_0_OSC_XOSCHFCTL_TCXO_MODE; + } + else + { + HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE; + } +} + +/* + * ======== PowerCC26X2_disableTCXOQual ======== + */ +__tz_c_veneer void PowerCC26X2_disableTCXOQual(void) +{ + /* Disable clock qualification on 48MHz signal from TCXO and turn + * off TCXO bypass. + * If we do not disable clock qualificaition, it will not run the + * next time we switch to TCXO. + */ + if (CCFGRead_TCXO_TYPE() == 1) + { + /* Also turn off bias if clipped sine TCXO type. The bias + * consumes a few hundred uA. That is fine while the TCXO is + * running but we should not incur this penalty when not running + * on TCXO. + */ + HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE | + DDI_0_OSC_XOSCHFCTL_BYPASS | + DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN; + } + else + { + HWREG(AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_TCXO_MODE | + DDI_0_OSC_XOSCHFCTL_BYPASS; + } +} + +/* + * ======== PowerCC26X2_turnOnXosc ======== + */ +__tz_c_veneer void PowerCC26X2_turnOnXosc(void) +{ + OSCHF_TurnOnXosc(); +} + +/* + * ======== PowerCC26X2_switchToTCXO ======== + * Switching to TCXO after TCXO startup time has expired. + */ +__tz_c_veneer void PowerCC26X2_switchToTCXO(void) +{ + /* Set bypass bit */ + HWREG(AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL) = DDI_0_OSC_XOSCHFCTL_BYPASS; + + /* Request XOSC_HF. In this instance, that is the TCXO. */ + OSCHF_TurnOnXosc(); +} + +/* + * ======== PowerCC26X2_sysCtrlStandby ======== + */ +__tz_c_veneer void PowerCC26X2_sysCtrlStandby(bool retainCache) +{ + SysCtrlStandby(retainCache, VIMS_ON_CPU_ON_MODE, SYSCTRL_PREFERRED_RECHARGE_MODE); +} + +/* + * ======== PowerCC26X2_sysCtrlVoltageConditionalControl ======== + */ +__tz_c_veneer void PowerCC26X2_sysCtrlVoltageConditionalControl(void) +{ + SysCtrl_DCDC_VoltageConditionalControl(); +} + +/* + * ======== PowerCC26X2_sysCtrlIdle ======== + */ +__tz_c_veneer void PowerCC26X2_sysCtrlIdle(uint32_t vimsPdMode) +{ + SysCtrlIdle(vimsPdMode); +} + +#if TFM_ENABLED +/* + * ======== PowerCC26X2_isSecurePeriph ======== + */ +static bool PowerCC26X2_isSecurePeriph(uint32_t prcmPeriph) +{ + bool isSecurePeriph = false; + + if ((prcmPeriph == PRCM_PERIPH_PKA) || (prcmPeriph == PRCM_PERIPH_CRYPTO) || (prcmPeriph == PRCM_PERIPH_TRNG) || + (prcmPeriph == PRCM_PERIPH_UDMA)) + { + isSecurePeriph = true; + } + + return isSecurePeriph; +} +#endif + +/* + * ======== PowerCC26X2_setPeriphDependency ======== + * @param prcmPeriph Must be set to a PRCM_PERIPH_XXXX define + */ +__tz_c_veneer void PowerCC26X2_setPeriphDependency(uint32_t prcmPeriph) +{ +#if TFM_ENABLED + if (!PowerCC26X2_isSecurePeriph(prcmPeriph)) + { + tfm_core_panic(); + } +#endif + + PRCMPeripheralRunEnable(prcmPeriph); + PRCMPeripheralSleepEnable(prcmPeriph); + PRCMPeripheralDeepSleepEnable(prcmPeriph); + + PRCMLoadSet(); + while (!PRCMLoadGet()) {} +} + +/* + * ======== PowerCC26X2_releasePeriphDependency ======== + * @param prcmPeriph Must be set to a PRCM_PERIPH_XXXX define + */ +__tz_c_veneer void PowerCC26X2_releasePeriphDependency(uint32_t prcmPeriph) +{ +#if TFM_ENABLED + if (!PowerCC26X2_isSecurePeriph(prcmPeriph)) + { + tfm_core_panic(); + } +#endif + + PRCMPeripheralRunDisable(prcmPeriph); + PRCMPeripheralSleepDisable(prcmPeriph); + PRCMPeripheralDeepSleepDisable(prcmPeriph); + + PRCMLoadSet(); + while (!PRCMLoadGet()) {} +} + +/* + * ======== PowerCC26X2_setPeriphDeepSleepEnable ======== + * @param prcmPeriph Must be set to a PRCM_PERIPH_XXXX define + */ +__tz_c_veneer void PowerCC26X2_setPeriphDeepSleepEnable(uint32_t prcmPeriph) +{ +#if TFM_ENABLED + if (!PowerCC26X2_isSecurePeriph(prcmPeriph)) + { + tfm_core_panic(); + } +#endif + + PRCMPeripheralDeepSleepEnable(prcmPeriph); +} + +/* + * ======== PowerCC26X2_sysCtrlGetResetSource ======== + */ +__tz_c_veneer uint32_t PowerCC26X2_sysCtrlGetResetSource(void) +{ + return SysCtrlResetSourceGet(); +} + +/* + * ======== PowerCC26X2_setSubSecIncToXoscLf ======== + */ +__tz_c_veneer void PowerCC26X2_setSubSecIncToXoscLf(uint32_t subsecinc) +{ + /* We only want to set SubSecInc if we are running on XOSC_LF */ + if (CCFGRead_SCLK_LF_OPTION() == CCFGREAD_SCLK_LF_OPTION_XOSC_LF) + { + /* Check that the argument is within allowed limits. The range is + * the nominal RTC increment value (0x800000) +/- 2%. This is to + * allow RTC SWTCXO to set the value within a reasonable range, + * without allowing arbitrary values to be written + */ + if (subsecinc > 0x7D70A3 && subsecinc < 0x828F5C) + { + /* Set SubSecInc back to 32.768 kHz, or a compensated value + * if RTC SWTCXO is enabled. In that case, the argument will + * be an already temperature-adjusted value + */ + SetupSetAonRtcSubSecInc(subsecinc); + } + } +} + +/* + * ======== PowerCC26X2_sysCtrlUpdateVoltageRegulator ======== + */ +__tz_c_veneer void PowerCC26X2_sysCtrlUpdateVoltageRegulator(void) +{ + SysCtrl_DCDC_VoltageConditionalControl(); +} + +/* + * ======== PowerCC26X2_sysCtrlReset ======== + */ +__tz_c_veneer void PowerCC26X2_sysCtrlReset(void) +{ + SysCtrlSystemReset(); +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.h b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.h new file mode 100644 index 00000000..c59063da --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X2_helpers.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* This file is for internal use only. These functions are called by the power + * driver during normal operation, but may trigger a secure gateway instruction + * on devices where the core supports it. Other calls to these functions may + * have a negative impact on the power driver. + */ + +/* Functions implemented in PowerCC26X2_helpers.c */ +void PowerCC26X2_oscCtlClearXtal(void); +void PowerCC26X2_pmctlDisableJtag(void); +void PowerCC26X2_sysctrlShutdownWithAbort(void); +void PowerCC26X2_prcmEnableCacheRetention(void); +void PowerCC26X2_oschfSwitchToRcosc(void); +uint32_t PowerCC26X2_oscClockSourceGet(uint32_t ui32SrcClk); +void PowerCC26X2_oscDisableQualifiers(void); +bool PowerCC26X2_getOscHfSourceReady(void); +uint32_t PowerCC26X2_oschfTrySwitchToXosc(void); +bool PowerCC26X2_oscIsHPOSCEnabledWithHfDerivedLfClock(void); +void PowerCC26X2_enableTCXOQual(void); +void PowerCC26X2_disableTCXOQual(void); +void PowerCC26X2_switchToTCXO(void); +void PowerCC26X2_turnOnXosc(void); +void PowerCC26X2_sysCtrlStandby(bool retainCache); +void PowerCC26X2_sysCtrlVoltageConditionalControl(void); +void PowerCC26X2_sysCtrlIdle(uint32_t vimsPdMode); +void PowerCC26X2_setPeriphDependency(uint32_t prcmPeriph); +void PowerCC26X2_releasePeriphDependency(uint32_t prcmPeriph); +void PowerCC26X2_setPeriphDeepSleepEnable(uint32_t prcmPeriph); +uint32_t PowerCC26X2_sysCtrlGetResetSource(void); +void PowerCC26X2_setSubSecIncToXoscLf(uint32_t subsecinc); +void PowerCC26X2_sysCtrlUpdateVoltageRegulator(void); +void PowerCC26X2_sysCtrlReset(void); + +/* Functions implemented in PowerCC26X2_calibrateRCOSC_helpers.c */ +void PowerCC26X2_updateSubSecInc(bool firstLF); +int32_t PowerCC26X2_readCtrim(void); +int32_t PowerCC26X2_readCtrimFract(void); +int32_t PowerCC26X2_readRtrim(void); +void PowerCC26X2_writeCtrim(int32_t newValue); +void PowerCC26X2_writeCtrimFract(int32_t newValue); +void PowerCC26X2_writeCtrimFractEn(int32_t newValue); +void PowerCC26X2_writeRtrim(int32_t newValue); +void PowerCC26X2_setTdcClkSrc24M(void); +void PowerCC26X2_setAclkRefSrc(uint32_t source); diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26X4_stubs.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X4_stubs.c new file mode 100644 index 00000000..4278af7c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26X4_stubs.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26X4_stubs.c ======== + * Contains power function stubs which are used for drivers built into the + * TF-M binary. + */ + +#include + +#include + +#ifndef TFM_BUILD /* TFM_BUILD indicates this is a TF-M build */ + #error "Power function stubs are for TF-M builds only" +#endif + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + (void)constraintId; /* Unused arg */ + return (Power_SOK); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId) +{ + (void)resourceId; /* Unused arg */ + return (Power_SOK); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + (void)constraintId; /* Unused arg */ + return (Power_SOK); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(Power_Resource resourceId) +{ + (void)resourceId; /* Unused arg */ + return (Power_SOK); +} \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.c new file mode 100644 index 00000000..82fceed2 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.c @@ -0,0 +1,1533 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26XX.c ======== + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_prcm.h) +#include DeviceFamily_constructPath(inc/hw_nvic.h) +#include DeviceFamily_constructPath(inc/hw_aon_wuc.h) +#include DeviceFamily_constructPath(inc/hw_aon_rtc.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(inc/hw_rfc_pwr.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/pwr_ctrl.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/aon_wuc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) +#include DeviceFamily_constructPath(driverlib/aux_wuc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/vims.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/setup.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +static unsigned int configureXOSCHF(unsigned int action); +static unsigned int nopResourceHandler(unsigned int action); +static unsigned int configureRFCoreClocks(unsigned int action); +static void switchXOSCHFclockFunc(uintptr_t arg0); +static void lfClockReadyCallback(uintptr_t arg); +static void disableLfClkQualifiersEnableClkLoss(); +static void emptyClockFunc(uintptr_t arg); +static int_fast16_t notify(uint_fast16_t eventType); + +/* RCOSC calibration functions functions */ +extern void PowerCC26XX_doCalibrate(void); +extern bool PowerCC26XX_initiateCalibration(void); +extern void PowerCC26XX_auxISR(uintptr_t arg); +extern void PowerCC26XX_RCOSC_clockFunc(uintptr_t arg); + +/* Externs */ +extern const PowerCC26XX_Config PowerCC26XX_config; + +/* Macro for weak definition of the Power Log module */ +Log_MODULE_DEFINE_WEAK(LogModule_Power, {0}); + +/* Module_State */ +PowerCC26XX_ModuleState PowerCC26XX_module = { + .notifyList = {NULL}, /* list of registered notifications */ + .constraintMask = 0, /* the constraint mask */ + .clockObj = {0}, /* Clock object for scheduling wakeups */ + .xoscClockObj = {0}, /* Clock object for XOSC_HF switching */ + .lfClockObj = {0}, /* Clock object for LF clock check */ + .calClockStruct = {0}, /* Clock object for RCOSC calibration */ + .hwiStruct = {0}, /* hwi object for calibration */ + .nDeltaFreqCurr = 0, /* RCOSC calibration variable */ + .nCtrimCurr = 0, /* RCOSC calibration variable */ + .nCtrimFractCurr = 0, /* RCOSC calibration variable */ + .nCtrimNew = 0, /* RCOSC calibration variable */ + .nCtrimFractNew = 0, /* RCOSC calibration variable */ + .nRtrimNew = 0, /* RCOSC calibration variable */ + .nRtrimCurr = 0, /* RCOSC calibration variable */ + .nDeltaFreqNew = 0, /* RCOSC calibration variable */ + .bRefine = false, /* RCOSC calibration variable */ + .state = Power_ACTIVE, /* current transition state */ + .xoscPending = false, /* is XOSC_HF activation in progress? */ + .calLF = false, /* calibrate RCOSC_LF? */ + .hwiState = 0, /* calibration AUX ISR state */ + .busyCal = false, /* already busy calibrating */ + .calStep = 1, /* current calibration step */ + .firstLF = true, /* is this first LF calibration? */ + .enablePolicy = false, /* default value is false */ + .initialized = false, /* whether Power_init has been called */ +#if defined(DeviceFamily_CC26X0R2) + .emulatorAttached = false, /* emulator attached during boot */ +#endif + .constraintCounts = {0, 0, 0, 0, 0, 0, 0}, + .resourceCounts = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + .resourceHandlers = {configureRFCoreClocks, configureXOSCHF, nopResourceHandler}, /* special resource handler + functions */ + .policyFxn = NULL /* power policyFxn */ +}; + +/* resource database */ +const PowerCC26XX_ResourceRecord resourceDB[PowerCC26XX_NUMRESOURCES] = { + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER0}, /* PERIPH_GPT0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER1}, /* PERIPH_GPT1 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER2}, /* PERIPH_GPT2 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TIMER3}, /* PERIPH_GPT3 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_SSI0}, /* PERIPH_SSI0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_UART0}, /* PERIPH_UART0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_SERIAL, PRCM_PERIPH_I2C0}, /* PERIPH_I2C0 */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_TRNG}, /* PERIPH_TRNG */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_GPIO}, /* PERIPH_GPIO */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_UDMA}, /* PERIPH_UDMA */ + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_CRYPTO}, /* PERIPH_CRYPTO */ + {PowerCC26XX_PERIPH | PowerCC26XX_PERIPH_UDMA, PRCM_PERIPH_I2S}, /* PERIPH_I2S */ + {PowerCC26XX_SPECIAL | PowerCC26XX_DOMAIN_RFCORE, 0}, /* PERIPH_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 1}, /* XOSC_HF */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_PERIPH}, /* DOMAIN_PERIPH */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_SERIAL}, /* DOMAIN_SERIAL */ + {PowerCC26XX_DOMAIN | PowerCC26XX_NOPARENT, PRCM_DOMAIN_RFCORE}, /* DOMAIN_RFCORE */ + {PowerCC26XX_SPECIAL | PowerCC26XX_NOPARENT, 2} /* DOMAIN_SYSBUS */ + {0}, + {PowerCC26XX_PERIPH | PowerCC26XX_DOMAIN_PERIPH, PRCM_PERIPH_SSI1}, /* PERIPH_SSI1 */ +}; + +/* ****************** Power APIs ******************** */ + +/* + * ======== Power_disablePolicy ======== + * Do not run the configured policy + */ +bool Power_disablePolicy(void) +{ + bool enablePolicy = PowerCC26XX_module.enablePolicy; + PowerCC26XX_module.enablePolicy = false; + + return (enablePolicy); +} + +/* + * ======== Power_enablePolicy ======== + * Run the configured policy + */ +void Power_enablePolicy(void) +{ + PowerCC26XX_module.enablePolicy = true; +} + +/* + * ======== Power_getConstraintMask ======== + * Get a bitmask indicating the constraints that have been registered with + * Power. + */ +uint_fast32_t Power_getConstraintMask(void) +{ + return (PowerCC26XX_module.constraintMask); +} + +/* + * ======== Power_getDependencyCount ======== + * Get the count of dependencies that are currently declared upon a resource. + */ +int_fast16_t Power_getDependencyCount(Power_Resource resourceId) +{ + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + return ((int_fast16_t)PowerCC26XX_module.resourceCounts[resourceId]); +} + +/* + * ======== Power_getConstraintCount ======== + * Get the count of constraints that are currently set on a certain + * operational transition + */ +int_fast16_t Power_getConstraintCount(uint_fast16_t constraintId) +{ + DebugP_assert(constraintId < PowerCC26XX_NUMCONSTRAINTS); + + if (constraintId < PowerCC26XX_NUMCONSTRAINTS) + { + return (int_fast16_t)PowerCC26XX_module.constraintCounts[constraintId]; + } + else + { + return (int_fast16_t)Power_EINVALIDINPUT; + } +} + +/* + * ======== Power_getTransitionLatency ======== + * Get the transition latency for a sleep state. The latency is reported + * in units of microseconds. + */ +uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, uint_fast16_t type) +{ + uint32_t latency = 0; + + if (type == Power_RESUME) + { + if (sleepState == PowerCC26XX_STANDBY) + { + latency = PowerCC26XX_RESUMETIMESTANDBY; + } + } + else + { + if (sleepState == PowerCC26XX_STANDBY) + { + latency = PowerCC26XX_TOTALTIMESTANDBY; + } + } + + return (latency); +} + +/* + * ======== Power_getTransitionState ======== + * Get the current sleep transition state. + */ +uint_fast16_t Power_getTransitionState(void) +{ + return (PowerCC26XX_module.state); +} + +/* + * ======== Power_idleFunc ======== + * Function needs to be plugged into the idle loop. + * It calls the configured policy function if the + * 'enablePolicy' flag is set. + */ +void Power_idleFunc() +{ + if (PowerCC26XX_module.enablePolicy) + { + if (PowerCC26XX_module.policyFxn != NULL) + { + (*(PowerCC26XX_module.policyFxn))(); + } + } +} + +/* + * ======== Power_init ======== + */ +int_fast16_t Power_init() +{ + ClockP_Params clockParams; + uint32_t ccfgLfClkSrc; + uint32_t timeout; + + /* if this function has already been called, just return */ + if (PowerCC26XX_module.initialized) + { + return (Power_SOK); + } + +#if defined(DeviceFamily_CC26X0R2) + /* check to see if the JTAG_PD is on, meaning the emulator was attached during boot and */ + /* that the user is in an active debug session */ + PowerCC26XX_module.emulatorAttached = (HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) == + AON_WUC_PWRSTAT_JTAG_PD_ON; +#endif + + /* set module state field 'initialized' to true */ + PowerCC26XX_module.initialized = true; + + /* set the module state enablePolicy field */ + PowerCC26XX_module.enablePolicy = PowerCC26XX_config.enablePolicy; + + /* copy the Power policy function to module state */ + PowerCC26XX_module.policyFxn = PowerCC26XX_config.policyFxn; + + /* construct the Clock object for scheduling of wakeups */ + /* initiated and started by the power policy */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26XX_module.clockObj, &emptyClockFunc, 0, &clockParams); + + /* construct the Clock object for XOSC_HF switching */ + /* initiated and started by Power module when activating XOSC_HF */ + ClockP_construct(&PowerCC26XX_module.xoscClockObj, &switchXOSCHFclockFunc, 0, &clockParams); + + /* construct the Clock object for disabling LF clock quailifiers */ + /* one shot, auto start, first expires at 100 msec */ + ClockP_construct(&PowerCC26XX_module.lfClockObj, &lfClockReadyCallback, 0, &clockParams); + + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_SETUP_CALIBRATE); + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* check if should calibrate RCOSC_LF */ + if (PowerCC26XX_config.calibrateRCOSC_LF) + { + /* verify RCOSC_LF is the LF clock source */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) + { + PowerCC26XX_module.calLF = true; + } + } + + /* + * if LF source is RCOSC_LF or XOSC_LF: assert DISALLOW_STANDBY constraint + * and start a timeout to check for activation + */ + if ((ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) || (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF)) + { + + /* disallow STANDBY pending LF clock quailifier disabling */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* determine timeout */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) + { + timeout = PowerCC26XX_INITIALWAITRCOSC_LF; + } + else + { + timeout = PowerCC26XX_INITIALWAITXOSC_LF; + } + + /* start the Clock object */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), (timeout / ClockP_getSystemTickPeriod())); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } + + /* + * else, if the LF clock source is external, can disable clock qualifiers + * now; no need to assert DISALLOW_STANDBY or start the Clock object + */ + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF) + { + + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + } + /* + * else, user has requested LF to be derived from XOSC_HF + */ + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF) + { + /* disallow standby */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* wait for the XOSC_HF to power up if it's not ready.. */ + if (OSCClockSourceGet(OSC_SRC_CLK_LF) == OSC_XOSC_HF) + { + /* XOSC_HF is ready. Simply disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(NULL); + } + else + { + /* XOSC_HF is not ready yet, schedule clock to check again later */ + timeout = PowerCC26XX_INITIALWAITXOSC_HF / ClockP_getSystemTickPeriod(); + /* start the Clock object */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), (timeout / ClockP_getSystemTickPeriod())); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } + } + + /* if VIMS RAM is configured as GPRAM: set retention constraint */ + if (!CCFGRead_DIS_GPRAM()) + { + Power_setConstraint(PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY); + } + + return (Power_SOK); +} + +/* + * ======== Power_registerNotify ======== + * Register a function to be called on a specific power event. + * + */ +int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, + uint_fast16_t eventTypes, + Power_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + int_fast16_t status = Power_SOK; + + /* check for NULL pointers */ + if ((pNotifyObj == NULL) || (notifyFxn == NULL)) + { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_registerNotify: Notify registration failed due to NULL pointer"); + + status = Power_EINVALIDPOINTER; + } + + else + { + /* fill in notify object elements */ + pNotifyObj->eventTypes = eventTypes; + pNotifyObj->notifyFxn = notifyFxn; + pNotifyObj->clientArg = clientArg; + + Log_printf(LogModule_Power, + Log_INFO, + "Power_registerNotify: Register fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + notifyFxn, + eventTypes, + clientArg); + + /* place notify object on event notification queue */ + List_put(&PowerCC26XX_module.notifyList, (List_Elem *)pNotifyObj); + } + + return (status); +} + +/* + * ======== Power_releaseConstraint ======== + * Release a previously declared constraint. + */ +int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + uint8_t count; + + DebugP_assert(constraintId < PowerCC26XX_NUMCONSTRAINTS); + + key = HwiP_disable(); + + /* get the count of the constraint */ + count = PowerCC26XX_module.constraintCounts[constraintId]; + + DebugP_assert(count != 0); + + count--; + + /* save the updated count */ + PowerCC26XX_module.constraintCounts[constraintId] = count; + + if (count == 0) + { + PowerCC26XX_module.constraintMask &= ~(1 << constraintId); + } + + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_releaseDependency ======== + * Release a previously declared dependency. + */ +int_fast16_t Power_releaseDependency(Power_Resource resourceId) +{ + PowerCC26XX_Resource parent; + uint8_t count; + uint32_t id; + unsigned int key; + + /* assert resourceId is valid */ + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and decrement the reference count */ + count = PowerCC26XX_module.resourceCounts[resourceId]; + + DebugP_assert(count != 0); + + count--; + + /* save the reference count */ + PowerCC26XX_module.resourceCounts[resourceId] = count; + + /* if this was the last dependency being released.., */ + if (count == 0) + { + /* deactivate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) + { + PRCMPeripheralRunDisable(id); + PRCMPeripheralSleepDisable(id); + PRCMPeripheralDeepSleepDisable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) {} + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) + { + /* call the special handler */ + PowerCC26XX_module.resourceHandlers[id](PowerCC26XX_DISABLE); + } + + /* else resource is a power domain */ + else + { + PRCMPowerDomainOff(id); + while (PRCMPowerDomainsAllOff(id) != PRCM_DOMAIN_POWER_OFF) {} + } + + /* propagate release up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if 1st parent, make recursive call to release that dependency */ + if (parent < PowerCC26XX_NUMRESOURCES) + { + Power_releaseDependency(parent); + } + } + + Log_printf(LogModule_Power, + Log_INFO, + "Power_releaseDependency: Updated resource counter = %d for resource ID = 0x%x", + PowerCC26XX_module.resourceCounts[resourceId], resourceId); + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setConstraint ======== + * Declare an operational constraint. + */ +int_fast16_t Power_setConstraint(uint_fast16_t constraintId) +{ + unsigned int key; + + DebugP_assert(constraintId < PowerCC26XX_NUMCONSTRAINTS); + + /* disable interrupts */ + key = HwiP_disable(); + + /* set the specified constraint in the constraintMask */ + PowerCC26XX_module.constraintMask |= 1 << constraintId; + + /* increment the specified constraint count */ + PowerCC26XX_module.constraintCounts[constraintId]++; + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setDependency ======== + * Declare a dependency upon a resource. + */ +int_fast16_t Power_setDependency(Power_Resource resourceId) +{ + PowerCC26XX_Resource parent; + uint8_t count; + uint32_t id; + unsigned int key; + + DebugP_assert(resourceId < PowerCC26XX_NUMRESOURCES); + + /* disable interrupts */ + key = HwiP_disable(); + + /* read and increment reference count */ + count = PowerCC26XX_module.resourceCounts[resourceId]++; + + /* if resource was NOT activated previously ... */ + if (count == 0) + { + /* propagate set up the dependency tree ... */ + + /* check for a first parent */ + parent = resourceDB[resourceId].flags & PowerCC26XX_PARENTMASK; + + /* if first parent, make recursive call to set that dependency */ + if (parent < PowerCC26XX_NUMRESOURCES) + { + Power_setDependency(parent); + } + + /* now activate this resource ... */ + id = resourceDB[resourceId].driverlibID; + + /* is resource a peripheral?... */ + if (resourceDB[resourceId].flags & PowerCC26XX_PERIPH) + { + PRCMPeripheralRunEnable(id); + PRCMPeripheralSleepEnable(id); + PRCMPeripheralDeepSleepEnable(id); + PRCMLoadSet(); + while (!PRCMLoadGet()) {} + } + /* else, does resource require a special handler?... */ + else if (resourceDB[resourceId].flags & PowerCC26XX_SPECIAL) + { + /* call the special handler */ + PowerCC26XX_module.resourceHandlers[id](PowerCC26XX_ENABLE); + } + /* else resource is a power domain */ + else + { + PRCMPowerDomainOn(id); + while (PRCMPowerDomainsAllOn(id) != PRCM_DOMAIN_POWER_ON) {} + } + } + + Log_printf(LogModule_Power, + Log_INFO, + "Power_setDependency: Updated resource counter = %d for resource ID = 0x%x", + PowerCC26XX_module.resourceCounts[resourceId], resourceId); + + /* re-enable interrupts */ + HwiP_restore(key); + + return (Power_SOK); +} + +/* + * ======== Power_setPolicy ======== + * Set the Power policy function + */ +void Power_setPolicy(Power_PolicyFxn policy) +{ + PowerCC26XX_module.policyFxn = policy; +} + +/* + * ======== Power_shutdown ======== + */ +int_fast16_t Power_shutdown(uint_fast16_t shutdownState, uint_fast32_t shutdownTime) +{ + int_fast16_t status = Power_EFAIL; + unsigned int constraints; + unsigned int hwiKey; + + /* disable interrupts */ + hwiKey = HwiP_disable(); + + /* check if there is a constraint to prohibit shutdown */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_DISALLOW_SHUTDOWN)) + { + status = Power_ECHANGE_NOT_ALLOWED; + } + + /* OK to shutdown ... */ + else if (PowerCC26XX_module.state == Power_ACTIVE) + { + /* set new transition state to entering shutdown */ + PowerCC26XX_module.state = Power_ENTERING_SHUTDOWN; + + /* signal all clients registered for pre-shutdown notification */ + status = notify(PowerCC26XX_ENTERING_SHUTDOWN); + + /* check for any error */ + if (status != Power_SOK) + { + PowerCC26XX_module.state = Power_ACTIVE; + HwiP_restore(hwiKey); + return (status); + } + + /* now proceed with shutdown sequence ... */ + + /* If the JTAG_PD is on, make sure that the DUT reboots without + * stopping for halt-in-boot when it enters shutdown. */ +#if defined(DeviceFamily_CC26X0R2) + uint32_t aonSysctrlResetctl; + + if ((HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) && + (!PowerCC26XX_module.emulatorAttached)) + { + /* set BOOT_DET = b10. + * The next time the device enters shutdown the + * device will start booting immediately because the JTAG_PD is already on. + * However since since BOOT_DET == b10, the boot code will run not wait + * for a GPIO interrupt, but rather run to completion and branch to the + * flash image with the JTAG_PD turned off. + */ + aonSysctrlResetctl = HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & + ~(AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M | + AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M | AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M); + /* To get BOOT_DET = b10, set BOOT_DET_1_SET and BOOT_DET_0_CLR*/ + HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL) = aonSysctrlResetctl | (AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR | + AON_SYSCTL_RESETCTL_BOOT_DET_1_SET); + } +#endif + + /* 1. Switch HF, MF, and LF clocks to source from RCOSC_HF */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_RCOSC_HF) + { + /* 1.1. Source HF and MF from RCOSC_HF */ + OSCClockSourceSet(OSC_SRC_CLK_HF | OSC_SRC_CLK_MF, OSC_RCOSC_HF); + while (!OSCHfSourceReady()) {} + OSCHfSourceSwitch(); + } + /* 1.2. Source LF from RCOSC_LF */ + OSCClockSourceSet(OSC_SRC_CLK_LF, OSC_RCOSC_LF); + while (OSCClockSourceGet(OSC_SRC_CLK_LF) != OSC_RCOSC_LF) {} + + /* 2. Make sure DMA and CRYTO clocks are off in deep-sleep */ + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); + PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA); + PRCMLoadSet(); + while (!PRCMLoadGet()) {} + + /* 3. Power OFF AUX and disconnect from bus */ + AUXWUCPowerCtrl(AUX_WUC_POWER_OFF); + + /* 4. Remove AUX force ON */ + HWREG(AON_WUC_BASE + AON_WUC_O_AUXCTL) &= ~AON_WUC_AUXCTL_AUX_FORCE_ON; + + /* + * 5. Reset AON event source IDs to avoid pending events powering + * on MCU/AUX + */ + HWREG(AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL) = 0x3F3F3F3F; + HWREG(AON_EVENT_BASE + AON_EVENT_O_AUXWUSEL) = 0x003F3F3F; + + /* sync AON */ + SysCtrlAonSync(); + + /* + * 6. Enable shutdown - this latches the IOs, so configuration of + * IOCFGx registers must be done prior to this + */ + AONWUCShutDownEnable(); + + /* 7. Sync AON */ + SysCtrlAonSync(); + + /* 8. Wait until AUX powered off */ + while (AONWUCPowerStatusGet() & AONWUC_AUX_POWER_ON) {} + + /* 9. Request to power off MCU when go to deep sleep */ + PRCMMcuPowerOff(); + + /* + * 10. Turn off power domains inside MCU VD (BUS, FL_BUS, RFC, + * CPU) + */ + PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU | + PRCM_DOMAIN_VIMS); + + /* 11. Deep sleep to activate shutdown */ + PRCMDeepSleep(); + } + else + { + status = Power_EBUSY; + } + + /* NOTE: if shutdown succeeded, should never get here */ + + /* return failure status */ + PowerCC26XX_module.state = Power_ACTIVE; + + /* re-enable interrupts */ + HwiP_restore(hwiKey); + + /* if get here, failed to shutdown, return error code */ + return (status); +} + +/* + * ======== Power_sleep ======== + */ +int_fast16_t Power_sleep(uint_fast16_t sleepState) +{ + int_fast16_t status = Power_SOK; + int_fast16_t notifyStatus = Power_SOK; + int_fast16_t lateNotifyStatus = Power_SOK; + unsigned int xosc_hf_active = false; + uint_fast16_t postEventLate; + uint32_t poweredDomains = 0; + uint_fast16_t preEvent; + uint_fast16_t postEvent; + unsigned int constraints; + bool retainCache = false; + uint32_t modeVIMS; + +#if defined(DeviceFamily_CC26X0R2) + /* has JTAG_PD been turned AFTER boot due to TCK noise? */ + if ((HWREG(AON_WUC_BASE + AON_WUC_O_PWRSTAT) & AON_WUC_PWRSTAT_JTAG_PD_ON) && + (!PowerCC26XX_module.emulatorAttached)) + { + /* notify all subscribers */ + notify(PowerCC26XX_JTAG_PD_TURNED_ON); + } +#endif + + /* first validate the sleep code */ + if (sleepState != PowerCC26XX_STANDBY) + { + status = Power_EINVALIDINPUT; + + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed with status = 0x%x", + status); + } + + else + { + + /* check to make sure Power is not busy with another transition */ + if (PowerCC26XX_module.state == Power_ACTIVE) + { + /* set transition state to entering sleep */ + PowerCC26XX_module.state = Power_ENTERING_SLEEP; + } + else + { + status = Power_EBUSY; + + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed with status = 0x%x", + status); + } + + if (status == Power_SOK) + { + + /* setup sleep vars */ + preEvent = PowerCC26XX_ENTERING_STANDBY; + postEvent = PowerCC26XX_AWAKE_STANDBY; + postEventLate = PowerCC26XX_AWAKE_STANDBY_LATE; + + /* disable scheduling */ + PowerCC26XX_schedulerDisable(); + + /* signal all clients registered for pre-sleep notification */ + status = notify(preEvent); + + /* check for any error */ + if (status != Power_SOK) + { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Entering standby failed due to pre-sleep notification status = 0x%x", + status); + + PowerCC26XX_module.state = Power_ACTIVE; + PowerCC26XX_schedulerRestore(); + return (status); + } + + /* 1. Freeze the IOs on the boundary between MCU and AON */ + AONIOCFreezeEnable(); + + /* 2. If XOSC_HF is active, force it off */ + if (OSCClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) + { + Log_printf(LogModule_Power, + Log_VERBOSE, + "Power_sleep: Forcing XOSC_HF off"); + + xosc_hf_active = true; + configureXOSCHF(PowerCC26XX_DISABLE); + } + + /* 3. Allow AUX to power down */ + AONWUCAuxWakeupEvent(AONWUC_AUX_ALLOW_SLEEP); + + /* 4. Make sure writes take effect */ + SysCtrlAonSync(); + + /* now proceed to transition to Power_STANDBY ... */ + + /* 5. Query and save domain states before powering them off */ + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_RFCORE)) + { + poweredDomains |= PRCM_DOMAIN_RFCORE; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_SERIAL)) + { + poweredDomains |= PRCM_DOMAIN_SERIAL; + } + if (Power_getDependencyCount(PowerCC26XX_DOMAIN_PERIPH)) + { + poweredDomains |= PRCM_DOMAIN_PERIPH; + } + + /* 6. Gate running deep sleep clocks for Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) + { + PRCMPeripheralDeepSleepDisable(resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) + { + PRCMPeripheralDeepSleepDisable(resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + /* 7. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 8. Request power off of domains in the MCU voltage domain */ + PRCMPowerDomainOff(poweredDomains | PRCM_DOMAIN_CPU); + + /* 9. Request uLDO during standby */ + PRCMMcuUldoConfigure(true); + + /* query constraints to determine if cache should be retained */ + constraints = Power_getConstraintMask(); + if (constraints & (1 << PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY)) + { + retainCache = true; + } + + /* 10. If don't want VIMS retention in standby, disable it now... */ + if (retainCache == false) + { + + /* 10.1 Get the current VIMS mode */ + do + { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + /* 10.2 If in a cache mode, turn VIMS off */ + if (modeVIMS == VIMS_MODE_ENABLED) + { + + /* 10.3 Now turn off the VIMS */ + VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF); + } + + /* 10.4 Now disable retention */ + PRCMCacheRetentionDisable(); + } + + /* 11. Setup recharge parameters */ + SysCtrlSetRechargeBeforePowerDown(XOSC_IN_HIGH_POWER_MODE); + + /* 12. Make sure all writes have taken effect */ + SysCtrlAonSync(); + + /* 13. Invoke deep sleep to go to STANDBY */ + PRCMDeepSleep(); + + /* 14. If didn't retain VIMS in standby, re-enable retention now */ + if (retainCache == false) + { + + /* 14.1 If previously in a cache mode, restore the mode now */ + if (modeVIMS == VIMS_MODE_ENABLED) + { + VIMSModeSet(VIMS_BASE, modeVIMS); + } + + /* 14.2 Re-enable retention */ + PRCMCacheRetentionEnable(); + } + + /* 15. Start forcing on power to AUX */ + AONWUCAuxWakeupEvent(AONWUC_AUX_WAKEUP); + + /* 16. Start re-powering power domains */ + PRCMPowerDomainOn(poweredDomains); + + /* 17. Restore deep sleep clocks of Crypto and DMA */ + if (Power_getDependencyCount(PowerCC26XX_PERIPH_CRYPTO)) + { + PRCMPeripheralDeepSleepEnable(resourceDB[PowerCC26XX_PERIPH_CRYPTO].driverlibID); + } + if (Power_getDependencyCount(PowerCC26XX_PERIPH_UDMA)) + { + PRCMPeripheralDeepSleepEnable(resourceDB[PowerCC26XX_PERIPH_UDMA].driverlibID); + } + + /* 18. Make sure clock settings take effect */ + PRCMLoadSet(); + + /* 19. Release request for uLDO */ + PRCMMcuUldoConfigure(false); + + /* 20. Set transition state to EXITING_SLEEP */ + PowerCC26XX_module.state = Power_EXITING_SLEEP; + + /* 21. Wait until all power domains are back on */ + while (PRCMPowerDomainsAllOn(poweredDomains) != PRCM_DOMAIN_POWER_ON) {} + + /* 22. Wait for the RTC shadow values to be updated so that + * the early notification callbacks can read out valid RTC values + */ + SysCtrlAonSync(); + + /* + * 23. Signal clients registered for early post-sleep notification; + * this should be used to initialize any timing critical or IO + * dependent hardware + */ + notifyStatus = notify(postEvent); + + /* 24. Disable IO freeze and ensure RTC shadow value is updated */ + AONIOCFreezeDisable(); + SysCtrlAonSync(); + + /* 25. Wait for AUX to power up */ + while (!(AONWUCPowerStatusGet() & AONWUC_AUX_POWER_ON)) {}; + + /* 26. If XOSC_HF was forced off above, initiate switch back */ + if (xosc_hf_active == true) + { + Log_printf(LogModule_Power, + Log_VERBOSE, + "Power_sleep: Forcing XOSC_HF back on"); + + configureXOSCHF(PowerCC26XX_ENABLE); + } + + /* 27. Re-enable interrupts */ + CPUcpsie(); + + /* + * 28. Signal all clients registered for late post-sleep + * notification + */ + lateNotifyStatus = notify(postEventLate); + + /* + * 29. Now clear the transition state before re-enabling + * scheduler + */ + PowerCC26XX_module.state = Power_ACTIVE; + + /* 30. Adjust recharge parameters */ + SysCtrlAdjustRechargeAfterPowerDown(PowerCC26XX_config.vddrRechargeMargin); + + /* 31. Re-enable scheduling */ + PowerCC26XX_schedulerRestore(); + + /* if there was a notification error, set return status */ + if ((notifyStatus != Power_SOK) || (lateNotifyStatus != Power_SOK)) + { + Log_printf(LogModule_Power, + Log_WARNING, + "Power_sleep: Notification error leaving standby. Status = 0x%x and late status = 0x%x", + notifyStatus, + lateNotifyStatus); + + status = Power_EFAIL; + } + } + } + + return (status); +} + +/* + * ======== Power_unregisterNotify ======== + * Unregister for a power notification. + * + */ +void Power_unregisterNotify(Power_NotifyObj *pNotifyObj) +{ + unsigned int key; + + /* remove notify object from its event queue */ + key = HwiP_disable(); + + Log_printf(LogModule_Power, + Log_INFO, + "Power_unregisterNotify: Unregister fxn at address 0x%x with event types 0x%x and clientArg 0x%x", + pNotifyObj->notifyFxn, + pNotifyObj->eventTypes, + pNotifyObj->clientArg); + + /* remove notify object from its event queue */ + List_remove(&PowerCC26XX_module.notifyList, (List_Elem *)pNotifyObj); + + HwiP_restore(key); +} + +/* ****************** CC26XX specific APIs ******************** */ + +/* + * ======== PowerCC26XX_calibrate ======== + * Plug this function into the PowerCC26XX_Config structure + * if calibration is needed. + */ +bool PowerCC26XX_calibrate(unsigned int arg) +{ + bool retVal = false; + ClockP_Params clockParams; + + switch (arg) + { + case PowerCC26XX_SETUP_CALIBRATE: + /* + * If RCOSC calibration is enabled, construct a Clock object for + * delays. Set timeout to '1' Clock tick period for the minimal + * delay. The object will explicitly started by Power module when + * appropriate + */ + ClockP_Params_init(&clockParams); + clockParams.period = 0; + clockParams.startFlag = false; + clockParams.arg = 0; + ClockP_construct(&PowerCC26XX_module.calClockStruct, &PowerCC26XX_RCOSC_clockFunc, 1, &clockParams); + + /* construct the Hwi */ + HwiP_construct(&PowerCC26XX_module.hwiStruct, 44, PowerCC26XX_auxISR, NULL); + + break; + + case PowerCC26XX_INITIATE_CALIBRATE: + retVal = PowerCC26XX_initiateCalibration(); + break; + + case PowerCC26XX_DO_CALIBRATE: + PowerCC26XX_doCalibrate(); + break; + } + + return (retVal); +} + +/* + * ======== PowerCC26XX_doWFI ======== + */ +void PowerCC26XX_doWFI(void) +{ + __asm(" wfi"); +} + +/* + * ======== PowerCC26XX_getClockHandle ======== + */ +ClockP_Handle PowerCC26XX_getClockHandle() +{ + return ((ClockP_Handle)&PowerCC26XX_module.clockObj); +} + +/* + * ======== PowerCC26XX_noCalibrate ======== + * Plug this function into the PowerCC26XX config structure if calibration + * is not needed. + */ +bool PowerCC26XX_noCalibrate(unsigned int arg) +{ + return (0); +} + +/* + * ======== PowerCC26XX_getXoscStartupTime ======== + * Get the estimated crystal oscillator startup time + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs) +{ + return (OSCHF_GetStartupTime(timeUntilWakeupInMs)); +} + +/* + * ======== PowerCC26XX_injectCalibration ======== + * Explicitly trigger RCOSC calibration + */ +bool PowerCC26XX_injectCalibration(void) +{ + if ((*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE)) + { + /* here if AUX SMPH was available, start calibration now ... */ + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + return (true); + } + + return (false); +} + +/* + * ======== PowerCC26XX_isStableXOSC_HF ======== + * Check if XOSC_HF has stabilized. + */ +bool PowerCC26XX_isStableXOSC_HF(void) +{ + bool ready = true; + unsigned int key; + + key = HwiP_disable(); + + /* only query if HF source is ready if there is a pending change */ + if (PowerCC26XX_module.xoscPending) + { + ready = OSCHfSourceReady(); + } + + HwiP_restore(key); + + return (ready); +} + +/* + * ======== PowerCC26XX_switchXOSC_HF ======== + * Switch to enable XOSC_HF. + * May only be called when using the PowerCC26XX_SWITCH_XOSC_HF_MANUALLY + * constraint. + * May only be called after ensuring the XOSC_HF is stable by calling + * PowerCC26XX_isStableXOSC_HF(). + */ +void PowerCC26XX_switchXOSC_HF(void) +{ + /* This function is just a veneer to call the static callback function for + * the XOSC_HF clock. This way, if the switching does fail because a constraint + * stopped it from switching, a clock will be scheduled into the future to try + * again. This could happen if there is an ongoing operation from another bus + * controller that reads from flash such as SPI or AES DMA operations. + */ + switchXOSCHFclockFunc((uintptr_t)NULL); +} + +/* * * * * * * * * * * internal and support functions * * * * * * * * * * */ + +/* + * ======== emptyClockFunc ======== + * Clock function used by power policy to schedule early wakeups. + */ +static void emptyClockFunc(uintptr_t arg) +{} + +/* + * ======== disableLfClkQualifiersEnableClkLoss ======== + * Function used to disable LF clock qualifiers and enable clock loss + */ +static void disableLfClkQualifiersEnableClkLoss() +{ + /* Disable the LF clock qualifiers */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M | DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M, + DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S, + 0x3); + + /* Enable clock loss detection */ + OSCClockLossEventEnable(); +} + +/* + * ======== lfClockReadyCallback ======== + * Clock function callback used to check if the LF clock is ready + */ +static void lfClockReadyCallback(uintptr_t arg) +{ + uint32_t ccfgLfClkSrc; + uint32_t sourceLF; + uint32_t timeout; + + /* query LF clock source */ + sourceLF = OSCClockSourceGet(OSC_SRC_CLK_LF); + + /* is LF source either RCOSC_LF or XOSC_LF yet? */ + if ((sourceLF == OSC_RCOSC_LF) || (sourceLF == OSC_XOSC_LF)) + { + Log_printf(LogModule_Power, + Log_INFO, + "lfClockReadyCallback: LF clock is ready with source = 0x%x", + sourceLF); + + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + + /* now finish by releasing the standby disallow constraint */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + /* is LF source XOSC_HF yet? */ + else if (sourceLF == OSC_XOSC_HF) + { + Log_printf(LogModule_Power, Log_INFO, "lfClockReadyCallback: LF clock is sourced from OSC_XOSC_HF"); + + /* Disable clock qualifiers and enable clock loss */ + disableLfClkQualifiersEnableClkLoss(); + + /* Keep PowerCC26XX_DISALLOW_STANDBY set, not allowed to enter standby + * when LF clock is sourced from from XOSC_HF + */ + } + + /* not yet, LF still derived from RCOSC_HF, restart clock to check back later */ + else + { + Log_printf(LogModule_Power, Log_INFO, "lfClockReadyCallback: LF clock is still derived from RCOSC_HF"); + + /* read the LF clock source from CCFG */ + ccfgLfClkSrc = CCFGRead_SCLK_LF_OPTION(); + + /* determine retry timeout */ + if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_RCOSC_LF) + { + timeout = PowerCC26XX_RETRYWAITRCOSC_LF; + } + else if (ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_LF) + { + timeout = PowerCC26XX_RETRYWAITXOSC_LF; + } + else + { + /* ccfgLfClkSrc == CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF */ + timeout = PowerCC26XX_RETRYWAITXOSC_HF; + } + /* retrigger LF Clock to fire again */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.lfClockObj), (timeout / ClockP_getSystemTickPeriod())); + ClockP_start(ClockP_handle(&PowerCC26XX_module.lfClockObj)); + } +} + +/* + * ======== nopResourceFunc ======== + * special resource handler + */ +static unsigned int nopResourceHandler(unsigned int action) +{ + return (0); +} + +/* + * ======== notify ======== + * Send notifications to registered clients. + * Note: Task scheduling is disabled when this function is called. + */ +static int_fast16_t notify(uint_fast16_t eventType) +{ + int_fast16_t notifyStatus; + Power_NotifyFxn notifyFxn; + uintptr_t clientArg; + List_Elem *elem; + + /* if queue is empty, return immediately */ + if (!List_empty(&PowerCC26XX_module.notifyList)) + { + /* point to first client notify object */ + elem = List_head(&PowerCC26XX_module.notifyList); + + /* walk the queue and notify each registered client of the event */ + do + { + if (((Power_NotifyObj *)elem)->eventTypes & eventType) + { + /* pull params from notify object */ + notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; + clientArg = ((Power_NotifyObj *)elem)->clientArg; + + /* call the client's notification function */ + Log_printf(LogModule_Power, + Log_VERBOSE, + "notify: Invoking notification fxn at address 0x%x with event type 0x%x and clientArg 0x%x", + notifyFxn, + eventType, + clientArg); + + notifyStatus = (int_fast16_t)(*(Power_NotifyFxn)notifyFxn)(eventType, 0, clientArg); + + /* if client declared error stop all further notifications */ + if (notifyStatus != Power_NOTIFYDONE) + { + Log_printf(LogModule_Power, + Log_WARNING, + "notify: Notification fxn reported error, fxn at address 0x%x with event type 0x%x and notifyStatus 0x%x", + notifyFxn, + eventType, + notifyStatus); + + return (Power_EFAIL); + } + } + + /* get next element in the notification queue */ + elem = List_next(elem); + + } while (elem != NULL); + } + + return (Power_SOK); +} + +/* + * ======== configureRFCoreClocks ======== + * Special dependency function for controlling RF core clocks. + * This function does nothing, but is kept for legacy reasons. + * All functionality has been integrated into the RF driver. + */ +static unsigned int configureRFCoreClocks(unsigned int action) +{ + return (0); +} + +/* + * ======== switchXOSCHFclockFunc ======== + * Clock function used for delayed switching to XOSC_HF. + */ +static void switchXOSCHFclockFunc(uintptr_t arg0) +{ + bool readyToCal; + uint32_t timeout; + unsigned int key; + + key = HwiP_disable(); + + /* if pending switch has already been made, just send out notifications */ + if (PowerCC26XX_module.xoscPending == false) + { + Log_printf(LogModule_Power, Log_INFO, "switchXOSCHFclockFunc: Switch done. Initiate RCOSC calibration"); + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE); + + /* notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) + { + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + } + } + + /* else, if HF ready to switch and we are allowed to, do it now ... */ + else if (!(Power_getConstraintMask() & (1 << PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING)) && OSCHfSourceReady()) + { + Log_printf(LogModule_Power, Log_INFO, "switchXOSCHFclockFunc: Switch to XOSC."); + + OSCHF_AttemptToSwitchToXosc(); + + PowerCC26XX_module.xoscPending = false; + + /* initiate RCOSC calibration */ + readyToCal = (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_INITIATE_CALIBRATE); + + /* now notify clients that were waiting for a switch notification */ + notify(PowerCC26XX_XOSC_HF_SWITCHED); + + /* if ready to start first cal measurment, do it now */ + if (readyToCal == true) + { + (*(PowerCC26XX_config.calibrateFxn))(PowerCC26XX_DO_CALIBRATE); + } + } + + /* else, wait some more, then see if can switch ... */ + else + { + /* calculate wait timeout in units of ticks */ + timeout = PowerCC26XX_RETRYWAITXOSC_HF / ClockP_getSystemTickPeriod(); + if (timeout == 0) + { + timeout = 1; /* wait at least 1 tick */ + } + + /* re-start Clock object with retry timeout */ + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.xoscClockObj), timeout); + ClockP_start(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + + Log_printf(LogModule_Power, + Log_INFO, + "switchXOSCHFclockFunc: Set timeout for switching. Timeout = 0x%x", + timeout); + } + + HwiP_restore(key); +} + +/* + * ======== configureXOSCHF ======== + */ +static unsigned int configureXOSCHF(unsigned int action) +{ + uint32_t timeout; + + if (action == PowerCC26XX_ENABLE && OSCClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) + { + OSCHF_TurnOnXosc(); + + PowerCC26XX_module.xoscPending = true; + + /* Unless it is disallowed, estimate the required stabilisation + * time and start a clock. + * When the clock times out, the callback will try and switch to + * the XOSC_HF. If the XOSC_HF is not ready yet, the callback + * will start a new clock to try again. + */ + if (!(Power_getConstraintMask() & (1 << PowerCC26XX_SWITCH_XOSC_HF_MANUALLY))) + { + /* calculate wait timeout in units of ticks */ + timeout = PowerCC26XX_INITIALWAITXOSC_HF / ClockP_getSystemTickPeriod(); + if (timeout == 0) + { + timeout = 1; /* wait at least 1 tick */ + } + + /* start Clock object with initial timeout */ + ClockP_stop(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + ClockP_setTimeout(ClockP_handle(&PowerCC26XX_module.xoscClockObj), timeout); + ClockP_start(ClockP_handle(&PowerCC26XX_module.xoscClockObj)); + } + } + + /* when release XOSC_HF, auto switch to RCOSC_HF */ + else + { + OSCHF_SwitchToRcOscTurnOffXosc(); + } + return (0); +} diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.h b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.h new file mode 100644 index 00000000..27bc3b86 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX.h @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file PowerCC26XX.h + * + * @brief Power manager interface for CC26XX/CC13XX + * + * The Power header file should be included in an application by including the + * top level header file as follows: + * @code + * #include + * @endcode + * + * Refer to @ref Power.h for a complete description of APIs. + * + * ## Implementation # + * This header file defines the power resources, constraints, events, sleep + * states and transition latencies for CC26XX/CC13XX. + * + * ============================================================================ + */ + +#ifndef ti_drivers_power_PowerCC26XX_ +#define ti_drivers_power_PowerCC26XX_ + +#include +#include +#include + +#include + +/* Note: Device specific Power include files are included in the bottom of this file. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* \cond */ +typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ +/* \endcond */ + +/*! The latency to reserve for resume from STANDBY (usec). */ +#define PowerCC26XX_RESUMETIMESTANDBY 750 + +/*! The total latency to reserve for entry to and exit from STANDBY (usec). */ +#define PowerCC26XX_TOTALTIMESTANDBY 1000 + +/*! The initial delay when waking from STANDBY (usec). */ +#define PowerCC26XX_WAKEDELAYSTANDBY 240 + +/*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ +#define PowerCC26XX_INITIALWAITRCOSC_LF 1000 + +/*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ +#define PowerCC26XX_RETRYWAITRCOSC_LF 1000 + +/*! The initial wait time (usec) before checking if XOSC_HF is stable. */ +#define PowerCC26XX_INITIALWAITXOSC_HF 50 + +/*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ +#define PowerCC26XX_RETRYWAITXOSC_HF 50 + +/*! The initial wait time (usec) before checking if XOSC_LF is stable. */ +#define PowerCC26XX_INITIALWAITXOSC_LF 10000 + +/*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ +#define PowerCC26XX_RETRYWAITXOSC_LF 5000 + +/* + * Resource IDs + */ +/*! Resource ID: General Purpose Timer 0 */ +#define PowerCC26XX_PERIPH_GPT0 0 + +/*! Resource ID: General Purpose Timer 1 */ +#define PowerCC26XX_PERIPH_GPT1 1 + +/*! Resource ID: General Purpose Timer 2 */ +#define PowerCC26XX_PERIPH_GPT2 2 + +/*! Resource ID: General Purpose Timer 3 */ +#define PowerCC26XX_PERIPH_GPT3 3 + +/*! Resource ID: Synchronous Serial Interface 0 */ +#define PowerCC26XX_PERIPH_SSI0 4 +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /*! Resource ID: SPI0 */ + #define PowerCC26XX_PERIPH_SPI0 PowerCC26XX_PERIPH_SSI0 +#endif + +/*! Resource ID: UART 0 */ +#define PowerCC26XX_PERIPH_UART0 5 + +/*! Resource ID: I2C 0 */ +#define PowerCC26XX_PERIPH_I2C0 6 + +/*! Resource ID: True Random Number Generator */ +#define PowerCC26XX_PERIPH_TRNG 7 + +/*! Resource ID: General Purpose I/Os */ +#define PowerCC26XX_PERIPH_GPIO 8 + +/*! Resource ID: uDMA Controller */ +#define PowerCC26XX_PERIPH_UDMA 9 + +/*! Resource ID: AES Security Module */ +#define PowerCC26XX_PERIPH_CRYPTO 10 + +/*! Resource ID: I2S */ +#define PowerCC26XX_PERIPH_I2S 11 + +/*! Resource ID: RF Core Module */ +#define PowerCC26XX_PERIPH_RFCORE 12 + +/*! Resource ID: High Frequency Crystal Oscillator */ +#define PowerCC26XX_XOSC_HF 13 + +/*! Resource ID: Peripheral Power Domain */ +#define PowerCC26XX_DOMAIN_PERIPH 14 + +/*! Resource ID: Serial Power Domain */ +#define PowerCC26XX_DOMAIN_SERIAL 15 + +/*! Resource ID: RF Core Power Domain */ +#define PowerCC26XX_DOMAIN_RFCORE 16 + +/*! Resource ID: System Bus Power Domain */ +#define PowerCC26XX_DOMAIN_SYSBUS 17 + +/* The PKA and UART1 peripherals are not available on CC13X1 and CC26X1 devices */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + /*! Resource ID: PKA Module */ + #define PowerCC26XX_PERIPH_PKA 18 + + /*! Resource ID: UART1 */ + #define PowerCC26XX_PERIPH_UART1 19 + + /*! Resource ID: Synchronous Serial Interface 1 */ + #define PowerCC26XX_PERIPH_SSI1 20 + #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /*! Resource ID: SPI1 */ + #define PowerCC26XX_PERIPH_SPI1 PowerCC26XX_PERIPH_SSI1 + #endif +#endif + +/* The peripherals below are only available on CC13X4 and CC26X4 devices */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + /*! Resource ID: UART2 */ + #define PowerCC26XX_PERIPH_UART2 21 + + /*! Resource ID: UART3 */ + #define PowerCC26XX_PERIPH_UART3 22 + + /*! Resource ID: SPI2 */ + #define PowerCC26XX_PERIPH_SPI2 23 + /*! Included for compatibilty. Please use \ref PowerCC26XX_PERIPH_SPI2 */ + #define PowerCC26XX_PERIPH_SSI2 PowerCC26XX_PERIPH_SPI2 + + /*! Resource ID: SPI3 */ + #define PowerCC26XX_PERIPH_SPI3 24 + /*! Included for compatibility. Please use \ref PowerCC26XX_PERIPH_SPI3 */ + #define PowerCC26XX_PERIPH_SSI3 PowerCC26XX_PERIPH_SPI3 + + /*! Resource ID: I2C1 */ + #define PowerCC26XX_PERIPH_I2C1 25 +#endif + +/* \cond */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0) + #define PowerCC26XX_NUMRESOURCES 19 /* Number of resources in database */ +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + #define PowerCC26XX_NUMRESOURCES 19 /* Number of resources in database */ +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + #define PowerCC26XX_NUMRESOURCES 21 /* Number of resources in database */ +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #define PowerCC26XX_NUMRESOURCES 26 /* Number of resources in database */ +#endif +/* \endcond */ + +/* \cond */ +/* Resource record bitmasks */ +#define PowerCC26XX_PERIPH 0x80 /* resource is a peripheral */ +#define PowerCC26XX_SPECIAL 0x40 /* resource requires special handler */ +#define PowerCC26XX_DOMAIN 0x00 /* resource is a domain */ +#define PowerCC26XX_PARENTMASK 0x3F /* parent resource mask */ +#define PowerCC26XX_NOPARENT 0x3F /* if resource has no parent */ +/* \endcond */ + +/*! The STANDBY sleep state */ +#define PowerCC26XX_STANDBY 0x1 +/* \cond */ +/* Internal flags for enabling/disabling resources */ +#define PowerCC26XX_ENABLE 1 +#define PowerCC26XX_DISABLE 0 +/* \endcond */ + +/* Constraints */ +/*! Constraint: VIMS RAM must be retained while in STANDBY */ +#define PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY 0 + +/*! Constraint: Disallow a transition to the SHUTDOWN state */ +#define PowerCC26XX_DISALLOW_SHUTDOWN 1 + +/*! Constraint: Disallow a transition to the STANDBY sleep state */ +#define PowerCC26XX_DISALLOW_STANDBY 2 + +/*! Constraint: Disallow a transition to the IDLE sleep state */ +#define PowerCC26XX_DISALLOW_IDLE 3 + +/*! Constraint: Flash memory needs to enabled during IDLE */ +#define PowerCC26XX_NEED_FLASH_IN_IDLE 4 + +/*! Constraint: Prevent power driver from starting an RTOS clock and + * automatically switching to the XOSC_HF when it is ready. The power + * driver will turn on the XOSC_HF and return control to the application. + * The application must poll the status of the XOSC_HF and make sure that it + * is stable before manually switching to it. + * If the constraint is released before the application has switched to the + * XOSC_HF, the application is still responsible for switching to the + * XOSC_HF. + * Failing to do so may cause an undefined internal state in the power + * driver. + */ +#define PowerCC26XX_SWITCH_XOSC_HF_MANUALLY 5 + +/*! Constraint: Prevent power driver from switching to XOSC_HF when the crystal is + * ready. The RTOS clock will be rescheduled to try again in the future. + * This is a workaround to prevent the flash from being accessed by a bus controller + * other than the CPU while switching to XOSC_HF. This would cause a bus stall. + * This functionality is only implemented on CC26X0, CC26X0R2, and CC13X0 as the + * bug was fixed in hardware on later devices. + */ +#define PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING 6 + +/* \cond */ +#define PowerCC26XX_NUMCONSTRAINTS 7 /* Number of constraints supported */ +/* \endcond */ + +/* \cond */ +/* Deprecated constraint names */ +#define PowerCC26XX_SD_DISALLOW PowerCC26XX_DISALLOW_SHUTDOWN +#define PowerCC26XX_SB_DISALLOW PowerCC26XX_DISALLOW_STANDBY +#define PowerCC26XX_IDLE_PD_DISALLOW PowerCC26XX_DISALLOW_IDLE +#define PowerCC26XX_XOSC_HF_SWITCHING_DISALLOW PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING +#define PowerCC26XX_SB_VIMS_CACHE_RETAIN PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY +/* \endcond */ + +/* + * Events + * + * Each event must be a power of two and must be sequential + * without any gaps. + */ +/*! Power event: The device is entering the STANDBY sleep state */ +#define PowerCC26XX_ENTERING_STANDBY 0x1 + +/*! Power event: The device is entering the SHUTDOWN state */ +#define PowerCC26XX_ENTERING_SHUTDOWN 0x2 + +/*! Power event: The device is waking up from the STANDBY sleep state */ +#define PowerCC26XX_AWAKE_STANDBY 0x4 + +/*! Power event: The device is waking up from STANDBY (this event is sent later during wakeup, after interrupts are + * re-enabled) */ +#define PowerCC26XX_AWAKE_STANDBY_LATE 0x8 + +/*! Power event: The high frequency (HF) clock source has been switched to XOSC_HF */ +#define PowerCC26XX_XOSC_HF_SWITCHED 0x10 + +/*! Power event: The low frequency (LF) clock source has been switched from + * RCOSC_HF derived to the source configured in CCFG. + * + * Only the XOSC_LF requires a significant amount of time to turn on and switch. + * The other LF clock sources will often have switched and trigger a + * notification before the OS schedules the first task after enabling + * interrupts. It may be necessary to register the notification in main, before + * interrupts are enabled to guarantee the event will not be missed by the + * application. + */ +#define PowerCC26XX_SCLK_LF_SWITCHED 0x20 + +/*! \warning Note that this power event is only supported by the CC2640R2 device! + * + * The JTAG subsystem on the CC26xx devices is automatically enabled after receiving + * 8 pulses on the TCK pin. This will cause the device to draw more power in all + * power modes (Active, Idle, Standby, Shutdown). + * The ::PowerCC26XX_JTAG_PD_TURNED_ON power event will + * let you know when this has happened outside of a debug session due to noise on the pin. + * This allows the application to do a reset of the device when it's convenient in order + * disable the JTAG subsystem and conserve power. + * + * In order to turn off the JTAG_PD the application should subscribe to this event. + * In the callback function the application can call Power_shutdown() and + * this will force a reset of the device. + * Alternatively the the callback function can post another event so that the application can + * reset the device when it's more convenient to do so. + * + * When Power_shutdown() is called when the JTAG subsystem is on, + * the device will reset and branch to the flash image again, + * only now with the JTAG_PD turned off, thus the excess power is gone. + * The wakeup source as read through the SysCtrlResetSourceGet() will in this case + * return RSTSRC_WAKEUP_FROM_SHUTDOWN. + * + * The power driver will, each time before entering standby, check to see if the + * JTAG_PD has been turned on after boot. If so, it will notify all subscribers to the + * ::PowerCC26XX_JTAG_PD_TURNED_ON event. + * If the JTAG_PD was turned on during boot, which is the case when + * using the debugger, the notification will NOT be sent even if the event is registered. + * This is because when actively developing code with an IDE and emulator, the user typically + * wants to be able to debug their code through standby without the device resetting. + * + * Summary of when the ::PowerCC26XX_JTAG_PD_TURNED_ON notification function will be called. + * + * | JTAG_PD state | Notification function registered | Notification function called | + * |----------------------|----------------------------------|------------------------ + * | Off | Don't care | No + * | Turned on during boot| Don't care | No + * | Turned on after boot | No | No + * | Turned on after boot | Yes | Yes + * + * \warning If the ::PowerCC26XX_JTAG_PD_TURNED_ON event is registered, and the notification + * callback function calls Power_shutdown() it will not be possible to attach + * an emulator to a running target. This is becasue the device will reset as soon as the + * emulator turns on the JTAG_PD as part of the connect sequence. + * + * Code snippet on how to register the notification and the callback function: + * @code + * void jtagPdTurnedOnCallbackFxn() + * { + * // Optionally save any critical application information + * // gracefullyShutdownApplication(); + * // Call shutdown, this will reset device, and the application will reboot with JTAG_PD off. + * Power_shutdown(NULL, NULL); + * // Power_shutdown(...) should never return, device will reset. + * } + * + * void taskFxn(UArg a0, UArg a1) + * { + * ... + * // Register "JTAG power domain turned on" notification function + * // Everytime the device is about to enter standby, the power driver will check + * // to see if the JTAG_PD has been turned on after boot. If so, the notification + * // function will be called before entering standby... + * Power_registerNotify(&jtagPdTurnedOnNotifyObj, PowerCC26XX_JTAG_PD_TURNED_ON, (Fxn)jtagPdTurnedOnCallbackFxn, + * NULL); + * ... + * } + * @endcode + */ +#define PowerCC26XX_JTAG_PD_TURNED_ON 0x40 + +/* \cond */ +#define PowerCC26XX_NUMEVENTS 6 /* Number of events supported */ +/* \endcond */ + +/* \cond */ +/* + * Calibration stages + */ +#define PowerCC26XX_SETUP_CALIBRATE 1 +#define PowerCC26XX_INITIATE_CALIBRATE 2 +#define PowerCC26XX_DO_CALIBRATE 3 +/* \endcond */ + +/* \cond */ +/*! @brief Power resource database record format */ +typedef struct +{ + uint8_t flags; /* resource type | first parent */ + uint16_t driverlibID; /* corresponding driverlib ID for this resource */ +} PowerCC26XX_ResourceRecord; +/* \endcond */ + +/*! @brief Global configuration structure */ +typedef struct +{ + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26XX_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26XX_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26XX_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26XX_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int arg); + /*! + * @brief Time in system ticks that specifies the maximum duration the device + * may spend in standby. + * + * When the power driver tries to put the device into standby and determines + * the next wakeup should usually be further into the future than + * maxStandbyDuration system ticks, the power driver will schedule a wakeup + * maxStandbyDuration into the future. When the device wakes up after + * being in standby for maxStandbyDuration ticks, the power driver will + * repeat this process and go back into standby if the state of the system + * allows it. + * + * Inserting such periodic wakeups can be used to automatically calibrate + * the RCOSC with a maximum period between calibrations or to force the + * recalculation of the initial VDDR recharge period. This assumes that + * the constraint to prohibit standby is not set and that periods of + * inactivity are long enough for the power driver to put the device + * into standby. + * + * The value 0 is invalid. When PowerCC26XX_Config.enableMaxStandbyDuration is + * set to false, any value (including 0) is ignored and the feature is + * disabled. + * This feature should not be used to disallow entering standby; + * the PowerCC26XX_DISALLOW_STANDBY constraint should be used for + * this purpose. + */ + uint32_t maxStandbyDuration; + /*! + * @brief Margin in SCLK_LF periods subtracted from previous longest + * VDDR recharge period. + * + * As the device comes out of standby, it updated its previous initial + * VDDR recharge period to be closer to the longest recharge period + * experienced during the time spent in standby before waking up. + * + * vddrRechargeMargin is subtracted from the longest VDDR recharge + * period in SysCtrlAdjustRechargeAfterPowerDown to ensure there is + * some margin between the new initial and converged VDDR recharge + * period. The converged recharge period at a certain temperature + * is board and device dependent. + * + * The default value of 0 disables this feature. + */ + uint16_t vddrRechargeMargin; + /*! + * @brief Boolean that enables limiting the duration spent in standby + * + * If false, the power driver will put the device into standby as + * appropriate without duration restrictions. + * + * If true, the the power driver will force a wakeup every + * PowerCC26XX_Config.maxStandbyDuration system ticks before reevaluating + * the state of the system. + * + * This is set to false by default. + */ + bool enableMaxStandbyDuration; + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; +} PowerCC26XX_Config; + +/*! + * @brief PowerCC26XX_ModuleState + * + * Power manager state structure. The application must not access any members + * of this structure! + */ +typedef struct +{ + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct xoscClockObj; /*!< Clock object for XOSC_HF switching */ + ClockP_Struct lfClockObj; /*!< Clock object for LF clock checking */ + ClockP_Struct calClockStruct; /*!< Clock object for RCOSC calibration */ + HwiP_Struct hwiStruct; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t hwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint8_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ +#if defined(DeviceFamily_CC26X0R2) + bool emulatorAttached; /*!< Was an emulator detected during boot? */ +#endif + uint8_t constraintCounts[PowerCC26XX_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26XX_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int arg); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ +} PowerCC26XX_ModuleState; + +/*! + * @brief The RC Oscillator (RCOSC) calibration function + * + * The function to be used for performing RCOSC calibation. This is the + * default calibration function, and is specified via the calibrateFxn + * pointer in the PowerCC26XX_Config structure. + * + * @param arg used internally + * + * @return used internally + */ +bool PowerCC26XX_calibrate(unsigned int arg); + +/*! + * @brief The Wait for interrupt (WFI) policy + * + * This is a lightweight Power Policy which simply invokes CPU wait for + * interrupt. + * + * This policy can be selected statically via the policyFxn pointer in the + * PowerCC26XX_Config structure, or dynamically at runtime, via + * Power_setPolicy(). + */ +void PowerCC26XX_doWFI(void); + +/*! + * @brief Get the handle of the Clock object used for scheduling device + * wakeups + * + * During initialization, the Power Manager creates a Clock object that a + * Power Policy can use to schedule device wakeups. This function can + * be called by a policy function to get the handle of this pre-allocated + * Clock object. + * + * @return The handle of the Clock object + */ +ClockP_Handle PowerCC26XX_getClockHandle(void); + +/*! + * @brief Get the estimated HF crystal oscillator (XOSC_HF) startup delay, + * for a given delay from now, until startup is initiated + * + * @param timeUntilWakeupInMs The estimated time until the next wakeup + * event, in units of milliseconds + * + * @return The estimated HF crystal oscillator startup latency, in + * units of microseconds. + */ +uint32_t PowerCC26XX_getXoscStartupTime(uint32_t timeUntilWakeupInMs); + +/*! + * @brief Explicitly trigger RC oscillator calibration + * + * When enabled, RCOSC calibration is normally triggered upon each device + * wakeup from STANDBY. To trigger more frequent calibration, an application + * can explicitly call this function, to initiate an immediate calibration + * cycle. + * + * @pre This function may only be called if the XOSC_HF running and stable. + * Practically, this means that a dependency was set earlier on the + * XOSC_HF and it has already been switched to earlier. + * + * @return true if calibration was actually initiated otherwise false + */ +bool PowerCC26XX_injectCalibration(void); + +/*! + * @brief Function to specify when RCOSC calibration is to be disabled + * + * This function should be specified as the 'calibrateFxn' in the + * PowerCC26XX_Config structure when RCOSC calibration is to be disabled. + * + * Note that the reason a function pointer is used here (versus a simple + * Boolean) is so that references to internal calibration subroutines can be + * removed, to eliminate pulling the calibration code into the application + * image; this enables a significant reduction in memory footprint when + * calibration is disabled. + * + * @param arg used internally + * + * @return used internally + */ +bool PowerCC26XX_noCalibrate(unsigned int arg); + +/*! + * @brief Check if the XOSC_HF is stable and ready to be switched to + * + * @pre Set PowerCC26XX_SWITCH_XOSC_HF_MANUALLY in the early standby + * wakeup notification. + * + * This function should be called when using the + * PowerCC26XX_SWITCH_XOSC_HF_MANUALLY power constraint to ensure that + * the XOSC_HF is stable before switching to it. + * + * \sa PowerCC26XX_switchXOSC_HF() + */ +bool PowerCC26XX_isStableXOSC_HF(void); + +/*! + * @brief Switch the HF clock source to XOSC_HF + * + * @pre PowerCC26XX_switchXOSC_HF() returns true. + * + * This function should only be called when using the + * PowerCC26XX_SWITCH_XOSC_HF_MANUALLY power constraint after ensuring + * the XOSC_HF is stable. + * If the driver cannot switch to the XOSC_HF despite the crystal being + * stable, a clock will be scheduled in the future and the callback will + * try to switch again. + * + * \sa PowerCC26XX_isStableXOSC_HF() + */ +void PowerCC26XX_switchXOSC_HF(void); + +/*! + * @brief The STANDBY Power Policy + * + * This is an agressive Power Policy, which considers active constraints, + * sleep state transition latencies, and time until the next scheduled + * work, and automatically transitions the device into the deepest sleep state + * possible. + * + * The first goal is to enter STANDBY; if that is not appropriate + * given current conditions (e.g., the sleep transition latency is greater + * greater than the time until the next scheduled Clock event), then + * the secondary goal is the IDLE state; if that is disallowed (e.g., if + * the PowerCC26XX_DISALLOW_IDLE constraint is declared), then the policy + * will fallback and simply invoke WFI, to clock gate the CPU until the next + * interrupt. + * + * In order for this policy to run, it must be selected as the Power + * Policy (either by being specified as the 'policyFxn' in the + * PowerCC26XX_Config structure, or specified at runtime with + * Power_setPolicy()), and the Power Policy must be enabled (either via + * 'enablePolicy' in the PowerCC26XX_Config structure, or via a call to + * Power_enablePolicy() at runtime). + */ +void PowerCC26XX_standbyPolicy(void); + +void PowerCC26XX_schedulerDisable(void); +void PowerCC26XX_schedulerRestore(void); + +#ifdef __cplusplus +} +#endif + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#endif + +#endif /* POWER_CC26XX_ */ diff --git a/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c new file mode 100644 index 00000000..8b66542f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/power/PowerCC26XX_calibrateRCOSC.c @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== PowerCC26XX_calibrateRCOSC.c ======== + */ + +#include + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_aux_evctl.h) +#include DeviceFamily_constructPath(inc/hw_aux_smph.h) +#include DeviceFamily_constructPath(inc/hw_aux_wuc.h) +#include DeviceFamily_constructPath(inc/hw_aux_tdc.h) +#include DeviceFamily_constructPath(inc/hw_ddi_0_osc.h) +#include DeviceFamily_constructPath(inc/hw_ddi.h) +#include DeviceFamily_constructPath(inc/hw_ccfg.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/ddi.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/aux_wuc.h) + +#define AUX_TDC_SEMAPHORE_NUMBER 1 /* semaphore 1 protects TDC */ +#define NUM_RCOSC_LF_PERIODS_TO_MEASURE 32 /* x RCOSC_LF periods vs XOSC_HF */ +#define NUM_RCOSC_HF_PERIODS_TO_MEASURE 1 /* x RCOSC_HF periods vs XOSC_HF */ +#define ACLK_REF_SRC_RCOSC_HF 0 /* Use RCOSC_HF for ACLK REF */ +#define ACLK_REF_SRC_RCOSC_LF 2 /* Use RCOSC_LF for ACLK REF */ +#define SCLK_LF_OPTION_RCOSC_LF 3 /* defined in cc26_ccfg.xls */ +#define RCOSC_HF_LOW_THRESHOLD_TDC_VALUE \ + 1535 /* If TDC value is within threshold range, no need for another TDC measurement */ +#define RCOSC_HF_PERFECT_TDC_VALUE 1536 /* RCOSC_HF runs at perfect 48 MHz when ending up with this TDC value */ +#define RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE \ + 1537 /* If TDC value is within threshold range, no need for another TDC measurement */ + +#define DDI_0_OSC_O_CTL1_LOCAL 0x00000004 /* offset */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M 0x007C0000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S 18 /* shift */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M 0x00020000 /* mask */ +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S 17 /* shift */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M 0x00000C00 /* offset */ +#define DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S 10 /* shift */ + +/* AUX ISR states */ +#define WAIT_SMPH 0 /* just took SMPH, start RCOSC_LF */ +#define CAL_RCOSC_LF 1 /* just finished RCOSC_LF, start first RCOSC_HF */ +#define CAL_RCOSC_HF1 2 /* just finished 1st RCOSC_HF, start 2nd */ +#define CAL_RCOSC_HF2 3 /* just finished 2nd RCOSC_HF, decide best */ + +/* calibration steps */ +#define STEP_TDC_INIT_1 1 +#define STEP_TDC_INIT_2 2 +#define STEP_CAL_LF_1 3 +#define STEP_CAL_LF_2 4 +#define STEP_CAL_LF_3 5 +#define STEP_CAL_HF1_1 6 +#define STEP_CAL_HF1_2 7 +#define STEP_CAL_HF1_3 8 +#define STEP_CAL_HF2_1 9 +#define STEP_CAL_HF2_2 10 +#define STEP_CLEANUP_1 11 +#define STEP_CLEANUP_2 12 + +/* macros */ +#define Scale_rndInf(x) ((3 * (x) + (((x) < 0) ? -2 : 2)) / 4) + +#define INSTRUMENT 0 + +#if INSTRUMENT +volatile unsigned int gotSEM = 0; +volatile unsigned int calLFi = 0; +volatile unsigned int calHF1i = 0; +volatile unsigned int calHF2i = 0; +volatile bool doneCal = false; +unsigned int tdcResult_LF = 0; +unsigned int tdcResult_HF1 = 0; +unsigned int tdcResult_HF2 = 0; +unsigned int numISRs = 0; +unsigned int calClocks = 0; +#endif + +/* Forward declarations */ +static bool getTdcSemaphore(); +static void updateSubSecInc(uint32_t tdcResult); +static void calibrateRcoscHf1(int32_t tdcResult); +static void calibrateRcoscHf2(int32_t tdcResult); +void PowerCC26XX_doCalibrate(void); + +/* Externs */ +extern PowerCC26XX_ModuleState PowerCC26XX_module; +extern const PowerCC26XX_Config PowerCC26XX_config; + +/* + * ======== PowerCC26XX_initiateCalibration ======== + * Initiate calibration of RCOSC_LF and RCOSCHF + */ +bool PowerCC26XX_initiateCalibration() +{ + unsigned int hwiKey; + bool busy = false; + bool status; + bool gotSem; + + if ((PowerCC26XX_module.calLF == false) && (PowerCC26XX_config.calibrateRCOSC_HF == false)) + { + return (false); + } + + /* make sure calibration is not already in progress */ + hwiKey = HwiP_disable(); + + if (PowerCC26XX_module.busyCal == false) + { + PowerCC26XX_module.busyCal = true; + } + else + { + busy = true; + } + + HwiP_restore(hwiKey); + + if (busy == true) + { + return (false); + } + +#if INSTRUMENT + gotSEM = 0; + calLFi = 0; + calHF1i = 0; + calHF2i = 0; + doneCal = false; +#endif + + /* set contraint to prohibit standby during calibration sequence */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set dependency to keep XOSC_HF active during calibration sequence */ + Power_setDependency(PowerCC26XX_XOSC_HF); + + /* initiate acquisition of semaphore protecting TDC */ + gotSem = getTdcSemaphore(); + + /* if didn't acquire semaphore, must wait for autotake ISR */ + if (gotSem == false) + { + PowerCC26XX_module.hwiState = WAIT_SMPH; + status = false; /* false: don't do anything else until acquire SMPH */ + } + + /* else, semaphore acquired, OK to proceed with first measurement */ + else + { +#if INSTRUMENT + gotSEM = 1; +#endif + status = true; /* true: OK to start first measurement */ + } + + return (status); +} + +/* + * ======== PowerCC26XX_auxISR ======== + * ISR for the AUX combo interrupt event. Implements Hwi state machine to + * step through the RCOSC calibration steps. + */ +void PowerCC26XX_auxISR(uintptr_t arg) +{ + uint32_t tdcResult; + +#if INSTRUMENT + numISRs++; +#endif + + /* + * disable all events that are part of AUX_COMBINED_INTERRUPT. + * This interrupt is reserved for use during RCOSC calibration. + * Other AUX perihperals that want to generate interrupts to CM3 + * must use dedicated interrupt lines or go through AON combined. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* ****** state = WAIT_SMPH: arrive here if just took the SMPH ****** */ + if (PowerCC26XX_module.hwiState == WAIT_SMPH) + { +#if INSTRUMENT + gotSEM = 1; +#endif + } + + /* **** state = CAL_RCOSC_LF: here when just finished LF counting **** */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_LF) + { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_LF = tdcResult; +#endif + /* update the RTC SUBSECINC register based on LF measurement result */ + updateSubSecInc(tdcResult); +#if INSTRUMENT + calLFi = 1; +#endif + /* if doing HF calibration initiate it now */ + if (PowerCC26XX_config.calibrateRCOSC_HF) + { + PowerCC26XX_module.calStep = STEP_CAL_LF_3; /* next: trigger LF */ + } + + /* else, start cleanup */ + else + { + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + } + + /* ****** state = CAL_RCOSC_HF1: here when just finished 1st RCOSC_HF */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_HF1) + { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_HF1 = tdcResult; + calHF1i = 1; +#endif + + /* use first HF measurement to setup new trim values */ + calibrateRcoscHf1(tdcResult); + + /* if HF setting perfect, nothing more to do, calibration is done */ + if ((tdcResult >= RCOSC_HF_LOW_THRESHOLD_TDC_VALUE) && (tdcResult <= RCOSC_HF_HIGH_THRESHOLD_TDC_VALUE)) + { + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + + /* else, tweak trims, initiate another HF measurement */ + else + { + + PowerCC26XX_module.calStep = STEP_CAL_HF1_3; /* next: HF meas. #2 */ + } + } + + /* ****** state = just finished second RCOSC_HF measurement ****** */ + else if (PowerCC26XX_module.hwiState == CAL_RCOSC_HF2) + { + + tdcResult = HWREG(AUX_TDC_BASE + AUX_TDC_O_RESULT); + +#if INSTRUMENT + tdcResult_HF2 = tdcResult; +#endif + /* look for improvement on #2, else revert to previous trim values */ + calibrateRcoscHf2(tdcResult); + + PowerCC26XX_module.calStep = STEP_CLEANUP_1; /* next: cleanup */ + } + + /* do the next calibration step... */ + PowerCC26XX_doCalibrate(); +} + +/* + * ======== PowerCC26XX_doCalibrate ======== + */ +void PowerCC26XX_doCalibrate(void) +{ + switch (PowerCC26XX_module.calStep) + { + + case STEP_TDC_INIT_1: + + /* turn on clock to TDC module */ + AUXWUCClockEnable(AUX_WUC_TDCIF_CLOCK); + + /* set saturation config to 2^24 */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_SATCFG) = AUX_TDC_SATCFG_LIMIT_R24; + + /* set start and stop trigger sources and polarity */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGSRC) = (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF | AUX_TDC_TRIGSRC_STOP_POL_HIGH) | + (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF | AUX_TDC_TRIGSRC_START_POL_HIGH); + + /* set TDC_SRC clock to be XOSC_HF/2 = 24 MHz */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S, + 2); + + /* read back to ensure no race condition between OSC_DIG and AUX_WUC */ + DDI16BitfieldRead(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S); + + /* set AUX_WUC:TDCCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = AUX_WUC_TDCCLKCTL_REQ; + + /* set next state */ + PowerCC26XX_module.calStep = STEP_TDC_INIT_2; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_TDC_INIT_2: + + /* Enable trig count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; + + /* if LF calibration enabled start LF measurement */ + if (PowerCC26XX_module.calLF) + { + + /* clear UPD_REQ, new sub-second increment is NOT available */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL) = 0; + + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_LF_1; + } + + /* else, start first HF measurement */ + else + { + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_HF1_1; + } + + /* abort TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; + + /* clear AUX_WUC:REFCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* if not ready, start Clock object to delay while wait for ACK */ + if (HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & AUX_WUC_REFCLKCTL_ACK) + { + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + } + + /* else, if ready now, fall thru to next step ... */ + + case STEP_CAL_LF_1: + case STEP_CAL_HF1_1: + case STEP_CAL_HF2_1: + + if (PowerCC26XX_module.calStep == STEP_CAL_LF_1) + { + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_LF); + + /* set next Swi state */ + PowerCC26XX_module.calStep = STEP_CAL_LF_2; + } + else + { + + /* set the ACLK reference clock */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M, + DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S, + ACLK_REF_SRC_RCOSC_HF); + + /* set next Swi state */ + if (PowerCC26XX_module.calStep == STEP_CAL_HF1_1) + { + PowerCC26XX_module.calStep = STEP_CAL_HF1_2; + } + else + { + PowerCC26XX_module.calStep = STEP_CAL_HF2_2; + } + } + + /* set AUX_WUC:REFCLKCTL.REQ */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = AUX_WUC_REFCLKCTL_REQ; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CAL_LF_2: + case STEP_CAL_HF1_2: + case STEP_CAL_HF2_2: + + if (PowerCC26XX_module.calStep == STEP_CAL_LF_2) + { + + /* Set number of periods of ACLK to count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_LF_PERIODS_TO_MEASURE; + + /* set next Hwi state before triggering TDC */ + PowerCC26XX_module.hwiState = CAL_RCOSC_LF; + } + else + { + + /* Set number of periods of ACLK to count */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_TRIGCNTLOAD) = NUM_RCOSC_HF_PERIODS_TO_MEASURE; + + /* set next Hwi state before triggering TDC */ + if (PowerCC26XX_module.calStep == STEP_CAL_HF2_2) + { + PowerCC26XX_module.hwiState = CAL_RCOSC_HF2; + } + else + { + PowerCC26XX_module.hwiState = CAL_RCOSC_HF1; + } + } + + /* Reset/clear result of TDC */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_CLR_RESULT; + + /* Clear possible pending interrupt source */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE; + + /* Enable TDC done interrupt as part of AUX_COMBINED interrupt */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE; + + /* Run TDC (start synchronously) */ + HWREG(AUX_TDC_BASE + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_RUN_SYNC_START; + + break; + + case STEP_CAL_LF_3: + case STEP_CAL_HF1_3: + + /* set next Swi state */ + if (PowerCC26XX_module.calStep == STEP_CAL_LF_3) + { + PowerCC26XX_module.calStep = STEP_CAL_HF1_1; + } + else + { + PowerCC26XX_module.calStep = STEP_CAL_HF2_1; + } + + /* clear AUX_WUC:REFCLKCTL.REQ... */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CLEANUP_1: + + /* release the TDC clock request */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) = 0; + + /* release the TDC reference clock request */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) = 0; + + /* set next state */ + PowerCC26XX_module.calStep = STEP_CLEANUP_2; + + /* start Clock object to delay while wait for ACK */ + ClockP_start(ClockP_handle(&PowerCC26XX_module.calClockStruct)); + + break; + + case STEP_CLEANUP_2: + + /* + * Disable all interrupts as part of AUX_COMBINED interrupt + * Once we release semaphore, the sensor controller is allowed + * to use the TDC. When it does, we must ensure that this + * does not cause any unexpected interrupts to the CM3. + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = 0; + + /* release AUX semaphore */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1) = 1; + + /* release the power down constraints and XOSC_HF dependency */ + Power_releaseDependency(PowerCC26XX_XOSC_HF); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* set next state */ + PowerCC26XX_module.calStep = STEP_TDC_INIT_1; + +#if INSTRUMENT + doneCal = true; + calHF2i = 1; +#endif + PowerCC26XX_module.busyCal = false; + break; + + default: + for (;;) {} + } +} + +/* + * ======== PowerCC26XX_RCOSC_clockFunc ======== + */ +void PowerCC26XX_RCOSC_clockFunc(uintptr_t arg) +{ +#if INSTRUMENT + calClocks++; +#endif + + switch (PowerCC26XX_module.calStep) + { + + case STEP_TDC_INIT_2: + /* finish wait for AUX_WUC:TDCCLKCTL.ACK to be set ... */ + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) & AUX_WUC_TDCCLKCTL_ACK)) {} + break; + + case STEP_CAL_LF_1: + case STEP_CAL_HF1_1: + case STEP_CAL_HF2_1: + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & AUX_WUC_REFCLKCTL_ACK) {} + break; + + case STEP_CAL_LF_2: + case STEP_CAL_HF1_2: + case STEP_CAL_HF2_2: + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be set ... */ + while (!(HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & AUX_WUC_REFCLKCTL_ACK)) {} + break; + + case STEP_CLEANUP_2: + /* finish wait for AUX_WUC:TDCCLKCTL.ACK to be cleared ... */ + while ((HWREG(AUX_WUC_BASE + AUX_WUC_O_TDCCLKCTL) & AUX_WUC_TDCCLKCTL_ACK)) {} + /* finish wait for AUX_WUC:REFCLKCTL.ACK to be cleared ... */ + while (HWREG(AUX_WUC_BASE + AUX_WUC_O_REFCLKCTL) & AUX_WUC_REFCLKCTL_ACK) {} + break; + + default: + for (;;) {} + } + + PowerCC26XX_doCalibrate(); +} + +/* + * ======== getTdcSemaphore ======== + * Get TDC semaphore (number 1) + */ +static bool getTdcSemaphore() +{ + unsigned int own; + + /* try to acquire SMPH */ + own = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH1); + + /* if acquired SMPH: done */ + if (own != 0) + { + return (true); + } + + /* clear the interrupt source, can only be cleared when we don't have semaphore */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_EVTOMCUFLAGSCLR) = AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE; + + /* + * else, did not acquire the semaphore, enable SMPH_AUTOTAKE_DONE event + * (don't OR, write entire register, no other interrupts can be enabled!) + */ + HWREG(AUX_EVCTL_BASE + AUX_EVCTL_O_COMBEVTOMCUMASK) = AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE; + + /* start AUTOTAKE of semaphore for TDC access */ + HWREG(AUX_SMPH_BASE + AUX_SMPH_O_AUTOTAKE) = AUX_TDC_SEMAPHORE_NUMBER; + + return (false); +} + +/* + * ======== updateSubSecInc ======== + * Update the SUBSECINC register based on measured RCOSC_LF frequency + */ +static void updateSubSecInc(uint32_t tdcResult) +{ + int32_t newSubSecInc; + uint32_t oldSubSecInc; + uint32_t subSecInc; + uint32_t ccfgModeConfReg; + int32_t hposcOffset; + int32_t hposcOffsetInv; + + /* + * Calculate the new SUBSECINC + * Here's the formula: AON_RTC:SUBSECINC = (45813 * NR) / 256 + * Based on measuring 32 LF clock periods + */ + newSubSecInc = (45813 * tdcResult) / 256; + + /* TODO: Replace with ccfgread driverlib call */ + ccfgModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); + /* Compensate HPOSC drift if HPOSC is in use */ + if (((ccfgModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M) >> CCFG_MODE_CONF_XOSC_FREQ_S) == 1) + { + /* Get the HPOSC relative offset at this temperature */ + hposcOffset = OSC_HPOSCRelativeFrequencyOffsetGet(AONBatMonTemperatureGetDegC()); + /* Convert to RF core format */ + hposcOffsetInv = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(hposcOffset); + /* Adjust SUBSECINC */ + newSubSecInc += (((newSubSecInc >> 4) * (hposcOffsetInv >> 3)) >> 15); + } + + /* Apply filter, but not for first calibration */ + if (PowerCC26XX_module.firstLF) + { + /* Don't apply filter first time, to converge faster */ + subSecInc = newSubSecInc; + /* No longer first measurement */ + PowerCC26XX_module.firstLF = false; + } + else + { + /* Read old SUBSECINC value */ + oldSubSecInc = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC) & 0x00FFFFFF; + /* Apply filter, 0.5 times old value, 0.5 times new value */ + subSecInc = (oldSubSecInc * 1 + newSubSecInc * 1) / 2; + } + + /* Update SUBSECINC values */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC0) = subSecInc; + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINC1) = subSecInc >> 16; + + /* update to use new values */ + HWREG(AUX_WUC_BASE + AUX_WUC_O_RTCSUBSECINCCTL) = AUX_WUC_RTCSUBSECINCCTL_UPD_REQ; +} + +/* + * ======== PowerCC26XX_calibrateRcoscHf1 ======== + * Calibrate RCOSC_HF agains XOSC_HF: compute and setup new trims + */ +static void calibrateRcoscHf1(int32_t tdcResult) +{ + /* *** STEP 1: Find RCOSC_HF-XOSC_HF frequency offset with current trim settings */ + /* Read in current trim settings */ + PowerCC26XX_module.nCtrimCurr = (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RCOSCHFCTL) & + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M) >> + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S; + + PowerCC26XX_module.nCtrimFractCurr = (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL1_LOCAL) & + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M) >> + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S; + + PowerCC26XX_module.nRtrimCurr = (DDI32RegRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ATESTCTL) & + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M) >> + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S; + + /* + * Find RCOSC_HF-XOSC_HF frequency offset with current trim settings + * Positive value => RCOSC_HF runs slow, CTRIM(FRACT) should be increased + * Negative value => RCOSC_HF runs fast, CTRIM(FRACT) should be decreased + * Resolution: 31.25 kHz; CTRIMFRACT resolution ~30 kHz + */ + PowerCC26XX_module.nDeltaFreqCurr = (int32_t)tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + + /* *** STEP 2: Attempt to calculate more optimal settings */ + if (PowerCC26XX_module.nDeltaFreqCurr == 0) + { + /* If perfect, don't perform second measurement and keep current settings */ + PowerCC26XX_module.bRefine = false; + return; + } + if (PowerCC26XX_module.bRefine) + { + /* + * Trying to find better match across CTRIM/RTRIM. Due to mismatches the + * first try might not have been more optimal than the current setting. + * Continue refining, starting from stored values + */ + } + else + { + /* Start from current values */ + PowerCC26XX_module.nCtrimFractNew = PowerCC26XX_module.nCtrimFractCurr; + PowerCC26XX_module.nCtrimNew = PowerCC26XX_module.nCtrimCurr; + PowerCC26XX_module.nRtrimNew = PowerCC26XX_module.nRtrimCurr; + PowerCC26XX_module.nDeltaFreqNew = PowerCC26XX_module.nDeltaFreqCurr; + } + + /* + * Calculate change to CTRIMFRACT with safe assumptions of gain, + * apply delta to current CTRIMFRACT and convert to valid CTRIM/CTRIMFRACT + */ + PowerCC26XX_module.nCtrimFractNew = PowerCC26XX_module.nCtrimFractNew + + Scale_rndInf(PowerCC26XX_module.nDeltaFreqNew); + PowerCC26XX_module.nCtrimNew = PowerCC26XX_module.nCtrimCurr; + + /* One step of CTRIM is about 500 kHz, so limit to one CTRIM step */ + if (PowerCC26XX_module.nCtrimFractNew < 1) + { + if (PowerCC26XX_module.nRtrimNew == 3) + { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26XX_module.nCtrimFractNew = Math_MAX(1, PowerCC26XX_module.nCtrimFractNew + 21); + PowerCC26XX_module.nRtrimNew = 0; + } + else + { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26XX_module.nCtrimFractNew = Math_MAX(1, PowerCC26XX_module.nCtrimFractNew + 32 - 21); + PowerCC26XX_module.nCtrimNew = Math_MAX(0, PowerCC26XX_module.nCtrimNew - 1); + PowerCC26XX_module.nRtrimNew = 3; + } + } + else if (PowerCC26XX_module.nCtrimFractNew > 30) + { + if (PowerCC26XX_module.nRtrimNew == 0) + { + /* We try the slow RTRIM in this CTRIM first */ + PowerCC26XX_module.nCtrimFractNew = Math_MIN(30, PowerCC26XX_module.nCtrimFractNew - 21); + PowerCC26XX_module.nRtrimNew = 3; + } + else + { + /* Step down one CTRIM and use fast RTRIM */ + PowerCC26XX_module.nCtrimFractNew = Math_MIN(30, PowerCC26XX_module.nCtrimFractNew - 32 + 21); + PowerCC26XX_module.nCtrimNew = Math_MIN(0x3F, PowerCC26XX_module.nCtrimNew + 1); + PowerCC26XX_module.nRtrimNew = 0; + } + } + else + { + /* We're within sweet spot of current CTRIM => no change */ + } + + /* Find RCOSC_HF vs XOSC_HF frequency offset with new trim settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26XX_module.nCtrimNew); + + /* Enable RCOSCHFCTRIMFRACT_EN */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_LOCAL_S, + 1); + + /* Modify CTRIM_FRACT */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26XX_module.nCtrimFractNew); + + /* Modify RTRIM */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26XX_module.nRtrimNew); +} + +/* + * ======== Power_calibrateRcoscHf2 ======== + * Calibrate RCOSC_HF agains XOSC_HF: determine better result, set new trims + */ +static void calibrateRcoscHf2(int32_t tdcResult) +{ + + PowerCC26XX_module.nDeltaFreqNew = (int32_t)tdcResult - RCOSC_HF_PERFECT_TDC_VALUE; + /* Calculate new delta freq */ + + /* *** STEP 4: Determine whether the new settings are better or worse */ + if (Math_ABS(PowerCC26XX_module.nDeltaFreqNew) <= Math_ABS(PowerCC26XX_module.nDeltaFreqCurr)) + { + /* New settings are better or same -> make current by keeping in registers */ + PowerCC26XX_module.bRefine = false; + } + else + { + /* First measurement was better than second, restore current settings */ + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_RCOSCHFCTL, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M, + DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S, + PowerCC26XX_module.nCtrimCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_CTL1_LOCAL, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_M, + DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_LOCAL_S, + PowerCC26XX_module.nCtrimFractCurr); + + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, + DDI_0_OSC_O_ATESTCTL, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_M, + DDI_0_OSC_ATESTCTL_SET_RCOSC_HF_FINE_RESISTOR_LOCAL_S, + PowerCC26XX_module.nRtrimCurr); + + /* Enter a refinement mode where we keep searching for better matches */ + PowerCC26XX_module.bRefine = true; + } +} diff --git a/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.c b/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.c new file mode 100644 index 00000000..1498bbd3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.c @@ -0,0 +1,464 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file PWMTimerCC26XX.c + * @brief CC26XX/CC13XX implementation of ti/drivers/PWM.h + * + * # Overview # + * CC26XX/CC13XX PWM driver using the built-in GPTimer. + * + * # Note # + * The driver requires the GPTimer bit GPT.TnMR.TnPLO to be set. + * Using this, the PWM output will be always low when load=match and always + * high when match>load. Setting match > load is used for 100% duty cycle + * + ******************************************************************************* + */ + +#include +#include + +#include +#include + +#include "ti/drivers/PWM.h" +#include "ti/drivers/pwm/PWMTimerCC26XX.h" +#include "ti/drivers/timer/GPTimerCC26XX.h" + +/* PWMTimerCC26XX defines */ +#define PWM_COUNT_MAX \ + 0xFFFFFE /* GPTimer has maximum 24 bits incl prescaler. \ + Max count is set to (2^24 - 2) to allow for \ + a glitch free 100% duty cycle at max period count.*/ + +/*! + * @brief If the PWM period is lower than this value, setDutyAndPeriod + * will briefly disable the PWM channel to set the new values. + * + * This is to prevent the case where the period, but not the duty, is + * applied before the timeout and the next cycle is in an undetermined state. + */ +#define PWM_PERIOD_FOR_GLITCH_PROTECTION 0xF + +/* PWMTimerCC26XX functions */ +void PWMTimerCC26XX_close(PWM_Handle handle); +int_fast16_t PWMTimerCC26XX_control(PWM_Handle handle, uint_fast16_t cmd, void *arg); +void PWMTimerCC26XX_init(PWM_Handle handle); +PWM_Handle PWMTimerCC26XX_open(PWM_Handle handle, PWM_Params *params); +int_fast16_t PWMTimerCC26XX_setDuty(PWM_Handle handle, uint32_t dutyValue); +int_fast16_t PWMTimerCC26XX_setPeriod(PWM_Handle handle, uint32_t periodValue); +int_fast16_t PWMTimerCC26XX_setDutyAndPeriod(PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue); +void PWMTimerCC26XX_start(PWM_Handle handle); +void PWMTimerCC26XX_stop(PWM_Handle handle); + +/* PWMTimerCC26XX internal functions */ +static uint32_t PWMTimerCC26XX_getperiodCounts(PWM_Period_Units periodUnit, uint32_t periodValue); +static int32_t PWMTimerCC26XX_getdutyCounts(uint32_t periodCounts, PWM_Duty_Units dutyUnit, uint32_t dutyValue); + +/* PWM function table for PWMTimerCC26XX implementation */ +const PWM_FxnTable PWMTimerCC26XX_fxnTable = { + PWMTimerCC26XX_close, + PWMTimerCC26XX_control, + PWMTimerCC26XX_init, + PWMTimerCC26XX_open, + PWMTimerCC26XX_setDuty, + PWMTimerCC26XX_setPeriod, + PWMTimerCC26XX_setDutyAndPeriod, + PWMTimerCC26XX_start, + PWMTimerCC26XX_stop, +}; + +/*! + * @brief PWM CC26XX initialization + * + * This is a dummy function since driver implementation assumes + * the handle->object->isOpen flag is set to 0 at boot + * + * @pre Calling context: Hwi, Swi, Task, Main + * + * @param handle A SPI_Handle + * + */ +void PWMTimerCC26XX_init(PWM_Handle handle) +{} + +/* Open the specific PWM peripheral with the settings given in params. + * Will return a PWM handle if successfull, NULL if failed. + * PWM will output configured idle level when opened. + * Function sets a dependency on the underlying timer and muxes the PWM pin + */ +PWM_Handle PWMTimerCC26XX_open(PWM_Handle handle, PWM_Params *params) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + /* Check if PWM already open */ + uint32_t key = HwiP_disable(); + if (object->isOpen) + { + HwiP_restore(key); + DebugP_log1("PWM_open(%x): Unit already in use.", (uintptr_t)handle); + return NULL; + } + object->isOpen = 1; + HwiP_restore(key); + + /* Open timer resource */ + GPTimerCC26XX_Params timerParams; + GPTimerCC26XX_Params_init(&timerParams); + timerParams.width = GPT_CONFIG_16BIT; + timerParams.mode = GPT_MODE_PWM; + timerParams.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + timerParams.matchTiming = GPTimerCC26XX_SET_MATCH_ON_TIMEOUT; + GPTimerCC26XX_Handle hTimer = GPTimerCC26XX_open(hwAttrs->gpTimerUnit, &timerParams); + + /* Fail if cannot open timer */ + if (hTimer == NULL) + { + DebugP_log2("PWM_open(%x): Timer unit (%d) already in use.", (uintptr_t)handle, hwAttrs->gpTimerUnit); + object->isOpen = false; + return NULL; + } + + uint32_t idleLevel = GPIO_CFG_OUT_HIGH; + if (params->idleLevel == PWM_IDLE_LOW) + { + idleLevel = GPIO_CFG_OUT_LOW; + } + + /* Set config for PWM pin. */ + GPIO_setConfig(hwAttrs->pwmPin, GPIO_CFG_OUTPUT | idleLevel | GPIO_CFG_DRVSTR_HIGH_INTERNAL); + + /* Store configuration to object */ + object->periodUnit = params->periodUnits; + object->periodValue = params->periodValue; + object->dutyUnit = params->dutyUnits; + object->dutyValue = params->dutyValue; + object->idleLevel = params->idleLevel; + object->hTimer = hTimer; + + /* Configure PWM period*/ + uint32_t period = object->periodValue; + + /* This will also set the duty cycle */ + if (PWMTimerCC26XX_setPeriod(handle, period) != PWM_STATUS_SUCCESS) + { + DebugP_log1("PWM_open(%x): Failed setting period", (uintptr_t)handle); + GPIO_resetConfig(hwAttrs->pwmPin); + GPTimerCC26XX_close(hTimer); + object->isOpen = false; + return NULL; + } + + DebugP_log1("PWM_open(%x): Opened with great success!", (uintptr_t)handle); + return handle; +} + +/* PWMTimerCC26XX_setPeriod - + Sets / update PWM period. Unit must already be defined in object. + Also updates duty cycle. + */ +int_fast16_t PWMTimerCC26XX_setPeriod(PWM_Handle handle, uint32_t periodValue) +{ + PWMTimerCC26XX_Object *object = handle->object; + /* Copy current duty value and store new period */ + uint32_t dutyValue = object->dutyValue; + uint32_t newperiodCounts = PWMTimerCC26XX_getperiodCounts(object->periodUnit, periodValue); + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(newperiodCounts, object->dutyUnit, dutyValue); + + /* Fail if period is out of range */ + if ((newperiodCounts > PWM_COUNT_MAX) || (newperiodCounts == 0)) + { + DebugP_log2("PWM(%x): Period (%d) is out of range", (uintptr_t)handle, periodValue); + return PWM_STATUS_INVALID_PERIOD; + } + + /* Compare to new period and fail if invalid */ + if (newperiodCounts < (newdutyCounts - 1) || (newdutyCounts < 0)) + { + DebugP_log2("PWM(%x): Period is shorter than duty (%d)", (uintptr_t)handle, periodValue); + return PWM_STATUS_INVALID_PERIOD; + } + + /* Store new period and update timer */ + object->periodValue = periodValue; + object->periodCounts = newperiodCounts; + GPTimerCC26XX_setLoadValue(object->hTimer, newperiodCounts); + + /* Store new duty cycle and update timer */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + DebugP_log1("PWM_setPeriod(%x): Period set with great success!", (uintptr_t)handle); + return PWM_STATUS_SUCCESS; +} + +/* PWMTimerCC26XX_setDuty - + Sets / update PWM duty. Unit must already be defined in object. + Period must already be configured in object before calling this API. + */ +int_fast16_t PWMTimerCC26XX_setDuty(PWM_Handle handle, uint32_t dutyValue) +{ + PWMTimerCC26XX_Object *object = handle->object; + /* Copy current duty unit and store new period */ + PWM_Duty_Units dutyUnit = object->dutyUnit; + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(object->periodCounts, dutyUnit, dutyValue); + + /* Fail if duty cycle count is out of range. */ + if (newdutyCounts > PWM_COUNT_MAX) + { + DebugP_log2("PWM(%x): Duty (%d) is out of range", (uintptr_t)handle, dutyValue); + return PWM_STATUS_INVALID_DUTY; + } + + /* Error checking: + * Unit PWM_DUTY_FRACTION will always be within range + * Unit PWM_DUTY_US with value 0 will always be correct(set by getdutyCounts) + * Unit PWM_DUTY_US value != 0 needs error checking + * Unit PWM_DUTY_COUNTS needs error checking + */ + if (((newdutyCounts > (object->periodCounts + 1)) && + ((dutyUnit == PWM_DUTY_US) || (dutyUnit == PWM_DUTY_COUNTS))) || + (newdutyCounts < 0)) + { + DebugP_log2("PWM(%x): Duty (%d) is larger than period", (uintptr_t)handle, dutyValue); + return PWM_STATUS_INVALID_DUTY; + } + + /* Store new duty cycle and update timer */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + DebugP_log1("PWM_setDuty(%x): Duty set with great success!", (uintptr_t)handle); + return PWM_STATUS_SUCCESS; +} + +/* ======== PWMTimerCC26XX_setDutyAndPeriod ======== + Sets / update PWM duty and period. Unit must already be defined in object. + */ +int_fast16_t PWMTimerCC26XX_setDutyAndPeriod(PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue) +{ + uint32_t key; + bool stopped = false; + PWMTimerCC26XX_Object *object = handle->object; + + uint32_t oldPeriod = object->periodValue; + uint32_t newperiodCounts = PWMTimerCC26XX_getperiodCounts(object->periodUnit, periodValue); + int32_t newdutyCounts = PWMTimerCC26XX_getdutyCounts(newperiodCounts, object->dutyUnit, dutyValue); + + /* Fail if period is out of range or incompatible with new duty */ + if ((newperiodCounts > PWM_COUNT_MAX) || (newperiodCounts == 0) || (newperiodCounts < (newdutyCounts - 1))) + { + return PWM_STATUS_INVALID_PERIOD; + } + + /* Fail if duty cycle count is out of range. */ + if ((newdutyCounts > PWM_COUNT_MAX) || (newdutyCounts < 0)) + { + return PWM_STATUS_INVALID_DUTY; + } + + /* Store new period */ + object->periodValue = periodValue; + object->periodCounts = newperiodCounts; + + /* Store new duty cycle */ + object->dutyValue = dutyValue; + object->dutyCounts = newdutyCounts; + + // Disable interrupts for register update + key = HwiP_disable(); + + if (object->isRunning && (oldPeriod <= PWM_PERIOD_FOR_GLITCH_PROTECTION || + GPTimerCC26XX_getValue(object->hTimer) <= PWM_PERIOD_FOR_GLITCH_PROTECTION)) + { + stopped = true; + GPTimerCC26XX_stop(object->hTimer); + } + + /* Update timer */ + GPTimerCC26XX_setLoadValue(object->hTimer, newperiodCounts); + GPTimerCC26XX_setMatchValue(object->hTimer, newdutyCounts); + + if (stopped) + { + GPTimerCC26XX_start(object->hTimer); + } + + // Restore interrupts + HwiP_restore(key); + return PWM_STATUS_SUCCESS; +} + +/* Return period in timer counts */ +static uint32_t PWMTimerCC26XX_getperiodCounts(PWM_Period_Units periodUnit, uint32_t periodValue) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t periodCounts; + + switch (periodUnit) + { + case PWM_PERIOD_US: + periodCounts = ((uint64_t)freq.lo * (uint64_t)periodValue / 1000000) - 1; + break; + case PWM_PERIOD_HZ: + periodCounts = (freq.lo / periodValue) - 1; + break; + case PWM_PERIOD_COUNTS: + /* Fall through */ + default: + periodCounts = periodValue; + break; + } + return periodCounts; +} + +/* Return duty cycle in timer counts */ +static int32_t PWMTimerCC26XX_getdutyCounts(uint32_t periodCounts, PWM_Duty_Units dutyUnit, uint32_t dutyValue) +{ + ClockP_FreqHz freq; + ClockP_getCpuFreq(&freq); + + uint32_t dutyCounts; + + /* Corner case, 0% duty cycle. Set timer count to period count */ + if (dutyValue == 0) + { + dutyCounts = periodCounts; + } + else + { + /* Invert the duty cycle count to get the expected PWM signal output. */ + switch (dutyUnit) + { + case PWM_DUTY_US: + dutyCounts = periodCounts - (((uint64_t)freq.lo * (uint64_t)dutyValue / 1000000) - 1); + break; + case PWM_DUTY_FRACTION: + dutyCounts = periodCounts - ((uint64_t)dutyValue * (uint64_t)periodCounts / PWM_DUTY_FRACTION_MAX); + break; + case PWM_DUTY_COUNTS: + /* Fall through */ + default: + dutyCounts = periodCounts - dutyValue; + break; + } + + /* Corner case: If 100% duty cycle, the resulting dutyCount will be 0, set new dutyCounts to periodCounts + 1 to + * create a glitch free signal. */ + if (dutyCounts == 0) + { + dutyCounts = periodCounts + 1; + } + } + return dutyCounts; +} + +/* Stop PWM output for given PWM peripheral. PWM pin will be routed + to the GPIO module to provide Idle level and timer is stopped + */ +void PWMTimerCC26XX_stop(PWM_Handle handle) +{ + uint32_t pinConfig; + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + object->isRunning = 0; + + GPTimerCC26XX_stop(object->hTimer); + + /* Route PWM pin to GPIO module */ + GPIO_getConfig(hwAttrs->pwmPin, &pinConfig); + GPIO_setConfigAndMux(hwAttrs->pwmPin, pinConfig, GPIO_MUX_GPIO); +} + +/* Start PWM output for given PWM peripheral. + PWM pin will be routed to the Timer module and timer is started + */ +void PWMTimerCC26XX_start(PWM_Handle handle) +{ + uint32_t pinConfig; + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + object->isRunning = 1; + + /* Route PWM pin to timer output */ + GPIO_getConfig(hwAttrs->pwmPin, &pinConfig); + GPIO_setConfigAndMux(hwAttrs->pwmPin, pinConfig, GPTimerCC26XX_getPinMux(object->hTimer)); + + GPTimerCC26XX_start(object->hTimer); +} + +/* Close the specific PWM peripheral. A running PWM must be stopped first. + PWM output will revert to output value if any is defined. + */ +void PWMTimerCC26XX_close(PWM_Handle handle) +{ + PWMTimerCC26XX_HwAttrs const *hwAttrs = handle->hwAttrs; + PWMTimerCC26XX_Object *object = handle->object; + + /* Restore PWM pin to GPIO module with default configuration */ + GPIO_resetConfig(hwAttrs->pwmPin); + + /* Close and delete timer handle */ + GPTimerCC26XX_close(object->hTimer); + object->hTimer = NULL; + + /* Clear isOpen flag */ + object->isOpen = 0; +} + +/* Driver specific control options. PWM peripheral must be opened before + using this API */ +int_fast16_t PWMTimerCC26XX_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) +{ + PWMTimerCC26XX_Object *object = handle->object; + int stat = PWM_STATUS_SUCCESS; + + switch (cmd) + { + case PWMTimerCC26XX_CMD_DEBUG_STALL: + GPTimerCC26XX_configureDebugStall(object->hTimer, *(GPTimerCC26XX_DebugMode *)arg); + break; + default: + stat = PWM_STATUS_UNDEFINEDCMD; + break; + } + return stat; +} diff --git a/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.h b/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.h new file mode 100644 index 00000000..78fd391c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/pwm/PWMTimerCC26XX.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file PWMTimerCC26XX.h + * @brief PWM driver implementation for CC26XX/CC13XX + * + * # Overview # + * The general PWM API should be used in application code, i.e. PWM_open() + * should be used instead of PWMTimerCC26XX_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * + * # General Behavior # + * Before using PWM on CC26XX: + * - The Timer HW is configured and system dependencies (for example IOs, + * power, etc.) are set by calling PWM_open(). + * + * # Error handling # + * If unsupported arguments are provided to an API returning an error code, the + * PWM configuration will *not* be updated and PWM will stay in the mode it + * was already configured to. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The PWMTimerCC26XX.h driver is not explicitly setting a power constraint when the + * PWM is running to prevent standby as this is assumed to be done in the + * underlying GPTimer driver. + * The following statements are valid: + * - After PWM_open(): The device is still allowed to enter Standby. When the + * device is active the underlying GPTimer peripheral will + * be enabled and clocked. + * - After PWM_start(): The device can only go to Idle power mode since the + * high-frequency clock is needed for PWM operation: + * - After PWM_stop(): Conditions are equal as for after PWM_open + * - After PWM_close(): The underlying GPTimer is turned off and the device + * is allowed to go to standby. + * + * # Accuracy # + * The PWM output period and duty cycle are limited by the underlying timer. + * In PWM mode the timer is effectively 24 bits which results in a minimum + * frequency of 48MHz / (2^24-1) = 2.86Hz (349.525ms) + * The driver will round off the configured duty and period to a value limited + * by the timer resolution and the application is responsible for selecting + * duty and period that works with the underlying timer if high accuracy is + * needed. + * + * The effect of this is most visible when using high output frequencies as the + * available duty cycle resolution is reduced correspondingly. For a 24MHz PWM + * only a 0%/50%/100% duty is available as the timer uses only counts 0 and 1. + * Similarly for a 12MHz period the duty cycle will be limited to a 12.5% + * resolution. + * + * @note The PWM signals are generated using the high-frequency clock as + * a source. The internal RC oscillator is the source of the high frequency + * clock, but may not be accurate enough for certain applications. If very + * high-accuracy outputs are needed, the application should request using + * the external HF crystal: + * @code + * #include + * #include + * Power_setDependency(PowerCC26XX_XOSC_HF); + * @endcode + * + * # Limitations # + * - The PWM output can currently not be synchronized with other PWM outputs + * - The PWM driver does not support updating duty and period using DMA. + * - Changes to the timer period are applied immediately, which can cause + * pulses to be too long or short unless period changes are applied close + * to a timeout. Does not apply to duty cycle, which is applied on timeout. + * # PWM usage # + * + * ## Basic PWM output ## + * The below example will output a 8MHz PWM signal with 50% duty cycle. + * @code + * PWM_Handle pwmHandle; + * PWM_Params params; + * + * PWM_Params_init(¶ms); + * params.idleLevel = PWM_IDLE_LOW; + * params.periodUnits = PWM_PERIOD_HZ; + * params.periodValue = 8e6; + * params.dutyUnits = PWM_DUTY_FRACTION; + * params.dutyValue = PWM_DUTY_FRACTION_MAX / 2; + * + * pwmHandle = PWM_open(CONFIG_PWM0, ¶ms); + * if(pwmHandle == NULL) { + * Log_error0("Failed to open PWM"); + * Task_exit(); + * } + * PWM_start(pwmHandle); + * @endcode + * + * + ******************************************************************************* + */ +#ifndef ti_drivers_pwm__PWMTimerCC26XX_include +#define ti_drivers_pwm__PWMTimerCC26XX_include + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name PWMTimerCC26XX specific control commands and arguments + * @{ + */ + +/*! Timer debug stall mode (stop PWM output debugger halts CPU) + When enabled, PWM output will be HIGH when CPU is halted + */ +#define PWMTimerCC26XX_CMD_DEBUG_STALL PWM_CMD_RESERVED + 0 /*!< @hideinitializer */ +/*! + * @name Arguments for PWMTimerCC26XX_CMD_DEBUG_STALL + * @{ + */ +#define CMD_ARG_DEBUG_STALL_OFF (uint32_t) GPTimerCC26XX_DEBUG_STALL_OFF /*!< @hideinitializer */ +#define CMD_ARG_DEBUG_STALL_ON (uint32_t) GPTimerCC26XX_DEBUG_STALL_ON /*!< @hideinitializer */ +/* @} */ + +/* @} */ + +/* PWM function table pointer */ +extern const PWM_FxnTable PWMTimerCC26XX_fxnTable; + +/*! + * @brief PWMTimer26XX Hardware attributes + * + * These fields are used by the driver to set up underlying GPIO and GPTimer + * driver statically. + */ +typedef struct PWMTimerCC26XX_HwAttrs +{ + uint8_t pwmPin; /*!< Pin to output PWM signal on */ + uint8_t gpTimerUnit; /*!< GPTimer unit index (0A, 0B, 1A..) */ +} PWMTimerCC26XX_HwAttrs; + +/*! + * @brief PWMTimer26XX Object + * + * These fields are used by the driver to store and modify PWM configuration + * during run-time. + * The application must not edit any member variables of this structure. + * Appplications should also not access member variables of this structure + * as backwards compatibility is not guaranteed. + */ +typedef struct PWMTimerCC26XX_Object +{ + bool isOpen; /*!< open flag used to check if PWM is opened */ + bool isRunning; /*!< running flag, set if the output is active */ + PWM_Period_Units periodUnit; /*!< Current period unit */ + uint32_t periodValue; /*!< Current period value in unit */ + uint32_t periodCounts; /*!< Current period in raw timer counts */ + PWM_Duty_Units dutyUnit; /*!< Current duty cycle unit */ + uint32_t dutyValue; /*!< Current duty cycle value in unit */ + uint32_t dutyCounts; /*!< Current duty in raw timer counts */ + PWM_IdleLevel idleLevel; /*!< PWM idle level when stopped / not started */ + GPTimerCC26XX_Handle hTimer; /*!< Handle to underlying GPTimer peripheral */ +} PWMTimerCC26XX_Object; + +#ifdef __cplusplus +} +#endif +#endif /* ti_driver_pwm_PWMTimerCC26XX_include */ diff --git a/simplelink_lpf2/source/ti/drivers/rf/RF.h b/simplelink_lpf2/source/ti/drivers/rf/RF.h new file mode 100644 index 00000000..535d3df1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/rf/RF.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** +@file RF.h +@brief Common Radio Frequency (RF) Core Driver. + +To use the RF driver, ensure that the correct driver library for your device +is linked in and include this header file as follows: + +@code +#include +@endcode + + ****************************************************************************** + */ + +#ifndef ti_drivers_rf__include +#define ti_drivers_rf__include + +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + #include +#else +#error "An incompatible device is defined in the project. \ + To build with this driver, change the DeviceFamily token definition." +#endif + +#endif /* ti_drivers_rf__include */ diff --git a/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2.h b/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2.h new file mode 100644 index 00000000..5811c7cc --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2.h @@ -0,0 +1,2667 @@ +/* + * Copyright (c) 2016-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** +@file RFCC26X2.h +@brief Radio Frequency (RF) Core Driver for the CC13X2 and CC26X2 device + family. + +To use the RF driver, ensure that the correct driver library for your device +is linked in and include the top-level header file as follows: + +@code +#include +@endcode + +
+@anchor rf_overview +Overview +======== + +The RF driver provides access to the radio core on the CC13x2/CC26x2 device +family. It offers a high-level interface for command execution and to the +radio timer (RAT). The RF driver ensures the lowest possible power consumption +by providing automatic power management that is fully transparent for the +application. + +@note This document describes the features and usage of the RF driver API. For a +detailed explanation of the RF core, please refer to the +Technical +Reference Manual or the +Proprietary +RF User Guide. + +Key features are: + +@li @ref rf_command_execution "Synchronous execution of direct and immediate radio commands" +@li @ref rf_command_execution "Synchronous and asynchronous execution of radio operation commands" +@li Various @ref rf_event_callbacks "event hooks" to interact with RF commands and the RF driver +@li Automatic @ref rf_power_management "power management" +@li @ref rf_scheduling "Preemptive scheduler for RF operations" of different RF driver instances +@li Convenient @ref rf_rat "Access to the radio timer" (RAT) +@li @ref rf_tx_power "Programming the TX power level" +@li @ref rf_temperature_compensation "Temperature Compensation" + +@anchor rf_setup_and_configuration +Setup and configuration +======================= + +The RF driver can be configured at 4 different places: + +1. In the build configuration by choosing either the single-client or + multi-client driver version. + +2. At compile-time by setting hardware and software interrupt priorities + in the board support file. + +3. During run-time initialization by setting #RF_Params when calling + #RF_open(). + +4. At run-time via #RF_control(). + + +Build configuration +------------------- + +The RF driver comes in two versions: single-client and multi-client. The +single-client version allows only one driver instance to access the RF core at +a time. The multi-client driver version allows concurrent access to the RF +core with different RF settings. The multi-client driver has a slightly larger +footprint and is not needed for many proprietary applications. The driver +version can be selected in the build configuration by linking against a +RFCC26X2_multiMode pre-built library. The multi-client driver is the default +configuration in the SimpleLink SDKs. + + +Board configuration +------------------- + +The RF driver handles RF core hardware interrupts and uses software interrupts +for its internal state machine. For managing the interrupt priorities, it +expects the existence of a global #RFCC26XX_HWAttrsV2 object. This object is configured +in SysConfig and defined in the generated file `ti_drivers_config.c`. +By default, the priorities are set to the lowest possible value: + +@code +const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs = { + .hwiPriority = INT_PRI_LEVEL7, // Lowest HWI priority: INT_PRI_LEVEL7 + // Highest HWI priority: INT_PRI_LEVEL1 + + .swiPriority = 0, // Lowest SWI priority: 0 + // Highest SWI priority: Swi.numPriorities - 1 + + .xoscHfAlwaysNeeded = true // Power driver always starts XOSC-HF: true + // RF driver will request XOSC-HF if needed: false +}; +@endcode + + +Initialization +-------------- + +When initiating an RF driver instance, the function #RF_open() accepts a +pointer to a #RF_Params object which might set several driver parameters. In +addition, it expects an #RF_Mode object and a setup command which is usually +generated by SmartRF Studio: + +@code +RF_Params rfParams; +RF_Params_init(&rfParams); +rfParams.nInactivityTimeout = 2000; + +RF_Handle rfHandle = RF_open(&rfObject, &RF_prop, + (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams); +@endcode + +The function #RF_open() returns a driver handle that is used for accessing the +correct driver instance. Please note that the first RF operation command +before an RX or TX operation command must be a `CMD_FS` to set the synthesizer +frequency. The RF driver caches both, the pointer to the setup command and the +physical `CMD_FS` for automatic power management. + + +Run-time configuration +---------------------- + +While a driver instance is opened, it can be re-configured with the function +#RF_control(). Various configuration parameters @ref RF_CTRL are available. +Example: + +@code +uint32_t timeoutUs = 2000; +RF_control(rfHandle, RF_CTRL_SET_INACTIVITY_TIMEOUT, &timeoutUs); +@endcode + +
+@anchor rf_command_execution +Command execution +================= + +The RF core supports 3 different kinds of commands: + +1. Direct commands +2. Immediate commands +3. Radio operation commands + +Direct and immediate commands are dispatched via #RF_runDirectCmd() and +#RF_runImmediateCmd() respectively. These functions block until the command +has completed and return a status code of the type #RF_Stat when done. + +@code +#include + +RF_Stat status = RF_runDirectCmd(rfHandle, CMD_ABORT); +assert(status == RF_StatCmdDoneSuccess); +@endcode + +Radio operation commands are potentially long-running commands and support +different triggers as well as conditional execution. Only one command can be +executed at a time, but the RF driver provides an internal queue that stores +commands until the RF core is free. Two interfaces are provided for radio +operation commands: + +1. Asynchronous: #RF_postCmd() and #RF_pendCmd() +2. Synchronous: #RF_runCmd() + +The asynchronous function #RF_postCmd() posts a radio operation into the +driver's internal command queue and returns a command handle of the type +#RF_CmdHandle which is an index in the command queue. The command is +dispatched as soon as the RF core has completed any previous radio operation +command. + +@code +#include + +RF_Callback callback = NULL; +RF_EventMask subscribedEvents = 0; +RF_CmdHandle rxCommandHandle = RF_postCmd(rfHandle, (RF_Op*)&RF_cmdRx, + RF_PriorityNormal, callback, subscribedEvents); + +assert(rxCommandHandle != RF_ALLOC_ERROR); // The command queue is full. +@endcode + +Command execution happens in background. The calling task may proceed with +other work or execute direct and immediate commands to interact with the +posted radio operation. But beware that the posted command might not have +started, yet. By calling the function #RF_pendCmd() and subscribing events of +the type #RF_EventMask, it is possible to re-synchronize to a posted command: + +@code +// RF_EventRxEntryDone must have been subscribed in RF_postCmd(). +RF_EventMask events = RF_pendCmd(rfHandle, rxCommandHandle, + RF_EventRxEntryDone); + +// Program proceeds after RF_EventRxEntryDone or after a termination event. +@endcode + +The function #RF_runCmd() is a combination of both, #RF_postCmd() and +#RF_pendCmd() and allows synchronous execution. + +A pending or already running command might be aborted at any time by calling +the function #RF_cancelCmd() or #RF_flushCmd(). These functions take command +handles as parameters, but can also just abort anything in the RF driver's +queue: + +@code +uint8_t abortGraceful = 1; + +// Abort a single command +RF_cancelCmd(rfHandle, rxCommandHandle, abortGraceful); + +// Abort anything +RF_flushCmd(rfHandle, RF_CMDHANDLE_FLUSH_ALL, abortGraceful); +@endcode + +When aborting a command, the return value of #RF_runCmd() or #RF_pendCmd() +will contain the termination reason in form of event flags. If the command is +in the RF driver queue, but has not yet start, the #RF_EventCmdCancelled event is +raised. + +
+@anchor rf_event_callbacks +Event callbacks +=============== + +The RF core generates multiple interrupts during command execution. The RF +driver maps these interrupts 1:1 to callback events of the type #RF_EventMask. +Hence, it is unnecessary to implement own interrupt handlers. Callback events +are divided into 3 groups: + +- Command-specific events, documented for each radio operation command. An example + is the #RF_EventRxEntryDone for the `CMD_PROP_RX`. + +- Generic events, defined for all radio operations and originating on the RF core. + These are for instance #RF_EventCmdDone and #RF_EventLastCmdDone. Both events + indicate the termination of one or more RF operations. + +- Generic events, defined for all radio operations and originating in the RF driver, + for instance #RF_EventCmdCancelled. + +@sa @ref RF_Core_Events, @ref RF_Driver_Events. + +How callback events are subscribed was shown in the previous section. The +following snippet shows a typical event handler callback for a proprietary RX +operation: + +@code +void rxCallback(RF_Handle handle, RF_CmdHandle command, RF_EventMask events) +{ + if (events & RF_EventRxEntryDone) + { + Semaphore_post(rxPacketSemaphore); + } + if (events & RF_EventLastCmdDone) + { + // ... + } +} +@endcode + +In addition, the RF driver can generate error and power-up events that do not +relate directly to the execution of a radio command. Such events can be +subscribed by specifying the callback function pointers #RF_Params::pErrCb and +#RF_Params::pPowerCb. + +All callback functions run in software interrupt (SWI) context. Therefore, +only a minimum amount of code should be executed. When using absolute timed +commands with tight timing constraints, then it is recommended to set the RF +driver SWIs to a high priority. +See @ref rf_setup_and_configuration "Setup and configuration" for more details. + +
+@anchor rf_power_management +Power management +================ + +The RF core is a hardware peripheral and can be switched on and off. The RF +driver handles that automatically and provides the following power +optimization features: + +- Lazy power-up and radio setup caching +- Power-down on inactivity +- Deferred dispatching of commands with absolute timing + + +Lazy power-up and radio setup caching +------------------------------------- + +The RF core optimizes the power consumption by enabling the RF core as late as +possible. For instance does #RF_open() not power up the RF core immediately. +Instead, it waits until the first radio operation command is dispatched by +#RF_postCmd() or #RF_runCmd(). + +The function #RF_open() takes a radio setup command as parameter and expects a +`CMD_FS` command to follow. The pointer to the radio setup command and the +whole `CMD_FS` command are cached internally in the RF driver. They will be +used for every proceeding power-up procedure. Whenever the client re-runs a +setup command, the driver updates its internal cache with the new settings. +RF driver also caches the first CMD_FS from the list of done commands. Please +refer #RF_postCmd() for limitations of command chains. + +By default, the RF driver measures the time that it needs for the power-up +procedure and uses that as an estimate for the next power cycle. On the +CC13x0/CC26x0 devices, power-up takes usually 1.6 ms. Automatic measurement +can be suppressed by specifying a custom power-up time with +#RF_Params::nPowerUpDuration. In addition, the client might set +#RF_Params::nPowerUpDurationMargin to cover any uncertainty when doing +automatic measurements. This is necessary in applications with a high hardware +interrupt load which can delay the RF driver's internal state machine +execution. + + +Power-down on inactivity +------------------------ + +Whenever a radio operation completes and there is no other radio operation in +the queue, the RF core might be powered down. There are two options in the RF +driver: + +- **Automatic power-down** by setting the parameter + #RF_Params::nInactivityTimeout. The RF core will then start a timer after + the last command in the queue has completed. The default timeout is "forever" + and this feature is disabled. + +- **Manual power-down** by calling #RF_yield(). The client should do this + whenever it knows that no further radio operation will be executed for a + couple of milliseconds. + +During the power-down procedure the RF driver stops the radio timer and saves +a synchronization timestamp for the next power-up. This keeps the radio timer +virtually in sync with the RTC even though it is not running all the time. The +synchronization is done in hardware. + + +Deferred dispatching of commands with absolute timing +----------------------------------------------------- + +When dispatching a radio operation command with an absolute start trigger that +is ahead in the future, the RF driver defers the execution and powers the RF +core down until the command is due. It does that only, when: + +1. `cmd.startTrigger.triggerType` is set to `TRIG_ABSTIME` + +2. The difference between #RF_getCurrentTime() and `cmd.startTime` + is at not more than 3/4 of a full RAT cycle. Otherwise the driver assumes + that `cmd.startTime` is in the past. + +3. There is enough time to run a full power cycle before `cmd.startTime` is + due. That includes: + + - the power-down time (fixed value, 1 ms) if the RF core is already + powered up, + + - the measured power-up duration or the value specified by + #RF_Params::nPowerUpDuration, + + - the power-up safety margin #RF_Params::nPowerUpDurationMargin + (the default is 282 microseconds). + +If one of the conditions are not fulfilled, the RF core is kept up and +running and the command is dispatched immediately. This ensures, that the +command will execute on-time and not miss the configured start trigger. + +
+@anchor rf_scheduling +Preemptive scheduling of RF commands in multi-client applications +================================================================= + +Schedule BLE and proprietary radio commands. + +@code +RF_Object rfObject_ble; +RF_Object rfObject_prop; + +RF_Handle rfHandle_ble, rfHandle_prop; +RF_Params rfParams_ble, rfParams_prop; +RF_ScheduleCmdParams schParams_ble, schParams_prop; + +RF_Mode rfMode_ble = +{ + .rfMode = RF_MODE_MULTIPLE, // rfMode for dual mode + .cpePatchFxn = &rf_patch_cpe_ble, + .mcePatchFxn = 0, + .rfePatchFxn = &rf_patch_rfe_ble, +}; + +RF_Mode rfMode_prop = +{ + .rfMode = RF_MODE_MULTIPLE, // rfMode for dual mode + .cpePatchFxn = &rf_patch_cpe_genfsk, + .mcePatchFxn = 0, + .rfePatchFxn = 0, +}; + +// Init RF and specify non-default parameters +RF_Params_init(&rfParams_ble); +rfParams_ble.nInactivityTimeout = 200; // 200us + +RF_Params_init(&rfParams_prop); +rfParams_prop.nInactivityTimeout = 200; // 200us + +// Configure RF schedule command parameters directly. +schParams_ble.priority = RF_PriorityNormal; +schParams_ble.endTime = 0; +schParams_ble.allowDelay = RF_AllowDelayAny; + +// Alternatively, use the helper function to configure the default behavior +RF_ScheduleCmdParams_init(&schParams_prop); + +// Open BLE and proprietary RF handles +rfHandle_ble = RF_open(rfObj_ble, &rfMode_ble, (RF_RadioSetup*)&RF_cmdRadioSetup, &rfParams_ble); +rfHandle_prop = RF_open(rfObj_prop, &rfMode_prop, (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams_prop); + +// Run a proprietary Fs command +RF_runCmd(rfHandle_pro, (RF_Op*)&RF_cmdFs, RF_PriorityNormal, NULL, NULL); + +// Schedule a proprietary RX command +RF_scheduleCmd(rfHandle_pro, (RF_Op*)&RF_cmdPropRx, &schParams_prop, &prop_callback, RF_EventRxOk); + +// Schedule a BLE advertiser command +RF_scheduleCmd(rfHandle_ble, (RF_Op*)&RF_cmdBleAdv, &schParams_ble, &ble_callback, + (RF_EventLastCmdDone | RF_EventRxEntryDone | RF_EventTxEntryDone)); + +@endcode + +
+@anchor rf_rat +Accessing the Radio Timer (RAT) +============================== + +The Radio Timer on the RF core is an independent 32 bit timer running at a +tick rate of 4 ticks per microsecond. It is only physically active while the +RF core is on. But because the RF driver resynchronizes the RAT to the RTC on +every power-up, it appears to the application as the timer is always running. +The RAT accuracy depends on the system HF clock while the RF core is active +and on the LF clock while the RF core is powered down. + +The current RAT time stamp can be obtained by #RF_getCurrentTime(): + +@code +uint32_t now = RF_getCurrentTime(); +@endcode + +The RAT has 8 independent channels that can be set up in capture and compare +mode by #RF_ratCapture() and #RF_ratCompare() respectively. Three of these +channels are accessible by the RF driver. Each channel may be connected to +physical hardware signals for input and output or may trigger a callback +function. + +In order to allocate a RAT channel and trigger a callback function at a +certain time stamp, use #RF_ratCompare(): + +@code +RF_Handle rfDriver; +RF_RatConfigCompare config; +RF_RatConfigCompare_init(&config); +config.callback = &onRatTriggered; +config.channel = RF_RatChannelAny; +config.timeout = RF_getCurrentTime() + RF_convertMsToRatTicks(1701); + +RF_RatHandle ratHandle = RF_ratCompare(rfDriver, &config, nullptr); +assert(ratHandle != RF_ALLOC_ERROR); + +void onRatTriggered(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime) +{ + if (e & RF_EventError) + { + // RF driver failed to trigger the callback on time. + } + printf("RAT has triggered at %u.", compareCaptureTime); + + // Trigger precisely with the same period again + config.timeout = compareCaptureTime + RF_convertMsToRatTicks(1701); + ratHandle = RF_ratCompare(rfDriver, &config, nullptr); + assert(ratHandle != RF_ALLOC_ERROR); +} +@endcode + +The RAT may be used to capture a time stamp on an edge of a physical pin. This +can be achieved with #RF_ratCapture(). + +@code +#include +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include +#include +// Map IO 26 to RFC_GPI0 +GPIO_setConfigAndMux(IOID_26, GPIO_CFG_NO_DIR, IOC_PORT_RFC_GPI0); + +RF_Handle rfDriver; +RF_RatConfigCapture config; +RF_RatConfigCapture_init(&config); +config.callback = &onSignalTriggered; +config.channel = RF_RatChannelAny; +config.source = RF_RatCaptureSourceRfcGpi0; +config.captureMode = RF_RatCaptureModeRising; +config.repeat = RF_RatCaptureRepeat; + +RF_RatHandle ratHandle = RF_ratCapture(rfDriver, &config, nullptr); +assert(ratHandle != RF_ALLOC_ERROR); + +void onSignalTriggered(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime) +{ + if (e & RF_EventError) + { + // An internal error has occurred + } + printf("Rising edge detected on IO 26 at %u.", compareCaptureTime); +} +@endcode + +In both cases, the RAT may generate an output signal when being triggered. The +signal can be routed to a physical IO pin: + +@code +// Generate a pulse on an internal RAT output signal +RF_RatConfigOutput output; +RF_RatConfigOutput_init(&output); +output.mode = RF_RatOutputModePulse; +output.select = RF_RatOutputSelectRatGpo3; +RF_ratCompare(...); + +// Map RatGpo3 to one of four intermediate doorbell signals. +// This has to be done in the override list in order to take permanent effect. +// The override list can be found in the RF settings .c file exported from +// SmartRF Studio. +// Attention: This will change the default mapping of the PA and LNA signal as well. +#include +static uint32_t pOverrides[] = +{ + HW_REG_OVERRIDE(0x1110, RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3), + // ... +} + +// Finally, route the intermediate doorbell signal to a physical pin. +#include +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include +#include +GPIO_setConfigAndMux(IOID_17, GPIO_CFG_NO_DIR, IOC_PORT_RFC_GPO2); +@endcode + +
+@anchor rf_tx_power +Programming the TX power level +============================== + +The application can program a TX power level for each RF client with the function +#RF_setTxPower(). The new value takes immediate effect if the RF core is up and +running. Otherwise, it is stored in the RF driver client configuration. + +TX power may be stored in a lookup table in ascending order. This table is usually +generated and exported from SmartRF Studio together with the rest of the PHY configuration. +A typical power table my look as follows: +@code +RF_TxPowerTable_Entry txPowerTable[] = { + { .power = 11, .value = { 0x1233, RF_TxPowerTable_DefaultPA }}, + { .power = 13, .value = { 0x1234, RF_TxPowerTable_DefaultPA }}, + // ... + RF_TxPowerTable_TERMINATION_ENTRY +}; +@endcode + +@note Some devices offer a high-power PA in addition to the default PA. +A client must not mix configuration values in the same power table and must +not hop from a default PA configuration to a high-power PA configuration unless it +can guarantee that the RF setup command is re-executed in between. + +Given this power table format, the application may program a new power level in multiple +ways. It can use convenience functions to search a certain power level +in the power table or may access the table index-based: +@code +// Set a certain power level. Search a matching level. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, 17)); + +// Set a certain power level with a known level. +RF_setTxPower(h, txPowerTable[3].value); + +// Set a certain power without using a human readable level. +RF_setTxPower(h, value); + +// Set maximum power. Search the value. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, RF_TxPowerTable_MAX_DBM)); + +// Set minimum power without searching. +RF_setTxPower(h, txPowerTable[0].value); + +// Set minimum power. Search the value. +RF_setTxPower(h, RF_TxPowerTable_findValue(txPowerTable, RF_TxPowerTable_MIN_DBM)); + +// Set maximum power without searching. +int32_t lastIndex = sizeof(txPowerTable) / sizeof(RF_TxPowerTable_Entry) - 2; +RF_setTxPower(h, txPowerTable[lastIndex].value); +@endcode + +The current configured power level for a client can be retrieved by #RF_getTxPower(). +@code +// Get the current configured power level. +int8_t power = RF_TxPowerTable_findPowerLevel(txPowerTable, RF_getTxPower(h)); +@endcode + +
+@anchor rf_temperature_compensation +Temperature Compensation +============================== + +The RF driver improves the accuracy of XOSC_HF by performing temperature +dependent compensation. This is commonly done in the BAW/SIP devices where the +compensation parameters are already available inside the package. + +When temperature compensation is enabled, RF_enableHPOSCTemperatureCompensation() +is called during the board initialization(in Board_init()). This function enables +the RF driver to update HPOSC_OVERRIDE with the correct frequency offset according +to the ambient temperature at radio setup. + +@code +// Enable RF Temperature Compensation +status = RF_enableHPOSCTemperatureCompensation(void) +@endcode + +The RF driver also subscribes to a temperature notification event that triggers +for 3 degree Celsius change in temperature. At every 3 degree Celsius change in +temperature, it updates the RF core with the new frequency offset and re-subscribes +to the temperature notification with updated thresholds. + +@warning At the moment, temperature compensation is only supported on BAW or SIP +device variants. + +Error Handling +-------------- +When temperature compensation is enabled, but HPOSC_OVERRIDE is not found, then +RF_open() returns a NULL handle. + +RF_enableHPOSCTemperatureCompensation() returns #RF_StatInvalidParamsError if +the temperature notification fails to register. + +When the temperature notification fails to register, a global callback can be +executed by subscribing to the event #RF_GlobalEventTempNotifyFail defined in +#RF_GlobalEvent. + +@note The #RF_Handle in the global callback function will belong to the current +active client and this client is not causing the failure, since neither the +temperature event nor the failure is client specific. + +
+@anchor rf_convenience_features +Convenience features +==================== + +The RF driver simplifies often needed tasks and provides additional functions. +For instance, it can read the RSSI while the RF core is in RX mode using the +function :tidrivers_api:`RF_getRssi`: + +@code +int8_t rssi = RF_getRssi(rfHandle); +assert (rssi != RF_GET_RSSI_ERROR_VAL); // Could not read the RSSI +@endcode + +
+ ****************************************************************************** + */ + +//***************************************************************************** +// +//! \addtogroup rf_driver +//! @{ +//! \addtogroup rf_driver_cc13x2_cc26x2 +//! @{ +// +//***************************************************************************** + +#ifndef ti_drivers_rfcc26x2__include +#define ti_drivers_rfcc26x2__include + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_ble_cmd.h) +#include DeviceFamily_constructPath(driverlib/rf_ieee_cmd.h) + +/** + * @name RF Core Events + * @anchor RF_Core_Events + * + * Events originating on the RF core and caused during command execution. + * They are aliases for the corresponding interrupt flags. + * RF Core Events are command-specific and are explained in the Technical Reference Manual. + * + * @sa RF_postCmd(), RF_pendCmd(), RF_runCmd() + * @{ + */ +#define RF_EventCmdDone (1 << 0) ///< A radio operation command in a chain finished. +#define RF_EventLastCmdDone (1 << 1) ///< A stand-alone radio operation command or the last radio operation command in a chain finished. +#define RF_EventFGCmdDone (1 << 2) ///< A IEEE-mode radio operation command in a chain finished. +#define RF_EventLastFGCmdDone (1 << 3) ///< A stand-alone IEEE-mode radio operation command or the last command in a chain finished. +#define RF_EventTxDone (1 << 4) ///< Packet transmitted +#define RF_EventTXAck (1 << 5) ///< ACK packet transmitted +#define RF_EventTxCtrl (1 << 6) ///< Control packet transmitted +#define RF_EventTxCtrlAck (1 << 7) ///< Acknowledgement received on a transmitted control packet +#define RF_EventTxCtrlAckAck (1 << 8) ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define RF_EventTxRetrans (1 << 9) ///< Packet retransmitted +#define RF_EventTxEntryDone (1 << 10) ///< Tx queue data entry state changed to Finished +#define RF_EventTxBufferChange (1 << 11) ///< A buffer change is complete +#define RF_EventPaChanged (1 << 14) ///< The PA was reconfigured on the fly. +#define RF_EventSamplesEntryDone (1 << 15) ///< CTE data has been copied, only valid if autocopy feature is enabled +#define RF_EventRxOk (1 << 16) ///< Packet received with CRC OK, payload, and not to be ignored +#define RF_EventRxNOk (1 << 17) ///< Packet received with CRC error +#define RF_EventRxIgnored (1 << 18) ///< Packet received with CRC OK, but to be ignored +#define RF_EventRxEmpty (1 << 19) ///< Packet received with CRC OK, not to be ignored, no payload +#define RF_EventRxCtrl (1 << 20) ///< Control packet received with CRC OK, not to be ignored +#define RF_EventRxCtrlAck (1 << 21) ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define RF_EventRxBufFull (1 << 22) ///< Packet received that did not fit in the Rx queue +#define RF_EventRxEntryDone (1 << 23) ///< Rx queue data entry changing state to Finished +#define RF_EventDataWritten (1 << 24) ///< Data written to partial read Rx buffer +#define RF_EventNDataWritten (1 << 25) ///< Specified number of bytes written to partial read Rx buffer +#define RF_EventRxAborted (1 << 26) ///< Packet reception stopped before packet was done +#define RF_EventRxCollisionDetected (1 << 27) ///< A collision was indicated during packet reception +#define RF_EventModulesUnlocked (1 << 29) ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define RF_EventInternalError (uint32_t)(1 << 31) ///< Internal error observed +#define RF_EventMdmSoft 0x0000002000000000 ///< Synchronization word detected (MDMSOFT interrupt flag) +/** @}*/ + +/** + * @name RF Driver Events + * @anchor RF_Driver_Events + * + * Event flags generated by the RF Driver. + * @{ + */ +#define RF_EventCmdCancelled 0x1000000000000000 ///< Command canceled before it was started. +#define RF_EventCmdAborted 0x2000000000000000 ///< Abrupt command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventCmdStopped 0x4000000000000000 ///< Graceful command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventRatCh 0x0800000000000000 ///< A user-programmable RAT channel triggered an event. +#define RF_EventPowerUp 0x0400000000000000 ///< RF power up event. \deprecated This event is deprecated. Use #RF_ClientEventPowerUpFinished instead. +#define RF_EventError 0x0200000000000000 ///< Event flag used for error callback functions to indicate an error. See RF_Params::pErrCb. +#define RF_EventCmdPreempted 0x0100000000000000 ///< Command preempted by another command with higher priority. Applies only to multi-client applications. +/** @}*/ + +/** + * @name Control codes for driver configuration + * @anchor RF_CTRL + * + * Control codes are used in RF_control(). + * + * @{ + */ + +/*! + * @brief Control code used by RF_control to set inactivity timeout + * + * Setting this control allows RF to power down the radio upon completion of a radio + * command after a specified timeout period (in us) + * With this control code @b arg is a pointer to the timeout variable and returns RF_StatSuccess. + */ +#define RF_CTRL_SET_INACTIVITY_TIMEOUT 0 +/*! + * @brief Control code used by RF_control to update setup command + * + * Setting this control notifies RF that the setup command is to be updated, so that RF will take + * proper actions when executing the next setup command. + * Note the updated setup command will take effect in the next power up cycle when RF executes the + * setup command. Prior to updating the setup command, user should make sure all pending commands + * have completed. + */ +#define RF_CTRL_UPDATE_SETUP_CMD 1 +/*! + * @brief Control code used by RF_control to set powerup duration margin + * + * Setting this control updates the powerup duration margin. Default is RF_DEFAULT_POWER_UP_MARGIN. + */ +#define RF_CTRL_SET_POWERUP_DURATION_MARGIN 2 +/*! + * @brief Control code used by RF_control to set the phy switching margin + * + * Setting this control updates the phy switching duration margin, which is used to calculate when + * run-time conflicts shall be evaluated in case of colliding radio operations issued from two + * different clients. Default is RF_DEFAULT_PHY_SWITCHING_MARGIN. + */ +#define RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN 3 +/*! + * @brief Control code used by RF_control to set max error tolerance for RAT/RTC + * + * Setting this control updates the error tol for how frequently the CMD_RAT_SYNC_STOP is sent. + * Default is RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US (5 us) + * Client is recommeneded to change this setting before sending any commands. + */ +#define RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL 4 +/*! + * @brief Control code used by RF_control to set power management + * + * Setting this control configures RF driver to enable or disable power management. + * By default power management is enabled. + * If disabled, once RF core wakes up, RF driver will not go to standby and will not power down RF core. + * To configure power management, use this control to pass a parameter value of 0 to disable power management, + * and pass a parameter value of 1 to re-enable power management. + * This control is valid for dual-mode code only. Setting this control when using single-mode code has no effect + * (power management always enabled). + */ +#define RF_CTRL_SET_POWER_MGMT 5 +/*! + * @brief Control code used by RF_control to set the hardware interrupt priority level of the RF driver. + * + * This control code sets the hardware interrupt priority level that is used by the RF driver. Valid + * values are INT_PRI_LEVEL1 (highest) until INT_PRI_LEVEL7 (lowest). The default interrupt priority is + * set in the board support file. The default value is -1 which means "lowest possible priority". + * + * When using the TI-RTOS kernel, INT_PRI_LEVEL0 is reserved for zero-latency interrupts and must not be used. + * + * Execute this control code only while the RF core is powered down and the RF driver command queue is empty. + * This is usually the case after calling RF_open(). Changing the interrupt priority level while the RF driver + * is active will result in RF_StatBusyError being returned. + * + * Example: + * @code + * #include DeviceFamily_constructPath(driverlib/interrupt.h) + * + * int32_t hwiPriority = INT_PRI_LEVEL5; + * RF_control(rfHandle, RF_CTRL_SET_HWI_PRIORITY, &hwiPriority); + * @endcode + */ +#define RF_CTRL_SET_HWI_PRIORITY 6 +/*! + * @brief Control code used by RF_control to set the software interrupt priority level of the RF driver. + * + * This control code sets the software interrupt priority level that is used by the RF driver. Valid + * values are integers starting at 0 (lowest) until Swi_numPriorities - 1 (highest). The default + * interrupt priority is set in the board support file. The default value is 0 which means means + * "lowest possible priority". + * + * Execute this control code only while the RF core is powered down and the RF driver command queue is empty. + * This is usually the case after calling RF_open(). Changing the interrupt priority level while the RF driver + * is active will result in RF_StatBusyError being returned. + * + * Example: + * @code + * #include + * + * // Set highest possible priority + * uint32_t swiPriority = ~0; + * RF_control(rfHandle, RF_CTRL_SET_SWI_PRIORITY, &swiPriority); + * @endcode + */ +#define RF_CTRL_SET_SWI_PRIORITY 7 +/*! + * @brief Control code used by RF_control to mask the available RAT channels manually. + * + * This control code can be used to manually disallow/allow access to certain RAT channels from the RAT APIs. + * A typical use case is when a RAT channel is programmed through chained radio operations, and hence is + * used outside the scope of the RF driver. By disallowing access to this channel one can prevent collision + * between the automatic channel allocation through #RF_ratCompare()/#RF_ratCapture() and the direct + * configuration through #RF_postCmd(). + */ +#define RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK 8 +/*! + * @brief Control code used by RF_control to enable or disable the coexistence feature at runtime + * + * This control code can be used to manually override the statically configured setting for global enable/disable + * of the coexistence feature. It will have no effect if coexistence is not originally enabled and included + * in the compiled project. + * + * Example: + * @code + * // Disable the CoEx feature + * uint32_t coexEnabled = 0; + * RF_control(rfHandle, RF_CTRL_COEX_CONTROL, &coexEnabled); + * @endcode + */ +#define RF_CTRL_COEX_CONTROL 9 +/** @}*/ + +/** + * @name TX Power Table defines + * @{ + */ + +/** + * Refers to the the minimum available power in dBm when accessing a power + * table. + * + * \sa #RF_TxPowerTable_findValue() + */ +#define RF_TxPowerTable_MIN_DBM -128 + +/** + * Refers to the the maximum available power in dBm when accessing a power + * table. + * + * \sa #RF_TxPowerTable_findValue() + */ +#define RF_TxPowerTable_MAX_DBM 126 + +/** + * Refers to an invalid power level in a TX power table. + * + * \sa #RF_TxPowerTable_findPowerLevel() + */ +#define RF_TxPowerTable_INVALID_DBM 127 + +/** + * Refers to an invalid power value in a TX power table. + * + * This is the raw value part of a TX power configuration. In order to check + * whether a given power configuration is valid, do: + * + * @code + * RF_TxPowerTable_Value value = ...; + * if (value.rawValue == RF_TxPowerTable_INVALID_VALUE) { + * // error, value not valid + * } + * @endcode + * + * A TX power table is always terminated by an invalid power configuration. + * + * \sa #RF_getTxPower(), RF_TxPowerTable_findValue + */ +#define RF_TxPowerTable_INVALID_VALUE 0x3fffff + +/** + * Marks the last entry in a TX power table. + * + * In order to use #RF_TxPowerTable_findValue() and #RF_TxPowerTable_findPowerLevel(), + * every power table must be terminated by a %RF_TxPowerTable_TERMINATION_ENTRY: + * + * @code + * RF_TxPowerTable_Entry txPowerTable[] = + * { + * { 20, RF_TxPowerTable_HIGH_PA_ENTRY(1, 2, 3) }, + * // ... , + * RF_TxPowerTable_TERMINATION_ENTRY + * }; + * @endcode + */ +#define RF_TxPowerTable_TERMINATION_ENTRY \ + { .power = RF_TxPowerTable_INVALID_DBM, .value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, .paType = RF_TxPowerTable_DefaultPA } } + +/** + * Creates a TX power table entry for the default PA. + * + * The values for \a bias, \a gain, \a boost and \a coefficient are usually measured by Texas Instruments + * for a specific front-end configuration. They can then be obtained from SmartRFStudio or SysConfig. + */ +#define RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost, coefficient) \ + { .rawValue = ((bias) << 0) | ((gain) << 6) | ((boost) << 8) | ((coefficient) << 9), .paType = RF_TxPowerTable_DefaultPA } + +/** + * Creates a TX power table Sub1-GHz entry for the default PA. + * + * The values for \a bias, \a gain, \a boost, \a coefficient and \a gain2 are usually measured by Texas Instruments + * for a specific front-end configuration. They can then be obtained from SmartRFStudio or SysConfig. + */ +#define RF_TxPowerTable_CC13x4Sub1GHz_DEFAULT_PA_ENTRY(bias, gain, boost, coefficient, gain2) \ + { .rawValue = ((bias) << 0) | ((gain) << 6) | ((boost) << 8) | ((coefficient) << 9) | ((gain2) << 16), .paType = RF_TxPowerTable_DefaultPA } + +/** + * Creates a TX power table entry for the High-power PA. + * + * The values for \a bias, \a ibboost, \a boost, \a coefficient and \a ldoTrim are usually measured by Texas Instruments + * for a specific front-end configuration. They can then be obtained from SmartRFStudio or SysConfig. + */ +#define RF_TxPowerTable_HIGH_PA_ENTRY(bias, ibboost, boost, coefficient, ldotrim) \ + { .rawValue = ((bias) << 0) | ((ibboost) << 6) | ((boost) << 8) | ((coefficient) << 9) | ((ldotrim) << 16), .paType = RF_TxPowerTable_HighPA } + + +/** @} */ + +/** + * @name Other defines + * @{ + */ +#define RF_GET_RSSI_ERROR_VAL (-128) ///< Error return value for RF_getRssi() +#define RF_CMDHANDLE_FLUSH_ALL (-1) ///< RF command handle to flush all RF commands +#define RF_ALLOC_ERROR (-2) ///< RF command or RAT channel allocation error +#define RF_SCHEDULE_CMD_ERROR (-3) ///< RF command schedule error +#define RF_ERROR_RAT_PROG (-255) ///< A rat channel could not be programmed. +#define RF_ERROR_INVALID_RFMODE (-256) ///< Invalid RF_Mode. Used in error callback. +#define RF_ERROR_CMDFS_SYNTH_PROG (-257) ///< Synthesizer error with CMD_FS. Used in error callback. If this error occurred in error callback, user needs to resend CMD_FS to recover. See the device's errata for more details. + +#define RF_NUM_SCHEDULE_ACCESS_ENTRIES 2 ///< Number of access request entries +#define RF_NUM_SCHEDULE_COMMAND_ENTRIES 8 ///< Number of scheduled command entries +#define RF_NUM_SCHEDULE_MAP_ENTRIES (RF_NUM_SCHEDULE_ACCESS_ENTRIES + RF_NUM_SCHEDULE_COMMAND_ENTRIES) ///< Number of schedule map entries. This is the sum of access request and scheduled command entries +#define RF_SCH_MAP_CURRENT_CMD_OFFSET RF_NUM_SCHEDULE_ACCESS_ENTRIES ///< Offset of the current command entry in the schedule map +#define RF_SCH_MAP_PENDING_CMD_OFFSET (RF_SCH_MAP_CURRENT_CMD_OFFSET + 2) ///< Offset of the first pending command entry in the schedule map + +#define RF_ABORT_PREEMPTION (1<<2) ///< Used with RF_cancelCmd() to provoke subscription to RadioFreeCallback +#define RF_ABORT_GRACEFULLY (1<<0) ///< Used with RF_cancelCmd() for graceful command termination + +#define RF_SCH_CMD_EXECUTION_TIME_UNKNOWN 0 ///< For unknown execution time for RF scheduler + +#define RF_RAT_ANY_CHANNEL (-1) ///< To be used within the channel configuration structure. Allocate any of the available channels. +#define RF_RAT_TICKS_PER_US 4 ///< Radio timer (RAT) ticks per microsecond. + +#define RF_LODIVIDER_MASK 0x7F ///< Mask to be used to determine the effective value of the setup command's loDivider field. + +/** + * @name Stack ID defines + * @anchor RF_Stack_ID + * + * Reserved values to identify which stack owns an RF_Handle h (stored as h->clientConfig.nID) + * @{ + */ +#define RF_STACK_ID_DEFAULT 0x00000000 ///< No value is set. +#define RF_STACK_ID_154 0x8000F154 ///< ID for TI 15.4 Stack +#define RF_STACK_ID_BLE 0x8000FB1E ///< ID for TI BLE Stack +#define RF_STACK_ID_EASYLINK 0x8000FEA2 ///< ID for TI EasyLink Stack +#define RF_STACK_ID_THREAD 0x8000FEAD ///< ID for TI Thread Stack +#define RF_STACK_ID_TOF 0x8000F00F ///< ID for TI TOF Stack +#define RF_STACK_ID_CUSTOM 0x0000FC00 ///< ID for Custom Stack +/** @} */ + +/*! +\brief Converts a duration given in \a microseconds into radio timer (RAT) ticks. +*/ +#define RF_convertUsToRatTicks(microseconds) \ + ((microseconds) * (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in \a milliseconds into radio timer (RAT) ticks. +*/ +#define RF_convertMsToRatTicks(milliseconds) \ + ((milliseconds) * 1000 * (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in radio timer (RAT) \a ticks into microseconds. +*/ +#define RF_convertRatTicksToUs(ticks) \ + ((ticks) / (RF_RAT_TICKS_PER_US)) + +/*! +\brief Converts a duration given in radio timer (RAT) \a ticks into milliseconds. +*/ +#define RF_convertRatTicksToMs(ticks) \ + ((ticks) / (1000 * (RF_RAT_TICKS_PER_US))) + + +/** @}*/ + + +/** + * \brief PA configuration value for a certain power level. + * + * A %RF_TxPowerTable_Value contains the power amplifier (PA) configuration for a certain power level. + * It encodes the PA type as well as a raw configuration value for the RF core hardware. + * + * \sa #RF_getTxPower(), #RF_setTxPower(), #RF_TxPowerTable_Entry, #RF_TxPowerTable_PAType. + */ +typedef struct { + uint32_t rawValue:22; ///< Hardware configuration value. + ///< + ///< - \c [15:0] used for default PA, + ///< - \c [21:0] used for High-power PA + uint32_t __dummy:9; + uint32_t paType:1; ///< Selects the PA type to be used. + ///< + ///< - 0: #RF_TxPowerTable_DefaultPA + ///< - 1: #RF_TxPowerTable_HighPA +} RF_TxPowerTable_Value; + +/** + * \brief TX power configuration entry in a TX power table. + * + * A %RF_TxPowerTable_Entry defines an entry in a lookup table. Each entry contains a + * human-readable power level \a power as key and a hardware configuration \a value. + * + * Example of a typical power table: + * \code + * RF_TxPowerTable_Entry txPowerTable[] = { + * { .power = 20, .value = { .rawValue = 0x1234, .paType = RF_TxPowerTable_HighPA }}, + * { .power = 19, .value = { .rawValue = 0x1233, .paType = RF_TxPowerTable_HighPA }}, + * // ... + * RF_TxPowerTable_TERMINATION_ENTRY + * }; + * \endcode + * + * \sa #RF_TxPowerTable_findPowerLevel(), #RF_TxPowerTable_findPowerLevel() + */ +typedef struct +{ + int8_t power; ///< Human readable power value representing + ///< the output in dBm. + + RF_TxPowerTable_Value value; ///< PA hardware configuration for that power level. +} __attribute__((packed)) RF_TxPowerTable_Entry; + + +/** + * \brief Selects a power amplifier path in a TX power value. + * + * %RF_TxPowerTable_PAType selects one of the available power amplifiers + * on the RF core. It is usually included in a #RF_TxPowerTable_Value. + */ +typedef enum { + RF_TxPowerTable_DefaultPA = 0, ///< Default PA + RF_TxPowerTable_HighPA = 1, ///< High-power PA +} RF_TxPowerTable_PAType; + + +/** @brief Base type for all radio operation commands. + * + * All radio operation commands share a common part. + * That includes the command id, a status field, chaining properties + * and a start trigger. + * Whenever an RF operation command is used with the RF driver, it needs + * to be casted to an RF_Op. + * + * More information about RF operation commands can be found in the Proprietary RF + * User's Guide. + * + * @sa RF_runCmd(), RF_postCmd(), RF_pendCmd() + */ +typedef rfc_radioOp_t RF_Op; + + +/** @brief Specifies a RF core firmware configuration. + * + * %RF_Mode selects a mode of operation and points to firmware patches for the RF core. + * There exists one instance per radio PHY configuration, usually generated by + * SmartRF Studio. + * After assigning %RF_Mode configuration to the RF driver via RF_open(), the + * driver caches the containing information and re-uses it on every power-up. + */ +typedef struct { + uint8_t rfMode; ///< Specifies which PHY modes should be activated. Must be set to RF_MODE_MULTIPLE for dual-mode operation. + void (*cpePatchFxn)(void); ///< Pointer to CPE patch function + void (*mcePatchFxn)(void); ///< Pointer to MCE patch function + void (*rfePatchFxn)(void); ///< Pointer to RFE patch function +} RF_Mode; + +/** @brief Scheduling priority of RF operation commands. + * + * When multiple RF driver instances are used at the same time, + * commands from different clients may overlap. + * If an RF operation with a higher priority than the currently + * running operation is scheduled by RF_scheduleCmd(), then the + * running operation is interrupted. + * + * In single-client applications, %RF_PriorityNormal should be used. + */ +typedef enum { + RF_PriorityHighest = 2, ///< Highest priority. Only use this for urgent commands. + RF_PriorityHigh = 1, ///< High priority. Use this for time-critical commands in synchronous protocols. + RF_PriorityNormal = 0, ///< Default priority. Use this in single-client applications. +} RF_Priority; + +/** + * @brief Priority level for coexistence priority signal. + * + * When the RF driver is configured for three-wire coexistence mode, one of the + * output wires will signal the priority level of the coexistence request. When + * RF operations are scheduled with RF_scheduleCmd(), the scheduler can be configured + * to override the default coexistence priority level for the RF operation. + * + * The coexistence priority level is binary because it translates to a high/low output signal. + */ +typedef enum { + RF_PriorityCoexDefault = 0, ///< Default priority. Use value configured by setup command. + RF_PriorityCoexLow = 1, ///< Low priority. Override default value configured by setup command. + RF_PriorityCoexHigh = 2, ///< High priority. Override default value configured by setup command. +} RF_PriorityCoex; + +/** + * @brief Behavior for coexistence request signal. + * + * When the RF driver is configured for three-wire coexistence mode, one of the + * output wires will signal the request level of the coexistence request. When + * RF operations are scheduled with RF_scheduleCmd(), the scheduler can be configured + * to override the default coexistence request line behavior for the RF operation in RX. + * + * This override will be ignored if the option to set request for an entire chain is active. + */ +typedef enum { + RF_RequestCoexDefault = 0, ///< Default request line behavior. Use value configured by setup command. + RF_RequestCoexAssertRx = 1, ///< Assert REQUEST in RX. Override default value configured by setup command. + RF_RequestCoexNoAssertRx = 2, ///< Do not assert REQUEST in RX. Override default value configured by setup command. +} RF_RequestCoex; + +/** + * @brief Runtime coexistence override parameters + * + * When RF operations are scheduled with RF_scheduleCmd(), the scheduler can be configured + * to override the default coexistence behavior. This structure encapsulates the available parameters. + */ +typedef struct { + RF_PriorityCoex priority; ///< Priority level for coexistence priority signal. + RF_RequestCoex request; ///< Behavior for coexistence request signal. +} RF_CoexOverride; + +/** + * @brief Coexistence override settings for BLE5 application scenarios + * + * This configuration is provided to the BLE Stack to override the default coexistence configuration + * depending on the current application and stack states. + */ +typedef struct { + RF_CoexOverride bleInitiator; + RF_CoexOverride bleConnected; + RF_CoexOverride bleBroadcaster; + RF_CoexOverride bleObserver; +} RF_CoexOverride_BLEUseCases; + +/** @brief Status codes for various RF driver functions. + * + * RF_Stat is reported as return value for RF driver functions which + * execute direct and immediate commands. + * Such commands are executed by RF_runDirectCmd() and RF_runImmediateCmd() in the + * first place, but also by some convenience functions like RF_cancelCmd(), + * RF_flushCmd(), RF_getInfo() and others. + */ +typedef enum { + RF_StatBusyError, ///< Command not executed because RF driver is busy. + RF_StatRadioInactiveError, ///< Command not executed because RF core is powered down. + RF_StatCmdDoneError, ///< Command finished with an error. + RF_StatInvalidParamsError, ///< Function was called with an invalid parameter. + RF_StatCmdEnded, ///< Cmd is found in the pool but was already ended. + RF_StatError = 0x80, ///< General error specifier. + RF_StatCmdDoneSuccess, ///< Command finished with success. + RF_StatCmdSch, ///< Command successfully scheduled for execution. + RF_StatSuccess ///< Function finished with success. +} RF_Stat; + +/** @brief Data type for events during command execution. + * + * Possible event flags are listed in @ref RF_Core_Events and @ref RF_Driver_Events. + */ +typedef uint64_t RF_EventMask; + +/** @brief A unified type for radio setup commands of different PHYs. + * + * Radio setup commands are used to initialize a PHY on the RF core. + * Various partially similar commands exist, each one represented + * by a different data type. + * RF_RadioSetup is a generic container for all types. + * A specific setup command is usually exported from SmartRF Studio + * and then passed to the RF driver in RF_open(). + */ +typedef union { + rfc_command_t commandId; ///< Generic command identifier. This is the first field + ///< in every radio operation command. + rfc_CMD_RADIO_SETUP_t common; ///< Radio setup command for BLE and IEEE modes + rfc_CMD_BLE5_RADIO_SETUP_t ble5; ///< Radio setup command for BLE5 mode + rfc_CMD_PROP_RADIO_SETUP_t prop; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz + rfc_CMD_PROP_RADIO_DIV_SETUP_t prop_div; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz + rfc_CMD_RADIO_SETUP_PA_t common_pa; ///< Radio setup command for BLE and IEEE modes with High Gain PA + rfc_CMD_BLE5_RADIO_SETUP_PA_t ble5_pa; ///< Radio setup command for BLE5 mode with High Gain PA + rfc_CMD_PROP_RADIO_SETUP_PA_t prop_pa; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz with High Gain PA + rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t prop_div_pa; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz with High Gain PA +} RF_RadioSetup; + +/** @brief Client-related RF driver events. + * + * Events originating in the RF driver but not directly related to a specific radio command, + * are called client events. + * Clients may subscribe to these events by specifying a callback function RF_Params::pClientEventCb. + * Events are activated by specifying a bitmask RF_Params::nClientEventMask. + * The callback is called separately for every event providing an optional argument. + * + * @code + * void onClientEvent(RF_Handle h, RF_ClientEvent event, void* arg) + * { + * switch (event) + * { + * case RF_ClientEventPowerUpFinished: + * // Set output port + * break; + * default: + * // Unsubscribed events must not be issued. + * assert(false); + * } + * } + * + * RF_Params params; + * params.pClientEventCb = &onClientEvent; + * params.nClientEventMask = RF_ClientEventPowerUpFinished; + * RF_open(...); + * @endcode + */ +typedef enum { + RF_ClientEventPowerUpFinished = (1 << 0), ///< The RF core has been powered up the radio setup has been finished. + RF_ClientEventRadioFree = (1 << 1), ///< Radio becomes free after a command has been preempted by a high-priority command of another client. + ///< This event is only triggered on a client that has been preempted. + ///< Clients may use this event to retry running their low-priority RF operation. + + RF_ClientEventSwitchClientEntered = (1 << 2) ///< Signals the client that the RF driver is about to switch over from another client. +} RF_ClientEvent; + +/** @brief Global RF driver events. + * + * The RF driver provides an interface through the global \c RFCC26XX_hwAttrs + * struct to register a global, client independent callback. This callback is + * typically used to control board related configurations such as antenna + * switches. + * + * @code + * void globalCallback(RF_Handle h, RF_GlobalEvent event, void* arg) + * { + * switch (event) + * { + * case RF_GlobalEventRadioSetup: + * { + * RF_RadioSetup* setupCommand = (RF_RadioSetup*)arg; + * // Select antenna path + * if (setupCommand->common.commandNo == CMD_PROP_RADIO_DIV_SETUP) { + * // Sub-1 GHz ... + * } else { + * // 2.4 GHz ... + * } + * } + * break; + * + * case RF_GlobalEventRadioPowerDown: + * // Disable antenna switch + * break; + * + * default: + * // Unsubscribed events must not be issued. + * assert(false); + * } + * } + * @endcode + * + * For the coexistence (coex) feature, some of the events are used to handle + * the I/O muxing of the GPIO signals for REQUEST, PRIORITY and GRANT. + * + * @code + * void globalCallback(RF_Handle h, RF_GlobalEvent event, void* arg) + * { + * RF_Cmd* pCurrentCmd = (RF_Cmd*)arg; + * + * if (event & RF_GlobalEventInit) { + * // Initialize and mux coex I/O pins to RF Core I/O signals + * } + * else if (event & RF_GlobalEventCmdStart) { + * if (pCurrentCmd->coexPriority != RF_PriorityCoexDefault){ + * // Release PRIORITY pin from RF Core and set it to value of coexPriority + * } + * } + * else if (event & RF_GlobalEventCmdStop) { + * if (pCurrentCmd->coexPriority != RF_PriorityCoexDefault) { + * // Mux PRIORITY pin to RF Core signal to return to default priority level + * } + * } + * } + * @endcode + * + * \sa #RF_GlobalCallback + */ +typedef enum { + RF_GlobalEventRadioSetup = (1 << 0), ///< The RF core is being reconfigured through a setup command. + ///< The \a arg argument is a pointer to the setup command. + ///< HWI context. + + RF_GlobalEventRadioPowerDown = (1 << 1), ///< The RF core is being powered down. + ///< The \a arg argument is empty. + ///< SWI context. + + RF_GlobalEventInit = (1 << 2), ///< RF_open() is called for the first time (number of registered clients changes from 0 to 1). + ///< The \a arg argument is empty. + ///< Task context. + + RF_GlobalEventCmdStart = (1 << 3), ///< A command chain is being dispatched to the radio. + ///< The \a arg argument is a pointer to the current command. + ///< HWI context. + + RF_GlobalEventCmdStop = (1 << 4), ///< Command termination event is handled. + ///< The \a arg argument is a pointer to the current command. + ///< HWI context. + + RF_GlobalEventCoexControl = (1 << 5), ///< Change to coex configuration is requested + ///< The \a arg argument is pointer to at least 8-bit wide int with value 1=enable, or 0=disable + ///< Task/HWI context. + + RF_GlobalEventTempNotifyFail = (1 << 6), ///< Registration of temperature notification was unsuccessful + ///< (failure returned from temperature driver) + ///< The \a arg argument is empty. + ///< HWI context + +} RF_GlobalEvent; + + +/** @brief Event mask for combining #RF_ClientEvent event flags in #RF_Params::nClientEventMask. + * + */ +typedef uint32_t RF_ClientEventMask; + +/** @brief Event mask for combining #RF_GlobalEvent event flags in #RFCC26XX_HWAttrsV2::globalEventMask. + * + */ +typedef uint32_t RF_GlobalEventMask; + +/** @brief Command handle that is returned by RF_postCmd(). + * + * A command handle is an integer number greater equals zero and identifies + * a command container in the RF driver's internal command queue. A client + * can dispatch a command with RF_postCmd() and use the command handle + * later on to make the RF driver interact with the command. + * + * A negative value has either a special meaning or indicates an error. + * + * @sa RF_pendCmd(), RF_flushCmd(), RF_cancelCmd(), ::RF_ALLOC_ERROR, + * ::RF_CMDHANDLE_FLUSH_ALL + */ +typedef int16_t RF_CmdHandle; + +/** @struct RF_Object + * @brief Stores the client's internal configuration and states. + * + * Before RF_open() can be called, an instance of RF_Object must be created where + * the RF driver can store its internal configuration and states. + * This object must remain persistent throughout application run-time and must not be + * modified by the application. + * + * The size of #RF_Object can be optimized for single-mode applications by providing a + * `RF_SINGLEMODE` symbol at compilation time. The pre-built single-mode archive was generated + * with this symbol defined, hence any project using this archive must also define `RF_SINGLEMODE` + * on project level. + * + * @note Except configuration fields before call to RF_open(), modification of + * any field in %RF_Object is forbidden. + */ + + +/** @cond */ + +typedef struct RF_ObjectMultiMode RF_Object; + +/** Definition of the RF_Object structure for multi mode applications. + * It is applicable with the multi mode RF driver through the #RF_Object common type. + */ +struct RF_ObjectMultiMode{ + /// Configuration + struct { + uint32_t nInactivityTimeout; ///< Inactivity timeout in us. + RF_Mode* pRfMode; ///< Mode of operation. + RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. + uint32_t nPhySwitchingDuration; ///< Radio reconfiguration time to this client's phy and protocol. + uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. + uint32_t nPowerUpDurationFs; ///< Same as nPowerUpDuration, specifically when radio wakes up to execute an FS cmd. + bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. + bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. + uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. + void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead + void* pErrCb; ///< Error callback. + void* pClientEventCb; ///< Client event callback. + RF_ClientEventMask nClientEventMask; ///< Client event mask to activate client event callback. + uint16_t nPhySwitchingDurationMargin; ///< Phy switching duration margin in us. It is used to calculate when run-time conflicts shall be resolved. + uint32_t nID; ///< RF handle identifier. + } clientConfig; + /// State & variables + struct { + struct { + rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. + } mode_state; ///< (Mode-specific) state structure + SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. + RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). + void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. + RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). + ClockP_Struct clkReqAccess; ///< Clock used for request access timeout. + bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. + } state; +}; + +/** @endcond */ + +/** @brief A handle that is returned by to RF_open(). + * + * %RF_Handle is used for further RF client interaction with the RF driver. + * An invalid handle has the value NULL. + */ +typedef RF_Object* RF_Handle; + + +/** @brief RAT handle that is returned by RF_ratCompare() or RF_ratCapture(). + * + * An %RF_RatHandle is an integer number with value greater than or equal to zero and identifies + * a Radio Timer Channel in the RF driver's internal RAT module. A client can interact with the + * RAT module through the RF_ratCompare(), RF_ratCapture() or RF_ratDisableChannel() APIs. + * + * A negative value indicates an error. A typical example when RF_ratCompare() returns with RF_ALLOC_ERROR. + */ +typedef int8_t RF_RatHandle; + +/** @brief Selects the entry of interest in RF_getInfo(). + * + */ +typedef enum { + RF_GET_CURR_CMD, ///< Retrieve a command handle of the current command. + RF_GET_AVAIL_RAT_CH, ///< Create a bitmask showing available RAT channels. + RF_GET_RADIO_STATE, ///< Show the current RF core power state. 0: Radio OFF, 1: Radio ON. + RF_GET_SCHEDULE_MAP, ///< Deprecated. Not supported. + RF_GET_CLIENT_LIST, ///< Provide the client list. + RF_GET_CLIENT_SWITCHING_TIME, ///< Provide the client to client switching times +} RF_InfoType; + +/** @brief Stores output parameters for RF_getInfo(). + * + * This union structure holds one out of multiple data types. + * The contained value is selected by #RF_InfoType. + */ +typedef union { + RF_CmdHandle ch; ///< Command handle (#RF_GET_CURR_CMD). + uint16_t availRatCh; ///< Available RAT channels (RF_GET_AVAIL_RAT_CH). + bool bRadioState; ///< Current RF core power state (#RF_GET_RADIO_STATE). + RF_Handle pClientList[2]; ///< Client pointer list, [0]: client 1, [1]: client 2. + uint32_t phySwitchingTimeInUs[2]; ///< Phy switching time 0: client 1 -> 2, 1 : client 2 -> 1. + void *pScheduleMap; ///< Deprecated. Not supported. +} RF_InfoVal; + +/** @brief RF schedule map entry structure. + * + */ +typedef struct { + RF_CmdHandle ch; ///< Command handle + RF_Handle pClient; ///< Pointer to client object + uint32_t startTime; ///< Start time (in RAT tick) of the command or access request + uint32_t endTime; ///< End time (in RAT tick) of the command or access request + RF_Priority priority; ///< Priority of the command or access request +} RF_ScheduleMapElement; + +/** @brief RF schedule map structure. + * + */ +typedef struct { + RF_ScheduleMapElement accessMap[RF_NUM_SCHEDULE_ACCESS_ENTRIES]; ///< Access request schedule map + RF_ScheduleMapElement commandMap[RF_NUM_SCHEDULE_COMMAND_ENTRIES]; ///< Command schedule map +} RF_ScheduleMap; + +/** @brief Handles events related to RF command execution. + * + * RF command callbacks notify the application of any events happening during RF command execution. + * Events may either refer to RF core interrupts (@ref RF_Core_Events) or may be generated by the RF driver + * (@ref RF_Driver_Events). + * + * RF command callbacks are set up as parameter to RF_postCmd() or RF_runCmd() and provide: + * + * - the relevant driver client handle \a h which was returned by RF_open(), + * - the relevant radio operation command handle \a ch, + * - an event mask \a e containing the occurred events. + * + * RF command callbacks are executed in Software Interrupt (SWI) context and must not perform any + * blocking operation. + * The priority is configurable via #RFCC26XX_HWAttrsV2 in the board file or #RF_CTRL_SET_SWI_PRIORITY in RF_control(). + * + * The %RF_Callback function type is also used for signaling power events and + * errors. + * These are set in #RF_Params::pPowerCb and #RF_Params::pErrCb respectively. + * In case of a power event, \a ch can be ignored and \a e has #RF_EventPowerUp set. + * In case of an error callback, \a ch contains an error code instead of a command handle and + * \a e has the #RF_EventError flag set. + * + * @note Error and power callbacks will be replaced by #RF_ClientCallback in future releases. + */ +typedef void (*RF_Callback)(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); + +/** @brief Handles events related to the Radio Timer (RAT). + * + * The RF driver provides an interface to the Radio Timer through RF_ratCompare(), RF_ratCapture() and + * RF_ratDisableChannel() APIs. Each API call receives an optional input argument of the type + * RF_RatCallback. When a timer event occurs (compare, capture or error events), the registered + * callback is invoked. + * + * The RF_RatCallback provides the following argument: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - the relevant rat timer handle \a rh which the event is caused by, + * - an event mask \a e containing the occurred event (RF_EventRatCh or RF_EventError) + * - the captured value or the compare time \a compareCaptureTime read from the Radio Timer channel. + */ +typedef void (*RF_RatCallback)(RF_Handle h, RF_RatHandle rh, RF_EventMask e, uint32_t compareCaptureTime); + +/** + * @brief Handles events related to a driver instance. + * + * The RF driver produces additional events that are not directly related to the execution of a certain command, but + * happen during general RF driver operations. + * This includes power-up events, client switching events and others. + * + * A client callback provides the following arguments: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - an event identifier \a event, + * - an optional argument \a arg depending on the event. + * + * RF client callbacks are executed in Software Interrupt (SWI) context and must not perform any blocking operation. + * The priority is configurable via #RFCC26XX_HWAttrsV2 in the board file or #RF_CTRL_SET_SWI_PRIORITY in RF_control(). + */ +typedef void (*RF_ClientCallback)(RF_Handle h, RF_ClientEvent event, void* arg); + +/** + * @brief Handles global events as part of PHY configuration. + * + * The RF driver serves additional global, client independent events by invoking the #RF_GlobalCallback function + * registered through #RFCC26XX_HWAttrsV2::globalCallback in the board file. The function can subscribe to + * particular events through the #RFCC26XX_HWAttrsV2::globalEventMask, and receives the following arguments: + * - the relevant driver client handle \a h which was returned by RF_open(), + * - an event identifier \a event, + * - an optional argument \a arg depending on the event. + * + * If multiple events happen at the same time, the callback is always invoked separately for each event. + * Depending on the event, the callback might be invoked in SWI or HWI context. + */ +typedef void (*RF_GlobalCallback)(RF_Handle h, RF_GlobalEvent event, void* arg); + +/** @brief RF driver configuration parameters. + * + * %RF_Params is used for initial RF driver configuration. + * It is initialized by RF_Params_init() and used by RF_open(). + * Each client has its own set of parameters. + * They are reconfigured on a client switch. + * Some of the parameters can be changed during run-time using RF_control(). + */ +typedef struct { + uint32_t nInactivityTimeout; ///< Inactivity timeout in microseconds. + ///< The default value is 0xFFFFFFFF (infinite). + + uint32_t nPowerUpDuration; ///< A custom power-up duration in microseconds. + ///< If 0, the RF driver will start with a conservative value and measure the actual time during the first power-up. + ///< The default value is 0. + + RF_Callback pPowerCb; ///< \deprecated Power up callback, will be removed future versions, see RF_Params::pClienteventCb instead. + ///< The default value is NULL. + + RF_Callback pErrCb; ///< \deprecated Callback function for driver error events. + + uint16_t nPowerUpDurationMargin; ///< An additional safety margin to be added to #RF_Params::nPowerUpDuration. + ///< This is necessary because of other hardware and software interrupts + ///< preempting the RF driver interrupt handlers and state machine. + ///< The default value is platform-dependent. + + uint16_t nPhySwitchingDurationMargin; ///< An additional safety margin to be used to calculate when conflicts shall be evaluated run-time. + + RF_ClientCallback pClientEventCb; ///< Callback function for client-related events. + ///< The default value is NULL. + + RF_ClientEventMask nClientEventMask; ///< Event mask used to subscribe certain client events. + ///< The purpose is to keep the number of callback executions small. + + uint32_t nID; ///< RF handle identifier. +} RF_Params; + +/** @brief Controls the behavior of the RF_scheduleCmd() API. + * + */ +typedef enum { + RF_StartNotSpecified = 0, + RF_StartAbs = 1, +} RF_StartType; + +/** @brief Controls the behavior of the RF_scheduleCmd() API. + * + */ +typedef enum { + RF_EndNotSpecified = 0, + RF_EndAbs = 1, + RF_EndRel = 2, + RF_EndInfinit = 3, + } RF_EndType; + +/* RF command. */ +typedef struct RF_Cmd_s RF_Cmd; + +/* RF command . */ +struct RF_Cmd_s { + List_Elem _elem; /* Pointer to next and previous elements. */ + RF_Callback volatile pCb; /* Pointer to callback function */ + RF_Op* pOp; /* Pointer to (chain of) RF operations(s) */ + RF_Object* pClient; /* Pointer to client */ + RF_EventMask bmEvent; /* Enable mask for interrupts from the command */ + RF_EventMask pastifg; /* Accumulated value of events happened within a command chain */ + RF_EventMask rfifg; /* Return value for callback 0:31 - RF_CPE0_INT, 32:63 - RF_HW_INT */ + RF_CmdHandle ch; /* Command handle */ + RF_Priority ePri; /* Priority of RF command */ + uint8_t volatile flags; /* [0: Aborted, 1: Stopped, 2: canceled] */ + uint32_t startTime; /* Command start time (in RAT ticks) */ + RF_StartType startType; /* Command start time type */ + uint32_t allowDelay; /* Delay allowed if the start time cannot be met. */ + uint32_t endTime; /* Command end time (in RAT ticks) */ + RF_EndType endType; /* Command end type */ + uint32_t duration; /* Command duration (in RAT ticks) */ + uint32_t activityInfo; /* General value supported by user */ + RF_PriorityCoex coexPriority; /* Command priority to use for coexistence request. */ + RF_RequestCoex coexRequest; /* Command REQUEST line behavior to use for coexistence request. */ +}; + +/** @brief RF Hardware attributes. + * + * This data structure contains platform-specific driver configuration. + * It is usually defined globally in a board support file. + */ +typedef struct { + uint8_t hwiPriority; ///< Priority for HWIs belong to the RF driver. + uint8_t swiPriority; ///< Priority for SWIs belong to the RF driver. + bool xoscHfAlwaysNeeded; ///< Indicate that the XOSC HF should be turned on by the power driver + RF_GlobalCallback globalCallback; ///< Pointer to a callback function serving client independent events listed in #RF_GlobalEvent. + RF_GlobalEventMask globalEventMask; ///< Event mask which the globalCallback is invoked upon. +} RFCC26XX_HWAttrsV2; + +/** @brief Controls the behavior of the state machine of the RF driver when a conflict is identified + * run-time between the commands waiting on the pend queue and the commands being actively executed + * by the radio. + */ +typedef enum +{ + RF_ExecuteActionNone = 0, ///< Execute if no conflict, let current command finish if conflict. + RF_ExecuteActionRejectIncoming = 1, ///< Abort the incoming command, letting the ongoing command finish. + RF_ExecuteActionAbortOngoing = 2, ///< Abort the ongoing command and run dispatcher again. +} RF_ExecuteAction; + +/** @brief Describes the location within the pend queue where the new command was inserted by the scheduler. + */ +typedef enum +{ + RF_ScheduleStatusError = -3, + RF_ScheduleStatusNone = 0, + RF_ScheduleStatusTop = 1, + RF_ScheduleStatusMiddle = 2, + RF_ScheduleStatusTail = 4, + RF_ScheduleStatusPreempt = 8 +} RF_ScheduleStatus; + +/** + * @brief Handles the queue sorting algorithm when a new command is submitted to the driver from any of + * the active clients. + * + * The function is invoked within the RF_scheduleCmd API. + * + * The default algorithm is subscribed through the #RFCC26XX_SchedulerPolicy::submitHook and implemented + * in the RF driver. The arguments are: + * - \a pCmdNew points to the command to be submitted. + * - \a pCmdBg is the running background command. + * - \a pCmdFg is the running foreground command. + * - \a pPendQueue points to the head structure of pend queue. + * - \a pDoneQueue points to the head structure of done queue. + * + * In case the radio APIs do not distinguish between background and foreground contexts, the active operation + * will be returned within the pCmdBg pointer. If there are no commands being executed, both the + * pCmdBg and pCmdFg pointers are returned as NULL. + */ +typedef RF_ScheduleStatus (*RF_SubmitHook)(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + +/** + * @brief Defines the execution and conflict resolution hook at runtime. + * + * The function is invoked before a scheduled command is about to be executed. + * If a conflict is identified before the start-time of the next radio command + * in the pending queue, this information is passed to the hook. The return + * value of type #RF_ExecuteAction determines the policy to be followed by the RF + * driver. + * + * The arguments are: + * - \a pCmdBg is the running background command. + * - \a pCmdFg is the running foreground command. + * - \a pPendQueue points to the head structure of pend queue. + * - \a pDoneQueue points to the head structure of done queue. + * - \a bConflict whether the incoming command conflicts with ongoing. + * - \a conflictCmd command that conflicts with ongoing. + */ +typedef RF_ExecuteAction (*RF_ExecuteHook)(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, bool bConflict, RF_Cmd* conflictCmd); + +/** @brief RF scheduler policy. + * + * This data structure contains function hooks which implements the scheduling + * algorithm used to inter-align one or more independent protocol stacks. + */ +typedef struct { + RF_SubmitHook submitHook; ///< Function hook implements the scheduling policy to be executed at the time of RF_scheduleCmd API call. + RF_ExecuteHook executeHook; ///< Function hook implements the runtime last second go-no-go execute decision +} RFCC26XX_SchedulerPolicy; + +/** @brief Controls the behavior of the RF_scheduleCmd() API. + * + */ +typedef enum { + RF_AllowDelayNone = 0, + RF_AllowDelayAny = UINT32_MAX +} RF_AllowDelay; + +/* @brief RF schedule command parameter struct + * + * RF schedule command parameters are used with the RF_scheduleCmd() call. + */ +typedef struct { + uint32_t startTime; ///< Start time in RAT Ticks for the radio command + RF_StartType startType; ///< Start type for the start time + uint32_t allowDelay; ///< Control word to define the policy of the scheduler if the timing of a command cannot be met. + ///< Only applicable on CC13x2 and CC26x2 devices. + ///< RF_AllowDelayNone: Reject the command. + ///< RF_AllowDelayAny: Append the command to the end of the queue. + uint32_t endTime; ///< End time in RAT Ticks for the radio command + RF_EndType endType; ///< End type for the end time + uint32_t duration; ///< Duration in RAT Ticks for the radio command + uint32_t activityInfo; ///< Activity info provided by user + RF_PriorityCoex coexPriority; ///< Priority to use for coexistence request. + RF_RequestCoex coexRequest; ///< REQUEST line behavior to use for coexistence request. +} RF_ScheduleCmdParams; + +/** @brief RF request access parameter struct + * + * RF request access command parameters are used with the RF_requestAccess() call. + */ +typedef struct { + uint32_t duration; ///< Radio access duration in RAT Ticks requested by the client + uint32_t startTime; ///< Start time window in RAT Time for radio access + RF_Priority priority; ///< Access priority +} RF_AccessParams; + +/** @brief Select the preferred RAT channel through the configuration of #RF_ratCompare() or #RF_ratCapture(). + * + * If RF_RatChannelAny is provided within the channel configuration (default), the API will + * allocate the first available channel. Otherwise, it tries to allocate the requested channel, + * and if it is not available, returns with #RF_ALLOC_ERROR. + */ +typedef enum { + RF_RatChannelAny = -1, ///< Chose the first available channel. + RF_RatChannel0 = 0, ///< Use RAT user channel 0. + RF_RatChannel1 = 1, ///< Use RAT user channel 1. + RF_RatChannel2 = 2, ///< Use RAT user channel 2. +} RF_RatSelectChannel; + +/** @brief Selects the source signal for #RF_ratCapture(). + * + * The source of a capture event can be selected through the source field of the + * #RF_RatConfigCapture configuration structure. + */ +typedef enum { + RF_RatCaptureSourceRtcUpdate = 20, ///< Selects the RTC update signal source. + RF_RatCaptureSourceEventGeneric = 21, ///< Selects the Generic event of Event Fabric as source. + RF_RatCaptureSourceRfcGpi0 = 22, ///< Selects the RFC_GPI[0] as source. This can be used i.e. + ///< to capture events on a GPIO. This requires that the GPIO + ///< is connected to RFC_GPO[0] from the GPIO driver. + RF_RatCaptureSourceRfcGpi1 = 23 ///< Selects the RFC_GPO[1] as source. This can be used i.e. + ///< to capture events on a GPIO. This requires that the GPIO + ///< is connected to RFC_GPO[1] from the GPIO driver. +} RF_RatCaptureSource; + +/** @brief Selects the mode of #RF_ratCapture(). + * + * The trigger mode of a capture event can be selected through the mode field of + * #RF_RatConfigCapture configuration structure. + */ +typedef enum { + RF_RatCaptureModeRising = 0, ///< Rising edge of the selected source will trigger a capture event. + RF_RatCaptureModeFalling = 1, ///< Falling edge of the selected source will trigger a capture event. + RF_RatCaptureModeBoth = 2 ///< Both rising and falling edges of the selected source will generate + ///< capture events. +} RF_RatCaptureMode; + +/** @brief Selects the repetition of #RF_ratCapture(). + * + * The configuration of a capture channel also defines whether the channel should be + * freed or automatically rearmed after a capture event occurred. In the latter case, the + * user needs to free the channel manually through the #RF_ratDisableChannel() API. + */ +typedef enum { + RF_RatCaptureSingle = 0, ///< Free the channel after the first capture event. + RF_RatCaptureRepeat = 1 ///< Rearm the channel after each capture events. +} RF_RatCaptureRepetition; + +/** @brief Selects the mode of the RAT_GPO[x] for #RF_ratCompare() or #RF_ratCapture(). + * + * In case of compare mode, the channel can generate an output signal of the selected + * mode on the configured RAT_GPO[x] interface, and can be interconnected with + * other subsystems through the RFC_GPO[x] or Event Fabric. An example use case is + * to generate a pulse on a GPIO. + * + * In case of capture mode, the channel can also generate an output signal of the + * selected mode on the configured RAT_GPO[x] interface. Note that the configuration + * of this output event is independent of the source signal of the capture event. + * An example use case is to generate a pulse on a GPIO on each raising edge of another + * GPIO source. + * + */ +typedef enum { + RF_RatOutputModePulse = 0, ///< Generates a one-clock period width pulse. + RF_RatOutputModeSet = 1, ///< Sets the output high on a RAT event. + RF_RatOutputModeClear = 2, ///< Sets the output low on a RAT event. + RF_RatOutputModeToggle = 3, ///< Inverts the polarity of the output. + RF_RatOutputModeAlwaysZero = 4, ///< Sets the output low independently of any RAT events. + RF_RatOutputModeAlwaysOne = 5, ///< Sets the output high independently of any RAT events. +} RF_RatOutputMode; + +/** @brief Selects GPO to be used with #RF_ratCompare() or #RF_ratCapture(). + * + * RAT_GPO[0] - Reserved by the RF core. User shall not modify the configuration, + * but can observe the signal through any of RFC_GPO[0:3]. + * RAT_GPO[1] - Reserved by the RF core only if sync word detection is enabled. + * Otherwise can be used through RFC_GPO[0:3]. + * RAT_GPO[2:3] - Available and can be used through any of the RFC_GPO[0:3]. + * RAT_GPO[4:7] - Available and can be used through the Event fabric. + */ +typedef enum { + RF_RatOutputSelectRatGpo1 = 1, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[1] + RF_RatOutputSelectRatGpo2 = 2, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[2] + RF_RatOutputSelectRatGpo3 = 3, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[3] + RF_RatOutputSelectRatGpo4 = 4, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[4] + RF_RatOutputSelectRatGpo5 = 5, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[5] + RF_RatOutputSelectRatGpo6 = 6, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[6] + RF_RatOutputSelectRatGpo7 = 7, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[7] +} RF_RatOutputSelect; + +/** @brief RF_ratCapture parameter structure. + * + * %RF_RatCapture parameters are used with the #RF_ratCapture() call. + */ +typedef struct { + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + RF_RatCaptureSource source; ///< Configuration of the event source to cause a capture event. + RF_RatCaptureMode captureMode; ///< Configuration of the mode of event to cause a capture event. + RF_RatCaptureRepetition repeat; ///< Configuration of the channel to be used in single or repeated mode. +} RF_RatConfigCapture; + +/** @brief RF_ratCompare parameter structure. + * + * %RF_RatCompare parameters are used with the #RF_ratCompare() call. + */ +typedef struct { + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + uint32_t timeout; ///< Timeout value in RAT ticks to be programmed in the timer as the + ///< trigger of compare event. +} RF_RatConfigCompare; + +/** @brief RAT related IO parameter structure. + * + * These parameters are used with the #RF_ratCompare() or #RF_ratCapture() calls. + */ +typedef struct { + RF_RatOutputMode mode; ///< The mode the GPO should operate in. + RF_RatOutputSelect select; ///< The signal which shall be connected to the GPO. +} RF_RatConfigOutput; + +/** @brief Creates a a new client instance of the RF driver. + * + * This function initializes an RF driver client instance using \a pObj as storage. + * It does not power up the RF core. + * Once the client starts the first RF operation command later in the application, + * the RF core is powered up and set into a PHY mode specified by \a pRfMode. + * The chosen PHY is then configured by a radio setup command \a pRadioSetup. + * Whenever the RF core is powered up, the RF driver re-executes the radio setup command \a pRadioSetup. + * Additional driver behavior may be set by an optional \a params. + * + * @code + * // Define parameters + * RF_Params rfParams; + * rfParams.nInactivityTimeout = 4; + * RF_Params_init(&rfParams); + * rfParams.nInactivityTimeout = 1701; // microseconds + * + * RF_Handle rfHandle = RF_open(&rfObject, &RF_prop, (RF_RadioSetup*)&RF_cmdPropRadioDivSetup, &rfParams); + * @endcode + * + * @note Calling context : Task + * + * @param pObj Pointer to a #RF_Object that will hold the state for this + * RF client. The object must be in persistent and writable + * memory. + * @param pRfMode Pointer to a #RF_Mode struct holding PHY information + * @param pRadioSetup Pointer to the radio setup command used for this client. + * This is re-executed by the RF Driver on each power-up. + * @param params Pointer to an RF_Params object with the desired driver configuration. + * A NULL pointer results in the default configuration being loaded. + * @return A handle for further RF driver calls on success. Otherwise NULL. + */ +extern RF_Handle RF_open(RF_Object *pObj, RF_Mode *pRfMode, RF_RadioSetup *pRadioSetup, RF_Params *params); + +/** + * @brief Close client connection to RF driver + * + * Allows a RF client (high-level driver or application) to close its connection + * to the RF driver. + * RF_close pends on all commands in the command queue before closing the connection. + * If a client has access to the radio by using RF_RequestAccess API, and the same client calls RF_close, + * then the connection to the RF driver is closed immediately without waiting for the access duration to be over. + * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + */ +extern void RF_close(RF_Handle h); + +/** + * @brief Return current radio timer value + * + * If the radio is powered returns the current radio timer value, if not returns + * a conservative estimate of the current radio timer value + * + * @note Calling context : Task/SWI/HWI + * + * @return Current radio timer value + */ +extern uint32_t RF_getCurrentTime(void); + +/** + * @brief Appends RF operation commands to the driver's command queue and returns a + * command handle. + * + * The RF operation \a pOp may either represent a single operation or may be the first + * operation in a chain. + * If the command queue is empty, the \a pCmd is dispatched immediately. If there are + * other operations pending, then \a pCmd is processed after all other commands have been + * finished. + * The RF operation command must be compatible to the RF_Mode selected by RF_open(), e.g. + * proprietary commands can only be used when the RF core is configured for proprietary mode. + * + * The returned command handle is an identifier that can be used to control command execution + * later on, for instance with RF_pendCmd() or RF_cancelCmd(). + * It is a 16 Bit signed integer value, incremented on every new command. + * If the RF driver runs out of command containers, RF_ALLOC_ERROR is returned. + * + * The priority \a ePri is only relevant in multi-client applications where commands of distinct + * clients may interrupt each other. + * Only commands started by RF_scheduleCmd() can preempt + * running commands. #RF_postCmd() or RF_runCmd() do never interrupt a running command. + * In single-client applications, \a ePri is ignored and should be set to ::RF_PriorityNormal. + * + * A callback function \a pCb might be specified to get notified about events during command + * execution. Events are subscribed by the bit mask \a bmEvent. + * Valid event flags are specified in @ref RF_Core_Events and @ref RF_Driver_Events. + * If no callback is set, RF_pendCmd() can be used to synchronize the current task to command + * execution. For this it is necessary to subscribe all relevant events. + * The termination events ::RF_EventLastCmdDone, ::RF_EventCmdCancelled, ::RF_EventCmdAborted and + * ::RF_EventCmdStopped are always implicitly subscribed. + * + * The following limitations apply to the execution of command chains: + * + * - If TRIG_ABSTIME is used as a start trigger for the first command, TRIG_REL_FIRST_START + * can not be used for any other command. This is because the RF driver may insert a + * frequency-select command (CMD_FS) at the front of the chain when it performs an + * automatic power-up. + * - If a command chain has more than one CMD_FS, the first CMD_FS in the chain is cached. + * This CMD_FS is used on the next automatic power-up. + * - To avoid execution of cached CMD_FS and directly use a new CMD_FS on power up, place CMD_FS + * at the head of the command chain. + * + * @note Calling context : Task/SWI + * + * @sa RF_pendCmd(), RF_runCmd(), RF_scheduleCmd(), RF_RF_cancelCmd(), RF_flushCmd(), RF_getCmdOp() + * + * @param h Driver handle previously returned by RF_open() + * @param pOp Pointer to the RF operation command. + * @param ePri Priority of this RF command (used for arbitration in multi-client systems) + * @param pCb Callback function called during command execution and upon completion. + * If RF_postCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback or that can be pended on. + * @return A handle to the RF command. Return value of RF_ALLOC_ERROR indicates error. + */ +extern RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op *pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Sorts and adds commands to the RF driver internal command queue. + * + * @param pCmdNew Pointer to the command to be submitted. + * @param pCmdBg Running background command. + * @param pCmdFg Running foreground command. + * @param pPendQueue Pointer to the head structure of pend queue. + * @param pDoneQueue Pointer to the head structure of done queue.. + * @return RF_defaultSubmitPolicy identifies the success or failure of queuing. + */ +extern RF_ScheduleStatus RF_defaultSubmitPolicy(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); + +/** + * @brief Makes a final decision before dispatching a scheduled command. + * + * @param pCmdBg Running background command. + * @param pCmdFg Running foreground command. + * @param pPendQueue Pointer to the head structure of pend queue. + * @param pDoneQueue Pointer to the head structure of done queue. + * @param bConflict Whether the incoming command conflicts with the ongoing. + * @param conflictCmd Command that conflicts with ongoing. + * @return RF_defaultSubmitPolicy identifies the success or failure of queuing. + */ +extern RF_ExecuteAction RF_defaultExecutionPolicy(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, bool bConflict, RF_Cmd* conflictCmd); + + +/** + * @brief Initialize the configuration structure to default values to be used with the RF_scheduleCmd() API. + * + * @note Calling context : Task/SWI/HWI + * + * @param pSchParams Pointer to the configuration structure. + * @return none + */ +extern void RF_ScheduleCmdParams_init(RF_ScheduleCmdParams *pSchParams); + +/** + * @brief Schedule an RF operation (chain) to the command queue. + * + * Schedule an #RF_Op to the RF command queue of the client with handle h.
+ * The command can be the first in a chain of RF operations or a standalone RF operation. + * If a chain of operations are posted they are treated atomically, i.e. either all + * or none of the chained operations are run.
+ * All operations must be posted in strictly increasing chronological order. Function returns + * immediately.
+ * + * Limitations apply to the operations posted: + * - The operation must be in the set supported in the chosen radio mode when + * RF_open() was called + * - Only a subset of radio operations are supported + * - Only some of the trigger modes are supported with potential power saving (TRIG_NOW, TRIG_ABSTIME) + * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param pOp Pointer to the #RF_Op. Must normally be in persistent and writable memory + * @param pSchParams Pointer to the schedule command parameter structure + * @param pCb Callback function called upon command completion (and some other events). + * If RF_scheduleCmd() fails no callback is made + * @param bmEvent Bitmask of events that will trigger the callback. + * @return A handle to the RF command. Return value of RF_ALLOC_ERROR indicates error. + */ +extern RF_CmdHandle RF_scheduleCmd(RF_Handle h, RF_Op *pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Synchronizes the calling task to an RF operation command \a ch and + * returns accumulated event flags. + * + * After having dispatched an RF operation represented by \a ch with RF_postCmd(), the + * command is running in parallel on the RF core. Thus, it might be desirable to synchronize + * the calling task to the execution of the command. + * With #RF_pendCmd(), the application can block until one of the events specified in + * \a bmEvent occurs or until the command finishes. + * The function consumes and returns all accumulated event flags that occurred during + * execution if they have been previously subscribed by RF_postCmd(). + * Possible events are specified in @ref RF_Core_Events and @ref RF_Driver_Events. + * The termination events ::RF_EventLastCmdDone, ::RF_EventCmdCancelled, + * ::RF_EventCmdAborted and ::RF_EventCmdStopped are always implicitly subscribed and + * can not be masked. + * + * #RF_pendCmd() may be called multiple times for the same command. + * + * If #RF_pendCmd() is called for a command handle representing a finished command, + * then only the ::RF_EventLastCmdDone flag is returned, regardless of how the command + * finished. + * + * If the command has also a callback set, the callback is executed before #RF_pendCmd() + * returns. + * + * Example: + * @code + * // Dispatch a command to the RF driver's command queue + * RF_CmdHandle ch = RF_postCmd(driver, (RF_Op*)&CMD_PROP_RX, RF_PriorityNormal, NULL, RF_EventRxEntryDone); + * assert(ch != RF_ALLOC_ERROR); + * + * bool finished = false; + * while (finished == false) + * { + * // Synchronize to events during command execution. + * uint32_t events = RF_pendCmd(driver, ch, RF_EventRxEntryDone); + * // Check events that happen during execution + * if (events & RF_EventRxEntryDone) + * { + * // Process packet + * } + * if (events & (RF_EventLastCmdDone | RF_EventCmdStopped | RF_EventCmdAborted | RF_EventCmdCancelled)) + * { + * finished = true; + * } + * // ... + * } + * @endcode + * + * @note Calling context : Task + * + * @param h Driver handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param bmEvent Bitmask of events that make RF_pendCmd() return. Termination events + * are always implicitly subscribed. + * @return Event flags accumulated during command execution. + * + * @sa RF_postCmd() + */ +extern RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent); + +/** + * @brief Runs synchronously an RF operation command or a chain of commands and returns + * the termination reason. + * + * This function appends an RF operation command or a chain of commands to the RF driver's + * command queue and then waits for it to complete. + * A command is completed if one of the termination events ::RF_EventLastCmdDone, + * ::RF_EventCmdCancelled, ::RF_EventCmdAborted, ::RF_EventCmdStopped occurred. + * + * This function is a combination of RF_postCmd() and RF_pendCmd(). + * All options and limitations for RF_postCmd() apply here as well. + * + * An application should always ensure that the command completed in the expected way and + * with an expected status code. + * + * @note Calling context : Task + * + * @param h Driver handle previously returned by RF_open() + * @param pOp Pointer to the RF operation command. + * @param ePri Priority of this RF command (used for arbitration in multi-client systems) + * @param pCb Callback function called during command execution and upon completion. + * If RF_runCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback or that can be pended on. + * @return The relevant termination event. + * + * @sa RF_postCmd(), RF_pendCmd(), RF_cancelCmd(), RF_flushCmd() + */ +extern RF_EventMask RF_runCmd(RF_Handle h, RF_Op *pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Runs synchronously a (chain of) RF operation(s) for dual or single-mode. + * + * Allows a (chain of) operation(s) to be scheduled to the command queue and then waits + * for it to complete.
A command is completed if one of the RF_EventLastCmdDone, + * RF_EventCmdCancelled, RF_EventCmdAborted, RF_EventCmdStopped occurred. + * + * @note Calling context : Task + * @note Only one call to RF_pendCmd() or RF_runScheduleCmd() can be made at a time for + * each client + * + * @param h Handle previously returned by RF_open() + * @param pOp Pointer to the #RF_Op. Must normally be in persistent and writable memory + * @param pSchParams Pointer to the schedule command parameter structure + * @param pCb Callback function called upon command completion (and some other events). + * If RF_runScheduleCmd() fails, no callback is made. + * @param bmEvent Bitmask of events that will trigger the callback. + * @return The relevant command completed event. + */ +extern RF_EventMask RF_runScheduleCmd(RF_Handle h, RF_Op *pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent); + +/** + * @brief Abort/stop/cancel single command in command queue. + * + * If command is running, aborts/stops it and posts callback for the + * aborted/stopped command.
+ * If command has not yet run, cancels it it and posts callback for the + * canceled command.
+ * If command has already run or been aborted/stopped/canceled, has no effect.
+ * If RF_cancelCmd is called from a Swi context with same or higher priority + * than RF Driver Swi, when the RF core is powered OFF -> the cancel callback will be delayed + * until the next power-up cycle.
+ * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param mode 1: Stop gracefully, 0: abort abruptly + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode); + +/** + * @brief Abort/stop/cancel command and any subsequent commands in command queue. + * + * If command is running, aborts/stops it and then cancels all later commands in queue.
+ * If command has not yet run, cancels it and all later commands in queue.
+ * If command has already run or been aborted/stopped/canceled, has no effect.
+ * The callbacks for all canceled commands are issued in chronological order.
+ * If RF_flushCmd is called from a Swi context with same or higher priority + * than RF Driver Swi, when the RF core is powered OFF -> the cancel callback will be delayed + * until the next power-up cycle.
+ * + * @note Calling context : Task/SWI + * + * @param h Handle previously returned by RF_open() + * @param ch Command handle previously returned by RF_postCmd(). + * @param mode 1: Stop gracefully, 0: abort abruptly + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode); + +/** + * @brief Send any Immediate command.
+ * + * Immediate Command is send to RDBELL, if radio is active and the RF_Handle points + * to the current client.
+ * In other appropriate RF_Stat values are returned.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param pCmdStruct Pointer to the immediate command structure + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t *pCmdStruct); + +/** + * @brief Send any Direct command.
+ * + * Direct Command value is send to RDBELL immediately, if radio is active and + * the RF_Handle point to the current client.
+ * In other appropriate RF_Stat values are returned.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param cmd Direct command value. + * @return RF_Stat indicates if command was successfully completed. + */ +extern RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd); + +/** + * @brief Signal that radio client is not going to issue more commands in a while.
+ * + * Hint to RF driver that, irrespective of inactivity timeout, no new further + * commands will be issued for a while and thus the radio can be powered down at + * the earliest convenience. In case the RF_yield() is called within a callback, + * the callback will need to finish and return before the power down sequence is + * initiated. Posting new commands to the queue will cancel any pending RF_yield() + * request.
+ * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + */ +extern void RF_yield(RF_Handle h); + +/** + * @brief Function to initialize the RF_Params struct to its defaults. + * + * @param params An pointer to RF_Params structure for + * initialization + * + * Defaults values are: + * nInactivityTimeout = BIOS_WAIT_FOREVER + * nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME + */ +extern void RF_Params_init(RF_Params *params); + +/** + * @brief Get value for some RF driver parameters.
+ * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param type Request value parameter defined by RF_InfoType + * @param pValue Pointer to return parameter values specified by RF_InfoVal + * @return RF_Stat indicates if command was successfully completed + */ +extern RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue); + +/** + * @brief Get RSSI value. + * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @return RSSI value. Return value of RF_GET_RSSI_ERROR_VAL indicates error case. + */ +extern int8_t RF_getRssi(RF_Handle h); + +/** + * @brief Get command structure pointer. + * + * @note Calling context : Task/SWI/HWI + * + * @param h Handle previously returned by RF_open() + * @param cmdHnd Command handle returned by RF_postCmd() + * @return Pointer to the command structure. + */ +extern RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle cmdHnd); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT compare event. + * + * @note Calling context : Task/SWI/HWI + * + * @param channelConfig Pointer to the compare configuration structure. + * @return none + */ +extern void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT capture event. + * + * @note Calling context : Task/SWI/HWI + * + * @param channelConfig Pointer to the capture configuration structure. + * @return none + */ +extern void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig); + +/** + * @brief Initialize the configuration structure to be used to set up a RAT IO. + * + * @note Calling context : Task/SWI/HWI + * + * @param ioConfig Pointer to the IO configuration structure. + * @return none + */ +extern void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig); + +/** + * @brief Setup a Radio Timer (RAT) channel in compare mode. + * + * The %RF_ratCompare() API sets up one of the three available RAT channels in compare mode. + * When the compare event happens at the given compare time, the registered callback + * is invoked. + * + * The RF driver handles power management. If the provided compare time is far into the future + * (and there is no other constraint set i.e. due to radio command execution), the RF core will be + * powered OFF and the device will enter the lowest possible power state. The RF core will be + * automatically powered ON just before the registered compare event. The callback function is + * served upon expiration of the allocated channel. The function is invoked with event type + * #RF_EventRatCh and runs in SWI context. + * + * The API generates a "one-shot" compare event. Since the channel is automatically freed before + * the callback is served, the same channel can be reallocated from the callback itself through a + * new API call. + * + * In case there were no available channels at the time of API call, the function returns with + * #RF_ALLOC_ERROR and no callback is invoked. + * + * In case a runtime error occurs after the API successfully allocated a channel, the registered + * callback is invoked with event type #RF_EventError. A typical example is when the provided compare + * time is in the past and rejected by the RF core itself. + * + * The events issued by the RAT timer can be output from the timer module through the RAT_GPO + * interface, and can be interconnected with other parts of the system through the RFC_GPO or + * the Event Fabric. The mapping between the allocated RAT channel and the selected RAT_GPO + * can be controlled through the optional ioConfig argument of %RF_ratCompare(). The possible + * RAT_GPO[x] are defined in #RF_RatOutputSelect. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param channelConfig Pointer to configuration structure needed to set up a channel in compare mode. + * @param ioConfig Pointer to a configuration structure to set up the RAT_GPOs for the allocated + * channel (optional). + * @return Allocated RAT channel. If allocation fails, #RF_ALLOC_ERROR is returned. + * + * \sa #RF_RatConfigCompare_init(), #RF_RatConfigOutput_init(), #RF_ratDisableChannel(), #RF_ratCapture() + */ +extern RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig); + +/** + * @brief Setup a Radio Timer (RAT) channel in capture mode. + * + * The %RF_ratCapture() API sets up one of the three available RAT channels in capture mode. + * The registered callback is invoked on the capture event. + * + * The RF driver handles power management. If the RF core is OFF when the %RF_ratCapture() is called, + * it will be powered ON immediately and the RAT channel will be configured to capture mode. As long as + * at least one of the three RAT channels are in capture mode, the RF core will be kept ON. The callback + * function is served upon a capture event occurs. The function is invoked with event type RF_EventRatCh + * and runs in SWI context. + * + * In case the channel is configured into single capture mode, the channel is automatically freed before + * the callback is called. In repeated capture mode, the channel remains allocated and automatically rearmed. + * + * In case there were no available channels at the time of API call, the function returns with + * #RF_ALLOC_ERROR and no callback is invoked. + * + * In case a runtime error occurs after the API successfully allocated a channel, the registered + * callback is invoked with event type #RF_EventError. A typical example is when the provided compare + * time is in the past and rejected by the RF core itself. + * + * The events issued by the RAT timer can be output from the timer module through the RAT_GPO + * interface, and can be interconnected with other parts of the system through the RFC_GPO or + * the Event Fabric. The mapping between the allocated RAT channel and the selected RAT_GPO + * can be controlled through the optional ioConfig argument of %RF_ratCapture(). The possible + * RAT_GPO[x] are defined in #RF_RatOutputSelect. Note that this configuration is independent of + * the source signal of the capture event. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param channelConfig Pointer to configuration structure needed to set up a channel in compare mode. + * @param ioConfig Pointer to a configuration structure to set up the RAT_GPO for the allocated + * channel (optional). + * @return Allocated RAT channel. If allocation fails, #RF_ALLOC_ERROR is returned. + * + * \sa #RF_RatConfigCapture_init(), #RF_RatConfigOutput_init() , #RF_ratDisableChannel(), #RF_ratCompare() + */ +extern RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig); + +/** + * @brief Disable a RAT channel. + * + * The #RF_RatHandle returned by the #RF_ratCompare() or #RF_ratCapture() APIs can be used for further interaction with the + * Radio Timer. Passing the handle to %RF_ratDisableChannel() will abort a compare/capture event, and the provided channel + * is deallocated. No callback is invoked. This API can be called both if the RF core is ON or OFF. After the channel is + * freed, the next radio event will be rescheduled. A typical use case if a channel is configured in repeated capture mode, + * and the application decides to abort this operation. + * + * @note Calling context : Task/SWI + * + * @param rfHandle Handle previously returned by RF_open(). + * @param ratHandle #RF_RatHandle returned by #RF_ratCompare() or #RF_ratCapture(). + * @return #RF_Stat indicates if command was successfully completed. + * + * \sa #RF_ratCompare(), #RF_ratCapture() + */ +extern RF_Stat RF_ratDisableChannel(RF_Handle rfHandle, RF_RatHandle ratHandle); + +/** + * @brief Set RF control parameters. + * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + * @param ctrl Control codes + * @param args Pointer to control arguments + * @return RF_Stat indicates if API call was successfully completed. + */ +extern RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args); + +/** + * @brief Request radio access.
+ * + * Scope: + * 1. Only supports request access which start immediately.
+ * 2. The #RF_AccessParams duration should be less than a pre-defined value + * RF_REQ_ACCESS_MAX_DUR_US in RFCC26X2_multiMode.c.
+ * 3. The #RF_AccessParams priority should be set RF_PriorityHighest.
+ * 4. Single request for a client at anytime.
+ * 5. Command from different client are blocked until the radio access + * period is completed.
+ * + * @note Calling context : Task + * + * @param h Handle previously returned by RF_open() + * @param pParams Pointer to RF_AccessRequest parameters + * @return RF_Stat indicates if API call was successfully completed. + */ +extern RF_Stat RF_requestAccess(RF_Handle h, RF_AccessParams *pParams); + +/** + * @brief Returns the currently configured transmit power configuration. + * + * This function returns the currently configured transmit power configuration under the assumption + * that it has been previously set by #RF_setTxPower(). The value might be used for reverse + * lookup in a TX power table. If no power has been programmed, it returns an invalid value. + * + * @code + * RF_TxPowerTable_Value value = RF_getTxPower(handle); + * if (value.rawValue == RF_TxPowerTable_INVALID_VALUE) { + * // error, value not valid + * } + * @endcode + * + * @param h Handle previously returned by #RF_open() + * @return PA configuration struct + * + * @sa #RF_setTxPower(), #RF_TxPowerTable_findPowerLevel() + */ +extern RF_TxPowerTable_Value RF_getTxPower(RF_Handle h); + +/** + * @brief Updates the transmit power configuration of the RF core. + * + * This function programs a new TX power \a value and returns a status code. The API will return + * with RF_StatBusyError if there are still pending commands in the internal queue. In case of + * success, RF_StatSuccess is returned and the new configuration becomes effective from the next + * radio operation. + * + * Some devices provide an integrated high-power PA in addition to the Default PA. On these devices + * the API accepts configurations for both, and if \a value selects a different PA, the + * \a globalCallback is invoked. The implementation of \a globalCallback is board specific and can + * be used to reconfigure the external RF switches (if any). + * + * @param h Handle previously returned by #RF_open() + * @param value TX power configuration value. + * @return #RF_StatSuccess on success, otherwise an error code. + * + * @sa #RF_getTxPower(), #RF_TxPowerTable_Value, #RF_TxPowerTable_findValue() + */ +extern RF_Stat RF_setTxPower(RF_Handle h, RF_TxPowerTable_Value value); + +/** + * @brief Retrieves a power level in dBm for a given power configuration value. + * + * \c %RF_TxPowerTable_findPowerLevel() searches in a lookup \a table for a given transmit power + * configuration \a value and returns the power level in dBm if a matching configuration is found. + * If \a value can not be found, #RF_TxPowerTable_INVALID_DBM is returned. + * + * This function does a reverse lookup compared to #RF_TxPowerTable_findValue() and has + * O(n). It is assumed that \a table is terminated by a #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param table List of #RF_TxPowerTable_Entry entries, + * terminated by #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param value Power configuration value. + * + * @return Human readable power level in dBm on success, + * otherwise #RF_TxPowerTable_INVALID_DBM. + */ +extern int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value); + +/** + * @brief Retrieves a power configuration value for a given power level in dBm. + * + * \c %RF_TxPowerTable_findValue() searches in a lookup \a table for a given transmit power level + * \a powerLevel in dBm and returns a matching power configuration. If \a powerLevel can not be + * found, #RF_TxPowerTable_INVALID_VALUE is returned. + * + * This function performs a linear search in \a table and has O(n). + * It is assumed that \a table is defined in ascending order and is terminated by a + * #RF_TxPowerTable_TERMINATION_ENTRY. + * + * The following special values for \a powerLevel are also accepted: + * + * - #RF_TxPowerTable_MIN_DBM which returns always the lowest power value in the table + * - #RF_TxPowerTable_MAX_DBM which returns always the highest power value in the table + * + * @param table List of #RF_TxPowerTable_Entry entries, + * terminated by #RF_TxPowerTable_TERMINATION_ENTRY. + * + * @param powerLevel Human-readable power level in dBm. + * + * @return PA configuration value on success. + * otherwise #RF_TxPowerTable_INVALID_VALUE. + */ +extern RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel); + + +/** + * @brief Enables temperature monitoring and temperature based drift compensation + * + * @return #RF_StatSuccess if succesful or + * #RF_StatInvalidParamsError if temperature notification fails + * to register. + * + */ +extern RF_Stat RF_enableHPOSCTemperatureCompensation(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_rfcc26x2__include */ + +//***************************************************************************** +// +//! Close the Doxygen group. +//! @} +//! @} +// +//***************************************************************************** diff --git a/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2_multiMode.c b/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2_multiMode.c new file mode 100644 index 00000000..9dca62ba --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/rf/RFCC26X2_multiMode.c @@ -0,0 +1,6097 @@ +/* +* Copyright (c) 2015-2020, Texas Instruments Incorporated +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* +* * Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_memmap_common.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_rfc_rat.h) +#include DeviceFamily_constructPath(inc/hw_rfc_dbell.h) +#include DeviceFamily_constructPath(inc/hw_fcfg1.h) +#include DeviceFamily_constructPath(driverlib/rfc.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/aon_ioc.h) +#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib/adi.h) +#include DeviceFamily_constructPath(driverlib/aon_rtc.h) +#include DeviceFamily_constructPath(driverlib/chipinfo.h) +#include DeviceFamily_constructPath(driverlib/osc.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma diag_remark=Pa082 +#endif + +#if defined(RF_SINGLEMODE) +#error "An incompatible symbol (RF_SINGLEMODE) is defined in the project. \ + To build with this driver, remove the RF_SINGLEMODE token definition." +#endif + +/*-------------- Typedefs, structures & defines ---------------*/ + +/* Definition of internal state-machine events. */ +typedef enum RF_FsmEvent_ { + RF_FsmEventLastCommandDone = (1UL << 1), /* Indicates that a radio command is finished. */ + RF_FsmEventWakeup = (1UL << 2), /* Used to initiate the power up sequence of the RF core. */ + RF_FsmEventPowerDown = (1UL << 3), /* Used to initiate the power down sequence of the RF core. */ + RF_FsmEventInitChangePhy = (1UL << 10), /* Used to initiate the PHY change sequence. */ + RF_FsmEventFinishChangePhy = (1UL << 11), /* Used to finalize the PHY change sequence. */ + RF_FsmEventCpeInt = (1UL << 14), /* Generated during command execution. */ + RF_FsmEventPowerStep = (1UL << 29), /* Generated during the power up sequence of RF core. */ + RF_FsmEventRunScheduler = (1UL << 30) /* Used to invoke the scheduler again to check for conflicts. */ +} RF_FsmEvent; + +/* Definition of states of RF core. */ +typedef enum RF_CoreStatus_ { + RF_CoreStatusIdle = 0, /* The RF core is OFF. */ + RF_CoreStatusPoweringUp = 1, /* The RF core is being powered up. */ + RF_CoreStatusActive = 2, /* The RF core is ON. */ + RF_CoreStatusPoweringDown = 3, /* The RF core is being powered down. */ + RF_CoreStatusPhySwitching = 4 /* The RF core is being reconfigured. */ +} RF_CoreStatus; + +/* Definition of internal power constraints. Note that the physical RAT channels in the RF core are + not a one-to-one map to the constraint values here. */ +typedef enum RF_PowerConstraintSrc_ { + RF_PowerConstraintNone = 0, + RF_PowerConstraintRatCh0 = (1U << 0), /* Indicates that the Channel 0 of RAT timer is running. */ + RF_PowerConstraintRatCh1 = (1U << 1), /* Indicates that the Channel 1 of RAT timer is running. */ + RF_PowerConstraintRatCh2 = (1U << 2), /* Indicates that the Channel 2 of RAT timer is running. */ + RF_PowerConstraintCmdQ = (1U << 3), /* Indicates that the RF core executing a radio command. */ + RF_PowerConstraintDisallow = (1U << 7) /* Disable automatic power management. */ +} RF_PowerConstraintSrc; + +/* Definition of internal Radio Timer (RAT) modes. */ +typedef enum RF_RatMode_ { + RF_RatModeUndefined = 0, /* Indicates that the RAT channel is not configured. */ + RF_RatModeCompare = 1, /* Indicates that the RAT channel is configured to compare mode. */ + RF_RatModeCapture = 2 /* Indicates that the RAT channel is configured to capture mode. */ +} RF_RatMode; + +/* Definition of internal Radio Timer (RAT) states. */ +typedef enum RF_RatStatus_ { + RF_RatStatusIdle = 0, /* Indicates that the RAT channel is not used. */ + RF_RatStatusPending = 1, /* Indicates that the RAT channel is configured, but the RAT timer is not running (i.e. RF core is OFF). */ + RF_RatStatusRunning = 2 /* Indicates that the RAT channel is configured, and the RAT timer is running. */ +} RF_RatStatus; + +/* Definition of internal status codes of command shceduling. */ +typedef enum RF_ScheduleCmdStatus_ { + RF_ScheduleCmdSuccess = 0, /* Schedule command success. */ + RF_ScheduleCmdAllocError = 1, /* Schedule command allocation error (such as queue is full). */ + RF_ScheduleCmdSchError = 2 /* SChedule command scheduler error (timing or priority conflict). */ +} RF_ScheduleCmdStatus; + +/*-------------- Macros ---------------*/ + +#define ABS(x) (((x) < 0) ? -(x) : (x)) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) +#define MIN(x,y) (((x) < (y)) ? (x) : (y)) +#define UDIFF(x,y) (((y) > (x)) ? ((y) - (x)) : ((~0) + (y) - (x) + (1))) +#define ADD(x,y) ((x > ((~0) - (y))) ? (~0) : ((x) + (y))) + +/*-------------- Defines ---------------*/ + +/* Max # of RF driver clients */ +#define N_MAX_CLIENTS 2 +/* 8 RF_Cmds in pool */ +#define N_CMD_POOL 8 +/* Modulus mask used for RF_CmdHandle calculations */ +#define N_CMD_MODMASK 0xFFF + +/*-------------- Internal RF constants ---------------*/ + +#define RF_CMD0 0x0607 +#define RF_BOOT0 0xE0000011 +#define RF_BOOT1 0x00000080 +/* Accessible RF Core interrupts mask MSB 32 bits : RFHW int, LSB 32 bits : RF CPE int */ +#define RF_INTERNAL_IFG_MASK 0xFFFFFFDF60001000 +#define RF_TERMINATION_EVENT_MASK (RF_EventLastCmdDone | RF_EventLastFGCmdDone | RF_EventCmdAborted | RF_EventCmdStopped | RF_EventCmdCancelled) +#define RF_CMD_FG_CMD_FLAG (1 << 4) +#define RF_CMD_ALLOC_FLAG (1 << 7) +#define RF_CMD_TERMINATED (DONE_OK | ERROR_PAST_START) +#define RF_HW_INT_RAT_CH_MASK (RFC_DBELL_RFHWIFG_RATCH7 | RFC_DBELL_RFHWIFG_RATCH6 | RFC_DBELL_RFHWIFG_RATCH5) +#define RF_RAT_CH_CNT 3 +#define RF_HW_INT_CPE_MASK RFC_DBELL_RFHWIFG_MDMSOFT +#define RF_CPE0_INT_MASK 0xFFFFFFFF +/* Default value for power up duration (in us) used before first power cycle */ +#define RF_DEFAULT_POWER_UP_TIME 2500 +/* Default minimum power up duration (in us) */ +#define RF_DEFAULT_MIN_POWER_UP_TIME 300 +/* Default power-up margin (in us) to account for wake-up sequence outside the RF power state machine */ +#define RF_DEFAULT_POWER_UP_MARGIN 314 +/* Default phy-switching margin (in us) to account for overhead of processing time on the system MCU. */ +#define RF_DEFAULT_PHY_SWITCHING_MARGIN 314 +/* Default power down duration in us */ +#define RF_DEFAULT_POWER_DOWN_TIME 1000 +#define RF_MAX_CHAIN_CMD_LEN 8 +/* RAT channel (0-4) are used by RF Core. Only 5,6,7 are available for application */ +#define RF_RAT_CH_LOWEST 5 +#define RF_SEND_RAT_STOP_RATIO 7 +#define RF_RTC_CONV_TO_US_SHIFT 12 +#define RF_SHIFT_4_BITS 4 +#define RF_SHIFT_8_BITS 8 +#define RF_SHIFT_16_BITS 16 +#define RF_SHIFT_32_BITS 32 +#define RF_RTC_TICK_INC (0x100000000LL/32768) +#define RF_SCALE_RTC_TO_4MHZ 4000000 +#define RF_NUM_RAT_TICKS_IN_1_US 4 +/* (3/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_US (UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US * 3 / 4) +/* (1/4)th of a full RAT cycle, in us */ +#define RF_DISPATCH_MAX_TIME_WRAPAROUND_US (int32_t)(RF_DISPATCH_MAX_TIME_US - UINT32_MAX / RF_NUM_RAT_TICKS_IN_1_US) +#define RF_DISPATCH_INFINIT_TIME (UINT32_MAX) +#define RF_XOSC_HF_SWITCH_CHECK_PERIOD_US 50 +#define RF_DEFAULT_AVAILRATCH_VAL 0x7 +#define RF_ABORT_FLUSH_ALL 0x2 +#define RF_CMDSTA_REG_VAL_MASK 0xFF +#define RF_RAT_CAPTURE_REPEAT_MODE 0x10000000 +#define RF_RAT_INTERRUPT_BASE_INDEX 0x01 +#define RF_RAT_ERROR_BASE_INDEX 0x10 +#define RF_RAT_COMPENSATION_TIME_US 25 +#define RF_PHY_SWITCHING_MODE 1 +#define RF_PHY_BOOTUP_MODE 0 +#define RF_SCH_CMD_TIMING_INSERT 0x4 +#define RF_REQ_ACCESS_MAX_DUR_US 1000000 +/* Additional analog config time for setup command */ +#define RF_ANALOG_CFG_TIME_US 96 +/* Update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_UPDATE 0 +/* Don't update analog configuration in setup */ +#define RF_SETUP_ANALOGCFG_NOUPDATE 0x2D +#define RF_SCH_CMD_STARTTIME_NOW 0 +#define RF_SCH_CMD_ENDTIME_IGNORE 0 +#define RF_DEFAULT_PHY_SWITCHING_TIME 500 +#define RF_RADIOFREECB_PREEMPT_FLAG 0x1 +#define RF_RADIOFREECB_REQACCESS_FLAG 0x2 +#define RF_RADIOFREECB_CMDREJECT_FLAG 0x4 +#define RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US 5 +/* Approx for 1e6 / 500. XTAL drift is 500 ppm */ +#define RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT 11 +/* Window (in us) to decide if wakeup was from RF power up clock */ +#define RF_WAKEUP_DETECTION_WINDOW_IN_US 300 +/* Ieee context mask and background value */ +#define RF_IEEE_ID_MASK 0xFC00 +#define RF_IEEE_FG_CMD 0x2C00 +/* Defines for to mask High-PA overrides. */ +#define RF_TXSUB1_ENABLED 0xFFFE +#define RF_TX20_ENABLED 0xFFFF +#define RF_TX20_PATYPE_ADDRESS 0x21000345 +#define RF_TX20_PATYPE_MASK 0x04 +#define RF_TX20_GAIN_ADDRESS 0x2100034C +#define RF_TX20_GAIN_MASK 0x003FFFFF +#define RF_TX20_PATTERN TX20_POWER_OVERRIDE(0) +#define RF_TXSTD_PATTERN TX_STD_POWER_OVERRIDE(0) +#define RF_TXSUB1_PATTERN RF_TXSTD_PATTERN +#define RF_TX_OVERRIDE_MASK 0x000003FF +#define RF_TX_OVERRIDE_SHIFT 10 +#define RF_TX_OVERRIDE_INVALID_OFFSET 0xFF +/* Defines for update of the HPOSC override */ +#define RF_HPOSC_OVERRIDE_PATTERN HPOSC_OVERRIDE(0) +#define RF_HPOSC_OVERRIDE_MASK 0xFFFF +/* Common defines for override handling*/ +#define RF_OVERRIDE_SEARCH_DEPTH 80 +/* Define for HPOSC temperature limits */ +#define RF_TEMP_LIMIT_3_DEGREES_CELSIUS 0x3 + +/*-------------- Structures and definitions ---------------*/ + +/* FSM typedef. */ +typedef void (*RF_FsmStateFxn)(RF_Object*, RF_FsmEvent const); + +/* Rat channel configuration. */ +typedef struct RF_RatChannel_s RF_RatChannel; + +/* Rat channel configuration. */ +struct RF_RatChannel_s { + RF_Handle pClient; /* Pointer to client owning the channel. NULL means the channel is free. */ + RF_RatCallback pCb; /* Callback pointer of the channel. */ + RF_RatMode mode; /* Mode of this RAT channel: RF_RatModeCompare, etc. */ + RF_RatHandle handle; /* Channel number: 0,1,2. */ + RF_RatStatus status; /* Status of the channel: RF_RatStatusIdle, RF_RatStatusPending, RF_RatStatusRunning */ + uint64_t chCmd; /* Generic storage for the command structure itself. */ + uint32_t ioCmd; /* Raw binary to be sent to the CM0 to set up the GPOs. This is optional. */ +}; + +/* Rat module configuration. */ +typedef struct RF_RatModule_s RF_RatModule; + +/* Rat module configuration. */ +struct RF_RatModule_s { + RF_RatChannel channel[RF_RAT_CH_CNT]; /* Container of channel configurations. */ + uint8_t availableRatChannels; /* Storage of available RAT channels read from the RF core. */ + uint8_t volatile pendingInt; /* Pending interrupt flags to be served. */ + uint8_t numActiveChannels; /* Counter of active channels. This is used to compensate the + overhead of programming the channels.*/ +}; + +/* RF core configuration. */ +typedef struct RF_CoreState_s RF_CoreState; + +/* RF core configuration. */ +struct RF_CoreState_s +{ + RF_CoreStatus volatile status; + RF_FsmStateFxn fxn; + uint32_t activeTimeUs; + bool init; + bool manualXoscHfSelect; +}; + +/* RAT synchronization. */ +typedef union RF_RatSyncCmd_u RF_RatSyncCmd; + +/* RAT synchronization. */ +union RF_RatSyncCmd_u +{ + rfc_CMD_SYNC_START_RAT_t start; + rfc_CMD_SYNC_STOP_RAT_t stop; +}; + +/* Reconfigure the PA settings. */ +typedef union RF_ConfigurePaCmd_u RF_ConfigurePaCmd; + +/* Reconfigure the PA settings. */ +union RF_ConfigurePaCmd_u { + rfc_CMD_SET_TX_POWER_t tuneTxPower; + rfc_CMD_SET_TX20_POWER_t tuneTx20Power; +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + rfc_CMD_SET_TXSUB1_POWER_t tuneTxSub1Power; +#endif + rfc_CMD_CHANGE_PA_t changePa; +}; + +/* Command queue. */ +typedef struct RF_CmdQ_s RF_CmdQ; + +/* Command queue. */ +struct RF_CmdQ_s{ + List_List pPend; /* List of pending commands to be dispatched. */ + List_List pDone; /* List of executed commands to be served. */ + RF_Cmd* volatile pCurrCmdBg; /* Currently running command. */ + RF_Cmd* volatile pCurrCmdFg; /* Currently running foreground command. */ + RF_Cmd* volatile pCurrCmdCb; /* Command which callback to be invoked. */ + RF_CmdHandle volatile nSeqPost; /* Sequence # for previously posted command. */ + RF_CmdHandle volatile nSeqDone; /* Sequence # for last done command. */ +}; + +/* RF scheduler. */ +typedef struct RF_Sch_s RF_Sch_t; + +/* RF scheduler. */ +struct RF_Sch_s { + RF_Handle clientHnd[N_MAX_CLIENTS]; /* Client handle for each registered client. */ + RF_AccessParams accReq[N_MAX_CLIENTS]; /* Input parameters from any RF_requestAccess API calls. */ + RF_Handle clientHndRadioFreeCb; /* Client handle for the radio callback. */ + uint8_t issueRadioFreeCbFlags; /* Indicate if driver needs to issue RF_EventRadioFree callback {0:pre-emption, 1:requestAccess running, 2: reject command}. */ + uint8_t cmdInsertFlags; /* Indicate if the command was inserted based on timing information. */ +}; + +/*-------------- RTOS objects ---------------*/ + +/* RF core software interrupts */ +static SwiP_Struct RF_swiFsmObj; +static void RF_swiFsm(uintptr_t a, uintptr_t b); + +/* RF core hardware interrupts */ +static HwiP_Struct RF_hwiCpe0Obj; +static void RF_hwiCpe0Active(uintptr_t a); +static void RF_hwiCpe0PowerFsm(uintptr_t a); + +/* RF core HW software interrupts */ +static SwiP_Struct RF_swiHwObj; +static void RF_swiHw(uintptr_t a, uintptr_t b); + +/* RF core HW hardware interrupts */ +static HwiP_Struct RF_hwiHwObj; +static void RF_hwiHw(uintptr_t a); + +/* Clock used for triggering power-up sequences */ +static ClockP_Struct RF_clkPowerUpObj; +static void RF_clkPowerUp(uintptr_t a); + +/* Common inactivity timeout clock callback */ +static ClockP_Struct RF_clkInactivityObj; +static void RF_clkInactivityCallback(uintptr_t a); + +/* Common request access timeout clock callback */ +static void RF_clkReqAccess(uintptr_t a); + + +/*-------------- Static structures ---------------*/ + +/* Default RF parameters structure */ +static const RF_Params RF_defaultParams = { + .nInactivityTimeout = SemaphoreP_WAIT_FOREVER, + .nPowerUpDuration = 0, + .pPowerCb = NULL, + .pErrCb = NULL, + .nPowerUpDurationMargin = RF_DEFAULT_POWER_UP_MARGIN, + .nPhySwitchingDurationMargin = RF_DEFAULT_PHY_SWITCHING_MARGIN, + .pClientEventCb = NULL, + .nClientEventMask = 0, + .nID = 0, +}; + +/*-------------- Global variables ---------------*/ + +/* RF_Cmd container pool. Containers with extra information about RF commands. */ +static RF_Cmd RF_cmdPool[N_CMD_POOL]; + +/* Command queue top level structure. It contains pointers to the different queues. */ +static RF_CmdQ RF_cmdQ; + +/* Static object used to subscribe from early notification in the power driver */ +static Power_NotifyObj RF_wakeupNotifyObj; + +/* Power constraints set by the RF driver */ +static volatile uint8_t RF_powerConstraint; + +/* Pointer to current radio client (indicates also whether the radio is powered) */ +static RF_Object* RF_currClient; + +/* Current state of the RF core. */ +static RF_CoreState RF_core; + +/* Static container of a direct/immediate commands */ +static RF_RatModule RF_ratModule; + +/* Commands used to synchronize the RTC and the RAT timer. */ +static volatile RF_RatSyncCmd RF_ratSyncCmd; + +/* Top level structure of the shceduler unit. */ +static RF_Sch_t RF_Sch; + +/* Variables used for powerUpDuration, phySwitchingTime and RAT sync time calculation. */ +static uint32_t RF_rtcTimestampA; /* RTC timer value power-up and active time calculation. */ +static uint32_t RF_rtcBeginSequence; /* RTC timer value for switching time calculation. */ +static uint32_t RF_errTolValInUs; /* max allowed error between RAT/RTC drift to enable resync at power-down (in us). */ + +/* Counter of radio clients */ +static uint8_t RF_numClients; + +/* Current HPOSC frequency offset */ +static int32_t RF_currentHposcFreqOffset; + +/* Temperature notify object used by HPOSC device */ +static Temperature_NotifyObj RF_hposcRfCompNotifyObj; + +/* Common system-level temperature based synth compensation */ +static void (*pfnUpdateHposcOverride)(uint32_t *pRegOverride) = NULL; +static int_fast16_t (*pfnTemperatureUnregisterNotify)(Temperature_NotifyObj *notifyObject) = NULL; + +/*-------------- Externs ---------------*/ + +/* Hardware attribute structure populated in board file. */ +extern const RFCC26XX_HWAttrsV2 RFCC26XX_hwAttrs; + +/* Software policy set in the board file and implements the distributed scheduling algorithm. */ +__attribute__((weak)) RFCC26XX_SchedulerPolicy RFCC26XX_schedulerPolicy = { + .submitHook = RF_defaultSubmitPolicy, + .executeHook = RF_defaultExecutionPolicy +}; + +/*-------------- Booleans ---------------*/ + +/* variable to indicate with the FLASH is disable during the power up */ +static bool bDisableFlashInIdleConstraint; + +/*-------------- State machine functions ---------------*/ + +/* FSM state functions */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e); +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e); + +/*-------------- Helper functions ---------------*/ + +/* Command queue handling */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* pHead); + +/* Command handling*/ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd); +static RF_Cmd* RF_cmdAlloc(void); +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask); +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events); +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks, bool conflict, RF_Cmd** pAbsCmd); +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt); +static bool RF_checkCmdFsError(void); +static void RF_cacheFsCmd(RF_Cmd* pCmd); +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt); + +/* Scheduler */ +static void RF_issueRadioFreeCb(uint8_t src); +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd); +static RF_ScheduleStatus RF_howToSchedule(RF_Cmd* newCmd, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, RF_Cmd** pInsertLocation); + +/* RAT module */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch); +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel); +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle); +static uint32_t RF_ratGetValue(void); +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig); +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig); +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig); +static void RF_ratRestartChannels(void); +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh); +static void RF_ratFreeChannel(RF_RatChannel* ratCh); +static void RF_ratSuspendChannels(void); +static bool RF_ratReleaseChannels(void); +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks); +static bool RF_ratIsRunning(void); + +/* Time management */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration); +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks); +static void RF_dispatchNextEvent(void); +static void RF_dispatchNextCmd(void); +static void RF_restartClockTimeout(ClockP_Handle clock, uint32_t timeout); + +/* Power management */ +static void RF_corePowerDown(void); +void RF_powerConstraintRelease(RF_PowerConstraintSrc src); +void RF_powerConstraintSet(RF_PowerConstraintSrc src); +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src); +static void RF_setInactivityTimeout(void); + +/* Others */ +static void RF_init(void); +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e); +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus); +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus); +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg); +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd); +static void RF_dbellSyncOnAck(void); +static bool RF_isRadioSetup(RF_Op* pOp); +static void RF_initRadioSetup(RF_Handle handle); +static void RF_radioOpDoneCb(void); +static RF_Op* RF_findEndOfChain(RF_Op* pOp); +static void RF_applyRfCorePatch(bool mode); +static bool RF_isStateTransitionAllowed(void); + +/* PA management */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd); +static RF_Stat RF_updateSub1GHzPaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd); +static void RF_extractPaConfiguration(RF_Handle handle); +static bool RF_decodeOverridePointers(RF_RadioSetup* radioSetup, uint16_t** pTxPower, uint32_t** pRegOverride, uint32_t** pRegOverrideTxStd, uint32_t** pRegOverrideTx20); +static void RF_attachOverrides(uint32_t* baseOverride, uint32_t* newOverride); +static void RF_detachOverrides(uint32_t* baseOverride, uint32_t* newOverride); + +/* HPOSC management */ +static void RF_updateHpOscOverride(uint32_t *pRegOverride); +static void RF_hposcRfCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *notifyObject); + +/*-------------- Command queue internal functions ---------------*/ + +/* + * Compares the client of a command. + * + * Input: h - Client to check against. + * pCmd - Command to check. + * Return: true - If the client owns the command. + * false - Otherwise. + */ +static bool RF_isClientOwner(RF_Handle h, RF_Cmd* pCmd) +{ + if (pCmd && (pCmd->pClient == h)) + { + return(true); + } + else + { + return(false); + } +} + +/* + * Search last entry in simple queue for particular client. + * + * Input: h - Client handle. + * list - List to search within. + * Return: RF_Cmd if found any + */ +static RF_Cmd* RF_queueEnd(RF_Handle h, List_List* list) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Local variables */ + List_Elem* pTail = NULL; + List_Elem* pHead = List_head(list); + + /* Start at the head of queue */ + while (pHead) + { + if (RF_isClientOwner(h, (RF_Cmd*)pHead)) + { + pTail = pHead; + } + + pHead = List_next(pHead); + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the last entry belongs to the client */ + return((RF_Cmd*)pTail); +} + +/* + * Allocate a command buffer from the command pool. + * + * Input: none + * Return: RF command + */ +static RF_Cmd* RF_cmdAlloc(void) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the first available entry in the command pool */ + if (!(RF_cmdPool[i].flags & RF_CMD_ALLOC_FLAG)) + { + return(&RF_cmdPool[i]); + } + } + return(NULL); +} + +/* + * Search command in the command pool. + * + * Input: h - Handle to the client which the command should belong to. + * ch - Handle to the command to search for. + * mask - Optional mask of flags to compare to. + * Return: RF command + */ +static RF_Cmd* RF_cmdGet(RF_Handle h, RF_CmdHandle ch, uint8_t mask) +{ + uint32_t i; + for (i = 0; i < N_CMD_POOL; i++) + { + /* Find the allocated command pool entry corresponding to ch */ + if (RF_cmdPool[i].ch == ch) + { + if (RF_isClientOwner(h, &RF_cmdPool[i])) + { + /* If a mask is provided, check the flags too */ + if (!mask || (RF_cmdPool[i].flags & mask)) + { + return(&RF_cmdPool[i]); + } + } + } + } + return(NULL); +} + +/* + * Atomic storage of radio events happened during the execution of a command. + * + * Input: pCmd - Command the events belogn to. + * events - The radio events to be store within the context of the command. + * Return: none + */ +static void RF_cmdStoreEvents(RF_Cmd* pCmd, RF_EventMask events) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Store the events within the context of the command. */ + if (pCmd) + { + /* The field rfifg store the events for the next callback. + The field pastifg accumulates the events in case an + RF_pendCmd() API call happens. */ + pCmd->rfifg |= events; + pCmd->pastifg |= events; + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Reconfigure and restart a particular clock object. + * + * Input: clockObj - A pointer to a clock object. + * timeoutClockTicks - The timeout to be set in unit of clock ticks. + * Return: none + */ +static void RF_restartClockTimeout(ClockP_Handle clockHandle, uint32_t timeoutClockTicks) +{ + /* Ceil the value at minimum 1 clock tick. */ + timeoutClockTicks = MAX(timeoutClockTicks, 1); + + /* Reprogram the clock object. */ + ClockP_setTimeout(clockHandle, timeoutClockTicks); + ClockP_start(clockHandle); +} + +/* + * Calculate the delta time to an RF event including the overhead of powering up + * and down. + * + * Input: abstime - The timestamp the event will need to happen. + * nTotalPowerUpDuration - The duration we need to compensate with. + * Return: deltaTime - The time left until the RF core need to be trigged. + */ +static uint32_t RF_calculateDeltaTimeUs(uint32_t absTime, uint32_t nTotalPowerUpDuration) +{ + /* Local variables. */ + uint32_t deltaTimeUs; + + /* Read the timestamp to calculate difference from. */ + uint32_t currentTime = RF_getCurrentTime(); + + /* Calculate the difference with the current timestamp. */ + deltaTimeUs = UDIFF(currentTime, absTime); + deltaTimeUs /= RF_NUM_RAT_TICKS_IN_1_US; + + /* Check if delta time is greater than (powerup duration + power down duration) for a + power cycle, and is less than 3/4 of a RAT cycle (~17 minutes) */ + if ((deltaTimeUs > (int32_t)(nTotalPowerUpDuration + RF_DEFAULT_POWER_DOWN_TIME)) && + (deltaTimeUs <= RF_DISPATCH_MAX_TIME_US)) + { + /* Dispatch command in the future */ + return(MAX((deltaTimeUs - nTotalPowerUpDuration), 1)); + } + else + { + /* Dispatch immediately */ + return(0); + } +} + +/* + * Calculate the wakeup time of next command in the queue. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * conflict - true: compare to the first command which have TRIG_ABSTIME trigger type. + * false: compare to the first command in the queue + * pAbsCmd - Pointer to the first command which has an absolute start time. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_cmdDispatchTime(uint32_t* dispatchTimeClockTicks, bool conflict, RF_Cmd** pAbsCmd) +{ + /* By default, there is no command in the queue. */ + RF_Cmd* pCmd = NULL; + bool validTime = false; + + /* The input argument determines which command to use as a reference. This is to be able to + reuse the calculation for both power management and conflict resolution. */ + if (conflict == true) + { + /* Start from the beginning of queue. */ + RF_Cmd* pTempCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Walk the queue and find the first command contains an absolute start time. */ + while (pTempCmd) + { + /* Finish the search upon the first match. This assumes that commands with + absolute start times are in order. */ + if (pTempCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd = pTempCmd; + break; + } + else + { + /* Continue the search if no match. */ + pTempCmd = (RF_Cmd*)List_next((List_Elem*)pTempCmd); + } + } + } + else + { + /* The next command in the queue independently of its type determines the timing. */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + } + + /* Only recognizes TRIG_ABSTIME triggers, everything else gets dispatched immediately. */ + if (pCmd) + { + /* If there is at least one pending command, we can calculate a legit dispatch time. */ + validTime = true; + + /* Return with the command which we calculate the remained time against. */ + if (pAbsCmd) + { + *pAbsCmd = pCmd; + } + + /* If the start trigger is absolute, we can calculate the time difference. */ + if (pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + uint32_t nTotalDuration = 0; + + /* Calculate the sum of overhead it takes to start up and configure the RF core. */ + if (conflict == true) + { + nTotalDuration = pCmd->pClient->clientConfig.nPhySwitchingDuration + + pCmd->pClient->clientConfig.nPhySwitchingDurationMargin; + } + else + { + /* If radio wakes up to execute an FS command use nPowerUpDurationFs */ + if ((pCmd->pOp->commandNo == CMD_FS) || (pCmd->pOp->commandNo == CMD_FS_OFF)) + { + nTotalDuration = pCmd->pClient->clientConfig.nPowerUpDurationFs + + pCmd->pClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels); + } + else + { + nTotalDuration = pCmd->pClient->clientConfig.nPowerUpDuration + + pCmd->pClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels); + } + } + + /* Calculate the remained time until this absolute event. The calculation takes + into account the minimum power cycle time. */ + *dispatchTimeClockTicks = RF_calculateDeltaTimeUs(pCmd->startTime, nTotalDuration); + + /* Scale the value to clock ticks*/ + *dispatchTimeClockTicks /= ClockP_getSystemTickPeriod(); + } + else + { + /* Dispatch immediately. */ + *dispatchTimeClockTicks = 0; + } + } + else + { + /* This value will not be used. */ + *dispatchTimeClockTicks = 0; + } + + /* If the returned timestamp represents a valid dispatch time, return with true. */ + return(validTime); +} + +/* + * Determines if the RAT timer is running (clock is not gated) or not. + * This is used to determine if any RAT related command can be execured. + * + * Input: none + * Return: PWMCLK_EN_RAT - RAT timer is running. + * 0 - RAT timer is not running. + */ +static bool RF_ratIsRunning(void) +{ + /* Assume by default that the RAT is not available. */ + bool status = false; + + /* If the RF core power domain is ON, read the clock of the RAT. */ + if (HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDSTAT0) & PRCM_PDSTAT0_RFC_ON) + { + status = (bool)(HWREG(RFC_PWR_BASE + RFC_PWR_O_PWMCLKEN) & RFC_PWR_PWMCLKEN_RAT_M); + } + + /* Return with the status of RAT. */ + return(status); +} + +/* + * Allocate a RAT channel from the three slots available + * for the user. + * + * Input: ratChannel - Pointer to a user provided RF_RatHandle. + * Return: RF_RatChannel* - Pointer to the allocated channel if success. + * NULL - If failure. + */ +static RF_RatChannel* RF_ratAllocChannel(RF_RatHandle ratChannel) +{ + /* Walk the RAT channel indexes. */ + uint32_t i; + for (i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Calculate the bit representing this channel within the available channels. */ + uint32_t bitMask = (1 << i); + + /* Verify that no one is using this channel (from outside the scope of RF driver). */ + if (RF_ratModule.availableRatChannels & bitMask) + { + /* Mask the possible channels if a user handle is provided, otherwise find the + the first available channel. */ + if ((ratChannel == RF_RatChannelAny) || (ratChannel == i)) + { + /* Decode the fields of a channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If an available channel is found. */ + if (ratCh && (ratCh->status == RF_RatStatusIdle)) + { + /* Mark the channel as occupied. */ + RF_ratModule.availableRatChannels &= ~bitMask; + + /* Put the channel into pending state. */ + ratCh->status = RF_RatStatusPending; + ratCh->handle = i; + + /* Increment the counter of active channels. This is used to compensate the + power up time with the overhead of programming these channels. */ + RF_ratModule.numActiveChannels += 1; + + /* Return with a pointer to the channel. */ + return(ratCh); + } + } + } + } + + /* Return with an invalid channel pointer in case of error. */ + return(NULL); +} + +/* + * Free a given RAT channel. + * + * Input: ratCh - Pointer to a RAT channel in RF_ratModule. + * Return: none + */ +static void RF_ratFreeChannel(RF_RatChannel* ratCh) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If a valid pointer is provided */ + if (ratCh && ratCh->status) + { + /* Precalculate the contraint ID of this channel. */ + RF_PowerConstraintSrc powerConstraint = (RF_PowerConstraintSrc)(1 << ratCh->handle); + + /* If the RF core power domain is ON. */ + if (RF_ratIsRunning()) + { + /* Calculate the channel index based on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Disable the RAT channel interrupt source. */ + RFCHwIntDisable(ratChIntFlag); + RFCHwIntClear(ratChIntFlag); + } + + /* Reset the status of the channel. */ + ratCh->status = RF_RatStatusIdle; + ratCh->mode = RF_RatModeUndefined; + ratCh->pClient = NULL; + ratCh->pCb = NULL; + ratCh->chCmd = 0; + ratCh->ioCmd = 0; + + /* Mark the channel as available. */ + RF_ratModule.availableRatChannels |= (1 << ratCh->handle); + + /* Decrement the counter of active channels. To avoid underflow, check its value first. */ + if (RF_ratModule.numActiveChannels) + { + RF_ratModule.numActiveChannels -= 1; + } + + /* Notify the state machine that the RF core can be possibly powered down. */ + RF_powerConstraintRelease(powerConstraint); + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Returns with a pointer to a RAT channel based on it's handle. + * + * Input: ch - Channel handle. + * Return: ratCh - Pointer to a RAT channel in RF_ratModule. + */ +static RF_RatChannel* RF_ratGetChannel(uint8_t ch) +{ + /* Convert a valid index into a pointer of a RAT channel configuration. */ + if (ch < RF_RAT_CH_CNT) + { + return((RF_RatChannel*)&RF_ratModule.channel[ch]); + } + + /* Return with NULL in case of invalid input argument. */ + return(NULL); +} + +/* + * Suspend the running channels and potentially initiate a power down. + * + * Input: none + * Return: true - All RAT channel is suspended. + * false - Otherwise. + */ +static bool RF_ratReleaseChannels(void) +{ + /* Only try to release the RAT channels if there is no other dependencies set. */ + if (!RF_powerConstraintGet(RF_PowerConstraintCmdQ) && + !RF_powerConstraintGet(RF_PowerConstraintDisallow)) + { + /* Calculate if there is enough time to power down and up. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + /* If the next event is sufficiently far into the future. */ + if (!validTime || (validTime && dispatchTimeClockTicks)) + { + /* Avoid powering down the radio if there are callbacks to be served. The + SWI will try to access the RAT timer, which need to be powered. */ + if (RF_ratModule.pendingInt == 0U) + { + /* Suspend all RAT channels. */ + RF_ratSuspendChannels(); + + /* RAT channels were suspended. */ + return(true); + } + } + } + + /* RAT channels were not suspended. */ + return(false); +} + +/* + * Calculate the timeout of closest RAT event. + * + * Input: dispatchTimeClockTicks - Location where the calculated time is being stored. + * Return: validTime - Indicates if the returned time is valid. + */ +static bool RF_ratDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* By default, there is no RAT running. */ + bool validTime = false; + + /* Initialize the return value. */ + *dispatchTimeClockTicks = RF_DISPATCH_INFINIT_TIME; + + /* Iterate through the RAT containers and calculate the remained time until + the closest RAT event. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Use a local pointer to have easier access to member fields. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is either in PENDING or RUNNING state, meaning it is in use. */ + if (ratCh && ratCh->status) + { + /* There is at least one active channel, we can calculate a legit timestamp. */ + validTime = true; + + /* If there is at least one channel in Capture mode, we need to power + up immediately. */ + if (ratCh->mode == RF_RatModeCapture) + { + /* Use immediate timeout orcing the RF core to be powered up. */ + *dispatchTimeClockTicks = 0; + + /* No point to look to the other RAT channels.*/ + break; + } + else + { + /* Decode the compareTime field. */ + rfc_CMD_SET_RAT_CMP_t* cmd = (rfc_CMD_SET_RAT_CMP_t *)&ratCh->chCmd; + uint32_t compareTime = cmd->compareTime; + + /* Calculate the remained time until this RAT event. The calculation takes + into account the minimum power cycle time. */ + uint32_t deltaTimeUs = RF_calculateDeltaTimeUs(compareTime, + RF_currClient->clientConfig.nPowerUpDuration + + RF_currClient->clientConfig.nPowerUpDurationMargin + + (RF_RAT_COMPENSATION_TIME_US * RF_ratModule.numActiveChannels)); + + /* Scale the value to clock ticks. */ + uint32_t deltaTimeClockTicks = deltaTimeUs / ClockP_getSystemTickPeriod(); + + /* If this is the closest RAT event, update the timer. */ + if (deltaTimeClockTicks < (*dispatchTimeClockTicks)) + { + *dispatchTimeClockTicks = deltaTimeClockTicks; + } + } + } + } + + /* Return with true if the dispatchTime represents a valid timestamp. */ + return(validTime); +} + +/* + * Arms a given RAT channel. The mode of the channel will define which mode + * it is being configured to. The cmd variable contains the raw word to be + * sent to the RF core. + * + * Input: ratCh - Pointer to a RAT channel. + * Return: status - Status code based on the response of RF core. + * + */ +static RF_Stat RF_ratArmChannel(RF_RatChannel* ratCh) +{ + /* Local variable */ + RF_Stat status = RF_StatError; + + /* Only those channels can be programmed which are in pending state. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Calculate the channel interrupt flag on the handle. */ + uint32_t ratChIntFlag = (1 << (RFC_DBELL_RFHWIFG_RATCH5_BITN + ratCh->handle)); + + /* Clear and enable the interrupt source for that particular channel. */ + RFCHwIntClear(ratChIntFlag); + RFCHwIntEnable(ratChIntFlag); + + /* Set the power constraint on this channel to keep the RF core ON. */ + RF_powerConstraintSet((RF_PowerConstraintSrc)(1 << ratCh->handle)); + + /* Send the command to the RF core. */ + status = RF_executeDirectImmediateCmd((uint32_t)&ratCh->chCmd, NULL); + + /* If the channel configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + /* Send the IO command to the RF core if there is any configured. */ + if (ratCh->ioCmd) + { + status = RF_executeDirectImmediateCmd((uint32_t)ratCh->ioCmd, NULL); + } + + /* If both the channel and io configuration is succesfull. */ + if (status == RF_StatCmdDoneSuccess) + { + ratCh->status = RF_RatStatusRunning; + } + } + } + + /* Return with the status code. */ + return(status); +} + +/* + * Restarts any RAT channels which are in pending state at the moment of + * invoking this method. This is used to automatically restore the rat module + * right after the RF core is powered up. This is essential for power management. + * + * Input: none + * Return: none + * + */ +static void RF_ratRestartChannels(void) +{ + /* Iterate through the RAT containers and restore the channels + which were in running state before we entered Standby mode. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Convert the index to a pointer. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* If the channel is in pending state, program it. */ + if (ratCh && (ratCh->status == RF_RatStatusPending)) + { + /* Try to program the RAT channel. */ + RF_Stat status = RF_ratArmChannel(ratCh); + + /* Execute error handling if programming fails, i.e. due to past timestamp. + This is done in SWI context. */ + if (status != RF_StatCmdDoneSuccess) + { + /* Mark the event as an error by setting also a shadow bit. */ + RF_ratModule.pendingInt |= ((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << ratCh->handle); + + /* Post the SWI handler to serve the callback. */ + SwiP_or(&RF_swiHwObj, 0); + } + } + } +} + +/* + * Suspends any RAT channel which are in RUNNING state. + * This is used to force all RAT channels into pending state allowing the power + * management to power off the RF core power domain and resynchronize the RAT channels + * on next power up. + * + * Input: none + * Return: none + */ +static void RF_ratSuspendChannels(void) +{ + /* Iterate through the RAT containers and suspend the active channels. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + /* Set a pointer to the channel. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Only actively running channles can be suspended. */ + if (ratCh && ratCh->status) + { + /* Set the status to be suspended. */ + ratCh->status = RF_RatStatusPending; + + /* Clear the power constraint of this channel */ + RF_powerConstraintRelease((RF_PowerConstraintSrc)(1 << ratCh->handle)); + } + } +} + +/* + * Read the counter value from the RAT timer. + * + * Input: none + * Return: time - The value found in the RATCNT running register. + */ +static uint32_t RF_ratGetValue(void) +{ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCNT)); +} + +/* + * Read the channel value from the RAT timer. + * + * Input: ratHandle - The handle to the channel. + * Return: timeout - The value found in the RATCHxVAL register. + */ +static uint32_t RF_ratGetChannelValue(RF_RatHandle ratHandle) +{ + /* Read the channel value. */ + return(HWREG(RFC_RAT_BASE + RFC_RAT_O_RATCH5VAL + ratHandle * sizeof(uint32_t))); +} + +/* + * Generate a command which can be used to configure a RAT channel into COMPARE mode. + * + * Input: ratCh - Pointer to the channel. + * ratConfig - Configuration structure holding the channel setup. + * Return: none + */ +static void RF_ratGenerateChCmd(RF_RatChannel* ratCh, void* ratConfig) +{ + /* Generate a command based on the mode. */ + if (ratCh->mode == RF_RatModeCompare) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCompare* ratCompareConfig = (RF_RatConfigCompare*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CMP_t* pCmd = (rfc_CMD_SET_RAT_CMP_t*)&ratCh->chCmd; + + /* Populate the command structure properly. */ + pCmd->commandNo = CMD_SET_RAT_CMP; /* Instruct the RF core to use COMPARE mode. */ + pCmd->ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->compareTime = ratCompareConfig->timeout; /* Select the compare timeout. */ + } + else if (ratCh->mode == RF_RatModeCapture) + { + /* Local pointer to cast the configuration to the proper type. */ + RF_RatConfigCapture* ratCaptureConfig = (RF_RatConfigCapture*) ratConfig; + + /* Point a pointer to the generic command field within the channels context. */ + rfc_CMD_SET_RAT_CPT_t* pCmd = (rfc_CMD_SET_RAT_CPT_t*)&ratCh->chCmd; + + /* Calculate the direct command to be sent to the RF core.*/ + pCmd->commandNo = CMD_SET_RAT_CPT; /* Instruct the RF core to use CAPTURE mode. */ + pCmd->config.ratCh = RF_RAT_CH_LOWEST + ratCh->handle; /* Encode the selected channel number. */ + pCmd->config.inputSrc = ratCaptureConfig->source; /* Select the source to be captured. */ + pCmd->config.inputMode = ratCaptureConfig->captureMode; /* Select the mode of capture: raising, falling, etc*/ + pCmd->config.bRepeated = ratCaptureConfig->repeat; /* Select if we should re-arm the channel after a capture event. */ + } +} + +/* + * Generate a command which can be used to configure an IO for a particular RAT channel. + * + * Input: ratCh - Pointer to the channel. + * ioConfig - Configuration channel for the IO. + * Return: cmdToDoorbell - Return with the command structure. It is casted to uint32_t as it is + * stored in a generic variable. + */ +static void RF_ratGenerateIoCmd(RF_RatChannel* ratCh, RF_RatConfigOutput* ioConfig) +{ + /* Local variable. */ + uint32_t cmdToDoorbell = 0; + + /* If there is an IO configuration. */ + if (ioConfig) + { + cmdToDoorbell |= ioConfig->select << 2; + cmdToDoorbell |= ioConfig->mode << 5; + cmdToDoorbell |= (uint32_t)(RF_RAT_CH_LOWEST + ratCh->handle) << 8; + + cmdToDoorbell = (uint32_t)CMDR_DIR_CMD_2BYTE(CMD_SET_RAT_OUTPUT, cmdToDoorbell); + } + + /* Return with the raw command to be sent to the doorbell. */ + ratCh->ioCmd = cmdToDoorbell; +} + +/* + * Wrapper function to setup a RAT channel into the selected mode. + * + * Input: ratClient - Handle previously returned by RF_open(). + * ratMode - Identifies the mode the channel is being set up: RF_RatModeCompare or RF_RatModeCapture. + * ratCallback - Callback function to be registered to the RAT channel. + * ratChannel - Preferred channel to be allocated. If RF_RatChannelAny is provided, allocatethe first available channel. + * ratConfig - Configuration structure holding the setup of the particulare channel. + * ioConfig - Configuration strucutre of the assosiated GPO setup. + * Return: ratHandle - RF_RatHandle to the allocated channel. If allocation fails, RF_ALLOC_ERROR is returned. + */ +static RF_RatHandle RF_ratSetupChannel(RF_Handle ratClient, RF_RatMode ratMode, RF_RatCallback ratCallback, RF_RatHandle ratChannel, void* ratConfig, RF_RatConfigOutput* ioConfig) +{ + /* Return with an error. Either we couldn't allocate any RAT + channel, or the RAT module declined our configuration. */ + RF_RatHandle ratHandle = (RF_RatHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Find and allocate a RAT channel (if any is available) */ + RF_RatChannel* ratCh = RF_ratAllocChannel(ratChannel); + + /* If we could allocate a RAT channel */ + if (ratCh) + { + /* Populate the container. Use the default "do nothing" callback + if no user callback is provided and generate the command based + on the mode of the channel. */ + ratCh->pClient = ratClient; + ratCh->mode = ratMode; + ratCh->pCb = (RF_RatCallback)RF_defaultCallback; + RF_ratGenerateChCmd(ratCh, ratConfig); + RF_ratGenerateIoCmd(ratCh, ioConfig); + + /* If there is a user callback provided, override the default callback. */ + if (ratCallback) + { + ratCh->pCb = ratCallback; + } + + /* Decide which PHY should be used upon first start up. */ + if (RF_currClient == NULL) + { + RF_currClient = ratCh->pClient; + } + + /* Calculate the RAT/RTC timestamp to be used to wake the RF core. */ + RF_dispatchNextEvent(); + + /* Return with the handle upon success. */ + ratHandle = (RF_RatHandle)ratCh->handle; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with either an error OR a handle to a RAT channel. */ + return(ratHandle); +} + +/* + * Poll the RFACKIFG and clear the flag afterwards. This is used during the power up sequence + * of the RF core where interlaying processing is implemented. + * + * Input: none + * Return: none + */ +static void RF_dbellSyncOnAck(void) +{ + while (!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; +} + +/* + * Submit a command to the doorbell without blocking command execution. This is used during the + * power up sequence where the system CPU can continue with processing data while the RF core + * executes the submitted command. + * + * Input: rawCmd - The raw command to be written to the doorbell. This can be a pointer or a + * a direct/immediate command. + * Return: none + */ +static void RF_dbellSubmitCmdAsync(uint32_t rawCmd) +{ + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0; + HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = rawCmd; +} + +/* + * Wake up notification callback from the power driver. If the callback is from RF wakeup + * set constraint to let RF Driver control the XOSC switching else do nothing in the + * callback. + * + * Input: eventType - The type of event when the notification is invoked + * eventArg - Not used. + * clientArg - Not used. + * Return: Power_NOTIFYDONE + */ +static uint8_t RF_wakeupNotification(uint8_t eventType, uint32_t *eventArg, uint32_t *clientArg) +{ + /* Check if the callback is for wakeup from standby and if power up clock is running */ + if ((eventType == PowerCC26XX_AWAKE_STANDBY) && (ClockP_isActive(&RF_clkPowerUpObj))) + { + /* Calculate time (in us) until next trigger (assume next trigger is max ~70 min away) */ + uint32_t timeInUsUntilNextTrig = ClockP_getSystemTickPeriod() * ClockP_getTimeout(&RF_clkPowerUpObj); + + /* Check if the next trig time is close enough to the actual power up */ + if (timeInUsUntilNextTrig < RF_WAKEUP_DETECTION_WINDOW_IN_US) + { + /* Stop power up clock */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Setup RF Driver to do the XOSC_HF switching */ + Power_setConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + + /* Set variable to indicate RF Driver will do the XOSC_HF switching */ + RF_core.manualXoscHfSelect = true; + + /* Start the RF Core power up */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + + return(Power_NOTIFYDONE); +} + +/*-------------- Scheduler internal functions --------------------------------*/ + +/* + * Issue RF_EventRadioFree callback to the client. The callback is issued - + * 1. After pre-emption is complete + * 2. Dedicated request access period expires or released + * 3. command reject because of other high priority command running + * + * Input: src - Flag indicating the source of callback request. + * Return: none + */ +static void RF_issueRadioFreeCb(uint8_t src) +{ + /* Enter critical section*/ + uint32_t key = HwiP_disable(); + + /* Clear the reason why the callback is being invoked */ + RF_Sch.issueRadioFreeCbFlags &= ~src; + + /* Local variable */ + bool isReqAccessActive = false; + + /* If any of the clients has active request access, indicate it */ + if (RF_Sch.clientHnd[0]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[0]->state.clkReqAccess); + } + if (RF_Sch.clientHnd[1]) + { + isReqAccessActive |= ClockP_isActive(&RF_Sch.clientHnd[1]->state.clkReqAccess); + } + + /* If we cleared all the potential sources and there is no request access*/ + if ((RF_Sch.issueRadioFreeCbFlags == 0) && !isReqAccessActive) + { + /* If a valid client handle is provided through the global pointer */ + if (RF_Sch.clientHndRadioFreeCb && (RF_Sch.clientHndRadioFreeCb->clientConfig.nClientEventMask & RF_ClientEventRadioFree)) + { + /* Get a pointer to the client event callback */ + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_Sch.clientHndRadioFreeCb->clientConfig.pClientEventCb; + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoek the client event callback */ + pClientEventCb(RF_Sch.clientHndRadioFreeCb, RF_ClientEventRadioFree, NULL); + + /* Clear the client pointer in any case */ + RF_Sch.clientHndRadioFreeCb = NULL; + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } +} + +/* + * Decode how much time it will take to switch protocol/phy configuration. + * + * Input: prevCmd - The command switching from. + * nextCmd - The command switching to. + * Return: switchingTime - The time it takes to switch the PHY. + */ +static int32_t RF_getSwitchingTimeInUs(RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + int32_t switchingTime = 0; + + /* If otherCmd and newCmd are from different client then there is a switching time + related to moving between the two commands. */ + if (prevCmd->pClient != nextCmd->pClient) + { + switchingTime = nextCmd->pClient->clientConfig.nPhySwitchingDuration; + } + + /* Return the switching time related to moving between the two clients. */ + return(switchingTime); +} + +/* + * Check if new request can inserted between the previous and next command in the + * current queue. + * + * Input: newCmd - RF_Cmd pointer for the new command request + * prevCmd - RF_Cmd pointer for the previous cmd in the queue + * nextCmd - RF_Cmd pointer for the next cmd in the queue + * Return: true - If command can be inserted in the queue else + * false - Otherwise. + */ +static bool RF_verifyGap(RF_Cmd* newCmd, RF_Cmd* prevCmd, RF_Cmd* nextCmd) +{ + /* Initialize local variables. */ + bool insertNewCmdAfterPrev = prevCmd ? false : true; + bool insertNewCmdBeforeNext = nextCmd ? false : true; + int32_t deltaInUs = 0; + + /* Step 1 - The newCmd must have an endTime in order to be placed anywhere + else than the end. Or if there are no commands behind. */ + if ((newCmd) && (insertNewCmdBeforeNext || (newCmd->endType != RF_EndNotSpecified))) + { + /* If there is a prevCmd and it have an endTime, we could potentially + put the new command behind it. */ + if ((prevCmd) && (prevCmd->endType != RF_EndNotSpecified)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(newCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(prevCmd->endTime); + + /* Substract the switching time needed to move between prevCmd and newCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(prevCmd, newCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command */ + insertNewCmdAfterPrev = true; + } + } + + /* If there is a nextCmd, and it has an aboslute startTime, we could potentially put the new command in front of it. + If we already have evaluated that we can't be behind the prevCmd, there is no need to evalue this. */ + if ((insertNewCmdAfterPrev) && (nextCmd) && (nextCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + /* Take the start time of the command located later in the timeline. */ + deltaInUs = (int32_t)RF_convertRatTicksToUs(nextCmd->startTime); + + /* Substract the time earlier in the timeline. The result is the gap in between. */ + deltaInUs -= (int32_t)RF_convertRatTicksToUs(newCmd->endTime); + + /* Substract the switching time needed to move between newCmd and nextCmd. */ + deltaInUs -= RF_getSwitchingTimeInUs(newCmd, nextCmd); + + /* Handle timer overflow with the assumption that the difference between the startTime + and endTime is less than ~8 min. */ + if ((deltaInUs < ((int32_t)RF_DISPATCH_MAX_TIME_WRAPAROUND_US)) || (deltaInUs > 0)) + { + /* Allow insertion if startTime has wrapped around or no wrap around and we can insert the command. */ + insertNewCmdBeforeNext = true; + } + } + } + + /* Return with true if the command can be inserted into the queue (both before or after criteria met). */ + return(insertNewCmdBeforeNext & insertNewCmdAfterPrev); +} + +/* + * Check what scheduling strategy that can be used to schedule the requesting command. + * + * Input: newCmd - Points to the newly submitted radio command, + * pCmdBg - Points to the active background command (if any). + * pCmdFg - Points to the active foreground command (if any). + * pPendQueue - Points to the queue holding the commands to be executed. + * pDoneQueue - Points to the queue holding the commands which has been exeuted. + * pInsertLocation - Reference to command which the newCmd shall be inserted behind. + * + * Return: RF_ScheduleStatus - Returning status containing the scheduling decision. + */ +static RF_ScheduleStatus RF_howToSchedule(RF_Cmd* newCmd, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, RF_Cmd** pInsertLocation) +{ + /* By default, reject any new request. */ + volatile RF_ScheduleStatus status = RF_ScheduleStatusError; + + /* Typecast the arguments to RF commands. */ + RF_Cmd* pHead = (RF_Cmd*)List_head(pPendQueue); + + /* Load list head as the start point of the iterator. */ + RF_Cmd* it = pHead; + + /* Step 1 - Check if new command can be inserted based on the timing information + at the top of the pending queue. */ + if (RF_verifyGap(newCmd, pCmdBg, pHead)) + { + /* Indicate that the command was put on the top of the queue.ss */ + status = RF_ScheduleStatusTop; + } + + /* Step 2 - Check if new command can be inserted based on the timing information + in the middle/end of the pending queue. This require the new command + to have an ABSOLUTE startTrigger type. */ + if ((status == RF_ScheduleStatusError) && (newCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + /* Walk the queue.*/ + while (it) + { + /* Check if we can insert the new command in between. */ + if (RF_verifyGap(newCmd, it, (RF_Cmd*)List_next((List_Elem*)it))) + { + /* Set the return value that the new command should be + inserted in between it and it->pNext. */ + status = RF_ScheduleStatusMiddle; + break; + } + else + { + it = (RF_Cmd*)List_next((List_Elem*)it); + } + } + } + + /* Step 3 - If step 1) or 2) fails, reject or append the command to the end of the queue + based on the allowDelay argument of RF_scheduleCmd() API call. */ + if ((status == RF_ScheduleStatusError) && (newCmd->allowDelay)) + { + status = RF_ScheduleStatusTail; + } + + /* Set pInsertLocation to mark where to insert the new command. */ + *pInsertLocation = it; + + /* Return with the scheduling method. */ + return(status); +} + +/** + * Sorts and adds command to the RF driver internal command queue. + * + * Input: pCmdNew - Pointer to the command to be submitted. + * pCmdBg - Running background command. + * pCmdFg - Running foreground command. + * pPendQueue - Pointer to the head structure of pend queue. + * pDoneQueue - Pointer to the head structure of done queue. + * Return: RF_ScheduleStatus - Identifies the success or failure of enquing. + */ +RF_ScheduleStatus RF_defaultSubmitPolicy(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue) +{ + /* Local pointer to a command which will be used if insertition + is selected as a method. */ + RF_Cmd* pInsertLocation = NULL; + + /* Check the method how the new command should be scheduled. */ + RF_ScheduleStatus status = RF_howToSchedule(pCmdNew, pCmdBg, pCmdFg, pPendQueue, pDoneQueue, &pInsertLocation); + + /* Step 1 - If the new command is placed to the top of the pend queue. */ + if (status == RF_ScheduleStatusTop) + { + /* Insert command at the beginning of the queue */ + List_putHead(pPendQueue, (List_Elem*)pCmdNew); + } + + /* Step 2 - If the new command is inserted behind a particular command. */ + if (status == RF_ScheduleStatusMiddle) + { + /* Insert command between pInsertLocation and pInsertLocation->pNext. */ + if (List_next((List_Elem*)pInsertLocation)) + { + /* Insert command before pInsertLocation->next. */ + List_insert(pPendQueue, (List_Elem*)pCmdNew, List_next((List_Elem*)pInsertLocation)); + } + else + { + /* Append command to the end of the queue (if next does not exist). */ + List_put(pPendQueue, (List_Elem*)pCmdNew); + } + } + + /* Step 3 - Append command to the end of the queue. */ + if (status == RF_ScheduleStatusTail) + { + List_put(pPendQueue, (List_Elem*)pCmdNew); + } + + /* Return command with the method we used to schedule the command. + Might be RF_ScheduleStatusError if none of the above rules applied. */ + return(status); +} + +/** + * Sorts and adds command to the RF driver internal command queue. + * + * Input: pCmdBg - Running background command. + * pCmdFg - Running foreground command. + * pPendQueue - Pointer to the head structure of pend queue. + * pDoneQueue - Pointer to the head structure of done queue. + * bConflict - Whether the incoming command conflicts with ongoing activity. + * conflictCmd - Pointer to the command that conflicts with ongoing. + * Return: RF_ScheduleStatus - Identifies the success or failure of enquing. + */ +RF_ExecuteAction RF_defaultExecutionPolicy(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue, bool bConflict, RF_Cmd* conflictCmd) +{ + return(RF_ExecuteActionNone); +} + +/* + * Execute RF power down sequence. + * + * Input: none + * Return: none + */ +static void RF_corePowerDown(void) +{ + /* Local variables to calculate active time in current window. */ + uint32_t deltaTimeInUs = 0; + + /* Disable all CPE and HW interrupts as we are about to power down the core. + Clearing is not important as content will be lost anyway. */ + RFCCpeIntDisable(~0); + RFCHwIntDisable(~0); + + /* Remap HWI to the startup function (preparing for next wake up) */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0PowerFsm, (uintptr_t)NULL); + + /* Take wake up timestamp and the current timestamp */ + uint32_t rtcTimestampB = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Find the radio core active delta time since the last power up. */ + deltaTimeInUs = UDIFF(RF_rtcTimestampA, rtcTimestampB); + deltaTimeInUs >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Accumulate the delta time with the previous active time windows. Avoid overflow. */ + RF_core.activeTimeUs = ADD(RF_core.activeTimeUs, deltaTimeInUs); + + /* Decide whether to send the CMD_SYNC_STOP_RAT command. If this is first power down (.init) or active time (activeTimeInUs) + is longer than the time that can cause maximum allowed error between RAT and RTC clocks. Yielding will automatically fulfill + the latter. */ + if (!(RF_core.init) || + (RF_core.activeTimeUs > (RF_errTolValInUs << RF_DEFAULT_COMB_XTAL_DRIFT_BITS_SHIFT))) + { + /* Stop and synchronize the RAT if it is running */ + if (RF_ratIsRunning()) + { + /* Setup RAT_SYNC command to follow powerdown. */ + RF_ratSyncCmd.stop.commandNo = CMD_SYNC_STOP_RAT; + RF_ratSyncCmd.stop.status = IDLE; + RF_ratSyncCmd.stop.condition.rule = COND_NEVER; + RF_ratSyncCmd.stop.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.stop.pNextOp = NULL; + + /* Send RAT Stop command and synchronously wait until it run. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.stop); + while (!(RF_ratSyncCmd.stop.status & RF_CMD_TERMINATED)); + } + + /* The RF core is now initialized and RAT is synchronized. */ + RF_core.init = true; + RF_core.activeTimeUs = 0; + } + + /* Turn off Synth */ + RFCSynthPowerDown(); + + /* Turn off the RF core by gating its clock. This is a quick way to have it shut off. */ + RFCClockDisable(); +} + +/*-------------- Power constraints internal functions ------------------------*/ + +/* + * Set RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintSet(RF_PowerConstraintSrc src) +{ + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Set constraint based on source */ + RF_powerConstraint |= src; + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * Release RF power constraints. + * + * Input: src - RF_PowerConstraintSrc (Source: Queue or RAT) + * Return: none + */ +void RF_powerConstraintRelease(RF_PowerConstraintSrc src) +{ + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Release this constraint. */ + RF_powerConstraint &= ~src; + + /* Check if all constraints are clear. */ + if (!(RF_powerConstraint & RF_PowerConstraintCmdQ)) + { + /* Initiate power down if the above criterion is met. + The RAT timer though might will prevent us to proceed. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerDown); + } + + /* Exit critical section. */ + HwiP_restore(key); +} + +/* + * Get RF power constraints. + * + * Input: src - Mask of constraints we requesting + * Return: Bitwise-OR of the power constraints set and the input argument + */ +RF_PowerConstraintSrc RF_powerConstraintGet(RF_PowerConstraintSrc src) +{ + /* Set constraint based on source */ + return((RF_PowerConstraintSrc)(RF_powerConstraint & (uint8_t)src)); +} + +/* + * It calculates and returns the closest RF event in time if any. + * + * Calling context: Hwi, Swi + * + * Input: dispatchTime - pointer to a container where the calculated time can be returned + * Return: ticks - If command is far away in future. + * 0 - If command is too close and should be scheduled now. + */ +static bool RF_calculateDispatchTime(uint32_t* dispatchTimeClockTicks) +{ + /* Local variables. */ + uint32_t deltaTimeCmdClockTicks; + uint32_t deltaTimeRatClockTicks; + + /* Initialize return value. */ + *dispatchTimeClockTicks = 0; + + /* Calculate the timestamp of the next command in the command queue. */ + bool validCmdTime = RF_cmdDispatchTime(&deltaTimeCmdClockTicks, false, NULL); + + /* If any of the RAT timers expire before the command should be dispatched, + reprogram the power up clock to the RAT event instead. */ + bool validRatTime = RF_ratDispatchTime(&deltaTimeRatClockTicks); + + if (validCmdTime && validRatTime) + { + /* Determine if command execution or RAT event comes first. */ + *dispatchTimeClockTicks = MIN(deltaTimeCmdClockTicks, deltaTimeRatClockTicks); + } + else if (validCmdTime) + { + /* Command queue determines the next event. */ + *dispatchTimeClockTicks = deltaTimeCmdClockTicks; + } + else if (validRatTime) + { + /* RAT timer determines the next event. */ + *dispatchTimeClockTicks = deltaTimeRatClockTicks; + } + + /* If any of them valid, return with true indicating a valid dispatch time. */ + return(validCmdTime || validRatTime); +} + +/* + * Dispatch the closest event generated either by a command or the RAT timer. + * If the RF core is powered, it triggs the HWI to execute the dispatcher. + * If the RF core is not powered, it decides if it should be powered ON immediately, or + * the execution can be deferred to a later timestamp. In the latter case, the RTC is used to keep + * track of proper timing. + * + * Input: none + * Return: status - Status of the command execution. + * + */ +static void RF_dispatchNextEvent(void) +{ + if (RF_core.status == RF_CoreStatusActive) + { + /* Kick the HWI to dispatch the next pending event. */ + HwiP_post(INT_RFC_CPE_0); + } + else if ((RF_core.status == RF_CoreStatusPoweringUp) || + (RF_core.status == RF_CoreStatusPhySwitching)) + { + /* Do nothing. We will dispatch the next event at the end + of power-up/phy-switching sequence naturally. */ + } + else + { + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Calculate dispatch time. */ + uint32_t dispatchTimeClockTicks; + bool validTime = RF_calculateDispatchTime(&dispatchTimeClockTicks); + + if (validTime) + { + /* Decide whether the command should be dispatched. */ + if (dispatchTimeClockTicks) + { + /* Dispatch command in the future. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + } + else + { + /* Dispatch the event immediately. Clock is not needed anymore. */ + ClockP_stop(&RF_clkPowerUpObj); + + /* Initiate powering up the RF core. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } + } + else + { + /* There is no event to be dispatched. */ + ClockP_stop(&RF_clkPowerUpObj); + } + + /* Exit critical section. */ + HwiP_restore(key); + } +} + +/* + * Update the cached FS command within the client's context. + * + * Calling context: Hwi, Swi + * + * Input: pCmd - Pointer to radio operation command. + * Return: none + */ +static void RF_cacheFsCmd(RF_Cmd* pCmd) +{ + /* Upper limit of the number of operations in a chain */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain */ + RF_Op* pOp = pCmd->pOp; + while (pOp && nCmdChainMax) + { + /* If the operation is a CMD_FS or CMD_FS_OFF */ + if ((pOp->commandNo == CMD_FS) || (pOp->commandNo == CMD_FS_OFF)) + { + /* Create a copy of the first CMD_FS command (or CMD_FS_OFF) for later power up */ + memcpy(&pCmd->pClient->state.mode_state.cmdFs, pOp, sizeof(pCmd->pClient->state.mode_state.cmdFs)); + break; + } + + /* Step the chain */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops) */ + --nCmdChainMax; + } +} + +/* + * Find the last radio operation within a chain. + * + * Calling context: Task, Hwi, Swi + * + * Input: pOp - Pointer to the first radio operation. + * Return: RF_Op* - Pointer to the last radio operation. + */ +static RF_Op* RF_findEndOfChain(RF_Op* pOp) +{ + /* Upper limit of the number of operations in a chain. */ + uint8_t nCmdChainMax = RF_MAX_CHAIN_CMD_LEN; + + /* Traverse the chain. */ + while (pOp->pNextOp && nCmdChainMax) + { + /* Step the chain. */ + pOp = pOp->pNextOp; + + /* Avoid infinit loop (in case of closed loops). */ + --nCmdChainMax; + } + + /* Return with the last radio operation. */ + return(pOp); +} + +/* + * Verify if the given command is a setup command. + * + * Calling context: Hwi, Swi + * + * Input: pOp - Pointer to radio operation. + * Return: true - The given command is a setup command. + * false - The given command is not a setup command. + */ +static bool RF_isRadioSetup(RF_Op* pOp) +{ + /* Verify the command ID against the known setup commands. */ + switch(pOp->commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* The given radio operation is indead a setup command. */ + return(true); + default: + /* Do nothing. */ + return(false); + } +} + +/* + * Ensure that the setup command is properly initialized. + * + * Input: handle - Pointer to the client. + * Return: None + */ +static void RF_initRadioSetup(RF_Handle handle) +{ + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + bool tx20FeatureAvailable = false; + bool update = handle->clientConfig.bUpdateSetup; + + /* Decode the setup command. */ + RF_RadioSetup* radioSetup = handle->clientConfig.pRadioSetup; + radioSetup->common.status = IDLE; + + /* Adjust the setup command if needed. */ + switch (radioSetup->common.commandNo) + { + case (CMD_RADIO_SETUP): + case (CMD_BLE5_RADIO_SETUP): + /* Configure that the frequency synthetizer should be powered up */ + radioSetup->common.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->common.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + + case (CMD_PROP_RADIO_SETUP): + case (CMD_PROP_RADIO_DIV_SETUP): + /* Configure that the frequency synthetizer should be powered ON */ + radioSetup->prop.config.bNoFsPowerUp = 0; + + /* If requested, also change the analog configuration during power up */ + if (update) + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_UPDATE; + } + else + { + radioSetup->prop.config.analogCfgMode = RF_SETUP_ANALOGCFG_NOUPDATE; + } + break; + default: + break; + } + + /* Clear the update request flag as it was handled by now. */ + handle->clientConfig.bUpdateSetup = false; + + /* Decode if High Gain PA is available. */ + tx20FeatureAvailable = RF_decodeOverridePointers(radioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Ensure that overrides are in sync with the selected PA. */ + if (tx20FeatureAvailable && (*pTxPower == RF_TX20_ENABLED)) + { + /* Attach the High Gain overrides. It does nothing if the extra overrides are NULL. */ + RF_attachOverrides(pRegOverride, pRegOverrideTx20); + } + else + { + /* Detach the High Gain overrides. It does nothing if it is not present. */ + RF_detachOverrides(pRegOverride, pRegOverrideTx20); + } + + /* Perform Software Temperature Controlled Crystal Oscillator compensation (SW TCXO), if enabled */ + if(pfnUpdateHposcOverride != NULL) + { + pfnUpdateHposcOverride(pRegOverride); + } +} + +/* + * Submit the pending command to the RF Core. + * + * Input: none + * Return: none + */ +static void RF_dispatchNextCmd(void) +{ + bool doDispatchNow = false; + RF_Cmd* pConflictCmd = NULL; + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + bool validTime = false; + uint32_t dispatchTimeClockTicks = 0; + + /* Decide whether to schedule the next command or not. */ + if (pNextCmd) + { + /* Either no commands are active, and we will execute */ + if (NULL == RF_cmdQ.pCurrCmdFg && NULL == RF_cmdQ.pCurrCmdBg) + { + doDispatchNow = true; + } + /* Or the current client wants to execute in the foreground on top of a background command */ + else if (RF_cmdQ.pCurrCmdBg + && (RF_cmdQ.pCurrCmdBg->pClient == pNextCmd->pClient) + && (pNextCmd->flags & RF_CMD_FG_CMD_FLAG) + && (NULL == RF_cmdQ.pCurrCmdFg)) + { + /* Try to execute the foreground command. */ + doDispatchNow = true; + + /* Be sure that the background command is started within the RF core. + This is to avoid race condition. */ + while ((RF_cmdQ.pCurrCmdBg->pOp->status == IDLE) || + (RF_cmdQ.pCurrCmdBg->pOp->status == PENDING)); + } + /* Or there is conflict. */ + else + { + /* By default let current command finish. */ + doDispatchNow = false; + } + } + else + { + /* There is nothing to do, serve the last callbacks. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* + * Calculate the timestamp of the next command in the command queue. + * `conflict` parameter (here opposite of doDistpatch) implicitly used to determine margin needed to execute incoming command. + */ + if (pNextCmd && (validTime = RF_cmdDispatchTime(&dispatchTimeClockTicks, !doDispatchNow, &pConflictCmd))) + { + /* If there is a conflict, but there is time left */ + if (!doDispatchNow && dispatchTimeClockTicks > 0) + { + /* The conflict is in the future, and might resolve naturally. + Revisit the issue again before the execution should start. */ + RF_restartClockTimeout(&RF_clkPowerUpObj, dispatchTimeClockTicks); + + /* Set pNext to NULL to avoid calling the hook until we revisit. */ + pNextCmd = NULL; + } + } + + /* Invoke the registered hook to get a final decision if there is still one to be made */ + if(pNextCmd && RFCC26XX_schedulerPolicy.executeHook && validTime && (0 == dispatchTimeClockTicks)) + { + /* Invoke the conflit hook to determine what action we shall take. */ + RF_ExecuteAction action = + RFCC26XX_schedulerPolicy.executeHook(RF_cmdQ.pCurrCmdBg, + RF_cmdQ.pCurrCmdFg, + &RF_cmdQ.pPend, + &RF_cmdQ.pDone, + !doDispatchNow, + pConflictCmd); + + switch (action) + { + case RF_ExecuteActionAbortOngoing: + { + RF_abortCmd(RF_cmdQ.pCurrCmdBg->pClient, RF_cmdQ.pCurrCmdBg->ch, false, true, true); + /* Do not dispatch now, wait for abort to complete, then reschedule */ + doDispatchNow = false; + } + break; + + case RF_ExecuteActionRejectIncoming: + { + RF_Cmd *abortCmd = pConflictCmd ? pConflictCmd : pNextCmd; + RF_abortCmd(abortCmd->pClient, abortCmd->ch, false, false, true); + /* Do not dispatch now, wait for abort to complete, then reschedule */ + doDispatchNow = false; + } + break; + + case RF_ExecuteActionNone: + default: + { + /* + * Ignore command if conflict, and pick it up after current finishes. + * If no conflict, dispatch. + */ + ; + } + break; + } + } + + /* We need to evaluate and handle the next command. Check pointer for static analysis. */ + if (doDispatchNow && pNextCmd) + { + if (pNextCmd->pClient != RF_currClient) + { + /* We need to change radio client, signal to FSM. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventInitChangePhy); + } + else + { + /* Dispatch command in the future */ + if (validTime && dispatchTimeClockTicks && !RF_cmdQ.pCurrCmdBg && !RF_cmdQ.pCurrCmdFg) + { + /* Command sufficiently far into future that it shouldn't be dispatched yet + Release RF power constraint and potentially power down radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* Set power constraint on the command queue, since there is now a running command. */ + RF_powerConstraintSet(RF_PowerConstraintCmdQ); + + /* Move the command from the pending queue to the current command. */ + if (pNextCmd->flags & RF_CMD_FG_CMD_FLAG) + { + RF_cmdQ.pCurrCmdFg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + else + { + RF_cmdQ.pCurrCmdBg = (RF_Cmd*)List_get(&RF_cmdQ.pPend); + } + + /* Clear and enable the requested interrupt sources of the command. */ + RFCCpeIntClear((uint32_t) (pNextCmd->bmEvent)); + RFCCpeIntEnable((uint32_t)(pNextCmd->bmEvent)); + RFCHwIntClear((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + RFCHwIntEnable((uint32_t) (pNextCmd->bmEvent >> RF_SHIFT_32_BITS)); + + /* Decode the radio operation itself. */ + RF_Op* pOp = (RF_Op*)pNextCmd->pOp; + + /* Invoke global callback to indicate start of command chain */ + RF_invokeGlobalCallback(RF_GlobalEventCmdStart, (void*)pNextCmd); + + /* Send the radio operation to the RF core. */ + RFCDoorbellSendTo((uint32_t)pOp); + + /* If the command is a new setup command, notify the board file. */ + if (RF_isRadioSetup(pOp)) + { + /* Invoke the global callback if the setup command changed. This is needed to + adjust the front-end configuration according to the new PHY. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pOp); + } + + /* Check the pending queue for any foreground command (IEEE 15.4 mode) */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventRunScheduler); + } + } + } +} + +/* + * Check if there was an error with the synth while running CMD_FS + * error callback is not issued in this function. + * + * Input: none + * Return: true - If there was an error. + * false - If there was no error. + */ +static bool RF_checkCmdFsError(void) +{ + /* Take the handle of the current client */ + RF_Handle pObj = RF_currClient; + + /* Find the FS command stored in the context of the client */ + RF_Op *tmp1 = (RF_Op*)&pObj->clientConfig.pRadioSetup->prop; + while (tmp1->pNextOp && tmp1->pNextOp != (RF_Op*)&pObj->state.mode_state.cmdFs) + { + tmp1 = tmp1->pNextOp; + } + + /* Evaluate if the FS command succeeded */ + if ((tmp1->condition.rule == COND_ALWAYS) && + (pObj->state.mode_state.cmdFs.status == ERROR_SYNTH_PROG)) + { + /* CMD_FS completed with error so return true */ + return(true); + } + else + { + /* There is no synth error so return false */ + return(false); + } +} + +/* + * RF HW ISR when radio is active. + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiHw(uintptr_t a) +{ + /* Prepare a direct command */ + RF_Cmd* pCmd = RF_cmdQ.pCurrCmdBg; + + /* Read and clear the interrupt flags */ + uint32_t rfchwifg = RFCHwIntGetAndClear(RF_HW_INT_CPE_MASK | RF_HW_INT_RAT_CH_MASK); + uint32_t rfchwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_CPE_MASK; + uint32_t rathwien = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) & RF_HW_INT_RAT_CH_MASK; + + if (rfchwifg & rfchwien) + { + /* Post SWI_FSM if MODEM_SOFT event occured and the interrupt was enabled */ + if (pCmd) + { + /* Store the command which callback need to be served */ + RF_cmdQ.pCurrCmdCb = pCmd; + + /* Decode the event numeber. */ + RF_EventMask events = ((RF_EventMask)(rfchwifg & rfchwien) << RF_SHIFT_32_BITS); + + /* Store the events within the context of the command for the callback. */ + RF_cmdStoreEvents(pCmd, events); + + /* Trig the state machine to handle this event */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventCpeInt); + } + } + + /* Post the SWI_HW if any RAT channel event occured */ + if (rfchwifg & rathwien) + { + /* Store the channel which cause the interrupt */ + RF_ratModule.pendingInt |= (rfchwifg & rathwien) >> RFC_DBELL_RFHWIFG_RATCH5_BITN; + + /* Post the swi to handle its callback */ + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * Software interrupt handler which servers Radio Timer (RAT) related events. + * + * Input: a - Generic argument. Not used. + * b - Generic argument. Not used. + * Return: none + */ +static void RF_swiHw(uintptr_t a, uintptr_t b) +{ + /* Local variable */ + bool error = false; + + /* If the interrupt was trigged due to one of the RAT channels. */ + if (RF_ratModule.pendingInt) + { + /* Process lower channel first and allow multiple interrupt flags to be processed sequentially. */ + uint32_t i; + for(i = 0; i < RF_RAT_CH_CNT; i++) + { + if (RF_ratModule.pendingInt & (RF_RAT_INTERRUPT_BASE_INDEX << i)) + { + /* If there is also a bit indicating that the interrupt is due to an error. */ + if (RF_ratModule.pendingInt & (RF_RAT_ERROR_BASE_INDEX << i)) + { + error = true; + } + + /* Enter critical section. */ + uint32_t key= HwiP_disable(); + + /* Atomic read-modify-write instruction of the interrupt flags. + Knowing that this is the only place when such a flag can be cleared, it is safe to only guard this + operation. Additional flags (which have been raised in the meantime) will be reserved and served in the + next iteration. */ + RF_ratModule.pendingInt &= ~((RF_RAT_INTERRUPT_BASE_INDEX | RF_RAT_ERROR_BASE_INDEX) << i); + + /* Exit critical section. */ + HwiP_restore(key); + + /* Convert the channel index to a pointer of rat configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(i); + + /* Serve the interrupt if it is from an active channel. This is to avoid decoding function + pointers from invalid containers due to fantom interrupts. */ + if (ratCh && ratCh->status) + { + /* Read the channel counter from the RAT timer. In capture mode this is the captured value, + in compare mode this is the compare timestamp.*/ + uint32_t compareCaptureValue = RF_ratGetChannelValue(ratCh->handle); + + /* Temporarily store the callback handler and the channel offset. + This is necessary in order to be able to free and reallocate the + same channel within the context of the callback itself. */ + RF_Handle ratClient = (RF_Handle) ratCh->pClient; + RF_RatHandle ratHandle = (RF_CmdHandle) ratCh->handle; + RF_RatCallback ratCallback = (RF_RatCallback) ratCh->pCb; + + /* Only free the channel if it is NOT in repeated capture mode, or an error occured. */ + if (error || !(ratCh->mode == RF_RatModeCapture) || !(ratCh->chCmd & RF_RAT_CAPTURE_REPEAT_MODE)) + { + /* Free RAT channel. If this is the last channel, it might delay with 1 LF edge to + calculate the next wake up event. */ + RF_ratFreeChannel(ratCh); + } + + /* Serve the user callback with Error or Compare/Capture Event. */ + if (error) + { + ratCallback(ratClient, ratHandle, RF_EventError, 0); + } + else + { + ratCallback(ratClient, ratHandle, RF_EventRatCh, compareCaptureValue); + } + } + + /* Only serve one channel at a time. */ + break; + } + } + } + + /* Repost the SWI again if multiple interrupt flags are still set. */ + if (RF_ratModule.pendingInt) + { + SwiP_or(&RF_swiHwObj, 0); + } +} + +/* + * RF CPE0 ISR when radio is active. Assume that all IRQs relevant to command + * dispatcher are mapped here. Furthermore, assume that there is no need for + * critical sections here (i.e. that this ISR has higher priority than + * any HWI calling a RF API function or that HWIs can't call the RF API). + * + * Input: a - Not used. + * Return: none + */ +static void RF_hwiCpe0Active(uintptr_t a) +{ + /* Local variables. */ + RF_Cmd* volatile* ppActiveCmd = NULL; + RF_Cmd* volatile* activeCmd[2] = {&RF_cmdQ.pCurrCmdBg, &RF_cmdQ.pCurrCmdFg}; + uint32_t rfcpeifgMask = 0; + uint32_t rfcpeifg = 0; + uint32_t nextEvent = 0; + + /* Handle PA switching. */ + if (RFCCpeIntGetAndClear(RF_EventPaChanged)) + { + /* The PA was changed during a chain of radio operation. We need to extract the current configuration + and propagate it back to the setup command. This is to reserve the change after power cycle. */ + RF_extractPaConfiguration(RF_currClient); + + /* Invoke the board file to reconfigure the external front-end configuration. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*) RF_currClient->clientConfig.pRadioSetup); + } + + /* Iterate through the possible active commands. */ + uint32_t i; + for(i = 0; i < sizeof(activeCmd)/sizeof(uint32_t); i++) + { + /* Decode the active command. */ + ppActiveCmd = activeCmd[i]; + + /* If there was a command running (handles both foreground and background context). */ + if (*ppActiveCmd) + { + /* Decode the events the active command subscribed to. */ + rfcpeifgMask = (*ppActiveCmd)->bmEvent; + + /* Read the interrupt flags which belong to the active command (including the mandatory termination events). */ + rfcpeifg = RFCCpeIntGetAndClear(rfcpeifgMask); + + /* Save the events happened and to be passed to the callback. */ + RF_cmdStoreEvents((*ppActiveCmd), rfcpeifg); + + /* Look for termination events. */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + /* Disable interrupt sources which were subsribed by the command. Since the LAST_CMD_DONE is + is shared with the state machine, it cannot be disabled. */ + RFCCpeIntDisable((uint32_t)((*ppActiveCmd)->bmEvent & ~(RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M | RFC_DBELL_RFCPEIEN_IRQ14_M))); + RFCHwIntDisable((uint32_t) ((*ppActiveCmd)->bmEvent >> RF_SHIFT_32_BITS)); + + /* Invoke global callback to indicate end of command chain */ + RF_invokeGlobalCallback(RF_GlobalEventCmdStop, (void*)(*ppActiveCmd)); + + /* Move active command to done queue. */ + List_put(&RF_cmdQ.pDone, (List_Elem*)(*ppActiveCmd)); + + /* Retire the command, it is not running anymore. */ + (*ppActiveCmd) = NULL; + + /* We will invoke the callback and deallocate the command. */ + nextEvent |= RF_FsmEventLastCommandDone; + } + else if (rfcpeifg) + { + /* The interrupt is just an ordinary event without termination. */ + RF_cmdQ.pCurrCmdCb = (*ppActiveCmd); + + /* We will just invoke the callback. */ + nextEvent |= RF_FsmEventCpeInt; + } + } + } + + /* Post SWI to handle registered callbacks if there is any. */ + if (nextEvent) + { + SwiP_or(&RF_swiFsmObj, nextEvent); + } + + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next pending command if exists. */ + RF_dispatchNextCmd(); +} + +/* + * Temperature limit notification function. + */ +static void RF_hposcRfCompensateFxn(int16_t currentTemperature, + int16_t thresholdTemperature, + uintptr_t clientArg, + Temperature_NotifyObj *NotifyObj) +{ + int32_t relFreqOffset; + int16_t relFreqOffsetConverted; + int_fast16_t status; + + /* Check if HPOSC frequency offset has changed */ + relFreqOffset = OSC_HPOSCRelativeFrequencyOffsetGet(currentTemperature); + if (relFreqOffset != RF_currentHposcFreqOffset) + { + /* Frequency offset has changed. Compensation is required */ + RF_currentHposcFreqOffset = relFreqOffset; + relFreqOffsetConverted = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(relFreqOffset); + + /* Check if radio is powered */ + if ((RF_core.status == RF_CoreStatusActive) || (RF_core.status == RF_CoreStatusPhySwitching)) + { + /* Radio is powered. Check if any actively running command */ + if (RF_cmdQ.pCurrCmdBg || RF_cmdQ.pCurrCmdFg) + { + /* Command is running. Abort command and assure that both RF_EventCmdStopped and RF_EventCmdPreempt rf events are set */ + RF_abortCmd(RF_cmdQ.pCurrCmdBg->pClient, RF_cmdQ.pCurrCmdBg->ch, true, false, true); + } + + /* Update RFCore with the HPOSC frequency offset */ + RF_runDirectImmediateCmd(RF_currClient, CMDR_DIR_CMD_2BYTE(CMD_UPDATE_HPOSC_FREQ, relFreqOffsetConverted), NULL); + } + } + + /* Register the notification again with updated thresholds */ + status = Temperature_registerNotifyRange(NotifyObj, + currentTemperature + RF_TEMP_LIMIT_3_DEGREES_CELSIUS, + currentTemperature - RF_TEMP_LIMIT_3_DEGREES_CELSIUS, + RF_hposcRfCompensateFxn, + (uintptr_t)NULL); + + if (status != Temperature_STATUS_SUCCESS) { + /* Invoke global callback to indicate unsuccessful registration of temperature notification */ + RF_invokeGlobalCallback(RF_GlobalEventTempNotifyFail, NULL); + } +} + +/* + * Clock callback due to inactivity timeout. + * + * Input: pObj - Not used. + * Return: none + */ +static void RF_clkInactivityCallback(uintptr_t a) +{ + /* If there are no pending commands in the queue */ + if (RF_cmdQ.nSeqPost == RF_cmdQ.nSeqDone) + { + /* Release the constraint on the command queue and if nothing prevents, power down the radio */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } +} + +/* + * Clock callback due to request access timeout. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkReqAccess(uintptr_t a) +{ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); +} + +/* + * Callback used to post semaphore for runCmd() and pendCmd(). + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_syncCb(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Local variables */ + RF_Cmd* pCmd; + + /* If there is a user callback provided. */ + if (h->state.pCbSync) + { + /* Invoke the user callback with the events fired. */ + ((RF_Callback)h->state.pCbSync)(h, ch, e); + } + + /* Mask the possible causes of releasing the semaphore */ + RF_EventMask maskedEvents = (e & h->state.eventSync); + + /* Release the semaphore on any of the reasons: last command done, + subscribed event happened, last FG command is done in IEEE mode */ + if (maskedEvents) + { + /* Find the command. We do it here within the SWI context. */ + pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* Store the events in the context of the client */ + h->state.unpendCause = maskedEvents; + + /* Find the command. We do it here within the SWI context. */ + if (pCmd) + { + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Exhange the callback function: use the user callback from this point */ + pCmd->pCb = (RF_Callback)h->state.pCbSync; + } + + /* Clear temporary storage of user callback (it was restored and served at this point) */ + h->state.pCbSync = NULL; + + /* Post the semaphore to release the RF_pendCmd() */ + SemaphoreP_post(&h->state.semSync); + } +} + +/* + * Invoke the global callback registered through the RFCC26XX_hwAttrs. + * + * Input: e - Events causing the function call. + * Return: none + */ +static void RF_invokeGlobalCallback(RF_GlobalEvent event, void* arg) +{ + /* Decode the global callback and it's mask from the board file. */ + RF_GlobalCallback callback = RFCC26XX_hwAttrs.globalCallback; + RF_GlobalEventMask eventMask = RFCC26XX_hwAttrs.globalEventMask; + + /* If the board has subscribed to this event, invoke the callback. */ + if (callback && (eventMask & event)) + { + callback(RF_currClient, event, arg); + } +} + +/* + * Default callback function. + * + * Input: h - Handle to the client. + * ch - Handle to the command which callback to be invoked. + * e - Events causing the function call. + * Return: none + */ +static void RF_defaultCallback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e) +{ + /* Do nothing */; +} + +/*-------------- RF powerup/powerdown FSM functions ---------------*/ + +/* + * The SWI handler for FSM events. + * + * Input: a0 - Not used. + * a1 - Not used. + * Return: none + */ +static void RF_swiFsm(uintptr_t a0, uintptr_t a1) +{ + RF_core.fxn(RF_currClient, (RF_FsmEvent)SwiP_getTrigger()); +} + +/* + * Clock callback called upon powerup. + * + * Input: a - Not used. + * Return: none + */ +static void RF_clkPowerUp(uintptr_t a) +{ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Dispatch the next RF core event. */ + RF_dispatchNextEvent(); + } + else + { + /* Trigger FSM SWI to start the wake up sequence of the radio. + This is important when we poll the XOSC_HF. */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventWakeup); + } +} + +/* + * RF CPE0 ISR during FSM powerup/powerdown. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0PowerFsm(uintptr_t a0) +{ + /* Read all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + /* If the radio is active */ + if (RF_core.fxn == RF_fsmActiveState) + { + /* Change HWI handler to the correct one */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* No synth error */ + if (!RF_checkCmdFsError()) + { + /* Restart pending rat channels. */ + RF_ratRestartChannels(); + + /* Dispatch the next command */ + RF_dispatchNextCmd(); + } + } + + /* Handle special events as boot, etc */ + if (rfcpeifg & (RFC_DBELL_RFCPEIFG_BOOT_DONE_M | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventPowerStep); + } +} + +/* + * RF CPE0 ISR during Change PHY switching. + * + * Input: a0 - Not used. + * Return: none + */ +static void RF_hwiCpe0ChangePhy(uintptr_t a0) +{ + /* Clear all IRQ flags in doorbell and then clear them */ + uint32_t rfcpeifg = RFCCpeIntGetAndClear(RF_CPE0_INT_MASK); + + if (rfcpeifg & IRQ_LAST_COMMAND_DONE) + { + /* Proceed to the second phase of the phy switching process */ + SwiP_or(&RF_swiFsmObj, RF_FsmEventFinishChangePhy); + } +} + +/*-------------- Power management state functions ---------------*/ +/* + * Handles RF Core patching for CPE, MCE, RFE (if required) in setup state during power-up. + * + * Input: mode - RF_PHY_BOOTUP_MODE: First boot of the RF core. + * - RF_PHY_SWITCHING_MODE: Switching between two phys. + * Return: none + */ +static void RF_applyRfCorePatch(bool mode) +{ + /* Local reference to the patches. */ + void (*cpePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->cpePatchFxn; + void (*mcePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->mcePatchFxn; + void (*rfePatchFxn)(void) = RF_currClient->clientConfig.pRfMode->rfePatchFxn; + + if (mode == RF_PHY_SWITCHING_MODE) + { + /* If patches are provided, enable RFE and MCE clocks. */ + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Clear the previous patch. */ + if (cpePatchFxn != NULL) + { + RFCCpePatchReset(); + } + } + + /* Load the patches if relevant for this phy. */ + if (cpePatchFxn != NULL) + { + if (mode == RF_PHY_BOOTUP_MODE) + { + cpePatchFxn(); + } + } + + if ((mcePatchFxn != NULL) || (rfePatchFxn != NULL)) + { + /* Wait for clocks to be turned ON */ + RF_dbellSyncOnAck(); + + /* Patch MCE if relevant */ + if (mcePatchFxn != NULL) + { + mcePatchFxn(); + } + + /* Patch RFE if relevant */ + if (rfePatchFxn != NULL) + { + rfePatchFxn(); + } + + /* Turn off additional clocks */ + RFCDoorbellSendTo(CMDR_DIR_CMD_2BYTE(RF_CMD0, 0)); + } +} + +/* + * Arms the inactivity timer and hence postpones the decision whether + * power management shall take place or not. + * + * Input: none + * Return: none + */ +static void RF_setInactivityTimeout(void) +{ + /* Local variables to be used to find the correct timeout value. */ + uint32_t inactivityTimeUsA = 0; + uint32_t inactivityTimeUsB = 0; + RF_Handle handleA = RF_Sch.clientHnd[0]; + RF_Handle handleB = RF_Sch.clientHnd[1]; + + /* Issue radio free callback after pre-emption if required */ + uint8_t tmp = RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + + /* If the radio was yielded, add the flag */ + if (RF_currClient && RF_currClient->state.bYielded) + { + tmp |= RF_RADIOFREECB_REQACCESS_FLAG; + } + + /* Call the radio free callback */ + RF_issueRadioFreeCb(tmp); + + if (handleA) + { + if (handleA->state.bYielded == false) + { + inactivityTimeUsA = handleA->clientConfig.nInactivityTimeout; + } + handleA->state.bYielded = false; + } + + if (handleB) + { + if (handleB->state.bYielded == false) + { + inactivityTimeUsB = handleB->clientConfig.nInactivityTimeout; + } + handleB->state.bYielded = false; + } + + /* Set the inactivity time to the max between the two clients */ + uint32_t inactivityTimeUs = MAX(inactivityTimeUsA, inactivityTimeUsB); + + /* If immediate power down is reuqested */ + if (inactivityTimeUs == SemaphoreP_NO_WAIT) + { + /* We can powerdown immediately */ + RF_clkInactivityCallback((uintptr_t)NULL); + } + else if (inactivityTimeUs != SemaphoreP_WAIT_FOREVER) + { + /* Reprogram and start inactivity timer */ + RF_restartClockTimeout(&RF_clkInactivityObj, inactivityTimeUs/ClockP_getSystemTickPeriod()); + } +} + + +/* + * Handle callback to client for RF_EventLastCmdDone and issue radio free callback if required. + * + * Input: none + * Return: none + */ +static void RF_radioOpDoneCb(void) +{ + /* Serve the first entry in the done queue */ + RF_Cmd* pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pDone); + + /* Radio command done */ + if (pCmd) + { + /* Update implicit radio state (chained FS command if any) */ + RF_cacheFsCmd(pCmd); + + /* Read and clear the events */ + RF_EventMask events = pCmd->rfifg; + pCmd->rfifg = 0; + + /* Issue callback, free container and dequeue */ + if (pCmd->pCb) + { + /* If any of the cancel events are set, mask out the other events. */ + RF_EventMask abortMask = (RF_EventCmdCancelled + | RF_EventCmdAborted + | RF_EventCmdStopped + | RF_EventCmdPreempted); + + /* Mask out the other events if any of the above is set. */ + if (events & abortMask) + { + RF_EventMask nonTerminatingEvents = events & ~(abortMask | RF_EventCmdDone | RF_EventLastCmdDone | + RF_EventLastFGCmdDone | RF_EventFGCmdDone); + if (nonTerminatingEvents) + { + /* Invoke the user callback with any pending non-terminating events, since bare abort will follow */ + pCmd->pCb(pCmd->pClient, pCmd->ch, nonTerminatingEvents); + } + + /* Mask out the other events if any of the above is set. */ + events &= abortMask; + } + + /* Invoke the user callback */ + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Update num of radio command done */ + RF_cmdQ.nSeqDone = (RF_cmdQ.nSeqDone+1) & N_CMD_MODMASK; + + /* Commmand completed reset command flags */ + pCmd->flags = 0; + + /* Invalidate the command handle. This is to avoid having duplicate + handles in the pool. */ + pCmd->ch = RF_SCHEDULE_CMD_ERROR; + + /* Command completed, free command queue container */ + List_get(&RF_cmdQ.pDone); + + /* Exit critical section */ + HwiP_restore(key); + + /* Check if there are any more pending commands */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + RF_setInactivityTimeout(); + } + } +} + +/* + * Verify if reconiguring or powering down the radio is allowed. + * + * Input: none + * Return: none + */ +static bool RF_isStateTransitionAllowed(void) +{ + /* Local variable. */ + bool status = false; + + /* If we are not performing RF core state changes. */ + if (RF_core.status == RF_CoreStatusActive) + { + if(RF_cmdQ.pCurrCmdBg == NULL && + RF_cmdQ.pCurrCmdFg == NULL) + { + status = true; + } + } + + /* Return with the decision. */ + return(status); +} + +/* + * Measure radio powerup time. If it is lesser than the previous run, update + * the powerup duration value so that it can be used during next wake up. + * + * Input: *powerupDuration Pointer to the powerup duration that needs updating + * Return: none + */ +static void RF_updatePowerupDuration(uint32_t *powerupDuration) +{ + uint32_t rtcValTmp1; + uint32_t rtcValTmp2; + uint32_t prevPowerUpDuration; + /* Temporary storage to be able to compare the new value to the old measurement */ + prevPowerUpDuration = *powerupDuration; + + /* Take wake up timestamp and the current timestamp */ + rtcValTmp1 = (uint32_t) RF_rtcTimestampA; + rtcValTmp2 = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate the difference of the timestamps and convert it to us units */ + *powerupDuration = UDIFF(rtcValTmp1, rtcValTmp2); + *powerupDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Low pass filter on power up durations less than in the previous cycle */ + if (prevPowerUpDuration > *powerupDuration) + { + /* Expect that the values are small and the calculation can be done in 32 bits */ + *powerupDuration = (prevPowerUpDuration + *powerupDuration)/2; + } + + /* Power up duration should be within certain upper and lower bounds */ + if (*powerupDuration > RF_DEFAULT_POWER_UP_TIME) + { + *powerupDuration = RF_DEFAULT_POWER_UP_TIME; + } + else if (*powerupDuration < RF_DEFAULT_MIN_POWER_UP_TIME) + { + *powerupDuration = RF_DEFAULT_MIN_POWER_UP_TIME; + } +} + +/* + * RF state machine function during power up state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmPowerUpState(RF_Object *pObj, RF_FsmEvent e) +{ + /* Note: pObj is NULL in this state */ + if (e & RF_FsmEventLastCommandDone) + { + /* Invoke the user provided callback function */ + RF_radioOpDoneCb(); + + /* Retrig the SWI if there are more commands in the done queue. */ + if (List_head(&RF_cmdQ.pDone)) + { + /* Trigger self if there are more commands in callback queue */ + SwiP_or(&RF_swiFsmObj, (e | RF_FsmEventLastCommandDone)); + } + else + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + + /* Schedule the next event based on the state of the command queue + and the RAT module. */ + RF_dispatchNextEvent(); + } + } + else if (e & RF_FsmEventWakeup) + { + /* Notify the power driver that FLASH is needed in IDLE */ + bDisableFlashInIdleConstraint = true; + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + + /* Store the current RTC tick for nPowerUpDuration calculation */ + RF_rtcTimestampA = AONRTCCurrent64BitValueGet(); + + /* Set current client from first command in command queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pNextCmd) + { + RF_Object* pNextClient = pNextCmd->pClient; + + /* If the next command belongs to another client, initiate PHY switching */ + if ((RF_currClient) && (RF_currClient != pNextClient)) + { + /* Invoke the client switch callback if it was provided */ + if (pNextClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)pNextClient->clientConfig.pClientEventCb; + pClientEventCb(pNextClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Due to client switching, update the analogCfg field of setup command. */ + pNextClient->clientConfig.bUpdateSetup = true; + } + + /* Set the current client to be the next client */ + RF_currClient = pNextClient; + } + + /* Set the RF mode in the PRCM register (RF_open already verified that it is valid) */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCMODESEL) = RF_currClient->clientConfig.pRfMode->rfMode; + + /* Notiy the power driver that Standby is not allowed and RF core need to be powered */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_setDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Indicate that the power-up sequence is being started */ + RF_core.status = RF_CoreStatusPoweringUp; + + /* If the configuration on board level requires to set the dependency every time. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* If there are RFE and MCE patches, turn on their clocks */ + if ((RF_currClient->clientConfig.pRfMode->mcePatchFxn != NULL) || + (RF_currClient->clientConfig.pRfMode->rfePatchFxn != NULL)) + { + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_2BYTE(RF_CMD0, RFC_PWR_PWMCLKEN_MDMRAM | RFC_PWR_PWMCLKEN_RFERAM)); + } + + /* Turn on the clock to the RF core. Registers can be accessed afterwards. */ + RFCClockEnable(); + + /* Reconfigure the CPE interrupt lines to a start up value on a controlled way. */ + RFCCpeIntDisable(RF_CPE0_INT_MASK); + RFCCpe0IntSelect(RF_CPE0_INT_MASK); + + /* Enable some of the interrupt sources. */ + RFCCpeIntEnable(RFC_DBELL_RFCPEIEN_BOOT_DONE_M + | RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M + | RFC_DBELL_RFCPEIEN_IRQ14_M); + + /* Set the next state. */ + RF_core.fxn = RF_fsmSetupState; + + /* Enable interrupts: continue when boot is done */ + HwiP_enableInterrupt(INT_RFC_HW_COMB); + HwiP_enableInterrupt(INT_RFC_CPE_0); + } +} + +/* + * RF state machine function during setup state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmSetupState(RF_Object *pObj, RF_FsmEvent e) +{ + if (e & RF_FsmEventPowerStep) + { + /* Apply RF Core patches (if required) */ + RF_applyRfCorePatch(RF_PHY_BOOTUP_MODE); + + /* Initialize system bus request */ + RF_dbellSubmitCmdAsync((uint32_t)CMDR_DIR_CMD_1BYTE(CMD_BUS_REQUEST, 1)); + + /* Configure the RAT_SYNC command which will follow SETUP command */ + RF_ratSyncCmd.start.commandNo = CMD_SYNC_START_RAT; + RF_ratSyncCmd.start.status = IDLE; + RF_ratSyncCmd.start.startTrigger.triggerType = TRIG_NOW; + RF_ratSyncCmd.start.pNextOp = NULL; + RF_ratSyncCmd.start.condition.rule = COND_NEVER; + + /* Init the content of setup command. */ + RF_initRadioSetup(pObj); + + /* Configure the SETUP command. */ + RF_RadioSetup* pRadioSetup = pObj->clientConfig.pRadioSetup; + + /* Search for specific commands in the command chain. */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + /* Trace to the end of chain */ + tmp = tmp->pNextOp; + } + + /* Add the CMD_RAT_SYNC to the end of chain */ + tmp->pNextOp = (RF_Op*)&RF_ratSyncCmd.start; + tmp->condition.rule = COND_ALWAYS; + + /* Setup FS command to follow SETUP command */ + RF_Cmd* pCmdFirstPend = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + if (pCmdFirstPend && ((pCmdFirstPend->pOp->commandNo == CMD_FS) || (pCmdFirstPend->pOp->commandNo == CMD_FS_OFF))) + { + /* Do Nothing */ + } + else + { + if (pObj->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &pObj->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + RF_ratSyncCmd.start.pNextOp = (RF_Op*)pOpFs; + RF_ratSyncCmd.start.condition.rule = COND_ALWAYS; + } + } + +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + /* Trim directly the radio register values based on the ID of setup command. */ + rfTrim_t rfTrim; + RFCRfTrimRead((rfc_radioOp_t *)pRadioSetup, &rfTrim); + RFCRfTrimSet(&rfTrim); +#endif + + /* Make sure system bus request is done by now */ + RF_dbellSyncOnAck(); + + /* Set the next state. */ + RF_core.fxn = RF_fsmActiveState; + + /* Run the XOSC_HF switching if the pre-notify function setup the power + constraint PowerCC26XX_SWITCH_XOSC_HF_MANUALLY */ + if (RF_core.manualXoscHfSelect) + { + /* Wait until the XOSC_HF is stable */ + while (!PowerCC26XX_isStableXOSC_HF()); + + /* Invoke the XOSC_HF switching */ + PowerCC26XX_switchXOSC_HF(); + } + else if (PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_HF) != OSC_XOSC_HF) + { + /* If the XOSC_HF is not ready yet, only execute the first hal of the chain*/ + tmp->condition.rule = COND_NEVER; + + /* Next state: RF_fsmXOSCState (polling XOSC_HF)*/ + RF_core.fxn = RF_fsmXOSCState; + } + + /* Send the setup chain to the RF core */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } +} + +/* + * RF state machine function during XOSC state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmXOSCState(RF_Object *pObj, RF_FsmEvent e) +{ + if ((e & RF_FsmEventPowerStep) || (e & RF_FsmEventWakeup)) + { + /* If XOSC_HF is now ready */ + if (PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_HF) == OSC_XOSC_HF) + { + /* Next state: RF_fsmActiveState */ + RF_core.fxn = RF_fsmActiveState; + + /* Continue with the CMD_RAT_SYNC and the rest of the chain. */ + RF_dbellSubmitCmdAsync((uint32_t)&RF_ratSyncCmd.start); + } + else + { + /* Clock source not yet switched to XOSC_HF: schedule new polling */ + RF_restartClockTimeout(&RF_clkPowerUpObj, RF_XOSC_HF_SWITCH_CHECK_PERIOD_US/ClockP_getSystemTickPeriod()); + } + } +} + +/* + * RF state machine function during active state. + * + * Input: pObj - Pointer to RF object. + * e - State machine event. + * Return: none + */ +static void RF_fsmActiveState(RF_Object *pObj, RF_FsmEvent e) +{ + volatile RF_Cmd* pCmd; + RF_EventMask events; + bool transitionAllowed; + uint32_t key; + + if (e & RF_FsmEventCpeInt) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* Dereference the command which requested the callback*/ + pCmd = (RF_Cmd*)RF_cmdQ.pCurrCmdCb; + + /* If this is due to other event than LastCmdDone */ + if (pCmd && !(pCmd->rfifg & RF_TERMINATION_EVENT_MASK)) + { + /* Temporarily store the reason of callback */ + events = pCmd->rfifg; + + /* Clear the events which are handled here */ + pCmd->rfifg &= (~events); + + /* Exit critical section */ + HwiP_restore(key); + + /* Invoke the user callback if it is provided */ + if (pCmd->pCb && events) + { + pCmd->pCb(pCmd->pClient, pCmd->ch, events); + } + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventCpeInt; + } + /* Coming from powerup states */ + else if (e & RF_FsmEventPowerStep) + { + /* RF core boot process is now finished */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCBITS) |= RF_BOOT1; + + /* Release the constraint on the FLASH in IDLE */ + if (bDisableFlashInIdleConstraint) + { + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + bDisableFlashInIdleConstraint = false; + } + + /* Enter critical section */ + key = HwiP_disable(); + + /* Init last LF clock source to default boot source */ + static uint32_t lfClockSourceLast = OSC_RCOSC_HF; + + uint32_t lfClockSource = PowerCC26X2_oscClockSourceGet(OSC_SRC_CLK_LF); + + /* Update power up duration if the LF clock is derived from the same source as the last check. + Reset the calculation if the LF clock source has changed */ + if ((lfClockSource == lfClockSourceLast) + && pObj->clientConfig.bMeasurePowerUpDuration + && RF_rtcTimestampA) + { + /* Dereference the active background command */ + pCmd = (RF_Cmd*)RF_cmdQ.pCurrCmdBg; + + /* If CMD_FS is the first command executed after powerup, a cached FS cmd is not executed, + thus the powerupduration is expected to be shorter and is stored in nPowerUpDurationFs */ + if (pCmd && ((pCmd->pOp->commandNo == CMD_FS) || (pCmd->pOp->commandNo == CMD_FS_OFF))) + { + RF_updatePowerupDuration(&(pObj->clientConfig.nPowerUpDurationFs)); + } + /* Any other command executed on powerup would mean an implicit FS command is executed + by the RF driver, so update nPowerUpduration. This duration includes the time required to + execute the implicit FS cmd previously cached by the RF Driver */ + else + { + RF_updatePowerupDuration(&(pObj->clientConfig.nPowerUpDuration)); + } + } + else + { + /* LF Clock source changed, reset power up duration measurement */ + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.nPowerUpDurationFs = RF_DEFAULT_POWER_UP_TIME; + lfClockSourceLast = lfClockSource; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, return an error callback to the client. + The client can either resend the CMD_FS or ignore the error as per Errata on PG2.1 */ + if (RF_checkCmdFsError()) + { + /* Invoke the error callback: deault is do nothing */ + RF_Callback pErrCb = (RF_Callback)pObj->clientConfig.pErrCb; + pErrCb(pObj, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + + /* Check if there is pending command */ + if (List_head(&RF_cmdQ.pPend)) + { + /* Make sure the next pending command gets dispatched by issuing CPE0 IRQ */ + RF_dispatchNextEvent(); + } + else + { + /* No pending command */ + e |= RF_FsmEventLastCommandDone; + } + } + + /* Issue power up callback: the RF core is active */ + RF_Callback pPowerCb = (RF_Callback)pObj->clientConfig.pPowerCb; + pPowerCb(pObj, 0, RF_EventPowerUp); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerStep; + } + else if (e & RF_FsmEventLastCommandDone) + { + /* Issue radio operation done callback */ + RF_radioOpDoneCb(); + + /* Take the next command in the done queue if any left */ + if (List_empty(&RF_cmdQ.pDone)) + { + /* We've handled this event now */ + e &= ~RF_FsmEventLastCommandDone; + } + } + else if (e & RF_FsmEventInitChangePhy) + { + /* Enter critical section */ + key = HwiP_disable(); + + /* We only continue with phy switching if the RF core is still available. + This check is important since the queues might have changed in the meantime + of servicing the SWI. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* Take the next command from the pend queue */ + RF_Cmd* pNextCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + if ((transitionAllowed == true) && (pNextCmd != NULL)) + { + /* Indicate that we are changing phy on the RF core. */ + RF_core.status = RF_CoreStatusPhySwitching; + + /* Change HWI handler while switching the phy */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0ChangePhy, (uintptr_t)NULL); + + /* Exit critical section */ + HwiP_restore(key); + + /* Stop inactivity clock of the current client if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Store the timestamp or measurement of the switching time */ + RF_rtcBeginSequence = AONRTCCurrent64BitValueGet(); + + /* Notify the power driver that FLASH is needed in IDLE */ + bDisableFlashInIdleConstraint = true; + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + + /* Switch the current client to the commands client */ + RF_currClient = pNextCmd->pClient; + + /* Do client switch callback if provided */ + if (RF_currClient->clientConfig.nClientEventMask & RF_ClientEventSwitchClientEntered) + { + RF_ClientCallback pClientEventCb = (RF_ClientCallback)RF_currClient->clientConfig.pClientEventCb; + pClientEventCb(RF_currClient, RF_ClientEventSwitchClientEntered, NULL); + } + + /* Apply the new RF Core patch */ + RF_applyRfCorePatch(RF_PHY_SWITCHING_MODE); + + /* Ensure that the analog domain is updated. */ + RF_currClient->clientConfig.bUpdateSetup = true; + + /* Ensure that the overrides are correct. */ + RF_initRadioSetup(RF_currClient); + + /* Configure the SETUP command */ + RF_RadioSetup* pRadioSetup = RF_currClient->clientConfig.pRadioSetup; + + /* Walk the chain and search or specific commands */ + RF_Op* tmp = (RF_Op*)&pRadioSetup->prop; + while ((tmp->pNextOp) && (tmp->pNextOp->commandNo != CMD_SYNC_START_RAT) && + (tmp->pNextOp->commandNo != CMD_FS) && + (tmp->pNextOp->commandNo != CMD_FS_OFF)) + { + tmp = tmp->pNextOp; + } + + /* Clear any of the found specific command */ + tmp->pNextOp = NULL; + tmp->condition.rule = COND_NEVER; + + /* Setup FS command to follow SETUP command */ + RF_Op* pOpFirstPend = pNextCmd->pOp; + if ((pOpFirstPend->commandNo == CMD_FS) || (pOpFirstPend->commandNo == CMD_FS_OFF)) + { + /* First command is FS command so no need to chain an implicit FS command -> reset nRtc2 */ + RF_rtcBeginSequence = 0; + } + else + { + if (RF_currClient->state.mode_state.cmdFs.commandNo) + { + /* Chain in the implicit FS command */ + rfc_CMD_FS_t* pOpFs = &RF_currClient->state.mode_state.cmdFs; + pOpFs->status = IDLE; + pOpFs->pNextOp = NULL; + pOpFs->startTrigger.triggerType = TRIG_NOW; + pOpFs->condition.rule = COND_NEVER; + tmp->pNextOp = (RF_Op*)pOpFs; + tmp->condition.rule = COND_ALWAYS; + } + } + +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1) + /* Trim directly the radio register values based on the ID of setup command. */ + rfTrim_t rfTrim; + RFCRfTrimRead((rfc_radioOp_t *)pRadioSetup, &rfTrim); + RFCRfTrimSet(&rfTrim); +#endif + + /* Send the command chain */ + RF_dbellSubmitCmdAsync((uint32_t)pRadioSetup); + + /* Invoke the global callback. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioSetup, (void*)pRadioSetup); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + } + + /* We've handled this event now */ + e &= ~RF_FsmEventInitChangePhy; + } + else if (e & RF_FsmEventFinishChangePhy) + { + /* Release the constraint on the FLASH in IDLE */ + if (bDisableFlashInIdleConstraint) + { + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + bDisableFlashInIdleConstraint = false; + } + + /* Check the status of the CMD_FS, if it was sent (chained) to the setup command. + If it failed, invoke the error callback of the client. + The client can either resend the CMD_FS or ignore the error. */ + if (RF_checkCmdFsError()) + { + RF_Callback pErrCb = (RF_Callback)RF_currClient->clientConfig.pErrCb; + pErrCb(RF_currClient, RF_ERROR_CMDFS_SYNTH_PROG, RF_EventError); + } + + /* Only compute PHY switching time if RF_rtcBeginSequence is not zero (was initialized) */ + if (RF_rtcBeginSequence) + { + /* Record the timestamp for switching time measurement. */ + uint32_t RF_rtcEndSequence = (uint32_t) AONRTCCurrent64BitValueGet(); + + /* Calculate how long it took to reconfigure the radio to a new phy. */ + RF_currClient->clientConfig.nPhySwitchingDuration = UDIFF(RF_rtcBeginSequence, RF_rtcEndSequence); + RF_currClient->clientConfig.nPhySwitchingDuration >>= RF_RTC_CONV_TO_US_SHIFT; + + /* Reset RF_rtcBeginSequence value at the end of phy switching sequence. */ + RF_rtcBeginSequence = 0; + } + + /* Change HWI handler */ + HwiP_setFunc(&RF_hwiCpe0Obj, RF_hwiCpe0Active, (uintptr_t)NULL); + + /* Mark radio and client as being active */ + RF_core.status = RF_CoreStatusActive; + + /* Serve the callbacks if the queue was rearranged while PHY switching was performed. */ + if (List_head(&RF_cmdQ.pDone)) + { + SwiP_or(&RF_swiFsmObj, RF_FsmEventLastCommandDone); + } + + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We have handled this event now */ + e &= ~RF_FsmEventFinishChangePhy; + } + else if (e & RF_FsmEventPowerDown) + { + /* Enter critical section. */ + key = HwiP_disable(); + + /* Verify if the decision has not been reverted in the meantime. */ + transitionAllowed = RF_isStateTransitionAllowed(); + + /* If possible, put the running RAT channels into pending state allowing to + power down the RF core. */ + if (transitionAllowed) + { + transitionAllowed = RF_ratReleaseChannels(); + } + + /* If there is nothing prevent us to power down, proceed. */ + if (transitionAllowed) + { + /* Indicate that the RF core is being powered down from now */ + RF_core.status = RF_CoreStatusPoweringDown; + + /* Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Exit ritical setion. */ + HwiP_restore(key); + + /* Execute power down sequence of the RF core */ + RF_corePowerDown(); + + /* Invoke the global callback. At this point the clock of RF core is OFF, but the + power domain is still powered (hence the doorbell signals are still active. + We do the callback here to save some power. */ + RF_invokeGlobalCallback(RF_GlobalEventRadioPowerDown, NULL); + + /* Notify the power driver that Standby mode is allowed and the RF core can be powered down. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + Power_releaseDependency(PowerCC26XX_DOMAIN_RFCORE); + + /* Closing all handles */ + if (!RF_numClients) + { + /* Release the semaphore to be sure no one is pending on it */ + SemaphoreP_post(&RF_currClient->state.semSync); + } + + /* If there is no specific client request or the XOSC, release the dependency */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == false) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + + /* Release constraint of switching XOSC_HF from the RF driver itself */ + if (RF_core.manualXoscHfSelect) + { + RF_core.manualXoscHfSelect = false; + Power_releaseConstraint(PowerCC26XX_SWITCH_XOSC_HF_MANUALLY); + } + + /* Next state: RF_fsmPowerUpState */ + RF_core.fxn = RF_fsmPowerUpState; + + /* Indicate that the RF core is now powered down */ + RF_core.status = RF_CoreStatusIdle; + + /* Issue radio available callback if RF_yield was called with no + pending commands in the queue */ + uint8_t tmp = RF_RADIOFREECB_REQACCESS_FLAG; + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + tmp |= RF_RADIOFREECB_PREEMPT_FLAG | RF_RADIOFREECB_CMDREJECT_FLAG; + } + RF_issueRadioFreeCb(tmp); + } + else + { + /* Exit ritical setion. */ + HwiP_restore(key); + } + + /* Reschedule the next event based on the state of the command queue + and the RAT module. We do it here as future commands need to work even if + power management is disabled manually. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventPowerDown; + } + else if (e & RF_FsmEventRunScheduler) + { + /* Run the scheduler again. */ + RF_dispatchNextEvent(); + + /* We've handled this event now */ + e &= ~RF_FsmEventRunScheduler; + } + + /* Call self again if there are outstanding events to be processed */ + if (e) + { + /* Trig the SWI with the remained/unhandled events */ + SwiP_or(&RF_swiFsmObj, e); + } +} + +/*-------------- Initialization & helper functions ---------------*/ + +/* + * Initialize RF driver. + * + * Input: none + * Return: none + */ +static void RF_init(void) +{ + union { + HwiP_Params hp; + SwiP_Params sp; + } params; + + /* Power init */ + Power_init(); + +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT != DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + /* Enable output RTC clock for Radio Timer Synchronization + * + * This is done by setup.c which executes on the secure side for + * CC13X4_CC26X3_CC26X4 devices. For all other devices it is not done by + * setup and needs to be done by the RF driver. + */ + HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M; +#endif + + /* Set the automatic bus request */ + HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCBITS) = RF_BOOT0; + + /* Initialize SWI used by the RF driver. */ + SwiP_Params_init(¶ms.sp); + params.sp.priority = RFCC26XX_hwAttrs.swiPriority; + SwiP_construct(&RF_swiFsmObj, RF_swiFsm, ¶ms.sp); + SwiP_construct(&RF_swiHwObj, RF_swiHw, ¶ms.sp); + + /* Initialize HWI used by the RF driver. */ + HwiP_Params_init(¶ms.hp); + params.hp.priority = RFCC26XX_hwAttrs.hwiPriority; + HwiP_construct(&RF_hwiCpe0Obj, INT_RFC_CPE_0, RF_hwiCpe0PowerFsm, ¶ms.hp); + HwiP_construct(&RF_hwiHwObj, INT_RFC_HW_COMB, RF_hwiHw, ¶ms.hp); + + /* Initialize clock object used as power-up trigger */ + ClockP_construct(&RF_clkPowerUpObj, &RF_clkPowerUp, 0, NULL); + ClockP_construct(&RF_clkInactivityObj, &RF_clkInactivityCallback, 0, NULL); + + /* If TCXO is selected in CCFG, the RF Driver must not be allowed to control + the XOSC switching by subscribing to wakeup notification from the Power driver. */ + if (CCFGRead_XOSC_FREQ() != CCFGREAD_XOSC_FREQ_TCXO) + { + /* Subscribe to wakeup notification from the Power driver */ + Power_registerNotify(&RF_wakeupNotifyObj, /* Object to register */ + PowerCC26XX_AWAKE_STANDBY, /* Event the notification to be invoked upon */ + (Power_NotifyFxn) RF_wakeupNotification, /* Function to be invoked */ + (uintptr_t) NULL); /* Parameters */ + } + + /* Set the XOSC_HF dependency if the HW attributes say so. This will ensure + that the XOSC_HF is turned on by the power driver as soon as possible when + coming out of standby. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_setDependency(PowerCC26XX_XOSC_HF); + } + + /* Initialized the queues. */ + List_clearList(&RF_cmdQ.pDone); + List_clearList(&RF_cmdQ.pPend); + + /* Initialize global variables */ + RF_core.status = RF_CoreStatusIdle; + RF_core.init = false; + RF_core.activeTimeUs = 0; + RF_core.manualXoscHfSelect = false; + RF_ratModule.availableRatChannels = RF_DEFAULT_AVAILRATCH_VAL; + RF_rtcTimestampA = 0; + RF_rtcBeginSequence = 0; + RF_errTolValInUs = RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US; + RF_powerConstraint = 0; + + /* Set FSM state to power up */ + RF_core.fxn = RF_fsmPowerUpState; + + /* Invoke the board file init function. */ + RF_invokeGlobalCallback(RF_GlobalEventInit, NULL); +} + +/* + * Trace through the pending queue and flush the command(s). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command where the cancelling should start with. + * bFlushAll - Decides weather one or more commands should be aborted. + * Return: Number of commands was terminated. + */ +static uint32_t RF_discardPendCmd(RF_Handle h, RF_Cmd* pCmd, bool bFlushAll, bool bPreempt) +{ + /* Local variables, start from the head of queue. */ + uint32_t numDiscardedCmd = 0; + RF_Cmd* pElem = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + + /* Find the first command to be cancelled. */ + while (pElem && (pElem != pCmd)) + { + pElem = (RF_Cmd*)List_next((List_Elem*)pElem); + } + + /* If we found the command to be cancelled. */ + while (pElem) + { + /* Temporarly store the next element, since we will need + to continue from there. */ + RF_Cmd* pNextElem = (RF_Cmd*)List_next((List_Elem*)pElem); + + if (RF_isClientOwner(h, pElem)) + { + /* Mark the command that it was cancelled. */ + RF_cmdStoreEvents(pElem, RF_EventCmdCancelled); + + if (bPreempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(pElem, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove the command from the pend queue and place it to + the done queue. */ + List_remove(&RF_cmdQ.pPend, (List_Elem*)pElem); + List_put(&RF_cmdQ.pDone, (List_Elem*)pElem); + + /* Increment the counter of cancelled commands. */ + numDiscardedCmd += 1; + } + + /* Break the loop if only single cancel was requested. + Step the queue otherwise. */ + if (bFlushAll) + { + pElem = pNextElem; + } + else + { + break; + } + } + + /* Return with the number of cancelled commands. */ + return(numDiscardedCmd); +} + +/* + * Process cancel commands. It is used by RF_cancelCmd, RF_flushCmd API. + * + * Input: h - Handle to the client calling this function. + * ch - Handle to the command where the cancelling should start with. + * graceful - true: stop the command + * false: abort the command + * flush - true: flush all commands of this client + * false: only cancel the given command + * preempt - mark the command as the reason of aborting is preemption + * Return: status + */ +static RF_Stat RF_abortCmd(RF_Handle h, RF_CmdHandle ch, bool graceful, bool flush, bool preempt) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Initialize local variables */ + RF_Cmd* pCmd = NULL; + RF_Stat status = RF_StatInvalidParamsError; + RF_EventMask event = graceful ? RF_EventCmdStopped : RF_EventCmdAborted; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Handle FLUSH_ALL request */ + if (ch == RF_CMDHANDLE_FLUSH_ALL) + { + /* Start to cancel the commands from the actively running once if it belongs to this client. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + pCmd = RF_cmdQ.pCurrCmdBg; + } + else if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdFg)) + { + pCmd = RF_cmdQ.pCurrCmdFg; + } + else + { + /* Start to walk the pending queue from its head. */ + pCmd = (RF_Cmd*)List_head(&RF_cmdQ.pPend); + } + } + else + { + /* Search for the command in the command pool based on its handle. The command can + locate on any of the queues at this point. */ + pCmd = RF_cmdGet(h, ch, 0x00); + } + + /* If command handle is valid, proceed to cancel. */ + if (pCmd) + { + /* If the command is still allocated. */ + if (pCmd->flags & RF_CMD_ALLOC_FLAG) + { + /* If the command we want to cancel is actively running. */ + if (pCmd == RF_cmdQ.pCurrCmdBg) + { + /* Canceling background command */ + /* Flag that the command has been aborted. In IEEE 15.4 mode, this means + aborting both the background and foreground commands when background is aborted. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, event); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, event); + + /* Decode what method to use to terminate the ongoing radio operation. */ + uint32_t directCmd = (graceful) ? CMDR_DIR_CMD(CMD_STOP) : CMDR_DIR_CMD(CMD_ABORT); + + /* Send the abort/stop command through the doorbell to the RF core. */ + RFCDoorbellSendTo(directCmd); + + if (preempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdBg, RF_EventCmdPreempted); + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove all commands from the pend queue belong to this client. Only do it + if it was explicitely requested through the flush argument. */ + if (flush) + { + RF_discardPendCmd(h, (RF_Cmd*)List_head(&RF_cmdQ.pPend), flush, preempt); + } + + /* Return with success as we cancelled at least the currently running command. */ + status = RF_StatSuccess; + } + else if (pCmd == RF_cmdQ.pCurrCmdFg) + { + /* Canceling foreground command */ + /* Flag that the command has been aborted */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, event); + + /* Decode what method to use to terminate the ongoing FG radio operation. */ + uint32_t directCmd = (graceful) ? CMDR_DIR_CMD(CMD_IEEE_STOP_FG) : CMDR_DIR_CMD(CMD_IEEE_ABORT_FG); + + /* Send the abort/stop command through the doorbell to the RF core. */ + RFCDoorbellSendTo(directCmd); + + if (preempt) + { + /* Mark the command as being preempted. */ + RF_cmdStoreEvents(RF_cmdQ.pCurrCmdFg, RF_EventCmdPreempted); + + /* Subscribe the client for RadioFree callback. */ + RF_Sch.clientHndRadioFreeCb = pCmd->pClient; + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Remove all commands from the pend queue belong to this client. Only do it + if it was explicitely requested through the flush argument. */ + if (flush) + { + RF_discardPendCmd(h, (RF_Cmd*)List_head(&RF_cmdQ.pPend), flush, preempt); + } + + /* Return with success as we cancelled at least the currently running command. */ + status = RF_StatSuccess; + } + else + { + /* Remove one/all commands from the pend queue based on the flush argument. + If at least one command is cancelled the operation was succesful. Otherwise, + either the pend queue is empty or pCmd have terminated earlier */ + if (RF_discardPendCmd(h, pCmd, flush, preempt)) + { + /* Kick the state machine to handle the done queue and re-execute the scheduler. + This is not necessary when the RF is currently performing a power-up. */ + if ((RF_core.status != RF_CoreStatusPoweringUp) && + (RF_core.status != RF_CoreStatusPhySwitching)) + { + SwiP_or(&RF_swiFsmObj, (RF_FsmEventLastCommandDone | RF_FsmEventRunScheduler)); + } + + /* At least one command was cancelled. */ + status = RF_StatSuccess; + } + else + { + /* The command is not running and is not in the pend queue. It is located on the + done queue, hence return RF_StatCmdEnded. */ + status = RF_StatCmdEnded; + } + } + } + else + { /* If command is still in the pool but it is not allocated anymore, i.e. it was already served. */ + status = RF_StatCmdEnded; + } + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the result: + - RF_StatSuccess if at least one command was cancelled. + - RF_StatCmdEnded, when the command already finished (in the Done Q, but not deallocated yet). + - RF_StatInvalidParamsError otherwise. */ + return(status); +} + +/* + * Execute a direct or immediate command in the RF Core if possible. + * + * Input: pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of the raw status byte read from the CMDSTA register. + * Return: The return value interprets and converts the result of command execution to and RF_Stat value. + * RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_executeDirectImmediateCmd(uint32_t pCmd, uint32_t* rawStatus) +{ + /* If the RF core is ON, we can send the command */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Submit the command to the doorbell */ + uint32_t localStatus = RFCDoorbellSendTo(pCmd); + + /* Pass the rawStatus to the callee if possible. */ + if (rawStatus) + { + *rawStatus = localStatus; + } + + /* Check the return value of the RF core through the CMDSTA register within the doorbell */ + if ((localStatus & RF_CMDSTA_REG_VAL_MASK) == CMDSTA_Done) + { + /* The command was accepted */ + return(RF_StatCmdDoneSuccess); + } + else + { + /* The command was rejected */ + return(RF_StatCmdDoneError); + } + } + else + { + /* The RF core is not capable of receiving the command */ + return(RF_StatRadioInactiveError); + } +} + +/* + * Send a direct or immediate command to the RF core. The command is rejected + * if the RF core is configured to a different PHY (client). + * + * Input: h - Handle to the client calling this function. + * pCmd - Pointer to the command which shall be sent to the RF core. + * rawStatus - Return address of raw status byte read from CMDSTA register. + * Return: RF_StatCmdDoneSuccess - If the command was sent and accepted by the RF core. + * RF_StatCmdDoneError - Command was rejected by the RF core. + * RF_StatInvalidParamsError - Client do not have the right to send commands now. + * RF_StatRadioInactiveError - The RF core is OFF. + */ +static RF_Stat RF_runDirectImmediateCmd(RF_Handle h, uint32_t pCmd, uint32_t* rawStatus) +{ + /* Local variable. */ + RF_Stat status; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Only the current client is allowed to send direct commands */ + if (h != RF_currClient) + { + /* Return with an error code it is a different client */ + status = RF_StatInvalidParamsError; + } + else + { + /* Execute the direct or immediate command. */ + status = RF_executeDirectImmediateCmd(pCmd, rawStatus); + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status information about the success of command execution. */ + return(status); +} + +/* + * Helper function to find the first override representing a High PA value (CC13x2P devices). + * + * Input: pOverride - Pointer to an override list to be searched. + * overridePattern - Pattern o override to search for. + * currentValue - Reference where the current value can be returned. + * Return: paOffset - Offset of the High PA override. + * RF_TX_OVERRIDE_INVALID_OFFSET - No override was found in the list. + */ +static uint8_t RF_getPAOverrideOffsetAndValue(uint32_t* pOverride, uint32_t overridePattern, uint32_t* currentValue) +{ + /* Search for the particular override. */ + uint8_t paOffset = RFCOverrideSearch(pOverride, overridePattern, RF_TX_OVERRIDE_MASK, RF_OVERRIDE_SEARCH_DEPTH); + + /* If the override was found. */ + if (currentValue) + { + *currentValue = pOverride[paOffset] >> RF_TX_OVERRIDE_SHIFT; + } + + /* Return with an invalid value. */ + return(paOffset); +} + +/* + * Helper function to find and replace the first override representing a High PA value. + * + * Input: pOverride - Pointer to an override list to be searched. + * overridePattern - Mask of override type to searh for. + * newValue - The new raw value the PA to be set to. + * Return: paOffset - Offset of the High PA override. + * RF_TX_OVERRIDE_INVALID_OFFSET - No override was found in the list. Hence nothing to replace. + */ +static uint8_t RF_searchAndReplacePAOverride(uint32_t* pOverride, uint32_t overridePattern, uint32_t newValue) +{ + /* Search for the particular override. */ + uint8_t paOffset = RF_getPAOverrideOffsetAndValue(pOverride, overridePattern, NULL); + + /* If the override was found. */ + if (paOffset != RF_TX_OVERRIDE_INVALID_OFFSET) + { + if (overridePattern == RF_TX20_PATTERN) + { + /* Replace the high PA gain with the new value. */ + pOverride[paOffset] = TX20_POWER_OVERRIDE(newValue); + } + else + { + /* Replace the default or Sub-1GHz PA gain with the new value. */ + pOverride[paOffset] = TX_STD_POWER_OVERRIDE(newValue); + } + } + + /* Return with the offset of the PA override. */ + return(paOffset); +} + +/* + * Appends the PA specific override list to the end of given overrides. + * + * Input: baseOverride - Override list to append the applicable segment to. + * newOverride - Override segment to be appended. + * Return: none + */ +static void RF_attachOverrides(uint32_t* baseOverride, uint32_t* newOverride) +{ + if (newOverride != NULL) + { + /* Search for the attached override list. */ + uint32_t maskOverride = NEW_OVERRIDE_SEGMENT(newOverride); + + /* Search for the end of the base override list. We also look for new segment vectors. */ + while ((*baseOverride != END_OVERRIDE) && (*baseOverride != maskOverride)) + { + baseOverride++; + } + + /* Append the second override list. */ + *baseOverride = maskOverride; + } +} + +/* + * Terminate the override list at the first match of a jump to the given newOverride. + * The function assumes that there are no other jump vectors before. + * + * Input: baseOverride - Override list to append the applicable segment to. + * newOverride - Override segment to be appended. + * Return: none + */ +static void RF_detachOverrides(uint32_t* baseOverride, uint32_t* newOverride) +{ + if (newOverride != NULL) + { + /* Search for the attached override list. */ + uint32_t maskOverride = NEW_OVERRIDE_SEGMENT(newOverride); + + /* Search for the end of the base override list. We also look for new segment vectors. */ + while ((*baseOverride != END_OVERRIDE) && (*baseOverride != maskOverride)) + { + baseOverride++; + } + + /* Append the second override list if exists. */ + *baseOverride = END_OVERRIDE; + } +} + +/* + * Decode all the override pointers according to the type of the setup command. + * + * Input: radioSetup - Pointer to the setup command to be evaluated. + * Return: tx20FeatureAvailable - true if the High Gain PA is available. + * pTxPower - Pointer to the txPower field of setup command. + * pRegOverride - Pointer to the base override list. + * pRegOverrideTxStd - Pointer to the Default PA override list. + * pRegOverrideTx20 - Pointer to the High PA override list. + */ +static bool RF_decodeOverridePointers(RF_RadioSetup* radioSetup, uint16_t** pTxPower, uint32_t** pRegOverride, uint32_t** pRegOverrideTxStd, uint32_t** pRegOverrideTx20) +{ + /* Read FCFG user ID register for device identification */ + uint32_t fcfg1UserId = ChipInfo_GetUserId(); + + /* Decode if High Gain PA is even available. Bit FCFG1:USER_ID.PA tells us PA availability. */ + bool tx20FeatureAvailable = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >> FCFG1_USER_ID_PA_S ); + + /* Only decode the offset of those fields which exist on this device. */ + if (tx20FeatureAvailable) + { + /* Local variables. */ + uint8_t loDivider; + uint8_t frontEndMode; + uint8_t index; + + /* Decode the offset of txPower field and all the override pointers + available on the CC1352P/CC2652P devices. */ + switch (radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + *pTxPower = &radioSetup->common_pa.txPower; + *pRegOverride = radioSetup->common_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->common_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->common_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->common_pa.loDivider; + frontEndMode = radioSetup->common_pa.config.frontEndMode; + + break; + case (CMD_BLE5_RADIO_SETUP): + *pTxPower = &radioSetup->ble5_pa.txPower; + *pRegOverride = radioSetup->ble5_pa.pRegOverrideCommon; + *pRegOverrideTxStd = radioSetup->ble5_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->ble5_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->ble5_pa.loDivider; + frontEndMode = radioSetup->ble5_pa.config.frontEndMode; + + break; + case (CMD_PROP_RADIO_SETUP): + *pTxPower = &radioSetup->prop_pa.txPower; + *pRegOverride = radioSetup->prop_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->prop_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->prop_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = 0; + frontEndMode = radioSetup->prop_pa.config.frontEndMode; + break; + default: + *pTxPower = &radioSetup->prop_div_pa.txPower; + *pRegOverride = radioSetup->prop_div_pa.pRegOverride; + *pRegOverrideTxStd = radioSetup->prop_div_pa.pRegOverrideTxStd; + *pRegOverrideTx20 = radioSetup->prop_div_pa.pRegOverrideTx20; + + /* Input to recalculation of overrides. */ + loDivider = radioSetup->prop_div_pa.loDivider; + frontEndMode = radioSetup->prop_div_pa.config.frontEndMode; + break; + } + + /* Modify the divider and front-end specific override. This is to keep the override + list and the setup command in sync, even if the setup command was changed runtime + due to the changing stack configuration. */ + if (*pRegOverrideTxStd) + { + index = RFCOverrideSearch(*pRegOverrideTxStd, RFC_FE_OVERRIDE_ADDRESS, RFC_FE_OVERRIDE_MASK, RFC_MAX_SEARCH_DEPTH); + + if (index < RFC_MAX_SEARCH_DEPTH) + { + (*pRegOverrideTxStd)[index] = RFCAnaDivTxOverride(loDivider, frontEndMode); + } + } + + if (*pRegOverrideTx20) + { + index = RFCOverrideSearch(*pRegOverrideTx20, RFC_FE_OVERRIDE_ADDRESS, RFC_FE_OVERRIDE_MASK, RFC_MAX_SEARCH_DEPTH); + + if (index < RFC_MAX_SEARCH_DEPTH) + { + (*pRegOverrideTx20)[index] = RFCAnaDivTxOverride(loDivider, RFC_FE_MODE_ESCAPE_VALUE); + } + } + } + else + { + /* Decode the offset of txPower field and the only relevant override pointer + available on all other devices. */ + switch (radioSetup->commandId.commandNo) + { + case (CMD_RADIO_SETUP): + *pTxPower = &radioSetup->common.txPower; + *pRegOverride = radioSetup->common.pRegOverride; + break; + case (CMD_BLE5_RADIO_SETUP): + *pTxPower = &radioSetup->ble5.txPower; + *pRegOverride = radioSetup->ble5.pRegOverrideCommon; + break; + case (CMD_PROP_RADIO_SETUP): + *pTxPower = &radioSetup->prop.txPower; + *pRegOverride = radioSetup->prop.pRegOverride; + break; + default: + *pTxPower = &radioSetup->prop_div.txPower; + *pRegOverride = radioSetup->prop_div.pRegOverride; + break; + } + + /* Force the value of non-existing pointers to be NULL. */ + *pRegOverrideTxStd = NULL; + *pRegOverrideTx20 = NULL; + } + + /* Return if the High Gain PA feature is available or not. */ + return (tx20FeatureAvailable); +} + +/* + * In case the PA configuration changes during the execution of a chain, this function + * propagates the change back to the setup command. This is to reserve the change even + * after a power cycle + * + * Input: handle - Radio handle the change should be stored within + * Return: none + */ +static void RF_extractPaConfiguration(RF_Handle handle) +{ + /* Local variable to store the return value of function call. It is not used here. */ + RF_ConfigurePaCmd configurePaCmd; + + /* Retrieve the PA configuration from the RF core itself. */ + RF_TxPowerTable_Value value; + value.rawValue = RFCGetPaGain(); + value.paType = (RF_TxPowerTable_PAType) RFCGetPaType(); + + /* Update the setup command with the new settings. The change is now permanent + and will be kept even if the RF core is powered off. */ + RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value, &configurePaCmd); +} + +/* + * Helper function to find the HPOSC_OVERRIDE in provided override list and modify the HPOSC frequency offset. + * + * Input: pRegOverride - Pointer to override list. + * Return: None + */ +static void RF_updateHpOscOverride(uint32_t *pRegOverride) +{ + /* Local variables. */ + int32_t tempDegC; + int32_t relFreqOffset; + int16_t relFreqOffsetConverted; + + /* Find override for HPOSC frequency offset. */ + if (pRegOverride) + { + uint8_t index; + index = RFCOverrideSearch(pRegOverride, RF_HPOSC_OVERRIDE_PATTERN, RF_HPOSC_OVERRIDE_MASK, RF_OVERRIDE_SEARCH_DEPTH); + + if (index < RF_OVERRIDE_SEARCH_DEPTH) + { + /* Get temperature dependent HPOSC frequency offset */ + tempDegC = Temperature_getTemperature(); + relFreqOffset = OSC_HPOSCRelativeFrequencyOffsetGet(tempDegC); + RF_currentHposcFreqOffset = relFreqOffset; + relFreqOffsetConverted = OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(relFreqOffset); + + /* Update override with the HPOSC frequency offset */ + pRegOverride[index] = HPOSC_OVERRIDE(relFreqOffsetConverted); + } + } +} + +/* + * Helper function to find and modify the PA selection and gain of the provided setup command. + * + * Input: radioSetup - Setup command belong to the client. + * newValue - The new value the PA to be set to. + * configurePaCmd - The immediate command to be used to apply the changes if the RF core is active. + * Return: RF_StatSuccess - The setup command was reconfigured. + * Otherwise - An error occured. + */ +static RF_Stat RF_updatePaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd) +{ + /* Set the default return value to indicate success. */ + RF_Stat status = RF_StatSuccess; + + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + + /* Decode if High Gain PA is available. */ + bool tx20FeatureAvailable = RF_decodeOverridePointers(radioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Decode if the frequency band used is Sub-1GHz. */ + bool sub1GHz = (bool)((RF_LODIVIDER_MASK & radioSetup->common.loDivider) != 0); + + /* The new value requires the deault PA. */ + if (newValue.paType == RF_TxPowerTable_DefaultPA) + { + /* On CC1352P/CC2652P devices with the correct override lists. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + /* Store the new value in the setup command. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Ensure that the gain within the overrides are also updated. */ + RF_searchAndReplacePAOverride(pRegOverrideTxStd, RF_TXSTD_PATTERN, newValue.rawValue); + + /* Detach the High Gain overrides. It does nothing if the overrides are not attached. */ + RF_detachOverrides(pRegOverride, pRegOverrideTx20); + + /* Return with the immediate command in the argument. */ + configurePaCmd->changePa.commandNo = CMD_CHANGE_PA; + configurePaCmd->changePa.pRegOverride = pRegOverrideTxStd; + } + else if (tx20FeatureAvailable) + { + /* Limited backward compatibility on CC1352P/CC2652P devices without the + proper override lists. Only gain tuning on the Default PA is available. */ + if (*pTxPower != RF_TX20_ENABLED) + { + /* Store the new value in the setup command. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Use the dedicated command to tune the gain */ + configurePaCmd->tuneTxPower.commandNo = CMD_SET_TX_POWER; + configurePaCmd->tuneTxPower.txPower = newValue.rawValue; + } + else + { + /* PA swithing is not allowed due to the missing overrides. */ + status = RF_StatInvalidParamsError; + } + } + else + { + /* On any other devices, just accept the new gain. */ + *pTxPower = (uint16_t) newValue.rawValue; + + /* Use the dedicated command to tune the gain. */ + configurePaCmd->tuneTxPower.commandNo = CMD_SET_TX_POWER; + configurePaCmd->tuneTxPower.txPower = newValue.rawValue; + } + /* Ensure dedicated configuration for Sub1-GHz client. */ + if (sub1GHz && (status != RF_StatInvalidParamsError)) + { + status = RF_updateSub1GHzPaConfiguration(radioSetup, newValue, configurePaCmd); + } + } + else + { + /* On CC1352P/CC2652P devices with the correct override lists. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + /* If the High Gain PA is available store the escape value in the setup + command and update the overrides. */ + *pTxPower = (uint16_t) RF_TX20_ENABLED; + + /* Change the gain to the new value. */ + RF_searchAndReplacePAOverride(pRegOverrideTx20, RF_TX20_PATTERN, newValue.rawValue); + + /* Attach the High Gain overrides. */ + RF_attachOverrides(pRegOverride, pRegOverrideTx20); + + /* Return with the command argument to be used. */ + configurePaCmd->changePa.commandNo = CMD_CHANGE_PA; + configurePaCmd->changePa.pRegOverride = pRegOverrideTx20; + } + else if (tx20FeatureAvailable) + { + /* Limited backward compatibility on CC1352P/CC2652P devices without the + proper override lists. Only gain tuning on the High PA is available + if the gain override is present within the base override list.*/ + if (RF_searchAndReplacePAOverride(pRegOverride, RF_TX20_PATTERN, newValue.rawValue) == RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* Cannot use the high gain PA without a proper override list + that contains at least a placeholder gain entry. */ + status = RF_StatInvalidParamsError; + } + else + { + /* If updating the override list with the gain value was succesful, + set the escape value in the setup command. */ + *pTxPower = (uint16_t) RF_TX20_ENABLED; + + /* Use the dedicated command to tune the gain. */ + configurePaCmd->tuneTx20Power.commandNo = CMD_SET_TX20_POWER; + configurePaCmd->tuneTx20Power.tx20Power = newValue.rawValue; + } + } + else + { + /* Do not accept any high gain PA values on devices which do not support it. */ + status = RF_StatInvalidParamsError; + } + } + + /* Return with the status. */ + return(status); +} + +/* + * Helper function to configure CC13x4 Sub-1GHz gain for the default PA + * + * Input: radioSetup - Setup command belong to the client. + * newValue - The new value the PA to be set to. + * configurePaCmd - The immediate command to be used to apply the changes if the RF core is active. + * Return: RF_StatSuccess - The setup command was reconfigured. + * Otherwise - An error occured. + */ +static RF_Stat RF_updateSub1GHzPaConfiguration(RF_RadioSetup* radioSetup, RF_TxPowerTable_Value newValue, RF_ConfigurePaCmd* configurePaCmd) +{ + /* Set the default return value to indicate success. */ + RF_Stat status = RF_StatSuccess; + +/* The following feature and corresponding commands are only supported by device family cc13x4_cc26x4. */ +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; /* Not used */ + uint8_t paOffset = RF_TX_OVERRIDE_INVALID_OFFSET; + + /* Decode if High Gain PA is available. */ + bool tx20FeatureAvailable = RF_decodeOverridePointers(radioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Store the Sub-1GHz flag value in the setup command. */ + *pTxPower = RF_TXSUB1_ENABLED; + + /* Ensure that the gain within the correct override list is updated. */ + if (tx20FeatureAvailable && pRegOverrideTxStd) { + paOffset = RF_searchAndReplacePAOverride(pRegOverrideTxStd, RF_TXSUB1_PATTERN, newValue.rawValue); + + /* Use command CMD_CHANGE_PA to tune the gain. */ + configurePaCmd->changePa.commandNo = CMD_CHANGE_PA; + configurePaCmd->changePa.pRegOverride = pRegOverrideTxStd; + } + else if (pRegOverride) + { + paOffset = RF_searchAndReplacePAOverride(pRegOverride, RF_TXSUB1_PATTERN, newValue.rawValue); + + /* Use the dedicated command to tune the gain. */ + configurePaCmd->tuneTxSub1Power.commandNo = CMD_SET_TXSUB1_POWER; + configurePaCmd->tuneTxSub1Power.txSub1Power = newValue.rawValue; + } + else + { + /* PA configuration is not possible due to no override lists. */ + status = RF_StatInvalidParamsError; + } + + /* Ensure that the gain within the override list was successfully updated. */ + if (paOffset == RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* PA configuration is not possible due to missing power override. */ + status = RF_StatInvalidParamsError; + } + +#endif + + /* Return with the status. */ + return(status); +} + +/*-------------- API functions ---------------*/ +/* + * ======== RF_open ======== + * Open an RF handle + */ +RF_Handle RF_open(RF_Object *pObj, RF_Mode* pRfMode, RF_RadioSetup* pRadioSetup, RF_Params *params) +{ + /* Local variables. */ + uint8_t index; + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + + /* Assert */ + DebugP_assert(pObj != NULL); + + /* Read available RF modes from the PRCM register */ + uint32_t availableRfModes = HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCMODEHWOPT); + + /* Check for illegal PHY mode in CC2672 device */ + #if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) + /* Check for chip ID */ + if ((ChipInfo_GetChipType() == CHIP_TYPE_CC2652P7) || + (ChipInfo_GetChipType() == CHIP_TYPE_CC2652R7)) + { + /* Check if Sub-1G frequency band is used */ + if (pRadioSetup->commandId.commandNo == CMD_PROP_RADIO_DIV_SETUP) + { + if (pRadioSetup->prop_div.loDivider > 2) + /* If the data rate is NOT 100kbps or 500 kbps return NULL handle + as this is an unsupported setting on this device */ + if (! ((pRadioSetup->prop_div.symbolRate.preScale == 0x0F && + pRadioSetup->prop_div.symbolRate.rateWord == 0x10000) || + (pRadioSetup->prop_div.symbolRate.preScale == 0x0F && + pRadioSetup->prop_div.symbolRate.rateWord == 0x50000))) + { + return(NULL); + } + } + else if (pRadioSetup->commandId.commandNo == CMD_RADIO_SETUP) + { + if (pRadioSetup->common.loDivider > 2) + return(NULL); + } + else if (pRadioSetup->commandId.commandNo == CMD_BLE5_RADIO_SETUP) + { + if (pRadioSetup->ble5.loDivider > 2) + return(NULL); + } + } + #endif + + /* Verify that the provided configuration is supported by this device. + Reject any request which is not compliant. */ + if (pRfMode && pRadioSetup && (availableRfModes & (1 << pRfMode->rfMode))) + { + /* Trim the override list; The implementation of RFCOverrideUpdate is device specific */ + RFCOverrideUpdate((RF_Op*)pRadioSetup, NULL); + + /* Register the setup command to the client */ + pObj->clientConfig.pRadioSetup = pRadioSetup; + + /* Register the mode to the client */ + pObj->clientConfig.pRfMode = pRfMode; + } + else + { + /* Return with null if the device do not support the requested configuration */ + return(NULL); + } + + /* Verify that the HPOSC_OVERRIDE exists in the override list if SW TCXO is enabled */ + if (pfnUpdateHposcOverride) + { + /* Get pointer to override list */ + RF_decodeOverridePointers(pRadioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Search override list for HPOSC_OVERRIDE */ + index = RFCOverrideSearch(pRegOverride, RF_HPOSC_OVERRIDE_PATTERN, RF_HPOSC_OVERRIDE_MASK, RF_OVERRIDE_SEARCH_DEPTH); + + /* Return NULL if HPOSC_OVERRIDE is not found on the override list */ + if (index == 0xFF) + { + return(NULL); + } + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Check whether RF driver is accepting more clients */ + if (RF_numClients < N_MAX_CLIENTS) + { + /* Initialize shared objects on first client opening */ + if (RF_numClients == 0) RF_init(); + + /* Save the new RF_Handle */ + RF_Sch.clientHnd[RF_numClients++] = pObj; + + /* Exit critical section */ + HwiP_restore(key); + + /* Populate default RF parameters if not provided */ + RF_Params rfParams; + if (params == NULL) + { + RF_Params_init(&rfParams); + params = &rfParams; + } + + /* Initialize RF_Object configuration */ + pObj->clientConfig.nInactivityTimeout = params->nInactivityTimeout; + pObj->clientConfig.nPhySwitchingDuration = RF_DEFAULT_PHY_SWITCHING_TIME; + pObj->clientConfig.nClientEventMask = params->nClientEventMask; + pObj->clientConfig.nPowerUpDurationMargin = params->nPowerUpDurationMargin; + pObj->clientConfig.bUpdateSetup = true; + pObj->clientConfig.nID = params->nID; + + /* Decide if automatic adjustment should be used. */ + if (params->nPowerUpDuration) + { + pObj->clientConfig.nPowerUpDuration = params->nPowerUpDuration; + /* Use same value of user provided power up duration even if the first cmd + is an Fs command */ + pObj->clientConfig.nPowerUpDurationFs = params->nPowerUpDuration; + pObj->clientConfig.bMeasurePowerUpDuration = false; + } + else + { + pObj->clientConfig.nPowerUpDuration = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.nPowerUpDurationFs = RF_DEFAULT_POWER_UP_TIME; + pObj->clientConfig.bMeasurePowerUpDuration = true; + } + + /* Set all the callbacks to the default (do nothing) callback */ + pObj->clientConfig.pErrCb = (void*) RF_defaultCallback; + pObj->clientConfig.pClientEventCb = (void*) RF_defaultCallback; + pObj->clientConfig.pPowerCb = (void*) RF_defaultCallback; + + /* If a user specified callback is provided, overwrite the default */ + if (params->pErrCb) + { + pObj->clientConfig.pErrCb = (void *)params->pErrCb; + } + if (params->pClientEventCb) + { + pObj->clientConfig.pClientEventCb = (void *)params->pClientEventCb; + } + if (params->pPowerCb) + { + pObj->clientConfig.pPowerCb = (void *)params->pPowerCb; + } + + /* Initialize client state & variables to zero */ + memset((void*)&pObj->state, 0, sizeof(pObj->state)); + + /* Initialize client specific semaphore object */ + SemaphoreP_constructBinary(&pObj->state.semSync, 0); + + /* Initialize client specific clock objects */ + ClockP_construct(&pObj->state.clkReqAccess, RF_clkReqAccess, 0, NULL); + + /* Return with the RF handle. */ + return(pObj); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* Return with null if no more clients are accepted */ + return(NULL); + } +} + +/* + * ======== RF_close ======== + * Close an RF handle + */ +void RF_close(RF_Handle h) +{ + DebugP_assert(h != NULL); + + /* If there is at least one active client */ + if (RF_numClients) + { + /* Wait for all issued commands to finish before freeing the resources */ + if (RF_cmdQ.nSeqPost != RF_cmdQ.nSeqDone) + { + /* There are commands which not even dispatched yet. */ + RF_Cmd* pCmd = RF_queueEnd(h, &RF_cmdQ.pPend); + + /* There is no pending commmand, determine if there are items on the + other queues. */ + if (!pCmd) + { + /* If the client is executing a command running. */ + if (RF_isClientOwner(h, RF_cmdQ.pCurrCmdBg)) + { + /* The currentlty running command is the last. */ + pCmd = RF_cmdQ.pCurrCmdBg; + } + else + { + /* All commands has been dispatched, some just need to be served. This also + can return with NULL if nothing to be done. */ + pCmd = RF_queueEnd(h, &RF_cmdQ.pDone); + } + } + + /* Pend until the running command terminates */ + if (pCmd) + { + RF_pendCmd(h, pCmd->ch, RF_TERMINATION_EVENT_MASK); + } + } + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Clear the RF_sch client handle */ + if (h == RF_Sch.clientHnd[0]) + { + RF_Sch.clientHnd[0] = NULL; + } + else + { + RF_Sch.clientHnd[1] = NULL; + } + + /* Check whether this is the last client */ + if (--RF_numClients == 0) + { + /* If this is the last client, set it to be the active client */ + RF_currClient = h; + + if (RF_core.status == RF_CoreStatusActive) + { + /* Release the constraint on the RF resources */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + + /* Exit critical section */ + HwiP_restore(key); + + /* Wait until the radio is powered down (outside critical section) */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Enter critical section */ + key = HwiP_disable(); + } + + /* Unregister shared RTOS objects initalized during RF_init by the first client */ + SwiP_destruct(&RF_swiFsmObj); + HwiP_destruct(&RF_hwiCpe0Obj); + SwiP_destruct(&RF_swiHwObj); + HwiP_destruct(&RF_hwiHwObj); + ClockP_destruct(&RF_clkPowerUpObj); + ClockP_destruct(&RF_clkInactivityObj); + + /* Unregister temperature notify object if SW TCXO functionality is enabled. */ + if(pfnTemperatureUnregisterNotify != NULL) + { + pfnTemperatureUnregisterNotify(&RF_hposcRfCompNotifyObj); + } + + /* Unregister the wakeup notify callback */ + Power_unregisterNotify(&RF_wakeupNotifyObj); + + /* Release XOSC_HF dependency if it was set on board level. */ + if (RFCC26XX_hwAttrs.xoscHfAlwaysNeeded == true) + { + Power_releaseDependency(PowerCC26XX_XOSC_HF); + } + } + + /* If we're the current RF client, stop being it */ + if (RF_currClient == h) + { + RF_currClient = NULL; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Unregister client specific RTOS objects (these are not shared between clients) */ + SemaphoreP_destruct(&h->state.semSync); + ClockP_destruct(&h->state.clkReqAccess); + } +} + +/* + * ======== RF_getCurrentTime ======== + * Get current time in RAT ticks + */ +uint32_t RF_getCurrentTime(void) +{ + /* Local variable */ + uint64_t nCurrentTime = 0; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* If radio is active, read the RAT */ + if ((RF_core.status == RF_CoreStatusActive) || (RF_core.status == RF_CoreStatusPhySwitching)) + { + /* Read the RAT timer through register access */ + nCurrentTime = RF_ratGetValue(); + + /* Exit critical section */ + HwiP_restore(key); + } + else + { + /* Exit critical section */ + HwiP_restore(key); + + /* The radio is inactive, read the RTC instead */ + nCurrentTime = AONRTCCurrent64BitValueGet(); + + /* Conservatively assume that we are just about to increment the RTC + Scale with the 4 MHz that the RAT is running + Add the RAT offset for RTC==0 */ + nCurrentTime += RF_RTC_TICK_INC; + nCurrentTime *= RF_SCALE_RTC_TO_4MHZ; + nCurrentTime += ((uint64_t)RF_ratSyncCmd.start.rat0) << RF_SHIFT_32_BITS; + nCurrentTime >>= RF_SHIFT_32_BITS; + } + + /* Return with the current value */ + return((uint32_t) nCurrentTime); +} + +/* + * ======== RF_postCmd ======== + * Post radio command + */ +RF_CmdHandle RF_postCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Try to allocate container */ + RF_Cmd* pCmd = RF_cmdAlloc(); + + /* If allocation succeeded */ + if (pCmd) + { + /* Stop inactivity clock if running */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Populate container with reset values */ + pCmd->pOp = pOp; + pCmd->ePri = ePri; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = (bmEvent | RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M) & ~RF_INTERNAL_IFG_MASK; + pCmd->pastifg = 0; + pCmd->flags = RF_CMD_ALLOC_FLAG; + pCmd->endTime = 0; + pCmd->endType = RF_EndNotSpecified; + pCmd->startTime = 0; + pCmd->startType = RF_StartNotSpecified; + pCmd->allowDelay = RF_AllowDelayAny; + pCmd->duration = 0; + pCmd->activityInfo = 0; + pCmd->coexPriority = RF_PriorityCoexDefault; + pCmd->coexRequest = RF_RequestCoexDefault; + + /* Update start time if absolute start time present in radio operation. */ + if (pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd->startType = RF_StartAbs; + pCmd->startTime = pOp->startTime; + } + + /* Cancel ongoing yielding */ + h->state.bYielded = false; + + /* Submit to pending command to the queue. */ + List_put(&RF_cmdQ.pPend, (List_Elem*)pCmd); + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if (List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) + { + RF_dispatchNextEvent(); + } + + /* Return with the command handle as success */ + cmdHandle = pCmd->ch; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with an error code */ + return(cmdHandle); +} + +/* + * ==================== RF_ScheduleCmdParams_init ============================ + * Initialize the parameter structure to be used with RF_scheduleCmd(). + */ +void RF_ScheduleCmdParams_init(RF_ScheduleCmdParams *pSchParams) +{ + /* Assert */ + DebugP_assert(pSchParams != NULL); + + /* Set the configuration to use the default values. */ + pSchParams->startTime = 0; + pSchParams->startType = RF_StartNotSpecified; + pSchParams->allowDelay = RF_AllowDelayAny; + pSchParams->endTime = 0; + pSchParams->endType = RF_EndNotSpecified; + pSchParams->duration = 0; + pSchParams->activityInfo = 0; + pSchParams->coexPriority = RF_PriorityCoexDefault; + pSchParams->coexRequest = RF_RequestCoexDefault; +} + +/* + * ==================== RF_scheduleCmd ============================ + * Process request to schedule new command from a particular client + */ +RF_CmdHandle RF_scheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Local variable declaration. */ + RF_Cmd* pCmd; + RF_Handle h2; + RF_ScheduleStatus status; + + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pOp != NULL); + + /* Local pointer to a radio commands. */ + RF_CmdHandle cmdHandle = (RF_CmdHandle)RF_ALLOC_ERROR; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Assign h2 to client that is not issuing the new command. + The client h is issuing the new command. */ + if (h == RF_Sch.clientHnd[0]) + { + h2 = RF_Sch.clientHnd[1]; + } + else + { + h2 = RF_Sch.clientHnd[0]; + } + + /* If client h2 already has, reject any new commands from h. */ + if (h2 && (ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Set the status value to schedule_error if we could not allocate space. */ + cmdHandle = (RF_CmdHandle) RF_ScheduleStatusError; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + } + else + { + /* Check if command queue has free entries and allocate RF_Op* container + if command queue is full reject the command. */ + pCmd = RF_cmdAlloc(); + + /* If allocation was successful. */ + if (pCmd) + { + /* Stop inactivity clock if running. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Increment the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost + 1) & N_CMD_MODMASK; + + /* Cache meta-data. */ + pCmd->pOp = pOp; + pCmd->ePri = RF_PriorityNormal; + pCmd->pCb = pCb; + pCmd->ch = RF_cmdQ.nSeqPost; + pCmd->pClient = h; + pCmd->bmEvent = bmEvent & ~RF_INTERNAL_IFG_MASK; + pCmd->flags = 0; + pCmd->pastifg = 0; + pCmd->endTime = pSchParams->endTime; + pCmd->endType = pSchParams->endType; + pCmd->startTime = pSchParams->startTime; + pCmd->startType = pSchParams->startType; + pCmd->allowDelay = pSchParams->allowDelay; + pCmd->duration = pSchParams->duration; + pCmd->activityInfo = pSchParams->activityInfo; + pCmd->coexPriority = pSchParams->coexPriority; + pCmd->coexRequest = pSchParams->coexRequest; + + /* Update the default endTime based on the scheduling parameters. */ + if (pSchParams->endType == RF_EndNotSpecified) + { + if (pSchParams->endTime != 0) + { + pCmd->endType = RF_EndAbs; + } + } + + /* Update the default startTime based on the command parameters. */ + if (pSchParams->startType == RF_StartNotSpecified) + { + if (pOp->startTrigger.triggerType == TRIG_ABSTIME) + { + pCmd->startType = RF_StartAbs; + pCmd->startTime = pOp->startTime; + } + } + + /* Find the last radio operation within the chain. */ + RF_Op* pEndOfChain = RF_findEndOfChain(pOp); + + /* Mark the context of the command based on it's ID and subscribe it + to the expected termination event. */ + if ((pEndOfChain->commandNo & RF_IEEE_ID_MASK) == RF_IEEE_FG_CMD) + { + pCmd->flags |= RF_CMD_FG_CMD_FLAG; + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M; + } + else + { + pCmd->bmEvent |= RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M; + } + + /* Cancel the radio free callback if new command is from the same client. */ + if ((RF_Sch.clientHndRadioFreeCb == h) && + (RF_Sch.issueRadioFreeCbFlags & RF_RADIOFREECB_PREEMPT_FLAG)) + { + RF_Sch.issueRadioFreeCbFlags &= ~RF_RADIOFREECB_PREEMPT_FLAG; + } + + /* Invoke the submit policy which shall identify where exactly the new command is being + inserted based on the application level prioritization table. */ + if (RFCC26XX_schedulerPolicy.submitHook == NULL) + { + status = RF_ScheduleStatusError; + } + else + { + /* Execute the scheduling logic and queue management. */ + status = RFCC26XX_schedulerPolicy.submitHook(pCmd, + RF_cmdQ.pCurrCmdBg, + RF_cmdQ.pCurrCmdFg, + &RF_cmdQ.pPend, + &RF_cmdQ.pDone); + + /* In case of rescheduling (re-entering the same command), the assigned handle will + not match and the counter need to be corrected. */ + if ((status != RF_ScheduleStatusError) && (RF_cmdQ.nSeqPost != pCmd->ch)) + { + /* Decrement the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost - 1) & N_CMD_MODMASK; + } + } + + /* Command was rejected. Either there was no slot available, or the timing did not fit. */ + if ((status == RF_ALLOC_ERROR) || (status == RF_ScheduleStatusError)) + { + /* Decrement the sequence number and mask the value. */ + RF_cmdQ.nSeqPost = (RF_cmdQ.nSeqPost - 1) & N_CMD_MODMASK; + + /* Store the reason and the handle why the callback is being invoked. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_CMDREJECT_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + + /* Ensure that the error code reflects the reason of rejection. */ + cmdHandle = (RF_CmdHandle) status; + } + else + { + /* Command was inserted. Return with the valid handle. */ + cmdHandle = pCmd->ch; + + /* Mark the command as being allocated. */ + pCmd->flags |= RF_CMD_ALLOC_FLAG; + + /* Cancel previous yielding. */ + h->state.bYielded = false; + + /* Trigger dispatcher if the timings need to be reconsidered. */ + if ((List_head(&RF_cmdQ.pPend) == (List_Elem*)pCmd) || + (pCmd->pOp->startTrigger.triggerType == TRIG_ABSTIME)) + { + RF_dispatchNextEvent(); + } + } + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the command handle. */ + return(cmdHandle); +} + +/* + * ======== RF_pendCmd ======== + * Pend on radio command + */ +RF_EventMask RF_pendCmd(RF_Handle h, RF_CmdHandle ch, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* If the command handle is invalid (i.e. RF_ALLOC_ERROR) */ + if (ch < 0) + { + /* Return with zero means the command was rejected earlier */ + return(0); + } + + /* Enter critical section */ + uint32_t key = SwiP_disable(); + + /* Find the command based on its handle in the command pool */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command was already disposed */ + if (!pCmd || !(pCmd->flags & RF_CMD_ALLOC_FLAG)) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Return with last command done event */ + return(RF_EventLastCmdDone); + } + + /* Expand the pend mask to accept RF_EventLastCmdDone and RF_EventLastFGCmdDone events even if it is not given explicitely */ + bmEvent = (bmEvent | RF_TERMINATION_EVENT_MASK); + + /* If the command is being executed, but the event we pending on has already happend (i.e. in a chain), + return the past events */ + if (pCmd->pastifg & bmEvent) + { + /* Exit critical section */ + SwiP_restore(key); + + /* Store the cause of returning */ + h->state.unpendCause = pCmd->pastifg & bmEvent; + + /* Clear the handled past events so it is possible to pend again */ + pCmd->pastifg &= ~h->state.unpendCause; + + /* Return with the events */ + return(h->state.unpendCause); + } + + /* Command has still not finished, override user callback with one that calls the user callback then posts to semaphore */ + if (pCmd->pCb != RF_syncCb) + { + /* Temporarily store the callback function */ + h->state.pCbSync = (void*)pCmd->pCb; + + /* Exhange the callback function: this will invoke the user callback and post to the semaphore if needed */ + pCmd->pCb = RF_syncCb; + } + + /* Store the event subscriptions in the clients context. This can only be one of the already enabled + interrupt sources by RF_postCmd (including RF_EventLastCmdDone) */ + h->state.eventSync = bmEvent; + + /* Exit critical section */ + SwiP_restore(key); + + /* Wait for semaphore */ + SemaphoreP_pend(&h->state.semSync, SemaphoreP_WAIT_FOREVER); + + /* Return the events that resulted in releasing the RF_pend() call */ + return(h->state.unpendCause); +} + +/* + * ======== RF_runCmd ======== + * Run to completion a posted command + */ +RF_EventMask RF_runCmd(RF_Handle h, RF_Op* pOp, RF_Priority ePri, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_postCmd(h, pOp, ePri, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_runScheduleCmd ======== + * Run to completion a scheduled command + */ +RF_EventMask RF_runScheduleCmd(RF_Handle h, RF_Op* pOp, RF_ScheduleCmdParams *pSchParams, RF_Callback pCb, RF_EventMask bmEvent) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Post the requested command */ + RF_CmdHandle ch = RF_scheduleCmd(h, pOp, pSchParams, pCb, bmEvent); + + /* If the command was accepted, pend until one of the special events occur */ + return(RF_pendCmd(h, ch, RF_TERMINATION_EVENT_MASK)); +} + +/* + * ======== RF_yieldCmd ======== + * Release client access + */ +void RF_yield(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Request the synchronization of RTC and RAT at next power down. This is trigged + by ceiling the active time to the maximum value. */ + RF_core.activeTimeUs = UINT32_MAX; + + /* Stop ongoing request access and issue callback if the radio is off */ + ClockP_stop((&h->state.clkReqAccess)); + + /* If all commands are done */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + if ((RF_core.status != RF_CoreStatusActive) && RF_Sch.issueRadioFreeCbFlags) + { + /* Exit critical section. */ + HwiP_restore(key); + + /* Invoke the radio free callback provided by the user. */ + RF_issueRadioFreeCb(RF_RADIOFREECB_REQACCESS_FLAG | + RF_RADIOFREECB_PREEMPT_FLAG | + RF_RADIOFREECB_CMDREJECT_FLAG); + + /* Enter critical section. */ + key = HwiP_disable(); + } + } + + /* If the radioFreeCb did not post new commands. */ + if (RF_cmdQ.nSeqDone == RF_cmdQ.nSeqPost) + { + /* All commands are done. Stop inactivity timer. */ + ClockP_stop(&RF_clkInactivityObj); + + /* Potentially power down the RF core. */ + RF_powerConstraintRelease(RF_PowerConstraintCmdQ); + } + else + { + /* There are still client commands that haven't finished. + Set flag to indicate immediate powerdown when last command is done. */ + h->state.bYielded = true; + } + + /* Exit critical section */ + HwiP_restore(key); +} + +/* + * ======== RF_cancelCmd ======== + * Cancel single radio command + */ +RF_Stat RF_cancelCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = (bool)(mode & RF_ABORT_FLUSH_ALL); + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Invoke the aborting process with the input arguments on a single command */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_flushCmd ======== + * Cancel multiple radio commands from a client + */ +RF_Stat RF_flushCmd(RF_Handle h, RF_CmdHandle ch, uint8_t mode) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Decode what method to be used for terminating the commands. */ + bool graceful = (bool)(mode & RF_ABORT_GRACEFULLY); + bool flush = true; + bool preempt = (bool)(mode & RF_ABORT_PREEMPTION); + + /* Abort multiple radio commands implicitly */ + return(RF_abortCmd(h, ch, graceful, flush, preempt)); +} + +/* + * ======== RF_Params_init ======== + * Initialize the RF_params to default value + */ +void RF_Params_init(RF_Params *params) +{ + /* Assert */ + DebugP_assert(params != NULL); + + /* Assign default values for RF_params */ + *params = RF_defaultParams; +} + +/* + * ======== RF_runImmediateCmd ======== + * Run immediate command + */ +RF_Stat RF_runImmediateCmd(RF_Handle h, uint32_t* pCmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, (uint32_t)pCmd, NULL)); +} + +/* + * ======== RF_runDirectCmd ======== + * Run direct command + */ +RF_Stat RF_runDirectCmd(RF_Handle h, uint32_t cmd) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Submit the command to the RF core */ + return(RF_runDirectImmediateCmd(h, cmd, NULL)); +} + +/* + * ======== RF_getRssi ======== + * Get RSSI value + */ +int8_t RF_getRssi(RF_Handle h) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Local variable. */ + uint32_t rawRssi; + + /* Read the RSSI value if possible. */ + RF_Stat status = RF_runDirectImmediateCmd(h, CMDR_DIR_CMD(CMD_GET_RSSI), &rawRssi); + + /* Decode the RSSI value if possible. */ + if (status == RF_StatCmdDoneSuccess) + { + return((int8_t)((rawRssi >> RF_SHIFT_16_BITS) & RF_CMDSTA_REG_VAL_MASK)); + } + else + { + return((int8_t)RF_GET_RSSI_ERROR_VAL); + } +} + +/* + * ======== RF_getInfo ======== + * Get RF driver info + */ +RF_Stat RF_getInfo(RF_Handle h, RF_InfoType type, RF_InfoVal *pValue) +{ + /* Prepare the default status value */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different flavor of requests */ + switch (type) + { + case RF_GET_CURR_CMD: + /* Get the handle of the currently running command. It can be conerted + to a pointer through the RF_getCmdOp() API. */ + if (RF_cmdQ.pCurrCmdBg) + { + pValue->ch = RF_cmdQ.pCurrCmdBg->ch; + } + else + { + status = RF_StatError; + } + break; + + case RF_GET_AVAIL_RAT_CH: + /* Get available user channels within the RAT timer. + These channels can be allocated and used by the application. */ + pValue->availRatCh = RF_ratModule.availableRatChannels; + break; + + case RF_GET_RADIO_STATE: + /* Get current radio state */ + pValue->bRadioState = (RF_core.status == RF_CoreStatusActive) ? true : false; + break; + + case RF_GET_CLIENT_LIST: + /* Copy the client pointer list ([0] -> client 1, [1] -> client 2) */ + pValue->pClientList[0] = RF_Sch.clientHnd[0]; + pValue->pClientList[1] = RF_Sch.clientHnd[1]; + break; + + case RF_GET_CLIENT_SWITCHING_TIME: + /* Copy the phy switching times to the RF_InfoVal structure */ + pValue->phySwitchingTimeInUs[0] = RF_Sch.clientHnd[0] ? RF_Sch.clientHnd[0]->clientConfig.nPhySwitchingDuration : 0; + pValue->phySwitchingTimeInUs[1] = RF_Sch.clientHnd[1] ? RF_Sch.clientHnd[1]->clientConfig.nPhySwitchingDuration : 0; + break; + + default: + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with a status code */ + return(status); +} + +/* + * ======== RF_getCmdOp ======== + * Get RF command + */ +RF_Op* RF_getCmdOp(RF_Handle h, RF_CmdHandle ch) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Find the command in the command pool based on its handle */ + RF_Cmd* pCmd = RF_cmdGet(h, ch, RF_CMD_ALLOC_FLAG); + + /* If the command is found */ + if (pCmd) + { + /* Return with the first operation in the command */ + return(pCmd->pOp); + } + else + { + /* Return with null in case of error */ + return(NULL); + } +} + +/* + * ======== RF_RatConfigCompare_init ======== + * Initialize RAT compare configuration + */ +void RF_RatConfigCompare_init(RF_RatConfigCompare* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCompare)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigCapture_init ======== + * Initialize RAT capture configuration + */ +void RF_RatConfigCapture_init(RF_RatConfigCapture* channelConfig) +{ + /* Assert */ + DebugP_assert(channelConfig != NULL); + + /* Set the values to default. */ + memset((void*)channelConfig, 0, sizeof(RF_RatConfigCapture)); + + /* Set the default allocation method to use any channel. */ + channelConfig->channel = RF_RatChannelAny; +} + +/* + * ======== RF_RatConfigOutput_init ======== + * Initialize RAT IO configuration + */ +void RF_RatConfigOutput_init(RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(ioConfig != NULL); + + /* Set the values to default. */ + memset((void*)ioConfig, 0, sizeof(RF_RatConfigOutput)); +} + +/* + * ======== RF_ratCompare ======== + * Set RAT compare + */ +RF_RatHandle RF_ratCompare(RF_Handle rfHandle, RF_RatConfigCompare* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into COMPARE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCompare, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratCapture ======== + * Set RAT capture + */ +RF_RatHandle RF_ratCapture(RF_Handle rfHandle, RF_RatConfigCapture* channelConfig, RF_RatConfigOutput* ioConfig) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Configure the RAT channel into CAPTURE mode. */ + return(RF_ratSetupChannel(rfHandle, RF_RatModeCapture, channelConfig->callback, channelConfig->channel, (void*) channelConfig, ioConfig)); +} + +/* + * ======== RF_ratDisableChannel ======== + * Disable RAT channel + */ +RF_Stat RF_ratDisableChannel(RF_Handle h, RF_RatHandle ratHandle) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Default return value */ + RF_Stat status = RF_StatError; + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Find the pointer to the RAT channel configuration. */ + RF_RatChannel* ratCh = RF_ratGetChannel(ratHandle); + + /* If the provided handler is valid. */ + if (ratCh && ratCh->status && (ratCh->pClient == h)) + { + /* If the RF core is active, abort the RAT event. */ + if (RF_core.status == RF_CoreStatusActive) + { + /* Calculate the configuration field of command (the channel we disable). */ + uint16_t config = (uint16_t)(RF_RAT_CH_LOWEST + ratCh->handle) << RF_SHIFT_8_BITS; + + /* Disable the channel within the RF core. + It has been checked that RAT channel to be disabled is owned by the input handle h. + Call the function that executes the disabling with RF_currClient as input argument in + instead of h in order to force the function to accept the disable request. This is + required in the case where the client that will disable a RAT channel is not the same + client as currently controlling the radio. + */ + status = RF_runDirectImmediateCmd(RF_currClient, ((uint32_t)CMDR_DIR_CMD_2BYTE(CMD_DISABLE_RAT_CH, config)), NULL); + + /* Free the container for further use. We do it after the direct command to be sure it is not powered down. + This will implicitely schedule the next event and run the power management accordingly. */ + RF_ratFreeChannel(ratCh); + } + else + { + /* Set status to be successful. */ + status = RF_StatCmdDoneSuccess; + + /* Free the container for further use. If possible, power down the radio. */ + RF_ratFreeChannel(ratCh); + + /* Recalculate the next wakeup event if the radio was off. */ + RF_dispatchNextEvent(); + } + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_control ======== + * RF control + */ +RF_Stat RF_control(RF_Handle h, int8_t ctrl, void *args) +{ + /* Assert */ + DebugP_assert(h != NULL); + + /* Prepare the return value for worst case scenario */ + RF_Stat status = RF_StatSuccess; + + /* Enter critical section */ + uint32_t key = HwiP_disable(); + + /* Serve the different requests */ + switch (ctrl) + { + case RF_CTRL_SET_INACTIVITY_TIMEOUT: + /* Update the inactivity timeout of the client. + This can be used if the value given at RF_open + need to be updated */ + h->clientConfig.nInactivityTimeout = *(uint32_t *)args; + break; + + case RF_CTRL_UPDATE_SETUP_CMD: + /* Enable a special boot process which can be controlled + through the config field of the radio setup command. + This will influence only the next power up sequence + and will be reset automatically afterwards. The special + power up process will require longer power up time, hence + the nPowerUpDuration need to be increased */ + h->clientConfig.bUpdateSetup = true; + h->clientConfig.nPowerUpDuration += RF_ANALOG_CFG_TIME_US; + h->clientConfig.nPowerUpDurationFs += RF_ANALOG_CFG_TIME_US; + break; + + case RF_CTRL_SET_POWERUP_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPowerUpDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN: + /* Configure the margin which is added to the measured + nPowerUpDuration. This can ensure that the commands + are executed on time, depending on the load of the + cpu */ + h->clientConfig.nPhySwitchingDurationMargin = *(uint32_t *)args; + break; + + case RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL: + /* Configure the tolerance value which is used to determine + the period when the RAT need to be syncronized to the RTC + due to the frequency offset */ + RF_errTolValInUs = *(uint32_t*)args; + break; + + case RF_CTRL_SET_POWER_MGMT: + /* The RF drivers power management can be enabled/disabled by + directly setting the power constraints from the application. + It is important that the order of actions align. */ + if (*(uint32_t*)args == 0) + { + RF_powerConstraintSet(RF_PowerConstraintDisallow); + } + else if (*(uint32_t*)args == 1) + { + RF_powerConstraintRelease(RF_PowerConstraintDisallow); + } + else + { + status = RF_StatInvalidParamsError; + } + break; + + case RF_CTRL_SET_HWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + HwiP_setPriority(INT_RFC_CPE_0, *(uint32_t *)args); + HwiP_setPriority(INT_RFC_HW_COMB, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_SWI_PRIORITY: + /* Changing priorities during run-time has constraints. + To not mess up with the RF driver, we require the RF + driver to be inactive. */ + if (RF_core.status || (List_head(&RF_cmdQ.pPend))) + { + status = RF_StatBusyError; + } + else + { + SwiP_setPriority(&RF_swiFsmObj, *(uint32_t *)args); + SwiP_setPriority(&RF_swiHwObj, *(uint32_t *)args); + } + break; + + case RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK: + /* Mask the available RAT channels manually. This can be used when + a particular RAT channel is used through oridnary radio operations + instead of the dedicated RAT APIs. */ + RF_ratModule.availableRatChannels = *(uint8_t *)args; + break; + + case RF_CTRL_COEX_CONTROL: + /* Pass this request on to the dynamically generated board file + event handler */ + RF_invokeGlobalCallback(RF_GlobalEventCoexControl, args); + break; + + default: + /* Request can not be served */ + status = RF_StatInvalidParamsError; + break; + } + + /* Exit critical section */ + HwiP_restore(key); + + /* Return with the status code */ + return(status); +} + +/* + * ======== RF_requestAccess ======== + * RF request access + */ +RF_Stat RF_requestAccess(RF_Handle h, RF_AccessParams *pParams) +{ + /* Assert. */ + DebugP_assert(h != NULL); + DebugP_assert(pParams != NULL); + + /* By default, the status is set to busy. */ + RF_Stat status = RF_StatBusyError; + + /* Convert the requested duration to us. */ + uint32_t durationInUs = RF_convertRatTicksToUs(pParams->duration); + + /* Check if the requested period is within the acceptable range. */ + if (durationInUs > RF_REQ_ACCESS_MAX_DUR_US) + { + /* Reject the request if not. */ + status = RF_StatInvalidParamsError; + } + + /* Enter critical section. */ + uint32_t key = HwiP_disable(); + + /* Determine the ID of the requesting client. */ + uint8_t clientIdx = 0; + if (h == RF_Sch.clientHnd[1]) + { + clientIdx = 1; + } + + /* Get handle to the other client. */ + RF_Handle h2 = RF_Sch.clientHnd[clientIdx ^ 0x1]; + + /* Check if the radio is free and if request can be served. + If possible update the RF_Sch structure and start the timer (RTC) + for the request access duration, else, return RF_StatBusyError. */ + if (!(h && ClockP_isActive(&h->state.clkReqAccess)) && + !(h2 && ClockP_isActive(&h2->state.clkReqAccess))) + { + /* Update the scheduler. */ + RF_Sch.accReq[clientIdx].duration = pParams->duration; + RF_Sch.accReq[clientIdx].priority = pParams->priority; + + /* Start timeout of the request. */ + RF_restartClockTimeout(&h->state.clkReqAccess, durationInUs/ClockP_getSystemTickPeriod()); + + /* Set status to success after the access was granted. */ + status = RF_StatSuccess; + } + else + { + /* In case the request can not be served, prepare for a notification + callback when the radio becomes available. */ + RF_Sch.issueRadioFreeCbFlags |= RF_RADIOFREECB_REQACCESS_FLAG; + RF_Sch.clientHndRadioFreeCb = h; + } + + /* Exit critical section. */ + HwiP_restore(key); + + /* Return the status. */ + return(status); +} + +/* + * ======== RF_setTxPower ======== + * Set the TX power of the client + */ +RF_Stat RF_setTxPower(RF_Handle handle, RF_TxPowerTable_Value value) +{ + /* Local variable stores the return value. */ + RF_Stat status; + + /* Placeholder of the command to be used to update the PA configuration within the RF core immediately. */ + RF_ConfigurePaCmd configurePaCmd; + + /* Update the setup command to make the changes permanent. */ + status = RF_updatePaConfiguration(handle->clientConfig.pRadioSetup, value, &configurePaCmd); + + /* If we managed to decode and cache the changes in the setup command. */ + if (status == RF_StatSuccess) + { + /* Execute the necessary command to apply the changes. It only takes effect if the RF core + is active and we configure the current client. The IO configuration can be re-evaluated when + the RF core issues the PA_CHANGED interrupt. */ + RF_runDirectImmediateCmd(handle, (uint32_t)&configurePaCmd, NULL); + } + + /* Return with the status. */ + return(status); +} + +/* + * ======== RF_getTxPower ======== + * Get the current TX power value + */ +RF_TxPowerTable_Value RF_getTxPower(RF_Handle handle) +{ + /* Default return value. */ + RF_TxPowerTable_Value value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA}; + + /* Local variables. */ + uint16_t* pTxPower = NULL; + uint32_t* pRegOverride = NULL; + uint32_t* pRegOverrideTxStd = NULL; + uint32_t* pRegOverrideTx20 = NULL; + uint32_t rawValue = RF_TxPowerTable_INVALID_VALUE; + + /* Decode if High Gain PA is available. */ + bool tx20FeatureAvailable = RF_decodeOverridePointers(handle->clientConfig.pRadioSetup, &pTxPower, &pRegOverride, &pRegOverrideTxStd, &pRegOverrideTx20); + + /* Continue the search for the proper value if the High PA is used. */ + if (*pTxPower == RF_TX20_ENABLED) + { + /* Returning the High Gain PA gain is only possible if the P device is in use. */ + if (tx20FeatureAvailable && pRegOverrideTxStd && pRegOverrideTx20) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverrideTx20, RF_TX20_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* Return the value found in the gain related list. */ + value.rawValue = rawValue; + value.paType = RF_TxPowerTable_HighPA; + } + } + else if (tx20FeatureAvailable) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverride, RF_TX20_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + /* As a backup option, parse the common list too. This is for backward compatibility + and new software shall not rely on this feature. */ + value.rawValue = rawValue; + value.paType = RF_TxPowerTable_HighPA; + } + } + } +#if defined(DeviceFamily_PARENT) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + else if (*pTxPower == RF_TXSUB1_ENABLED) + { + /* The Sub-1GHz gain override defualts to the regular override list, but will be in the standard TX override list when defined. */ + if (pRegOverrideTxStd) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverrideTxStd, RF_TXSUB1_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + value.rawValue = rawValue; + } + } + else if (pRegOverride) + { + if (RF_getPAOverrideOffsetAndValue(pRegOverride, RF_TXSUB1_PATTERN, &rawValue) != RF_TX_OVERRIDE_INVALID_OFFSET) + { + value.rawValue = rawValue; + } + } + } +#endif + else + { + /* The value in the .txPower field represents the output power.*/ + value.rawValue = *pTxPower; + } + + /* Return with the decoded value. */ + return(value); +} + +/* + * ======== RF_TxPowerTable_findPowerLevel ======== + * Retrieves a power level in dBm for a given power configuration value. + */ +int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_TxPowerTable_Value value) +{ + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; (table[i].power != RF_TxPowerTable_INVALID_DBM) && + (table[i].value.rawValue != RF_TxPowerTable_INVALID_VALUE); i++) + { + if (((uint32_t)table[i].value.paType == (uint32_t)value.paType) && + ((uint32_t)table[i].value.rawValue == (uint32_t)value.rawValue)) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + /* Return with the power level in dBm or with the + termination value RF_TxPowerTable_INVALID_DBM. */ + return(table[i].power); +} + +/* + * ======== RF_TxPowerTable_findValue ======== + * Retrieves a power configuration value for a given power level in dBm. + */ +RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel) +{ + /* Local variable stores an invalid value. */ + RF_TxPowerTable_Value invalidValue = { .rawValue = RF_TxPowerTable_INVALID_VALUE, + .paType = RF_TxPowerTable_DefaultPA }; + + /* Handle special input argument. */ + if (powerLevel == RF_TxPowerTable_MIN_DBM) + { + return(table[0].value); + } + else + { + /* Iterate through the power table. We do not verify against nullptr. */ + uint32_t i; + for (i=0; ((int8_t)table[i].power != (int8_t)RF_TxPowerTable_INVALID_DBM) && + ((uint32_t)table[i].value.rawValue != (uint32_t)RF_TxPowerTable_INVALID_VALUE); i++) + { + if (table[i].power > powerLevel) + { + /* Break the loop on the first entry which satisfies + the lower-or-equal criterion toward the input argument. */ + break; + } + } + + if (i == 0) + { + /* If the first entry is already larger, then the requested + power level is invalid. */ + return(invalidValue); + } + else + { + /* Return with a valid RF_TxPowerTable_Value or with the + maximum value in the table. */ + return(table[i-1].value); + } + } +} + +/* + * ======== RF_enableHPOSCTemperatureCompensation ======== + * Initializes the temperature compensation monitoring (SW TCXO) + * This function enables RF synthesizer temperature compensation + * It is intended for use on the SIP or BAW devices where compensation + * coefficients are available inside the chip. + * + * The name of the function is a misnomer, as it does not only apply to + * HPOSC (BAW) configuration, but will generically enable SW TCXO. + */ +RF_Stat RF_enableHPOSCTemperatureCompensation(void) +{ + int_fast16_t status; + + Temperature_init(); + + int16_t currentTemperature = Temperature_getTemperature(); + + status = Temperature_registerNotifyRange(&RF_hposcRfCompNotifyObj, + currentTemperature + RF_TEMP_LIMIT_3_DEGREES_CELSIUS, + currentTemperature - RF_TEMP_LIMIT_3_DEGREES_CELSIUS, + RF_hposcRfCompensateFxn, + (uintptr_t)NULL); + + pfnUpdateHposcOverride = &RF_updateHpOscOverride; + pfnTemperatureUnregisterNotify = &Temperature_unregisterNotify; + + if (status != Temperature_STATUS_SUCCESS) + { + return(RF_StatInvalidParamsError); + } + return(RF_StatSuccess); +} diff --git a/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.c b/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.c new file mode 100644 index 00000000..1083ada0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== RNGCC26XX.c ======== + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +extern uint8_t RNG_instancePool[]; + +extern const TRNGCC26XX_HWAttrs RNGCC26XX_trngHWAttrs; + +typedef struct RNGCC26XX_OperationParameters_ RNGCC26XX_OperationParameters; + +typedef bool (*RNGCC26XX_validator)(RNGCC26XX_OperationParameters *opParams); + +/* + * These values are needed when operating in callback mode. + */ +struct RNGCC26XX_OperationParameters_ +{ + RNG_Handle rngHandle; + uint8_t *output; + size_t outputBitLength; + CryptoKey *destinationKey; + CryptoUtils_Endianess endianess; + RNGCC26XX_validator validator; + const uint8_t *lowerLimit; + const uint8_t *upperLimit; +}; + +typedef struct +{ + /* No data in the structure should be read or written without first taking this semaphore. */ + SemaphoreP_Struct accessSemaphore; + size_t poolLevel; + RNGCC26XX_OperationParameters operationalParameters; +} RNGCC26XX_Instance; + +RNGCC26XX_Instance RNG_instanceData; + +static bool RNGCC26XX_isInitialized = false; + +/*** Prototypes ***/ +static int_fast16_t RNGCC26XX_translateTRNGStatus(int_fast16_t trngStatus); +static int_fast16_t RNGCC26XX_generateEntropy(TRNG_Handle trngHandle, uint8_t *byteDest, size_t byteSize); +static void RNGCC26XX_invokeCallback(RNG_Handle handle, + uint8_t *randomBits, + size_t bitLength, + CryptoKey *generatedKey, + int_fast16_t returnValue); +static void RNGCC26XX_trngCallbackFxn(TRNG_Handle trngHandle, + int_fast16_t returnValue, + uint8_t *trngOutputBytes, + size_t trngOutputSize); +static size_t RNGCC26XX_getEntropyFromPool(void *dest, size_t byteSize); +static bool RNGCC26XX_checkRange(RNGCC26XX_OperationParameters *opParams); +static int_fast16_t RNGCC26XX_getValidatedNumber(RNG_Handle handle, + void *randomNumber, + size_t randomNumberBitLength, + CryptoKey *key, + CryptoUtils_Endianess endianess, + RNGCC26XX_validator validator, + const void *lowerLimit, + const void *upperLimit); + +static int_fast16_t RNGCC26XX_translateTRNGStatus(int_fast16_t trngStatus) +{ + int_fast16_t returnValue; + + switch (trngStatus) + { + case TRNG_STATUS_SUCCESS: + returnValue = RNG_STATUS_SUCCESS; + break; + case TRNG_STATUS_ERROR: + returnValue = RNG_STATUS_ERROR; + break; + case TRNG_STATUS_RESOURCE_UNAVAILABLE: + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + break; + case TRNG_STATUS_CANCELED: + returnValue = RNG_STATUS_CANCELED; + break; + default: + returnValue = RNG_STATUS_ERROR; + break; + } + + return returnValue; +} + +static int_fast16_t RNGCC26XX_generateEntropy(TRNG_Handle trngHandle, uint8_t *byteDest, size_t byteSize) +{ + int_fast16_t returnValue; + int_fast16_t trngResult; + + trngResult = TRNG_getRandomBytes(trngHandle, byteDest, byteSize); + + returnValue = RNGCC26XX_translateTRNGStatus(trngResult); + + return returnValue; +} + +static void RNGCC26XX_invokeCallback(RNG_Handle handle, + uint8_t *randomBits, + size_t bitLength, + CryptoKey *generatedKey, + int_fast16_t returnValue) +{ + RNG_Params *params = &((RNGCC26XX_Object *)handle->object)->rngParams; + + if ((generatedKey != NULL) && (params->cryptoKeyCallbackFxn != NULL)) + { + params->cryptoKeyCallbackFxn(handle, returnValue, generatedKey); + } + else + { + if (params->randomBitsCallbackFxn != NULL) + { + params->randomBitsCallbackFxn(handle, returnValue, randomBits, bitLength); + } + } +} + +static void RNGCC26XX_trngCallbackFxn(TRNG_Handle trngHandle, + int_fast16_t returnValue, + uint8_t *trngOutputBytes, + size_t trngOutputSize) +{ + RNGCC26XX_OperationParameters *opParams = &RNG_instanceData.operationalParameters; + int_fast16_t rngStatus; + uint8_t bitMask; + size_t totalByteSize; + bool isValid = true; + + rngStatus = RNGCC26XX_translateTRNGStatus(returnValue); + + if (rngStatus == RNG_STATUS_SUCCESS) + { + + totalByteSize = (opParams->outputBitLength + 7u) >> 3u; + + /* Mask out any extra bits copied */ + bitMask = (2u << (((opParams->outputBitLength + 7u) % 8u))) - 1u; + if (opParams->endianess == CryptoUtils_ENDIANESS_BIG) + { + opParams->output[0] &= bitMask; + } + else + { + opParams->output[totalByteSize - 1u] &= bitMask; + } + + /* Check resulting value against limits (if any). If lowerLimit is set, the upperLimit must also be set. */ + if (opParams->validator != NULL) + { + isValid = opParams->validator(opParams); + + if (!isValid) + { + rngStatus = RNGCC26XX_generateEntropy(trngHandle, opParams->output, totalByteSize); + } + } + } + + if ((rngStatus != RNG_STATUS_SUCCESS) || isValid) + { + RNGCC26XX_invokeCallback(opParams->rngHandle, + opParams->output, + opParams->outputBitLength, + opParams->destinationKey, + rngStatus); + SemaphoreP_post(&RNG_instanceData.accessSemaphore); + } +} + +/* + * Precondition: RNG_instanceData.accessSemaphore has been taken. + * + * Returns number of _bytes_ remaining to fulfill the request (rounded up from number of bits remaining.) + * These will have to be generated since a non-zero return value indicates the pool is now empty. + */ +static size_t RNGCC26XX_getEntropyFromPool(void *dest, size_t byteSize) +{ + + uint8_t *byteDest = (uint8_t *)dest; + + size_t bytesRemaining = byteSize; + size_t bytesToCopy; + + /* Get entropy from pool first */ + if ((bytesRemaining > 0u) && (RNG_instanceData.poolLevel > 0u)) + { + bytesToCopy = (bytesRemaining > RNG_instanceData.poolLevel) ? RNG_instanceData.poolLevel : bytesRemaining; + + (void)memcpy(byteDest, &RNG_instancePool[RNG_instanceData.poolLevel - bytesToCopy], bytesToCopy); + CryptoUtils_memset(&RNG_instancePool[RNG_instanceData.poolLevel - bytesToCopy], + RNG_poolByteSize, + 0, + bytesToCopy); + RNG_instanceData.poolLevel -= bytesToCopy; + + bytesRemaining -= bytesToCopy; + } + + return bytesRemaining; +} + +static bool RNGCC26XX_checkRange(RNGCC26XX_OperationParameters *opParams) +{ + return CryptoUtils_isNumberInRange(opParams->output, + opParams->outputBitLength, + opParams->endianess, + opParams->lowerLimit, + opParams->upperLimit); +} + +static int_fast16_t RNGCC26XX_getValidatedNumber(RNG_Handle handle, + void *randomNumber, + size_t randomNumberBitLength, + CryptoKey *key, + CryptoUtils_Endianess endianess, + RNGCC26XX_validator validator, + const void *lowerLimit, + const void *upperLimit) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + RNGCC26XX_Object *object; + size_t bytesToGenerate; + size_t byteSize; + uint8_t *byteDestination; + uint8_t bitMask; + bool isValid = false; + bool trngCallbackExpected = false; + + if ((handle == NULL) || (randomNumber == NULL) || (randomNumberBitLength >= RNG_MAX_BIT_LENGTH)) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + object = (RNGCC26XX_Object *)handle->object; + + if (SemaphoreP_pend(&RNG_instanceData.accessSemaphore, object->rngParams.timeout) != SemaphoreP_OK) + { + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + } + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + RNG_instanceData.operationalParameters.rngHandle = handle; + RNG_instanceData.operationalParameters.outputBitLength = randomNumberBitLength; + RNG_instanceData.operationalParameters.output = randomNumber; + RNG_instanceData.operationalParameters.destinationKey = key; + RNG_instanceData.operationalParameters.endianess = endianess; + RNG_instanceData.operationalParameters.validator = validator; + RNG_instanceData.operationalParameters.lowerLimit = lowerLimit; + RNG_instanceData.operationalParameters.upperLimit = upperLimit; + + byteSize = (randomNumberBitLength + 7u) >> 3u; + byteDestination = (uint8_t *)randomNumber; + bitMask = (2u << (((randomNumberBitLength + 7u) % 8u))) - 1u; + } + + while ((returnValue == RNG_STATUS_SUCCESS) && !isValid && !trngCallbackExpected) + { + + bytesToGenerate = RNGCC26XX_getEntropyFromPool(byteDestination, byteSize); + + if (bytesToGenerate > 0u) + { + + if (object->rngParams.returnBehavior == RNG_RETURN_BEHAVIOR_CALLBACK) + { + trngCallbackExpected = true; + } + + returnValue = RNGCC26XX_generateEntropy(&object->trngConfig, + &byteDestination[byteSize - bytesToGenerate], + bytesToGenerate); + + if (returnValue != RNG_STATUS_SUCCESS) + { + /* + * Regardless of return behavior, if there was an error, + * it is expected the TRNG callback will not execute. + */ + trngCallbackExpected = false; + } + } + + if (!trngCallbackExpected) + { + /* All bytes needed have been obtained, Mask off extra bits in MSB */ + if (endianess == CryptoUtils_ENDIANESS_BIG) + { + byteDestination[0] &= bitMask; + } + else + { + byteDestination[byteSize - 1u] &= bitMask; + } + + if (validator != NULL) + { + isValid = validator(&RNG_instanceData.operationalParameters); + } + else + { + isValid = true; + } + } + } + + if (!trngCallbackExpected) + { + if (returnValue == RNG_STATUS_SUCCESS) + { + if (object->rngParams.returnBehavior == RNG_RETURN_BEHAVIOR_CALLBACK) + { + RNGCC26XX_invokeCallback(handle, randomNumber, randomNumberBitLength, key, returnValue); + } + } + + SemaphoreP_post(&RNG_instanceData.accessSemaphore); + } + + return returnValue; +} + +void RNG_Params_init(RNG_Params *params) +{ + *params = RNG_defaultParams; +} + +int_fast16_t RNG_init(void) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + + if (RNGCC26XX_isInitialized == false) + { + RNG_instanceData.poolLevel = 0u; + if (SemaphoreP_constructBinary(&RNG_instanceData.accessSemaphore, 1) == NULL) + { + returnValue = RNG_STATUS_ERROR; + } + else + { + TRNG_init(); + RNGCC26XX_isInitialized = true; + } + } + + return returnValue; +} + +RNG_Handle RNG_construct(const RNG_Config *config, const RNG_Params *params) +{ + const RNG_Config *handle; + RNGCC26XX_Object *object; + TRNG_Params trngParams; + + handle = (const RNG_Config *)config; + object = (RNGCC26XX_Object *)handle->object; + + TRNG_Params_init(&trngParams); + + if (params == NULL) + { + trngParams.returnBehavior = (TRNG_ReturnBehavior)RNG_defaultParams.returnBehavior; + } + else + { + trngParams.returnBehavior = (TRNG_ReturnBehavior)params->returnBehavior; + } + + trngParams.randomBytesCallbackFxn = RNGCC26XX_trngCallbackFxn; + + object->trngConfig.object = &object->trngObject; + object->trngConfig.hwAttrs = &RNGCC26XX_trngHWAttrs; + + if (TRNG_construct(&object->trngConfig, &trngParams) != NULL) + { + /* If params are NULL, use defaults */ + if (params == NULL) + { + object->rngParams = RNG_defaultParams; + } + else + { + object->rngParams = *params; + } + } + else + { + handle = NULL; + } + + return (RNG_Handle)handle; +} + +void RNG_close(RNG_Handle handle) +{ + RNGCC26XX_Object *object; + + if (handle != NULL) + { + object = (RNGCC26XX_Object *)handle->object; + + TRNG_close(&object->trngConfig); + } +} + +int_fast16_t RNG_getRandomBits(RNG_Handle handle, void *randomBits, size_t randomBitsLength) +{ + + return RNGCC26XX_getValidatedNumber(handle, + randomBits, + randomBitsLength, + NULL, + CryptoUtils_ENDIANESS_LITTLE, + NULL, + NULL, + NULL); +} + +int_fast16_t RNG_getLERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength) +{ + + return RNGCC26XX_getValidatedNumber(handle, + randomNumber, + randomNumberBitLength, + NULL, + CryptoUtils_ENDIANESS_LITTLE, + &RNGCC26XX_checkRange, + lowerLimit, + upperLimit); +} + +int_fast16_t RNG_getBERandomNumberInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + void *randomNumber, + size_t randomNumberBitLength) +{ + + return RNGCC26XX_getValidatedNumber(handle, + randomNumber, + randomNumberBitLength, + NULL, + CryptoUtils_ENDIANESS_BIG, + &RNGCC26XX_checkRange, + lowerLimit, + upperLimit); +} + +int_fast16_t RNG_generateKey(RNG_Handle handle, CryptoKey *key) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + uint8_t *randomBits; + size_t randomBitsLength; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (key->u.plaintext.keyLength > (RNG_MAX_BIT_LENGTH >> 3u)) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + + if (returnValue == RNG_STATUS_SUCCESS) + { + randomBits = key->u.plaintext.keyMaterial; + randomBitsLength = key->u.plaintext.keyLength << 3u; /* Bytes to bits */ + + returnValue = RNGCC26XX_getValidatedNumber(handle, + randomBits, + randomBitsLength, + key, + CryptoUtils_ENDIANESS_LITTLE, + NULL, + NULL, + NULL); + } + + return returnValue; +} + +int_fast16_t RNG_generateLEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength) +{ + int_fast16_t returnValue; + uint8_t *randomBits; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + else + { + + randomBits = key->u.plaintext.keyMaterial; + + returnValue = RNGCC26XX_getValidatedNumber(handle, + randomBits, + randomNumberBitLength, + key, + CryptoUtils_ENDIANESS_LITTLE, + &RNGCC26XX_checkRange, + lowerLimit, + upperLimit); + } + + return returnValue; +} + +int_fast16_t RNG_generateBEKeyInRange(RNG_Handle handle, + const void *lowerLimit, + const void *upperLimit, + CryptoKey *key, + size_t randomNumberBitLength) +{ + int_fast16_t returnValue; + uint8_t *randomBits; + + if (key->encoding != CryptoKey_BLANK_PLAINTEXT) + { + returnValue = RNG_STATUS_INVALID_INPUTS; + } + else + { + randomBits = key->u.plaintext.keyMaterial; + + returnValue = RNGCC26XX_getValidatedNumber(handle, + randomBits, + randomNumberBitLength, + key, + CryptoUtils_ENDIANESS_BIG, + &RNGCC26XX_checkRange, + lowerLimit, + upperLimit); + } + + return returnValue; +} + +int_fast16_t RNG_fillPoolIfLessThan(size_t bytes) +{ + int_fast16_t returnValue = RNG_STATUS_SUCCESS; + size_t bytesNeeded; + TRNG_Params trngParams; + TRNGCC26XX_Object trngObject; + TRNG_Config trngConfig; + TRNG_Handle trngHandle; + + TRNG_init(); + + TRNG_Params_init(&trngParams); + trngConfig.object = &trngObject; + trngConfig.hwAttrs = &RNGCC26XX_trngHWAttrs; + trngObject.isOpen = false; + + trngHandle = TRNG_construct(&trngConfig, &trngParams); + + if (trngHandle == NULL) + { + returnValue = RNG_STATUS_ERROR; + } + else if (SemaphoreP_pend(&RNG_instanceData.accessSemaphore, SemaphoreP_WAIT_FOREVER) != SemaphoreP_OK) + { + returnValue = RNG_STATUS_RESOURCE_UNAVAILABLE; + TRNG_close(trngHandle); + } + else + { + if (RNG_instanceData.poolLevel < bytes) + { + bytesNeeded = RNG_poolByteSize - RNG_instanceData.poolLevel; + + if (bytesNeeded != 0) + { + returnValue = RNGCC26XX_generateEntropy(trngHandle, + &RNG_instancePool[RNG_instanceData.poolLevel], + bytesNeeded); + + if (returnValue == RNG_STATUS_SUCCESS) + { + RNG_instanceData.poolLevel = RNG_poolByteSize; + } + } + } + + SemaphoreP_post(&RNG_instanceData.accessSemaphore); + + TRNG_close(trngHandle); + } + + return returnValue; +} + +int_fast16_t RNG_cancelOperation(RNG_Handle handle) +{ + RNGCC26XX_Object *object; + int_fast16_t returnValue = RNG_STATUS_INVALID_INPUTS; + + if (handle != NULL) + { + object = (RNGCC26XX_Object *)handle->object; + returnValue = TRNG_cancelOperation(&object->trngConfig); + } + + return returnValue; +} diff --git a/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.h b/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.h new file mode 100644 index 00000000..9235790b --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/rng/RNGCC26XX.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file RNGCC26XX.h + * + * @brief RNG driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the RNG_config + * structure. + * + * The CC26XX family has a general purpose TRNG. This implementation of the + * RNG driver for the CC26XX family uses the TRNG for all entropy generation. + * + */ + +#ifndef ti_drivers_rnd_RNGCC26XX__include +#define ti_drivers_rnd_RNGCC26XX__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! \cond Internal APIs */ + +/*! + * @brief RNGCC26XX Object + * + * \note The application must not access any member variables of this structure! + */ +typedef struct +{ + TRNG_Config trngConfig; + TRNGCC26XX_Object trngObject; + RNG_Params rngParams; + volatile bool operationInProgress; + bool operationCanceled; +} RNGCC26XX_Object; + +/*! \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_rnd_RNGCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/sd/SDSPI.c b/simplelink_lpf2/source/ti/drivers/sd/SDSPI.c new file mode 100644 index 00000000..0b4cdbf3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sd/SDSPI.c @@ -0,0 +1,840 @@ +/* + * Copyright (c) 2017-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SDSPI.c ======== + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Definitions for MMC/SDC command */ +#define CMD0 (0x40 + 0) /* GO_IDLE_STATE */ +#define CMD1 (0x40 + 1) /* SEND_OP_COND */ +#define CMD8 (0x40 + 8) /* SEND_IF_COND */ +#define CMD9 (0x40 + 9) /* SEND_CSD */ +#define CMD10 (0x40 + 10) /* SEND_CID */ +#define CMD12 (0x40 + 12) /* STOP_TRANSMISSION */ +#define CMD16 (0x40 + 16) /* SET_BLOCKLEN */ +#define CMD17 (0x40 + 17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40 + 18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40 + 23) /* SET_BLOCK_COUNT */ +#define CMD24 (0x40 + 24) /* WRITE_BLOCK */ +#define CMD25 (0x40 + 25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD41 (0x40 + 41) /* SEND_OP_COND (ACMD) */ +#define CMD55 (0x40 + 55) /* APP_CMD */ +#define CMD58 (0x40 + 58) /* READ_OCR */ +#define START_BLOCK_TOKEN (0xFE) +#define START_MULTIBLOCK_TOKEN (0xFC) +#define STOP_MULTIBLOCK_TOKEN (0xFD) + +#define SD_SECTOR_SIZE (512) + +#define DRIVE_NOT_MOUNTED ((uint16_t)~0) + +void SDSPI_close(SD_Handle handle); +int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, void *arg); +uint_fast32_t SDSPI_getNumSectors(SD_Handle handle); +uint_fast32_t SDSPI_getSectorSize(SD_Handle handle); +int_fast16_t SDSPI_initialize(SD_Handle handle); +void SDSPI_init(SD_Handle handle); +SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params); +int_fast16_t SDSPI_read(SD_Handle handle, void *buf, int_fast32_t sector, uint_fast32_t sectorCount); +int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, int_fast32_t sector, uint_fast32_t sectorCount); + +static inline void assertCS(SDSPI_HWAttrs const *hwAttrs); +static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs); +static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count); +static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg); +static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, void *txBuf, size_t count); +static bool waitUntilReady(SPI_Handle handle); +static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, uint8_t token); + +/* SDSPI function table for SDSPI implementation */ +const SD_FxnTable SDSPI_fxnTable = {SDSPI_close, + SDSPI_control, + SDSPI_getNumSectors, + SDSPI_getSectorSize, + SDSPI_init, + SDSPI_initialize, + SDSPI_open, + SDSPI_read, + SDSPI_write}; + +/* + * ======== SDSPI_close ======== + */ +void SDSPI_close(SD_Handle handle) +{ + SDSPI_Object *object = handle->object; + + if (object->spiHandle) + { + SPI_close(object->spiHandle); + object->spiHandle = NULL; + } + + if (object->lockSem) + { + SemaphoreP_delete(object->lockSem); + object->lockSem = NULL; + } + + object->cardType = SD_NOCARD; + object->isOpen = false; +} + +/* + * ======== SDSPI_control ======== + */ +int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (SD_STATUS_UNDEFINEDCMD); +} + +/* + * ======== SDSPI_getNumSectors ======== + */ +uint_fast32_t SDSPI_getNumSectors(SD_Handle handle) +{ + uint8_t n; + uint8_t csd[16]; + uint16_t csize; + uint32_t sectors = 0; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + assertCS(hwAttrs); + + /* Get number of sectors on the disk (uint32_t) */ + if ((sendCmd(object->spiHandle, CMD9, 0) == 0) && recvDataBlock(object->spiHandle, csd, 16)) + { + /* SDC ver 2.00 */ + if ((csd[0] >> 6) == 1) + { + csize = csd[9] + (csd[8] << 8) + 1; + sectors = csize << 10; + } + /* MMC or SDC ver 1.XX */ + else + { + n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; + + csize = (csd[8] >> 6) + ((uint16_t)csd[7] << 2) + ((uint16_t)(csd[6] & 3) << 10) + 1; + sectors = (uint32_t)csize << (n - 9); + } + } + + deassertCS(hwAttrs); + + SemaphoreP_post(object->lockSem); + + return (sectors); +} + +/* + * ======== SDSPI_getSectorSize ======== + */ +uint_fast32_t SDSPI_getSectorSize(SD_Handle handle) +{ + return (SD_SECTOR_SIZE); +} + +/* + * ======== SDSPI_init ======== + */ +void SDSPI_init(SD_Handle handle) +{ + GPIO_init(); + SPI_init(); +} + +/* + * ======== SDSPI_initialize ======== + */ +int_fast16_t SDSPI_initialize(SD_Handle handle) +{ + SD_CardType cardType = SD_NOCARD; + uint8_t i; + uint8_t ocr[4]; + uint8_t txDummy[10] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + SPI_Params spiParams; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * The CS line should not be asserted when attempting to put the + * SD card into SPI mode. + */ + deassertCS(hwAttrs); + + /* + * To put the SD card in SPI mode we must keep the TX line high while + * toggling the clock line several times. To do this we transmit 0xFF + * 10 times. Do not assert CS during this time + */ + status = spiTransfer(object->spiHandle, NULL, &txDummy, 10); + if (status != SD_STATUS_SUCCESS) + { + SemaphoreP_post(object->lockSem); + return (status); + } + + /* Now select the SD Card's chip select to send CMD0 command */ + assertCS(hwAttrs); + + /* + * Send CMD0 to put the SD card in idle mode. Depending on the previous + * state of the SD card, this may take up to a couple hundred milliseconds. + * Rather than delay between attempts, we try up to 255 attempts. + * Failure is returned if the card does not respond will a valid byte + * within 255 attempts. When the card will respond with 0x1 when its + * in idle mode. + */ + for (i = 255, status = 0xFF; i > 0 && status != 0x1; i--) + { + status = sendCmd(object->spiHandle, CMD0, 0); + } + + /* If the card never transitioned into idle mode */ + if (status != 0x1) + { + deassertCS(hwAttrs); + SemaphoreP_post(object->lockSem); + return (SD_STATUS_ERROR); + } + + /* + * Proceed with initialization since the SD Card is in the idle state + * Determine what SD Card version we are dealing with + * Depending on which SD Card version, we need to send different SD + * commands to the SD Card, which will have different response fields. + */ + if (sendCmd(object->spiHandle, CMD8, 0x1AA) == 1) + { + /* SD Version 2.0 or higher */ + status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); + if (status == SD_STATUS_SUCCESS) + { + /* + * Ensure that the card's voltage range is valid + * The card can work at VDD range of 2.7-3.6V + */ + if ((ocr[2] == 0x01) && (ocr[3] == 0xAA)) + { + /* + * Wait for data packet in timeout of 1s - status used to + * indicate if a timeout occurred before operation + * completed. + */ + status = SD_STATUS_ERROR; + timeout = 1000000 / ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + + do + { + /* ACMD41 with HCS bit */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && + (sendCmd(object->spiHandle, CMD41, 1UL << 30) == 0)) + { + status = SD_STATUS_SUCCESS; + break; + } + currentTime = ClockP_getSystemTicks(); + } while ((currentTime - startTime) < timeout); + + /* + * Check CCS bit to determine which type of capacity we are + * dealing with + */ + if ((status == SD_STATUS_SUCCESS) && sendCmd(object->spiHandle, CMD58, 0) == 0) + { + status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); + if (status == SD_STATUS_SUCCESS) + { + cardType = (ocr[0] & 0x40) ? SD_SDHC : SD_SDSC; + } + } + } + } + } + else + { + /* SDC Version 1 or MMC */ + /* + * The card version is not SDC V2+ so check if we are dealing with a + * SDC or MMC card + */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && (sendCmd(object->spiHandle, CMD41, 0) <= 1)) + { + cardType = SD_SDSC; + } + else + { + cardType = SD_MMC; + } + + /* + * Wait for data packet in timeout of 1s - status used to + * indicate if a timeout occurred before operation + * completed. + */ + status = SD_STATUS_ERROR; + timeout = 1000000 / ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do + { + if (cardType == SD_SDSC) + { + /* ACMD41 */ + if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && (sendCmd(object->spiHandle, CMD41, 0) == 0)) + { + status = SD_STATUS_SUCCESS; + break; + } + } + else + { + /* CMD1 */ + if (sendCmd(object->spiHandle, CMD1, 0) == 0) + { + status = SD_STATUS_SUCCESS; + break; + } + } + currentTime = ClockP_getSystemTicks(); + } while ((currentTime - startTime) < timeout); + + /* Select R/W block length */ + if ((status == SD_STATUS_ERROR) || (sendCmd(object->spiHandle, CMD16, SD_SECTOR_SIZE) != 0)) + { + cardType = SD_NOCARD; + } + } + + deassertCS(hwAttrs); + + object->cardType = cardType; + + /* Check to see if a card type was determined */ + if (cardType == SD_NOCARD) + { + status = SD_STATUS_ERROR; + } + else + { + /* Reconfigure the SPI to operate @ 2.5 MHz */ + SPI_close(object->spiHandle); + + SPI_Params_init(&spiParams); + spiParams.bitRate = 2500000; + object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); + status = (object->spiHandle == NULL) ? SD_STATUS_ERROR : SD_STATUS_SUCCESS; + } + + SemaphoreP_post(object->lockSem); + + return (status); +} + +/* + * ======== SDSPI_open ======== + */ +SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params) +{ + uintptr_t key; + int_fast16_t status; + SPI_Params spiParams; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + /* Configure the SPI CS pin as output set high */ + status = GPIO_setConfig(hwAttrs->spiCsGpioIndex, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); + if (status != GPIO_STATUS_SUCCESS) + { + object->isOpen = false; + + return (NULL); + } + + object->lockSem = SemaphoreP_createBinary(1); + if (object->lockSem == NULL) + { + object->isOpen = false; + + return (NULL); + } + + /* + * SPI is initially set to 400 kHz to perform SD initialization. This is + * is done to ensure compatibility with older SD cards. Once the card has + * been initialized (in SPI mode) the SPI peripheral will be closed & + * reopened at 2.5 MHz. + */ + SPI_Params_init(&spiParams); + spiParams.bitRate = 400000; + object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); + if (object->spiHandle == NULL) + { + SDSPI_close(handle); + + return (NULL); + } + + /* Ensure the CS line is de-asserted. */ + deassertCS(hwAttrs); + + return (handle); +} + +/* + * ======== SDSPI_read ======== + */ +int_fast16_t SDSPI_read(SD_Handle handle, void *buf, int_fast32_t sector, uint_fast32_t sectorCount) +{ + uint8_t ffByte = 0xFF; + int_fast16_t status = SD_STATUS_ERROR; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (sectorCount == 0) + { + return (SD_STATUS_ERROR); + } + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * On a SDSC card, the sector address is a byte address on the SD Card + * On a SDHC card, the sector addressing is via sector blocks + */ + if (object->cardType != SD_SDHC) + { + /* Convert to byte address */ + sector *= SD_SECTOR_SIZE; + } + + assertCS(hwAttrs); + + /* Single block read */ + if (sectorCount == 1) + { + if ((sendCmd(object->spiHandle, CMD17, sector) == 0) && recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) + { + status = SD_STATUS_SUCCESS; + } + } + /* Multiple block read */ + else + { + if (sendCmd(object->spiHandle, CMD18, sector) == 0) + { + do + { + if (!recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) + { + break; + } + buf = (void *)(((uint32_t)buf) + SD_SECTOR_SIZE); + } while (--sectorCount); + + /* + * STOP_TRANSMISSION - order is important; always want to send + * stop signal + */ + if (sendCmd(object->spiHandle, CMD12, 0) == 0 && sectorCount == 0) + { + status = SD_STATUS_SUCCESS; + } + } + } + + deassertCS(hwAttrs); + + /* Send a 0xFF with CS high to try to put SD card into low power mode */ + spiTransfer(object->spiHandle, NULL, &ffByte, 1); + + SemaphoreP_post(object->lockSem); + + return (status); +} + +/* + * ======== SDSPI_write ======== + */ +int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, int_fast32_t sector, uint_fast32_t sectorCount) +{ + int_fast16_t status = SD_STATUS_SUCCESS; + SDSPI_Object *object = handle->object; + SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (sectorCount == 0) + { + return (SD_STATUS_ERROR); + } + + SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); + + /* + * On a SDSC card, the sector address is a byte address on the SD Card + * On a SDHC card, the sector addressing is via sector blocks + */ + if (object->cardType != SD_SDHC) + { + /* Convert to byte address if needed */ + sector *= SD_SECTOR_SIZE; + } + + assertCS(hwAttrs); + + /* Single block write */ + if (sectorCount == 1) + { + if ((sendCmd(object->spiHandle, CMD24, sector) == 0) && + transmitDataBlock(object->spiHandle, (void *)buf, SD_SECTOR_SIZE, START_BLOCK_TOKEN)) + { + sectorCount = 0; + } + } + /* Multiple block write */ + else + { + if ((object->cardType == SD_SDSC) || (object->cardType == SD_SDHC)) + { + if (sendCmd(object->spiHandle, CMD55, 0) != 0) + { + status = SD_STATUS_ERROR; + } + + /* ACMD23 */ + if ((status == SD_STATUS_SUCCESS) && (sendCmd(object->spiHandle, CMD23, sectorCount) != 0)) + { + status = SD_STATUS_ERROR; + } + } + + /* WRITE_MULTIPLE_BLOCK command */ + if ((status == SD_STATUS_SUCCESS) && (sendCmd(object->spiHandle, CMD25, sector) == 0)) + { + do + { + if (!transmitDataBlock(object->spiHandle, (void *)buf, SD_SECTOR_SIZE, START_MULTIBLOCK_TOKEN)) + { + break; + } + buf = (void *)(((uint32_t)buf) + SD_SECTOR_SIZE); + } while (--sectorCount); + + /* STOP_TRAN token */ + if (!transmitDataBlock(object->spiHandle, NULL, 0, STOP_MULTIBLOCK_TOKEN)) + { + sectorCount = 1; + } + } + } + + /* + * Wait for SD card to finish storing the data it received. This may help + * the card go into low power mode. + */ + waitUntilReady(object->spiHandle); + + deassertCS(hwAttrs); + + SemaphoreP_post(object->lockSem); + + return ((sectorCount) ? SD_STATUS_ERROR : SD_STATUS_SUCCESS); +} + +/* + * ======== assertCS ======== + */ +static inline void assertCS(SDSPI_HWAttrs const *hwAttrs) +{ + GPIO_write(hwAttrs->spiCsGpioIndex, 0); +} + +/* + * ======== deassertCS ======== + */ +static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs) +{ + GPIO_write(hwAttrs->spiCsGpioIndex, 1); +} + +/* + * ======== recvDataBlock ======== + * Function to receive a block of data from the SDCard + */ +static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count) +{ + uint8_t rxBuf[2]; + uint8_t txBuf[2] = {0xFF, 0xFF}; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + + /* + * Wait for SD card to be ready up to 1s. SD card is ready when the + * START_BLOCK_TOKEN is received. + */ + timeout = 1000000 / ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do + { + status = spiTransfer(handle, &rxBuf, &txBuf, 1); + currentTime = ClockP_getSystemTicks(); + } while ((status == SD_STATUS_SUCCESS) && (rxBuf[0] == 0xFF) && (currentTime - startTime) < timeout); + + if (rxBuf[0] != START_BLOCK_TOKEN) + { + /* Return error if valid data token was not received */ + return (false); + } + + /* Receive the data block into buffer */ + if (spiTransfer(handle, buf, NULL, count) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Read the 16 bit CRC, but discard it */ + if (spiTransfer(handle, &rxBuf, &txBuf, 2) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Return with success */ + return (true); +} + +/* + * ======== sendCmd ======== + * Function to send a command to the SD card. Command responses from + * SD card are returned. (0xFF) is returned on failures. + */ +static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg) +{ + uint8_t i; + uint8_t rxBuf; + uint8_t txBuf[6]; + int_fast16_t status; + + if ((cmd != CMD0) && !waitUntilReady(handle)) + { + return (0xFF); + } + + /* Setup SPI transaction */ + txBuf[0] = cmd; /* Command */ + txBuf[1] = (uint8_t)(arg >> 24); /* Argument[31..24] */ + txBuf[2] = (uint8_t)(arg >> 16); /* Argument[23..16] */ + txBuf[3] = (uint8_t)(arg >> 8); /* Argument[15..8] */ + txBuf[4] = (uint8_t)arg; /* Argument[7..0] */ + + if (cmd == CMD0) + { + /* CRC for CMD0(0) */ + txBuf[5] = 0x95; + } + else if (cmd == CMD8) + { + /* CRC for CMD8(0x1AA) */ + txBuf[5] = 0x87; + } + else + { + /* Default CRC should be at least 0x01 */ + txBuf[5] = 0x01; + } + + if (spiTransfer(handle, NULL, &txBuf, 6) != SD_STATUS_SUCCESS) + { + return (0xFF); + } + + /* Prepare to receive SD card response (send 0xFF) */ + txBuf[0] = 0xFF; + + /* + * CMD 12 has R1b response which transfers an additional + * "busy" byte + */ + if ((cmd == CMD12) && (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS)) + { + return (0xFF); + } + + /* Wait for a valid response; 10 attempts */ + i = 10; + do + { + status = spiTransfer(handle, &rxBuf, &txBuf, 1); + } while ((status == SD_STATUS_SUCCESS) && (rxBuf & 0x80) && (--i)); + + /* Return with the response value */ + return (rxBuf); +} + +/* + * ======== spiTransfer ======== + * Returns SD_STATUS_SUCCESS when transfer is completed; + * SD_STATUS_ERROR otherwise. + */ +static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, void *txBuf, size_t count) +{ + int_fast16_t status; + SPI_Transaction transaction; + + transaction.rxBuf = rxBuf; + transaction.txBuf = txBuf; + transaction.count = count; + + status = (SPI_transfer(handle, &transaction)) ? SD_STATUS_SUCCESS : SD_STATUS_ERROR; + + return (status); +} + +/* + * ======== transmitDataBlock ======== + * Function to transmit a block of data to the SD card. A valid command + * token must be sent to the SD card prior to sending the data block. + * The available tokens are: + * START_BLOCK_TOKEN + * START_MULTIBLOCK_TOKEN + * STOP_MULTIBLOCK_TOKEN + */ +static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, uint8_t token) +{ + uint8_t rxBuf; + uint8_t txBuf[2] = {0xFF, 0xFF}; + + if (!waitUntilReady(handle)) + { + return (false); + } + + /* transmit data token */ + txBuf[0] = token; + if (spiTransfer(handle, NULL, &txBuf, 1) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Send data only when token != STOP_MULTIBLOCK_TOKEN */ + if (token != STOP_MULTIBLOCK_TOKEN) + { + /* Write data to the SD card */ + if (spiTransfer(handle, NULL, buf, count) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Receive the 16 bit CRC, but discard it */ + txBuf[0] = (0xFF); + if (spiTransfer(handle, NULL, &txBuf, 2) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Receive data response token from SD card */ + if (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS) + { + return (false); + } + + /* Check data response; return error if data was rejected */ + if ((rxBuf & 0x1F) != 0x05) + { + return (false); + } + } + + return (true); +} + +/* + * ======== waitUntilReady ======== + * Function to check if the SD card is busy. + * + * Returns true if SD card is ready; false indicates the SD card is still busy + * & a timeout occurred. + */ +static bool waitUntilReady(SPI_Handle handle) +{ + uint8_t rxDummy; + uint8_t txDummy = 0xFF; + int_fast16_t status; + uint32_t currentTime; + uint32_t startTime; + uint32_t timeout; + + /* Wait up to 1s for data packet */ + timeout = 1000000 / ClockP_getSystemTickPeriod(); + startTime = ClockP_getSystemTicks(); + do + { + status = spiTransfer(handle, &rxDummy, &txDummy, 1); + currentTime = ClockP_getSystemTicks(); + } while ((status == SD_STATUS_SUCCESS) && (rxDummy != 0xFF) && (currentTime - startTime) < timeout); + + return (rxDummy == 0xFF); +} diff --git a/simplelink_lpf2/source/ti/drivers/sd/SDSPI.h b/simplelink_lpf2/source/ti/drivers/sd/SDSPI.h new file mode 100644 index 00000000..82985063 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sd/SDSPI.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2017-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!*************************************************************************** + * @file SDSPI.h + * + * @brief SD driver implementation built on the TI SPI driver. + * + * The SDSPI header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref SD.h for a complete description of APIs & example of use. + * + * This SD driver implementation can be used to communicate with SD cards + * via a SPI peripheral. This driver leverages the TI SPI driver to transfer + * data to/from the host processor to the SD card. The SD card chip select + * is also handled by this driver via the TI GPIO driver. Both the SPI + * driver instance & the GPIO pin (used as chip select) must be specified + * in the SDSPI hardware attributes. + * + * Note: This driver requires that the 'defaultTxBufValue' field in the SPI + * driver hardware attributes be set to '0xFF'. + * + * ## Data location & alignment # + * + * This driver relies on the TI SPI driver to configure the SPI peripheral & + * perform data transfers. This means that data to be transferred must comply + * with rules & restrictions set SPI driver (memory alignment & DMA + * accessibility requirements). Refer to @ref SPI.h & the device specific + * SPI implementation header files for details. + * + *
+ */ + +#ifndef ti_drivers_sd_SDSPI__include +#define ti_drivers_sd_SDSPI__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* SDSPI function table */ +extern const SD_FxnTable SDSPI_fxnTable; + +/*! + * @brief SDSPI Hardware attributes + * + * The #SDSPI_HWAttrs configuration structure contains the index of the SPI + * peripheral to be used for data transfers & the index of the GPIO Pin which + * will act as chip select. This driver uses this information to: + * - configure & open the SPI driver instance for data transfers + * - select the SD card (via chip select) when performing data transfers + * + * @struct SDSPI_HWAttrs + * An example configuration structure could look as the following: + * @code + * const SDSPI_HWAttrs sdspiHWAttrs[1] = { + * { + * // SPI driver index + * .spiIndex = 0, + * + * // GPIO driver pin index + * .spiCsGpioIndex = 3 + * } + * }; + * @endcode + */ +typedef struct +{ + uint_least8_t spiIndex; + uint16_t spiCsGpioIndex; +} SDSPI_HWAttrs; + +/*! + * @brief SDSPI Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + SemaphoreP_Handle lockSem; + SPI_Handle spiHandle; + SD_CardType cardType; + bool isOpen; +} SDSPI_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sd_SDSPI__include */ diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.c b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.c new file mode 100644 index 00000000..e8ebc06e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.c @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/rom_sha256.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +/* Outer and inner padding bytes used in HMAC */ +#define HMAC_OPAD_BYTE 0x5C +#define HMAC_IPAD_BYTE 0x36 + +/* Forward declarations */ +static void SHA2CC26X1_xorBufferWithByte(uint8_t *buffer, size_t bufferLength, uint8_t byte); + +/* + * ======== SHA2CC26X1_xorBufferWithByte ======== + */ +static void SHA2CC26X1_xorBufferWithByte(uint8_t *buffer, size_t bufferLength, uint8_t byte) +{ + size_t i; + + for (i = 0; i < bufferLength; i++) + { + buffer[i] = buffer[i] ^ byte; + } +} + +/* + * ======== SHA2_init ======== + */ +void SHA2_init(void) +{} + +/* + * ======== SHA2_construct ======== + */ +SHA2_Handle SHA2_construct(SHA2_Config *config, const SHA2_Params *params) +{ + SHA2_Handle handle; + SHA2CC26X1_Object *object; + uint_fast8_t key; + + handle = (SHA2_Config *)config; + object = handle->object; + + key = HwiP_disable(); + + if (object->isOpen) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + + HwiP_restore(key); + + if (params == NULL) + { + params = &SHA2_defaultParams; + } + + /* This implementation only supports SHA256 */ + if (params->hashType != SHA2_HASH_TYPE_256) + { + + object->isOpen = false; + + return NULL; + } + + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + + return handle; +} + +/* + * ======== SHA2_close ======== + */ +void SHA2_close(SHA2_Handle handle) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + /* If there is still an operation ongoing, abort it now. */ + object->isOpen = false; +} + +/* + * ======== SHA2CC26X1_addData ======== + */ +int_fast16_t SHA2CC26X1_addData(SHA2_Handle handle, const void *data, size_t length) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + uint8_t status; + + if (object->workzone.textLen[0] == 0) + { + SHA256_init(&object->workzone); + } + + status = SHA256_process(&object->workzone, (uint8_t *)data, length); + + return (status == SHA256_SUCCESS) ? SHA2_STATUS_SUCCESS : SHA2_STATUS_ERROR; +} + +/* + * ======== SHA2_addData ======== + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void *data, size_t length) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + int_fast16_t returnStatus = SHA2CC26X1_addData(handle, data, length); + + /* If the application uses callback return behaviour, emulate it */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, returnStatus); + + return SHA2_STATUS_SUCCESS; + } + else + { + return returnStatus; + } +} + +/* + * ======== SHA2CC26X1_finalize ======== + */ +int_fast16_t SHA2CC26X1_finalize(SHA2_Handle handle, void *digest) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + uint8_t status; + + status = SHA256_final(&object->workzone, digest); + + // Reset object state + object->workzone.textLen[0] = 0; + + return (status == SHA256_SUCCESS) ? SHA2_STATUS_SUCCESS : SHA2_STATUS_ERROR; +} + +/* + * ======== SHA2_finalize ======== + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + int_fast16_t returnStatus = SHA2CC26X1_finalize(handle, digest); + + /* If the application uses callback return behaviour, emulate it */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, returnStatus); + + return SHA2_STATUS_SUCCESS; + } + else + { + return returnStatus; + } +} + +/* + * ======== SHA2CC26X1_hashData ======== + */ +int_fast16_t SHA2CC26X1_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + uint8_t status; + + SHA256_init(&object->workzone); + + status = SHA256_full(&object->workzone, digest, (uint8_t *)data, length); + + return (status == SHA256_SUCCESS) ? SHA2_STATUS_SUCCESS : SHA2_STATUS_ERROR; +} + +/* + * ======== SHA2_hashData ======== + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + int_fast16_t returnStatus = SHA2CC26X1_hashData(handle, data, length, digest); + + /* If the application uses callback return behaviour, emulate it */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn(handle, returnStatus); + + return SHA2_STATUS_SUCCESS; + } + else + { + return returnStatus; + } +} + +/* + * ======== SHA2CC26X1_setupHmac ======== + * + * This function starts an HMAC operation and computes as much of the + * intermediate results as it can using only the key. + * + * HMAC requires concatenation of intermediate results and the application's + * message. We do not have the memory to do that kind of concatenation nor + * would it be runtime efficient to do that much copying. + * Instead, we use segmented hashes to start the computation of the hashes + * and then add in each segment without moving it in memory. + * + * We can compute all operations where the keying material is required. + * That way, we do not need to store the intermediate keying material + * for future use but only store the intermediate hash result. + * + * - It computes the intermediate key, k0 based on the input key's length. + * - It starts a segmented hash of the k0^opad part of + * H(k0 ^ opad || H(k0 ^ ipad || message)) + * - The intermediate output is saved in SHA2CC26X1_Object.hmacDigest + * - It starts a segmented hash with the k0^ipad part of + * H(k0 ^ipad || message) + * - The intermediate output is saved by the SHA2 driver as usual in + * SHA2CC26X1_Object.workzone.state + */ +int_fast16_t SHA2CC26X1_setupHmac(SHA2_Handle handle, const CryptoKey *key) +{ + uint8_t xorBuffer[SHA2_BLOCK_SIZE_BYTES_256]; + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + size_t keyLength = key->u.plaintext.keyLength; + uint8_t *keyingMaterial = key->u.plaintext.keyMaterial; + + /* Prepare the buffer of the derived key. We set the entire buffer to 0x00 + * so we do not need to pad it to the block size after copying the keying + * material provided or the hash thereof there. + */ + memset(xorBuffer, 0x00, SHA2_BLOCK_SIZE_BYTES_256); + + /* If the keying material fits in the derived key buffer, copy it there. + * Otherwise, we need to hash it first and copy the digest there. Since + * We filled the entire buffer with 0x00, we do not need to pad to the block + * size. + */ + if (keyLength <= SHA2_BLOCK_SIZE_BYTES_256) + { + memcpy(xorBuffer, keyingMaterial, keyLength); + } + else + { + SHA2CC26X1_hashData(handle, keyingMaterial, keyLength, xorBuffer); + } + + SHA256_init(&object->workzone); + + /* Compute k0 ^ opad */ + SHA2CC26X1_xorBufferWithByte(xorBuffer, SHA2_BLOCK_SIZE_BYTES_256, HMAC_OPAD_BYTE); + + /* Start a hash of k0 ^ opad. + * The intermediate result will be stored in the object for later + * use when the application calls SHA2_addData on its actual message. + */ + SHA2CC26X1_addData(handle, xorBuffer, SHA2_BLOCK_SIZE_BYTES_256); + + /* Copy the intermediate state of H(k0 ^ opad) */ + memcpy(object->hmacDigest, object->workzone.state, SHA2_DIGEST_LENGTH_BYTES_256); + + /* Undo k0 ^ opad to reconstruct k0. Use the memory of k0 instead + * of allocating a new copy on the stack to save RAM. + */ + SHA2CC26X1_xorBufferWithByte(xorBuffer, SHA2_BLOCK_SIZE_BYTES_256, HMAC_OPAD_BYTE); + + /* Compute k0 ^ ipad. */ + SHA2CC26X1_xorBufferWithByte(xorBuffer, SHA2_BLOCK_SIZE_BYTES_256, HMAC_IPAD_BYTE); + + /* Reset workzone to prepare to start a new hash */ + SHA256_init(&object->workzone); + + /* Start a hash of k0 ^ ipad. + * Use top-level fxn to invoke callback if needed + */ + SHA2CC26X1_addData(handle, xorBuffer, SHA2_BLOCK_SIZE_BYTES_256); + + return SHA2_STATUS_SUCCESS; +} + +/* + * ======== SHA2_setupHmac ======== + * The callback invocation is split out into a separate wrapper function to + * avoid invoking the callback multiple times during compound operations such + * as SHA2_hmac() + */ +int_fast16_t SHA2_setupHmac(SHA2_Handle handle, const CryptoKey *key) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + int_fast16_t returnStatus = SHA2CC26X1_setupHmac(handle, key); + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, SHA2_STATUS_SUCCESS); + } + + return returnStatus; +} + +/* + * ======== SHA2_finalizeHmac ======== + * + * This function completes the HMAC operation once all application data + * has been added through SHA_addData(). + * + * - It finalizes H((k0 ^ ipad) || data) + * - It adds H((k0 ^ ipad) || data) to the previously started hash that already + * includes k0 ^ opad. + * - It finalizes H(k0 ^ opad || H((k0 ^ ipad) || data)) + */ +int_fast16_t SHA2_finalizeHmac(SHA2_Handle handle, void *hmac) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + uint8_t tmpDigest[SHA2_DIGEST_LENGTH_BYTES_256]; + + /* Finalize H((k0 ^ ipad) || data) */ + SHA2CC26X1_finalize(handle, tmpDigest); + + memcpy(object->workzone.state, object->hmacDigest, SHA2_DIGEST_LENGTH_BYTES_256); + + /* We already processed one block of input earlier */ + object->workzone.textLen[0] = SHA2_BLOCK_SIZE_BYTES_256; + + /* Add the temporary digest computed earlier to the current digest */ + SHA2CC26X1_addData(handle, tmpDigest, SHA2_DIGEST_LENGTH_BYTES_256); + + /* Finalize H(k0 ^ opad || H((k0 ^ ipad) || data)) */ + SHA2_finalize(handle, hmac); + + return SHA2_STATUS_SUCCESS; +} + +/* + * ======== SHA2_hmac ======== + * + * This is practically just a convenience function. Because of the need for + * segmented hashes to construct the HMAC without actually allocating memory + * to concatenate intermediate results and the message, this function is not + * actually faster than an application using the segmented APIs. + */ +int_fast16_t SHA2_hmac(SHA2_Handle handle, const CryptoKey *key, const void *data, size_t size, void *hmac) +{ + SHA2CC26X1_setupHmac(handle, key); + + /* Add the input message to the hash */ + SHA2CC26X1_addData(handle, data, size); + + return SHA2_finalizeHmac(handle, hmac); +} + +/* + * ======== SHA2_reset ======== + */ +void SHA2_reset(SHA2_Handle handle) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + SHA256_init(&object->workzone); +} + +/* + * ======== SHA2_cancelOperation ======== + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle) +{ + SHA2CC26X1_Object *object = (SHA2CC26X1_Object *)handle->object; + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, SHA2_STATUS_CANCELED); + } + + SHA256_init(&object->workzone); + + return SHA2_STATUS_SUCCESS; +} + +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type) +{ + /* We only support SHA256. Trying to switch to any other hash type returns + * an error. + */ + return (type == SHA2_HASH_TYPE_256) ? SHA2_STATUS_SUCCESS : SHA2_STATUS_ERROR; +} diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.h b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.h new file mode 100644 index 00000000..6657d14e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X1.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SHA2CC26X1.h + * + * @brief SHA2 driver implementation for the CC26X1 family + * + * This file should only be included in the board file to fill the SHA2_config + * struct. + * + * The CC26X1 family does not have a dedicated hardware crypto accelerator. + * As a result, there are several limitations and advantages over accelerator + * based implementations. + * + * # Limitations # + * - Asynchronously canceling an operation is not possible. The APIs will + * always run to completion. + * - Invoking driver APIs from multiple contexts at the same time using the + * same handle is not permitted or guarded against. + * + * # Advantages # + * - Since this is a software implementation that uses dependency injection, + * it is possible for multiple clients to simultaneously invoke driver APIs + * with their respective handles. + * + * # Supported Digest Sizes # + * + * The driver is built on top of a SHA256 software implementation stored in + * ROM. As a result, digest sizes other than 256 bits are not supported with + * this driver. + * + * | SHA2_HashTypes Supported | + * |--------------------------| + * | SHA2_HASH_TYPE_256 | + * + */ + +#ifndef ti_drivers_sha2_SHA2CC26X1__include +#define ti_drivers_sha2_SHA2CC26X1__include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/rom_sha256.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Hardware-specific configuration attributes + * + * SHA2CC26X1 hardware attributes are used in the board file by the + * #SHA2_Config struct. + */ +typedef struct +{ + uint8_t dummy; +} SHA2CC26X1_HWAttrs; + +/*! \cond Internal APIs */ + +/* + * SHACC26XX Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + SHA2_ReturnBehavior returnBehavior; + SHA2_CallbackFxn callbackFxn; + uint32_t hmacDigest[SHA2_DIGEST_LENGTH_BYTES_256 / sizeof(uint32_t)]; + SHA256_Workzone workzone; +} SHA2CC26X1_Object; + +/*! \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sha2_SHA2CC26X1__include */ diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.c b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.c new file mode 100644 index 00000000..6483d146 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.c @@ -0,0 +1,1325 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_crypto.h) +#include DeviceFamily_constructPath(driverlib/sha2.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/smph.h) + +#if (ENABLE_KEY_STORAGE == 1) + #include +#endif + +/* Defines and enumerations */ +#define SHA2_UNUSED(value) ((void)(value)) + +/* Outer and inner padding bytes used in HMAC */ +#define HMAC_OPAD_BYTE 0x5C +#define HMAC_IPAD_BYTE 0x36 + +#if (ENABLE_KEY_STORAGE == 1) + /*! @brief Maximum HMAC key size in bytes when using KeyStore */ + #define SHA2CC26X2_HMAC_MAX_KEYSTORE_KEY_SIZE 128 +#endif /* ENABLE_KEY_STORAGE */ + +/* Though the DMA Length Registers are 32-bit, they can only take a 16-bit + * length while the bits [31:16] are reserved. + */ +#define DMA_MAX_TXN_LENGTH 0xFFFFU + +typedef enum +{ + SHA2_OperationType_SingleStep, + SHA2_OperationType_MultiStep, + SHA2_OperationType_Finalize, +} SHA2_OperationType; + +/* Forward declarations */ +static uint32_t floorUint32(uint32_t value, uint32_t divider); +static void SHA2_hwiFxn(uintptr_t arg0); +static int_fast16_t SHA2CC26X2_waitForAccess(SHA2_Handle handle); +static int_fast16_t SHA2CC26X2_waitForResult(SHA2_Handle handle); +static void SHA2CC26X2_configureInterrupts(SHA2_Handle handle, + SHA2CC26X2_Object *object, + SHA2CC26X2_HWAttrs const *hwAttrs, + void (*callbackFxn)(uintptr_t arg0)); +static void SHA2CC26X2_xorBufferWithByte(uint8_t *buffer, size_t bufferLength, uint8_t byte); +static void SHA2CC26X2_cleanUpAfterOperation(SHA2CC26X2_Object *object); +static int_fast16_t SHA2CC26X2_addData(SHA2_Handle handle, const void *data, size_t length); +static int_fast16_t SHA2CC26X2_finalize(SHA2_Handle handle, void *digest); +static int_fast16_t SHA2CC26X2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest); +static void SHA2CC26X2_emptyFinalize(SHA2CC26X2_Object *object, void *digest); +static void SHA2CC26X2_computeIntermediateHash(SHA2CC26X2_Object *object); + +/* Static globals */ +static const uint32_t hashModeTable[] = {SHA2_MODE_SELECT_SHA224, + SHA2_MODE_SELECT_SHA256, + SHA2_MODE_SELECT_SHA384, + SHA2_MODE_SELECT_SHA512}; + +/* This table converts from SHA2_HashType values to the corresponding block size. */ +static const uint8_t blockSizeTable[] = {SHA2_BLOCK_SIZE_BYTES_224, + SHA2_BLOCK_SIZE_BYTES_256, + SHA2_BLOCK_SIZE_BYTES_384, + SHA2_BLOCK_SIZE_BYTES_512}; + +/* This table converts from SHA2_HashType values to the corresponding digest size. */ +const uint8_t digestSizeTable[] = {SHA2_DIGEST_LENGTH_BYTES_224, + SHA2_DIGEST_LENGTH_BYTES_256, + SHA2_DIGEST_LENGTH_BYTES_384, + SHA2_DIGEST_LENGTH_BYTES_512}; + +/* This table converts from SHA2_HashType values to the corresponding intermediate digest size. */ +static const uint8_t intermediateDigestSizeTable[] = {SHA2_DIGEST_LENGTH_BYTES_256, + SHA2_DIGEST_LENGTH_BYTES_256, + SHA2_DIGEST_LENGTH_BYTES_512, + SHA2_DIGEST_LENGTH_BYTES_512}; + +static const uint8_t *SHA2_data; + +/* Used only for single-step operations to track the final destination of + * the output digest, in case the operation is internally segmented to + * tackle the limitation in the max length the DMA controller can handle + * per DMA transaction. */ +static void *SHA2_finalDigest; + +static uint32_t SHA2_dataBytesRemaining; + +static SHA2_OperationType SHA2_operationType; + +static bool isInitialized = false; + +static bool readIntermediateDigest = false; + +/* + * ======== floorUint32 helper ======== + */ +uint32_t floorUint32(uint32_t value, uint32_t divider) +{ + return (value / divider) * divider; +} + +/* + * ======== SHA2_hwiFxn ======== + */ +static void SHA2_hwiFxn(uintptr_t arg0) +{ + SHA2CC26X2_Object *object = ((SHA2_Handle)arg0)->object; + + SHA2CC26X2_cleanUpAfterOperation(object); + + /* Ensure all DMA transactions are done before releasing the resources or + * posting a callback. If there's more data remaining tracked by + * SHA2_dataBytesRemaining, the operation is not complete yet, unless + * the remaining data is smaller than a block size in which case it will + * be buffered in. + */ + if (!object->operationInProgress) + { + if (object->retainAccessCounter == 0) + { + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + } + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + object->callbackFxn((SHA2_Handle)arg0, object->returnStatus); + } + } +} + +/* + * ======== SHA2CC26X2_cleanUpAfterOperation ======== + */ +static void SHA2CC26X2_cleanUpAfterOperation(SHA2CC26X2_Object *object) +{ + uint32_t blockSize = blockSizeTable[object->hashType]; + uint32_t irqStatus; + uint32_t key; + + irqStatus = SHA2IntStatusRaw(); + SHA2IntClear(SHA2_RESULT_RDY | SHA2_DMA_IN_DONE | SHA2_DMA_BUS_ERR); + + /* + * Prevent the following section from being interrupted by + * SHA2_cancelOperation(). + */ + key = HwiP_disable(); + + if (object->operationCanceled) + { + /* + * If the operation has been canceled we can end here. + * Cleanup is done by SHA2_cancelOperation() + */ + HwiP_restore(key); + return; + } + else if (irqStatus & SHA2_DMA_BUS_ERR) + { + /* + * In the unlikely event of an error we can stop here. + */ + object->returnStatus = SHA2_STATUS_ERROR; + } + else + { + if (readIntermediateDigest == true) + { + /* + * Last transaction has finished and we need to store an intermediate + * digest. + */ + SHA2GetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + + readIntermediateDigest = false; + } + + if (SHA2_operationType == SHA2_OperationType_SingleStep) + { + if (SHA2_dataBytesRemaining > blockSize) + { + SHA2CC26X2_computeIntermediateHash(object); + + HwiP_restore(key); + return; + } + else if (SHA2_dataBytesRemaining > 0) + { + /* SHA2ComputeIntermediateHash reads out and writes back + * intermediate digest sizes of the the final digest size. For + * SHA-224 and SHA-384, this produces incorrect results. Instead, + * the digest size of SHA-256 and SHA-512 should be used instead. + * This is why we are writing the digest to the accelerator here + * first to cover the difference in digest sizes. + */ + SHA2SetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + + SHA2ComputeFinalHash(SHA2_data, + SHA2_finalDigest, + object->digest, + object->bytesProcessed + SHA2_dataBytesRemaining, + SHA2_dataBytesRemaining, + hashModeTable[object->hashType]); + + /* No need to update object->bytesProcessed for finalization + * as it would be cleared upon reentry into SHA2CC26X2_cleanUpAfterOperation + * and will anyways not be used anymore. */ + SHA2_dataBytesRemaining = 0; + SHA2_data = NULL; + readIntermediateDigest = false; + + HwiP_restore(key); + return; + } + } + else + { /* Multi-step operation */ + if (SHA2_dataBytesRemaining >= blockSize) + { + SHA2CC26X2_computeIntermediateHash(object); + + HwiP_restore(key); + return; + } + else if (SHA2_dataBytesRemaining > 0) + { + /* Copy remaining data into buffer if it's a multi-step + * operation and only less than a block-size of data is + * remaining. + */ + memcpy(object->buffer, SHA2_data, SHA2_dataBytesRemaining); + object->bytesInBuffer += SHA2_dataBytesRemaining; + SHA2_dataBytesRemaining = 0; + } + } + } + + /* + * Since we got here, every transaction has been finished + */ + object->operationInProgress = false; + + /* + * Reset byte counter if a hash has been finalized + */ + if (SHA2_operationType != SHA2_OperationType_MultiStep) + { + object->bytesProcessed = 0; + object->bytesInBuffer = 0; + } + + HwiP_restore(key); +} + +/* + * ======== SHA2CC26X2_computeIntermediateHash ======== + * NOTE: This function should only be used within a critical section. + */ +static void SHA2CC26X2_computeIntermediateHash(SHA2CC26X2_Object *object) +{ + uint32_t blockSize = blockSizeTable[object->hashType]; + uint32_t transactionLength; + + /* DMA Controller has a limitation of processing max 0xFFFF bytes per transaction */ + if (SHA2_dataBytesRemaining > DMA_MAX_TXN_LENGTH) + { + transactionLength = floorUint32(DMA_MAX_TXN_LENGTH, blockSize); + } + else + { + transactionLength = floorUint32(SHA2_dataBytesRemaining, blockSize); + } + + /* SHA2ComputeIntermediateHash reads out and writes back + * intermediate digest sizes of the the final digest size. For + * SHA-224 and SHA-384, this produces incorrect results. Instead, + * the digest size of SHA-256 and SHA-512 should be used instead. + * This is why we are writing the digest to the accelerator here + * first to cover the difference in digest sizes. + */ + SHA2SetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + + SHA2ComputeIntermediateHash(SHA2_data, object->digest, hashModeTable[object->hashType], transactionLength); + + SHA2_dataBytesRemaining -= transactionLength; + SHA2_data += transactionLength; + object->bytesProcessed += transactionLength; + readIntermediateDigest = true; + + return; +} + +/* + * ======== SHA2CC26X2_waitForAccess ======== + */ +static int_fast16_t SHA2CC26X2_waitForAccess(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object = handle->object; + + return SemaphoreP_pend(&CryptoResourceCC26XX_accessSemaphore, object->accessTimeout); +} + +/* + * ======== SHA2CC26X2_waitForResult ======== + */ +static int_fast16_t SHA2CC26X2_waitForResult(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object = handle->object; + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + do + { + SHA2WaitForIRQFlags(SHA2_RESULT_RDY | SHA2_DMA_BUS_ERR); + SHA2CC26X2_cleanUpAfterOperation(object); + } while (object->operationInProgress); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (object->retainAccessCounter == 0) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + } + + return object->returnStatus; + } + else if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoResourceCC26XX_operationSemaphore, (uint32_t)SemaphoreP_WAIT_FOREVER); + + return object->returnStatus; + } + else + { + return SHA2_STATUS_SUCCESS; + } +} + +/* + * ======== SHA2CC26X2_configureInterrupts ======== + */ +static void SHA2CC26X2_configureInterrupts(SHA2_Handle handle, + SHA2CC26X2_Object *object, + SHA2CC26X2_HWAttrs const *hwAttrs, + void (*callbackFxn)(uintptr_t arg0)) +{ + /* If we are in SHA2_RETURN_BEHAVIOR_POLLING, we do not want an interrupt to trigger. + * We need to disable it before kicking off the operation. + */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } + else + { + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * drivers and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + HwiP_setFunc(&CryptoResourceCC26XX_hwi, callbackFxn, (uintptr_t)handle); + HwiP_setPriority(INT_CRYPTO_RESULT_AVAIL_IRQ, hwAttrs->intPriority); + + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); + } +} + +/* + * ======== SHA2CC26X2_xorBufferWithByte ======== + */ +static void SHA2CC26X2_xorBufferWithByte(uint8_t *buffer, size_t bufferLength, uint8_t byte) +{ + size_t i; + + for (i = 0; i < bufferLength; i++) + { + buffer[i] = buffer[i] ^ byte; + } +} + +/* + * ======== SHA2_init ======== + */ +void SHA2_init(void) +{ + CryptoResourceCC26XX_constructRTOSObjects(); + + isInitialized = true; +} + +/* + * ======== SHA2_construct ======== + */ +SHA2_Handle SHA2_construct(SHA2_Config *config, const SHA2_Params *params) +{ + SHA2_Handle handle; + SHA2CC26X2_Object *object; + uint_fast8_t key; + + handle = (SHA2_Config *)config; + object = handle->object; + + key = HwiP_disable(); + + if (object->isOpen || !isInitialized) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + object->operationInProgress = false; + object->operationCanceled = false; + + HwiP_restore(key); + + if (params == NULL) + { + params = &SHA2_defaultParams; + } + + DebugP_assert(params->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + object->returnBehavior = params->returnBehavior; + object->callbackFxn = params->callbackFxn; + object->hashType = params->hashType; + + if (params->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + object->accessTimeout = params->timeout; + } + else + { + object->accessTimeout = SemaphoreP_NO_WAIT; + } + + /* Set power dependency - i.e. power up and enable clock for Crypto (CryptoResourceCC26XX) module. */ + Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + + return handle; +} + +/* + * ======== SHA2_close ======== + */ +void SHA2_close(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object; + uintptr_t key; + + DebugP_assert(handle); + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + /* If there is still an operation ongoing, abort it now. */ + key = HwiP_disable(); + if (object->operationInProgress) + { + SHA2_cancelOperation(handle); + } + object->isOpen = false; + HwiP_restore(key); + + /* Release power dependency on Crypto Module. */ + Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== SHA2_addData ======== + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void *data, size_t length) +{ + /* Try and obtain access to the crypto module */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + return SHA2CC26X2_addData(handle, data, length); +} + +/* + * ======== SHA2CC26X2_addData ======== + */ +static int_fast16_t SHA2CC26X2_addData(SHA2_Handle handle, const void *data, size_t length) +{ + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t blockSize = blockSizeTable[object->hashType]; + uintptr_t key; + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + SHA2_operationType = SHA2_OperationType_MultiStep; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + if ((object->bytesInBuffer + length) >= blockSize) + { + /* We have accumulated enough data to start a transaction. Now the question + * remains whether we have to merge bytes from the data stream into the + * buffer first. If so, we do that now, then start a transaction. + * If the buffer is empty, we can start a transaction on the data stream. + * Once the transaction is finished, we will decide how to follow up, + * i.e. copy remaining data into the buffer. + */ + uint32_t transactionLength; + const uint8_t *transactionStartAddress; + + if (object->bytesInBuffer > 0) + { + uint8_t *bufferTail = &object->buffer[object->bytesInBuffer]; + uint32_t bytesToCopyToBuffer = blockSize - object->bytesInBuffer; + memcpy(bufferTail, data, bytesToCopyToBuffer); + + /* We reset the value already. That saves a comparison + * in the ISR handler + */ + object->bytesInBuffer = 0; + + transactionStartAddress = object->buffer; + transactionLength = blockSize; + + SHA2_data = (const uint8_t *)data + bytesToCopyToBuffer; + SHA2_dataBytesRemaining = length - bytesToCopyToBuffer; + } + else + { + transactionStartAddress = data; + + /* DMA Controller has a limitation of processing max 0xFFFF bytes per transaction */ + if (length > DMA_MAX_TXN_LENGTH) + { + transactionLength = floorUint32(DMA_MAX_TXN_LENGTH, blockSize); + } + else + { + transactionLength = floorUint32(length, blockSize); + } + + SHA2_data = (const uint8_t *)data + transactionLength; + SHA2_dataBytesRemaining = length - transactionLength; + } + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + + /* + * Finally we need to decide whether this is the first hash + * operation or a follow-up from a previous one. + */ + if (object->bytesProcessed > 0) + { + /* SHA2ComputeIntermediateHash reads out and writes back + * intermediate digest sizes of the the final digest size. For + * SHA-224 and SHA-384, this produces incorrect results. Instead, + * the digest size of SHA-256 and SHA-512 should be used instead. + * This is why we are writing the digest to the accelerator here + * first to cover the difference in digest sizes. + */ + SHA2SetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + + SHA2ComputeIntermediateHash(transactionStartAddress, + object->digest, + hashModeTable[object->hashType], + transactionLength); + } + else + { + SHA2ComputeInitialHash(transactionStartAddress, + object->digest, + hashModeTable[object->hashType], + transactionLength); + } + + object->bytesProcessed += transactionLength; + object->operationInProgress = true; + readIntermediateDigest = true; + HwiP_restore(key); + } + else + { + /* There is no action required by the hardware. But we kick the + * interrupt in order to follow the same code path as the other + * operations. + */ + uint8_t *bufferTail = &object->buffer[object->bytesInBuffer]; + memcpy(bufferTail, data, length); + object->bytesInBuffer += length; + SHA2_dataBytesRemaining = 0; + + /* + * Asserting the IRQ and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + object->operationInProgress = true; + SHA2IntEnable(SHA2_RESULT_RDY); + HWREG(CRYPTO_BASE + CRYPTO_O_IRQSET) = SHA2_RESULT_RDY; + HwiP_restore(key); + } + + return SHA2CC26X2_waitForResult(handle); +} + +/* + * ======== SHA2_finalize ======== + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest) +{ + + /* Try and obtain access to the crypto module */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + return SHA2CC26X2_finalize(handle, digest); +} + +/* + * ======== SHA2CC26X2_finalize ======== + */ +static int_fast16_t SHA2CC26X2_finalize(SHA2_Handle handle, void *digest) +{ + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + SHA2_operationType = SHA2_OperationType_Finalize; + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + object->operationInProgress = true; + + if (object->bytesProcessed == 0) + { + /* + * Since no hash operation has been performed yet and no intermediate + * digest is available, we have to perform a full hash operation. + * + * No new data can be added during a finalize operation. That means + * in this case, the total length of all the data added using addData + * calls is less than a blocksize for the given hashType. So the remaining + * data is only in the buffer and only that needs to be hashed. + */ + SHA2ComputeHash(object->buffer, digest, object->bytesInBuffer, hashModeTable[object->hashType]); + } + else if (object->bytesInBuffer > 0) + { + uint32_t totalLength = object->bytesProcessed + object->bytesInBuffer; + uint32_t chunkLength = object->bytesInBuffer; + + /* SHA2ComputeIntermediateHash and SHA2ComputeFinalHash read out and writes + * back intermediate digest sizes of the the final digest size. For + * SHA-224 and SHA-384, this produces incorrect results. Instead, + * the digest size of SHA-256 and SHA-512 should be used instead. + * This is why we are writing the digest to the accelerator here + * first to cover the difference in digest sizes. + */ + SHA2SetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + + SHA2ComputeFinalHash(object->buffer, + digest, + object->digest, + totalLength, + chunkLength, + hashModeTable[object->hashType]); + } + else + { + SHA2CC26X2_emptyFinalize(object, digest); + } + + HwiP_restore(key); + + return SHA2CC26X2_waitForResult(handle); +} + +/* + * ======== SHA2_emptyFinalize ======== + */ +static void SHA2CC26X2_emptyFinalize(SHA2CC26X2_Object *object, void *digest) +{ + /* + * The hardware is incapable of finalizing a SHA2 hash without additional + * data to process. However, SW can create the final block (consisting of + * pad and an encoding of the message length) and request that block + * be hashed by the hardware. The resulting hash is the final SHA2 hash. + * + * Calculate the length in bits and put it at the end of the dummy + * finalization block in big endian order + */ + uint64_t lengthInBits = object->bytesProcessed * 8; + uint32_t blockSize = blockSizeTable[object->hashType]; + uint8_t *lengthBytes = (uint8_t *)&lengthInBits; + + /* + * Use the existing buffer as scratch pad + */ + memset(object->buffer, 0, blockSize); + + /* + * Final block starts with '10000000'. + */ + object->buffer[0] = 0x80; + + /* + * The length is written into the end of the finalization block + * in big endian order. We always write only the last 8 bytes. + */ + uint32_t i = 0; + for (i = 0; i < 4; i++) + { + object->buffer[blockSize - 8 + i] = lengthBytes[7 - i]; + object->buffer[blockSize - 4 + i] = lengthBytes[3 - i]; + } + + /* + * There is no singular function in the driverlib SHA2 interface + * that can handle this situation. Thus, several lower-level + * calls to the driverlib SHA2 library as well as direct + * register access is performed. + */ + SHA2ClearDigestAvailableFlag(); + + if (object->hashType == SHA2_HASH_TYPE_224 || object->hashType == SHA2_HASH_TYPE_256) + { + // Configure DMA to handle shorter digest outputs + SHA2SelectAlgorithm(SHA2_ALGSEL_SHA256 | SHA2_ALGSEL_TAG); + } + else + { + // Configure DMA to handle longer digest outputs + SHA2SelectAlgorithm(SHA2_ALGSEL_SHA512 | SHA2_ALGSEL_TAG); + } + + SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); + + /* + * For CC13x4/CC26x4 devices, SHA2_DMA_IN_DONE is also routed to + * INT_CRYPTO_RESULT_AVAIL_IRQ in addition to SHA2_RESULT_RDY. To prevent + * multiple interrupts from occurring, SHA2_DMA_IN_DONE is not enabled for + * those devices. + */ +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + SHA2IntEnable(SHA2_RESULT_RDY); +#else + SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); +#endif + + HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashModeTable[object->hashType]; + SHA2SetDigest(object->digest, intermediateDigestSizeTable[object->hashType]); + SHA2StartDMAOperation(object->buffer, blockSize, digest, digestSizeTable[object->hashType]); + + return; +} + +/* + * ======== SHA2_hashData ======== + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) +{ + + /* Try and obtain access to the crypto module */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + return SHA2CC26X2_hashData(handle, data, length, digest); +} + +/* + * ======== SHA2CC26X2_hashData ======== + */ +static int_fast16_t SHA2CC26X2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) +{ + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t blockSize = blockSizeTable[object->hashType]; + uintptr_t key; + uint32_t transactionLength; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + SHA2_operationType = SHA2_OperationType_SingleStep; + SHA2_dataBytesRemaining = 0; + + object->returnStatus = SHA2_STATUS_SUCCESS; + object->operationCanceled = false; + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + + /* + * Starting the accelerator and setting the operationInProgress + * flag must be atomic. + */ + key = HwiP_disable(); + + /* DMA Controller has a limitation of processing max 0xFFFF bytes per transaction. + * Segment the operation internally catering to that limitation to process all the + * available data successfully. */ + if (length <= DMA_MAX_TXN_LENGTH) + { + SHA2ComputeHash(data, digest, length, hashModeTable[object->hashType]); + } + else + { + transactionLength = floorUint32(DMA_MAX_TXN_LENGTH, blockSize); + + SHA2ComputeInitialHash(data, object->digest, hashModeTable[object->hashType], transactionLength); + + SHA2_data = (const uint8_t *)data + transactionLength; + SHA2_dataBytesRemaining = length - transactionLength; + object->bytesProcessed += transactionLength; + readIntermediateDigest = true; + SHA2_finalDigest = digest; + } + + object->operationInProgress = true; + HwiP_restore(key); + + return SHA2CC26X2_waitForResult(handle); +} + +/* + * ======== SHA2CC26X2_setupHmac ======== + * + * This function starts an HMAC operation and computes as much of the + * intermediate results as it can using only the key. + * + * HMAC requires concatenation of intermediate results and the application's + * message. We do not have the memory to do that kind of concatenation nor + * would it be runtime efficient to do that much copying. + * Instead, we use segmented hashes to start the computation of the hashes + * and then add in each segment without moving it in memory. + * + * We can compute all operations where the keying material is required. + * That way, we do not need to store the intermediate keying material + * for future use but only store the intermediate hash result. + * + * - It computes the intermediate key, k0 based on the input key's length. + * - It starts a segmented hash with the k0^ipad part of + * H(k0 ^ipad || message) + * - The intermediate output is saved by the SHA2 driver as usual in + * SHA2CC26X2_Object.digest + * - It starts a segmented hash of the k0^opad part of + * H(k0 ^ opad || H(k0 ^ ipad || message)) + * - The intermediate output is saved in SHA2CC26X2_Object.hmacDigest + */ +int_fast16_t SHA2CC26X2_setupHmac(SHA2_Handle handle, const CryptoKey *key) +{ + uint8_t xorBuffer[SHA2CC26X2_MAX_BLOCK_SIZE_BYTES]; + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + +#if (ENABLE_KEY_STORAGE == 1) + /* Expect SHA2 keys using KeyStore to not be more than the max SHA2 block size */ + uint8_t KeyStore_keyingMaterial[SHA2CC26X2_HMAC_MAX_KEYSTORE_KEY_SIZE]; + int_fast16_t status = KEYSTORE_PSA_STATUS_GENERIC_ERROR; + KeyStore_PSA_KeyFileId keyID; +#endif /* ENABLE_KEY_STORAGE */ + + size_t keyLength; + uint8_t *keyingMaterial = NULL; + + if (key->encoding == CryptoKey_PLAINTEXT) + { + keyLength = key->u.plaintext.keyLength; + keyingMaterial = key->u.plaintext.keyMaterial; + } +#if (ENABLE_KEY_STORAGE == 1) + else if (key->encoding == CryptoKey_KEYSTORE) + { + GET_KEY_ID(keyID, key->u.keyStore.keyID); + + switch (object->hashType) + { + case SHA2_HASH_TYPE_224: + status = KeyStore_PSA_getKey(keyID, + KeyStore_keyingMaterial, + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_SHA_224, + KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT); + break; + case SHA2_HASH_TYPE_256: + status = KeyStore_PSA_getKey(keyID, + KeyStore_keyingMaterial, + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_SHA_256, + KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT); + break; + case SHA2_HASH_TYPE_384: + status = KeyStore_PSA_getKey(keyID, + KeyStore_keyingMaterial, + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_SHA_384, + KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT); + break; + case SHA2_HASH_TYPE_512: + status = KeyStore_PSA_getKey(keyID, + KeyStore_keyingMaterial, + sizeof(KeyStore_keyingMaterial), + &keyLength, + KEYSTORE_PSA_ALG_SHA_512, + KEYSTORE_PSA_KEY_USAGE_DECRYPT | KEYSTORE_PSA_KEY_USAGE_ENCRYPT); + break; + default: + break; + } + + if ((status != KEYSTORE_PSA_STATUS_SUCCESS) || (keyLength != key->u.keyStore.keyLength)) + { + return SHA2_STATUS_KEYSTORE_ERROR; + } + + keyingMaterial = KeyStore_keyingMaterial; + } +#endif + else + { + return SHA2_STATUS_UNSUPPORTED; + } + + /* Since we will be making multiple calls to SHA2 driver APIs, we need + * to ensure we retain access across those calls. Otherwise another + * client could come in and start an operation while our later ones are + * ongoing. This is because the first SHA2 driver API call would + * release the access semaphore. + */ + object->retainAccessCounter++; + + /* Put the driver into polling mode. This allows us to implement a linear + * flow of other calls to SHA2 APIs. Otherwise, we would need to construct + * a state machine executed and further kicked off from a registered + * callback function if SHA2_RETURN_BEHAVIOR_CALLBACK were used. + * This is highly inefficient in terms of code size, complexity, and + * runtime as the inputs to the hash function are short. + */ + SHA2_ReturnBehavior originalReturnBehavior = object->returnBehavior; + object->returnBehavior = SHA2_RETURN_BEHAVIOR_POLLING; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + /* Reset segmented processing state to ensure we start a fresh + * transaction + */ + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + + /* Prepare the buffer of the derived key. We set the entire buffer to 0x00 + * so we do not need to pad it to the block size after copying the keying + * material provided or the hash thereof there. + */ + memset(xorBuffer, 0x00, blockSizeTable[object->hashType]); + + /* If the keying material fits in the derived key buffer, copy it there. + * Otherwise, we need to hash it first and copy the digest there. Since + * We filled the entire buffer with 0x00, we do not need to pad to the block + * size. + */ + if (keyLength <= blockSizeTable[object->hashType]) + { + memcpy(xorBuffer, keyingMaterial, keyLength); + } + else + { + SHA2CC26X2_hashData(handle, keyingMaterial, keyLength, xorBuffer); + } + + /* Compute k0 ^ ipad */ + SHA2CC26X2_xorBufferWithByte(xorBuffer, blockSizeTable[object->hashType], HMAC_IPAD_BYTE); + + /* Start a hash of k0 ^ ipad. + * The intermediate result will be stored in the object for later + * use when the application calls SHA2_addData on its actual message. + */ + SHA2CC26X2_addData(handle, xorBuffer, blockSizeTable[object->hashType]); + + /* Undo k0 ^ ipad to reconstruct k0. Use the memory of k0 instead + * of allocating a new copy on the stack to save RAM. + */ + SHA2CC26X2_xorBufferWithByte(xorBuffer, blockSizeTable[object->hashType], HMAC_IPAD_BYTE); + + /* Compute k0 ^ opad. */ + SHA2CC26X2_xorBufferWithByte(xorBuffer, blockSizeTable[object->hashType], HMAC_OPAD_BYTE); + + /* Start a hash of k0 ^ opad. + * We are using driverlib here since using the interal SHA2 driver APIs + * would corrupt our previously stored intermediate results. + * This lets us save a second intermediate result. + */ + SHA2ComputeInitialHash(xorBuffer, + object->hmacDigest, + hashModeTable[object->hashType], + blockSizeTable[object->hashType]); + + SHA2WaitForIRQFlags(SHA2_RESULT_RDY | SHA2_DMA_BUS_ERR); + + SHA2GetDigest(object->hmacDigest, intermediateDigestSizeTable[object->hashType]); + + /* Restore original return behaviour */ + object->returnBehavior = originalReturnBehavior; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + object->retainAccessCounter--; + if (object->retainAccessCounter == 0) + { + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + /* Only call callbackFxn if this is going to be the last sub-operation + * of this HMAC call. + */ + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, SHA2_STATUS_SUCCESS); + } + } + + return SHA2_STATUS_SUCCESS; +} + +/* + * ======== SHA2_setupHmac ======== + */ +int_fast16_t SHA2_setupHmac(SHA2_Handle handle, const CryptoKey *key) +{ + /* Try and obtain access to the crypto module. + * We will be keeping this for multiple operations + */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + return SHA2CC26X2_setupHmac(handle, key); +} + +/* + * ======== SHA2CC26X2_finalizeHmac ======== + * + * This function completes the HMAC operation once all application data + * has been added through SHA_addData(). + * + * - It finalizes H((k0 ^ ipad) || data) + * - It adds H((k0 ^ ipad) || data) to the previously started hash that already + * includes k0 ^ opad. + * - It finalizes H(k0 ^ opad || H((k0 ^ ipad) || data)) + */ +int_fast16_t SHA2CC26X2_finalizeHmac(SHA2_Handle handle, void *hmac) +{ + uint8_t tmpDigest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES]; + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + SHA2_ReturnBehavior originalReturnBehavior = object->returnBehavior; + object->returnBehavior = SHA2_RETURN_BEHAVIOR_POLLING; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + /* Retain access over multiple SHA2 driver calls */ + object->retainAccessCounter++; + + /* Finalize H((k0 ^ ipad) || data) */ + SHA2CC26X2_finalize(handle, tmpDigest); + + memcpy(object->digest, object->hmacDigest, intermediateDigestSizeTable[object->hashType]); + + object->bytesProcessed = blockSizeTable[object->hashType]; + + SHA2_operationType = SHA2_OperationType_MultiStep; + + /* Add the temporary digest computed earlier to the current digest */ + SHA2CC26X2_addData(handle, tmpDigest, digestSizeTable[object->hashType]); + + object->returnBehavior = originalReturnBehavior; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + object->retainAccessCounter--; + + /* Finalize H(k0 ^ opad || H((k0 ^ ipad) || data)) + * Posting of access semaphore and other cleanup handled by + * SHA2CC26X2_finalize call + */ + SHA2CC26X2_finalize(handle, hmac); + + return SHA2_STATUS_SUCCESS; +} + +/* + * ======== SHA2_finalizeHmac ======== + */ +int_fast16_t SHA2_finalizeHmac(SHA2_Handle handle, void *hmac) +{ + /* Try and obtain access to the crypto module. + * We will be keeping this for multiple operations + */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + return SHA2CC26X2_finalizeHmac(handle, hmac); +} + +/* + * ======== SHA2_hmac ======== + * + * This is practically just a convenience function. Because of the need for + * segmented hashes to construct the HMAC without actually allocating memory + * to concatenate intermediate results and the message, this function is not + * actually faster than an application using the segmented APIs. + */ +int_fast16_t SHA2_hmac(SHA2_Handle handle, const CryptoKey *key, const void *data, size_t size, void *hmac) +{ + SHA2CC26X2_Object *object = handle->object; + SHA2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + int16_t status = SHA2_STATUS_ERROR; + + /* Try and obtain access to the crypto module. + * We will be keeping this for multiple operations + */ + if (SHA2CC26X2_waitForAccess(handle) != SemaphoreP_OK) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + /* Retain access over multiple SHA2 driver calls */ + object->retainAccessCounter++; + + status = SHA2CC26X2_setupHmac(handle, key); + if (status != SHA2_STATUS_SUCCESS) + { + return status; + } + + /* For now, only polling return behaviour is supported for the main data + * segment + * */ + SHA2_ReturnBehavior originalReturnBehavior = object->returnBehavior; + object->returnBehavior = SHA2_RETURN_BEHAVIOR_POLLING; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + /* Add the input message to the hash */ + SHA2CC26X2_addData(handle, data, size); + + object->returnBehavior = originalReturnBehavior; + SHA2CC26X2_configureInterrupts(handle, object, hwAttrs, SHA2_hwiFxn); + + /* Allow the SHA2CC26X2_finalizeHmac() call below to release the access + * semaphore when it completes; + */ + object->retainAccessCounter--; + + return SHA2CC26X2_finalizeHmac(handle, hmac); +} + +/* + * ======== SHA2_reset ======== + */ +void SHA2_reset(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object = (SHA2CC26X2_Object *)handle->object; + + uint32_t key = HwiP_disable(); + + if (object->operationInProgress == true) + { + SHA2_cancelOperation(handle); + } + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + + HwiP_restore(key); +} + +/* + * ======== SHA2_cancelOperation ======== + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle) +{ + SHA2CC26X2_Object *object = handle->object; + uint32_t key; + + key = HwiP_disable(); + + if (!object->operationInProgress) + { + HwiP_restore(key); + return SHA2_STATUS_SUCCESS; + } + + /* Reset the accelerator. Immediately stops ongoing operations. */ + HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = CRYPTO_SWRESET_SW_RESET; + + /* Consume any outstanding interrupts we may have accrued + * since disabling interrupts. + */ + IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + object->bytesInBuffer = 0; + object->bytesProcessed = 0; + object->operationCanceled = true; + object->returnStatus = SHA2_STATUS_CANCELED; + object->retainAccessCounter = 0; + + HwiP_restore(key); + + /* Grant access for other threads to use the crypto module. + * The semaphore must be posted before the callbackFxn to allow the chaining + * of operations. + */ + SemaphoreP_post(&CryptoResourceCC26XX_accessSemaphore); + + if (object->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoResourceCC26XX_operationSemaphore); + } + else + { + /* Call the callback function provided by the application. */ + object->callbackFxn(handle, SHA2_STATUS_CANCELED); + } + + return SHA2_STATUS_SUCCESS; +} + +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type) +{ + + SHA2CC26X2_Object *object = (SHA2CC26X2_Object *)handle->object; + + if (object->operationInProgress) + { + return SHA2_STATUS_ERROR; + } + + object->hashType = type; + + return SHA2_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.h b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.h new file mode 100644 index 00000000..45cc292c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X2.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2017-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SHA2CC26X2.h + * + * @brief SHA2 driver implementation for the CC26X2 family + * + * This file should only be included in the board file to fill the SHA2_config + * struct. + * + * The CC26X2 family has a dedicated hardware crypto accelerator. It is capable + * of multiple AES block cipher modes of operation as well as SHA2 operations. + * Only one operation can be carried out on the accelerator at a time. Mutual + * exclusion is implemented at the driver level and coordinated between all + * drivers relying on the accelerator. It is transparent to the application + * and only noted ensure sensible access timeouts are set. + * + * The driver implementation does not perform runtime checks for most input + * parameters. + * Only values that are likely to have a stochastic element to them are + * checked (such as whether a driver is already open). Higher input parameter + * validation coverage is achieved by turning on assertions when compiling + * the driver. + * + */ + +#ifndef ti_drivers_sha2_SHA2CC26X2__include +#define ti_drivers_sha2_SHA2CC26X2__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Hardware-specific configuration attributes + * + * SHA2CC26X2 hardware attributes are used in the board file by the + * #SHA2_Config struct. + */ +typedef struct +{ + /*! Hardware interrupt priority of the Hash accelerator. + * + * The CC26XX provides 8 interrupt priority levels encoded in three bits: + * + * Value | Description + * ------------ | ----------------------- + * (~0) | Special value: always lowest priority across all OS kernels. + * (7 << 5) | Priority level 7: lowest, but rather use ~0 instead. + * .. | .. + * (0 << 5) | Priority level 0: highest, not supported by this driver + * + * Hardware interrupts with priority level 0 ignore the hardware interrupt dispatcher + * for minimum latency. This is not supported by this driver. + */ + uint8_t intPriority; +} SHA2CC26X2_HWAttrs; + +/*! \cond Internal APIs */ + +#define SHA2CC26X2_MAX_BLOCK_SIZE_BYTES (SHA2_BLOCK_SIZE_BYTES_512) +#define SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES (SHA2_DIGEST_LENGTH_BYTES_512) + +/*! + * @brief SHACC26XX Object + * + * \note The application must not access any member variables of this structure! + */ +typedef struct +{ + bool isOpen; + volatile bool operationInProgress; + bool operationCanceled; + volatile uint8_t retainAccessCounter; + SHA2_ReturnBehavior returnBehavior; + int_fast16_t returnStatus; + uint32_t accessTimeout; + SHA2_CallbackFxn callbackFxn; + SHA2_HashType hashType; + uint16_t bytesInBuffer; + uint32_t bytesProcessed; + uint32_t digest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES / sizeof(uint32_t)]; + uint32_t hmacDigest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES / sizeof(uint32_t)]; + uint8_t buffer[SHA2CC26X2_MAX_BLOCK_SIZE_BYTES]; +} SHA2CC26X2_Object; + +/*! \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sha2_SHA2CC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.c new file mode 100644 index 00000000..d7773219 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.c @@ -0,0 +1,711 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern SHA2_s_SecureCallback sha2SecureCB_ns[]; +extern SHA2CC26X4_ns_Object sha2Object_ns[]; + +/* + * ======== SHA2_ns_callbackFxn ======== + */ +void SHA2_ns_callbackFxn(uintptr_t arg) +{ + SHA2_s_SecureCallback *secureCallbackObject = (SHA2_s_SecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + + if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&CryptoPSACC26X4_operationSemaphore); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + sha2Object_ns[index].callbackFxn(sha2SecureCB_ns[index].handle, sha2SecureCB_ns[index].returnStatus); + } +} + +/* + * ======== SHA2_ns_registerCallback ======== + */ +static psa_status_t SHA2_ns_registerCallback(SHA2_Handle handle, const SHA2_Params *params) +{ + SHA2_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB object */ + SecureCallback_construct(&sha2SecureCB_ns[index].object, SHA2_ns_callbackFxn, (uintptr_t)&sha2SecureCB_ns[index]); + + callbackMsg.handle = handle; + callbackMsg.callback = &sha2SecureCB_ns[index]; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver - assumes CryptoPSACC26X4 lock is already acquired */ + return CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_REGISTER_CALLBACK, invecs, outvecs); +} + +/* + * ======== SHA2_init ======== + */ +void SHA2_init(void) +{ + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + isInitialized = true; + } +} + +/* + * ======== SHA2_open ======== + */ +SHA2_Handle SHA2_open(uint_least8_t index, const SHA2_Params *params) +{ + SHA2_Handle handle = NULL; + SHA2_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (SHA2_Params *)&SHA2_defaultParams; + } + + DebugP_assert(params->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING)) + { + if (SHA2_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + sha2Object_ns[index].returnBehavior = params->returnBehavior; + sha2Object_ns[index].callbackFxn = params->callbackFxn; + sha2Object_ns[index].semaphoreTimeout = params->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== SHA2_construct ======== + */ +SHA2_Handle SHA2_construct(SHA2_Config *config, const SHA2_Params *params) +{ + SHA2_Handle handle = NULL; + SHA2_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (SHA2_Params *)&SHA2_defaultParams; + } + + DebugP_assert(params->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING)) + { + if (SHA2_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + sha2Object_ns[index].returnBehavior = params->returnBehavior; + sha2Object_ns[index].callbackFxn = params->callbackFxn; + sha2Object_ns[index].semaphoreTimeout = params->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING + ? params->timeout + : SemaphoreP_NO_WAIT; + + /* Set power dependency */ + (void)Power_setDependency(PowerCC26XX_PERIPH_CRYPTO); + } + + return handle; +} + +/* + * ======== SHA2_close ======== + */ +void SHA2_close(SHA2_Handle handle) +{ + SHA2_s_CloseMsg closeMsg; + + DebugP_assert(handle); + + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Destruct SecureCallback object */ + SecureCallback_destruct(&sha2SecureCB_ns[index].object); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_CLOSE, invecs, outvecs); + + /* Release power dependency */ + (void)Power_releaseDependency(PowerCC26XX_PERIPH_CRYPTO); +} + +/* + * ======== SHA2_addData ======== + */ +int_fast16_t SHA2_addData(SHA2_Handle handle, const void *data, size_t length) +{ + SHA2_s_AddDataMsg addDataMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + addDataMsg.handle = handle; + addDataMsg.data = data; + addDataMsg.length = length; + invecs[0].base = &addDataMsg; + invecs[0].len = sizeof(addDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_ADD_DATA, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_finalize ======== + */ +int_fast16_t SHA2_finalize(SHA2_Handle handle, void *digest) +{ + SHA2_s_FinalizeMsg finalizeMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.digestOrHmac = digest; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_FINALIZE, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_hashData ======== + */ +int_fast16_t SHA2_hashData(SHA2_Handle handle, const void *data, size_t length, void *digest) +{ + SHA2_s_HashDataMsg hashDataMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + hashDataMsg.handle = handle; + hashDataMsg.data = data; + hashDataMsg.dataLength = length; + hashDataMsg.digest = digest; + invecs[0].base = &hashDataMsg; + invecs[0].len = sizeof(hashDataMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_HASH_DATA, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_setupHmac ======== + */ +int_fast16_t SHA2_setupHmac(SHA2_Handle handle, const CryptoKey *key) +{ + SHA2_s_SetupHmacMsg setupHmacMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + setupHmacMsg.handle = handle; + setupHmacMsg.key = key; + invecs[0].base = &setupHmacMsg; + invecs[0].len = sizeof(setupHmacMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_SETUP_HMAC, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_finalizeHmac ======== + */ +int_fast16_t SHA2_finalizeHmac(SHA2_Handle handle, void *hmac) +{ + SHA2_s_FinalizeMsg finalizeMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + finalizeMsg.handle = handle; + finalizeMsg.digestOrHmac = hmac; + invecs[0].base = &finalizeMsg; + invecs[0].len = sizeof(finalizeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_FINALIZE_HMAC, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_hmac ======== + */ +int_fast16_t SHA2_hmac(SHA2_Handle handle, const CryptoKey *key, const void *data, size_t size, void *hmac) +{ + SHA2_s_HmacMsg hmacMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + hmacMsg.handle = handle; + hmacMsg.key = key; + hmacMsg.data = data; + hmacMsg.dataLength = size; + hmacMsg.hmac = hmac; + invecs[0].base = &hmacMsg; + invecs[0].len = sizeof(hmacMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* Try to get semaphore for Crypto PSA access */ + if (CryptoPSACC26X4_acquireLock(sha2Object_ns[index].semaphoreTimeout) == false) + { + return SHA2_STATUS_RESOURCE_UNAVAILABLE; + } + + if (sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_HMAC, invecs, outvecs); + + if ((sha2Object_ns[index].returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) && (result != SHA2_STATUS_SUCCESS)) + { + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING) + { + CryptoPSACC26X4_releaseLock(); + } + else if (sha2Object_ns[index].returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_pend(&CryptoPSACC26X4_operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = sha2SecureCB_ns[index].returnStatus; + } + + return (result); +} + +/* + * ======== SHA2_reset ======== + */ +void SHA2_reset(SHA2_Handle handle) +{ + SHA2_s_ResetMsg resetMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + + /* Setup interface for input parameters */ + resetMsg.handle = handle; + invecs[0].base = &resetMsg; + invecs[0].len = sizeof(resetMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_RESET, invecs, outvecs); +} + +/* + * ======== SHA2_cancelOperation ======== + */ +int_fast16_t SHA2_cancelOperation(SHA2_Handle handle) +{ + SHA2_s_CancelOperationMsg cancelMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} + +int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type) +{ + SHA2_s_SetHashTypeMsg setHashTypeMsg; + int_fast16_t result = SHA2_STATUS_ERROR; + + /* Setup interface for input parameters */ + setHashTypeMsg.handle = handle; + setHashTypeMsg.type = type; + invecs[0].base = &setHashTypeMsg; + invecs[0].len = sizeof(setHashTypeMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to SHA2_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(SHA2_S_MSG_TYPE_SET_HASH_TYPE, invecs, outvecs); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.h new file mode 100644 index 00000000..cda6d488 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_ns.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file SHA2CC26X4_ns.h + * + * @brief SHA2 Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_sha2_SHA2CC26X4_ns__include +#define ti_drivers_sha2_SHA2CC26X4_ns__include + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief SHA2CC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + uint32_t semaphoreTimeout; + SHA2_CallbackFxn callbackFxn; + SHA2_ReturnBehavior returnBehavior; +} SHA2CC26X4_ns_Object; + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sha2_SHA2CC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.c b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.c new file mode 100644 index 00000000..15573d96 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.c @@ -0,0 +1,1016 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "SHA2CC26X4_s.h" + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +/* + * SHA2 Secure Dynamic Instance struct. + */ +typedef struct +{ + SHA2_Config config; + SHA2CC26X2_Object object; + SHA2CC26X2_HWAttrs hwAttrs; +} SHA2_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * SHA2_construct. + */ +static SHA2_s_DynamicInstance SHA2_s_dynInstance[CONFIG_SHA2_S_CONFIG_POOL_SIZE]; + +/* Stores pointers to non-secure SHA2_s_SecureCallbacks for each driver instance opened or constructed */ +static SHA2_s_SecureCallback *SHA2_s_secureCB[SHA2_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const SHA2_Config SHA2_config[]; + +/* Digest size table defined in SHA2CC26X2.c */ +extern const uint8_t digestSizeTable[]; + +/* + * ======== SHA2_s_getHashLength ======== + * Returns the length of the hash or zero if hash type is invalid. + */ +static uint8_t SHA2_s_getHashLength(SHA2CC26X2_Object *object) +{ + uint8_t hashLen = 0; + + if (object->hashType <= SHA2_HASH_TYPE_512) + { + hashLen = digestSizeTable[object->hashType]; + } + + return hashLen; +} + +/* + * ======== SHA2_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t SHA2_s_getCallbackIndex(SHA2_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_SHA2_COUNT; index++) + { + if (handle_s == (SHA2_Handle)&SHA2_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_SHA2_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &SHA2_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_SHA2_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== SHA2_s_hwiCallback ======== + */ +static void SHA2_s_hwiCallback(SHA2_Handle handle_s, int_fast16_t returnStatus) +{ + int8_t index; + SHA2_s_SecureCallback *sha2SecureCB_ns; + + index = SHA2_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < SHA2_SECURE_CALLBACK_COUNT)) + { + sha2SecureCB_ns = SHA2_s_secureCB[index]; + + if (sha2SecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + sha2SecureCB_ns->handle = (SHA2_Handle)(CRYPTO_S_HANDLE_ID_SHA2 | index); + sha2SecureCB_ns->returnStatus = returnStatus; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&sha2SecureCB_ns->object); + } + } +} + +/* + * ======== SHA2_s_copyConfig ======== + */ +static inline psa_status_t SHA2_s_copyConfig(SHA2_Config **secureConfig, + const SHA2_Config *config, + SHA2_Handle *retHandle) +{ + SHA2_Config *config_s; + SHA2_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_SHA2_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &SHA2_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + SHA2_s_secureCB[i + CONFIG_TI_DRIVERS_SHA2_COUNT] = NULL; + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_SHA2 OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (SHA2_Handle)(CRYPTO_S_HANDLE_ID_SHA2 | (i + CONFIG_TI_DRIVERS_SHA2_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== SHA2_s_releaseConfig ======== + */ +static inline void SHA2_s_releaseConfig(SHA2_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_SHA2) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_SHA2_COUNT) && (i < SHA2_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + SHA2_s_dynInstance[i - CONFIG_TI_DRIVERS_SHA2_COUNT].config.object = NULL; + } + } +} + +/* + * ======== SHA2_s_copyParams ======== + */ +static psa_status_t SHA2_s_copyParams(SHA2_Params *secureParams, const SHA2_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(SHA2_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(SHA2_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == SHA2_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == SHA2_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == SHA2_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != SHA2_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback function with our own + * callback which will populate the secure callback object registered + * using SHA2_S_MSG_TYPE_REGISTER_CALLBACK. + */ + secureParams->callbackFxn = SHA2_s_hwiCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = SHA2_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== SHA2_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static SHA2_Handle SHA2_s_getHandle(SHA2_Handle nsHandle) +{ + SHA2_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_SHA2) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_SHA2_COUNT) + { + secureHandle = (SHA2_Handle)&SHA2_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_SHA2_COUNT) && (i < SHA2_SECURE_CALLBACK_COUNT)) + { + secureHandle = &SHA2_s_dynInstance[i - CONFIG_TI_DRIVERS_SHA2_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== SHA2_s_registerCallback ======== + */ +static inline psa_status_t SHA2_s_registerCallback(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + handle_s = SHA2_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = SHA2_s_getCallbackIndex(handle_s); + + /* Validate index and callback object address range */ + if ((callbackIndex >= 0) && (callbackIndex < SHA2_SECURE_CALLBACK_COUNT) && + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.callback, sizeof(SHA2_s_SecureCallback)) != NULL)) + { + /* + * Store the pointer to SHA2_s_SecureCallback located in + * non-secure memory. + */ + SHA2_s_secureCB[callbackIndex] = callbackMsg.callback; + + status = PSA_SUCCESS; + } + } + + return status; +} + +/* + * ======== SHA2_s_construct ======== + */ +static inline psa_status_t SHA2_s_construct(psa_msg_t *msg) +{ + SHA2_s_ConstructMsg constructMsg; + SHA2_Handle handle; + SHA2_Params params_s; + const SHA2_Params *paramsPtr_s = NULL; + SHA2_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + SHA2_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = SHA2_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = SHA2_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = SHA2_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_open ======== + */ +static inline psa_status_t SHA2_s_open(psa_msg_t *msg) +{ + SHA2_s_OpenMsg openMsg; + SHA2_Handle handle; + SHA2_Params params_s; + SHA2_Params *paramsPtr_s = NULL; + SHA2_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = SHA2_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = SHA2_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback object pointer to NULL. The non-secure + * client must register a secure callback after constructing or + * opening a driver instance. + */ + SHA2_s_secureCB[openMsg.index] = NULL; + + /* + * Return CRYPTO_S_HANDLE_ID_SHA2 OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (SHA2_Handle)(CRYPTO_S_HANDLE_ID_SHA2 | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_close ======== + */ +static inline psa_status_t SHA2_s_close(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + SHA2_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + SHA2_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + SHA2_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_hashData ======== + */ +static inline psa_status_t SHA2_s_hashData(psa_msg_t *msg) +{ + SHA2_s_HashDataMsg hashMsg; + SHA2_Handle handle_s; + SHA2CC26X2_Object *object; + int_fast16_t ret; + psa_status_t status = PSA_SUCCESS; + uint8_t hashLen; + + if ((msg->in_size[0] != sizeof(hashMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &hashMsg, sizeof(hashMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(hashMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + hashLen = SHA2_s_getHashLength(object); + if (hashLen == 0) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate input data address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)hashMsg.data, hashMsg.dataLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate output digest address range */ + if (cmse_has_unpriv_nonsecure_rw_access((void *)hashMsg.digest, hashLen) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_hashData(handle_s, hashMsg.data, hashMsg.dataLength, hashMsg.digest); + } + else /* Secure client */ + { + ret = SHA2_hashData(hashMsg.handle, hashMsg.data, hashMsg.dataLength, hashMsg.digest); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return status; +} + +/* + * ======== SHA2_s_hmac ======== + */ +static inline psa_status_t SHA2_s_hmac(psa_msg_t *msg) +{ + /* + * Secure key may be stored on the stack because SHA2_hmac() processes + * the key in polling mode regardless of the return behavior specified. + */ + CryptoKey key_s; + SHA2_s_HmacMsg hmacMsg; + SHA2_Handle handle_s; + SHA2CC26X2_Object *object; + int_fast16_t ret; + uint8_t hashLen; + + if ((msg->in_size[0] != sizeof(hmacMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &hmacMsg, sizeof(hmacMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(hmacMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + hashLen = SHA2_s_getHashLength(object); + if (hashLen == 0) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = CryptoKey_copySecureInputKey(&key_s, &hmacMsg.key); + if (ret != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate input data address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)hmacMsg.data, hmacMsg.dataLength) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate output HMAC address range */ + if (cmse_has_unpriv_nonsecure_rw_access(hmacMsg.hmac, hashLen) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_hmac(handle_s, &key_s, hmacMsg.data, hmacMsg.dataLength, hmacMsg.hmac); + } + else /* Secure client */ + { + ret = SHA2_hmac(hmacMsg.handle, hmacMsg.key, hmacMsg.data, hmacMsg.dataLength, hmacMsg.hmac); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_setHashType ======== + */ +static inline psa_status_t SHA2_s_setHashType(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_SetHashTypeMsg setTypeMsg; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setTypeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setTypeMsg, sizeof(setTypeMsg)); + + /* Verify hash type is valid */ + if ((setTypeMsg.type < SHA2_HASH_TYPE_224) || (setTypeMsg.type > SHA2_HASH_TYPE_512)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(setTypeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_setHashType(handle_s, setTypeMsg.type); + } + else /* Secure client */ + { + ret = SHA2_setHashType(setTypeMsg.handle, setTypeMsg.type); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_setupHmac ======== + */ +static inline psa_status_t SHA2_s_setupHmac(psa_msg_t *msg) +{ + /* + * Secure key may be stored on the stack because SHA2_hmac() processes + * the key in polling mode regardless of the return behavior specified. + */ + CryptoKey key_s; + SHA2_Handle handle_s; + SHA2_s_SetupHmacMsg setupMsg; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(setupMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &setupMsg, sizeof(setupMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(setupMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = CryptoKey_copySecureInputKey(&key_s, &setupMsg.key); + if (ret != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_setupHmac(handle_s, &key_s); + } + else /* Secure client */ + { + ret = SHA2_setupHmac(setupMsg.handle, setupMsg.key); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_addData ======== + */ +static inline psa_status_t SHA2_s_addData(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_AddDataMsg addDataMsg; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(addDataMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &addDataMsg, sizeof(addDataMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(addDataMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify data address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)addDataMsg.data, addDataMsg.length) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_addData(handle_s, addDataMsg.data, addDataMsg.length); + } + else /* Secure client */ + { + ret = SHA2_addData(addDataMsg.handle, addDataMsg.data, addDataMsg.length); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_finalize ======== + */ +static inline psa_status_t SHA2_s_finalize(psa_msg_t *msg, int32_t msgType) +{ + SHA2_Handle handle_s; + SHA2_s_FinalizeMsg finalizeMsg; + SHA2CC26X2_Object *object; + int_fast16_t ret; + uint8_t hashLen; + + if ((msg->in_size[0] != sizeof(finalizeMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &finalizeMsg, sizeof(finalizeMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(finalizeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + object = handle_s->object; + hashLen = SHA2_s_getHashLength(object); + if (hashLen == 0) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Verify digest output address range */ + if (cmse_has_unpriv_nonsecure_rw_access(finalizeMsg.digestOrHmac, hashLen) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + } + else /* Secure client */ + { + handle_s = finalizeMsg.handle; + } + + if (msgType == SHA2_S_MSG_TYPE_FINALIZE) + { + ret = SHA2_finalize(handle_s, finalizeMsg.digestOrHmac); + } + else /* SHA2_S_MSG_TYPE_FINALIZE_HMAC */ + { + ret = SHA2_finalizeHmac(handle_s, finalizeMsg.digestOrHmac); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_cancelOperation ======== + */ +static inline psa_status_t SHA2_s_cancelOperation(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = SHA2_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = SHA2_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_reset ======== + */ +static inline psa_status_t SHA2_s_reset(psa_msg_t *msg) +{ + SHA2_Handle handle_s; + SHA2_s_ResetMsg resetMsg; + + if (msg->in_size[0] != sizeof(resetMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &resetMsg, sizeof(resetMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = SHA2_s_getHandle(resetMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + SHA2_reset(handle_s); + } + else + { + SHA2_reset(resetMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== SHA2_s_handlePsaMsg ======== + */ +psa_status_t SHA2_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If SHA2_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case SHA2_S_MSG_TYPE_CONSTRUCT: + status = SHA2_s_construct(msg); + break; + + case SHA2_S_MSG_TYPE_OPEN: + status = SHA2_s_open(msg); + break; + + /* + * SHA2_S_MSG_TYPE_REGISTER_CALLBACK is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case SHA2_S_MSG_TYPE_REGISTER_CALLBACK: + status = SHA2_s_registerCallback(msg); + break; + + case SHA2_S_MSG_TYPE_CLOSE: + status = SHA2_s_close(msg); + break; + + case SHA2_S_MSG_TYPE_HASH_DATA: + status = SHA2_s_hashData(msg); + break; + + case SHA2_S_MSG_TYPE_HMAC: + status = SHA2_s_hmac(msg); + break; + + case SHA2_S_MSG_TYPE_SET_HASH_TYPE: + status = SHA2_s_setHashType(msg); + break; + + case SHA2_S_MSG_TYPE_SETUP_HMAC: + status = SHA2_s_setupHmac(msg); + break; + + case SHA2_S_MSG_TYPE_ADD_DATA: + status = SHA2_s_addData(msg); + break; + + case SHA2_S_MSG_TYPE_FINALIZE: /* Fall through */ + case SHA2_S_MSG_TYPE_FINALIZE_HMAC: + status = SHA2_s_finalize(msg, msg->type); + break; + + /* + * SHA2_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case SHA2_S_MSG_TYPE_CANCEL_OPERATION: + status = SHA2_s_cancelOperation(msg); + break; + + case SHA2_S_MSG_TYPE_RESET: + status = SHA2_s_reset(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== SHA2_s_init ======== + */ +void SHA2_s_init(void) +{ + SHA2_init(); +} diff --git a/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.h b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.h new file mode 100644 index 00000000..7e0d9c33 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/sha2/SHA2CC26X4_s.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_sha2_SHA2CC26X4_s__include +#define ti_drivers_sha2_SHA2CC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SHA2 secure message types + */ +#define SHA2_S_MSG_TYPE_CONSTRUCT SHA2_S_MSG_TYPE(0U) +#define SHA2_S_MSG_TYPE_OPEN SHA2_S_MSG_TYPE(1U) +#define SHA2_S_MSG_TYPE_REGISTER_CALLBACK SHA2_S_MSG_TYPE(2U) +#define SHA2_S_MSG_TYPE_CLOSE SHA2_S_MSG_TYPE(3U) +#define SHA2_S_MSG_TYPE_HASH_DATA SHA2_S_MSG_TYPE(4U) +#define SHA2_S_MSG_TYPE_HMAC SHA2_S_MSG_TYPE(5U) +#define SHA2_S_MSG_TYPE_SET_HASH_TYPE SHA2_S_MSG_TYPE(6U) +#define SHA2_S_MSG_TYPE_SETUP_HMAC SHA2_S_MSG_TYPE(7U) +#define SHA2_S_MSG_TYPE_ADD_DATA SHA2_S_MSG_TYPE(8U) +#define SHA2_S_MSG_TYPE_FINALIZE SHA2_S_MSG_TYPE(9U) +#define SHA2_S_MSG_TYPE_FINALIZE_HMAC SHA2_S_MSG_TYPE(10U) +#define SHA2_S_MSG_TYPE_CANCEL_OPERATION SHA2_S_MSG_TYPE(11U) +#define SHA2_S_MSG_TYPE_RESET SHA2_S_MSG_TYPE(12U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using SHA2_construct(). + */ +#ifndef CONFIG_SHA2_S_CONFIG_POOL_SIZE + #define CONFIG_SHA2_S_CONFIG_POOL_SIZE 2 /* One instance used for EdDSA */ +#endif + +#define SHA2_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_SHA2_COUNT + CONFIG_SHA2_S_CONFIG_POOL_SIZE) + +/* + * ========= SHA2 Secure Callback struct ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* SHA2 callback fxn parameters */ + SHA2_Handle handle; + int_fast16_t returnStatus; +} SHA2_s_SecureCallback; + +/* + * ========= SHA2 Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * SHA2 secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + SHA2_Config *config; + const SHA2_Params *params; +} SHA2_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const SHA2_Params *params; +} SHA2_s_OpenMsg; + +typedef struct +{ + SHA2_Handle handle; + SHA2_s_SecureCallback *callback; +} SHA2_s_CallbackMsg; + +typedef struct +{ + SHA2_Handle handle; +} SHA2_s_CloseMsg; + +typedef struct +{ + SHA2_Handle handle; + const void *data; + size_t dataLength; + void *digest; +} SHA2_s_HashDataMsg; + +typedef struct +{ + SHA2_Handle handle; + const CryptoKey *key; + const void *data; + size_t dataLength; + void *hmac; +} SHA2_s_HmacMsg; + +typedef struct +{ + SHA2_Handle handle; + SHA2_HashType type; +} SHA2_s_SetHashTypeMsg; + +typedef struct +{ + SHA2_Handle handle; + const CryptoKey *key; +} SHA2_s_SetupHmacMsg; + +typedef struct +{ + SHA2_Handle handle; + const void *data; + size_t length; +} SHA2_s_AddDataMsg; + +/* For SHA2_S_MSG_TYPE_FINALIZE or SHA2_S_MSG_TYPE_FINALIZE_HMAC */ +typedef struct +{ + SHA2_Handle handle; + void *digestOrHmac; +} SHA2_s_FinalizeMsg; + +typedef struct +{ + SHA2_Handle handle; +} SHA2_s_CancelOperationMsg; + +typedef struct +{ + SHA2_Handle handle; +} SHA2_s_ResetMsg; + +/*! + * @brief Handles PSA messages for SHA2 secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t SHA2_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the SHA2 secure driver. + * + * @note This function should be called by secure partition thread only. + */ +void SHA2_s_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_sha2_SHA2CC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.c b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.c new file mode 100644 index 00000000..846984d3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.c @@ -0,0 +1,1588 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/ssi.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Headers required for intrinsics */ +#if defined(__TI_COMPILER_VERSION__) + #include +#elif defined(__GNUC__) + #include +#elif defined(__IAR_SYSTEMS_ICC__) + #include +#else + #error "Unsupported compiler" +#endif + +#define MAX_DMA_TRANSFER_AMOUNT (1024) + +/* SPI test control register */ +#define SSI_O_TCR (0x00000080) +#define SSI_TCR_TESTFIFO_ENABLE (0x2) +#define SSI_TCR_TESTFIFO_DISABLE (0x0) +/* SPI test data register */ +#define SSI_O_TDR (0x0000008C) + +#define PARAMS_DATASIZE_MIN (4) +#define PARAMS_DATASIZE_MAX (16) + +/* API Function Prototypes */ +void SPICC26X2DMA_close(SPI_Handle handle); +int_fast16_t SPICC26X2DMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg); +void SPICC26X2DMA_init(SPI_Handle handle); +SPI_Handle SPICC26X2DMA_open(SPI_Handle handle, SPI_Params *params); +static void SPICC26X2DMA_swiFxn(uintptr_t arg0, uintptr_t arg1); +bool SPICC26X2DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); +void SPICC26X2DMA_transferCancel(SPI_Handle handle); + +/* Local Function Prototypes */ +static void blockingTransferCallback(SPI_Handle handle, SPI_Transaction *msg); +static void configNextTransfer(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs); +static void csnCallback(uint_least8_t index); +static void flushFifos(SPICC26X2DMA_HWAttrs const *hwAttrs); +static inline uint32_t getDmaChannelNumber(uint32_t x); +static void initHw(SPI_Handle handle); +static void initIO(SPI_Handle handle); +static void finalizeIO(SPI_Handle handle); +static inline void primeTransfer(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs); +static inline void releaseConstraint(uint32_t txBufAddr); +static inline void setConstraint(uint32_t txBufAddr); +static inline void spiPollingTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs, + SPI_Transaction *transaction); +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +static inline bool spiBusy(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs); +static void finishTransfer(SPI_Handle handle); +static void processCSNDeassert(SPI_Handle handle); + +/* SPI function table for SPICC26X2DMA implementation */ +const SPI_FxnTable SPICC26X2DMA_fxnTable = {SPICC26X2DMA_close, + SPICC26X2DMA_control, + SPICC26X2DMA_init, + SPICC26X2DMA_open, + SPICC26X2DMA_transfer, + SPICC26X2DMA_transferCancel}; + +/* Mapping SPI frame format from generic driver to CC26XX driverlib */ +static const uint32_t frameFormat[] = { + SSI_FRF_MOTO_MODE_0, /* SPI_POLO_PHA0 */ + SSI_FRF_MOTO_MODE_1, /* SPI_POLO_PHA1 */ + SSI_FRF_MOTO_MODE_2, /* SPI_POL1_PHA0 */ + SSI_FRF_MOTO_MODE_3, /* SPI_POL1_PHA1 */ + SSI_FRF_TI, /* SPI_TI */ + SSI_FRF_NMW /* SPI_MW */ +}; + +/* + * These lookup tables are used to configure the DMA channels for the + * appropriate (8bit or 16bit) transfer sizes. + */ +static const uint32_t dmaTxConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | + UDMA_ARB_4}; + +static const uint32_t dmaRxConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | + UDMA_ARB_4}; + +static const uint32_t dmaNullConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4}; + +/* + * ======== SPICC26X2DMA_close ======== + */ +void SPICC26X2DMA_close(SPI_Handle handle) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + SSIDisable(hwAttrs->baseAddr); + + HwiP_destruct(&(object->hwi)); + + UDMACC26XX_close(object->udmaHandle); + + SwiP_destruct(&(object->swi)); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + SemaphoreP_destruct(&(object->transferComplete)); + } + + finalizeIO(handle); + + Power_releaseDependency(hwAttrs->powerMngrId); + + Power_unregisterNotify(&object->spiPostObj); + + object->isOpen = false; +} + +/*! + * @brief Function for setting control parameters of the SPI driver + * after it has been opened. + * + * @pre SPICC26X2DMA_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI handle returned from SPICC26X2DMA_open() + * + * @param cmd The command to execute, supported commands are: + * | Command | Description | + * |-------------------------------------------|------------------------------| + * | ::SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE | Enable RETURN_PARTIAL | + * | ::SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE | Disable RETURN_PARTIAL | + * | ::SPICC26X2DMA_CMD_SET_CSN_PIN | Re-configure chip select pin | + * | ::SPICC26X2DMA_CMD_SET_MANUAL | Enable manual start mode | + * | ::SPICC26X2DMA_CMD_CLR_MANUAL | Disable manual start mode | + * | ::SPICC26X2DMA_CMD_MANUAL_START | Perform a manual start | + * + * @param *arg Pointer to command arguments. + * + * @return ::SPI_STATUS_SUCCESS if success, or error code if error. + */ +int_fast16_t SPICC26X2DMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + uint_least8_t pinIndex; + + /* Initialize return value*/ + int ret = SPI_STATUS_ERROR; + + /* Perform command */ + switch (cmd) + { + case SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL if peripheral mode is enabled */ + + if (object->mode == SPI_PERIPHERAL) + { + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + ret = SPI_STATUS_SUCCESS; + } + else + { + /* Partial return not available in controller mode. */ + ret = SPI_STATUS_ERROR; + } + break; + + case SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE: + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X2DMA_retPartDisabled; + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X2DMA_CMD_SET_CSN_PIN: + pinIndex = *((uint_least8_t *)arg); + + if (pinIndex == GPIO_INVALID_INDEX) + { + /* If trying to disable the CS pin, forward to the CLEAR_CSN command and break */ + ret = SPICC26X2DMA_control(handle, SPICC26X2DMA_CMD_CLEAR_CSN_PIN, NULL); + break; + } + + /* Reset the previous CS pin and configure the new one */ + GPIO_resetConfig(object->csnPin); + object->csnPin = pinIndex; + GPIO_setConfigAndMux(object->csnPin, GPIO_CFG_INPUT, hwAttrs->csnPinMux); + + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X2DMA_CMD_CLEAR_CSN_PIN: + /* If the CS pin is assigned, reset and unassign it */ + if (object->csnPin != GPIO_INVALID_INDEX) + { + GPIO_resetConfig(object->csnPin); + object->csnPin = GPIO_INVALID_INDEX; + } + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X2DMA_CMD_SET_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) + { + object->manualStart = true; + ret = SPI_STATUS_SUCCESS; + } + break; + + case SPICC26X2DMA_CMD_CLR_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) + { + object->manualStart = false; + ret = SPI_STATUS_SUCCESS; + } + break; + + case SPICC26X2DMA_CMD_MANUAL_START: + if (object->headPtr != NULL && object->manualStart) + { + SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + SSIEnable(hwAttrs->baseAddr); + ret = SPI_STATUS_SUCCESS; + } + break; + + default: + /* This command is not defined */ + ret = SPI_STATUS_UNDEFINEDCMD; + break; + } + + return (ret); +} + +/* + * ======== SPICC26X2DMA_hwiFxn ======== + */ +static void SPICC26X2DMA_hwiFxn(uintptr_t arg) +{ + uint32_t freeChannel; + uint32_t intStatus; + SPI_Transaction *completedList; + size_t *transferSize; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + SPICC26X2DMA_Object *object = ((SPI_Handle)arg)->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = ((SPI_Handle)arg)->hwAttrs; + uint8_t i; + uintptr_t key; + + intStatus = SSIIntStatus(hwAttrs->baseAddr, true); + SSIIntClear(hwAttrs->baseAddr, intStatus); + + if (intStatus & SSI_RXOR) + { + if (object->headPtr != NULL) + { + /* + * RX overrun during a transfer; mark the current transfer + * as failed & cancel all remaining transfers. + */ + object->headPtr->status = SPI_TRANSFER_FAILED; + + SPICC26X2DMA_transferCancel((SPI_Handle)arg); + } + else + { + SSIDisable(hwAttrs->baseAddr); + + /* Disable DMA and clear DMA interrupts */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR); + + /* Clear out the FIFO by resetting SPI module and re-initting */ + flushFifos(hwAttrs); + } + } + else + { + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + + /* + * We check both channels for completion; this is done in case the + * second channel finishes while we are still configuring the first. + */ + for (i = 0; i < 2; i++) + { + if (object->headPtr == NULL) + { + /* When i was 0, we finished the last transaction */ + break; + } + + if (object->activeChannel == UDMA_PRI_SELECT) + { + transferSize = &object->priTransferSize; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryPri; + txDmaTableEntry = hwAttrs->dmaTxTableEntryPri; + } + else + { + transferSize = &object->altTransferSize; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryAlt; + txDmaTableEntry = hwAttrs->dmaTxTableEntryAlt; + } + + /* + * The SPI TX FIFO continuously requests the DMA to fill it if there + * is space available. If there are no more frames to put in the + * FIFO we run into a situation where DMA TX will cause undesired + * interrupts. To prevent many undesired interrupts disable DMA_TX + * uf there are no more frames to load into the FIFO & there are no + * pending queued transactions. + */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask) && + (txDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && + object->framesQueued == object->headPtr->count && object->headPtr->nextPtr == NULL) + { + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelBitMask); + } + + if ((rxDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && *transferSize != 0) + { + object->framesTransferred += *transferSize; + freeChannel = object->activeChannel; + object->activeChannel = (freeChannel == UDMA_PRI_SELECT) ? UDMA_ALT_SELECT : UDMA_PRI_SELECT; + + /* + * Set the channel's transfer size to 0; 0 lets + * configNextTransfer() know that there is a free channel. + */ + *transferSize = 0; + + if ((object->framesQueued) < (object->headPtr->count) || + (object->framesTransferred) < (object->headPtr->count)) + { + /* + * In this case we need to reconfigure the channel to + * continue transferring frames. configNextTransfer() will + * continue queueing frames for the current transfer or + * start the following transaction if necessary. + */ + configNextTransfer(object, hwAttrs); + + if (object->manualStart && UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) + { + /* Ping pong flow was broken, restart */ + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->txChannelBitMask); + } + } + else + { + key = HwiP_disable(); + /* + * All data has been transferred for the current + * transaction. Set status & move the transaction to + * object->completedList. This is required because + * object->headPtr is moved to the following transaction. + * Also, transaction callbacks are executed in the driver + * SWI which will be posted later. + */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + + if (object->completedTransfers == NULL) + { + /* List is empty; just add the transaction */ + object->completedTransfers = object->headPtr; + completedList = object->completedTransfers; + } + else + { + /* Traverse to the last element */ + completedList = object->completedTransfers; + while (completedList->nextPtr != NULL) + { + completedList = completedList->nextPtr; + } + + /* Store the completed transaction at end of list */ + completedList->nextPtr = object->headPtr; + + /* + * Make sure we are pointing to the end of the list; + * we need to clear references in completed transfer + * after we move object->headPtr forward. + */ + completedList = completedList->nextPtr; + } + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Clear references in completed transfer */ + completedList->nextPtr = NULL; + + /* Update object variables for the following transfer. */ + object->framesQueued = (object->activeChannel == UDMA_PRI_SELECT) ? object->priTransferSize + : object->altTransferSize; + object->framesTransferred = 0; + + HwiP_restore(key); + + if (object->headPtr != NULL) + { + /* Reconfigure channel for following transaction */ + configNextTransfer(object, hwAttrs); + + if (object->manualStart && + UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) + { + /* Ping pong flow was broken, restart */ + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->txChannelBitMask); + } + } + else + { + /* No more queued transfers; disable DMA & SPI */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + + /* + * For this driver implementation the peripheral is kept + * active until either a FIFO-overrun occurs or + * SPI_transferCancel() is executed. + */ + } + + /* Post driver SWI to execute transaction callbacks */ + SwiP_post(&(object->swi)); + } + } + } + } +} + +/* + * ======== SPICC26X2DMA_init ======== + */ +void SPICC26X2DMA_init(SPI_Handle handle) +{ + ((SPICC26X2DMA_Object *)handle->object)->isOpen = false; +} + +/* + * ======== SPICC26X2DMA_open ======== + */ +SPI_Handle SPICC26X2DMA_open(SPI_Handle handle, SPI_Params *params) +{ + union + { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + uint32_t key; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + /* Failure conditions */ + if (object->isOpen || params->dataSize > PARAMS_DATASIZE_MAX || params->dataSize < PARAMS_DATASIZE_MIN) + { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->dataSize >= 4) && (params->dataSize <= 16)); + + object->bitRate = params->bitRate; + object->dataSize = params->dataSize; + object->mode = params->mode; + object->transferMode = params->transferMode; + object->transferTimeout = params->transferTimeout; + object->returnPartial = SPICC26X2DMA_retPartDisabled; + object->headPtr = NULL; + object->tailPtr = NULL; + object->completedTransfers = NULL; + object->format = frameFormat[params->frameFormat]; + object->txScratchBuf = hwAttrs->defaultTxBufValue; + object->busyBit = (params->mode == SPI_CONTROLLER) ? SSI_SR_BSY : SSI_SR_TFE; + object->manualStart = false; + + Power_setDependency(hwAttrs->powerMngrId); + + initHw(handle); + + /* CSN is initialized using hwAttrs, but can be re-configured later */ + object->csnPin = hwAttrs->csnPin; + initIO(handle); + + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int)hwAttrs->intNum, SPICC26X2DMA_hwiFxn, ¶msUnion.hwiParams); + + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), SPICC26X2DMA_swiFxn, &(paramsUnion.swiParams)); + + object->udmaHandle = UDMACC26XX_open(); + + Power_registerNotify(&object->spiPostObj, + PowerCC26XX_AWAKE_STANDBY, + (Power_NotifyFxn)spiPostNotify, + (uint32_t)handle); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + /* + * Create a semaphore to block task execution for the duration of the + * SPI transfer + */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + object->transferCallbackFxn = blockingTransferCallback; + } + else + { + DebugP_assert(params->transferCallbackFxn != NULL); + object->transferCallbackFxn = params->transferCallbackFxn; + } + + return (handle); +} + +/* + * ======== SPICC26X2DMA_swiFxn ======== + */ +static void SPICC26X2DMA_swiFxn(uintptr_t arg0, uintptr_t arg1) +{ + SPI_Transaction *transaction; + SPICC26X2DMA_Object *object = ((SPI_Handle)arg0)->object; + uintptr_t key; + + /* To protect against any Linked-List manipulation, we took ownership of the processor and disabled interrupts + * This also includes the while loop check here, since another process might temporarily tamper with + * object->copmoletedTransfers + */ + key = HwiP_disable(); + + while (object->completedTransfers != NULL) + { + transaction = object->completedTransfers; + + /* Move object->completedTransfers to the next transaction */ + object->completedTransfers = object->completedTransfers->nextPtr; + + transaction->nextPtr = NULL; + + /* Transaction complete; release power constraints */ + releaseConstraint((uint32_t)transaction->txBuf); + + /* Inverted logic here to restore interrupts right before we jump to the callback function and disable them + * after we return */ + HwiP_restore(key); + + /* Execute callback function for completed transfer */ + object->transferCallbackFxn((SPI_Handle)arg0, transaction); + + key = HwiP_disable(); + } + + /* Restore interrupts */ + HwiP_restore(key); +} + +/* + * ======== SPICC26X2DMA_transfer ======== + */ +bool SPICC26X2DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + uint8_t alignMask; + bool buffersAligned; + uintptr_t key; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (transaction->count == 0) + { + return (false); + } + + key = HwiP_disable(); + + /* + * Make sure that the buffers are aligned properly. + * alignMask is used to check if the RX/TX buffers addresses + * are aligned to the frameSize. + */ + alignMask = (object->dataSize < 9) ? 0x0 : 0x01; + buffersAligned = ((((uint32_t)transaction->rxBuf & alignMask) == 0) && + (((uint32_t)transaction->txBuf & alignMask) == 0)); + + if (!buffersAligned || (object->headPtr && object->transferMode == SPI_MODE_BLOCKING)) + { + transaction->status = SPI_TRANSFER_FAILED; + + HwiP_restore(key); + + return (false); + } + else + { + if (object->headPtr) + { + object->tailPtr->nextPtr = transaction; + object->tailPtr = transaction; + object->tailPtr->status = SPI_TRANSFER_QUEUED; + } + else + { + object->headPtr = transaction; + object->tailPtr = transaction; + + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + object->tailPtr->status = (object->returnPartial != SPICC26X2DMA_retPartDisabled) + ? SPI_TRANSFER_PEND_CSN_ASSERT + : SPI_TRANSFER_STARTED; + } + + object->tailPtr->nextPtr = NULL; + } + + /* In peripheral mode, optionally enable callback on CSN de-assert */ + if (object->returnPartial == SPICC26X2DMA_retPartEnabledIntNotSet) + { + object->returnPartial = SPICC26X2DMA_retPartEnabledIntSet; + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_ENABLE | GPIO_CFG_IN_INT_BOTH_EDGES); + } + + /* Set constraints to guarantee transaction */ + setConstraint((uint32_t)transaction->txBuf); + + /* + * Polling transfer if BLOCKING mode & transaction->count < threshold + * Peripherals are not allowed to use polling unless timeout is disabled + * Polling not allowed with returnPartial mode + */ + if (object->transferMode == SPI_MODE_BLOCKING && transaction->count < hwAttrs->minDmaTransferSize && + object->returnPartial == SPICC26X2DMA_retPartDisabled && + (object->mode == SPI_CONTROLLER || object->transferTimeout == SPI_WAIT_FOREVER)) + { + HwiP_restore(key); + + spiPollingTransfer(object, hwAttrs, transaction); + + /* Release constraint since transaction is done */ + releaseConstraint((uint32_t)transaction->txBuf); + + /* Transaction completed; set status & mark SPI ready */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + object->headPtr = NULL; + object->tailPtr = NULL; + } + else + { + /* + * Perform a DMA backed SPI transfer; we need exclusive access while + * priming the transfer to prevent race conditions with + * SPICC26X2DMA_transferCancel(). + */ + primeTransfer(object, hwAttrs); + + /* Enable the RX overrun interrupt in the SSI module */ + SSIIntEnable(hwAttrs->baseAddr, SSI_RXOR); + + HwiP_restore(key); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + if (SemaphoreP_OK != SemaphoreP_pend(&(object->transferComplete), object->transferTimeout)) + { + /* Timeout occurred; cancel the transfer */ + object->headPtr->status = SPI_TRANSFER_FAILED; + SPICC26X2DMA_transferCancel(handle); + + /* + * SPICC26X2DMA_transferCancel() performs callback which posts + * transferComplete semaphore. This call consumes this extra + * post. + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_NO_WAIT); + + return (false); + } + } + } + return (true); +} + +/* + * ======== SPICC26X2DMA_transferCancel ======== + */ +void SPICC26X2DMA_transferCancel(SPI_Handle handle) +{ + uintptr_t key; + uint32_t temp; + SPI_Transaction *tempPtr; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Acquire exclusive access to the driver. Required to prevent race + * conditions if preempted by code trying to configure another transfer. + */ + key = HwiP_disable(); + + if (object->headPtr == NULL) + { + + /* + * Disable the SPI peripheral in case the peripherals finite state + * machine is in a bad state. Calling SPI_transfer() will re-enable + * the peripheral. + */ + SSIDisable(hwAttrs->baseAddr); + HwiP_restore(key); + + return; + } + + /* + * There are 2 use cases in which to call transferCancel(): + * 1. The driver is in CALLBACK mode. + * 2. The driver is in BLOCKING mode & there has been a transfer timeout. + */ + if (object->transferMode != SPI_MODE_BLOCKING || object->headPtr->status == SPI_TRANSFER_FAILED || + object->headPtr->status == SPI_TRANSFER_CSN_DEASSERT) + { + finishTransfer(handle); + + /* + * Go through all queued transfers; set status CANCELED (if we did + * not cancel due to timeout). The object->headPtr->count is + * stored/restored temporarily. + */ + temp = object->headPtr->count; + tempPtr = object->headPtr; + + while (tempPtr != NULL) + { + if (tempPtr->status != SPI_TRANSFER_FAILED && tempPtr->status != SPI_TRANSFER_CSN_DEASSERT) + { + tempPtr->status = SPI_TRANSFER_CANCELED; + } + + tempPtr->count = 0; + tempPtr = tempPtr->nextPtr; + } + object->headPtr->count = temp; + + /* Add all cancelled transactions to object->completedTransfers */ + tempPtr = object->completedTransfers; + if (tempPtr == NULL) + { + /* Empty list; just add all of the cancelled transactions */ + object->completedTransfers = object->headPtr; + } + else + { + /* Move through the list until we reach the last element */ + while (tempPtr->nextPtr != NULL) + { + tempPtr = tempPtr->nextPtr; + } + + /* Add all of the cancelled transactions */ + tempPtr->nextPtr = object->headPtr; + } + + /* Clear all driver object variables*/ + object->headPtr = NULL; + object->tailPtr = NULL; + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + + HwiP_restore(key); + + /* + * All transactions have been marked as cancelled & added to + * object->completedTransfers. Post the driver SWI to execute + * callback functions. + */ + SwiP_post(&(object->swi)); + + /* Must return here; do not call HwiP_restore() twice */ + return; + } + + HwiP_restore(key); +} + +/* + * ======== finishTransfer ======== + * This function completes the current transfer + */ +static void finishTransfer(SPI_Handle handle) +{ + uint32_t xferSize; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Prevent interrupt while finishing the transfer */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* + * Disable the TX DMA channel first to stop feeding more frames to + * the FIFO. Next, wait until the TX FIFO is empty (all frames in + * FIFO have been sent). RX DMA channel is disabled later to allow + * the DMA to move all frames already in FIFO to memory. + */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->txChannelBitMask); + + if (object->mode == SPI_CONTROLLER) + { + /* + * Wait until the TX FIFO is empty; this is to make sure the + * chip select is deasserted before disabling the SPI. + */ + while (SSIBusy(hwAttrs->baseAddr)) {} + } + + SSIDisable(hwAttrs->baseAddr); + + /* Now disable the RX, DMA & interrupts */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelBitMask); + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR); + + /* + * Update transaction->count with the amount of frames which have + * been transferred. + */ + object->headPtr->count = object->framesTransferred; + if (object->priTransferSize) + { + xferSize = UDMACC26XX_GET_TRANSFER_SIZE(hwAttrs->dmaRxTableEntryPri->ui32Control); + + if (xferSize <= object->priTransferSize) + { + object->headPtr->count += (object->priTransferSize - xferSize); + } + } + + if (object->altTransferSize) + { + xferSize = UDMACC26XX_GET_TRANSFER_SIZE(hwAttrs->dmaRxTableEntryAlt->ui32Control); + + if (xferSize <= object->altTransferSize) + { + object->headPtr->count += (object->altTransferSize - xferSize); + } + } + + /* + * Disables peripheral, clears all registers & reinitializes it to + * parameters used in SPI_open() + */ + initHw(handle); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); +} + +/* + * ======== processCSNDeassert ======== + */ +static void processCSNDeassert(SPI_Handle handle) +{ + uintptr_t key; + SPI_Transaction *tempXfer; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Acquire exclusive access to the driver. Required to prevent race + * conditions if preempted by code trying to configure another transfer. + */ + key = HwiP_disable(); + + if (object->headPtr == NULL) + { + /* + * Disable the SPI peripheral in case the peripherals finite state + * machine is in a bad state. Calling SPI_transfer() will re-enable + * the peripheral. + */ + SSIDisable(hwAttrs->baseAddr); + HwiP_restore(key); + return; + } + + object->headPtr->status = SPI_TRANSFER_CSN_DEASSERT; + + finishTransfer(handle); + + if (object->completedTransfers == NULL) + { + /* Empty list; just add the completed transaction */ + object->completedTransfers = object->headPtr; + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Clear references in completed transfer */ + object->completedTransfers->nextPtr = NULL; + } + else + { + tempXfer = object->completedTransfers; + + /* Move through the list until we reach the last element */ + while (tempXfer->nextPtr != NULL) + { + tempXfer = tempXfer->nextPtr; + } + + /* Add completed transaction to the end of the list */ + tempXfer->nextPtr = object->headPtr; + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Make sure we are pointing to the end of the list */ + tempXfer = tempXfer->nextPtr; + + /* Clear references in completed transfer */ + tempXfer->nextPtr = NULL; + } + + /* Clear driver object DMA transaction tracking variables */ + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + + if (object->headPtr != NULL) + { + /* Reconfigure channel for next transaction */ + configNextTransfer(object, hwAttrs); + + object->activeChannel = UDMA_PRI_SELECT; + if (object->headPtr->count > MAX_DMA_TRANSFER_AMOUNT) + { + configNextTransfer(object, hwAttrs); + } + + /* Enable DMA to generate interrupt on SPI peripheral */ + if (!object->manualStart) + { + SSIEnable(hwAttrs->baseAddr); + } + } + else + { + object->tailPtr = NULL; + + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + + /* No more queued transfers; disable DMA & SPI */ + SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + + /* + * For this driver implementation the peripheral is kept + * active until either a FIFO-overrun occurs or + * SPI_transferCancel() is executed. + */ + } + + HwiP_restore(key); + + /* + * Post the driver SWI to execute callback functions. + */ + SwiP_post(&(object->swi)); + + /* Must return here; do not call HwiP_restore() twice */ + return; +} + +/* + * ======== blockingTransferCallback ======== + */ +static void blockingTransferCallback(SPI_Handle handle, SPI_Transaction *msg) +{ + SPICC26X2DMA_Object *object = handle->object; + + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== configNextTransfer ======== + * This function must be executed with interrupts disabled. + */ +static void configNextTransfer(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + size_t framesQueued; + uint32_t transferAmt; + SPI_Transaction *transaction; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + uint8_t optionsIndex; + + /* + * The DMA options vary according to data frame size; options for 8-bit + * data (or smaller) are in index 0. Options for larger frame sizes are + * in index 1. + * + * optionsIndex was originally calculated by: + * optionsIndex = (object->dataSize < 9) ? 0x00 : 0x01; + * + * However, the IAR compiler generated incorrect assembly: + * + * configNextTransfer: + * 0x5140: 0xe92d 0x41fc PUSH.W {R2-R8, LR} + * optionsIndex = (object->dataSize < 9) ? 0x00 : 0x01; + * 0x5144: 0xf100 0x0594 ADD.W R5, R0, #148 ; 0x94 + * 0x5148: 0x6aaa LDR R2, [R5, #0x28] + * 0x514a: 0x2a08 CMP R2, #8 + * 0x514c: 0x419b SBCS R3, R3, R3 + * 0x514e: 0x43db MVNS R3, R3 + * 0x5150: 0x0fdb LSRS R3, R3, #31 + * + * To work around this issue is calculated as follows: + */ + optionsIndex = ((int32_t)(object->dataSize - 0x08) > 0) ? 0x01 : 0x00; + + /* + * object->framesQueued keeps track of how many frames (of the current + * transaction) have been configured for DMA transfer. If + * object->framesQueued == transaction->count; all frames have been queued + * & we should configure the free DMA channel to send the next transaction. + * When the current transaction has completed; object->framesQueued + * will be updated (in the ISR) to reflect the amount of frames queued + * of the following transaction. + */ + transaction = object->headPtr; + if (object->framesQueued < transaction->count) + { + framesQueued = object->framesQueued; + } + else + { + transaction = object->headPtr->nextPtr; + if (transaction == NULL) + { + /* There are no queued transactions */ + return; + } + + framesQueued = 0; + transaction->status = (object->returnPartial != SPICC26X2DMA_retPartDisabled) ? SPI_TRANSFER_PEND_CSN_ASSERT + : SPI_TRANSFER_STARTED; + } + + /* + * The DMA has a max transfer amount of 1024. If the transaction is + * greater; we must transfer it in chunks. framesQueued keeps track of + * how much data has been queued for transfer. + */ + if ((transaction->count - framesQueued) > MAX_DMA_TRANSFER_AMOUNT) + { + transferAmt = MAX_DMA_TRANSFER_AMOUNT; + } + else + { + transferAmt = transaction->count - framesQueued; + } + + /* Determine free channel & mark it as used by setting transfer size */ + if (object->priTransferSize == 0) + { + object->priTransferSize = transferAmt; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryPri; + txDmaTableEntry = hwAttrs->dmaTxTableEntryPri; + } + else + { + object->altTransferSize = transferAmt; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryAlt; + txDmaTableEntry = hwAttrs->dmaTxTableEntryAlt; + } + + /* Setup the TX transfer buffers & characteristics */ + if (transaction->txBuf) + { + txDmaTableEntry->ui32Control = dmaTxConfig[optionsIndex]; + + /* + * Add an offset for the amount of data transferred. The offset is + * calculated by: object->framesQueued * (optionsIndex + 1). This + * accounts for 8 or 16-bit sized transfers. + */ + txDmaTableEntry->pvSrcEndAddr = (void *)((uint32_t)transaction->txBuf + + (uint32_t)(framesQueued * (optionsIndex + 1)) + + (transferAmt << optionsIndex) - 1); + } + else + { + txDmaTableEntry->ui32Control = dmaNullConfig[optionsIndex]; + txDmaTableEntry->pvSrcEndAddr = (void *)&(object->txScratchBuf); + } + txDmaTableEntry->pvDstEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR); + txDmaTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transferAmt); + + /* Setup the RX transfer buffers & characteristics */ + if (transaction->rxBuf) + { + rxDmaTableEntry->ui32Control = dmaRxConfig[optionsIndex]; + + /* + * Add an offset for the amount of data transferred. The offset is + * calculated by: object->framesQueued * (optionsIndex + 1). This + * accounts for 8 or 16-bit sized transfers. + */ + + rxDmaTableEntry->pvDstEndAddr = (void *)((uint32_t)transaction->rxBuf + + (uint32_t)(framesQueued * (optionsIndex + 1)) + + (transferAmt << optionsIndex) - 1); + } + else + { + rxDmaTableEntry->ui32Control = dmaNullConfig[optionsIndex]; + rxDmaTableEntry->pvDstEndAddr = &object->rxScratchBuf; + } + rxDmaTableEntry->pvSrcEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR); + rxDmaTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transferAmt); + + if (transaction == object->headPtr) + { + /* + * Only update object->framesQueued if we are configuring a DMA + * channel for the current transaction. + */ + object->framesQueued += transferAmt; + } + + if (!object->manualStart) + { + /* Enable DMA to generate interrupt on SPI peripheral */ + SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + } + + return; +} + +/* + * ======== csnCallback ======== + * Peripheral mode optional callback function for when the CSN is asserted & + * deasserted. + */ +static void csnCallback(uint_least8_t index) +{ + uintptr_t key; + SPI_Handle spiHandle = (SPI_Handle)GPIO_getUserArg(index); + SPICC26X2DMA_Object *object = spiHandle->object; + + if (!GPIO_read(index)) + { + /* Start transfer if CSN goes low */ + key = HwiP_disable(); + if (object->headPtr != NULL) + { + /* We have data ready; indicate transaction started */ + object->headPtr->status = SPI_TRANSFER_STARTED; + } + else + { + /* We are not waiting to transfer; disable all interrupts */ + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X2DMA_retPartEnabledIntNotSet; + } + HwiP_restore(key); + } + else + { + processCSNDeassert(spiHandle); + } +} + +/* + * ======== flushFifos ======== + */ +static void flushFifos(SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + /* Flush RX FIFO */ + while (HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_RX_NOT_EMPTY) + { + /* Read element from RX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_DR); + } + + /* Enable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_ENABLE; + + /* Flush TX FIFO */ + while (!(HWREG(hwAttrs->baseAddr + SSI_O_SR) & SSI_TX_EMPTY)) + { + /* Read element from TX FIFO and discard */ + HWREG(hwAttrs->baseAddr + SSI_O_TDR); + } + + /* Disable TESTFIFO mode */ + HWREG(hwAttrs->baseAddr + SSI_O_TCR) = SSI_TCR_TESTFIFO_DISABLE; +} + +/* + * ======== getDmaChannelNumber ======== + */ +static inline uint32_t getDmaChannelNumber(uint32_t x) +{ +#if defined(__TI_COMPILER_VERSION__) + return ((uint32_t)__clz(__rbit(x))); +#elif defined(__GNUC__) + return ((uint32_t)__builtin_ctz(x)); +#elif defined(__IAR_SYSTEMS_ICC__) + return ((uint32_t)__CLZ(__RBIT(x))); +#else + #error "Unsupported compiler" +#endif +} + +/* + * ======== initHw ======== + */ +static void initHw(SPI_Handle handle) +{ + ClockP_FreqHz freq; + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + flushFifos(hwAttrs); + + /* Disable SSI operation */ + SSIDisable(hwAttrs->baseAddr); + + /* Disable SPI module interrupts */ + SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); + SSIIntClear(hwAttrs->baseAddr, SSI_RXOR | SSI_RXTO); + + /* Set the SPI configuration */ + ClockP_getCpuFreq(&freq); + SSIConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->format, object->mode, object->bitRate, object->dataSize); +} + +/* + * ======== initIO ======== + * This functions initializes the SPI IOs. + * + * @pre Function assumes that the SPI handle is pointing to a hardware + * module which has already been opened. + */ +static void initIO(SPI_Handle handle) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + GPIO_setConfigAndMux(hwAttrs->clkPin, GPIO_CFG_INPUT, hwAttrs->clkPinMux); + GPIO_setConfigAndMux(object->csnPin, GPIO_CFG_INPUT, hwAttrs->csnPinMux); + + if (object->mode == SPI_PERIPHERAL) + { + GPIO_setConfigAndMux(hwAttrs->picoPin, GPIO_CFG_INPUT, hwAttrs->rxPinMux); + GPIO_setConfigAndMux(hwAttrs->pociPin, GPIO_CFG_NO_DIR, hwAttrs->txPinMux); + + GPIO_setCallback(object->csnPin, csnCallback); + GPIO_setUserArg(object->csnPin, handle); + } + else + { + GPIO_setConfigAndMux(hwAttrs->picoPin, GPIO_CFG_NO_DIR, hwAttrs->txPinMux); + GPIO_setConfigAndMux(hwAttrs->pociPin, GPIO_CFG_INPUT, hwAttrs->rxPinMux); + } +} + +/* + * ======== finalizeIO ======== + * This function releases the SPI IOs. + */ +static void finalizeIO(SPI_Handle handle) +{ + SPICC26X2DMA_Object *object = handle->object; + SPICC26X2DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + GPIO_resetConfig(hwAttrs->picoPin); + GPIO_resetConfig(hwAttrs->pociPin); + GPIO_resetConfig(hwAttrs->clkPin); + GPIO_resetConfig(object->csnPin); +} + +/* + * ======== primeTransfer ======== + * Function must be executed with interrupts disabled. + */ +static inline void primeTransfer(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + if (object->priTransferSize != 0 && object->altTransferSize != 0) + { + /* + * Both primary & alternate channels are configured for a transfer. + * In this case no work is required; the Hwi will configure channels + * as transfers continue & complete. + */ + } + else if (object->priTransferSize == 0 && object->altTransferSize == 0) + { + /* + * Primary & alternate channels are disabled; no active transfer, + * configure a new transfer. + * + * DMA based transfers use the DMA in ping-pong mode. If the transfer is + * larger than what the primary channel can handle; alternate channel is + * configured to continue where the primary channel left off. Channels + * are continuously reconfigured until the transfer is completed. + * + * We disable the alternate channel initially. This however causes an + * undesired interrupt to be triggered; so we need to + * disable/clear/re-enable the interrupt. + */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* Set the primary DMA structure as active */ + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->rxChannelBitMask), + UDMA_ATTR_ALTSELECT); + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->txChannelBitMask), + UDMA_ATTR_ALTSELECT); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); + + /* Configure RX & TX DMA transfers */ + configNextTransfer(object, hwAttrs); + object->activeChannel = UDMA_PRI_SELECT; + if (object->headPtr->count > MAX_DMA_TRANSFER_AMOUNT) + { + configNextTransfer(object, hwAttrs); + } + + /* Enable DMA to generate interrupt on SPI peripheral */ + if (!object->manualStart) + { + SSIEnable(hwAttrs->baseAddr); + } + } + else + { + /* One of the channels is active; configure the other channel */ + configNextTransfer(object, hwAttrs); + } +} + +/* + * ======== releaseConstraint ======== + */ +static inline void releaseConstraint(uint32_t txBufAddr) +{ + /* Release need flash if buffer was in flash. */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) + { + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + } + + /* Release standby constraint since operation is done. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== setConstraint ======== + */ +static inline void setConstraint(uint32_t txBufAddr) +{ + /* + * Ensure flash is available if TX buffer is in flash. + * Flash starts with 0x0.. + */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) + { + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== spiPollingTransfer ======== + */ +static inline void spiPollingTransfer(SPICC26X2DMA_Object *object, + SPICC26X2DMA_HWAttrs const *hwAttrs, + SPI_Transaction *transaction) +{ + uint8_t txIncrement, rxIncrement; + uint32_t dummyBuffer; + size_t rxCount, txCount; + void *rxBuf; + void *txBuf; + bool put; + + /* Only increment src/destination pointers if buffers were provided */ + if (transaction->rxBuf) + { + rxBuf = transaction->rxBuf; + rxIncrement = (object->dataSize < 9) ? sizeof(uint8_t) : sizeof(uint16_t); + } + else + { + rxBuf = &(object->rxScratchBuf); + rxIncrement = 0; + } + + if (transaction->txBuf) + { + txBuf = transaction->txBuf; + txIncrement = (object->dataSize < 9) ? sizeof(uint8_t) : sizeof(uint16_t); + } + else + { + txBuf = (void *)&(object->txScratchBuf); + txIncrement = 0; + } + + rxCount = transaction->count; + txCount = rxCount; + + SSIEnable(hwAttrs->baseAddr); + + /* Fill the TX FIFO as much as we can before reading */ + while (rxCount--) + { + if (object->dataSize < 9) + { + put = true; + while (txCount > 0 && put) + { + put = SSIDataPutNonBlocking(hwAttrs->baseAddr, *((uint8_t *)txBuf)); + if (put) + { + txBuf = (void *)(((uint32_t)txBuf) + txIncrement); + txCount--; + } + } + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint8_t *)rxBuf) = (uint8_t)dummyBuffer; + } + else + { + put = true; + while (txCount > 0 && put) + { + put = SSIDataPutNonBlocking(hwAttrs->baseAddr, *((uint16_t *)txBuf)); + if (put) + { + txBuf = (void *)(((uint32_t)txBuf) + txIncrement); + txCount--; + } + } + SSIDataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint16_t *)rxBuf) = (uint16_t)dummyBuffer; + } + + /* Update rxBuf position */ + rxBuf = (void *)(((uint32_t)rxBuf) + rxIncrement); + } + + while (spiBusy(object, hwAttrs)) {} + + /* + * For this driver implementation the peripheral is kept active until + * either a FIFO-overrun occurs or SPI_transferCancel() is executed. + * + * SSIDisable(hwAttrs->baseAddr); + */ +} + +/* + * ======== spiPostNotify ======== + */ +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + initHw((SPI_Handle)clientArg); + + return (Power_NOTIFYDONE); +} + +/* + * ======== spiBusy ======== + * HW is busy when in controller mode and BSY bit is set, or when in peripheral + * mode and TFE bit is not set. + */ +static inline bool spiBusy(SPICC26X2DMA_Object *object, SPICC26X2DMA_HWAttrs const *hwAttrs) +{ + bool registerBit = (bool)(HWREG(hwAttrs->baseAddr + SSI_O_SR) & (object->busyBit)); + if (object->busyBit == SSI_SR_BSY) + { + return (registerBit); + } + else + { + return (!registerBit); + } +} diff --git a/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.h b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.h new file mode 100644 index 00000000..d5af1f72 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X2DMA.h @@ -0,0 +1,1010 @@ +/* + * Copyright (c) 2015-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* clang-format off */ +/*!***************************************************************************** + * @file SPICC26X2DMA.h + * + * @brief SPI driver implementation for a CC26XX SPI controller using + * the UDMA controller. + * + * # Driver include # + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs. + * + * Note that the user also needs to include the UDMACC26XX.h driver since the + * SPI uses uDMA in order to improve throughput. + * + * # Overview # + * The general SPI API should be used in application code, i.e. SPI_open() + * should be used instead of SPICC26X2DMA_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES_SPI_X2). + * + * # General Behavior # + * Before using SPI on CC26XX: + * - The SPI driver is initialized by calling SPI_init(). + * - The SPI HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling SPI_open(). + * - The SPI driver makes use of DMA in order to optimize throughput. + * This is handled directly by the SPI driver, so the application should never + * to make any calls directly to the UDMACC26XX.h driver. + * - This implementation supports queueing multiple transactions in callback + * mode. See the @ref USE_CASE_QUEUE "queueing example." + * - When queueing multiple transactions that should transfer one after the + * other, it is recommended to use the driver in 'manual start' mode by using + * the #SPICC26X2DMA_CMD_SET_MANUAL command. In this mode, the driver will + * not start any queued transfers until SPI_control() is called with the + * #SPICC26X2DMA_CMD_MANUAL_START command. This mode is off by default and + * can be disabled by using command #SPICC26X2DMA_CMD_CLR_MANUAL. See the + * @ref USE_CASE_MANUAL_START "Manual Start Example". + * + * The following is true for peripheral operation: + * - RX overrun IRQ, SPI and UDMA modules are enabled by calling SPI_transfer(). + * - All received bytes are ignored after SPI_open() is called, until + * the first SPI_transfer(). + * - If an RX overrun occur or if SPI_transferCancel() is called, RX overrun IRQ, SPI and UDMA + * modules are disabled, TX and RX FIFOs are flushed and all bytes are ignored. + * - After a successful transfer, RX overrun IRQ and SPI module remains enabled and UDMA module is disabled. + * SPI_transfer() must be called again before RX FIFO goes full in order to + * avoid overflow. If the TX buffer is underflowed, zeros will be output. + * It is safe to call another SPI_transfer() from the transfer callback, + * see [Continuous Peripheral Transfer] (@ref USE_CASE_CST_X2) use case below. + * - The SPI driver supports partial return, that can be used if the + * transfer size is unknown. If #SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE is + * passed to SPI_control(), the transfer will end when chip select is + * deasserted. The #SPI_Transaction.status and the #SPI_Transaction.count + * will be updated to indicate whether the transfer ended due to a chip + * select deassertion and how many bytes were transferred. See + * [Peripheral Mode With Return Partial] (@ref USE_CASE_RP_X2) use case below. + * - When queueing several transactions if the first is a 'short' + * transaction (8 or fewer frames), it is required to use + * @ref USE_CASE_MANUAL_START "Manual Start mode." + * + * @warning The SPI modules on the CC13x0, CC26x0, and CC26x0R2 devices have a + * bug which may result in TX data being lost when operating in SPI peripheral + * mode. Please refer to the device errata sheet for full details. The SPI + * protocol should therefore include a data integrity check, such as + * appending a CRC to the payload to ensure all the data was transmitted + * correctly by the SPI peripheral. + * + * The following apply for controller operation: + * - SPI and UDMA modules are enabled by calling SPI_transfer(). + * - If the SPI_transfer() succeeds, SPI module is enabled and UDMA module is disabled. + * - If SPI_transferCancel() is called, SPI and UDMA modules are disabled and + * TX and RX FIFOs are flushed. + * . + * After SPI operation has ended: + * - Release system dependencies for SPI by calling SPI_close(). + * . + * The callback function is always called in a SWI context. + * + * @warning The application should avoid transmitting data stored in flash via SPI if the application + * might switch to the XOSC_HF, the high frequency external oscillator, during this transfer. + * + * # Error handling # + * If an RX overrun occurs during peripheral operation: + * - If a transfer is ongoing, all bytes received up until the error occurs will be returned, with the + * error signaled in the #SPI_Transaction.status field. RX overrun IRQ, SPI and UDMA modules are then disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * - If a transfer is not ongoing, RX overrun IRQ, SPI and UDMA modules are disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * + * # Timeout # + * Timeout can occur in #SPI_MODE_BLOCKING, there's no timeout in #SPI_MODE_CALLBACK. + * When in #SPI_MODE_CALLBACK, the transfer must be cancelled by calling SPI_transferCancel().@n + * If a timeout happens in either #SPI_PERIPHERAL or #SPI_CONTROLLER mode, + * the receive buffer will contain the bytes received up until the timeout occurred. + * The SPI transaction status will be set to #SPI_TRANSFER_FAILED. + * The SPI transaction count will be set to the number of bytes sent/received before timeout. + * The remaining bytes will be flushed from the TX FIFO so that the subsequent transfer + * can be executed correctly. Note that specifying a timeout prevents the + * driver from performing a polling transfer when in peripheral mode. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The SPICC26X2DMA.h driver is setting a power constraint during transfers to keep + * the device out of standby. When the transfer has finished, the power + * constraint is released. + * The following statements are valid: + * - After SPI_open(): the device is still allowed to enter standby. + * - In peripheral mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After an RX overflow: device is allowed to enter standby. + * - After a successful SPI_transfer(): the device is allowed + * to enter standby, but SPI module remains enabled. + * - _Note_: In peripheral mode, the device might enter standby while a byte is being + * transferred if SPI_transfer() is not called again after a successful + * transfer. This could result in corrupt data being transferred. + * - Application thread should typically either issue another transfer after + * SPI_transfer() completes successfully, or call + * SPI_transferCancel() to disable the SPI module and thus assuring that no data + * is received while entering standby. + * . + * - In controller mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After SPI_transfer() succeeds: the device can enter standby. + * - If SPI_transferCancel() is called: the device can enter standby. + * + * @note The external hardware connected to the SPI might have some pull configured on the + * SPI lines. When the SPI is inactive, this might cause leakage on the IO and the + * current consumption to increase. The application must configure a pull configuration + * that aligns with the external hardware. + * See [Ensure low power during inactive periods] (@ref USE_CASE_LPWR_X2) for code example. + * + * # SPI details # + * ## Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_CONTROLLER modeSPI_PERIPHERAL mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI peripheral is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ### Multiple peripherals when operating in controller mode # + * In a scenario where the SPI module is operating in controller mode with multiple + * SPI peripherals, the chip select pin can be reallocated at runtime to select the + * appropriate peripheral device. See [Controller Mode With Multiple Peripherals](@ref USE_CASE_MMMS_X2) use case below. + * This is only relevant when chip select is a hardware chip select. Otherwise the application + * can control the chip select pins directly using the GPIO driver. + * + * ## Data Frames # + * + * SPI data frames can be any size from 4-bits to 16-bits. If the dataSize in + * #SPI_Params is greater that 8-bits, then the SPICC26X2DMA driver + * implementation will assume that the #SPI_Transaction txBuf and rxBuf + * point to an array of 16-bit uint16_t elements. + * + * dataSize | buffer element size | + * -------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * + * ## Bit Rate ## + * Maximum bit rate is 4MHz for both peripheral and controller modes. + * + * + * ## UDMA # + * ### Interrupts # + * The UDMA module generates IRQs on the SPI interrupt vector. This driver automatically + * installs a UDMA aware Hwi (interrupt) to service the assigned UDMA channels. + * + * ### Transfer Size Limit # + * + * The UDMA controller only supports data transfers of up to 1024 data frames. + * A transfer with more than 1024 frames will be transmitted/received in + * multiple 1024 sized portions until all data has been transmitted/received. + * A data frame can be 4 to 16 bits in length. + * + * ### Scratch Buffers # + * A uint16_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf + * are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size + * of the transfer count, a single-word UDMA accessible uint16_t scratch buffer is used. + * When rxBuf is NULL, the UDMA will transfer all the received SPI data into the + * scratch buffer as a "bit-bucket". + * When txBuf is NULL, the scratch buffer is initialized to defaultTxBufValue + * so the uDMA will send some known value. + * Each SPI driver instance uses its own scratch buffer. + * + * ### TX and RX buffers # + * Before SPI_transfer, txBuf should be filled with the outgoing SPI data. These + * data are sent out during the transfer, while the incoming data are received + * into rxBuf. To save memory space, txBuf and rxBuf can be assigned to the same + * buffer location. At the beginning of the transfer, this buffer holds outgoing + * data. At the end of the transfer, the outgoing data are overwritten and + * the buffer holds the received SPI data. + * + * ## Polling SPI transfers # + * When used in blocking mode small SPI transfers are can be done by polling + * the peripheral & sending data frame-by-frame. A controller device can perform + * the transfer immediately and return, but a peripheral will block until it + * receives the number of frames specified in the SPI_Transfer() call. + * The minDmaTransferSize field in the hardware attributes is + * the threshold; if the transaction count is below the threshold a polling + * transfer is performed; otherwise a DMA transfer is done. This is intended + * to reduce the overhead of setting up a DMA transfer to only send a few + * data frames. + * + * Notes: + * - Specifying a timeout prevents peripheral devices from using polling transfers. + * - Keep in mind that during polling transfers the current task + * is still being executed; there is no context switch to another task. + * + * # Supported Functions # + * Generic API function | API function | Description + * ----------------------|------------------------------- |------------------------------------------------------------- + * SPI_init() | SPICC26X2DMA_init() | Initialize SPI driver + * SPI_open() | SPICC26X2DMA_open() | Initialize SPI HW and set system dependencies + * SPI_close() | SPICC26X2DMA_close() | Disable SPI and UDMA HW and release system dependencies + * SPI_control() | SPICC26X2DMA_control() | Configure an already opened SPI handle + * SPI_transfer() | SPICC26X2DMA_transfer() | Start transfer from SPI + * SPI_transferCancel() | SPICC26X2DMA_transferCancel() | Cancel ongoing transfer from SPI + * + * @note All calls should go through the generic API + * + * ## Use Cases @anchor USE_CASES_SPI_X2 ## + * ### Basic Peripheral Mode # + * Receive 100 bytes over SPI in #SPI_MODE_BLOCKING. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Peripheral Mode With Return Partial @anchor USE_CASE_RP_X2 # + * This use case will perform a transfer in #SPI_MODE_BLOCKING until the wanted + * amount of bytes is transferred or until chip select is deasserted by the SPI + * controller. + * This SPI_transfer() call can be used when unknown amount of bytes shall + * be transferred. + *
Note: Partial return is also possible in #SPI_MODE_CALLBACK mode. + * In callback mode, partial transfers can be queued by calling SPI_transfer() + * multiple times. + *
Note: Polling transfers are not available when using return partial mode. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and initiate the partial read + * handle = SPI_open(CONFIG_SPI, ¶ms); + * + * // Enable RETURN_PARTIAL + * SPI_control(handle, SPICC26X2DMA_RETURN_PARTIAL_ENABLE, NULL); + * + * // Begin transfer + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Continuous Peripheral Transfer In #SPI_MODE_CALLBACK @anchor USE_CASE_CST_X2 # + * This use case will configure the SPI driver to transfer continuously in + * #SPI_MODE_CALLBACK, 16 bytes at the time and echoing received data after every + * 16 bytes. + * @code + * // Callback function + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Start another transfer + * SPI_transfer(handle, transaction); + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t buf[16]; // Receive and transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * params.transferMode = SPI_MODE_CALLBACK; + * params.transferCallbackFxn = transferCallback; + * + * // Configure the transaction + * transaction.count = 16; + * transaction.txBuf = buf; + * transaction.rxBuf = buf; + * + * // Open the SPI and initiate the first transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Wait forever + * while(true); + * } + * @endcode + * + * ### Basic Controller Mode # + * This use case will configure a SPI controller to send the data in txBuf while receiving data to rxBuf in + * BLOCKING_MODE. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * uint8_t rxBuf[11]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_CONTROLLER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Controller Mode With Multiple Peripherals @anchor USE_CASE_MMMS_X2 # + * This use case will configure a SPI controller to send data to one peripheral and then to another in + * BLOCKING_MODE. It is assumed that the board file is configured so that the two chip select + * pins have a default setting of a high output and that the #SPICC26X2DMA_HWAttrs used points + * to one of them since the SPI driver will revert to this default setting when switching the + * chip select pin. + * + * @code + * // From ti_drivers_config.c + * // Use the sysconfig settings to make sure both pins are set to HIGH when not in use + * GPIO_PinConfig gpioPinConfigs[31] = { + * ... + * GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH, // CONFIG_CSN_0 + * ... + * GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH, // CONFIG_CSN_1 + * } + * + * const SPICC26X2DMA_HWAttrs SPICC26X2DMAHWAttrs[CC2650_SPICOUNT] = { + * { // Use SPI0 module with default chip select on CONFIG_CSN_0 + * .baseAddr = SSI0_BASE, + * .intNum = INT_SSI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .defaultTxBufValue = 0, + * .powerMngrId = PERIPH_SSI0, + * .rxChannelIndex = UDMA_CHAN_SSI0_RX, + * .txChannelIndex = UDMA_CHAN_SSI0_TX, + * .picoPin = CONFIG_SPI0_PICO, + * .pociPin = CONFIG_SPI0_POCI, + * .clkPin = CONFIG_SPI0_CLK, + * .csnPin = CONFIG_CSN_0 + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint_least8_t csnPin1 = CONFIG_CSN_1; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_CONTROLLER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = NULL; + * + * // Open the SPI and perform transfer to the first peripheral + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Then switch chip select pin and perform transfer to the second peripheral + * SPI_control(handle, SPICC26X2DMA_SET_CSN_PIN, &csnPin1); + * SPI_transfer(handle, &transaction); + * } + * @endcode + * + * ### Queueing Transactions in Callback Mode # + * @anchor USE_CASE_QUEUE + * Below is an example of queueing three transactions + * @code + * // SPI already opened in callback mode + * SPI_Transaction t0, t1, t2; + * + * t0.txBuf = txBuff0; + * t0.rxBuf = rxBuff0; + * t0.count = 2000; + * + * t1.txBuf = txBuff1; + * t1.rxBuf = rxBuff1; + * t1.count = 1000; + * + * t2.txBuf = txBuff2; + * t2.rxBuf = NULL; + * t2.count = 1000; + * + * bool transferOk = false; + * + * if (SPI_transfer(spiHandle, &t0)) { + * if (SPI_transfer(spiHandle, &t1)) { + * transferOk = SPI_transfer(spiHandle, &t2); + * } + * } + * } + * @endcode + * + * ### Queueing in Manual Start Mode# + * This example shows a peripheral device queueing two transactions that will + * complete one after the other. From the controller's perspective there will be + * one long transfer. + * @note Manual mode also works while the device is in #SPI_CONTROLLER mode. The + * control call to MANUAL_START will start the transfers. + * + * @warning Manual start mode should not be enabled or disabled while a + * transaction is in progress. + * + * @anchor USE_CASE_MANUAL_START + * @code + * SPI_Handle spi; + * SPI_Params params; + * SPI_Transaction t0, t1; + * uint8_t status = SPI_STATUS_SUCCESS; + * + * SPI_Params_init(¶ms); + * params.mode = SPI_PERIPHERAL; + * spi = SPI_open(CONFIG_SPI, ¶ms); + * + * if (spi == NULL) { + * exit(0); + * } + * + * // Enable manual start mode + * SPI_control(spi, SPICC26X2DMA_CMD_SET_MANUAL, NULL); + * + * // Queue transactions + * t0.txBuf = txBuff0; + * t0.rxBuf = rxBuff0; + * t0.count = 2000; + * if (!SPI_transfer(spi, &t0)) { + * status = SPI_STATUS_FAIL; + * } + * + * t1.txBuf = txBuff1; + * t1.rxBuf = rxBuff1; + * t1.count = 1000; + * if (!SPI_transfer(spi, &t1)) { + * status = SPI_STATUS_FAIL; + * } + * + * // Enable the transfers + * if (status == SPI_STATUS_SUCCESS) { + * SPI_control(spi, SPICC26X2DMA_CMD_MANUAL_START, NULL); + * } + * else { + * status = SPI_STATUS_FAILURE; + * } + * + * // At this point the peripheral is ready for the controller to start the transfer + * // Assume the callback implementation (not shown) posts a semaphore when + * // the last transaction completes + * sem_wait(&spiSemaphore); + * + * // Disable manual start mode + * SPI_control(spi, SPICC26X2DMA_CMD_CLR_MANUAL, NULL); + * + * @endcode + * + * ### Ensure low power during inactive periods @anchor USE_CASE_LPWR_X2 # + * External hardware connected on the SPI, i.e. SPI host/peripheral, might have configured + * a pull on one or more of the SPI lines. Dependent on the hardware, it might conflict + * with the pull used for the CC26XX SPI. To avoid increased leakage and ensure the lowest + * possible power consumption when the SPI is inactive, the application must configure a + * matching pull on the SPI IOs. An example of how this can be done is shown below. + * + * @code + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Heartbeat"; // Transmit buffer + * uint8_t rxBuf[9]; // Receive buffer + * uint32_t standbyDurationMs = 100; + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_CONTROLLER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(CONFIG_SPI_0, ¶ms); + * + * // Apply low power sleep pull config for POCI + * GPIO_setConfig(CONFIG_GPIO_SPI_0_POCI, GPIO_CFG_IN_PU); + * + * // Do forever + * while(1) { + * // Transfer data + * SPI_transfer(handle, &transaction); + * // Sleep + * Task_sleep(standbyDurationMs*100); + * } + * @endcode + * + * ### Wake Up On Chip Select Deassertion In Peripheral Mode Using #SPI_MODE_CALLBACK # + * This example demonstrates using a GPIO callback on Chip Select to wake up the device + * to allow low power modes while waiting for a chip select edge. + * + * In sysconfig or the board file, the CSN GPIO should be configured + * as input/pull up with an interrupt on falling edge. Otherwise, SPI_close() + * will reset the pin to the wrong settings and you may see line glitches. + * + * *Note: The SPI controller must allow enough time between deasserting the chip select and the + * start of the transaction for the SPI peripheral to wake up and open up the SPI driver. + * + * @code + * // Global variables + * SPI_Handle spiHandle + * SPI_Params spiParams; + * SPI_Transaction spiTransaction; + * const uint8_t transferSize = 8; + * uint8_t txBuf[8]; + * + * // Chip select callback + * static void chipSelectCallback(uint_least8_t) + * { + * // Open SPI driver, which will override any previous GPIO configuration + * spiHandle = SPI_open(CONFIG_SPI, &spiParams); + * // Issue the transfer + * SPI_transfer(spiHandle, &spiTransaction); + * } + * + * // SPI transfer callback + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Close the SPI driver + * SPI_close(handle); + * + * // Note: SPI_close() will reset the pin configuration, so it is important to + * // set the default values correctly in sysconfig. We just need to set the + * // callback and enable the falling edge interrupt + * + * GPIO_setCallback(CS_PIN_INDEX, chipSelectCallback); + * GPIO_enableInt(CS_PIN_INDEX); + * } + * + * // From your_application.c + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * uint8_t i; + * + * // Setup SPI params + * SPI_Params_init(&spiParams); + * spiParams.bitRate = 1000000; + * spiParams.frameFormat = SPI_POL1_PHA1; + * spiParams.mode = SPI_PERIPHERAL; + * spiParams.dataSize = transferSize; + * spiParams.transferMode = SPI_MODE_CALLBACK; + * spiParams.transferCallbackFxn = transferCallback; + * + * // Setup SPI transaction + * spiTransaction.arg = NULL; + * spiTransaction.count = transferSize; + * spiTransaction.txBuf = txBuf; + * spiTransaction.rxBuf = txBuf; + * + * // First echo message + * for (i = 0; i < transferSize; i++) { + * txBuf[i] = i; + * } + * + * // Configure chip select callback + * GPIO_setCallback(CS_PIN_INDEX, chipSelectCallback); + * GPIO_enableInt(CS_PIN_INDEX); + * + * // Wait forever + * while(true); + * } + * @endcode + * + *
+ */ +/* clang-format on */ +#ifndef ti_drivers_spi_SPICC26X2DMA__include +#define ti_drivers_spi_SPICC26X2DMA__include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup SPI_STATUS + * SPICC26X2DMA_STATUS_* macros are command codes only defined in the + * SPICC26X2DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC26X2DMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC26X2DMA_CMD_* macros are command codes only defined in the + * SPICC26X2DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by SPI_control() to enable partial return + * + * Enabling this command allows SPI_transfer to return partial data if the + * controller de-asserts the CS line before the expected number of frames were + * received. This command @b arg is of type @a don't @a care and it returns + * SPI_STATUS_SUCCESS or SPI_STATUS_ERROR. + */ +#define SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) + +/*! + * @brief Command used by SPI_control() to disable partial return + * + * Disabling this command returns the SPICC26X2DMA to the default blocking + * behavior where SPI_transfer() blocks until all data bytes were received. With + * this command @b arg is @a don't @a care and it returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE (SPI_CMD_RESERVED + 1) + +/*! + * @brief Command used by SPI_control() to re-configure chip select pin + * + * Enables hardware control of the chip select pin @b arg should be a + * @c uint_least8_t indicating the device DIO to be used as the hardware CS pin. + * + * Passing GPIO_INVALID_INDEX or PIN_UNASSIGNED to this command is equivalent to + * calling #SPICC26X2DMA_CMD_CLEAR_CSN_PIN. + * + * Always returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X2DMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) + +/*! + * @brief Command used by SPI_control() to disable the hardware chip select pin + * + * @b arg should be NULL. This command will disable all hardware control and + * muxing of the csnPin. It can then be controlled by user software using the + * GPIO driver, or configured later using #SPICC26X2DMA_CMD_SET_CSN_PIN. + * + * Always returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X2DMA_CMD_CLEAR_CSN_PIN (SPI_CMD_RESERVED + 3) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * Manual start mode can only be used when in callback mode. In manual start + * mode, calls to SPI_transfer() queue the transaction but does not start the + * transfer until another control call is made with + * #SPICC26X2DMA_CMD_MANUAL_START. This allows multiple transactions to be + * queued and executed seamlessly using the DMA's ping pong mechanism. This + * mode is MANDATORY for peripherals queueing multiple short transactions. Manual + * start mode can only be enabled or disabled when no transactions are queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X2DMA_CMD_SET_MANUAL (SPI_CMD_RESERVED + 4) + +/*! + * @brief Command used by SPI_control() to disable manual start mode + * + * Manual start mode is disabled by default. Enabling and disabling manual mode + * can only be done if no transactions are currently queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + * + */ +#define SPICC26X2DMA_CMD_CLR_MANUAL (SPI_CMD_RESERVED + 5) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * This command is used with manual start mode enabled. If transactions have + * been queued and the driver is in manual mode, this command will enable the + * SSI and DMA. For controller devices, the transfer will start. For peripheral + * devices, the transfer will start when the controller initiates. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X2DMA_CMD_MANUAL_START (SPI_CMD_RESERVED + 6) + +/** @}*/ + +/* BACKWARDS COMPATIBILITY */ +#define SPICC26X2DMA_RETURN_PARTIAL_ENABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26X2DMA_RETURN_PARTIAL_DISABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26X2DMA_SET_CSN_PIN SPICC26X2DMA_CMD_SET_CSN_PIN +/* END BACKWARDS COMPATIBILITY */ + +/*! + * @internal + * @brief + * SPI function table pointer + */ +extern const SPI_FxnTable SPICC26X2DMA_fxnTable; + +/*! + * @internal + * @brief + * SPICC26X2DMA data frame size is used to determine how to configure the + * UDMA data transfers. This field is to be only used internally. + * + * - SPICC26X2DMA_8bit: txBuf and rxBuf are arrays of uint8_t elements + * - SPICC26X2DMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + */ +typedef enum +{ + SPICC26X2DMA_8bit = 0, + SPICC26X2DMA_16bit = 1 +} SPICC26X2DMA_FrameSize; + +/*! + * @internal + * @brief + * SPICC26X2DMA return partial field indicates the status of the return + * partial mode and the associated pin interrupt. This field is for internal + * use only. + */ +typedef enum +{ + SPICC26X2DMA_retPartDisabled = 0, + SPICC26X2DMA_retPartEnabledIntNotSet = 1, + SPICC26X2DMA_retPartEnabledIntSet = 2 +} SPICC26X2DMA_ReturnPartial; + +/*! + * @brief SPICC26X2DMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26xxWare these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/udma.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const SPICC26X2DMA_HWAttrs SPICC26X2DMAobjects[] = { + * { + * .baseAddr = SSI0_BASE, + * .intNum = INT_SPI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI0, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI0_RX, + * .txChannelBitMask = UDMA_CHAN_SPI0_TX, + * .picoPin = CONFIG_SPI0_POCI, + * .pociPin = CONFIG_SPI0_PICO, + * .clkPin = CONFIG_SPI0_CLK, + * .csnPin = CONFIG_SPI0_CSN + * }, + * { + * .baseAddr = SSI1_BASE, + * .intNum = INT_SPI1, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI1, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI1_RX, + * .txChannelBitMask = UDMA_CHAN_SPI1_TX, + * .picoPin = CONFIG_SPI1_POCI, + * .pociPin = CONFIG_SPI1_PICO, + * .clkPin = CONFIG_SPI1_CLK, + * .csnPin = CONFIG_SPI1_CSN + * }, + * }; + * @endcode + */ +typedef struct +{ + /*! @brief SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26XXDMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! uDMA controlTable primary tx entry */ + volatile tDMAControlTable *dmaTxTableEntryPri; + /*! uDMA controlTable primary tx entry */ + volatile tDMAControlTable *dmaRxTableEntryPri; + /*! uDMA controlTable alternate tx entry */ + volatile tDMAControlTable *dmaTxTableEntryAlt; + /*! uDMA controlTable alternate rx entry */ + volatile tDMAControlTable *dmaRxTableEntryAlt; + /*! Tx PIN mux value. Can be applied to either PICO or POCI */ + int32_t txPinMux; + /*! Rx PIN mux value. Can be applied to either PICO or POCI */ + int32_t rxPinMux; + /*! CLK PIN mux value for flow control */ + int32_t clkPinMux; + /*! CSN PIN mux value for flow control */ + int32_t csnPinMux; + /*! SPI PICO pin */ + uint_least8_t picoPin; + /*! SPI POCI pin */ + uint_least8_t pociPin; + /*! SPI CLK pin */ + uint_least8_t clkPin; + /*! SPI CSN pin */ + uint_least8_t csnPin; + + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; +} SPICC26X2DMA_HWAttrs; + +/*! + * @brief SPICC26X2DMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + HwiP_Struct hwi; + Power_NotifyObj spiPostObj; + SwiP_Struct swi; + SemaphoreP_Struct transferComplete; + + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction *headPtr; + SPI_Transaction *tailPtr; + SPI_Transaction *completedTransfers; + UDMACC26XX_Handle udmaHandle; + + size_t framesQueued; + size_t framesTransferred; + size_t priTransferSize; + size_t altTransferSize; + + uint32_t activeChannel; + uint32_t bitRate; + uint32_t dataSize; + uint32_t transferTimeout; + uint32_t busyBit; + + uint16_t rxScratchBuf; + uint16_t txScratchBuf; + + SPI_TransferMode transferMode; + SPI_Mode mode; + uint8_t format; + uint_least8_t csnPin; + SPICC26X2DMA_ReturnPartial returnPartial; + bool isOpen; + bool manualStart; +} SPICC26X2DMA_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC26X2DMA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.c b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.c new file mode 100644 index 00000000..261cf2a7 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.c @@ -0,0 +1,1946 @@ +/* + * Copyright (c) 2021-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_spi.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/prcm.h) +#include DeviceFamily_constructPath(driverlib/rom.h) + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Headers required for intrinsics */ +#if defined(__TI_COMPILER_VERSION__) + #include +#elif defined(__GNUC__) + #include +#elif defined(__IAR_SYSTEMS_ICC__) + #include +#else + #error "Unsupported compiler" +#endif + +#define MAX_DMA_TRANSFER_AMOUNT (1024) + +#define SPI_DATASIZE_4 (4) +#define SPI_DATASIZE_8 (8) +#define SPI_DATASIZE_16 (16) +#define SPI_DATASIZE_32 (32) +#define PARAMS_DATASIZE_MIN SPI_DATASIZE_4 +#define PARAMS_DATASIZE_MAX SPI_DATASIZE_32 + +/* API Function Prototypes */ +void SPICC26X4DMA_close(SPI_Handle handle); +int_fast16_t SPICC26X4DMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg); +void SPICC26X4DMA_init(SPI_Handle handle); +SPI_Handle SPICC26X4DMA_open(SPI_Handle handle, SPI_Params *params); +static void SPICC26X4DMA_swiFxn(uintptr_t arg0, uintptr_t arg1); +bool SPICC26X4DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); +void SPICC26X4DMA_transferCancel(SPI_Handle handle); + +/* Local Function Prototypes */ +static void blockingTransferCallback(SPI_Handle handle, SPI_Transaction *msg); +static void configNextTransfer(SPICC26X4DMA_Object *object, SPICC26X4DMA_HWAttrs const *hwAttrs); +static void csnCallback(uint_least8_t); +static void flushFifos(SPICC26X4DMA_HWAttrs const *hwAttrs); +static inline uint32_t getDmaChannelNumber(uint32_t x); +static bool initHw(SPI_Handle handle); +static void initIO(SPI_Handle handle); +static void finalizeIO(SPI_Handle handle); +static inline void primeTransfer(SPI_Handle handle); +static inline void releaseConstraint(uint32_t txBufAddr); +static inline void setConstraint(uint32_t txBufAddr); +static inline void spiPollingTransfer(SPI_Handle handle, SPI_Transaction *transaction); +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +static inline bool spiBusy(SPICC26X4DMA_Object *object, SPICC26X4DMA_HWAttrs const *hwAttrs); +static inline void disableSPI(uint32_t baseAddr); +static inline void enableSPIAndMux(SPI_Handle handle); +static inline bool isSPIEnabled(SPI_Handle handle); +static inline void enableInterrupt(uint32_t baseAddr, uint32_t irqs); +static inline void disableInterrupt(uint32_t baseAddr, uint32_t irqs); +static inline void clearInterrupt(uint32_t baseAddr, uint32_t irqs); +static void enableDMA(uint32_t baseAddr, uint32_t dmaFlags); +static void disableDMA(uint32_t baseAddr, uint32_t dmaFlags); +static inline uint32_t getInterruptStatus(uint32_t baseAddr, bool masked); +static bool configSPI(uint32_t baseAddr, + uint32_t freq, + uint32_t format, + uint32_t mode, + uint32_t bitRate, + uint32_t dataSize, + uint32_t dsample); +static int32_t dataPutNonBlocking(uint32_t baseAddr, uint32_t frame); +static void dataGet(uint32_t baseAddr, uint32_t *frame); +static bool isSPIbusy(uint32_t baseAddr); +static void finishTransfer(SPI_Handle handle); +static void processCSNDeassert(SPI_Handle handle); + +/* RX FIFO over flowed, data was lost */ +#define SPI_INT_RXOF (SPI_MIS_RXFIFO_OVF_SET) +/* RX FIFO trigger level was passed */ +#define SPI_INT_RXFF (SPI_MIS_RX_SET) +/* TX FIFO trigger level was passed */ +#define SPI_INT_TXFF (SPI_MIS_TX_SET) +/* Transfer complete, HW is idle */ +#define SPI_INT_IDLE (SPI_MIS_IDLE_SET) +/* Subset of SPI interrupts used by this driver */ +#define SPI_INT_SUBSET (SPI_INT_TXFF | SPI_INT_RXFF | SPI_INT_RXOF | SPI_INT_IDLE) +/* All SPI interrupts */ +#define SPI_INT_ALL \ + (SPI_INT_SUBSET | SPI_MIS_TXEMPTY_SET | SPI_MIS_PER_SET | SPI_MIS_RTOUT_SET | SPI_MIS_DMA_DONE_RX_SET | \ + SPI_MIS_DMA_DONE_TX_SET) + +/* DSAMPLE default value limits based bit rate */ +#define DSAMPLE_MED_BITRATE 4000000 +#define DSAMPLE_HIGH_BITRATE 8000000 + +/* SPI function table for SPICC26X4DMA implementation */ +const SPI_FxnTable SPICC26X4DMA_fxnTable = {SPICC26X4DMA_close, + SPICC26X4DMA_control, + SPICC26X4DMA_init, + SPICC26X4DMA_open, + SPICC26X4DMA_transfer, + SPICC26X4DMA_transferCancel}; + +/* Mapping SPI mode from generic driver to CC26X4 */ +static const uint32_t mode[] = { + /* SPI_CONTROLLER */ + SPI_CTL1_MS_ENABLE, + /* SPI_PERIPHERAL */ + SPI_CTL1_MS_DISABLE, +}; + +/* Mapping SPI frame format from generic driver to CC26XX driverlib */ +static const uint32_t frameFormat[] = { + /* SPI_POL0_PHA0 */ + (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_LOW | SPI_CTL0_SPH_FIRST), + /* SPI_POL0_PHA1 */ + (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_LOW | SPI_CTL0_SPH_SECOND), + /* SPI_POL1_PHA0 */ + (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_HIGH | SPI_CTL0_SPH_FIRST), + /* SPI_POL1_PHA1 */ + (SPI_CTL0_FRF_MOTOROLA_3WIRE | SPI_CTL0_SPO_HIGH | SPI_CTL0_SPH_SECOND), + /* SPI_TI */ + (SPI_CTL0_FRF_TI_SYNC), + /* SPI_MW */ + (SPI_CTL0_FRF_MIRCOWIRE), +}; + +/* + * These lookup tables are used to configure the DMA channels for the + * appropriate (8bit/16bit/32bit) transfer sizes. + */ +static const uint32_t dmaTxConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | + UDMA_ARB_4}; + +static const uint32_t dmaRxConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | + UDMA_ARB_4}; + +static const uint32_t dmaNullConfig[] = {UDMA_MODE_PINGPONG | UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4, + UDMA_MODE_PINGPONG | UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | + UDMA_ARB_4}; + +/* + * ======== SPICC26X4DMA_close ======== + */ +void SPICC26X4DMA_close(SPI_Handle handle) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Disable the SPI */ + disableSPI(hwAttrs->baseAddr); + + HwiP_destruct(&(object->hwi)); + + UDMACC26XX_close(object->udmaHandle); + + SwiP_destruct(&(object->swi)); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + SemaphoreP_destruct(&(object->transferComplete)); + } + + finalizeIO(handle); + + Power_releaseDependency(hwAttrs->powerMngrId); + + Power_unregisterNotify(&object->spiPostObj); + + object->isOpen = false; +} + +/*! + * ======== SPICC26X4DMA_control ======== + * @brief Function for setting control parameters of the SPI driver + * after it has been opened. + * + * @pre SPICC26X4DMA_open() has to be called first. + * Calling context: Hwi, Swi, Task + * + * @param handle A SPI handle returned from SPICC26X4DMA_open() + * + * @param cmd The command to execute, supported commands are: + * | Command | Description | + * |-------------------------------------------|------------------------------| + * | ::SPICC26X4DMA_CMD_RETURN_PARTIAL_ENABLE | Enable RETURN_PARTIAL | + * | ::SPICC26X4DMA_CMD_RETURN_PARTIAL_DISABLE | Disable RETURN_PARTIAL | + * | ::SPICC26X4DMA_CMD_SET_CSN_PIN | Re-configure chip select pin | + * | ::SPICC26X4DMA_CMD_SET_MANUAL | Enable manual start mode | + * | ::SPICC26X4DMA_CMD_CLR_MANUAL | Disable manual start mode | + * | ::SPICC26X4DMA_CMD_MANUAL_START | Perform a manual start | + * | ::SPICC26X4DMA_CMD_SET_SAMPLE_DELAY | Set a custom DSAMPLE value | + * + * @param *arg Pointer to command arguments. + * + * @return ::SPI_STATUS_SUCCESS if success, or error code if error. + */ +int_fast16_t SPICC26X4DMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + uint_least8_t pinIndex; + uint_least8_t sampleDelay; + + /* Initialize return value */ + int ret = SPI_STATUS_ERROR; + + /* Perform command */ + switch (cmd) + { + case SPICC26X4DMA_CMD_RETURN_PARTIAL_ENABLE: + /* Enable RETURN_PARTIAL if peripheral mode is enabled */ + + if (object->mode == SPI_PERIPHERAL) + { + object->returnPartial = SPICC26X4DMA_retPartEnabledIntNotSet; + ret = SPI_STATUS_SUCCESS; + } + else + { + /* Partial return not available in controller mode. */ + ret = SPI_STATUS_ERROR; + } + break; + + case SPICC26X4DMA_CMD_RETURN_PARTIAL_DISABLE: + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X4DMA_retPartDisabled; + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X4DMA_CMD_SET_CSN_PIN: + pinIndex = *((uint_least8_t *)arg); + + if (pinIndex == GPIO_INVALID_INDEX) + { + /* If trying to disable the CS pin, forward to the CLEAR_CSN command and break */ + ret = SPICC26X4DMA_control(handle, SPICC26X4DMA_CMD_CLEAR_CSN_PIN, NULL); + break; + } + + /* Reset the previous CS pin and configure the new one */ + GPIO_resetConfig(object->csnPin); + object->csnPin = pinIndex; + GPIO_setConfigAndMux(object->csnPin, GPIO_CFG_INPUT, hwAttrs->csnPinMux); + + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X4DMA_CMD_CLEAR_CSN_PIN: + /* If the CS pin is assigned, reset and unassign it */ + if (object->csnPin != GPIO_INVALID_INDEX) + { + GPIO_resetConfig(object->csnPin); + object->csnPin = GPIO_INVALID_INDEX; + } + ret = SPI_STATUS_SUCCESS; + break; + + case SPICC26X4DMA_CMD_SET_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) + { + object->manualStart = true; + ret = SPI_STATUS_SUCCESS; + } + break; + + case SPICC26X4DMA_CMD_CLR_MANUAL: + /* If a transaction is queued, do not modify */ + if (object->headPtr == NULL) + { + object->manualStart = false; + ret = SPI_STATUS_SUCCESS; + } + break; + + case SPICC26X4DMA_CMD_MANUAL_START: + if (object->headPtr != NULL && object->manualStart) + { + enableSPIAndMux(handle); + enableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + ret = SPI_STATUS_SUCCESS; + } + break; + + case SPICC26X4DMA_CMD_SET_SAMPLE_DELAY: + sampleDelay = *((uint_least8_t *)arg); + if (object->mode == SPI_CONTROLLER && sampleDelay <= (SPI_CLKCTL_DSAMPLE_M >> SPI_CLKCTL_DSAMPLE_S)) + { + /* Cache the value so it is persistent across standby */ + object->dsample = sampleDelay << SPI_CLKCTL_DSAMPLE_S; + + HWREG(hwAttrs->baseAddr + SPI_O_CLKCTL) &= ~SPI_CLKCTL_DSAMPLE_M; + HWREG(hwAttrs->baseAddr + SPI_O_CLKCTL) |= object->dsample; + ret = SPI_STATUS_SUCCESS; + } + break; + + default: + /* This command is not defined */ + ret = SPI_STATUS_UNDEFINEDCMD; + break; + } + + return (ret); +} + +/* + * ======== SPICC26X4DMA_hwiFxn ======== + */ +static void SPICC26X4DMA_hwiFxn(uintptr_t arg) +{ + uint32_t freeChannel; + uint32_t intStatus; + SPI_Transaction *completedList; + size_t *transferSize; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + SPICC26X4DMA_Object *object = ((SPI_Handle)arg)->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = ((SPI_Handle)arg)->hwAttrs; + uint8_t i; + uintptr_t key; + + intStatus = getInterruptStatus(hwAttrs->baseAddr, true); + clearInterrupt(hwAttrs->baseAddr, intStatus); + + if (intStatus & SPI_MIS_RXFIFO_OVF_SET) + { + if (object->headPtr != NULL) + { + /* + * RX overrun during a transfer; mark the current transfer + * as failed & cancel all remaining transfers. + */ + object->headPtr->status = SPI_TRANSFER_FAILED; + + SPICC26X4DMA_transferCancel((SPI_Handle)arg); + } + else + { + disableSPI(hwAttrs->baseAddr); + + /* Disable DMA and clear DMA interrupts */ + disableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + disableInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + clearInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + + /* Clear out the FIFO by resetting SPI module and re-initting */ + flushFifos(hwAttrs); + } + } + else + { + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + + /* + * We check both channels for completion; this is done in case the + * second channel finishes while we are still configuring the first. + */ + for (i = 0; i < 2; i++) + { + if (object->headPtr == NULL) + { + /* When i was 0, we finished the last transaction */ + break; + } + + if (object->activeChannel == UDMA_PRI_SELECT) + { + transferSize = &object->priTransferSize; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryPri; + txDmaTableEntry = hwAttrs->dmaTxTableEntryPri; + } + else + { + transferSize = &object->altTransferSize; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryAlt; + txDmaTableEntry = hwAttrs->dmaTxTableEntryAlt; + } + + /* + * The SPI TX FIFO continuously requests the DMA to fill it if there + * is space available. If there are no more frames to put in the + * FIFO we run into a situation where DMA TX will cause undesired + * interrupts. To prevent many undesired interrupts disable DMA_TX + * if there are no more frames to load into the FIFO & there are no + * pending queued transactions. + */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask) && + (txDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && + object->framesQueued == object->headPtr->count && object->headPtr->nextPtr == NULL) + { + disableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelBitMask); + } + + if ((rxDmaTableEntry->ui32Control & UDMA_MODE_M) == UDMA_MODE_STOP && *transferSize != 0) + { + object->framesTransferred += *transferSize; + freeChannel = object->activeChannel; + object->activeChannel = (freeChannel == UDMA_PRI_SELECT) ? UDMA_ALT_SELECT : UDMA_PRI_SELECT; + + /* + * Set the channel's transfer size to 0; 0 lets + * configNextTransfer() know that there is a free channel. + */ + *transferSize = 0; + + if ((object->framesQueued) < (object->headPtr->count) || + (object->framesTransferred) < (object->headPtr->count)) + { + /* + * In this case we need to reconfigure the channel to + * continue transferring frames. configNextTransfer() will + * continue queueing frames for the current transfer or + * start the following transaction if necessary. + */ + configNextTransfer(object, hwAttrs); + enableDMA(hwAttrs->baseAddr, (SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE)); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + } + else + { + key = HwiP_disable(); + /* + * All data has been transferred for the current + * transaction. Set status & move the transaction to + * object->completedList. This is required because + * object->headPtr is moved to the following transaction. + * Also, transaction callbacks are executed in the driver + * SWI which will be posted later. + */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + + if (object->completedTransfers == NULL) + { + /* List is empty; just add the transaction */ + object->completedTransfers = object->headPtr; + completedList = object->completedTransfers; + } + else + { + /* Traverse to the last element */ + completedList = object->completedTransfers; + while (completedList->nextPtr != NULL) + { + completedList = completedList->nextPtr; + } + + /* Store the completed transaction at end of list */ + completedList->nextPtr = object->headPtr; + + /* + * Make sure we are pointing to the end of the list; + * we need to clear references in completed transfer + * after we move object->headPtr forward. + */ + completedList = completedList->nextPtr; + } + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Clear references in completed transfer */ + completedList->nextPtr = NULL; + + /* Update object variables for the following transfer. */ + object->framesQueued = (object->activeChannel == UDMA_PRI_SELECT) ? object->priTransferSize + : object->altTransferSize; + object->framesTransferred = 0; + + HwiP_restore(key); + + if (object->headPtr != NULL) + { + /* Reconfigure channel for following transaction */ + configNextTransfer(object, hwAttrs); + enableDMA(hwAttrs->baseAddr, (SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE)); + UDMACC26XX_channelEnable(object->udmaHandle, + hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + } + else + { + /* No more queued transfers; disable DMA & SPI */ + disableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + + /* + * For this driver implementation the peripheral is kept + * active until either a FIFO-overrun occurs or + * SPI_transferCancel() is executed. + */ + } + + /* Post driver SWI to execute transaction callbacks */ + SwiP_post(&(object->swi)); + } + } + } + } +} + +/* + * ======== SPICC26X4DMA_init ======== + */ +void SPICC26X4DMA_init(SPI_Handle handle) +{ + ((SPICC26X4DMA_Object *)handle->object)->isOpen = false; +} + +/* + * ======== SPICC26X4DMA_open ======== + */ +SPI_Handle SPICC26X4DMA_open(SPI_Handle handle, SPI_Params *params) +{ + union + { + HwiP_Params hwiParams; + SwiP_Params swiParams; + } paramsUnion; + uint32_t key; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + /* Failure conditions */ + if (object->isOpen || params->dataSize > PARAMS_DATASIZE_MAX || params->dataSize < PARAMS_DATASIZE_MIN) + { + HwiP_restore(key); + + return (NULL); + } + object->isOpen = true; + + HwiP_restore(key); + + DebugP_assert((params->dataSize >= PARAMS_DATASIZE_MIN) && (params->dataSize <= PARAMS_DATASIZE_MAX)); + + object->bitRate = params->bitRate; + object->dataSize = params->dataSize; + object->mode = params->mode; + object->transferMode = params->transferMode; + object->transferTimeout = params->transferTimeout; + object->returnPartial = SPICC26X4DMA_retPartDisabled; + object->headPtr = NULL; + object->tailPtr = NULL; + object->completedTransfers = NULL; + object->format = params->frameFormat; + object->txScratchBuf = hwAttrs->defaultTxBufValue; + object->busyBit = (params->mode == SPI_CONTROLLER ? SPI_STAT_BUSY : SPI_STAT_TFE); + object->manualStart = false; + + /* + * Set a default dsample value based on the bitRate + * DSAMPLE can be changed later by the user using the SPI_control() API with + * the SPICC26X4DMA_CMD_SET_SAMPLE_DELAY option. + */ + object->dsample = 0; + if (object->bitRate >= DSAMPLE_MED_BITRATE) + { + object->dsample = 1 << SPI_CLKCTL_DSAMPLE_S; + } + else if (object->bitRate >= DSAMPLE_HIGH_BITRATE) + { + object->dsample = 2 << SPI_CLKCTL_DSAMPLE_S; + } + + Power_setDependency(hwAttrs->powerMngrId); + + /* + * Configure IOs after hardware has been initialized so that IOs aren't + * toggled unnecessary + */ + if (!initHw(handle)) + { + /* + * Trying to use SPI driver when some other driver or application + * has already allocated these pins, error! + */ + Power_releaseDependency(hwAttrs->powerMngrId); + + object->isOpen = false; + return (NULL); + } + + /* CSN is initialized using hwAttrs, but can be re-configured later */ + object->csnPin = hwAttrs->csnPin; + + /* + * IO configuration must occur before SPI IP is enabled + * for peripheral mode. + * For controller mode see enableSPIAndMux(). + */ + if (object->mode == SPI_PERIPHERAL) + { + initIO(handle); + } + + HwiP_Params_init(¶msUnion.hwiParams); + paramsUnion.hwiParams.arg = (uintptr_t)handle; + paramsUnion.hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), (int)hwAttrs->intNum, SPICC26X4DMA_hwiFxn, ¶msUnion.hwiParams); + + SwiP_Params_init(¶msUnion.swiParams); + paramsUnion.swiParams.arg0 = (uintptr_t)handle; + paramsUnion.swiParams.priority = hwAttrs->swiPriority; + SwiP_construct(&(object->swi), SPICC26X4DMA_swiFxn, &(paramsUnion.swiParams)); + + object->udmaHandle = UDMACC26XX_open(); + + Power_registerNotify(&object->spiPostObj, + PowerCC26XX_AWAKE_STANDBY, + (Power_NotifyFxn)spiPostNotify, + (uint32_t)handle); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + /* + * Create a semaphore to block task execution for the duration of the + * SPI transfer + */ + SemaphoreP_constructBinary(&(object->transferComplete), 0); + object->transferCallbackFxn = blockingTransferCallback; + } + else + { + DebugP_assert(params->transferCallbackFxn != NULL); + object->transferCallbackFxn = params->transferCallbackFxn; + } + + return (handle); +} + +/* + * ======== SPICC26X4DMA_swiFxn ======== + */ +static void SPICC26X4DMA_swiFxn(uintptr_t arg0, uintptr_t arg1) +{ + SPI_Transaction *transaction; + SPICC26X4DMA_Object *object = ((SPI_Handle)arg0)->object; + uintptr_t key; + + /* To protect against any Linked-List manipulation, we took ownership of the processor and disabled interrupts + * This also includes the while loop check here, since another process might temporarily tamper with + * object->copmoletedTransfers + */ + key = HwiP_disable(); + + while (object->completedTransfers != NULL) + { + transaction = object->completedTransfers; + + /* Move object->completedTransfers to the next transaction */ + object->completedTransfers = object->completedTransfers->nextPtr; + + transaction->nextPtr = NULL; + + /* Transaction complete; release power constraints */ + releaseConstraint((uint32_t)transaction->txBuf); + + /* Inverted logic here to restore interrupts right before we jump to the callback function and disable them + * after we return */ + HwiP_restore(key); + + /* Execute callback function for completed transfer */ + object->transferCallbackFxn((SPI_Handle)arg0, transaction); + + key = HwiP_disable(); + } + + /* Restore interrupts */ + HwiP_restore(key); +} + +/* + * ======== SPICC26X4DMA_transfer ======== + */ +bool SPICC26X4DMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + uint8_t alignMask; + bool buffersAligned; + uintptr_t key; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (transaction->count == 0) + { + return (false); + } + + key = HwiP_disable(); + + /* + * Make sure that the buffers are aligned properly. + * alignMask is used to check if the RX/TX buffers addresses + * are aligned to the frameSize. + */ + if (object->dataSize <= SPI_DATASIZE_8) + { + alignMask = 0; + } + else if (object->dataSize <= SPI_DATASIZE_16) + { + alignMask = 1; + } + else + { + alignMask = 3; + } + + buffersAligned = ((((uint32_t)transaction->rxBuf & alignMask) == 0) && + (((uint32_t)transaction->txBuf & alignMask) == 0)); + + if (!buffersAligned || (object->headPtr && object->transferMode == SPI_MODE_BLOCKING)) + { + transaction->status = SPI_TRANSFER_FAILED; + + HwiP_restore(key); + + return (false); + } + else + { + if (object->headPtr) + { + object->tailPtr->nextPtr = transaction; + object->tailPtr = transaction; + object->tailPtr->status = SPI_TRANSFER_QUEUED; + } + else + { + object->headPtr = transaction; + object->tailPtr = transaction; + + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + object->tailPtr->status = (object->returnPartial != SPICC26X4DMA_retPartDisabled) + ? SPI_TRANSFER_PEND_CSN_ASSERT + : SPI_TRANSFER_STARTED; + } + + object->tailPtr->nextPtr = NULL; + } + + /* In peripheral mode, optionally enable callback on CSN de-assert */ + if (object->returnPartial == SPICC26X4DMA_retPartEnabledIntNotSet) + { + object->returnPartial = SPICC26X4DMA_retPartEnabledIntSet; + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_IN_INT_BOTH_EDGES | GPIO_CFG_INT_ENABLE); + } + + /* Set constraints to guarantee transaction */ + setConstraint((uint32_t)transaction->txBuf); + + /* + * Polling transfer if BLOCKING mode & transaction->count < threshold + * Peripherals not allowed to use polling unless timeout is disabled + * Polling not allowed with returnPartial mode + */ + if (object->transferMode == SPI_MODE_BLOCKING && transaction->count < hwAttrs->minDmaTransferSize && + object->returnPartial == SPICC26X4DMA_retPartDisabled && + (object->mode == SPI_CONTROLLER || object->transferTimeout == SPI_WAIT_FOREVER)) + { + HwiP_restore(key); + + spiPollingTransfer(handle, transaction); + + /* Release constraint since transaction is done */ + releaseConstraint((uint32_t)transaction->txBuf); + + /* Transaction completed; set status & mark SPI ready */ + object->headPtr->status = SPI_TRANSFER_COMPLETED; + object->headPtr = NULL; + object->tailPtr = NULL; + } + else + { + /* + * Perform a DMA backed SPI transfer; we need exclusive access while + * priming the transfer to prevent race conditions with + * SPICC26X4DMA_transferCancel(). + */ + + /* Enable DMA interrupts */ + clearInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + enableInterrupt(hwAttrs->baseAddr, SPI_MIS_DMA_DONE_TX_SET | SPI_MIS_DMA_DONE_RX_SET); + + primeTransfer(handle); + + /* Enable the RX overrun interrupt in the SPI module */ + enableInterrupt(hwAttrs->baseAddr, SPI_MIS_RXFIFO_OVF_SET); + + HwiP_restore(key); + + if (object->transferMode == SPI_MODE_BLOCKING) + { + if (SemaphoreP_OK != SemaphoreP_pend(&(object->transferComplete), object->transferTimeout)) + { + /* Timeout occurred; cancel the transfer */ + object->headPtr->status = SPI_TRANSFER_FAILED; + SPICC26X4DMA_transferCancel(handle); + + /* + * SPICC26X4DMA_transferCancel() performs callback which posts + * transferComplete semaphore. This call consumes this extra + * post. + */ + SemaphoreP_pend(&(object->transferComplete), SemaphoreP_NO_WAIT); + + return (false); + } + } + } + return (true); +} + +/* + * ======== SPICC26X4DMA_transferCancel ======== + */ +void SPICC26X4DMA_transferCancel(SPI_Handle handle) +{ + uintptr_t key; + uint32_t temp; + SPI_Transaction *tempPtr; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Acquire exclusive access to the driver. Required to prevent race + * conditions if preempted by code trying to configure another transfer. + */ + key = HwiP_disable(); + + if (object->headPtr == NULL) + { + + /* + * Disable the SPI peripheral in case the peripherals finite state + * machine is in a bad state. Calling SPI_transfer() will re-enable + * the peripheral. + */ + disableSPI(hwAttrs->baseAddr); + HwiP_restore(key); + + return; + } + + /* + * There are 2 use cases in which to call transferCancel(): + * 1. The driver is in CALLBACK mode. + * 2. The driver is in BLOCKING mode & there has been a transfer timeout. + */ + if (object->transferMode != SPI_MODE_BLOCKING || object->headPtr->status == SPI_TRANSFER_FAILED || + object->headPtr->status == SPI_TRANSFER_CSN_DEASSERT) + { + finishTransfer(handle); + + /* + * Go through all queued transfers; set status CANCELED (if we did + * not cancel due to timeout). The object->headPtr->count is + * stored/restored temporarily. + */ + temp = object->headPtr->count; + tempPtr = object->headPtr; + + while (tempPtr != NULL) + { + if (tempPtr->status != SPI_TRANSFER_FAILED && tempPtr->status != SPI_TRANSFER_CSN_DEASSERT) + { + tempPtr->status = SPI_TRANSFER_CANCELED; + } + + tempPtr->count = 0; + tempPtr = tempPtr->nextPtr; + } + object->headPtr->count = temp; + + /* Add all cancelled transactions to object->completedTransfers */ + tempPtr = object->completedTransfers; + if (tempPtr == NULL) + { + /* Empty list; just add all of the cancelled transactions */ + object->completedTransfers = object->headPtr; + } + else + { + /* Move through the list until we reach the last element */ + while (tempPtr->nextPtr != NULL) + { + tempPtr = tempPtr->nextPtr; + } + + /* Add all of the cancelled transactions */ + tempPtr->nextPtr = object->headPtr; + } + + /* Clear all driver object variables*/ + object->headPtr = NULL; + object->tailPtr = NULL; + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + + HwiP_restore(key); + + /* + * All transactions have been marked as cancelled & added to + * object->completedTransfers. Post the driver SWI to execute + * callback functions. + */ + SwiP_post(&(object->swi)); + + /* Must return here; do not call HwiP_restore() twice */ + return; + } + + HwiP_restore(key); +} + +/* + * ======== finishTransfer ======== + * This function completes the current transfer + */ +static void finishTransfer(SPI_Handle handle) +{ + uint32_t xferSize; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Prevent interrupt while finishing the transfer */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* + * Disable the TX DMA channel first to stop feeding more frames to + * the FIFO. Next, wait until the TX FIFO is empty (all frames in + * FIFO have been sent). RX DMA channel is disabled later to allow + * the DMA to move all frames already in FIFO to memory. + */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->txChannelBitMask); + + if (object->mode == SPI_CONTROLLER) + { + /* + * Wait until the TX FIFO is empty; this is to make sure the + * chip select is deasserted before disabling the SPI. + */ + while (isSPIbusy(hwAttrs->baseAddr)) {} + } + + disableSPI(hwAttrs->baseAddr); + + /* Now disable the RX, DMA & interrupts */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelBitMask); + disableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + disableInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + clearInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + + /* + * Update transaction->count with the amount of frames which have + * been transferred. + */ + object->headPtr->count = object->framesTransferred; + if (object->priTransferSize) + { + xferSize = UDMACC26XX_GET_TRANSFER_SIZE(hwAttrs->dmaRxTableEntryPri->ui32Control); + + if (xferSize <= object->priTransferSize) + { + object->headPtr->count += (object->priTransferSize - xferSize); + } + } + + if (object->altTransferSize) + { + xferSize = UDMACC26XX_GET_TRANSFER_SIZE(hwAttrs->dmaRxTableEntryAlt->ui32Control); + + if (xferSize <= object->altTransferSize) + { + object->headPtr->count += (object->altTransferSize - xferSize); + } + } + + /* + * Disables peripheral, clears all registers & reinitializes it to + * parameters used in SPI_open() + */ + initHw(handle); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); +} + +/* + * ======== processCSNDeassert ======== + */ +static void processCSNDeassert(SPI_Handle handle) +{ + uintptr_t key; + SPI_Transaction *tempXfer; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* + * Acquire exclusive access to the driver. Required to prevent race + * conditions if preempted by code trying to configure another transfer. + */ + key = HwiP_disable(); + + if (object->headPtr == NULL) + { + /* + * Disable the SPI peripheral in case the peripherals finite state + * machine is in a bad state. Calling SPI_transfer() will re-enable + * the peripheral. + */ + disableSPI(hwAttrs->baseAddr); + HwiP_restore(key); + return; + } + + object->headPtr->status = SPI_TRANSFER_CSN_DEASSERT; + + finishTransfer(handle); + + if (object->completedTransfers == NULL) + { + /* Empty list; just add the completed transaction */ + object->completedTransfers = object->headPtr; + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Clear references in completed transfer */ + object->completedTransfers->nextPtr = NULL; + } + else + { + tempXfer = object->completedTransfers; + + /* Move through the list until we reach the last element */ + while (tempXfer->nextPtr != NULL) + { + tempXfer = tempXfer->nextPtr; + } + + /* Add completed transaction to the end of the list */ + tempXfer->nextPtr = object->headPtr; + + /* Move the object->headPtr to the next transaction */ + object->headPtr = object->headPtr->nextPtr; + + /* Make sure we are pointing to the end of the list */ + tempXfer = tempXfer->nextPtr; + + /* Clear references in completed transfer */ + tempXfer->nextPtr = NULL; + } + + /* Clear driver object DMA transaction tracking variables */ + object->framesQueued = 0; + object->framesTransferred = 0; + object->priTransferSize = 0; + object->altTransferSize = 0; + + if (object->headPtr != NULL) + { + /* Reconfigure channel for next transaction */ + configNextTransfer(object, hwAttrs); + + object->activeChannel = UDMA_PRI_SELECT; + if (object->headPtr->count > MAX_DMA_TRANSFER_AMOUNT) + { + configNextTransfer(object, hwAttrs); + } + + /* Enable DMA to generate interrupt on SPI peripheral */ + if (!object->manualStart) + { + enableSPIAndMux(handle); + } + } + else + { + object->tailPtr = NULL; + + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X4DMA_retPartEnabledIntNotSet; + + /* No more queued transfers; disable DMA & SPI */ + disableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + + /* + * For this driver implementation the peripheral is kept + * active until either a FIFO-overrun occurs or + * SPI_transferCancel() is executed. + */ + } + + HwiP_restore(key); + + /* + * Post the driver SWI to execute callback functions. + */ + SwiP_post(&(object->swi)); + + /* Must return here; do not call HwiP_restore() twice */ + return; +} + +/* + * ======== blockingTransferCallback ======== + */ +static void blockingTransferCallback(SPI_Handle handle, SPI_Transaction *msg) +{ + SPICC26X4DMA_Object *object = handle->object; + + SemaphoreP_post(&(object->transferComplete)); +} + +/* + * ======== configNextTransfer ======== + * This function must be executed with interrupts disabled. + */ +static void configNextTransfer(SPICC26X4DMA_Object *object, SPICC26X4DMA_HWAttrs const *hwAttrs) +{ + size_t framesQueued; + uint32_t transferAmt; + SPI_Transaction *transaction; + volatile tDMAControlTable *rxDmaTableEntry; + volatile tDMAControlTable *txDmaTableEntry; + uint8_t index; + uint8_t optionsIndex; + + /* + * The DMA options vary according to data frame size; options for 8-bit + * data (or smaller) are in index 0. Options for 16-bit frame sizes are + * in index 1, option for 32-bit frame sizes are in index 2 + */ + if (object->dataSize <= SPI_DATASIZE_8) + { + index = 0; + optionsIndex = 1; + } + else if (object->dataSize <= SPI_DATASIZE_16) + { + index = 1; + optionsIndex = 2; + } + else + { + index = 2; + optionsIndex = 4; + } + + /* + * object->framesQueued keeps track of how many frames (of the current + * transaction) have been configured for DMA transfer. If + * object->framesQueued == transaction->count; all frames have been queued + * & we should configure the free DMA channel to send the next transaction. + * When the current transaction has completed; object->framesQueued + * will be updated (in the ISR) to reflect the amount of frames queued + * of the following transaction. + */ + transaction = object->headPtr; + if (object->framesQueued < transaction->count) + { + framesQueued = object->framesQueued; + } + else + { + transaction = object->headPtr->nextPtr; + if (transaction == NULL) + { + /* There are no queued transactions */ + return; + } + + framesQueued = 0; + transaction->status = (object->returnPartial != SPICC26X4DMA_retPartDisabled) ? SPI_TRANSFER_PEND_CSN_ASSERT + : SPI_TRANSFER_STARTED; + } + + /* + * The DMA has a max transfer amount of 1024. If the transaction is + * greater; we must transfer it in chunks. framesQueued keeps track of + * how much data has been queued for transfer. + */ + if ((transaction->count - framesQueued) > MAX_DMA_TRANSFER_AMOUNT) + { + transferAmt = MAX_DMA_TRANSFER_AMOUNT; + } + else + { + transferAmt = transaction->count - framesQueued; + } + + /* Determine free channel & mark it as used by setting transfer size */ + if (object->priTransferSize == 0) + { + object->priTransferSize = transferAmt; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryPri; + txDmaTableEntry = hwAttrs->dmaTxTableEntryPri; + } + else + { + object->altTransferSize = transferAmt; + + rxDmaTableEntry = hwAttrs->dmaRxTableEntryAlt; + txDmaTableEntry = hwAttrs->dmaTxTableEntryAlt; + } + + /* Setup the TX transfer buffers & characteristics */ + if (transaction->txBuf) + { + txDmaTableEntry->ui32Control = dmaTxConfig[index]; + + /* + * Add an offset for the amount of data transferred. The offset is + * calculated by: object->framesQueued * (optionsIndex). This + * accounts for 8 or 16-bit sized transfers. + */ + txDmaTableEntry->pvSrcEndAddr = (void *)((uint32_t)transaction->txBuf + + (uint32_t)(framesQueued * optionsIndex) + (transferAmt << index) - 1); + } + else + { + txDmaTableEntry->ui32Control = dmaNullConfig[index]; + txDmaTableEntry->pvSrcEndAddr = (void *)&(object->txScratchBuf); + } + txDmaTableEntry->pvDstEndAddr = (void *)(hwAttrs->baseAddr + SPI_O_TXDATA); + txDmaTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transferAmt); + + /* Setup the RX transfer buffers & characteristics */ + if (transaction->rxBuf) + { + rxDmaTableEntry->ui32Control = dmaRxConfig[index]; + + /* + * Add an offset for the amount of data transferred. The offset is + * calculated by: object->framesQueued * (optionsIndex). This + * accounts for 8 or 16-bit sized transfers. + */ + + rxDmaTableEntry->pvDstEndAddr = (void *)((uint32_t)transaction->rxBuf + + (uint32_t)(framesQueued * optionsIndex) + (transferAmt << index) - 1); + } + else + { + rxDmaTableEntry->ui32Control = dmaNullConfig[index]; + rxDmaTableEntry->pvDstEndAddr = &object->rxScratchBuf; + } + rxDmaTableEntry->pvSrcEndAddr = (void *)(hwAttrs->baseAddr + SPI_O_RXDATA); + rxDmaTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transferAmt); + + if (transaction == object->headPtr) + { + /* + * Only update object->framesQueued if we are configuring a DMA + * channel for the current transaction. + */ + object->framesQueued += transferAmt; + } + + if (!object->manualStart && object->mode == SPI_PERIPHERAL) + { + /* Enable DMA to generate interrupt on SPI peripheral */ + enableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + } + + return; +} + +/* + * ======== csnCallback ======== + * Peripheral mode optional callback function for when the CSN is asserted & + * deasserted. + */ +static void csnCallback(uint_least8_t index) +{ + uintptr_t key; + SPI_Handle spiHandle = (SPI_Handle)GPIO_getUserArg(index); + SPICC26X4DMA_Object *object = spiHandle->object; + + if (!GPIO_read(index)) + { + /* Start transfer if CSN goes low */ + key = HwiP_disable(); + if (object->headPtr != NULL) + { + /* We have data ready; indicate transaction started */ + object->headPtr->status = SPI_TRANSFER_STARTED; + } + else + { + /* We are not waiting to transfer; disable all interrupts */ + GPIO_setInterruptConfig(object->csnPin, GPIO_CFG_INT_DISABLE); + object->returnPartial = SPICC26X4DMA_retPartEnabledIntNotSet; + } + HwiP_restore(key); + } + else + { + processCSNDeassert(spiHandle); + } +} + +/* + * ======== flushFifos ======== + */ +static void flushFifos(SPICC26X4DMA_HWAttrs const *hwAttrs) +{ + /* Disable the SPI in case it isn't already */ + disableSPI(hwAttrs->baseAddr); + + /* Trigger fifo flush */ + HWREG(hwAttrs->baseAddr + SPI_O_CTL1) |= SPI_CTL1_FIFORST_SET; + + /* Delay 5 cycles to ensure the flush is complete */ + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + + /* Complete the fifo flush */ + HWREG(hwAttrs->baseAddr + SPI_O_CTL1) &= ~(SPI_CTL1_FIFORST_SET); +} + +/* + * ======== getDmaChannelNumber ======== + */ +static inline uint32_t getDmaChannelNumber(uint32_t x) +{ +#if defined(__TI_COMPILER_VERSION__) + return ((uint32_t)__clz(__rbit(x))); +#elif defined(__GNUC__) + return ((uint32_t)__builtin_ctz(x)); +#elif defined(__IAR_SYSTEMS_ICC__) + return ((uint32_t)__CLZ(__RBIT(x))); +#else + #error "Unsupported compiler" +#endif +} + +/* + * ======== initHw ======== + */ +static bool initHw(SPI_Handle handle) +{ + ClockP_FreqHz freq; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t format; + + flushFifos(hwAttrs); + + /* Disable SPI operation */ + disableSPI(hwAttrs->baseAddr); + + /* Disable SPI module interrupts */ + disableInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + clearInterrupt(hwAttrs->baseAddr, SPI_INT_ALL); + + /* Get requested format */ + format = frameFormat[object->format]; + + if (hwAttrs->csnPin && ((format & SPI_CTL0_FRF_M) == SPI_CTL0_FRF_MOTOROLA_3WIRE)) + { + /* + * A CS pin was specified, upgrade the 3WIRE to a 4WIRE mode + */ + format |= SPI_CTL0_FRF_MOTOROLA_4WIRE; + } + + /* Set the SPI configuration */ + ClockP_getCpuFreq(&freq); + + if (freq.lo / 2 >= object->bitRate) + { + configSPI(hwAttrs->baseAddr, + freq.lo, + format, + mode[object->mode], + object->bitRate, + object->dataSize, + object->dsample); + return true; + } + return false; +} + +/* + * ======== initIO ======== + * This functions initializes the SPI IOs. + * + * @pre Function assumes that the SPI handle is pointing to a hardware + * module which has already been opened. + */ +static void initIO(SPI_Handle handle) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + GPIO_setConfigAndMux(hwAttrs->clkPin, GPIO_CFG_INPUT, hwAttrs->clkPinMux); + GPIO_setConfigAndMux(object->csnPin, GPIO_CFG_INPUT, hwAttrs->csnPinMux); + + if (object->mode == SPI_PERIPHERAL) + { + GPIO_setConfigAndMux(hwAttrs->picoPin, GPIO_CFG_INPUT, hwAttrs->rxPinMux); + GPIO_setConfigAndMux(hwAttrs->pociPin, GPIO_CFG_NO_DIR, hwAttrs->txPinMux); + + GPIO_setCallback(object->csnPin, csnCallback); + GPIO_setUserArg(object->csnPin, handle); + } + else + { + GPIO_setConfigAndMux(hwAttrs->clkPin, GPIO_CFG_INPUT, hwAttrs->clkPinMux); + GPIO_setConfigAndMux(hwAttrs->picoPin, GPIO_CFG_NO_DIR, hwAttrs->txPinMux); + GPIO_setConfigAndMux(hwAttrs->pociPin, GPIO_CFG_INPUT, hwAttrs->rxPinMux); + } +} + +/* + * ======== finalizeIO ======== + * This function releases the SPI IOs. + */ +static void finalizeIO(SPI_Handle handle) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + GPIO_resetConfig(hwAttrs->picoPin); + GPIO_resetConfig(hwAttrs->pociPin); + GPIO_resetConfig(hwAttrs->clkPin); + GPIO_resetConfig(object->csnPin); +} + +/* + * ======== primeTransfer ======== + * Function must be executed with interrupts disabled. + */ +static inline void primeTransfer(SPI_Handle handle) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (object->priTransferSize != 0 && object->altTransferSize != 0) + { + /* + * Both primary & alternate channels are configured for a transfer. + * In this case no work is required; the Hwi will configure channels + * as transfers continue & complete. + */ + } + else if (object->priTransferSize == 0 && object->altTransferSize == 0) + { + /* + * Primary & alternate channels are disabled; no active transfer, + * configure a new transfer. + * + * DMA based transfers use the DMA in ping-pong mode. If the transfer is + * larger than what the primary channel can handle; alternate channel is + * configured to continue where the primary channel left off. Channels + * are continuously reconfigured until the transfer is completed. + * + * We disable the alternate channel initially. This however causes an + * undesired interrupt to be triggered; so we need to + * disable/clear/re-enable the interrupt. + */ + HwiP_disableInterrupt(hwAttrs->intNum); + + /* Set the primary DMA structure as active */ + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->rxChannelBitMask), + UDMA_ATTR_ALTSELECT); + UDMACC26XX_disableAttribute(object->udmaHandle, + getDmaChannelNumber(hwAttrs->txChannelBitMask), + UDMA_ATTR_ALTSELECT); + + HwiP_clearInterrupt(hwAttrs->intNum); + HwiP_enableInterrupt(hwAttrs->intNum); + + /* Configure RX & TX DMA transfers */ + configNextTransfer(object, hwAttrs); + object->activeChannel = UDMA_PRI_SELECT; + if (object->headPtr->count > MAX_DMA_TRANSFER_AMOUNT) + { + configNextTransfer(object, hwAttrs); + } + + if (!object->manualStart) + { + enableSPIAndMux(handle); + if (object->mode == SPI_CONTROLLER) + { + /* Enable DMA to generate interrupt on SPI peripheral */ + enableDMA(hwAttrs->baseAddr, SPI_DMACR_TXDMAE | SPI_DMACR_RXDMAE); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelBitMask | hwAttrs->txChannelBitMask); + } + } + } + else + { + /* One of the channels is active; configure the other channel */ + configNextTransfer(object, hwAttrs); + } +} + +/* + * ======== releaseConstraint ======== + */ +static inline void releaseConstraint(uint32_t txBufAddr) +{ + /* Release need flash if buffer was in flash. */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) + { + Power_releaseConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + } + + /* Release standby constraint since operation is done. */ + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== setConstraint ======== + */ +static inline void setConstraint(uint32_t txBufAddr) +{ + /* + * Ensure flash is available if TX buffer is in flash. + * Flash starts with 0x0.. + */ + if (((txBufAddr & 0xF0000000) == 0x0) && (txBufAddr)) + { + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + Power_setConstraint(PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING); + } + + /* Set constraints to guarantee operation */ + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/* + * ======== spiPollingTransfer ======== + */ +static inline void spiPollingTransfer(SPI_Handle handle, SPI_Transaction *transaction) +{ + uint8_t txIncrement, rxIncrement; + uint32_t dummyBuffer; + size_t rxCount, txCount; + void *rxBuf; + void *txBuf; + bool put; + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Only increment src/destination pointers if buffers were provided */ + if (transaction->rxBuf) + { + rxBuf = transaction->rxBuf; + if (object->dataSize <= SPI_DATASIZE_8) + { + rxIncrement = sizeof(uint8_t); + } + else if (object->dataSize <= SPI_DATASIZE_16) + { + rxIncrement = sizeof(uint16_t); + } + else + { + rxIncrement = sizeof(uint32_t); + } + } + else + { + rxBuf = &(object->rxScratchBuf); + rxIncrement = 0; + } + + if (transaction->txBuf) + { + txBuf = transaction->txBuf; + if (object->dataSize <= SPI_DATASIZE_8) + { + txIncrement = sizeof(uint8_t); + } + else if (object->dataSize <= SPI_DATASIZE_16) + { + txIncrement = sizeof(uint16_t); + } + else + { + txIncrement = sizeof(uint32_t); + } + } + else + { + txBuf = (void *)&(object->txScratchBuf); + txIncrement = 0; + } + + rxCount = transaction->count; + txCount = rxCount; + + enableSPIAndMux(handle); + + /* Fill the TX FIFO as much as we can before reading */ + while (rxCount--) + { + if (object->dataSize <= SPI_DATASIZE_8) + { + put = true; + while (txCount > 0 && put) + { + put = dataPutNonBlocking(hwAttrs->baseAddr, *((uint8_t *)txBuf)); + if (put) + { + txBuf = (void *)(((uint32_t)txBuf) + txIncrement); + txCount--; + } + } + dataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint8_t *)rxBuf) = (uint8_t)dummyBuffer; + } + else if (object->dataSize <= SPI_DATASIZE_16) + { + put = true; + while (txCount > 0 && put) + { + put = dataPutNonBlocking(hwAttrs->baseAddr, *((uint16_t *)txBuf)); + if (put) + { + txBuf = (void *)(((uint32_t)txBuf) + txIncrement); + txCount--; + } + } + dataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint16_t *)rxBuf) = (uint16_t)dummyBuffer; + } + else + { + put = true; + while (txCount > 0 && put) + { + put = dataPutNonBlocking(hwAttrs->baseAddr, *((uint32_t *)txBuf)); + if (put) + { + txBuf = (void *)(((uint32_t)txBuf) + txIncrement); + txCount--; + } + } + dataGet(hwAttrs->baseAddr, &dummyBuffer); + *((uint32_t *)rxBuf) = (uint32_t)dummyBuffer; + } + + /* Update rxBuf position */ + rxBuf = (void *)(((uint32_t)rxBuf) + rxIncrement); + } + + while (spiBusy(object, hwAttrs)) {} +} + +/* + * ======== spiPostNotify ======== + */ +static int spiPostNotify(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + SPI_Handle handle = (SPI_Handle)clientArg; + initHw(handle); + enableSPIAndMux(handle); + return (Power_NOTIFYDONE); +} + +/* + * ======== spiBusy ======== + * HW is busy when in controller mode and BSY bit is set, or when in peripheral mode + * and TFE bit is not set. + */ +static inline bool spiBusy(SPICC26X4DMA_Object *object, SPICC26X4DMA_HWAttrs const *hwAttrs) +{ + bool registerBit = (bool)(HWREG(hwAttrs->baseAddr + SPI_O_STAT) & (object->busyBit)); + if (object->busyBit == SPI_STAT_BUSY_ACTIVE) + { + return (registerBit); + } + else + { + return (!registerBit); + } +} + +/* + * ======== disableSPI ======== + * Disables the SPI peripheral + */ +static inline void disableSPI(uint32_t baseAddr) +{ + HWREG(baseAddr + SPI_O_CTL1) &= ~SPI_CTL1_ENABLE_ENABLE; +} + +/* + * ======== enableSPIAndMux ======== + * Enables the SPI IP and perfroms Muxing only when in SPI_CONTROLLER Mode + */ +static inline void enableSPIAndMux(SPI_Handle handle) +{ + SPICC26X4DMA_Object *object = handle->object; + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t baseAddr = hwAttrs->baseAddr; + + if (!isSPIEnabled(handle)) + { + HWREG(baseAddr + SPI_O_CTL1) |= SPI_CTL1_ENABLE_ENABLE; + if (object->mode == SPI_CONTROLLER) + { + /* + * IO mux needs to occur after SPI IP is enabled + * to produce correct signal state. + */ + initIO(handle); + } + } +} + +/* + * ======== isSPIEnabled ======== + * returns the SPI peripheral state + */ +static inline bool isSPIEnabled(SPI_Handle handle) +{ + SPICC26X4DMA_HWAttrs const *hwAttrs = handle->hwAttrs; + return (HWREG(hwAttrs->baseAddr + SPI_O_CTL1) & SPI_CTL1_ENABLE_ENABLE) != 0; +} + +/* + * ======== getInterruptStatus ======== + * Return the masked interrupt status + */ +static inline uint32_t getInterruptStatus(uint32_t baseAddr, bool masked) +{ + /* Return either the interrupt status or the raw interrupt status as + requested. */ + if (masked) + { + return (HWREG(baseAddr + SPI_O_MIS)); + } + else + { + return (HWREG(baseAddr + SPI_O_RIS)); + } +} + +/* + * ======== enableInterrupt ======== + * Enables the SPI peripheral interrupt + */ +static inline void enableInterrupt(uint32_t baseAddr, uint32_t irqs) +{ + HWREG(baseAddr + SPI_O_IMASK) |= irqs; +} + +/* + * ======== disableInterrupt ======== + * Disables the SPI peripheral interrupt + */ +static inline void disableInterrupt(uint32_t baseAddr, uint32_t irqs) +{ + HWREG(baseAddr + SPI_O_IMASK) &= ~irqs; +} + +/* + * ======== clearInterrupt ======== + * Clears the specified SPI peripheral interrupts + */ +static inline void clearInterrupt(uint32_t baseAddr, uint32_t irqs) +{ + HWREG(baseAddr + SPI_O_ICLR) = irqs; +} + +/* + * ======== enableDMA ======== + * Enable the SPI DMA peripheral + */ +static void enableDMA(uint32_t baseAddr, uint32_t dmaFlags) +{ + /* Set the requested bits in the SPI DMA control register. */ + HWREG(baseAddr + SPI_O_DMACR) |= dmaFlags; +} + +static void disableDMA(uint32_t baseAddr, uint32_t dmaFlags) +{ + /* Clear the requested bits in the SPI DMA control register. */ + HWREG(baseAddr + SPI_O_DMACR) &= ~dmaFlags; +} + +/* + * ======== configSPI ======== + * Configures the peripheral settings + */ +static bool configSPI(uint32_t baseAddr, + uint32_t freq, + uint32_t format, + uint32_t mode, + uint32_t bitRate, + uint32_t dataSize, + uint32_t dsample) +{ + uint16_t scr; + uint32_t ratio; + + /* Get existing settings */ + uint32_t reg = HWREG(baseAddr + SPI_O_CTL0); + /* Create mask for settings to modify */ + uint32_t mask = (SPI_CTL0_DSS_M | SPI_CTL0_FRF_M | SPI_CTL0_SPO_M | SPI_CTL0_SPH_M); + + /* Convert and mask data size to HW register format */ + dataSize = (SPI_CTL0_DSS_M & (dataSize - 1)); + /* Apply updated register */ + HWREG(baseAddr + SPI_O_CTL0) = (reg & ~mask) | format | dataSize; + + /* Set controller/peripheral mode, MSB first */ + HWREG(baseAddr + SPI_O_CTL1) = mode | SPI_CTL1_MSB_ENABLE; + + /* Get existing settings */ + reg = HWREG(baseAddr + SPI_O_CLKCTL); + + /* Create a mask for settings to modify */ + mask = (SPI_CLKCTL_DSAMPLE_M | SPI_CLKCTL_SCR_M); + + /* Calculate scr variable */ + ratio = freq / (2 * bitRate); + if (ratio > 0 && ratio <= SPI_CLKCTL_SCR_MAXIMUM) + { + scr = (uint16_t)(ratio - 1); + } + else + { + scr = 0; + } + + /* Set clock divider */ + HWREG(baseAddr + SPI_O_CLKCTL) = (reg & ~mask) | dsample | scr; + + return (true); +} + +static int32_t dataPutNonBlocking(uint32_t baseAddr, uint32_t frame) +{ + /* Check for space to write. */ + if (HWREG(baseAddr + SPI_O_STAT) & SPI_STAT_TNF_NOT_FULL) + { + /* Write the data to the SPI TX FIFO. */ + HWREG(baseAddr + SPI_O_TXDATA) = frame; + return (1); + } + else + { + return (0); + } +} + +static void dataGet(uint32_t baseAddr, uint32_t *frame) +{ + /* Wait until there is data to be read. */ + while (HWREG(baseAddr + SPI_O_STAT) & SPI_STAT_RFE_EMPTY) {} + + /* Read data from SPI RX FIFO. */ + *frame = HWREG(baseAddr + SPI_O_RXDATA); +} + +static bool isSPIbusy(uint32_t baseAddr) +{ + /* Determine if the SPI is busy. */ + return ((HWREG(baseAddr + SPI_O_STAT) & SPI_STAT_BUSY) ? true : false); +} diff --git a/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.h b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.h new file mode 100644 index 00000000..6c7a0a62 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/spi/SPICC26X4DMA.h @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2021-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* clang-format off */ +/*!***************************************************************************** + * @file SPICC26X4DMA.h + * + * @brief SPI driver implementation for a CC26X4 SPI controller using + * the UDMA controller. + * + * # Driver include # + * The SPI header file should be included in an application as follows: + * @code + * #include + * #include + * #include + * @endcode + * + * Refer to @ref SPI.h for a complete description of APIs. + * + * Note that the user also needs to include the UDMACC26XX.h driver since the + * SPI uses uDMA in order to improve throughput. + * + * # Overview # + * The general SPI API should be used in application code, i.e. SPI_open() + * should be used instead of SPICC26X4DMA_open(). The board file will define the device + * specific config, and casting in the general API will ensure that the correct + * device specific functions are called. + * This is also reflected in the example code in [Use Cases](@ref USE_CASES_SPI_X4). + * + * # General Behavior # + * Before using SPI on CC26X4: + * - The SPI driver is initialized by calling SPI_init(). + * - The SPI HW is configured and flags system dependencies (e.g. IOs, + * power, etc.) by calling SPI_open(). + * - The SPI driver makes use of DMA in order to optimize throughput. + * This is handled directly by the SPI driver, so the application should never + * make any calls directly to the UDMACC26XX.h driver. + * - This implementation supports queueing multiple transactions in callback + * mode. See the @ref USE_CASE_QUEUE_X4 "queueing example." + * - When queueing multiple transactions that should transfer one after the + * other, it is recommended to use the driver in 'manual start' mode by using + * the #SPICC26X4DMA_CMD_SET_MANUAL command. In this mode, the driver will + * not start any queued transfers until SPI_control() is called with the + * #SPICC26X4DMA_CMD_MANUAL_START command. This mode is off by default and + * can be disabled by using command #SPICC26X4DMA_CMD_CLR_MANUAL. See the + * @ref USE_CASE_MANUAL_START_X4 "Manual Start Example". + * + * The following is true for peripheral operation: + * - RX overrun IRQ, SPI and UDMA modules are enabled by calling SPI_transfer(). + * - All received bytes are ignored after SPI_open() is called, until + * the first SPI_transfer(). + * - If an RX overrun occurs or if SPI_transferCancel() is called, RX overrun IRQ, SPI and UDMA + * modules are disabled, TX and RX FIFOs are flushed and all bytes are ignored. + * - After a successful transfer, RX overrun IRQ and SPI module remains enabled and UDMA module is disabled. + * SPI_transfer() must be called again before RX FIFO fills up in order to + * avoid overflow. If the TX buffer overflows, zeros will be output. + * It is safe to call another SPI_transfer() from the transfer callback, + * see [Continuous Peripheral Transfer] (@ref USE_CASE_CST_X4) use case below. + * - The SPI driver supports partial return, that can be used if the + * transfer size is unknown. If #SPICC26X4DMA_CMD_RETURN_PARTIAL_ENABLE is + * passed to SPI_control(), the transfer will end when chip select is + * deasserted. The #SPI_Transaction.status and the #SPI_Transaction.count + * will be updated to indicate whether the transfer ended due to a chip + * select deassertion and how many bytes were transferred. See + * [Peripheral Mode With Return Partial] (@ref USE_CASE_RP_X4) use case below. + * - When queueing several transactions if the first is a 'short' + * transaction (8 or fewer frames), it is required to use + * @ref USE_CASE_MANUAL_START_X4 "Manual Start mode." + * + * The following apply for controller operation: + * - SPI and UDMA modules are enabled by calling SPI_transfer(). + * - If the SPI_transfer() succeeds, SPI module is enabled and UDMA module is disabled. + * - If SPI_transferCancel() is called, SPI and UDMA modules are disabled and + * TX and RX FIFOs are flushed. + * + * After SPI operation has ended: + * - Release system dependencies for SPI by calling SPI_close(). + * + * The callback function is always called in a SWI context. + * + * # Error handling # + * If an RX overrun occurs during peripheral operation: + * - If a transfer is ongoing, all bytes received up until the error occurs will be returned, with the + * error signaled in the #SPI_Transaction.status field. RX overrun IRQ, SPI and UDMA modules are then disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * - If a transfer is not ongoing, RX overrun IRQ, SPI and UDMA modules are disabled, + * TX and RX FIFOs are flushed and all bytes will be ignored until a new transfer is issued. + * + * # Timeout # + * Timeout can occur in #SPI_MODE_BLOCKING, there's no timeout in #SPI_MODE_CALLBACK. + * When in #SPI_MODE_CALLBACK, the transfer must be cancelled by calling SPI_transferCancel().@n + * If a timeout happens in either #SPI_PERIPHERAL or #SPI_CONTROLLER mode, + * the receive buffer will contain the bytes received up until the timeout occurred. + * The SPI transaction status will be set to #SPI_TRANSFER_FAILED. + * The SPI transaction count will be set to the number of bytes sent/received before timeout. + * The remaining bytes will be flushed from the TX FIFO so that the subsequent transfer + * can be executed correctly. Note that specifying a timeout prevents the + * driver from performing a polling transfer when in peripheral mode. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The SPICC26X4DMA.h driver is setting a power constraint during transfers to keep + * the device out of standby. When the transfer has finished, the power + * constraint is released. + * The following statements are valid: + * - After SPI_open(): the device is still allowed to enter standby. + * - In peripheral mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After an RX overflow: device is allowed to enter standby. + * - After a successful SPI_transfer(): the device is allowed + * to enter standby, but SPI module remains enabled. + * - _Note_: In peripheral mode, the device might enter standby while a byte is being + * transferred if SPI_transfer() is not called again after a successful + * transfer. This could result in corrupt data being transferred. + * - Application thread should typically either issue another transfer after + * SPI_transfer() completes successfully, or call + * SPI_transferCancel() to disable the SPI module and thus assuring that no data + * is received while entering standby. + * . + * - In controller mode: + * - During SPI_transfer(): the device cannot enter standby, only idle. + * - After SPI_transfer() succeeds: the device can enter standby. + * - If SPI_transferCancel() is called: the device can enter standby. + * + * @note The external hardware connected to the SPI might have some pull configured on the + * SPI lines. When the SPI is inactive, this might cause leakage on the IO and the + * current consumption to increase. The application must configure a pull configuration + * that aligns with the external hardware. + * See [Ensure low power during inactive periods] (@ref USE_CASE_LPWR_X4) for code example. + * + * # SPI details # + * ## Chip Select # + * This SPI controller supports a hardware chip select pin. Refer to the + * user manual on how this hardware chip select pin behaves in regards + * to the SPI frame format. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Chip select typeSPI_CONTROLLER modeSPI_PERIPHERAL mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI peripheral is + * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
+ * + * ### Multiple peripherals when operating in controller mode # + * In a scenario where the SPI module is operating in controller mode with multiple + * SPI peripherals, the chip select pin can be reallocated at runtime to select the + * appropriate peripheral device. See [Controller Mode With Multiple Peripherals](@ref USE_CASE_MMMS_X4) use case below. + * This is only relevant when chip select is a hardware chip select. Otherwise the application + * can control the chip select pins directly using the GPIO driver. + * + * ## Data Frames # + * + * When the SPI is configured as SPI controller, the data frame can be any size from 4-bits to 32-bits. + * When the SPI is configured as SPI peripheral , the minimum data frame is 7-bits and the maximum is 32-bits. + * If the dataSize in #SPI_Params is greater that 8-bits, then the SPICC26X4DMA driver + * implementation will assume that the #SPI_Transaction txBuf and rxBuf + * point to an array of 16-bit uint16_t elements. Similarly, if the dataSize in + * #SPI_Params is greater than 16-bits, the SPICC26X4DMA driver will assume buffers + * of uint32_t elements are used. + * + * dataSize | buffer element size | + * -------- | ------------------- | + * 4-8 bits | uint8_t | + * 9-16 bits | uint16_t | + * 17-32 bits | uint32_t | + * + * ## Bit Rate ## + * When the SPI is configured as SPI peripheral, the maximum bit rate is 8MHz. + * + * When the SPI is configured as SPI controller, the maximum bit rate is 12MHz. + * + * + * ## UDMA # + * ### Interrupts # + * The UDMA module generates IRQs on the SPI interrupt vector. This driver automatically + * installs a UDMA aware Hwi (interrupt) to service the assigned UDMA channels. + * + * ### Transfer Size Limit # + * + * The UDMA controller only supports data transfers of up to 1024 data frames. + * A transfer with more than 1024 frames will be transmitted/received in + * multiple 1024 sized portions until all data has been transmitted/received. + * A data frame can be 4 to 32 bits in length depending on SPI controller or peripheral mode. + * + * ### Scratch Buffers # + * A uint16_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf + * are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size + * of the transfer count, a single-word UDMA accessible uint16_t scratch buffer is used. + * When rxBuf is NULL, the UDMA will transfer all the received SPI data into the + * scratch buffer as a "bit-bucket". + * When txBuf is NULL, the scratch buffer is initialized to defaultTxBufValue + * so the uDMA will send some known value. + * Each SPI driver instance uses its own scratch buffer. + * + * ### TX and RX buffers # + * Before SPI_transfer, txBuf should be filled with the outgoing SPI data. These + * data are sent out during the transfer, while the incoming data are received + * into rxBuf. To save memory space, txBuf and rxBuf can be assigned to the same + * buffer location. At the beginning of the transfer, this buffer holds outgoing + * data. At the end of the transfer, the outgoing data are overwritten and + * the buffer holds the received SPI data. + * + * ## Polling SPI transfers # + * When used in blocking mode small SPI transfers are can be done by polling + * the peripheral & sending data frame-by-frame. A controller device can perform + * the transfer immediately and return, but a peripheral will block until it + * receives the number of frames specified in the SPI_Transfer() call. + * The minDmaTransferSize field in the hardware attributes is + * the threshold; if the transaction count is below the threshold a polling + * transfer is performed; otherwise a DMA transfer is done. This is intended + * to reduce the overhead of setting up a DMA transfer to only send a few + * data frames. + * + * Notes: + * - Specifying a timeout prevents peripheral devices from using polling transfers. + * - Keep in mind that during polling transfers the current task + * is still being executed; there is no context switch to another task. + * + * # Supported Functions # + * Generic API function | API function | Description + * ----------------------|------------------------------- |------------------------------------------------------------ + * SPI_init() | SPICC26X4DMA_init() | Initialize SPI driver + * SPI_open() | SPICC26X4DMA_open() | Initialize SPI HW and set system dependencies + * SPI_close() | SPICC26X4DMA_close() | Disable SPI and UDMA HW and release system dependencies + * SPI_control() | SPICC26X4DMA_control() | Configure an already opened SPI handle + * SPI_transfer() | SPICC26X4DMA_transfer() | Start transfer from SPI + * SPI_transferCancel() | SPICC26X4DMA_transferCancel() | Cancel ongoing transfer from SPI + * + * @note All calls should go through the generic API + * + * # Unsupported Functionality # + * The SPI driver is unable to access flash memory in the address range 0x0000 - 0x2000 + * on devices based on the Cortex M33+ core (CC26X3/CC26X4) due to security constraints. + * + * ## Use Cases @anchor USE_CASES_SPI_X4 ## + * ### Basic Peripheral Mode # + * Receive 100 bytes over SPI in #SPI_MODE_BLOCKING. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Peripheral Mode With Return Partial @anchor USE_CASE_RP_X4 # + * This use case will perform a transfer in #SPI_MODE_BLOCKING until the wanted + * amount of bytes is transferred or until chip select is deasserted by the SPI + * controller. + * This SPI_transfer() call can be used when unknown amount of bytes shall + * be transferred. + *
Note: Partial return is also possible in #SPI_MODE_CALLBACK mode. + * In callback mode, partial transfers can be queued by calling SPI_transfer() + * multiple times. + *
Note: Polling transfers are not available when using return partial mode. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t rxBuf[100]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * + * // Configure the transaction + * transaction.count = 100; + * transaction.txBuf = NULL; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and initiate the partial read + * handle = SPI_open(CONFIG_SPI, ¶ms); + * + * // Enable RETURN_PARTIAL + * SPI_control(handle, SPICC26X4DMA_RETURN_PARTIAL_ENABLE, NULL); + * + * // Begin transfer + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Continuous Peripheral Transfer In #SPI_MODE_CALLBACK @anchor USE_CASE_CST_X4 # + * This use case will configure the SPI driver to transfer continuously in + * #SPI_MODE_CALLBACK, 16 bytes at the time and echoing received data after every + * 16 bytes. + * @code + * // Callback function + * static void transferCallback(SPI_Handle handle, SPI_Transaction *transaction) + * { + * // Start another transfer + * SPI_transfer(handle, transaction); + * } + * + * static void taskFxn(uintptr_t a0, uintptr_t a1) + * { + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t buf[16]; // Receive and transmit buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_PERIPHERAL; + * params.transferMode = SPI_MODE_CALLBACK; + * params.transferCallbackFxn = transferCallback; + * + * // Configure the transaction + * transaction.count = 16; + * transaction.txBuf = buf; + * transaction.rxBuf = buf; + * + * // Open the SPI and initiate the first transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * + * // Wait forever + * while(true); + * } + * @endcode + * + * ### Basic Controller Mode # + * This use case will configure a SPI controller to send the data in txBuf while receiving data to rxBuf in + * BLOCKING_MODE. + * @code + * SPI_Handle handle; + * SPI_Params params; + * SPI_Transaction transaction; + * uint8_t txBuf[] = "Hello World"; // Transmit buffer + * uint8_t rxBuf[11]; // Receive buffer + * + * // Init SPI and specify non-default parameters + * SPI_Params_init(¶ms); + * params.bitRate = 1000000; + * params.frameFormat = SPI_POL1_PHA1; + * params.mode = SPI_CONTROLLER; + * + * // Configure the transaction + * transaction.count = sizeof(txBuf); + * transaction.txBuf = txBuf; + * transaction.rxBuf = rxBuf; + * + * // Open the SPI and perform the transfer + * handle = SPI_open(CONFIG_SPI, ¶ms); + * SPI_transfer(handle, &transaction); + * @endcode + * + * ### Controller Mode With Multiple Peripherals @anchor USE_CASE_MMMS_X4 # + * This use case will configure a SPI controller to send data to one peripheral and then to another in + * BLOCKING_MODE. It is assumed that SysConfig is configured so that the two chip select + * pins have a default setting of a high output and that the #SPICC26X4DMA_HWAttrs used points + * to one of them since the SPI driver will revert to this default setting when switching the + * chip select pin. + * + * @code + * // From ti_drivers_config.c + * // Use the sysconfig settings to make sure both pins are set to HIGH when not in use + * GPIO_PinConfig gpioPinConfigs[31] = { + * ... + * GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH, // CONFIG_CSN_0 + * ... + * GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH, // CONFIG_CSN_1 + * } + * + * const SPICC26X4DMA_HWAttrs SPICC26X4DMAHWAttrs[CONFIG_SPI_COUNT] = { + * { // Use SPI0 module with default chip select on CONFIG_CSN_0 + * .baseAddr = SPI0_BASE, + * .intNum = INT_SSI0_COMB, + * .intPriority = (~0), + * .swiPriority = 0, + * .powerMngrId = PowerCC26XX_PERIPH_SSI0, + * .defaultTxBufValue = 0xFF, + * .rxChannelBitMask = 1< + */ +/* clang-format on */ +#ifndef ti_drivers_spi_SPICC26X4DMA__include +#define ti_drivers_spi_SPICC26X4DMA__include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup SPI_STATUS + * SPICC26X4DMA_STATUS_* macros are command codes only defined in the + * SPICC26X4DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add SPICC26X4DMA_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup SPI_CMD + * SPICC26X4DMA_CMD_* macros are command codes only defined in the + * SPICC26X4DMA.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/*! + * @brief Command used by SPI_control() to enable partial return + * + * Enabling this command allows SPI_transfer to return partial data if the + * controller de-asserts the CS line before the expected number of frames were + * received. This command @b arg is of type @a don't @a care and it returns + * SPI_STATUS_SUCCESS or SPI_STATUS_ERROR. + */ +#define SPICC26X4DMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) + +/*! + * @brief Command used by SPI_control() to disable partial return + * + * Disabling this command returns the SPICC26X4DMA to the default blocking + * behavior where SPI_transfer blocks until all data bytes were received. With + * this command @b arg is @a don't @a care and it returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X4DMA_CMD_RETURN_PARTIAL_DISABLE (SPI_CMD_RESERVED + 1) + +/*! + * @brief Command used by SPI_control() to re-configure chip select pin + * + * This command specifies a chip select pin in @b arg with type @c uint_least8_t. + * It always returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X4DMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) + +/*! + * @brief Command used by SPI_control() to clear the chip select pin + * + * This command @b arg should be NULL. It always returns #SPI_STATUS_SUCCESS. + */ +#define SPICC26X4DMA_CMD_CLEAR_CSN_PIN (SPI_CMD_RESERVED + 3) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * Manual start mode can only be used when in callback mode. In manual start + * mode, calls to SPI_transfer() queue the transaction but does not start the + * transfer until another control call is made with + * #SPICC26X4DMA_CMD_MANUAL_START. This allows multiple transactions to be + * queued and executed seamlessly using the DMA's ping pong mechanism. This + * mode is MANDATORY for peripherals queueing multiple short transactions. Manual + * start mode can only be enabled or disabled when no transactions are queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X4DMA_CMD_SET_MANUAL (SPI_CMD_RESERVED + 4) + +/*! + * @brief Command used by SPI_control() to disable manual start mode + * + * Manual start mode is disabled by default. Enabling and disabling manual mode + * can only be done if no transactions are currently queued. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + * + */ +#define SPICC26X4DMA_CMD_CLR_MANUAL (SPI_CMD_RESERVED + 5) + +/*! + * @brief Command used by SPI_control() to enable manual start mode + * + * This command is used with manual start mode enabled. If transactions have + * been queued and the driver is in manual mode, this command will enable the + * SPI and DMA. For controller devices, the transfer will start. For peripheral devices, + * the transfer will start when the controller initiates. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X4DMA_CMD_MANUAL_START (SPI_CMD_RESERVED + 6) + +/*! + * @brief Command used by SPI_control() to set the sample delay in controller mode + * + * This command is only used when in controller mode. After SPI_open() is called, + * the default DSAMPLE value is set as follows. + * * (bitRate < 4MHz) -> delay = 0 + * * (bitRate >= 4MHz) -> delay = 1 + * * (bitRate >= 8MHz) -> delay = 2 + * + * The sample delay is a measurement of clock cycles. In controller mode the data + * on the input pin will delay sampling by the defined clock cycles. At lower + * bitRates a delay is usually not necessary. At higher bitRates a delay may + * become necessary if the peripheral device is not keeping pace with the controller + * device. In this case, the delay can be used to ensure the controller device + * captures the data on the input pin. + * This command @b arg is of type uint8_t. + * + * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. + */ +#define SPICC26X4DMA_CMD_SET_SAMPLE_DELAY (SPI_CMD_RESERVED + 7) + +/** @}*/ + +/* BACKWARDS COMPATIBILITY */ +#define SPICC26X4DMA_RETURN_PARTIAL_ENABLE SPICC26X4DMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26X4DMA_RETURN_PARTIAL_DISABLE SPICC26X4DMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26X4DMA_SET_CSN_PIN SPICC26X4DMA_CMD_SET_CSN_PIN +/* END BACKWARDS COMPATIBILITY */ + +/*! + * @internal + * @brief + * SPI function table pointer + */ +extern const SPI_FxnTable SPICC26X4DMA_fxnTable; + +/*! + * @internal + * @brief + * SPICC26X4DMA data frame size is used to determine how to configure the + * UDMA data transfers. This field is to be only used internally. + * + * - SPICC26X4DMA_8bit: txBuf and rxBuf are arrays of uint8_t elements + * - SPICC26X4DMA_16bit: txBuf and rxBuf are arrays of uint16_t elements + */ +typedef enum +{ + SPICC26X4DMA_8bit = 0, + SPICC26X4DMA_16bit = 1 +} SPICC26X4DMA_FrameSize; + +/*! + * @internal + * @brief + * SPICC26X4DMA return partial field indicates the status of the return + * partial mode and the associated pin interrupt. This field is for internal + * use only. + */ +typedef enum +{ + SPICC26X4DMA_retPartDisabled = 0, + SPICC26X4DMA_retPartEnabledIntNotSet = 1, + SPICC26X4DMA_retPartEnabledIntSet = 2 +} SPICC26X4DMA_ReturnPartial; + +/*! + * @brief SPICC26X4DMA Hardware attributes + * + * These fields, with the exception of intPriority, + * are used by driverlib APIs and therefore must be populated by + * driverlib macro definitions. For CC26x4Ware these definitions are found in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/udma.h + * + * intPriority is the SPI peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * + * A sample structure is shown below: + * @code + * const SPICC26X4DMA_HWAttrs SPICC26X4DMAobjects[] = { + * { + * .baseAddr = SPI0_BASE, + * .intNum = INT_SPI0, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI0, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI0_RX, + * .txChannelBitMask = UDMA_CHAN_SPI0_TX, + * .picoPin = CONFIG_SPI0_POCI, + * .pociPin = CONFIG_SPI0_PICO, + * .clkPin = CONFIG_SPI0_CLK, + * .csnPin = CONFIG_SPI0_CSN + * }, + * { + * .baseAddr = SPI1_BASE, + * .intNum = INT_SPI1, + * .intPriority = ~0, + * .swiPriority = 0, + * .powerMngrId = PERIPH_SPI1, + * .defaultTxBufValue = 0, + * .rxChannelBitMask = UDMA_CHAN_SPI1_RX, + * .txChannelBitMask = UDMA_CHAN_SPI1_TX, + * .picoPin = CONFIG_SPI1_POCI, + * .pociPin = CONFIG_SPI1_PICO, + * .clkPin = CONFIG_SPI1_CLK, + * .csnPin = CONFIG_SPI1_CSN + * }, + * }; + * @endcode + */ +typedef struct +{ + /*! @brief SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26X4DMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26X4DMA Peripheral's interrupt priority. + + The CC26x4 uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! uDMA controlTable primary tx entry */ + volatile tDMAControlTable *dmaTxTableEntryPri; + /*! uDMA controlTable primary tx entry */ + volatile tDMAControlTable *dmaRxTableEntryPri; + /*! uDMA controlTable alternate tx entry */ + volatile tDMAControlTable *dmaTxTableEntryAlt; + /*! uDMA controlTable alternate rx entry */ + volatile tDMAControlTable *dmaRxTableEntryAlt; + /*! Tx PIN mux value. Can be applied to either PICO or POCI */ + int32_t txPinMux; + /*! Rx PIN mux value. Can be applied to either PICO or POCI */ + int32_t rxPinMux; + /*! CLK PIN mux value for flow control */ + int32_t clkPinMux; + /*! CSN PIN mux value for flow control */ + int32_t csnPinMux; + /*! SPI PICO pin */ + uint_least8_t picoPin; + /*! SPI POCI pin */ + uint_least8_t pociPin; + /*! SPI CLK pin */ + uint_least8_t clkPin; + /*! SPI CSN pin */ + uint_least8_t csnPin; + + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; +} SPICC26X4DMA_HWAttrs; + +/*! + * @brief SPICC26X4DMA Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + HwiP_Struct hwi; + Power_NotifyObj spiPostObj; + SwiP_Struct swi; + SemaphoreP_Struct transferComplete; + + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction *headPtr; + SPI_Transaction *tailPtr; + SPI_Transaction *completedTransfers; + UDMACC26XX_Handle udmaHandle; + + size_t framesQueued; + size_t framesTransferred; + size_t priTransferSize; + size_t altTransferSize; + + uint32_t activeChannel; + uint32_t bitRate; + uint32_t dataSize; + uint32_t transferTimeout; + uint32_t busyBit; + uint32_t dsample; + + uint16_t rxScratchBuf; + uint16_t txScratchBuf; + + SPI_TransferMode transferMode; + SPI_Mode mode; + uint8_t format; + uint_least8_t csnPin; + SPICC26X4DMA_ReturnPartial returnPartial; + bool isOpen; + bool manualStart; +} SPICC26X4DMA_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_spi_SPICC26X4DMA__include */ diff --git a/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.c b/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.c new file mode 100644 index 00000000..f4e0c8e6 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.c @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2020-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Includes */ +#include +#include +#include + +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/aon_batmon.h) +#include DeviceFamily_constructPath(driverlib/aon_event.h) + +/* Defines */ +#define BATMON_TEMPERATURE_MAX (250) +#define BATMON_TEMPERATURE_MIN (-250) +#define BATMON_TEMPERATURE_CODE_MAX 0x0000FF00 +#define BATMON_TEMPERATURE_CODE_MIN 0x00010000 +#define BATMON_TEMPERATURE_MASK_POSITIVE 0x0000FF00 +#define BATMON_TEMPERATURE_MASK_NEGATIVE 0x0001FF00 + +/* Offset to apply to all thresholds before programming the hardware. + * + * When the hardware samples the temperature sensor, the returned reading + * is drawn from a probability distribution of measurements for each true + * temperature. In order for a notification to trigger, two separate + * measurements must cross the configured threshold temperature. + * The first is initiated by the hardware in the background to check whether + * to trigger the HWI. The second is triggered by software within the HWI + * function. If the first measurement is part of the long tail of the + * distribution, it is highly probable that the second measurement will not + * cross the threshold. This is effectively a spurrious interrupt that wastes + * energy and CPU cycles. + * If we program the actual hardware registers with an additional offset, we + * effectively shift the distribution up or down such that the first measurement + * triggers on the long tail of the distribution that is DISTRIBUTION_OFFSET + * degrees away from the threshold provided by the application. The second + * measurement then has a much higher probability of crossing the threshold + * and triggering the notification and an update of the thresholds. + * + * The risk is of course that a particular chip has a compressed distribution + * where the long tail does not reach far enough to trigger the HWI with the + * offset applied. + * Additionally, the device does not sample nearly as frequently when in + * standby. + * + * Both of these risks result in a less accurate but overall more useful system. + * If the temperature keeps rising, both scenarios still cause a notification + * to trigger. Given that temperature changes are usually not instantaneous, + * this should be considered an acceptable risk. + */ +#define DISTRIBUTION_OFFSET 2 + +#define INVALID_TEMPERATURE_MAX BATMON_TEMPERATURE_MAX +#define INVALID_TEMPERATURE_MIN BATMON_TEMPERATURE_MIN + +/* Forward declarations */ +static void walkNotifyList(void); +static void setNextThresholds(void); +static void temperatureHwiFxn(uintptr_t arg0); +static void updateThresholds(int16_t thresholdHigh, int16_t thresholdLow); +static uint32_t degreesToCode(int32_t temperatureDegreesC); +static void setTempLowerLimit(int16_t thresholdLow); +static void setTempUpperLimit(int16_t thresholdHigh); +static void enableTempLowerLimit(void); +static void enableTempUpperLimit(void); +static void disableTempLowerLimit(void); +static void disableTempUpperLimit(void); +static void clearEventFlags(void); + +/* Globals */ + +/* Hwi struct for the shared batmon interrupt */ +static HwiP_Struct batmonHwi; + +/* Global list that stores all registered notifications */ +static List_List notificationList; + +/* Current threshold values. These should always reflect the state of the + * batmon registers without the need to read them out, shift down, and sign + * extend the values. + */ +static volatile int16_t currentThresholdHigh = INVALID_TEMPERATURE_MAX; +static volatile int16_t currentThresholdLow = INVALID_TEMPERATURE_MIN; + +static bool isInitialized = 0; + +extern const TemperatureCC26X2_Config TemperatureCC26X2_config; + +/* + * ======== degreesToCode ======== + */ +static uint32_t degreesToCode(int32_t temperatureDegreesC) +{ + /* Voltage dependent temp correction with 8 fractional bits */ + int32_t correctionOffset; + /* Signed byte value representing the TEMP offset slope with battery + * voltage in degrees C/V with 4 fractional bits. This must be multiplied + * by the voltage delta between the current voltage and the voltage used + * to compute this slope. + */ + int8_t voltageSlope; + int32_t temperatureCode; + + /* Typecasting voltageSlope to int8_t prior to assignment in order to make + * sure sign extension works properly. + * Using byte read (HWREGB) in order to make more efficient code since + * voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM + */ + voltageSlope = ((int8_t)HWREGB(FCFG1_BASE + FCFG1_O_MISC_TRIM)); + + /* Get the current supply voltage */ + correctionOffset = ((int32_t)HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT)); + /* The voltageSlope is measured at 3V in production test. We need to remove + * this from the current voltage to find the delta we need to apply. + * At 3V, there should be no adjustment necessary. The BATMON voltage + * measurement has 8 fractional bits. + */ + correctionOffset = correctionOffset - (3 << 8); + /* Multiply the delta with the voltageSlope. */ + correctionOffset = correctionOffset * voltageSlope; + /* Right shift by four to remove the fractional bits */ + correctionOffset = correctionOffset >> 4; + + /* Shift up and then back down to sign-extend the temperatureCode. + * Shift the temperature up by net 8 bit positions to move the integer part + * into bits 16:8. This is what the register expects and gives us 8 + * fractional bits to work with as well for voltage compensation. + */ + temperatureCode = (int32_t)((uint32_t)temperatureDegreesC << (32 - AON_BATMON_TEMP_INT_W)); + temperatureCode = temperatureCode >> (32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S); + + /* 0x80 represents the rounding factor of half the previous net shift value */ + temperatureCode = temperatureCode - 0x80; + + temperatureCode = temperatureCode + correctionOffset; + + if (temperatureDegreesC <= BATMON_TEMPERATURE_MIN) + { + temperatureCode = BATMON_TEMPERATURE_CODE_MIN; + } + else if (temperatureDegreesC >= BATMON_TEMPERATURE_MAX) + { + temperatureCode = BATMON_TEMPERATURE_CODE_MAX; + } + + if (temperatureCode < 0) + { + temperatureCode &= BATMON_TEMPERATURE_MASK_NEGATIVE; + } + else if (temperatureCode >= 0) + { + temperatureCode &= BATMON_TEMPERATURE_MASK_POSITIVE; + } + + return (uint32_t)(temperatureCode); +} + +/* + * ======== setTempLowerLimit ======== + */ +static void setTempLowerLimit(int16_t thresholdLow) +{ + uint32_t temperatureCode = degreesToCode(thresholdLow - DISTRIBUTION_OFFSET); + + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPLL) = temperatureCode; + + currentThresholdLow = thresholdLow; +} + +/* + * ======== setTempUpperLimit ======== + */ +static void setTempUpperLimit(int16_t thresholdHigh) +{ + uint32_t temperatureCode = degreesToCode(thresholdHigh + DISTRIBUTION_OFFSET); + + HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUL) = temperatureCode; + + currentThresholdHigh = thresholdHigh; +} + +/* + * ======== enableTempLowerLimit ======== + */ +static void enableTempLowerLimit(void) +{ + HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENTMASK) |= AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK; +} + +/* + * ======== enableTempUpperLimit ======== + */ +static void enableTempUpperLimit(void) +{ + HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENTMASK) |= AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK; +} + +/* + * ======== disableTempLowerLimit ======== + */ +static void disableTempLowerLimit(void) +{ + HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENTMASK) &= ~AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK; +} + +/* + * ======== disableTempUpperLimit ======== + */ +static void disableTempUpperLimit(void) +{ + HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENTMASK) &= ~AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK; +} + +/* + * ======== clearEventFlags ======== + */ +static void clearEventFlags(void) +{ + do + { + HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENT) &= AON_BATMON_EVENT_TEMP_BELOW_LL | AON_BATMON_EVENT_TEMP_OVER_UL; + } while (HWREG(AON_BATMON_BASE + AON_BATMON_O_EVENT) & + (AON_BATMON_EVENT_TEMP_BELOW_LL | AON_BATMON_EVENT_TEMP_OVER_UL)); +} + +/* + * ======== setNextThresholds ======== + */ +static void setNextThresholds(void) +{ + List_Elem *notifyLink; + int16_t nextThresholdHigh = INVALID_TEMPERATURE_MAX; + int16_t nextThresholdLow = INVALID_TEMPERATURE_MIN; + uint32_t key; + + key = HwiP_disable(); + + /* Starting with the head of the list, keep track of the smallest high + * threshold and largest low threshold. + */ + notifyLink = List_head(¬ificationList); + + while (notifyLink != NULL) + { + Temperature_NotifyObj *notifyObject = (Temperature_NotifyObj *)notifyLink; + + nextThresholdHigh = Math_MIN(nextThresholdHigh, notifyObject->thresholdHigh); + nextThresholdLow = Math_MAX(nextThresholdLow, notifyObject->thresholdLow); + + notifyLink = List_next(notifyLink); + } + + /* Now that we have found the next upper and lower thresholds, set them. + * These could be INVALID_TEMPERATURE_MAX and/or INVALID_TEMPERATURE_MIN + * if the list is empty or only high/low notifications were registered. + */ + updateThresholds(nextThresholdHigh, nextThresholdLow); + + HwiP_restore(key); +} + +/* + * ======== walkNotifyList ======== + */ +static void walkNotifyList(void) +{ + List_Elem *notifyLink = List_head(¬ificationList); + int16_t currentTemperature = Temperature_getTemperature(); + + /* If the notification list is empty, the head pointer will be + * NULL and the while loop will never execute the statement. + */ + while (notifyLink != NULL) + { + Temperature_NotifyObj *notifyObject = (Temperature_NotifyObj *)notifyLink; + + /* Buffer the next link in case the notification triggers. + * Without buffering, we might skip list entries if the + * notifyObject is freed or reregistered and the notifyObject->link.next + * pointer is altered. + */ + List_Elem *notifyLinkNext = List_next(notifyLink); + + /* If the current temperature is below this notification's low + * threshold or above its high threshold, remove it from the list and + * call the callback fxn + */ + if (currentTemperature <= notifyObject->thresholdLow || currentTemperature >= notifyObject->thresholdHigh) + { + + /* Choose the threshold to provide to the notifyFxn based on the + * thresholds and the current temperature. + */ + int16_t threshold = (currentTemperature <= notifyObject->thresholdLow) ? notifyObject->thresholdLow + : notifyObject->thresholdHigh; + + List_remove(¬ificationList, notifyLink); + notifyObject->isRegistered = false; + + notifyObject->notifyFxn(currentTemperature, threshold, notifyObject->clientArg, notifyObject); + } + + notifyLink = notifyLinkNext; + } +} + +/* + * ======== updateThresholds ======== + */ +static void updateThresholds(int16_t thresholdHigh, int16_t thresholdLow) +{ + if (thresholdHigh < currentThresholdHigh) + { + setTempUpperLimit(thresholdHigh); + enableTempUpperLimit(); + } + + if (thresholdLow > currentThresholdLow) + { + setTempLowerLimit(thresholdLow); + enableTempLowerLimit(); + } +} + +/* + * ======== temperatureHwiFxn ======== + * + * Batmon interrupt triggered on high or low temperature event + */ +static void temperatureHwiFxn(uintptr_t arg0) +{ + + setTempUpperLimit(INVALID_TEMPERATURE_MAX); + disableTempUpperLimit(); + + setTempLowerLimit(INVALID_TEMPERATURE_MIN); + disableTempLowerLimit(); + + /* Walk the notification list and issue any callbacks that have triggered + * at the current temperature. + */ + walkNotifyList(); + + /* Walk the queue another time to find and set the next set of thresholds. + * This is faster than making even one extra access to AON_BATMON. + */ + setNextThresholds(); + + /* Clear event flags. They may not immediately clear properly. */ + clearEventFlags(); + + IntPendClear(INT_BATMON_COMB); +} + +/* + * ======== Temperature_init ======== + */ +void Temperature_init(void) +{ + uint32_t key; + + key = HwiP_disable(); + + if (isInitialized == false) + { + /* Initialise the batmon hwi. The temperature sensor shares this + * interrupt with the battery voltage monitoring events. + */ + HwiP_Params hwiParams; + HwiP_Params_init(&hwiParams); + hwiParams.priority = TemperatureCC26X2_config.intPriority; + hwiParams.enableInt = true; + HwiP_construct(&batmonHwi, INT_BATMON_COMB, temperatureHwiFxn, &hwiParams); + + disableTempUpperLimit(); + disableTempLowerLimit(); + + AONBatMonEnable(); + + /* Set the combined BATMON interrupt as a wakeup source. This means the + * BATMON can bring the device out of standby when an event is + * triggered. + * We use WU2 since WU0 is the RTC and WU1 is a pad (GPIO) event. + */ + AONEventMcuWakeUpSet(AON_EVENT_MCU_WU2, AON_EVENT_BATMON_COMBINED); + + /* Wait until first measurement is ready to prevent + * Temperature_getTemperature from returning an invalid value + */ + while (AONBatMonNewTempMeasureReady() == false) {} + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== Temperature_getTemperature ======== + */ +int16_t Temperature_getTemperature(void) +{ + /* The temperature on CC13X2/CC26X2 is stored in a 32-bit register + * containing a 9-bit signed integer part and a 2-bit unsigned fractional + * part. + * The driverlib fxn handles this as well as compensating for the battery + * voltage which also affects the measured temperature. + */ + int16_t currentTemperature = AONBatMonTemperatureGetDegC(); + + return currentTemperature; +} + +/* + * ======== Temperature_registerNotifyHigh ======== + */ +int_fast16_t Temperature_registerNotifyHigh(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = INVALID_TEMPERATURE_MIN; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_registerNotifyLow ======== + */ +int_fast16_t Temperature_registerNotifyLow(Temperature_NotifyObj *notifyObject, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = INVALID_TEMPERATURE_MAX; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_registerNotifyRange ======== + */ +int_fast16_t Temperature_registerNotifyRange(Temperature_NotifyObj *notifyObject, + int16_t thresholdHigh, + int16_t thresholdLow, + Temperature_NotifyFxn notifyFxn, + uintptr_t clientArg) +{ + uint32_t key; + + key = HwiP_disable(); + + notifyObject->thresholdHigh = thresholdHigh; + notifyObject->thresholdLow = thresholdLow; + notifyObject->notifyFxn = notifyFxn; + notifyObject->clientArg = clientArg; + + if (notifyObject->isRegistered == false) + { + /* Add the notification to the end of the list. + * There is the implicit assumption that the notification is not already + * in the list. Otherwise the list linkage will be corrupted. + */ + List_put(¬ificationList, ¬ifyObject->link); + + notifyObject->isRegistered = true; + } + + updateThresholds(notifyObject->thresholdHigh, notifyObject->thresholdLow); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} + +/* + * ======== Temperature_unregisterNotify ======== + */ +int_fast16_t Temperature_unregisterNotify(Temperature_NotifyObj *notifyObject) +{ + uint32_t key; + + key = HwiP_disable(); + + if (notifyObject->isRegistered == true) + { + /* Remove the notification from the list */ + List_remove(¬ificationList, &(notifyObject->link)); + + notifyObject->isRegistered = false; + } + + /* Find the next set of thresholds and update the registers */ + setNextThresholds(); + + HwiP_restore(key); + + return Temperature_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.h b/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.h new file mode 100644 index 00000000..bd80462e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/temperature/TemperatureCC26X2.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TemperatureCC26X2.h + * + * @brief Temperature driver implementation for the CC26X2 family + * + * The temperature driver on CC26X2 is a part of the battery monitoring + * system in AON (always on). It periodically takes measurements of the + * temperature of the chip and will issue interrupts if the configured + * upper limit or lower limit is crossed. + * + * # Standby Power Mode Behavior # + * The temperature measurement is active while in standby power mode as well. + * The interrupt used by the temperature module is capable of bringing the + * device out of standby and into active mode to handle it. That means that + * an application will not miss a change in temperature just because the device + * has transitioned to standby power mode. + * While in standby, the temperature will only be sampled during a VDDR + * recharge pulse. This means that the sampling frequency in standby will be + * determined by the temperature as leakage increases with temperature and + * requires more frequent recharging of VDDR. + * + * # Measurement Confidence Bounds + * There is an inherent inaccuracy in the temperature measurements reported + * by the device for any given chip temperature. This inaccuracy varies + * by chip. + * In order to set accurate threshold values and act upon provided + * temperatures, the following table provides a 99% confidence interval for + * the upper and lower bounds of the measured temperature by true + * temperature. These figures are given across the range of manufacturing + * variances. + * + * | Ambient Temperature | -40 | -30 | -20 | -10 | 0 | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 | 110 | 120 | + * |---------------------|-----|-----|-----|-----|----|----|----|----|----|----|----|----|----|----|-----|-----|-----| + * | Upper | -28 | -20 | -12 | -3 | 7 | 17 | 26 | 36 | 46 | 56 | 65 | 75 | 85 | 95 | 105 | 115 | 125 | + * | Lower | -45 | -36 | -26 | -16 | -5 | 4 | 14 | 24 | 35 | 45 | 54 | 65 | 75 | 85 | 94 | 104 | 113 | + * + * # Measurement-to-Measurement Variations # + * For each chip, there is a distribution of temperature readings each + * measurement will yield for each true temperature. This means that if a + * notification threshold close to the current temperature is chosen, the + * hardware may cause an interrupt only for the driver to read out the + * temperature again with a value that does not cross the set threshold. + * In this case, the driver will not issue a notification. This does cost + * cpu cycles and energy though. + * + * Because of this measurement-to-measurement variability, it is not + * recommended to set a threshold closer than 5 degrees to the current + * temperature when registering a notification. + */ + +#ifndef ti_drivers_temperature_TemperatureCC26X2__include +#define ti_drivers_temperature_TemperatureCC26X2__include + +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Temperature driver configuration struct for CC26X2 + * + * This struct globally controls configuration settings for the CC26X2 + * Temperature driver. + * + * The CC26X2 Temperature driver implementation links against a structure + * of this type named TemperatureCC26X2_config. + * + * This structure must be allocated and configured by the application. If + * SysConfig is used, this struct will be automatically created when the + * Temperature module is used in SysConfig. + */ +typedef struct +{ + /*! @brief Temperature sensor's interrupt priority. + * + * The interrupt line is shared between the temperature sensor and the + * battery voltage monitor on CC26X2 + * + * The CC26X2 uses three of the priority bits, meaning ~0 has the same + * effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + * interrupts, thus invalidating the critical sections. + */ + uint8_t intPriority; +} TemperatureCC26X2_Config; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_temperature_TemperatureCC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.c b/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.c new file mode 100644 index 00000000..f3a02d48 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SecureCallback.c ======== + */ +#include +#include + +#include "SecureCallback.h" + +/* Driverlib includes*/ +#include +#include DeviceFamily_constructPath(driverlib/interrupt.h) + +static HwiP_Struct hwipStruct; +static HwiP_Handle hwipHandle; + +/* This list is only defined on the user application, and will be optimized out + * of the secure image + */ +static List_List allCallbackObjects; + +/* This object will be provided by sysconfig both the secure and application + * images, and must have the same interrupt number configured in both cases + */ +extern const SecureCallback_Config SecureCallback_config; + +/* + * ======== SecureCallback_hwi ======== + */ +static void SecureCallback_hwi(uintptr_t arg) +{ + SecureCallback_Object *element = (SecureCallback_Object *)List_head(&allCallbackObjects); + while (element != NULL) + { + if (element->pending == true && element->fxn != NULL) + { + element->pending = false; + element->fxn(element->arg); + } + element = (SecureCallback_Object *)List_next((List_Elem *)element); + } +} + +/* + * ======== SecureCallback_init ======== + */ +void SecureCallback_init() +{ + HwiP_Params hwiParams; + hwiParams.priority = SecureCallback_config.intPriority; + hwiParams.enableInt = true; + + List_clearList(&allCallbackObjects); + hwipHandle = HwiP_construct(&hwipStruct, SecureCallback_config.intNumber, SecureCallback_hwi, &hwiParams); + + /* No recovery mechanism for failure to create HwiP */ + if (hwipHandle == NULL) + { + while (1) {} + } +} + +/* + * ======== SecureCallback_construct ======== + */ +SecureCallback_Handle SecureCallback_construct(SecureCallback_Object *object, SecureCallback_FuncPtr fxn, uintptr_t arg) +{ + List_put(&allCallbackObjects, (List_Elem *)object); + object->pending = false; + object->arg = arg; + object->fxn = fxn; + return object; +} + +/* + * ======== SecureCallback_destruct ======== + */ +void SecureCallback_destruct(SecureCallback_Object *object) +{ + List_remove(&allCallbackObjects, (List_Elem *)object); +} + +/* + * ======== SecureCallback_post ======== + */ +void SecureCallback_post(SecureCallback_Handle handle) +{ + handle->pending = true; + IntPendSet(SecureCallback_config.intNumber); +} diff --git a/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.h b/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.h new file mode 100644 index 00000000..1c626146 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/tfm/SecureCallback.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== SecureCallback.h ======== + */ + +#ifndef ti_drivers_tfm_SecureCallback__include +#define ti_drivers_tfm_SecureCallback__include + +#include +#include + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +typedef void (*SecureCallback_FuncPtr)(uintptr_t arg); + +typedef struct SecureCallback_Object +{ + List_Elem elem; + uintptr_t arg; + bool pending; + SecureCallback_FuncPtr fxn; +} SecureCallback_Object; + +typedef SecureCallback_Object *SecureCallback_Handle; + +typedef struct SecureCallback_Config +{ + uint32_t intNumber; + uint8_t intPriority; +} SecureCallback_Config; + +/*! + * @brief Initialize SecureCallback driver + * + * @note This API is only available to non-secure code. Must be called once + * prior to invoking any other SecureCallback APIs. + */ +void SecureCallback_init(void); + +/*! + * @brief Construct a callback object and adds it to the servicing list. + * + * @note This API is only available to non-secure code. + * + * @param[in] object A pointer to a #SecureCallback_Object structure. + * @param[in] fxn A pointer to this object's callback function. + * @param[in] arg A uint argument passed to the callback function. + */ +SecureCallback_Handle SecureCallback_construct(SecureCallback_Object *object, + SecureCallback_FuncPtr fxn, + uintptr_t arg); + +/*! + * @brief Destruct a callback object, removing it from the servicing list. + * + * @note This API is only available to non-secure code. + * + * @param[in] object A pointer to a #SecureCallback_Object structure. + */ +void SecureCallback_destruct(SecureCallback_Object *object); + +/*! + * @brief Triggers the dispatcher targeting the specified callback. + * + * @note This API is available to both non-secure and secure code. + * + * @param[in] handle A #SecureCallback_Handle pointer. + * + * @pre The callback object must have been created by #SecureCallback_construct(). + */ +void SecureCallback_post(SecureCallback_Handle handle); + +#if defined(__cplusplus) +} +#endif + +#endif /* ti_drivers_tfm_SecureCallback__include */ diff --git a/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.c b/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.c new file mode 100644 index 00000000..33651cd1 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.c @@ -0,0 +1,804 @@ +/* + * Copyright (c) 2015-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file GPTimerCC26XX.c + * @brief CC26XX/CC13XX driver implementation for GPTimer peripheral + * + * + ******************************************************************************* + */ + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(driverlib/timer.h) + +/* GPTimer configuration array from application */ +extern const GPTimerCC26XX_Config GPTimerCC26XX_config[]; + +/* Register masks used by GPTimerCC26XX_resetHw */ +#define GPT_CTL_MASK (GPT_CTL_TASTALL_M | GPT_CTL_TAEVENT_M | GPT_CTL_TAPWML_M) + +/* GPTimerCC26XX internal functions */ +static void GPTimerCC26XX_initHw(GPTimerCC26XX_Handle handle, const GPTimerCC26XX_Params *params); +static void GPTimerCC26XX_resetHw(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXThreadsafeConstraintClr(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXThreadsafeConstraintSet(GPTimerCC26XX_Handle handle); +static void GPTimerCC26XXHwiFxn(uintptr_t a0); +static void GPTimerCC26XXSetLoadMatch(GPTimerCC26XX_Handle handle, + GPTimerCC26XX_Value loadMatchVal, + uint32_t regPre, + uint32_t regLoadMatch); +static GPTimerCC26XX_Value GPTimerCC26XX_getTimerValue(GPTimerCC26XX_Handle handle, uint32_t reg); + +/* GPTimerCC26XX temporary internal functions. + Will be removed once they are added to driverlib + */ +static inline void TimerSetConfig(uint32_t ui32Base, uint32_t ui32Config); +static inline void TimerSetMode(uint32_t ui32Base, uint32_t timer, uint32_t mode); + +/* Lookup table definition for interfacing driverlib and register fields. + Used to simplify code and to easily look up register fields as several fields + are not symmetric across timer A and timer B registers (interrupts & dma) + */ +typedef struct GPTimerCC26XX_LUT +{ + uint16_t map; /* Timer argument in driverlib (TIMER_A / TIMER_B) */ + uint16_t shift; /* Bit shift for registers shared between GPT_A / GPT_B */ + uint16_t offset; /* Byte offset for registers sequentially in memory map for GPT_A/GPT_B */ + uint16_t interrupts[GPT_NUM_INTS]; /* Interrupt bitfields for GPTA/B. Order must match GPTimerCC26XX_Interrupt */ +} const GPTimerCC26XX_LUT; + +/* Lookup table definition for interfacing driverlib and register fields. */ +static const GPTimerCC26XX_LUT GPT_LUT[GPT_PARTS_COUNT] = { + { + .map = TIMER_A, + .shift = 0, + .offset = 0, + .interrupts = {GPT_MIS_TATOMIS, GPT_MIS_CAMMIS, GPT_MIS_CAEMIS, GPT_MIS_TAMMIS}, + }, + { + .map = TIMER_B, + .shift = 8, + .offset = 4, + .interrupts = {GPT_MIS_TBTOMIS, GPT_MIS_CBMMIS, GPT_MIS_CBEMIS, GPT_MIS_TBMMIS}, + }, +}; + +/* Default GPTimer parameters */ +static const GPTimerCC26XX_Params GPT_DefaultParams = { + .width = GPT_CONFIG_32BIT, + .mode = GPT_MODE_PERIODIC, + .matchTiming = GPTimerCC26XX_SET_MATCH_NEXT_CLOCK, + .direction = GPTimerCC26XX_DIRECTION_UP, + .debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF, +}; + +/*! + * @brief Generic bit vector to lookup table vector implementation + * + * Parses generic lookup table and checks whether inputs exists in lookup table. + * + * @param pLookup pointer to look-up table + * @param inputVector Input vector + * @param length Number of bits in lookup table + * + * @return A bit vector containing set fields in lookup table + */ +static uint16_t GPTimerCC26XXLookupMask(const uint16_t *pLookup, uint16_t inputVector, uint8_t length) +{ + uint16_t maskLookup = 0; + uint32_t i; + /* Fetch data from lookup table */ + for (i = 0; i < length; i++) + { + /* Check if current index of lookup table is in input vector */ + if (inputVector & pLookup[i]) + { + /* Add vector input to looked up mask. */ + maskLookup |= 1 << i; + } + } + return maskLookup; +} + +/*! + * @brief Generic lookup table to bit vector implementation + * + * Parses input vector and checks which input fields are set + * + * @param pLookup pointer to look-up table + * @param inputVector Input vector + * @param length Number of bits in lookup table + * + * @return A bit vector mapped from lookup table + */ +static uint16_t GPTimerCC26XXReverseLookupMask(const uint16_t *pLookup, uint16_t inputVector, uint8_t length) +{ + uint16_t revMaskLookup = 0; + uint32_t i; + for (i = 0; i < length; i++) + { + /* Check if current index is set in input vector */ + if (inputVector & (1 << i)) + { + /* Add data from lookup table */ + revMaskLookup |= pLookup[i]; + } + } + return revMaskLookup; +} + +/*! + * @brief Function to initialize the GPTimerCC26XX_Params struct to default + * values + * + * @param params An pointer to GPTimerCC26XX_Params structure for + * initialization + * + * Defaults values are: + * Timer width : 32 bits, + * Timer mode : Periodic mode counting upwards + * Timer debug stall mode: Disabled + */ +void GPTimerCC26XX_Params_init(GPTimerCC26XX_Params *params) +{ + *params = GPT_DefaultParams; +} + +/*! + * @brief This function opens the given GPTimer peripheral. It will set a + * dependency on the timer, configure the timer mode and set timer + * as open. If params is NULL default values will be used. + * + * @return A GPTimerCC26XX_Handle on success or NULL on error or if timer is + * already open. If NULL is returned further GPTimer API calls will + * result in undefined behaviour. + * + * @sa GPTimerCC26XX_close() + */ +GPTimerCC26XX_Handle GPTimerCC26XX_open(unsigned int index, const GPTimerCC26XX_Params *params) +{ + unsigned int key; + GPTimerCC26XX_Handle handle = (GPTimerCC26XX_Handle)&GPTimerCC26XX_config[index]; + + /* Get the pointer to the object and hwAttrs and timer*/ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + /* + * Input argument checks + */ + + /* Fail if no params supplied */ + if (params == NULL) + { + DebugP_log1("Timer:(%p): No params supplied, using default.", hwAttrs->baseAddr); + params = &GPT_DefaultParams; + } + + if (params->width == GPT_CONFIG_32BIT) + { + /* Fail if invalid combination of mode and configuration + 32-bit config are only valid for periodic / oneshot modes */ + if (params->mode != GPT_MODE_ONESHOT_UP && params->mode != GPT_MODE_PERIODIC_UP) + { + DebugP_log1("Timer:(%p): Invalid combination of mode and configuration", hwAttrs->baseAddr); + return (NULL); + } + /* Fail if invalid combination of timer unit and configuration. + 32-bit config is only valid in combination with GPT A */ + if (handle->timerPart != GPT_A) + { + DebugP_log1("Timer:(%p): Invalid combination of configuration and timer unit", hwAttrs->baseAddr); + return (NULL); + } + } + + /* + * Check if Timer is already opened + */ + + /* Disable preemption while checking */ + key = HwiP_disable(); + + bool isOpen; + /* If trying to open a 32-bit mode timer then both A and B must be available */ + if (params->width == GPT_CONFIG_32BIT) + { + /* Timer already opened if one unit opened */ + isOpen = object->isOpen[GPT_A] | object->isOpen[GPT_B]; + } + else + { + isOpen = object->isOpen[handle->timerPart]; + } + /* Fail if corresponding timer is already open or if one of the two + units needed is taken for 32-bit mode */ + if (isOpen) + { + HwiP_restore(key); + DebugP_log2("Timer:(%p), Unit: (%u): Already in use.", hwAttrs->baseAddr, handle->timerPart); + return NULL; + } + + /* + * Open timer + */ + if (params->width == GPT_CONFIG_32BIT) + { + object->isOpen[GPT_A] = true; + object->isOpen[GPT_B] = true; + } + else + { + object->isOpen[handle->timerPart] = true; + } + /* Restore preemption again */ + HwiP_restore(key); + + /* Configure timer object */ + object->width = params->width; + + /* Register power dependency - i.e. power up and enable clock for GPTimer. + If both GPT_A and GPT_B is used then two dependencies will be set on GPTimer */ + Power_setDependency(hwAttrs->powerMngrId); + + /* Initialize HW */ + GPTimerCC26XX_initHw(handle, params); + + return handle; +} + +/*! + * @brief This function closes an opened GPTimer peripheral defined by the + * handle. It will remove the dependency on the timer and write all + * configured timer registers to its default values. Timer must be + * stopped beforing closing it. + * + * @sa GPTimerCC26XX_stop() + * @sa GPTimerCC26XX_close() + */ +void GPTimerCC26XX_close(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + /* Stop and reset timer */ + GPTimerCC26XX_resetHw(handle); + + /* Release dependency for timer */ + Power_releaseDependency(hwAttrs->powerMngrId); + + /* Mark the Timer unit as available */ + uint32_t key = HwiP_disable(); + + /* Close Timer(s) */ + if (object->width == GPT_CONFIG_32BIT) + { + object->isOpen[GPT_A] = false; + object->isOpen[GPT_B] = false; + } + else + { + object->isOpen[handle->timerPart] = false; + } + HwiP_restore(key); +} + +/*! + * @brief This function will start a GPTimer defined by the handle. + * @sa GPTimerCC26XX_stop() + */ +void GPTimerCC26XX_start(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Enable timer */ + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerEnable(hwAttrs->baseAddr, timer); + + /* Set constraint to disallow standby while running */ + GPTimerCC26XXThreadsafeConstraintSet(handle); +} + +/*! + * @brief This function will stop a running GPTimer defined by the handle + * @sa GPTimerCC26XX_start() + */ +void GPTimerCC26XX_stop(GPTimerCC26XX_Handle handle) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Disable timer */ + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerDisable(hwAttrs->baseAddr, timer); + + /* Clear constraint to allow standby again */ + GPTimerCC26XXThreadsafeConstraintClr(handle); +} + +/*! + * @brief Shared code to be used by GPTimerCC26XX_setLoadValue / GPTimerCC26XX_setMatchValue + * Sets load/match values using input value and register offset for + * prescaler and load/match register + * Functions calling this should specifiy which the register offset + * within the module base to the corresponding timer A register. + */ +static void GPTimerCC26XXSetLoadMatch(GPTimerCC26XX_Handle handle, + GPTimerCC26XX_Value loadMatchVal, + uint32_t regPre, + uint32_t regLoadMatch) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + /* Split value into correct timer and prescaler register for 16 bit modes. */ + if (object->width == GPT_CONFIG_16BIT) + { + /* Upper byte is used by prescaler */ + uint8_t prescaleValue = 0xFF & (loadMatchVal >> 16); + /* Discard upper byte (24 bits max) */ + loadMatchVal &= 0xFFFF; + + /* Set prescale value */ + HWREG(hwAttrs->baseAddr + offset + regPre) = prescaleValue; + } + + /* Set load / match value */ + HWREG(hwAttrs->baseAddr + offset + regLoadMatch) = loadMatchVal; +} + +/*! + * @brief Set GPTimer load value. For 32-bit configuration all 32 bits can + * be used. For split mode / 16-bit mode maximum value is 24 bits. + * Function concatenates prescaler functionality automatically + */ +void GPTimerCC26XX_setLoadValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadValue) +{ + GPTimerCC26XXSetLoadMatch(handle, loadValue, GPT_O_TAPR, GPT_O_TAILR); +} + +/*! + * @brief Set GPTimer match value. For 32-bit configuration all 32 bits can + * be used. For split mode / 16-bit mode maximum value is 24 bits. + * Function concatenates prescaler functionality automatically + */ +void GPTimerCC26XX_setMatchValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value matchValue) +{ + GPTimerCC26XXSetLoadMatch(handle, matchValue, GPT_O_TAPMR, GPT_O_TAMATCHR); +} + +/*! + * @brief Function to set which input event edge the GPTimer capture should + * use. Applies to edge-count and edge-time modes + * be called while GPTimer is running. + */ +void GPTimerCC26XX_setCaptureEdge(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Edge event) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + uint32_t shift = GPT_LUT[handle->timerPart].shift; + + /* Disable interrupts during RMW operation */ + uint32_t key = HwiP_disable(); + + uint32_t ctl = HWREG(hwAttrs->baseAddr + GPT_O_CTL); + /* Clear old setting */ + ctl &= ~(GPT_CTL_TAEVENT_M << shift); + /* Apply new setting */ + HWREG(hwAttrs->baseAddr + GPT_O_CTL) = ctl | (event << shift); + /* Restore HW interrupts */ + HwiP_restore(key); +} + +/*! + * @brief Shared code used to retrieve timer values by + * GPTimerCC26XX_getFreeRunValue and GPTimerCC26XX_getValue + * Functions calling this should specifiy which the register offset + * within the module base to the corresponding timer A register. + */ +static GPTimerCC26XX_Value GPTimerCC26XX_getTimerValue(GPTimerCC26XX_Handle handle, uint32_t reg) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + uint32_t value = HWREG(hwAttrs->baseAddr + offset + reg); + + /* Correct for 16-bit mode (remove bits 31:24) + Supported 16-bit modes uses prescaler as timer extension only. + In 16-bit mode, current prescaler value is found in bits 23:16 of the timer value register + */ + + if (object->width == GPT_CONFIG_16BIT) + { + /* Discard any upper byte */ + value = value & 0xFFFFFF; + } + return (GPTimerCC26XX_Value)value; +} + +/*! + * @brief Retrieve current free-running value from GPTimer + * In 16-bit modes the function will return a 24-bit word where the + * 8-bit prescaler value is included. + */ +GPTimerCC26XX_Value GPTimerCC26XX_getFreeRunValue(GPTimerCC26XX_Handle handle) +{ + return GPTimerCC26XX_getTimerValue(handle, GPT_O_TAV); +} + +/*! + * @brief Retrieve the current value of timer + * This returns the value of the timer in all modes except for + * input edge count and input edge time mode. + * In edge count mode, this register contains the number of edges that + * have occurred. In input edge time, this register contains the + * timer value at which the last edge event took place. + * In 16-bit modes the function will return a 24-bit word where the + * 8-bit prescaler value is included. + */ +GPTimerCC26XX_Value GPTimerCC26XX_getValue(GPTimerCC26XX_Handle handle) +{ + return GPTimerCC26XX_getTimerValue(handle, GPT_O_TAR); +} + +/*! + * @brief Register interrupts for timer handle. + * This function must only be called once after opening a timer. + * Interrupts should be unregistered again before closing + * the timer resource. + */ +void GPTimerCC26XX_registerInterrupt(GPTimerCC26XX_Handle handle, + GPTimerCC26XX_HwiFxn callback, + GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + /* Store callback function */ + object->hwiCallbackFxn[handle->timerPart] = callback; + /* Construct RTOS HWI */ + HwiP_Struct *pHwi = &object->hwi[handle->timerPart]; + HwiP_Params hp; + HwiP_Params_init(&hp); + hp.arg = (uintptr_t)handle; + hp.enableInt = true; + hp.priority = hwAttrs->intPriority; + HwiP_construct(pHwi, hwAttrs->intNum, GPTimerCC26XXHwiFxn, &hp); + + GPTimerCC26XX_enableInterrupt(handle, intMask); +} + +/*! + * @brief Destruct interrupt for timer handle. + * This function must only be called once after opening a timer and + * should not be called before calling GPTimerCC26XX_registerInterrupt + */ +void GPTimerCC26XX_unregisterInterrupt(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + uint32_t ui32Base = hwAttrs->baseAddr; + uint32_t timer = GPT_LUT[handle->timerPart].map; + + /* Disable all timer unit interrupts, use "timer" variable as mask */ + TimerIntDisable(ui32Base, timer); + + /* Destroy callback function */ + object->hwiCallbackFxn[handle->timerPart] = NULL; + /* Destruct HWI */ + HwiP_Struct *pHwi = &object->hwi[handle->timerPart]; + HwiP_destruct(pHwi); +} + +/*! + * @brief Enable interrupt source for current GPTimer unit. CPU interrupt + * for timer will not be enabled before calling + * GPTimerCC26XX_registerInterrupt + */ +void GPTimerCC26XX_enableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + /* Interrupt registers are shared by TA and TB but bit fields are not symmetric + Fetch mask from lookup table.*/ + uint32_t intMaskLookup = GPTimerCC26XXReverseLookupMask(GPT_LUT[handle->timerPart].interrupts, + intMask, + GPT_NUM_INTS); + + /* Enable interrupts in timer unit */ + TimerIntEnable(ui32Base, intMaskLookup); +} + +/*! + * @brief Disable interrupt source for current GPTimer unit. CPU interrupt + * for timer will not be disabled before calling GPTimerCC26XX_unregisterInterrupt + */ +void GPTimerCC26XX_disableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask intMask) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + /* Interrupt registers are shared by TA and TB but bit fields are not symmetric + Fetch mask from lookup table. */ + uint32_t intMaskLookup = GPTimerCC26XXReverseLookupMask(GPT_LUT[handle->timerPart].interrupts, + intMask, + GPT_NUM_INTS); + + /* Enable interrupts in timer unit */ + TimerIntDisable(ui32Base, intMaskLookup); +} + +static void GPTimerCC26XX_initHw(GPTimerCC26XX_Handle handle, const GPTimerCC26XX_Params *params) +{ + /* Get the pointer to the object and hwAttrs */ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object const *object = handle->object; + + TimerSetConfig(hwAttrs->baseAddr, object->width); + uint32_t timer = GPT_LUT[handle->timerPart].map; + + uint32_t mode = (uint32_t)params->mode; + + if (params->matchTiming == GPTimerCC26XX_SET_MATCH_ON_TIMEOUT) + { + /* Same bit position is also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TAMRSU_TOUPDATE; + } + else + { + /* Same bit position is also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TAMRSU_CYCLEUPDATE; + } + + if (params->direction == GPTimerCC26XX_DIRECTION_UP) + { + /* Same bit position also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TACDIR_UP; + } + else + { + /* Same bit position also valid for timer B in the TBMR register. */ + mode |= GPT_TAMR_TACDIR_DOWN; + } + + TimerSetMode(hwAttrs->baseAddr, timer, mode); + + GPTimerCC26XX_configureDebugStall(handle, params->debugStallMode); +} + +/*! + * @brief Restore GPTimer unit registers back to reset values. + * Needed since module does not have reset functionality. + */ +static void GPTimerCC26XX_resetHw(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t ui32Base = hwAttrs->baseAddr; + + uint32_t timer = GPT_LUT[handle->timerPart].map; + uint32_t regMask; + /* Some registers are shared by TA and TB. + Shift bit fields by 1 byte for timer B. */ + uint32_t shift = GPT_LUT[handle->timerPart].shift; + /* Some registers are offset by one word (4 bytes) for Timer B. */ + uint32_t offset = GPT_LUT[handle->timerPart].offset; + + /* Disable timer before configuring */ + TimerDisable(ui32Base, timer); + + /* Reset control regs for timer N (CTL) */ + regMask = ~(GPT_CTL_MASK << shift); + HWREG(ui32Base + GPT_O_CTL) &= regMask; + + /* Reset interrupt mask for Timer N (IMR). + Equivalent to TimerIntDisable(ui32Base, regMask) */ + regMask = 0; + uint8_t i; + for (i = 0; i < GPT_NUM_INTS; i++) + { + regMask |= (uint32_t)(GPT_LUT[handle->timerPart].interrupts[i]); + } + HWREG(ui32Base + GPT_O_IMR) &= ~regMask; + + /* Clear interrupts for Timer N ( ICLR). Same regMask as GPT_O_IMR. + Equivalent to TimerIntClear(ui32Base, regMask) */ + HWREG(ui32Base + GPT_O_ICLR) = regMask; + + /* Reset load register for timer N. + Equivalent to TimerLoadSet(ui32Base, timer, 0xFFFFFFF) */ + HWREG(ui32Base + offset + GPT_O_TAILR) = 0xFFFFFFFF; + + /* Reset match register for timer N. + Equivalent to TimerMatchSet(ui32Base, timer, 0xFFFFFFFF) */ + HWREG(ui32Base + offset + GPT_O_TAMATCHR) = 0xFFFFFFFF; + + /* Reset value register for timer N. + No equivalent function in driverlib. */ + HWREG(ui32Base + offset + GPT_O_TAV) = 0xFFFFFFFF; + + /* Reset pre-scale register for timer N. + Equivalent to TimerPrescaleSet(ui32Base, timer, 0) */ + HWREG(ui32Base + offset + GPT_O_TAPR) = 0; + + /* Reset pre-scale match register for timer N. + Equivalent to TimerPrescaleMatchSet(ui32Base, timer, 0) */ + HWREG(ui32Base + offset + GPT_O_TAPMR) = 0; +} + +/*! + * @brief GPTimer interrupt handler - Clears corresponding interrupt(s) + * and calls callback function with handle and bitmask argument + * as given in implementation header file. + */ +static void GPTimerCC26XXHwiFxn(uintptr_t a0) +{ + GPTimerCC26XX_Handle handle = (GPTimerCC26XX_Handle)a0; + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + GPTimerCC26XX_Object *object = handle->object; + + GPTimerCC26XX_HwiFxn callbackFxn = object->hwiCallbackFxn[handle->timerPart]; + uint32_t timer = GPT_LUT[handle->timerPart].map; + + /* Full width raw interrupt status */ + uint32_t interrupts = HWREG(hwAttrs->baseAddr + GPT_O_MIS); + /* Interrupt mask to clear (byte 0 or 1) */ + uint32_t interruptClr = timer & interrupts; + /* Clear interrupts */ + HWREG(hwAttrs->baseAddr + GPT_O_ICLR) = interruptClr; + + /* Interrupt registers are shared by TA and TB but bit fields are not + symmetric. Need to go through LUT and fetch bit vector based on interrupts + */ + uint16_t intMaskLookup = GPTimerCC26XXLookupMask(GPT_LUT[handle->timerPart].interrupts, interrupts, GPT_NUM_INTS); + + if (callbackFxn != NULL) + { + callbackFxn(handle, intMaskLookup); + } +} + +/*! + * @brief Set Standby constraint while using timer to avoid TI RTOS + * going into standby when timer is running. As constraints are + * counting, store constraint status and access atomically and only + * once per timer resource. + */ +static inline void GPTimerCC26XXThreadsafeConstraintSet(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + /* Only set if not already set */ + if (object->powerConstraint[handle->timerPart]) + { + HwiP_restore(key); + return; + } + object->powerConstraint[handle->timerPart] = true; + HwiP_restore(key); + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/*! + * @brief Clear Standby constraint while using timer to avoid TI RTOS + * going into standby when timer is running. As constraints are + * counting, store constraint status and access atomically and only + * once per timer resource. + */ +static inline void GPTimerCC26XXThreadsafeConstraintClr(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_Object *object = handle->object; + + uint32_t key = HwiP_disable(); + /* Only release if constraint set */ + if (!object->powerConstraint[handle->timerPart]) + { + HwiP_restore(key); + return; + } + object->powerConstraint[handle->timerPart] = false; + HwiP_restore(key); + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); +} + +/*! + * @brief Configure debug stall mode in timer. When enabled the timer will + * stop when the CPU is halted by the debugger. + */ +void GPTimerCC26XX_configureDebugStall(GPTimerCC26XX_Handle handle, GPTimerCC26XX_DebugMode mode) +{ + GPTimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + uint32_t timer = GPT_LUT[handle->timerPart].map; + TimerStallControl(hwAttrs->baseAddr, timer, mode); +} + +/*! + * @brief Set custom argument in GPTimerCC26XX_Object + */ +void GPTimerCC26XX_setArg(GPTimerCC26XX_Handle handle, void *arg) +{ + GPTimerCC26XX_Object *object = handle->object; + object->arg = (uint32_t)arg; +} + +/*! + * @brief Get custom argument in GPTimerCC26XX_Object + */ +uint32_t GPTimerCC26XX_getArg(GPTimerCC26XX_Handle handle) +{ + GPTimerCC26XX_Object *object = handle->object; + + return ((uint32_t)object->arg); +} + +/*! + * @brief Set timer configuration. Will be moved to driverlib. + */ +static inline void TimerSetConfig(uint32_t ui32Base, uint32_t ui32Config) +{ + HWREG(ui32Base + GPT_O_CFG) = ui32Config; +} +/*! + * @brief Set timer mode. Will be moved to driverlib. + */ +static inline void TimerSetMode(uint32_t ui32Base, uint32_t timer, uint32_t mode) +{ + uint32_t addr = ui32Base; + + if (timer == TIMER_B) + { + addr += GPT_O_TBMR; + } + else + { + addr += GPT_O_TAMR; + } + HWREG(addr) = mode; +} diff --git a/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.h b/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.h new file mode 100644 index 00000000..70d287bf --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/timer/GPTimerCC26XX.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file GPTimerCC26XX.h + * @brief GPTimer driver implementation for CC26XX/CC13XX + * + * # Overview # + * This TI RTOS driver can be used to configure GPTimer modules to the modes + * supported by the GPTimer. The board file or application must define the device + * specific configuration before using the driver. + * # Configuration # + * The GPTimer can be used in two different configurations. In 32-bit mode the + * timer will act as a full-width timer and is controlled using the Timer A unit. + * In split (16-bit) mode the timer is split into 2x 16-bit timers. In 16-bit mode + * a prescaler is available for each timer unit, effectively increasing the + * resolution in this mode to 24-bit. All supported modes by driver in split + * configuration uses prescaler as timer extension. + * + * # Modes # + * The GPTimer driver supports the following timer modes: + * - Oneshot mode counting upwards. When timer reaches load value, the timer + * is stopped automatically. Supported in both 16 and 32-bit configuration. + * - Periodic mode counting upwards. When timer reaches load value it wraps and + * starts counting from 0 again. Supported in both 16 and 32-bit configuration. + * - Input edge-count. Timer counts the number of events on its input capture port + * upwards from 0. Events can be rising-edge, falling-edge, or both. + * Supported only in 16-bit mode. + * - Input edge-time. Timer counts upwards from 0 and captures the time of an + * event on its input capture port. This can be used to count the time + * between events. Events can be rising-edge, falling-edge or both. + * Supported only in 16-bit mode. + * - PWM mode. Timer counts downwards from load value. CCP is set to 1 when + * reaching timeout (0) and toggles when reaching match value. + * + * # Power Management # + * The TI-RTOS power management framework will try to put the device into the most + * power efficient mode whenever possible. Please see the technical reference + * manual for further details on each power mode. + * + * The GPTimerCC26XX driver will set constraints on disallowed power modes when + * needed, removing the need for the application to handle this. + * The following statements are valid: + * - After GPTimerCC26XX_open(): + * The device is still allowed to enter Standby. When the device is + * active the corresponding GPTimer peripheral will be enabled and clocked. + * - After GPTimerCC26XX_start(): + * The device will only go to Idle power mode since the high-frequency + * clock is needed for timer operation. + * - After GPTimerCC26XX_stop(): + * Conditions are equal as for after GPTimerCC26XX_open + * - After GPTimerCC26XX_close(): + * The underlying GPTimer is turned off and the device is allowed to go + * to standby. + * + * # Accuracy # + * The GPTimer clock is dependent on the MCU system clock. + * If very high-accuracy outputs are needed, the application should request + * using the external HF crystal: + * @code + * #include + * #include + * Power_setDependency(XOSC_HF); + * @endcode + * + * # Limitations # + * - DMA usage is not supported + * - Timer synchronization is not supported + * - Down counting modes (except for PWM) are not supported by driver + * + * # GPTimerCC26XX usage # + * + * ## Periodic timer ## + * The example below will generate an interrupt using the GPTimer every 1 ms. + * + * @code + * GPTimerCC26XX_Handle hTimer; + * void timerCallback(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask) { + * // interrupt callback code goes here. Minimize processing in interrupt. + * } + * + * void taskFxn(uintptr_t a0, uintptr_t a1) { + * GPTimerCC26XX_Params params; + * GPTimerCC26XX_Params_init(¶ms); + * params.width = GPT_CONFIG_16BIT; + * params.mode = GPT_MODE_PERIODIC; + * params.direction = GPTimerCC26XX_DIRECTION_UP; + * params.debugStallMode = GPTimerCC26XX_DEBUG_STALL_OFF; + * hTimer = GPTimerCC26XX_open(CC2650_GPTIMER0A, ¶ms); + * if(hTimer == NULL) { + * Log_error0("Failed to open GPTimer"); + * Task_exit(); + * } + * + * Types_FreqHz freq; + * BIOS_getCpuFreq(&freq); + * GPTimerCC26XX_Value loadVal = freq.lo / 1000 - 1; //47999 + * GPTimerCC26XX_setLoadValue(hTimer, loadVal); + * GPTimerCC26XX_registerInterrupt(hTimer, timerCallback, GPT_INT_TIMEOUT); + * + * GPTimerCC26XX_start(hTimer); + * + * while(1) { + * Task_sleep(BIOS_WAIT_FOREVER); + * } + * } + * @endcode + * + * + * ## PWM output ## + * See the PWM2TimerCC26XX driver + ******************************************************************************* + */ + +#ifndef ti_drivers_timer_GPTIMERCC26XX__include +#define ti_drivers_timer_GPTIMERCC26XX__include + +#include +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_gpt.h) +#include DeviceFamily_constructPath(driverlib/event.h) +#include DeviceFamily_constructPath(driverlib/ioc.h) +#include DeviceFamily_constructPath(driverlib/timer.h) + +#ifdef __cplusplus +extern "C" { +#endif + +/* Backwards compatibility - old timer modes. New behaviour is count-up by default but configurable. */ +#define GPT_MODE_ONESHOT_UP GPT_MODE_ONESHOT +#define GPT_MODE_PERIODIC_UP GPT_MODE_PERIODIC +#define GPT_MODE_EDGE_COUNT_UP GPT_MODE_EDGE_COUNT +#define GPT_MODE_EDGE_TIME_UP GPT_MODE_EDGE_TIME + +/*! + * @brief + * Definitions for specifying the GPTimer configuration (width) + */ +typedef enum GPTimerCC26XX_Width +{ + GPT_CONFIG_32BIT = GPT_CFG_CFG_32BIT_TIMER, + GPT_CONFIG_16BIT = GPT_CFG_CFG_16BIT_TIMER, +} GPTimerCC26XX_Width; + +/*! + * @brief + * Definitions for supported GPTimer modes. Driver code assumes only modes + * using prescaler as timer extension in 16-bit configuration are used. + * Therefore new modes must not be added to the below description without + * also updating driver. + * + */ +typedef enum GPTimerCC26XX_Mode +{ + /* One shot mode counting upwards */ + GPT_MODE_ONESHOT = GPT_TAMR_TAMR_ONE_SHOT | GPT_TAMR_TAMIE, + /* Periodic mode counting upwards */ + GPT_MODE_PERIODIC = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAMIE, + /* Edge count mode counting upwards */ + GPT_MODE_EDGE_COUNT = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGCNT, + /* Edge count mode counting upwards */ + GPT_MODE_EDGE_TIME = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGTIME, + /* PWM mode counting downwards. This specific configuration is used by the + PWM2TimerCC26XX driver */ + GPT_MODE_PWM = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAPWMIE_EN | GPT_TAMR_TAAMS_PWM | GPT_TAMR_TACM_EDGCNT | + GPT_TAMR_TAPLO_CCP_ON_TO, +} GPTimerCC26XX_Mode; + +/*! + * @brief + * Definitions for supported GPTimer interrupts. GPTimerCC26XX_IntMask + * arguments should be a bit vector containing these definitions. + * See description in Technical Reference + */ +typedef enum GPTimerCC26XX_Interrupt +{ + GPT_INT_TIMEOUT = 1 << 0, + GPT_INT_CAPTURE_MATCH = 1 << 1, + GPT_INT_CAPTURE = 1 << 2, + GPT_INT_MATCH = 1 << 3, +} GPTimerCC26XX_Interrupt; + +/* Number of entries in GPTimerCC26XX_Interrupt */ +#define GPT_NUM_INTS 4 + +/*! + * @brief + * Definitions for GPTimer parts (Timer A / Timer B). + * Used in GPTimer configuration structure GPTimerCC26XX_config to + * configure the corresponding timer unit. + */ +typedef enum GPTimerCC26XX_Part +{ + GPT_A = 0, + GPT_B, +} GPTimerCC26XX_Part; + +#define GPT_PARTS_COUNT 2 + +/*! + * @brief + * Definitions for input / output ports in IO controller to connect GPTimer + * to a pin. Used in gptimerCC26xxHWAttrs for static timer configuration + * PIN driver is used to mux a pin to the timer. + * @sa PINCC26XX_setMux + * @sa GPTimerCC26XX_getPinMux + */ +typedef enum GPTimerCC26XX_PinMux +{ + GPT_PIN_0A = IOC_PORT_MCU_PORT_EVENT0, + GPT_PIN_0B = IOC_PORT_MCU_PORT_EVENT1, + GPT_PIN_1A = IOC_PORT_MCU_PORT_EVENT2, + GPT_PIN_1B = IOC_PORT_MCU_PORT_EVENT3, + GPT_PIN_2A = IOC_PORT_MCU_PORT_EVENT4, + GPT_PIN_2B = IOC_PORT_MCU_PORT_EVENT5, + GPT_PIN_3A = IOC_PORT_MCU_PORT_EVENT6, + GPT_PIN_3B = IOC_PORT_MCU_PORT_EVENT7, +} GPTimerCC26XX_PinMux; + +/*! + * @brief + * Definitions for controlling timer debug stall mode + */ +typedef enum GPTimerCC26XX_DebugMode +{ + GPTimerCC26XX_DEBUG_STALL_OFF = 0, + GPTimerCC26XX_DEBUG_STALL_ON, +} GPTimerCC26XX_DebugMode; + +/*! + * @brief + * Definitions for controlling timer counting direction. + * Setting the Direction for PWM operation has no effect (always counts down). + */ +typedef enum GPTimerCC26XX_Direction +{ + GPTimerCC26XX_DIRECTION_DOWN = 0, + GPTimerCC26XX_DIRECTION_UP, +} GPTimerCC26XX_Direction; + +/*! + * @brief + * Definitions for new value loading behaviour. + * + * If set to NEXT_CLOCK, then the new match value is updated immediately. + * If set to ON_TIMEOUT the new match will only be applied to the next timer cycle. + * + * Only match setting is affected by this option. Load setting is always applied immediately. + */ +typedef enum GPTimerCC26XX_SetMatchTiming +{ + GPTimerCC26XX_SET_MATCH_NEXT_CLOCK = 0, + GPTimerCC26XX_SET_MATCH_ON_TIMEOUT, +} GPTimerCC26XX_SetMatchTiming; + +/*! + * @brief + * Definitions for controlling edges used for timer capture. + * Used in GPTimer edge-time and edge-count modes. + */ +typedef enum GPTimerCC26XX_Edge +{ + GPTimerCC26XX_POS_EDGE = GPT_CTL_TAEVENT_POS, + GPTimerCC26XX_NEG_EDGE = GPT_CTL_TAEVENT_NEG, + GPTimerCC26XX_BOTH_EDGES = GPT_CTL_TAEVENT_BOTH, +} GPTimerCC26XX_Edge; + +/* Forward declaration of GPTimer configuration */ +typedef struct GPTimerCC26XX_Config GPTimerCC26XX_Config; + +/* GPTimer handle is pointer to configuration structure */ +typedef GPTimerCC26XX_Config *GPTimerCC26XX_Handle; + +/* Interrupt bit vector. See GPTimerCC26XX_Interrupt for available interrupts */ +typedef uint16_t GPTimerCC26XX_IntMask; + +/* Timer value */ +typedef uint32_t GPTimerCC26XX_Value; + +/* Function prototype for interrupt callbacks */ +typedef void (*GPTimerCC26XX_HwiFxn)(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); + +/*! + * @brief GPTimer26XX Hardware attributes + * + * These fields are used by the driver to set up underlying GPTimer + * driver statically. A sample structure is shown below: + * + * @code + * // GPTimer hardware attributes, one per timer unit (Timer 0A, 0B, 1A, 1B..) + * const GPTimerCC26XX_HWAttrs gptimerCC26xxHWAttrs[CC2650_GPTIMERPARTSCOUNT] = { + * {.baseAddr = GPT0_BASE, .intNum = INT_TIMER0A, .powerMngrId = PERIPH_GPT0, .pinMux = GPT_PIN_0A, }, + * {.baseAddr = GPT0_BASE, .intNum = INT_TIMER0B, .powerMngrId = PERIPH_GPT0, .pinMux = GPT_PIN_0B, }, + * {.baseAddr = GPT1_BASE, .intNum = INT_TIMER1A, .powerMngrId = PERIPH_GPT1, .pinMux = GPT_PIN_1A, }, + * {.baseAddr = GPT1_BASE, .intNum = INT_TIMER1B, .powerMngrId = PERIPH_GPT1, .pinMux = GPT_PIN_1B, }, + * {.baseAddr = GPT2_BASE, .intNum = INT_TIMER2A, .powerMngrId = PERIPH_GPT2, .pinMux = GPT_PIN_2A, }, + * {.baseAddr = GPT2_BASE, .intNum = INT_TIMER2B, .powerMngrId = PERIPH_GPT2, .pinMux = GPT_PIN_2B, }, + * {.baseAddr = GPT3_BASE, .intNum = INT_TIMER3A, .powerMngrId = PERIPH_GPT3, .pinMux = GPT_PIN_3A, }, + * {.baseAddr = GPT3_BASE, .intNum = INT_TIMER3B, .powerMngrId = PERIPH_GPT3, .pinMux = GPT_PIN_3B, }, + * }; + * @endcode + */ +typedef struct GPTimerCC26XX_HWAttrs +{ + /*! GPTimer peripheral base address */ + uint32_t baseAddr; + /*! GPTimer peripheral interrupt vector */ + uint8_t intNum; + /*! GPTimer peripheral's interrupt priority. + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + (7 << 5) will apply the lowest priority. + (1 << 5) will apply the highest priority. + Setting the priority to 0 is not supported by this driver. + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! GPTimer peripheral's power manager ID */ + uint8_t powerMngrId; + /*! GPTimer half timer unit */ + GPTimerCC26XX_Part timer; + /*! PIN driver MUX */ + GPTimerCC26XX_PinMux pinMux; +} GPTimerCC26XX_HWAttrs; + +/*! + * @brief GPTimer26XX Object + * + * These fields are used by the driver to store and modify GPTimer configuration + * during run-time. + * The application must not edit any member variables of this structure. + * Appplications should also not access member variables of this structure + * as backwards compatibility is not guaranteed. An example structure is shown + * below: + * @code + * // GPTimer objects, one per full-width timer (A+B) (Timer 0, Timer 1..) + * GPTimerCC26XX_Object gptimerCC26XXObjects[CC2650_GPTIMERCOUNT]; + * @endcode + */ +typedef struct GPTimerCC26XX_Object +{ + GPTimerCC26XX_Width width; /*!< Timer width configuration (16/32bit)*/ + bool isOpen[GPT_PARTS_COUNT]; /*!< Object is opened flag */ + HwiP_Struct hwi[GPT_PARTS_COUNT]; /*!< Hardware interrupt struct */ + GPTimerCC26XX_HwiFxn hwiCallbackFxn[GPT_PARTS_COUNT]; /*!< Hardware interrupt callback function */ + volatile bool powerConstraint[GPT_PARTS_COUNT]; /*!< Standby power constraint flag */ + uint32_t arg; /*!< Arbritrary Argument */ +} GPTimerCC26XX_Object; + +/*! + * @brief GPTimer Global configuration + * + * The GPTimerCC26XX_Config structure contains a set of pointers + * used to characterize the GPTimer driver implementation. + * An example structure is shown below: + * @code + * // GPTimer configuration (used as GPTimer_Handle by driver and application) + * const GPTimerCC26XX_Config GPTimerCC26XX_config[CC2650_GPTIMERPARTSCOUNT] = { + * { &gptimerCC26XXObjects[0], &gptimerCC26xxHWAttrs[0], GPT_A}, + * { &gptimerCC26XXObjects[0], &gptimerCC26xxHWAttrs[1], GPT_B}, + * { &gptimerCC26XXObjects[1], &gptimerCC26xxHWAttrs[2], GPT_A}, + * { &gptimerCC26XXObjects[1], &gptimerCC26xxHWAttrs[3], GPT_B}, + * { &gptimerCC26XXObjects[2], &gptimerCC26xxHWAttrs[4], GPT_A}, + * { &gptimerCC26XXObjects[2], &gptimerCC26xxHWAttrs[5], GPT_B}, + * { &gptimerCC26XXObjects[3], &gptimerCC26xxHWAttrs[6], GPT_A}, + * { &gptimerCC26XXObjects[3], &gptimerCC26xxHWAttrs[7], GPT_B}, + * }; + * @endcode + */ +struct GPTimerCC26XX_Config +{ + GPTimerCC26XX_Object *object; + const GPTimerCC26XX_HWAttrs *hwAttrs; + GPTimerCC26XX_Part timerPart; +}; + +/*! + * @brief GPTimerCC26XX Parameters + * + * GPTimer parameters are used to with the GPTimerCC26XX_open() call. + * Default values for these parameters are set using GPTimerCC26XX_Params_init(). + * + * @sa GPTimerCC26XX_Params_init() + */ +typedef struct GPTimerCC26XX_Params +{ + GPTimerCC26XX_Width width; /*!< Timer configuration (32/16-bit) */ + GPTimerCC26XX_Mode mode; /*!< Timer mode */ + GPTimerCC26XX_SetMatchTiming matchTiming; /*!< Set new match values on next timeout or next cycle */ + GPTimerCC26XX_Direction direction; /*!< Count up or down */ + GPTimerCC26XX_DebugMode debugStallMode; /*!< Timer debug stall mode */ +} GPTimerCC26XX_Params; + +/*! + * @brief Function to initialize the GPTimerCC26XX_Params struct to + * its default values + * + * @param params An pointer to GPTimerCC26XX_Params structure for + * initialization + * + * Defaults values are: + * - 32-bit configuration + * - Periodic mode counting upwards + * - Debug stall mode disabled + */ +extern void GPTimerCC26XX_Params_init(GPTimerCC26XX_Params *params); + +/*! + * @brief This function opens a given GPTimer peripheral. Will set dependency + * on timer and configure it into specified mode. + * + * @param index Logical peripheral number for the GPTimer indexed into + * the GPTimerCC26XX_config table + * + * @param params Pointer to a parameter block. If NULL, it will use + * default values. + * + * @return A GPTimerCC26XX_Handle on success or a NULL on an error or if it has been + * opened already. If NULL is returned, further GPTimerCC26XX API calls will + * result in undefined behaviour. + * + * @sa GPTimerCC26XX_close() + */ +extern GPTimerCC26XX_Handle GPTimerCC26XX_open(unsigned int index, const GPTimerCC26XX_Params *params); + +/*! + * @brief Function to close a GPTimer peripheral specified by the GPTimer handle. + * Closing timer will releae dependency on timer and clear configuration + * + * @pre GPTimerCC26XX_open() has to be called first. + * @pre GPTimerCC26XX_stop() should to be called first if GPTimer is started + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_start() + * @sa GPTimerCC26XX_stop() + */ +extern void GPTimerCC26XX_close(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to start the specified GPTimer with current settings + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_stop() + */ +extern void GPTimerCC26XX_start(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to stop the specified GPTimer. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open() + * + * @sa GPTimerCC26XX_open() + * @sa GPTimerCC26XX_start() + */ +extern void GPTimerCC26XX_stop(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to set load value of the specified GPTimer. Function can + * be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param loadValue Load value to set the GPTimer to. + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setLoadValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value loadValue); + +/*! + * @brief Function to set match value of the specified GPTimer. Function can + * be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param matchValue Match value to set the GPTimer to. + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setMatchValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value matchValue); + +/*! + * @brief Function to set which input edge the GPTimer capture should + * use. Applies to edge-count and edge-time modes + * Function can be called while GPTimer is running. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param edge The edge that should trigger a capture + * + * @sa GPTimerCC26XX_open() + */ +extern void GPTimerCC26XX_setCaptureEdge(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Edge edge); + +/*! + * @brief Function to retrieve the current free-running value of timer + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @return Current free-running timer value for all modes + * + * @sa GPTimerCC26XX_open() + */ +extern GPTimerCC26XX_Value GPTimerCC26XX_getFreeRunValue(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to retrieve the current value of timer + * This returns the value of the timer in all modes except for + * input edge count and input edge time mode. + * In edge count mode, this register contains the number of edges that + * have occurred. In input edge time, this register contains the + * timer value at which the last edge event took place. + * + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @return Current free-running timer value for all modes + * + * @sa GPTimerCC26XX_open() + */ +extern GPTimerCC26XX_Value GPTimerCC26XX_getValue(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to register a CPU interrupt for a given timer handle and + * enable a set of timer interrupt sources. The interrupt to the CPU + * will be a bitwise OR of the enabled interrupt sources. + * When an interrupt occurs, the driver will clear the + * interrupt source and call the application provided callback. + * The callback is executed in HW interrupt context and processing in + * callback should be minimized. + * + * Interrupt sources can also be individually disabled and enabled by + * using GPTimerCC26XX_enableInterrupt / GPTimerCC26XX_disableInterrupt. + * + * This function should only be called once for a handle after opening + * the timer. + * If closing a GPTimer, interrupts for the timer should be + * unregistered first using GPTimerCC26XX_unregisterInterrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param callback An application provided callback function + * @param intMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_enableInterrupt + * @sa GPTimerCC26XX_disableInterrupt + */ +extern void GPTimerCC26XX_registerInterrupt(GPTimerCC26XX_Handle handle, + GPTimerCC26XX_HwiFxn callback, + GPTimerCC26XX_IntMask intMask); + +/*! + * @brief Function to disable a CPU interrupt for a given timer handle and + * disable all interrupt sources for corresponding GPTimer unit. + * + * This function should only be called once for a handle after opening + * the timer and registering the interrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * @pre GPTimerCC26XX_registerInterrupt() has to be called first + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_registerInterrupt + */ +extern void GPTimerCC26XX_unregisterInterrupt(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to enable a set of GPTimer interrupt sources. + * The interrupt to the CPU must be enabled using + * GPTimerCC26XX_registerInterrupt. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param interruptMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_disableInterrupt + */ +extern void GPTimerCC26XX_enableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); +/*! + * @brief Function to disable a set of GPTimer interrupt sources. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param interruptMask A bit vector mask containing values from GPTimerCC26XX_Interrupt + * + * @sa GPTimerCC26XX_open + * @sa GPTimerCC26XX_enableInterrupt + */ +extern void GPTimerCC26XX_disableInterrupt(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); + +/*! + * @brief Function to control timer debug stall mode. + * When enabled, the timer will stop when the debugger halts the CPU. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param mode Configuration for debug stall mode (enable/disable) + * + * @sa GPTimerCC26XX_open + */ +extern void GPTimerCC26XX_configureDebugStall(GPTimerCC26XX_Handle handle, GPTimerCC26XX_DebugMode mode); + +/*! + * @brief Function to get a custom argument. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * @pre GPTimerCC26XX_setArg() has to be called first + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @sa GPTimerCC26XX_setArg + * @sa GPTimerCC26XX_open + */ +extern uint32_t GPTimerCC26XX_getArg(GPTimerCC26XX_Handle handle); + +/*! + * @brief Function to set a custom argument. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * @param arg Pointer to a custom argument + * + * @sa GPTimerCC26XX_getArg + * @sa GPTimerCC26XX_open + */ +extern void GPTimerCC26XX_setArg(GPTimerCC26XX_Handle handle, void *arg); + +/*! + * @brief Function to return the PIN mux used by the GPTimer identified by + * handle. This is used to connect a GPTimer capture/compare port to + * a device DIO using PINCC26XX_setMux. + * This is typically used in PWM mode and Timer Edge-Count / Edge-Time + * modes. + * Function assumes correct pinMux is set up in device specific + * GPTimerCC26XX_HWAttrs. + * + * @pre GPTimerCC26XX_open() has to be called first successfully + * + * @param handle A GPTimerCC26XX handle returned from GPTimerCC26XX_open + * + * @sa GPTimerCC26XX_open + */ +static inline GPTimerCC26XX_PinMux GPTimerCC26XX_getPinMux(GPTimerCC26XX_Handle handle) +{ + return handle->hwAttrs->pinMux; +} + +#ifdef __cplusplus +} +#endif +#endif /* ti_drivers_timer_GPTIMERCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.c b/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.c new file mode 100644 index 00000000..953ce574 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2019-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +/* Internal callback function */ +static void TimerCC26XX_callbackfxn(GPTimerCC26XX_Handle gptHandle, GPTimerCC26XX_IntMask intMask); + +extern uint_least8_t Timer_count; + +/* Default Parameters */ +static const Timer_Params defaultParams = {.timerMode = Timer_ONESHOT_BLOCKING, + .periodUnits = Timer_PERIOD_COUNTS, + .timerCallback = NULL, + .period = (uint16_t)~0}; + +/* + * ======== Timer_close ======== + */ +void Timer_close(Timer_Handle handle) +{ + TimerCC26XX_Object *object = handle->object; + + /* Unregister Interrupts and Callback */ + GPTimerCC26XX_unregisterInterrupt(object->gptHandle); + + /* Destruct semaphore */ + if (object->semHandle != NULL) + { + SemaphoreP_destruct(&(object->semStruct)); + object->semHandle = NULL; + } + + /* Close and delete gptHandle */ + GPTimerCC26XX_close(object->gptHandle); + object->gptHandle = NULL; + + /* Clear isOpen flag */ + object->isOpen = false; +} + +/* + * ======== Timer_control ======== + */ +int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, void *arg) +{ + return (Timer_STATUS_UNDEFINEDCMD); +} + +/* + * ======== Timer_getCount ======== + */ +uint32_t Timer_getCount(Timer_Handle handle) +{ + TimerCC26XX_Object const *object = handle->object; + uint32_t count; + + count = GPTimerCC26XX_getValue(object->gptHandle); + + return count; +} + +/* + * ======== TimerCC26XX_callbackfxn ======== + */ +static void TimerCC26XX_callbackfxn(GPTimerCC26XX_Handle gptHandle, GPTimerCC26XX_IntMask intMask) +{ + Timer_Handle handle; + /* Get Timer Handle from arg in GPTimerCC26XX_Object */ + handle = (Timer_Handle)GPTimerCC26XX_getArg(gptHandle); + TimerCC26XX_Object *object = handle->object; + + /* Callback not created when using Timer_FREE_RUNNING */ + if (object->mode != Timer_CONTINUOUS_CALLBACK) + { + Timer_stop(handle); + } + if (object->mode != Timer_ONESHOT_BLOCKING) + { + object->callBack(handle, Timer_STATUS_SUCCESS); + } +} + +/* + * ======== TimerCC26XX_open ======== + */ +Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params) +{ + Timer_Handle handle = NULL; + TimerCC26XX_HWAttrs const *hwAttrs; + TimerCC26XX_Object *object; + GPTimerCC26XX_Params gptParams; + int_fast16_t status; + + /* Verify driver index and state */ + if (index < Timer_count) + { + /* If parameters are NULL use defaults */ + if (params == NULL) + { + params = (Timer_Params *)&defaultParams; + } + + /* Get handle for this driver instance */ + handle = (Timer_Handle) & (Timer_config[index]); + object = handle->object; + hwAttrs = handle->hwAttrs; + } + else + { + return (NULL); + } + + /* Check if timer is already open */ + uint32_t key = HwiP_disable(); + if (object->isOpen) + { + HwiP_restore(key); + return (NULL); + } + object->isOpen = true; + HwiP_restore(key); + + /* Check for valid parameters */ + if (((params->timerMode == Timer_ONESHOT_CALLBACK || params->timerMode == Timer_CONTINUOUS_CALLBACK) && + params->timerCallback == NULL) || + params->period == 0) + { + + object->isOpen = false; + return (NULL); + } + + object->mode = params->timerMode; + object->period = params->period; + object->callBack = params->timerCallback; + object->isRunning = false; + + /* Initialize gptParams to default values */ + GPTimerCC26XX_Params_init(&gptParams); + + /* Convert Timer mode to GPT mode */ + switch (params->timerMode) + { + case Timer_ONESHOT_CALLBACK: + case Timer_ONESHOT_BLOCKING: + gptParams.mode = GPT_MODE_ONESHOT; + break; + + case Timer_CONTINUOUS_CALLBACK: + case Timer_FREE_RUNNING: + default: + gptParams.mode = GPT_MODE_PERIODIC; + break; + } + + /* Convert Timer width to GPT width */ + switch (hwAttrs->subTimer) + { + case TimerCC26XX_timer32: + gptParams.width = GPT_CONFIG_32BIT; + break; + + case TimerCC26XX_timer16A: + case TimerCC26XX_timer16B: + default: + gptParams.width = GPT_CONFIG_16BIT; + break; + } + + /* Pass a GPTimer index and params to GPTimer open call */ + object->gptHandle = GPTimerCC26XX_open(hwAttrs->gpTimerUnit, &gptParams); + + /* Check if returned gptHandle is null */ + if (object->gptHandle == NULL) + { + object->isOpen = false; + return (NULL); + } + + if (params->timerMode != Timer_FREE_RUNNING) + { + /* Set Timer Period and Units */ + status = Timer_setPeriod(handle, params->periodUnits, object->period); + if (status != Timer_STATUS_SUCCESS) + { + Timer_close(handle); + return (NULL); + } + + /* Create the semaphore for blocking mode */ + if (params->timerMode == Timer_ONESHOT_BLOCKING) + { + object->semHandle = SemaphoreP_constructBinary(&(object->semStruct), 0); + + if (object->semHandle == NULL) + { + Timer_close(handle); + return (NULL); + } + } + + /* Set custom arg in GPTimerCC26XX_Object to Timer handle */ + GPTimerCC26XX_setArg(object->gptHandle, (void *)handle); + + /* Register Interrupt */ + GPTimerCC26XX_registerInterrupt(object->gptHandle, TimerCC26XX_callbackfxn, GPT_INT_TIMEOUT); + } + + return (handle); +} + +/* + * ======== TimerSupport_timerDisable ======== + */ +void TimerSupport_timerDisable(Timer_Handle handle) +{ + TimerCC26XX_Object *object = handle->object; + + GPTimerCC26XX_stop(object->gptHandle); +} + +/* + * ======== TimerSupport_timerEnable ======== + */ +void TimerSupport_timerEnable(Timer_Handle handle) +{ + TimerCC26XX_Object *object = handle->object; + + GPTimerCC26XX_start(object->gptHandle); +} + +/* + * ======== TimerSupport_timerFullWidth ======== + */ +bool TimerSupport_timerFullWidth(Timer_Handle handle) +{ + TimerCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (hwAttrs->subTimer == TimerCC26XX_timer32) + { + return (true); + } + + return (false); +} + +/* + * ======== TimerSupport_timerLoad ======== + */ +void TimerSupport_timerLoad(Timer_Handle handle) +{ + TimerCC26XX_Object *object = handle->object; + + GPTimerCC26XX_setLoadValue(object->gptHandle, object->period); +} diff --git a/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.h b/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.h new file mode 100644 index 00000000..1b517463 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/timer/TimerCC26XX.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2019-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!***************************************************************************** + * @file TimerCC26XX.h + * @brief Timer driver interface for CC26XX devices + * + * # Operation # + * This driver implements a 32-bit or 16-bit general purpose timer for the + * CC26XX device. + * + * The timer always operates in count up mode. + * + * ============================================================================ + */ + +#ifndef ti_drivers_timer_TimerCC26XX__include +#define ti_drivers_timer_TimerCC26XX__include + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @def TimerCC26XX_SubTimer + * + * @brief Sub-timers on the CC26XX + * + * The timer peripheral supports full width and half width timer operation. + * Use the definitions in this enumerated type to specify a full width timer + * (32-bit) or half width timer (16-bit) in the hardware attributes. There are + * two half width timers per single timer peripheral. A 16-bit timer on this + * device has an 8-bit prescaler. + */ +typedef enum +{ + TimerCC26XX_timer16A = 0x0001, /*!< Half width timer A */ + TimerCC26XX_timer16B = 0x0002, /*!< Half width timer B */ + TimerCC26XX_timer32 = 0x0003, /*!< Full width timer */ +} TimerCC26XX_SubTimer; + +/*! + * @brief TimerCC26XX Hardware Attributes + * + * Timer hardware attributes that tell the TimerCC26XX driver specific GPTimer + * hardware configurations. + * + * A sample structure is shown below: + * @code + * const TimerCC26XX_HWAttrs timerCC26XXHWAttrs[] = + * { + * { + * .gpTimerUnit = GPTIMER0A, + .subTimer = TimerCC26XX_timer16A + * }, + * { + * .gpTimerUnit = GPTIMER0B, + .subTimer = TimerCC26XX_timer16B + * }, + * { + * .gpTimerUnit = GPTIMER1A, + .subTimer = TimerCC26XX_timer32 + * } + * }; + * @endcode + */ +typedef struct +{ + TIMER_BASE_HWATTRS + + /*! #GPTimerCC26XX_Config unit index (0A, 0B, 1A..) */ + uint8_t gpTimerUnit; + + /*! Specifies a full-width timer or half-width timer. */ + TimerCC26XX_SubTimer subTimer; + +} TimerCC26XX_HWAttrs; + +/*! + * @brief TimerCC26XX_Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + TIMER_BASE_OBJECT + + /* GPTimer handle used by Timer interface */ + GPTimerCC26XX_Handle gptHandle; + + /* Flag to show GPTimer is open */ + bool isOpen; + +} TimerCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_timer_TimerCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/timer/TimerSupport.h b/simplelink_lpf2/source/ti/drivers/timer/TimerSupport.h new file mode 100644 index 00000000..8c06b933 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/timer/TimerSupport.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file TimerSupport.h + * + * @brief Holder of common helper functions for the Timer driver + * + * ============================================================================ + */ + +#ifndef ti_drivers_TimerSupport__include +#define ti_drivers_TimerSupport__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Function to disable the timer peripheral + * + * @param[in] handle A Timer_Handle returned from Timer_open() + */ +extern void TimerSupport_timerDisable(Timer_Handle handle); + +/*! + * @brief Function to enable the timer peripheral + * + * @param[in] handle A Timer_Handle returned from Timer_open() + */ +extern void TimerSupport_timerEnable(Timer_Handle handle); + +/*! + * @brief Function to determine if timer is full-width + * + * @param[in] handle A Timer_Handle returned from Timer_open() + * @return Returns a bool indicating use of full-width timer + */ +extern bool TimerSupport_timerFullWidth(Timer_Handle handle); + +/*! + * @brief Function to load timer peripheral + * + * @param[in] handle A Timer_Handle returned from Timer_open() + */ +extern void TimerSupport_timerLoad(Timer_Handle handle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TimerSupport__include */ diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.c b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.c new file mode 100644 index 00000000..0fc7a76f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +/* Static globals */ +static bool isInitialized = false; + +static struct psa_invec invecs[1]; +static struct psa_outvec outvecs[1]; + +extern TRNG_ns_SecureCB trngSecureCB_ns[]; +extern TRNGCC26X4_ns_Object trngObject_ns[]; + +/* + * ======== TRNG_ns_cryptoKeyCallbackFxn ======== + */ +void TRNG_ns_cryptoKeyCallbackFxn(uintptr_t arg) +{ + TRNG_s_CryptoKeySecureCallback *secureCallbackObject = (TRNG_s_CryptoKeySecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&trngObject_ns[index].operationSemaphore); + } + else if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + trngObject_ns[index].cryptoKeyCallbackFxn(trngSecureCB_ns[index].cryptoKeyCallback.handle, + trngSecureCB_ns[index].cryptoKeyCallback.returnValue, + trngSecureCB_ns[index].cryptoKeyCallback.entropy); + } +} + +/* + * ======== TRNG_ns_randomBytesCallbackFxn ======== + */ +void TRNG_ns_randomBytesCallbackFxn(uintptr_t arg) +{ + TRNG_s_RandomBytesSecureCallback *secureCallbackObject = (TRNG_s_RandomBytesSecureCallback *)arg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(secureCallbackObject->handle); + + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + /* Unblock the pending task to signal that the operation is complete. */ + SemaphoreP_post(&trngObject_ns[index].operationSemaphore); + } + else if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) + { + /* Call the callback function provided by the application. */ + trngObject_ns[index].randomBytesCallbackFxn(trngSecureCB_ns[index].randomBytesCallback.handle, + trngSecureCB_ns[index].randomBytesCallback.returnValue, + trngSecureCB_ns[index].randomBytesCallback.randomBytes, + trngSecureCB_ns[index].randomBytesCallback.randomBytesSize); + } +} + +/* + * ======== TRNG_ns_registerCallback ======== + */ +static psa_status_t TRNG_ns_registerCallback(TRNG_Handle handle, const TRNG_Params *params) +{ + TRNG_s_CallbackMsg callbackMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Construct SecureCB objects */ + SecureCallback_construct(&trngSecureCB_ns[index].cryptoKeyCallback.object, + TRNG_ns_cryptoKeyCallbackFxn, + (uintptr_t)&trngSecureCB_ns[index].cryptoKeyCallback); + + SecureCallback_construct(&trngSecureCB_ns[index].randomBytesCallback.object, + TRNG_ns_randomBytesCallbackFxn, + (uintptr_t)&trngSecureCB_ns[index].randomBytesCallback); + + callbackMsg.handle = handle; + callbackMsg.cryptoKeyCallback = &trngSecureCB_ns[index].cryptoKeyCallback; + callbackMsg.randomBytesCallback = &trngSecureCB_ns[index].randomBytesCallback; + invecs[0].base = &callbackMsg; + invecs[0].len = sizeof(callbackMsg); + + /* Setup interface for return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + return CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_REGISTER_CALLBACKS, invecs, outvecs); +} + +/* + * ======== TRNG_init ======== + */ +void TRNG_init(void) +{ + uintptr_t key; + + if (!isInitialized) + { + /* Initialize CryptoPSA semaphores and SecureCB driver */ + CryptoPSACC26X4_init(); + + /* Enable power and clocks for TRNG here since the entropy pool starts + * filling as soon as TRNG initialization is done before the TRNG driver + * instance is opened or constructed. + */ + (void)Power_setDependency(PowerCC26XX_PERIPH_TRNG); + + key = HwiP_disable(); + + /* Call fast veneer */ + TRNG_s_init(); + + HwiP_restore(key); + + isInitialized = true; + } +} + +/* + * ======== TRNG_open ======== + */ +TRNG_Handle TRNG_open(uint_least8_t index, TRNG_Params *params) +{ + TRNG_Handle handle = NULL; + TRNG_s_OpenMsg openMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (TRNG_Params *)&TRNG_defaultParams; + } + + DebugP_assert(params->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + openMsg.index = index; + openMsg.params = params; + invecs[0].base = &openMsg; + invecs[0].len = sizeof(openMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_OPEN, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING)) + { + if (TRNG_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + trngObject_ns[index].returnBehavior = params->returnBehavior; + trngObject_ns[index].cryptoKeyCallbackFxn = params->cryptoKeyCallbackFxn; + trngObject_ns[index].randomBytesCallbackFxn = params->randomBytesCallbackFxn; + + /* + * params->timeout is not stored since infinite timeout must be used + * for blocking return behavior + */ + + SemaphoreP_constructBinary(&trngObject_ns[index].operationSemaphore, 0); + } + + return handle; +} + +/* + * ======== TRNG_construct ======== + */ +TRNG_Handle TRNG_construct(TRNG_Config *config, const TRNG_Params *params) +{ + TRNG_Handle handle = NULL; + TRNG_s_ConstructMsg constructMsg; + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + HwiP_restore(key); + return NULL; + } + + HwiP_restore(key); + + /* + * If params are NULL, use defaults. Secure driver can also set this, but + * NS driver needs to store the return behavior. + */ + if (params == NULL) + { + params = (TRNG_Params *)&TRNG_defaultParams; + } + + DebugP_assert(params->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK ? params->callbackFxn : true); + + /* Setup interface for input parameters */ + constructMsg.config = config; + constructMsg.params = params; + invecs[0].base = &constructMsg; + invecs[0].len = sizeof(constructMsg); + + /* Setup interface for return value */ + outvecs[0].base = &handle; + outvecs[0].len = sizeof(handle); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since handle (in outvecs) is initialized to NULL + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_CONSTRUCT, invecs, outvecs); + + if ((handle != NULL) && (params->returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING)) + { + if (TRNG_ns_registerCallback(handle, params) != PSA_SUCCESS) + { + handle = NULL; + } + } + + if (handle != NULL) + { + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Store NS handle object */ + trngObject_ns[index].returnBehavior = params->returnBehavior; + trngObject_ns[index].cryptoKeyCallbackFxn = params->cryptoKeyCallbackFxn; + trngObject_ns[index].randomBytesCallbackFxn = params->randomBytesCallbackFxn; + /* + * params->timeout is not stored since infinite timeout must be used + * for blocking return behavior + */ + + SemaphoreP_constructBinary(&trngObject_ns[index].operationSemaphore, 0); + } + + return handle; +} + +/* + * ======== TRNG_close ======== + */ +void TRNG_close(TRNG_Handle handle) +{ + TRNG_s_CloseMsg closeMsg; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + DebugP_assert(handle); + + /* Setup interface for input parameter */ + closeMsg.handle = handle; + invecs[0].base = &closeMsg; + invecs[0].len = sizeof(closeMsg); + + /* Setup interface for null return value */ + outvecs[0].base = NULL; + outvecs[0].len = 0; + + /* PSA call to secure driver */ + (void)CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_CLOSE, invecs, outvecs); + + SemaphoreP_destruct(&trngObject_ns[index].operationSemaphore); +} + +/* + * ======== TRNG_generateEntropy ======== + */ +int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey *entropy) +{ + return TRNG_generateKey(handle, entropy); +} + +/* + * ======== TRNG_generateKey ======== + */ +int_fast16_t TRNG_generateKey(TRNG_Handle handle, CryptoKey *entropy) +{ + TRNG_s_GenerateKeyMsg generateKeyMsg; + int_fast16_t result = TRNG_STATUS_ERROR; + psa_status_t psaStatus; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + + /* Setup interface for input parameters */ + generateKeyMsg.handle = handle; + generateKeyMsg.entropy = entropy; + invecs[0].base = &generateKeyMsg; + invecs[0].len = sizeof(generateKeyMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * The underlying TRNG driver supports queuing of blocking or callback + * operations and preemption by a polling operations. Therefore, no HW + * access semaphore acquisition required here. + */ + + if (trngObject_ns[index].returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* PSA call to secure driver */ + psaStatus = CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_GENERATE_KEY, invecs, outvecs); + + if (psaStatus == PSA_ERROR_PROGRAMMER_ERROR) + { + result = TRNG_STATUS_INVALID_INPUTS; + } + else if (psaStatus != PSA_SUCCESS) + { + result = TRNG_STATUS_ERROR; + } + + if (result != TRNG_STATUS_SUCCESS) + { + if (trngObject_ns[index].returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING) + { + /* Release power constraint if not successful */ + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + } + else if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + /* + * The app-specified timeout cannot be used here since the secure + * partition treats blocking return behavior in the same manner as + * callback. + */ + SemaphoreP_pend(&trngObject_ns[index].operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = trngSecureCB_ns[index].cryptoKeyCallback.returnValue; + } + + return (result); +} + +/* + * ======== TRNG_getRandomBytes ======== + */ +int_fast16_t TRNG_getRandomBytes(TRNG_Handle handle, void *randomBytes, size_t randomBytesSize) +{ + TRNG_s_GetRandomBytesMsg getRandomMsg; + int_fast16_t result = TRNG_STATUS_ERROR; + uintptr_t index = GET_CRYPTO_S_HANDLE_INDEX(handle); + psa_status_t psaStatus; + + /* Setup interface for input parameters */ + getRandomMsg.handle = handle; + getRandomMsg.randomBytes = randomBytes; + getRandomMsg.randomBytesSize = randomBytesSize; + invecs[0].base = &getRandomMsg; + invecs[0].len = sizeof(getRandomMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * The underlying TRNG driver supports queuing of blocking or callback + * operations and preemption by a polling operations. Therefore, no HW + * access semaphore acquisition required here. + */ + + if (trngObject_ns[index].returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING) + { + (void)Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + + /* PSA call to secure driver */ + psaStatus = CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_GET_RANDOM_BYTES, invecs, outvecs); + + if (psaStatus == PSA_ERROR_PROGRAMMER_ERROR) + { + result = TRNG_STATUS_INVALID_INPUTS; + } + else if (psaStatus != PSA_SUCCESS) + { + result = TRNG_STATUS_ERROR; + } + + if (result != TRNG_STATUS_SUCCESS) + { + if (trngObject_ns[index].returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING) + { + /* Release power constraint if not successful */ + (void)Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + } + } + else if (trngObject_ns[index].returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + /* + * The app-specified timeout cannot be used here since the secure + * partition treats blocking return behavior in the same manner as + * callback. + */ + SemaphoreP_pend(&trngObject_ns[index].operationSemaphore, SemaphoreP_WAIT_FOREVER); + result = trngSecureCB_ns[index].randomBytesCallback.returnValue; + } + + return (result); +} + +/* + * ======== TRNG_cancelOperation ======== + */ +int_fast16_t TRNG_cancelOperation(TRNG_Handle handle) +{ + TRNG_s_CancelOperationMsg cancelMsg; + int_fast16_t result = TRNG_STATUS_ERROR; + + /* Setup interface for input parameters */ + cancelMsg.handle = handle; + invecs[0].base = &cancelMsg; + invecs[0].len = sizeof(cancelMsg); + + /* Setup interface for return value */ + outvecs[0].base = &result; + outvecs[0].len = sizeof(result); + + /* + * PSA call to secure driver: + * + * Return value can be ignored since result (in outvecs) is initialized to TRNG_STATUS_ERROR + * and will only be updated if the PSA call is successful. + */ + (void)CryptoPSACC26X4_call(TRNG_S_MSG_TYPE_CANCEL_OPERATION, invecs, outvecs); + + return (result); +} + +/* + * ======== TRNGCC26XX_setSamplesPerCycle ======== + * samplesPerCycle must be between 2^8 and 2^24 (256 and 16777216) + */ +int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle) +{ + int_fast16_t result; + uintptr_t key; + + key = HwiP_disable(); + /* Call fast veneer */ + result = TRNGCC26XX_s_setSamplesPerCycle(handle, samplesPerCycle); + HwiP_restore(key); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.h b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.h new file mode 100644 index 00000000..2bfd5779 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_ns.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file TRNGCC26X4_ns.h + * + * @brief TRNG Nonsecure driver implementation for the CC26X4 family + * + */ + +#ifndef ti_drivers_TRNG_TRNGCC26X4_ns__include +#define ti_drivers_TRNG_TRNGCC26X4_ns__include + +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @cond NODOC */ + +/*! + * @brief TRNGCC26X4 NS Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + TRNG_CryptoKeyCallbackFxn cryptoKeyCallbackFxn; + TRNG_RandomBytesCallbackFxn randomBytesCallbackFxn; + TRNG_ReturnBehavior returnBehavior; + SemaphoreP_Struct operationSemaphore; +} TRNGCC26X4_ns_Object; + +/*! + * @brief TRNGCC26X4 NS Secure Callback Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + TRNG_s_CryptoKeySecureCallback cryptoKeyCallback; + TRNG_s_RandomBytesSecureCallback randomBytesCallback; +} TRNG_ns_SecureCB; + +/*! + * @brief Sets the number of entropy generation cycles before + * the results are returned. + * + * The default value is set to generate 64 bits of entropy. + * + * @pre TRNG_open() has to be called first successfully + * + * @param handle A TRNGCC26XX handle returned from TRNGCC26XX_open + * @param samplesPerCycle Number of 48MHz clock cycles to sample. Must be between 2^8 and 2^24. + * + * @sa TRNG_open() + */ +extern int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle); + +/*! @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TRNG_TRNGCC26X4_ns__include */ diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.c b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.c new file mode 100644 index 00000000..582428bb --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.c @@ -0,0 +1,844 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include "TRNGCC26X4_s.h" + +#include +#include +#include + +#include + +#include /* __tz_c_veneer */ + +#include +#include +#include +#include +#include + +#include /* TI CMSE helper functions */ +#include "ti_drivers_config.h" /* Sysconfig generated header */ + +#define TRNG_INSTANCE_COUNT TRNG_SECURE_CALLBACK_COUNT + +/* + * Stores a secure copy of the entropy key struct used when generating a key + * and the original pointer to the non-secure entropy key struct to return to + * non-secure client case of callback or blocking return behavior. + */ +typedef struct +{ + CryptoKey entropyKey_s; + CryptoKey *entropyKey_ns; +} TRNG_s_EntropyKey; + +/* + * The underlying TRNG driver supports preemption of existing operations with + * blocking or callback return behavior by a polling operation. Therefore, + * the entropy key must be tracked per driver instance. + */ +static TRNG_s_EntropyKey TRNG_s_entropyKey[TRNG_INSTANCE_COUNT]; + +/* + * TRNG Secure Dynamic Instance struct. + */ +typedef struct +{ + TRNG_Config config; + TRNGCC26XX_Object object; + TRNGCC26XX_HWAttrs hwAttrs; +} TRNG_s_DynamicInstance; + +/* + * Used to store a secure copy of the dynamic instance (config plus the + * object and hwAttrs that it points to) provided by non-secure calls to + * TRNG_construct. + */ +static TRNG_s_DynamicInstance TRNG_s_dynInstance[CONFIG_TRNG_S_CONFIG_POOL_SIZE]; + +typedef struct +{ + TRNG_s_CryptoKeySecureCallback *cryptoKeyCallback; + TRNG_s_RandomBytesSecureCallback *randomBytesCallback; +} TRNG_s_SecureCallbacks; + +/* Stores pointers to non-secure TRNG_s_SecureCallbacks for each driver instance opened or constructed */ +static TRNG_s_SecureCallbacks TRNG_s_secureCB[TRNG_SECURE_CALLBACK_COUNT]; + +/* Static driver instances allocated by SysConfig */ +extern const TRNG_Config TRNG_config[]; + +/* + * ======== TRNG_s_getCallbackIndex ======== + * Returns callback index or -1 if index is not found. + */ +static int8_t TRNG_s_getCallbackIndex(TRNG_Handle handle_s) +{ + uint_fast8_t index; + int8_t retIndex = -1; + bool indexFound = false; + + /* First, search config statically allocated by SysConfig */ + for (index = 0; index < CONFIG_TI_DRIVERS_TRNG_COUNT; index++) + { + if (handle_s == (TRNG_Handle)&TRNG_config[index]) + { + indexFound = true; + break; + } + } + + /* If not found, search secure config copies */ + if (!indexFound) + { + for (index = 0; index < CONFIG_TRNG_S_CONFIG_POOL_SIZE; index++) + { + if (handle_s == &TRNG_s_dynInstance[index].config) + { + index += CONFIG_TI_DRIVERS_TRNG_COUNT; + indexFound = true; + break; + } + } + } + + if (indexFound) + { + retIndex = (int8_t)index; + } + + return retIndex; +} + +/* + * ======== TRNG_s_clearCallbacks ======== + */ +static void TRNG_s_clearCallbacks(uint8_t index) +{ + TRNG_s_secureCB[index].cryptoKeyCallback = NULL; + TRNG_s_secureCB[index].randomBytesCallback = NULL; +} + +/* + * ======== TRNG_s_cryptoKeyCallback ======== + */ +static void TRNG_s_cryptoKeyCallback(TRNG_Handle handle_s, int_fast16_t returnValue, CryptoKey *entropy) +{ + int8_t index; + TRNG_s_CryptoKeySecureCallback *trngSecureCB_ns; + + index = TRNG_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < TRNG_SECURE_CALLBACK_COUNT)) + { + trngSecureCB_ns = TRNG_s_secureCB[index].cryptoKeyCallback; + + /* Copy the updated key encoding to the non-secure key struct */ + TRNG_s_entropyKey[index].entropyKey_ns->encoding = entropy->encoding; + + if (trngSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + trngSecureCB_ns->handle = (TRNG_Handle)(CRYPTO_S_HANDLE_ID_TRNG | index); + trngSecureCB_ns->returnValue = returnValue; + trngSecureCB_ns->entropy = TRNG_s_entropyKey[index].entropyKey_ns; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&trngSecureCB_ns->object); + } + } +} + +/* + * ======== TRNG_s_randomBytesCallback ======== + */ +static void TRNG_s_randomBytesCallback(TRNG_Handle handle_s, + int_fast16_t returnValue, + uint8_t *randomBytes, + size_t randomBytesSize) +{ + int8_t index; + TRNG_s_RandomBytesSecureCallback *trngSecureCB_ns; + TRNGCC26XX_Object *object = (TRNGCC26XX_Object *)handle_s->object; + + index = TRNG_s_getCallbackIndex(handle_s); + + if ((index >= 0) && (index < TRNG_SECURE_CALLBACK_COUNT)) + { + trngSecureCB_ns = TRNG_s_secureCB[index].randomBytesCallback; + + if (trngSecureCB_ns != NULL) + { + /* Store arguments in callback object for use by non-secure handler */ + trngSecureCB_ns->handle = (TRNG_Handle)(CRYPTO_S_HANDLE_ID_TRNG | index); + trngSecureCB_ns->returnValue = returnValue; + trngSecureCB_ns->randomBytes = object->entropyBuffer; + trngSecureCB_ns->randomBytesSize = object->entropyRequested; + + /* Trigger the interrupt for the non-secure callback dispatcher */ + SecureCallback_post(&trngSecureCB_ns->object); + } + } +} + +/* + * ======== TRNG_s_copyConfig ======== + */ +static inline psa_status_t TRNG_s_copyConfig(TRNG_Config **secureConfig, + const TRNG_Config *config, + TRNG_Handle *retHandle) +{ + TRNG_Config *config_s; + TRNG_s_DynamicInstance *dynInstance_s; + uint_fast8_t i; + + for (i = 0; i < CONFIG_TRNG_S_CONFIG_POOL_SIZE; i++) + { + dynInstance_s = &TRNG_s_dynInstance[i]; + config_s = &dynInstance_s->config; + + if (config_s->object == NULL) + { + /* Validate config address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config, sizeof(dynInstance_s->config)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy config to secure memory */ + (void)spm_memcpy(config_s, config, sizeof(dynInstance_s->config)); + + /* Validate object address range */ + if (cmse_has_unpriv_nonsecure_read_access(config_s->object, sizeof(dynInstance_s->object)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy object to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->object, config_s->object, sizeof(dynInstance_s->object)); + config_s->object = &dynInstance_s->object; + + /* Validate HW attributes address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)) == + NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Copy HW attributes to secure memory and point config to it */ + (void)spm_memcpy(&dynInstance_s->hwAttrs, config_s->hwAttrs, sizeof(dynInstance_s->hwAttrs)); + config_s->hwAttrs = &dynInstance_s->hwAttrs; + + *secureConfig = config_s; + + /* + * Set the secure callback pointers to NULL. The application + * must register secure callbacks after constructing or opening + * a driver instance. + */ + TRNG_s_clearCallbacks(i + CONFIG_TI_DRIVERS_TRNG_COUNT); + + /* + * Return handle is the CRYPTO_S_HANDLE_ID_TRNG OR'd with the + * the config pool array index plus the size of constant config + * array created by Sysconfig. + */ + *retHandle = (TRNG_Handle)(CRYPTO_S_HANDLE_ID_TRNG | (i + CONFIG_TI_DRIVERS_TRNG_COUNT)); + return PSA_SUCCESS; + } + } + + return PSA_ERROR_INSUFFICIENT_MEMORY; +} + +/* + * ======== TRNG_s_releaseConfig ======== + */ +static inline void TRNG_s_releaseConfig(TRNG_Handle nsHandle) +{ + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_TRNG) + { + /* Extract the secure handle index */ + uintptr_t i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + /* Check whether the handle instance refers to a dynamic instance */ + if ((i >= CONFIG_TI_DRIVERS_TRNG_COUNT) && (i < TRNG_SECURE_CALLBACK_COUNT)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + TRNG_s_dynInstance[i - CONFIG_TI_DRIVERS_TRNG_COUNT].config.object = NULL; + } + } +} + +/* + * ======== TRNG_s_copyParams ======== + */ +static psa_status_t TRNG_s_copyParams(TRNG_Params *secureParams, const TRNG_Params *params) +{ + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Validate params address range */ + if (cmse_has_unpriv_nonsecure_read_access((void *)params, sizeof(TRNG_Params)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + (void)spm_memcpy(secureParams, params, sizeof(TRNG_Params)); + + /* Validate the return behavior */ + if ((secureParams->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) || + (secureParams->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) || + (secureParams->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING)) + { + if (secureParams->returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING) + { + /* + * Overwrite the non-secure client's callback functions with our own + * callbacks which will populate the secure callback object registered + * using TRNG_S_MSG_TYPE_REGISTER_CALLBACKS. + */ + secureParams->cryptoKeyCallbackFxn = TRNG_s_cryptoKeyCallback; + secureParams->randomBytesCallbackFxn = TRNG_s_randomBytesCallback; + + /* Force to callback return behavior */ + secureParams->returnBehavior = TRNG_RETURN_BEHAVIOR_CALLBACK; + } + + status = PSA_SUCCESS; + } + + return status; +} + +/* + * ======== TRNG_s_getHandle ======== + * Returns a Secure handle from a handle provided from non-secure client. + */ +static TRNG_Handle TRNG_s_getHandle(TRNG_Handle nsHandle) +{ + TRNG_Handle secureHandle = NULL; + uint32_t i; + + if (GET_CRYPTO_S_HANDLE_ID(nsHandle) == CRYPTO_S_HANDLE_ID_TRNG) + { + /* Extract the secure handle index */ + i = GET_CRYPTO_S_HANDLE_INDEX(nsHandle); + + if (i < CONFIG_TI_DRIVERS_TRNG_COUNT) + { + secureHandle = (TRNG_Handle)&TRNG_config[i]; + } + else if ((i >= CONFIG_TI_DRIVERS_TRNG_COUNT) && (i < TRNG_SECURE_CALLBACK_COUNT)) + { + secureHandle = &TRNG_s_dynInstance[i - CONFIG_TI_DRIVERS_TRNG_COUNT].config; + } + } + + return secureHandle; +} + +/* + * ======== TRNG_s_registerCallbacks ======== + */ +static inline psa_status_t TRNG_s_registerCallbacks(psa_msg_t *msg) +{ + TRNG_Handle handle_s; + TRNG_s_CallbackMsg callbackMsg; + int8_t callbackIndex; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + + /* Only non-secure callers should be registering callbacks */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id) && (msg->in_size[0] == sizeof(callbackMsg))) + { + psa_read(msg->handle, 0, &callbackMsg, sizeof(callbackMsg)); + + /* At least one callback function must be non-NULL */ + if ((callbackMsg.cryptoKeyCallback == NULL) && (callbackMsg.randomBytesCallback == NULL)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + handle_s = TRNG_s_getHandle(callbackMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + callbackIndex = TRNG_s_getCallbackIndex(handle_s); + + /* Validate index */ + if ((callbackIndex >= 0) && (callbackIndex < TRNG_SECURE_CALLBACK_COUNT)) + { + /* + * Store the pointers to TRNG_s_CryptoKeySecureCallback and + * TRNG_s_RandomBytesCallback located in non-secure memory. + * NULL pointers are valid. + */ + if ((callbackMsg.cryptoKeyCallback == NULL) || + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.cryptoKeyCallback, + sizeof(TRNG_s_CryptoKeySecureCallback)) != NULL)) + { + TRNG_s_secureCB[callbackIndex].cryptoKeyCallback = callbackMsg.cryptoKeyCallback; + + if ((callbackMsg.randomBytesCallback == NULL) || + (cmse_has_unpriv_nonsecure_rw_access(callbackMsg.randomBytesCallback, + sizeof(TRNG_s_RandomBytesSecureCallback)) != NULL)) + { + TRNG_s_secureCB[callbackIndex].randomBytesCallback = callbackMsg.randomBytesCallback; + status = PSA_SUCCESS; + } + } + } + } + + return status; +} + +/* + * ======== TRNG_s_construct ======== + */ +static inline psa_status_t TRNG_s_construct(psa_msg_t *msg) +{ + TRNG_s_ConstructMsg constructMsg; + TRNG_Handle handle; + TRNG_Params params_s; + const TRNG_Params *paramsPtr_s = NULL; + TRNG_Config *configPtr_s; + psa_status_t status = PSA_ERROR_PROGRAMMER_ERROR; + TRNG_Handle retHandle = NULL; + + if ((msg->in_size[0] != sizeof(constructMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &constructMsg, sizeof(constructMsg)); + + /* + * For non-secure callers, the params and config must be verified and + * copied to secure memory. Assume secure callers are providing valid + * inputs located in secure memory which are accessible by this partition + * for the TF-M isolation level in use. At isolation levels 2 & 3, this + * means the params and config data may need to be defined within the + * same partition as the crypto driver. + * + * Non-secure callers have negative client ID. + */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + if (constructMsg.params != NULL) + { + /* + * Copy params to secure memory and substitute our own callback + * if callback return behavior is specified. + */ + status = TRNG_s_copyParams(¶ms_s, constructMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + + paramsPtr_s = ¶ms_s; + } + + /* Verify config and copy to secure memory */ + status = TRNG_s_copyConfig(&configPtr_s, constructMsg.config, &retHandle); + if (status != PSA_SUCCESS) + { + return status; + } + } + else /* Secure client */ + { + configPtr_s = constructMsg.config; + paramsPtr_s = constructMsg.params; + } + + handle = TRNG_construct(configPtr_s, paramsPtr_s); + + if (handle == NULL) + { + retHandle = NULL; + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* Set config's object pointer to NULL to indicate the config is available */ + configPtr_s->object = NULL; + } + } + else if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Return the pointer to the secure config struct provided by the + * secure caller. + */ + retHandle = handle; + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_open ======== + */ +static inline psa_status_t TRNG_s_open(psa_msg_t *msg) +{ + TRNG_s_OpenMsg openMsg; + TRNG_Handle handle; + TRNG_Params params_s; + TRNG_Params *paramsPtr_s = NULL; + TRNG_Handle retHandle = NULL; + psa_status_t status; + + if ((msg->in_size[0] != sizeof(openMsg)) || (msg->out_size[0] != sizeof(handle))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &openMsg, sizeof(openMsg)); + + if (openMsg.params != NULL) + { + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + status = TRNG_s_copyParams(¶ms_s, openMsg.params); + if (status != PSA_SUCCESS) + { + return status; + } + } + + paramsPtr_s = ¶ms_s; + } + + handle = TRNG_open(openMsg.index, paramsPtr_s); + + if (handle != NULL) + { + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + /* + * Set the secure callback pointers to NULL. The application + * must register a secure callbacks after constructing or opening + * a driver instance. + */ + TRNG_s_clearCallbacks(openMsg.index); + + /* + * Return CRYPTO_S_HANDLE_ID_TRNG OR'd with the config array index + * as the handle instead of a pointer to the config to allow for + * validation of handles provided by non-secure clients. + */ + retHandle = (TRNG_Handle)(CRYPTO_S_HANDLE_ID_TRNG | openMsg.index); + } + else /* Secure client */ + { + retHandle = handle; + } + } + + psa_write(msg->handle, 0, &retHandle, sizeof(retHandle)); + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_close ======== + */ +static inline psa_status_t TRNG_s_close(psa_msg_t *msg) +{ + TRNG_Handle handle_s; + TRNG_s_CloseMsg closeMsg; + + if (msg->in_size[0] != sizeof(closeMsg)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &closeMsg, sizeof(closeMsg)); + + /* Non-secure callers have negative client ID */ + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = TRNG_s_getHandle(closeMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + TRNG_close(handle_s); + + /* Release the secure config if it is a dynamic instance */ + TRNG_s_releaseConfig(closeMsg.handle); + } + else /* Secure client */ + { + TRNG_close(closeMsg.handle); + } + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_generateKey ======== + */ +static inline psa_status_t TRNG_s_generateKey(psa_msg_t *msg) +{ + TRNG_s_GenerateKeyMsg genKeyMsg; + TRNG_Handle handle_s; + CryptoKey *entropy_s; + int_fast16_t ret; + uint8_t idx; + + if ((msg->in_size[0] != sizeof(genKeyMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &genKeyMsg, sizeof(genKeyMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = TRNG_s_getHandle(genKeyMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Handle index is guaranteed to be valid if handle_s is non-NULL */ + idx = GET_CRYPTO_S_HANDLE_INDEX(genKeyMsg.handle); + entropy_s = &TRNG_s_entropyKey[idx].entropyKey_s; + + /* Validate crypto key struct address range */ + if (cmse_has_unpriv_nonsecure_read_access(genKeyMsg.entropy, sizeof(CryptoKey)) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Make a secure copy of the key struct */ + (void)spm_memcpy(entropy_s, genKeyMsg.entropy, sizeof(CryptoKey)); + + /* Save the non-secure key struct pointer */ + TRNG_s_entropyKey[idx].entropyKey_ns = genKeyMsg.entropy; + + if (CryptoKey_verifySecureOutputKey(entropy_s) != CryptoKey_STATUS_SUCCESS) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = TRNG_generateKey(handle_s, entropy_s); + + /* + * For polling return behavior, the key encoding will be updated upon + * successful completion. To avoid overhead of checking for successful + * return status and polling return behavior, blindly copy the updated + * encoding to the non-secure key struct. + */ + TRNG_s_entropyKey[idx].entropyKey_ns->encoding = entropy_s->encoding; + } + else /* Secure client */ + { + ret = TRNG_generateKey(genKeyMsg.handle, genKeyMsg.entropy); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_getRandomBytes ======== + */ +static inline psa_status_t TRNG_s_getRandomBytes(psa_msg_t *msg) +{ + TRNG_s_GetRandomBytesMsg getBytesMsg; + TRNG_Handle handle_s; + int_fast16_t ret; + + if ((msg->in_size[0] != sizeof(getBytesMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &getBytesMsg, sizeof(getBytesMsg)); + + if (TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + handle_s = TRNG_s_getHandle(getBytesMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + /* Validate random bytes buffer address range */ + if (cmse_has_unpriv_nonsecure_rw_access(getBytesMsg.randomBytes, getBytesMsg.randomBytesSize) == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = TRNG_getRandomBytes(handle_s, getBytesMsg.randomBytes, getBytesMsg.randomBytesSize); + } + else /* Secure client */ + { + ret = TRNG_getRandomBytes(getBytesMsg.handle, getBytesMsg.randomBytes, getBytesMsg.randomBytesSize); + } + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_cancelOperation ======== + */ +static inline psa_status_t TRNG_s_cancelOperation(psa_msg_t *msg) +{ + TRNG_Handle handle_s; + TRNG_s_CancelOperationMsg cancelMsg; + int_fast16_t ret; + + /* Cancellation is only supported for non-secure clients */ + if (!TFM_CLIENT_ID_IS_NS(msg->client_id)) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + if ((msg->in_size[0] != sizeof(cancelMsg)) || (msg->out_size[0] != sizeof(ret))) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + psa_read(msg->handle, 0, &cancelMsg, sizeof(cancelMsg)); + + handle_s = TRNG_s_getHandle(cancelMsg.handle); + if (handle_s == NULL) + { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + ret = TRNG_cancelOperation(handle_s); + + psa_write(msg->handle, 0, &ret, sizeof(ret)); + + return PSA_SUCCESS; +} + +/* + * ======== TRNG_s_handlePsaMsg ======== + */ +psa_status_t TRNG_s_handlePsaMsg(psa_msg_t *msg) +{ + psa_status_t status = PSA_SUCCESS; + + switch (msg->type) + { + /* + * If TRNG_S_MSG_TYPE_CONSTRUCT is used by other secure partitions, + * any pointer arguments provided must reference memory accessible by + * this partition which is dependent on the TF-M isolation level in use. + */ + case TRNG_S_MSG_TYPE_CONSTRUCT: + status = TRNG_s_construct(msg); + break; + + case TRNG_S_MSG_TYPE_OPEN: + status = TRNG_s_open(msg); + break; + + /* + * TRNG_S_MSG_TYPE_REGISTER_CALLBACKS is designed to be used non-secure + * callers only. Secure callers must only use polling return behavior. + */ + case TRNG_S_MSG_TYPE_REGISTER_CALLBACKS: + status = TRNG_s_registerCallbacks(msg); + break; + + case TRNG_S_MSG_TYPE_CLOSE: + status = TRNG_s_close(msg); + break; + + case TRNG_S_MSG_TYPE_GENERATE_KEY: + status = TRNG_s_generateKey(msg); + break; + + case TRNG_S_MSG_TYPE_GET_RANDOM_BYTES: + status = TRNG_s_getRandomBytes(msg); + break; + + /* + * TRNG_S_MSG_TYPE_CANCEL_OPERATION supported for non-secure clients + * only. Secure callers must only use polling return behavior. + */ + case TRNG_S_MSG_TYPE_CANCEL_OPERATION: + status = TRNG_s_cancelOperation(msg); + break; + + default: + /* Unknown msg type */ + status = PSA_ERROR_PROGRAMMER_ERROR; + break; + } + + return status; +} + +/* + * ======== TRNG_s_init ======== + */ +__tz_c_veneer void TRNG_s_init(void) +{ + TRNG_init(); +} + +/* + * ======== TRNGCC26XX_s_setSamplesPerCycle ======== + */ +__tz_c_veneer int_fast16_t TRNGCC26XX_s_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle) +{ + TRNG_Handle handle_s; + + handle_s = TRNG_s_getHandle(handle); + if (handle_s == NULL) + { + return (int_fast16_t)PSA_ERROR_PROGRAMMER_ERROR; + } + + return TRNGCC26XX_s_setSamplesPerCycle(handle_s, samplesPerCycle); +} diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.h b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.h new file mode 100644 index 00000000..176c02df --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26X4_s.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2022-2023, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_trng_TRNGCC26X4_s__include +#define ti_drivers_trng_TRNGCC26X4_s__include + +#include + +#include +#include + +#include + +#include +#include + +#if defined(TFM_BUILD) + #include "ti_drivers_config.h" /* Sysconfig generated header */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * TRNG secure message types + */ +#define TRNG_S_MSG_TYPE_CONSTRUCT TRNG_S_MSG_TYPE(0U) +#define TRNG_S_MSG_TYPE_OPEN TRNG_S_MSG_TYPE(1U) +#define TRNG_S_MSG_TYPE_REGISTER_CALLBACKS TRNG_S_MSG_TYPE(2U) +#define TRNG_S_MSG_TYPE_CLOSE TRNG_S_MSG_TYPE(3U) +#define TRNG_S_MSG_TYPE_GENERATE_KEY TRNG_S_MSG_TYPE(4U) +#define TRNG_S_MSG_TYPE_GET_RANDOM_BYTES TRNG_S_MSG_TYPE(5U) +#define TRNG_S_MSG_TYPE_CANCEL_OPERATION TRNG_S_MSG_TYPE(6U) + +/* + * Config pool size determines how many dynamic driver instances can be created + * by the non-secure client using TRNG_construct(). + */ +#ifndef CONFIG_TRNG_S_CONFIG_POOL_SIZE + #define CONFIG_TRNG_S_CONFIG_POOL_SIZE 2 /* One instance used for ECDSA */ +#endif + +#define TRNG_SECURE_CALLBACK_COUNT (CONFIG_TI_DRIVERS_TRNG_COUNT + CONFIG_TRNG_S_CONFIG_POOL_SIZE) + +/* + * ========= TRNG Secure Callback structs ========= + * Non-secure clients must register their callback after opening or + * constructing a driver instance with blocking or callback return behavior. + */ +typedef struct +{ + SecureCallback_Object object; + /* TRNG crypto key callback fxn parameters */ + TRNG_Handle handle; + int_fast16_t returnValue; + CryptoKey *entropy; +} TRNG_s_CryptoKeySecureCallback; + +typedef struct +{ + SecureCallback_Object object; + /* TRNG random bytes callback fxn parameters */ + TRNG_Handle handle; + int_fast16_t returnValue; + uint8_t *randomBytes; + size_t randomBytesSize; +} TRNG_s_RandomBytesSecureCallback; + +/* + * ========= TRNG Secure Message Structs ========= + * These secure message structs correspond to the secure message types defined + * above. Together, they are used by non-secure client to make PSA calls to the + * TRNG secure service. There is a single input vector for the PSA call + * which is a pointer to secure message struct. If the underlying function + * has a return value, there is a single output vector which is a pointer to + * storage for the return value. + */ +typedef struct +{ + TRNG_Config *config; + const TRNG_Params *params; +} TRNG_s_ConstructMsg; + +typedef struct +{ + uint_least8_t index; + const TRNG_Params *params; +} TRNG_s_OpenMsg; + +typedef struct +{ + TRNG_Handle handle; + TRNG_s_CryptoKeySecureCallback *cryptoKeyCallback; + TRNG_s_RandomBytesSecureCallback *randomBytesCallback; +} TRNG_s_CallbackMsg; + +typedef struct +{ + TRNG_Handle handle; +} TRNG_s_CloseMsg; + +typedef struct +{ + TRNG_Handle handle; + CryptoKey *entropy; +} TRNG_s_GenerateKeyMsg; + +typedef struct +{ + TRNG_Handle handle; + void *randomBytes; + size_t randomBytesSize; +} TRNG_s_GetRandomBytesMsg; + +typedef struct +{ + TRNG_Handle handle; +} TRNG_s_CancelOperationMsg; + +/*! + * @brief Handles PSA messages for TRNG secure driver + * + * @note This function should be called by secure partition thread only. + * + * @param [in] msg pointer to PSA message + * + * @retval PSA_SUCCESS if successful. + * @retval PSA_ERROR_PROGRAMMER_ERROR if any args point to secure addresses. + */ +psa_status_t TRNG_s_handlePsaMsg(psa_msg_t *msg); + +/*! + * @brief Initializes the TRNG secure driver. + * + * @note This function should be called by the non-secure client and power + * to TRNG HW must be enabled first. + */ +void TRNG_s_init(void); + +/*! + * @brief Fast veneer to set the number of entropy generation cycles before + * the results are returned. + * + * @param handle A valid TRNGCC26XX handle returned from TRNGCC26XX_open + * @param samplesPerCycle Number of 48MHz clock cycles to sample. Must be between 2^8 and 2^24. + * + * @retval PSA_ERROR_PROGRAMMER_ERROR if the handle is invalid. + * @retval TRNG_STATUS_SUCCESS if successful. + */ +int_fast16_t TRNGCC26XX_s_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_trng_TRNGCC26X4_s__include */ diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.c b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.c new file mode 100644 index 00000000..5e913d39 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.c @@ -0,0 +1,744 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/cpu.h) +#include DeviceFamily_constructPath(driverlib/interrupt.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/trng.h) + +/* Forward declarations */ +static void TRNGCC26XX_hwiFxn(uintptr_t arg0); +static int_fast16_t TRNGCC26XX_waitForResult(TRNG_Handle handle); +static void TRNGCC26XX_fillEntropyPool(uint32_t interruptStatus); +static void TRNGCC26XX_copyToClient(TRNGCC26XX_Object *object); +static void TRNGCC26XX_serviceJob(TRNG_Handle handle); +static void TRNGCC26XX_startJob(TRNG_Handle handle); +static void TRNGCC26XX_startTrng(uint32_t intPriority, bool enableInterrupts, uint32_t samplesPerCycle); +static void TRNGCC26XX_stopTrng(void); +/* TRNG_getRandom() + * The underlying function that executes the operation + * of getting random entropy data. + * + * IMPORTANT: + * If random data is requested to be output to a CryptoKey, the caller + * must ensure both the entropyKey and entropyBuffer are non-null values. + * If random data is requested to be output to an array/buffer, the caller + * must set the entropyKey field to null and ensure the entropyBuffer field + * is not null. + */ +static int_fast16_t TRNG_getRandom(TRNG_Handle handle); + +static HwiP_Struct TRNGCC26XX_hwi; + +static bool isInitialized = false; + +/* Keeps track of whether the TRNG is in ongoing use or if we should start + * the TRNG. + */ +static volatile bool trngActive = false; + +/* Ring buffer that keeps track of each 64-bit block of entropy that we keep + * as our entropy pool. We use 64-bit blocks because that is the minimum + * amount of entropy the TRNG hardware can generate. Using a smaller size would + * only waste generated entropy. This should be fine though because almost all + * requests should be a multiple of 64 bits; mostly 128 or 256 bits. + */ +static StructRingBuf_Object entropyPool; +static uint64_t entropyPoolBuffer[TRNGCC26XX_ENTROPY_POOL_SIZE] = {0}; + +/* Queue that keeps track of outstanding client jobs. Callback and blocking + * jobs are enqueued at the tail while polling jobs are enqueued at the head. + * This queue is worked off in FIFO order. After which, the driver will + * begin filling the depleted entropy pool. + */ +static List_List jobList = {0}; + +/* + * ======== TRNGCC26XX_fillEntropyPool ======== + * Copies freshly generated entropy from the TRNG hardware to the entropy pool. + */ +static void TRNGCC26XX_fillEntropyPool(uint32_t interruptStatus) +{ + uint8_t tmpEntropyBuf[TRNGCC26XX_MIN_BYTES_PER_ITERATION]; + + ((uint32_t *)tmpEntropyBuf)[0] = TRNGNumberGet(TRNG_LOW_WORD); + ((uint32_t *)tmpEntropyBuf)[1] = TRNGNumberGet(TRNG_HI_WORD); + + StructRingBuf_put(&entropyPool, tmpEntropyBuf); +} + +/* + * ======== TRNGCC26XX_copyToClient ======== + * Copies entropy from the pool to the client destination. + */ +static void TRNGCC26XX_copyToClient(TRNGCC26XX_Object *object) +{ + uint8_t tmpEntropyBuf[TRNGCC26XX_MIN_BYTES_PER_ITERATION]; + size_t bytesToCopy = 0; + + /* Do not do anything if this job does not need more entropy */ + while (object->entropyGenerated < object->entropyRequested) + { + + /* If there is entropy in the pool, dequeue it and copy to the job's + * target. + */ + if (StructRingBuf_get(&entropyPool, tmpEntropyBuf) != -1) + { + + bytesToCopy = Math_MIN(object->entropyRequested - object->entropyGenerated, sizeof(tmpEntropyBuf)); + + memcpy(object->entropyBuffer + object->entropyGenerated, tmpEntropyBuf, bytesToCopy); + + object->entropyGenerated += bytesToCopy; + } + /* If the pool is depleted, stop the process regardless of if the job + * is done yet. + */ + else + { + break; + } + } +} + +/* + * ======== TRNGCC26XX_serviceJob ======== + * Clean up a completed job and let the application know it is done. + */ +static void TRNGCC26XX_serviceJob(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object = handle->object; + + object->returnStatus = TRNG_STATUS_SUCCESS; + + /* Mark the CryptoKey as non-empty */ + if (object->entropyKey != NULL) + { + object->entropyKey->encoding = CryptoKey_PLAINTEXT; + } + + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&object->operationSemaphore); + } + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) + { + if (object->entropyKey != NULL) + { + object->cryptoKeyCallbackFxn(handle, object->returnStatus, object->entropyKey); + } + else + { + object->randomBytesCallbackFxn(handle, + object->returnStatus, + object->entropyBuffer, + object->entropyRequested); + } + } +} + +/* + * ======== TRNGCC26XX_hwiFxn ======== + */ +static void TRNGCC26XX_hwiFxn(uintptr_t arg0) +{ + uint32_t interruptStatus; + bool oldJobComplete = false; + TRNGCC26XX_Object *oldObject; + List_Elem *oldJob; + List_Elem *newJob; + uintptr_t key; + + /* We need to perform the TRNG HW -> entropy pool -> job copying atomically. + * The TRNGCC26XX_hwiFxn() is used by TRNG_generateEntropy() to kick off + * the entropy generation and deplete the entropy pool from any context. + * If we did not do this atomically, we might interrupt an ongoing job and + * change minimum entropy content settings or ISR priorities, call a + * callback function twice, mess up the queue, etc. + */ + key = HwiP_disable(); + + /* Only access the TRNG hardware if it is already powered and running. + * Otherwise, we might cause a hard fault. + */ + if (trngActive == true) + { + interruptStatus = TRNGStatusGet(); + TRNGIntClear(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + + if (interruptStatus & TRNG_NUMBER_READY) + { + + TRNGCC26XX_fillEntropyPool(interruptStatus); + + /* Stop the TRNG. It is fairly inexpensive to start/restart the + * TRNG after ever 64-bits and simplifies our implementation and + * makes it easier to keep the TRNG off while not in use to save + * power. + */ + TRNGCC26XX_stopTrng(); + } + } + + /* Handle the head of the job queue. This may be an ongoing job or a job + * that was just added and the TRNG is idle. + */ + oldJob = List_head(&jobList); + if (oldJob != NULL) + { + oldObject = (TRNGCC26XX_Object *)oldJob; + + /* Copy from the pool to the job destination. There may be no entropy + * in the pool. In that case, this call does nothing. + */ + TRNGCC26XX_copyToClient(oldObject); + + /* If we managed to fulfill the request either because the pool + * contained enough entropy to do so immediately or because we just + * finished generating the last bytes needed, removed the job from the + * head of the queue and mark the old job as completed. + */ + if (oldObject->entropyGenerated >= oldObject->entropyRequested) + { + oldJobComplete = true; + + List_remove(&jobList, oldJob); + oldObject->isEnqueued = false; + } + } + + /* Only attempt to start a new job if there is no active job in progress */ + if (trngActive == false) + { + /* Check if there is a job in the queue after we potentially completed + * the one above. + */ + newJob = List_head(&jobList); + if (newJob != NULL) + { + /* If there is another job queued, start it. */ + TRNGCC26XX_startJob(((TRNGCC26XX_Object *)newJob)->handle); + } + else if (StructRingBuf_isFull(&entropyPool) == false) + { + /* If no other job is queued, start the TRNG asynchronously to refill + * the pool. + */ + TRNGCC26XX_startTrng(~0, true, TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT); + } + } + + HwiP_restore(key); + + /* If we finished the old job above, unblock the job's task in blocking + * mode or call the callback function in callback mode. This is purposefully + * done outside the critical section to avoid the callback function being + * called with interrupts disabled. + */ + if (oldJobComplete) + { + TRNGCC26XX_serviceJob(((TRNGCC26XX_Object *)oldJob)->handle); + } +} + +/* + * ======== TRNGCC26XX_startJob ======== + * Kick off the TRNG with the settings specified by the job. + */ +static void TRNGCC26XX_startJob(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object = handle->object; + TRNGCC26XX_HWAttrs const *hwAttrs = handle->hwAttrs; + + TRNGCC26XX_startTrng(hwAttrs->intPriority, + object->returnBehavior != TRNG_RETURN_BEHAVIOR_POLLING, + object->samplesPerCycle); +} + +/* + * ======== TRNGCC26XX_startTrng ======== + * Start the TRNG with specified settings. + */ +static void TRNGCC26XX_startTrng(uint32_t intPriority, bool enableInterrupts, uint32_t samplesPerCycle) +{ + + trngActive = true; + + Power_setDependency(PowerCC26XX_PERIPH_TRNG); + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + HwiP_setPriority(INT_TRNG_IRQ, intPriority); + + /* We need to set the HWI function and priority since the same physical interrupt is shared by multiple + * driver instances and they all need to coexist. Whenever a driver starts an operation, it + * registers its HWI callback with the OS. + */ + TRNGIntClear(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + if (enableInterrupts) + { + TRNGIntEnable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + } + else + { + TRNGIntDisable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + } + + /* The first argument copies arg2 when set to zero - this instructs + * the TRNG to sample exactly samplesPerCycle times. The final argument + * causes the samples to happen each clock cycle. + */ + TRNGConfigure(0, samplesPerCycle, 0); + TRNGEnable(); +} + +/* + * ======== TRNGCC26XX_stopTrng ======== + */ +static void TRNGCC26XX_stopTrng(void) +{ + + TRNGDisable(); + + TRNGIntClear(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + Power_releaseDependency(PowerCC26XX_PERIPH_TRNG); + + trngActive = false; +} + +/* + * ======== TRNG_init ======== + */ +void TRNG_init(void) +{ + uintptr_t key; + + key = HwiP_disable(); + + if (!isInitialized) + { + + HwiP_construct(&(TRNGCC26XX_hwi), INT_TRNG_IRQ, TRNGCC26XX_hwiFxn, NULL); + + /* Create the ring buffer that we keep our entropy pool in. It is + * refilled asynchronously whenever depleted. It used an item-size of + * 64 bits because the TRNG can only generate at minimum 64 bits at a + * time. + */ + StructRingBuf_construct(&entropyPool, + entropyPoolBuffer, + sizeof(entropyPoolBuffer) / sizeof(entropyPoolBuffer[0]), + sizeof(entropyPoolBuffer[0])); + + /* Kick off initial filling of entropy pool. Most of this time is + * shared with qualification of the SCLK_LF so we do not spend much + * additional time in IDLE as opposed to STANDBY. + */ + TRNGCC26XX_startTrng(~0, true, TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT); + + isInitialized = true; + } + + HwiP_restore(key); +} + +/* + * ======== TRNGCC26XX_construct ======== + */ +TRNG_Handle TRNG_construct(TRNG_Config *config, const TRNG_Params *params) +{ + TRNG_Handle handle; + TRNGCC26XX_Object *object; + TRNGCC26XX_HWAttrs const *hwAttrs; + uintptr_t key; + + handle = config; + object = handle->object; + hwAttrs = handle->hwAttrs; + + key = HwiP_disable(); + + if (object->isOpen || !isInitialized) + { + HwiP_restore(key); + return NULL; + } + + object->isOpen = true; + object->isEnqueued = false; + + HwiP_restore(key); + + /* If params are NULL, use defaults */ + if (params == NULL) + { + params = &TRNG_defaultParams; + } + + /* For callback mode, check if at least one of the + * callback function pointers is set. */ + if ((params->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) && (params->cryptoKeyCallbackFxn == NULL) && + (params->randomBytesCallbackFxn == NULL)) + { + return NULL; + } + + object->returnBehavior = params->returnBehavior; + object->semaphoreTimeout = params->timeout; + object->cryptoKeyCallbackFxn = params->cryptoKeyCallbackFxn; + object->randomBytesCallbackFxn = params->randomBytesCallbackFxn; + object->handle = handle; + + if (hwAttrs->samplesPerCycle >= TRNGCC26XX_SAMPLES_PER_CYCLE_MIN && + hwAttrs->samplesPerCycle <= TRNGCC26XX_SAMPLES_PER_CYCLE_MAX) + { + + object->samplesPerCycle = hwAttrs->samplesPerCycle; + } + else + { + object->samplesPerCycle = TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT; + } + + SemaphoreP_constructBinary(&object->operationSemaphore, 0); + + return handle; +} + +/* + * ======== TRNG_close ======== + */ +void TRNG_close(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object; + + /* Get the pointer to the object and hwAttrs */ + object = handle->object; + + SemaphoreP_destruct(&object->operationSemaphore); + + /* Mark the module as available */ + object->isOpen = false; +} + +/* + * ======== TRNGCC26XX_waitForResult ======== + */ +static int_fast16_t TRNGCC26XX_waitForResult(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object = handle->object; + int_fast16_t status = TRNG_STATUS_ERROR; + + /* If we need to generate more entropy for a request, we will need to + * work off the job queue to get to the current request. When that is + * finished, the TRNGCC26XX_hwiFxn() will kick off an asynchronous refilling + * of the entropy pool. + */ + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING) + { + + /* Repeat until we have generated enough entropy. */ + while (object->entropyGenerated < object->entropyRequested) + { + /* Wait until the TRNG has generated 64 bits of entropy */ + do + { + CPUdelay(1); + } while (!(TRNGStatusGet() & (TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN))); + + TRNGCC26XX_hwiFxn((uintptr_t)NULL); + } + + status = object->returnStatus; + } + /* In blocking mode, we simply pend until the ISR posts our driver's + * semaphore when our job is complete. + */ + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + + SemaphoreP_pend(&object->operationSemaphore, object->semaphoreTimeout); + + status = object->returnStatus; + } + /* In callback mode, we always return with status success from this + * function. + */ + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) + { + status = TRNG_STATUS_SUCCESS; + } + + return status; +} + +/* + * ======== TRNGCC26XX_setSamplesPerCycle ======== + * samplesPerCycle must be between 2^8 and 2^24 (256 and 16777216) + */ +int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle) +{ + TRNGCC26XX_Object *object = handle->object; + + object->samplesPerCycle = samplesPerCycle; + return TRNG_STATUS_SUCCESS; +} + +/* + * ======== TRNG_generateEntropy ======== + */ +int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey *entropy) +{ + return TRNG_generateKey(handle, entropy); +} + +/* + * ======== TRNG_generateKey ======== + */ +int_fast16_t TRNG_generateKey(TRNG_Handle handle, CryptoKey *entropy) +{ + TRNGCC26XX_Object *object = handle->object; + + if ((entropy == NULL) || (entropy->u.plaintext.keyMaterial == NULL) || + (entropy->encoding != CryptoKey_BLANK_PLAINTEXT) || (entropy->u.plaintext.keyLength == 0)) + { + return TRNG_STATUS_INVALID_INPUTS; + } + + object->entropyGenerated = 0; + object->entropyKey = entropy; + object->entropyBuffer = entropy->u.plaintext.keyMaterial; + object->entropyRequested = entropy->u.plaintext.keyLength; + + return TRNG_getRandom(handle); +} + +/* + * ======== TRNG_getRandomBytes ======== + */ +int_fast16_t TRNG_getRandomBytes(TRNG_Handle handle, void *randomBytes, size_t randomBytesSize) +{ + TRNGCC26XX_Object *object = handle->object; + + if ((randomBytes == NULL) || (randomBytesSize == 0)) + { + return TRNG_STATUS_INVALID_INPUTS; + } + + object->entropyGenerated = 0; + object->entropyKey = NULL; + object->entropyBuffer = randomBytes; + object->entropyRequested = randomBytesSize; + + return TRNG_getRandom(handle); +} + +/* + * ======== TRNG_getRandom ======== + */ +static int_fast16_t TRNG_getRandom(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object = handle->object; + uintptr_t key; + bool preemptRefilling; + bool preemptJob; + + /* Initialize returnStatus */ + object->returnStatus = TRNG_STATUS_ERROR; + + key = HwiP_disable(); + + /* We need to turn off the TRNG interrupt if we are about to start a new + * polling job and the TRNG is already running. Otherwise, we might get + * into the situation where we start polling in waitForResult but interrupts + * are turned on. Then it is a race condition whether the loop's + * TRNGStatusGet() call manages to catch the updated status or the ISR + * comes in and clears it first. At best, the latter would cause the polling + * job to require longer than needed. At worst, it could cause a fault. + */ + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING && trngActive == true) + { + + TRNGIntClear(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + TRNGIntDisable(TRNG_NUMBER_READY | TRNG_FRO_SHUTDOWN); + } + + /* If we are filling up the entropy pool in the background and are starting + * a new job with a non-default samplesPerCycle setting, we need to stop + * the ongoing refill operation and restart with the new entropy setting. + * Otherwise, we might have to wait up to 5ms until the refill operation + * completes when we only want the minimum amount of entropy. + */ + preemptRefilling = object->samplesPerCycle != TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT && List_empty(&jobList) && + trngActive == true; + + /* If we start a job with polling return behaviour from a critical section + * while a callback job is currently executing, the callback might post a + * semaphore which globally turns on interrupts and would break the critical + * section this polling job was called from. Thus, we need to preempt the + * previously executing job and immediately handle this job to avoid calling + * any callback functions from within TRNGCC26XX_waitForResult() in this call. + */ + preemptJob = object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING && !List_empty(&jobList) && trngActive == true; + + if (preemptRefilling || preemptJob) + { + TRNGCC26XX_stopTrng(); + } + + if (object->isEnqueued == false) + { + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_POLLING) + { + List_putHead(&jobList, &object->listElement); + } + else + { + List_put(&jobList, &object->listElement); + } + object->isEnqueued = true; + } + else + { + /* Throw an error as a new job was never enqueued even though + * the getRandom operation was invoked. + */ + HwiP_restore(key); + return TRNG_STATUS_ERROR; + } + + HwiP_restore(key); + + TRNGCC26XX_hwiFxn((uintptr_t)NULL); + + return TRNGCC26XX_waitForResult(handle); +} + +/* + * ======== TRNG_cancelOperation ======== + */ +int_fast16_t TRNG_cancelOperation(TRNG_Handle handle) +{ + TRNGCC26XX_Object *object = handle->object; + uintptr_t key; + List_Elem *newJob; + + key = HwiP_disable(); + + if ((trngActive == false) || (object->isEnqueued == false)) + { + HwiP_restore(key); + return TRNG_STATUS_SUCCESS; + } + + if (&object->listElement == List_head(&jobList)) + { + TRNGCC26XX_stopTrng(); + + List_remove(&jobList, &object->listElement); + + /* Check if there is a job in the queue after we potentially completed + * the one above. + */ + newJob = List_head(&jobList); + if (newJob != NULL) + { + /* If there is another job queued, start it. */ + TRNGCC26XX_startJob(((TRNGCC26XX_Object *)newJob)->handle); + } + else if (StructRingBuf_isFull(&entropyPool) == false) + { + /* If no other job is queued, start the TRNG asynchronously to refill + * the pool. + */ + TRNGCC26XX_startTrng(~0, true, TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT); + } + } + else + { + List_remove(&jobList, &object->listElement); + } + object->isEnqueued = false; + + // Clear the entropy generated so far + memset(object->entropyBuffer, 0, object->entropyRequested); + object->entropyGenerated = 0; + object->returnStatus = TRNG_STATUS_CANCELED; + + HwiP_restore(key); + + if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_BLOCKING) + { + SemaphoreP_post(&object->operationSemaphore); + } + else if (object->returnBehavior == TRNG_RETURN_BEHAVIOR_CALLBACK) + { + if (object->entropyKey != NULL) + { + object->cryptoKeyCallbackFxn(handle, object->returnStatus, object->entropyKey); + } + else + { + object->randomBytesCallbackFxn(handle, + object->returnStatus, + object->entropyBuffer, + object->entropyRequested); + } + } + + return TRNG_STATUS_SUCCESS; +} diff --git a/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.h b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.h new file mode 100644 index 00000000..0467bb4a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/trng/TRNGCC26XX.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2018-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file TRNGCC26XX.h + * + * @brief TRNG driver implementation for the CC26XX family + * + * This file should only be included in the board file to fill the TRNG_config + * struct. + * + * # Hardware + * + * The CC26XX family has a dedicated hardware TRNG based on sampling multiple + * free running oscillators. With all FROs enabled, the TRNG hardware generates + * 64 bits of entropy approximately every 5ms. The driver implementation + * chains multiple 64-bit entropy generation operations together to generate + * an arbitrary amount of entropy. + * + * # Behaviour + * + * The driver keeps a global pool of entropy available to service any requests + * immediately. If the pool is not sufficiently large or is too depleted to + * service a request, entropy will be generated until the request is serviced. + * If there is an ongoing TRNG request that the hardware is generating entropy + * for, the driver will queue any other requests and work them off in FIFO + * order. + * + * Requests issued by driver instances with polling return behaviour will + * preempt any executing requests and be serviced immediately. + * + * After the request queue is emptied, the driver will start an asynchronous + * operation in the background to refill the depleted entropy pool. + * + * # Samples Per Cycle + * + * The EIP-75t HW takes 240,000 clock cycles in the default setting to generate + * one round of output (i.e. 64 bits). This comes to 5ms on a 48MHz clock. The + * clock cycles per round can be configured to be as low as 2^8 (256) to as high + * as 2^24 (16,777,216). + * Entropy re-generation time can be tailored in a trade-off between speed of + * random number generation and amount of entropy in each of those random numbers. + */ + +#ifndef ti_drivers_TRNG_TRNGCC26XX__include +#define ti_drivers_TRNG_TRNGCC26XX__include + +#include +#include + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! @brief Minimum random samples for each entropy generation call */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MIN 256 +/*! @brief Default random samples for each entropy generation call + * + * Set to generate 64 bits of randomness in 5ms with all FROs active. */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT 240000 +/*! @brief Maximum random samples for each entropy generation call */ +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MAX 16777216 + +/*! @brief Minimum number of bytes provided by the TRNG hardware in one go. + * + * Smaller amounts can by requested in driver + * calls but the full number will always be generated. + * Part of the generated entropy will simply not be copied + * back to the target buffer if the requested length is not + * a multiple of TRNGCC26XX_MIN_BYTES_PER_ITERATION. + */ +#define TRNGCC26XX_MIN_BYTES_PER_ITERATION (2 * sizeof(uint32_t)) + +/*! @brief Default TRNGCC26XX entropy pool size in 64-bit elements + * + * By default, the entropy pool is sized to immediately fulfill a 256-bit + * entropy generation request. If we assume that the TRNG is used infrequently, + * this should greatly decrease the latency of <= 256-bit requests. + * This value may be overridden by defining it at the project level and + * recompiling the driver. + */ +#ifndef TRNGCC26XX_ENTROPY_POOL_SIZE + #define TRNGCC26XX_ENTROPY_POOL_SIZE (32 / sizeof(uint64_t)) +#endif + +/*! + * @brief TRNGCC26XX Hardware Attributes + * + * TRNG26X0 hardware attributes should be included in the board file + * and pointed to by the TRNG_config struct. + */ +typedef struct +{ + /*! @brief Crypto Peripheral's interrupt priority. + + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + + (7 << 5) will apply the lowest priority. + + (1 << 5) will apply the highest priority. + + Setting the priority to 0 is not supported by this driver. + + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the + critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief TRNG SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration + file. + */ + uint32_t swiPriority; + /*! @brief TRNG Maximum Samples per Cycle. + Changes the maximum number of randomness samples in each entropy generation cycle before dump and interrupt. + The minimum is 2^8 (256) and the maximum is 2^24 (16777216). + The default is 240000 - enough to generate 64 bits of randomness at 5MHz. + */ + uint32_t samplesPerCycle; +} TRNGCC26XX_HWAttrs; + +/*! \cond Internal APIs */ + +/*! + * The application must not access any member variables of this structure! + */ +typedef struct +{ + List_Elem listElement; /* Must start with a List_Elem + * to allow casting of List_Elem + * pointer returned by List APIs + * to TRNGCC26XX_Object pointers. + */ + TRNG_Handle handle; + TRNG_CryptoKeyCallbackFxn cryptoKeyCallbackFxn; + TRNG_RandomBytesCallbackFxn randomBytesCallbackFxn; + uint32_t samplesPerCycle; + CryptoKey *entropyKey; + uint8_t *entropyBuffer; + uint32_t semaphoreTimeout; + size_t entropyGenerated; + size_t entropyRequested; + int_fast16_t returnStatus; + TRNG_ReturnBehavior returnBehavior; + bool isOpen; + bool isEnqueued; + SemaphoreP_Struct operationSemaphore; +} TRNGCC26XX_Object; + +/*! \endcond */ + +/*! + * @brief Sets the number of entropy generation cycles before + * the results are returned. + * + * The default value is set to generate 64 bits of entropy. + * + * @pre TRNG_open() has to be called first successfully + * + * @param handle A TRNGCC26XX handle returned from TRNGCC26XX_open + * @param samplesPerCycle Number of 48MHz clock cycles to sample. Must be between 2^8 and 2^24. + * + * @sa TRNG_open() + */ +extern int_fast16_t TRNGCC26XX_setSamplesPerCycle(TRNG_Handle handle, uint32_t samplesPerCycle); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_TRNG_TRNGCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.c b/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.c new file mode 100644 index 00000000..fcaa641a --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.c @@ -0,0 +1,1256 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== UART2CC26X2.c ======== + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +/* driverlib header files */ +#include +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_ints.h) +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/uart.h) +#include DeviceFamily_constructPath(driverlib/sys_ctrl.h) +#include DeviceFamily_constructPath(driverlib/flash.h) + +/* Headers required for intrinsics */ +#if defined(__TI_COMPILER_VERSION__) + #include +#elif defined(__GNUC__) + #include +#elif defined(__IAR_SYSTEMS_ICC__) + #include +#else + #error "Unsupported compiler" +#endif + +/* Macro for using the definition of the UART2 Log module */ +Log_MODULE_USE(LogModule_UART2); + +/* Options for DMA write and read */ +#define TX_CONTROL_OPTS (UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_4 | UDMA_MODE_BASIC) +#define RX_CONTROL_OPTS (UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_4 | UDMA_MODE_BASIC) + +/* Initial invalid address of internal write buffer. Set intentionally outside + * of flash region to ensure power constraints are set correctly + */ +#define INVALID_ADDR_NOT_IN_FLASH ((const unsigned char *)0xFFFFFFFF) + +/* Maximum number of bytes that DMA can transfer */ +#define MAX_DMA_SIZE (UDMA_XFER_SIZE_MAX) + +/* Static functions */ +static void UART2CC26X2_eventCallback(UART2_Handle handle, uint32_t event, uint32_t data, void *userArg); +static void UART2CC26X2_hwiIntFxn(uintptr_t arg); +static void UART2CC26X2_initHw(UART2_Handle handle); +static void UART2CC26X2_initIO(UART2_Handle handle); +static void UART2CC26X2_finalizeIO(UART2_Handle handle); +static int UART2CC26X2_postNotifyFxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg); +static void UART2CC26X2_hwiIntWrite(uintptr_t arg); +static void UART2CC26X2_hwiIntRead(uintptr_t arg, uint32_t status); + +/* Map UART2 data length to driverlib data length */ +static const uint8_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART2_DataLen_5 */ + UART_CONFIG_WLEN_6, /* UART2_DataLen_6 */ + UART_CONFIG_WLEN_7, /* UART2_DataLen_7 */ + UART_CONFIG_WLEN_8 /* UART2_DataLen_8 */ +}; + +/* Map UART2 stop bits to driverlib stop bits */ +static const uint8_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART2_StopBits_1 */ + UART_CONFIG_STOP_TWO /* UART2_StopBits_2 */ +}; + +/* Map UART2 parity type to driverlib parity type */ +static const uint8_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART2_Parity_NONE */ + UART_CONFIG_PAR_EVEN, /* UART2_Parity_EVEN */ + UART_CONFIG_PAR_ODD, /* UART2_Parity_ODD */ + UART_CONFIG_PAR_ZERO, /* UART2_Parity_ZERO */ + UART_CONFIG_PAR_ONE /* UART2_Parity_ONE */ +}; + +/* + * Map UART2CC26X2 FIFO threshold types to driverlib TX FIFO threshold + * defines. + */ +static const uint8_t txFifoThreshold[5] = { + UART_FIFO_TX1_8, /* UART2CC26X2_FIFO_THRESHOLD_1_8 */ + UART_FIFO_TX2_8, /* UART2CC26X2_FIFO_THRESHOLD_2_8 */ + UART_FIFO_TX4_8, /* UART2CC26X2_FIFO_THRESHOLD_4_8 */ + UART_FIFO_TX6_8, /* UART2CC26X2_FIFO_THRESHOLD_6_8 */ + UART_FIFO_TX7_8 /* UART2CC26X2_FIFO_THRESHOLD_7_8 */ +}; + +/* + * Map UART2CC26X2 FIFO threshold types to driverlib RX FIFO threshold + * defines. + */ +static const uint8_t rxFifoThreshold[5] = { + UART_FIFO_RX1_8, /* UART2CC26X2_FIFO_THRESHOLD_1_8 */ + UART_FIFO_RX2_8, /* UART2CC26X2_FIFO_THRESHOLD_2_8 */ + UART_FIFO_RX4_8, /* UART2CC26X2_FIFO_THRESHOLD_4_8 */ + UART_FIFO_RX6_8, /* UART2CC26X2_FIFO_THRESHOLD_6_8 */ + UART_FIFO_RX7_8 /* UART2CC26X2_FIFO_THRESHOLD_7_8 */ +}; + +/* + * ======== uartDmaEnable ======== + * Atomic version of DriverLib UARTDMAEnable() + */ +static inline void uartDmaEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + uintptr_t key; + + key = HwiP_disable(); + /* Set the requested bits in the UART DMA control register. */ + HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; + + HwiP_restore(key); +} + +/* + * ======== uartDmaDisable ======== + * Atomic version of DriverLib UARTDMADisable() + */ +static inline void uartDmaDisable(uint32_t ui32Base, uint32_t ui32DMAFlags) +{ + uintptr_t key; + + key = HwiP_disable(); + /* Clear the requested bits in the UART DMA control register. */ + HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; + + HwiP_restore(key); +} + +/* + * ======== uartEnableCTS ======== + * CTS only version of DriverLib UARTHwFlowControlEnable() + */ +static inline void uartEnableCTS(uint32_t ui32Base) +{ + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_CTSEN); +} + +/* + * ======== uartEnableRTS ======== + * RTS only version of DriverLib UARTHwFlowControlEnable() + */ +static inline void uartEnableRTS(uint32_t ui32Base) +{ + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_RTSEN); +} + +/* + * ======== uartDisableCTS ======== + * CTS only version of DriverLib UARTHwFlowControlDisable() + */ +static inline void uartDisableCTS(uint32_t ui32Base) +{ + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_CTSEN); +} + +/* + * ======== uartDisableRTS ======== + * RTS only version of DriverLib UARTHwFlowControlDisable() + */ +static inline void uartDisableRTS(uint32_t ui32Base) +{ + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_RTSEN); +} + +/* + * ======== UART2CC26X2_getRxData ======== + * Transfer data from FIFO to ring buffer. Must be called with HWI disabled. + */ +static inline size_t UART2CC26X2_getRxData(UART2_Handle handle, size_t size) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + size_t consumed = 0; + uint8_t data; + + while (!(HWREG(hwAttrs->baseAddr + UART_O_FR) & UART_FR_RXFE) && size) + { + data = HWREG(hwAttrs->baseAddr + UART_O_DR); + Log_printf(LogModule_UART2, Log_VERBOSE, + "UART2CC26X2_getRxData: Write one byte to the ring buffer from the FIFO."); + RingBuf_put(&object->rxBuffer, data); + ++consumed; + --size; + } + + return consumed; +} + +/* + * ======== dmaChannelNum ======== + * Get the channel number from the channel bit mask + */ +static inline uint32_t dmaChannelNum(uint32_t x) +{ +#if defined(__TI_COMPILER_VERSION__) + return ((uint32_t)__clz(__rbit(x))); +#elif defined(__GNUC__) + return ((uint32_t)__builtin_ctz(x)); +#elif defined(__IAR_SYSTEMS_ICC__) + return ((uint32_t)__CLZ(__RBIT(x))); +#else + #error "Unsupported compiler" +#endif +} + +/* + * ======== UART2CC26X2_getRxStatus ======== + * Get the left-most bit set in the RX error status (OE, BE, PE, FE) + * read from the RSR register: + * bit# 3 2 1 0 + * OE BE PE FE + * e.g., if OE and FE are both set, OE wins. This will make it easier + * to convert an RX error status to a UART2 error code. + */ +static inline uint32_t UART2CC26X2_getRxStatus(uint32_t bitMask) +{ +#if defined(__TI_COMPILER_VERSION__) + return ((uint32_t)(bitMask & (0x80000000 >> __clz(bitMask)))); +#elif defined(__GNUC__) + return ((uint32_t)(bitMask & (0x80000000 >> __builtin_clz(bitMask)))); +#elif defined(__IAR_SYSTEMS_ICC__) + return ((uint32_t)(bitMask & (0x80000000 >> __CLZ(bitMask)))); +#else + #error "Unsupported compiler" +#endif +} + +/* + * Function for checking whether flow control is enabled. + */ +static inline bool UART2CC26X2_isFlowControlEnabled(UART2CC26X2_HWAttrs const *hwAttrs) +{ + return hwAttrs->flowControl == UART2_FLOWCTRL_HARDWARE; +} + +/* + * ======== UART2_close ======== + */ +void UART2_close(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Disable UART and interrupts. */ + UARTIntDisable(hwAttrs->baseAddr, + UART_INT_TX | UART_INT_RX | UART_INT_RT | UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE | + UART_INT_CTS); + + /* Both these functions will only run conditionally on writeInUse and readInUse, respectively */ + UART2_writeCancel(handle); + UART2_readCancel(handle); + + /* Releases Power constraint if rx is enabled. */ + UART2_rxDisable(handle); + + /* Disable UART. This function will wait until TX FIFO is empty before + * shutting down peripheral, otherwise the BUSY-bit will remain set and + * can cause the peripheral to get stuck. + */ + UARTDisable(hwAttrs->baseAddr); + object->state.txEnabled = false; + + /* Deallocate pins */ + UART2CC26X2_finalizeIO(handle); + + HwiP_destruct(&(object->hwi)); + SemaphoreP_destruct(&(object->writeSem)); + SemaphoreP_destruct(&(object->readSem)); + + if (object->udmaHandle) + { + UDMACC26XX_close(object->udmaHandle); + } + + /* Unregister power notification objects */ + Power_unregisterNotify(&object->postNotify); + + /* Release power dependency - i.e. potentially power down serial domain. */ + Power_releaseDependency(hwAttrs->powerId); + + object->state.opened = false; +} + +/* + * ======== UART2_flushRx ======== + */ +void UART2_flushRx(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + uintptr_t key; + + key = HwiP_disable(); + UART2Support_dmaStopRx(handle); + HwiP_restore(key); + + RingBuf_flush(&object->rxBuffer); + + /* Read RX FIFO until empty */ + while (UARTCharsAvail(hwAttrs->baseAddr)) + { + UARTCharGetNonBlocking(hwAttrs->baseAddr); + } + + /* Clear any read errors */ + UARTRxErrorClear(hwAttrs->baseAddr); + + key = HwiP_disable(); + /* Start new RX transaction */ + UART2Support_dmaStartRx(handle); + HwiP_restore(key); +} + +/* + * ======== UART2_open ======== + */ +UART2_Handle UART2_open(uint_least8_t index, UART2_Params *params) +{ + UART2_Handle handle = NULL; + uintptr_t key; + UART2CC26X2_Object *object; + UART2CC26X2_HWAttrs const *hwAttrs; + HwiP_Params hwiParams; + + if (index < UART2_count) + { + handle = (UART2_Handle) & (UART2_config[index]); + hwAttrs = handle->hwAttrs; + object = handle->object; + } + else + { + return NULL; + } + + /* Check for callback when in UART2_Mode_CALLBACK */ + if (((params->readMode == UART2_Mode_CALLBACK) && (params->readCallback == NULL)) || + ((params->writeMode == UART2_Mode_CALLBACK) && (params->writeCallback == NULL))) + { + return NULL; + } + + key = HwiP_disable(); + + if (object->state.opened) + { + HwiP_restore(key); + return NULL; + } + object->state.opened = true; + + HwiP_restore(key); + + object->state.rxEnabled = false; + object->state.txEnabled = false; + object->state.rxCancelled = false; + object->state.txCancelled = false; + object->state.overrunActive = false; + object->state.inReadCallback = false; + object->state.inWriteCallback = false; + object->state.overrunCount = 0; + object->state.readMode = params->readMode; + object->state.writeMode = params->writeMode; + object->state.readReturnMode = params->readReturnMode; + object->readCallback = params->readCallback; + object->writeCallback = params->writeCallback; + object->eventCallback = params->eventCallback; + object->eventMask = params->eventMask; + object->baudRate = params->baudRate; + object->stopBits = params->stopBits; + object->dataLength = params->dataLength; + object->parityType = params->parityType; + object->userArg = params->userArg; + + /* Set UART transaction variables to defaults. */ + object->writeBuf = INVALID_ADDR_NOT_IN_FLASH; + object->readBuf = NULL; + object->writeCount = 0; + object->readCount = 0; + object->writeSize = 0; + object->readSize = 0; + object->rxStatus = 0; + object->txStatus = 0; + object->rxSize = 0; + object->txSize = 0; + object->readInUse = false; + object->writeInUse = false; + object->udmaHandle = NULL; + + /* Set the event mask to 0 if the callback is NULL to simplify checks */ + if (object->eventCallback == NULL) + { + object->eventCallback = UART2CC26X2_eventCallback; + object->eventMask = 0; + } + + /* Register power dependency - i.e. power up and enable clock for UART. */ + Power_setDependency(hwAttrs->powerId); + + RingBuf_construct(&object->rxBuffer, hwAttrs->rxBufPtr, hwAttrs->rxBufSize); + RingBuf_construct(&object->txBuffer, hwAttrs->txBufPtr, hwAttrs->txBufSize); + + UARTDisable(hwAttrs->baseAddr); + + /* Configure IOs */ + UART2CC26X2_initIO(handle); + + /* Always succeeds */ + object->udmaHandle = UDMACC26XX_open(); + + /* Initialize the UART hardware module. Enable the UART and FIFO, but do not enable RX or TX yet. */ + UART2CC26X2_initHw(handle); + + /* Register notification function */ + Power_registerNotify(&object->postNotify, PowerCC26XX_AWAKE_STANDBY, UART2CC26X2_postNotifyFxn, (uintptr_t)handle); + + /* Create Hwi object for this UART peripheral. */ + HwiP_Params_init(&hwiParams); + hwiParams.arg = (uintptr_t)handle; + hwiParams.priority = hwAttrs->intPriority; + HwiP_construct(&(object->hwi), hwAttrs->intNum, UART2CC26X2_hwiIntFxn, &hwiParams); + + SemaphoreP_constructBinary(&(object->readSem), 0); + SemaphoreP_constructBinary(&(object->writeSem), 0); + + /* Set rx src and tx dst addresses in open, since these won't change */ + hwAttrs->dmaRxTableEntryPri->pvSrcEndAddr = (void *)(hwAttrs->baseAddr + UART_O_DR); + hwAttrs->dmaTxTableEntryPri->pvDstEndAddr = (void *)(hwAttrs->baseAddr + UART_O_DR); + + /* UART opened successfully */ + return handle; +} + +/* + * ======== UART2Support_disableRx ======== + */ +void UART2Support_disableRx(UART2_HWAttrs const *hwAttrs) +{ + UARTIntDisable(hwAttrs->baseAddr, + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE | UART_INT_RT | UART_INT_RX); + UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE | UART_INT_RT | UART_INT_RX); + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~UART_CTL_RXE; +} + +/* + * ======== UART2Support_disableTx ======== + */ +void UART2Support_disableTx(UART2_HWAttrs const *hwAttrs) +{ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~(UART_CTL_TXE); +} + +/* + * ======== UART2Support_dmaStartRx ======== + * For mutual exclusion, must be called with HWI disabled. + */ +void UART2Support_dmaStartRx(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UDMACC26XX_HWAttrs const *hwAttrsUdma = object->udmaHandle->hwAttrs; + volatile tDMAControlTable *rxDmaEntry = hwAttrs->dmaRxTableEntryPri; + unsigned char *dstAddr; + + if (object->state.rxEnabled == false) + { + /* DMA RX not enabled. No need to return a status code, this function shold never be called if RX is disabled */ + return; + } + + /* Stop DMA RX which updates the ring buffer count */ + UART2Support_dmaStopRx(handle); + + /* Decide whether to either read from the FIFO into the ring buffer, into the user-buffer, or do nothing */ + if ((object->rxSize == 0 && (object->readBuf == NULL || object->readCount == 0)) || /* a) */ + (RingBuf_getCount(&object->rxBuffer) >= object->readCount) || /* b) */ + (object->state.readMode == UART2_Mode_NONBLOCKING)) /* c) */ + { + /* Setup a DMA transaction from FIFO to ring buffer if either + * a) Currently no active DMA RX transaction, and (no user-buffer available or no more bytes left to read) + * b) There are enough bytes in the ring buffer for this current read operation + * c) The driver is setup for a nonblocking read + */ + object->rxSize = RingBuf_putPointer(&object->rxBuffer, &dstAddr); + object->state.readToRingbuf = true; + } + else if (object->rxSize > 0 && (object->readBuf == NULL || object->readCount == 0)) + { + /* If there is an active DMA transaction into the ring buffer, and there is no user-buffer available, + * then keep doing that transaction. Do nothing further here + */ + return; + } + else if (object->readBuf != NULL) + { + /* If there is a user-buffer available, and neither of the cases above are true, then the driver should setup + * a DMA transaction into the the user-buffer. Offset the transaction with the number of bytes we already have + * in the ring buffer. The bytes in the ring buffer will be copied out at a later stage, in UART2_read + */ + UART2Support_dmaStopRx(handle); + + object->rxSize = object->readCount - RingBuf_getCount(&object->rxBuffer); + dstAddr = object->readBuf + object->bytesRead + RingBuf_getCount(&object->rxBuffer); + object->state.readToRingbuf = false; + } + else + { + /* It should not be possible to reach here */ + return; + } + + /* Setup and start a DMA RX transaction, if the rxSize was set above */ + if (object->rxSize > 0) + { + object->state.overrunActive = false; + + /* Limit the transaction to the maximum DMA transfer size */ + if (object->rxSize > MAX_DMA_SIZE) + { + object->rxSize = MAX_DMA_SIZE; + } + + Log_printf(LogModule_UART2, + Log_VERBOSE, + "UART2Support_dmaStartRx: Starting DMA transfer of %d byte(s) to address 0x%x", + object->rxSize, + dstAddr); + + /* Setup DMA control-structure and destination */ + rxDmaEntry->pvDstEndAddr = dstAddr + object->rxSize - 1; + rxDmaEntry->ui32Control = RX_CONTROL_OPTS; + + /* Set the size in the control options */ + rxDmaEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE(object->rxSize); + + /* enable burst mode */ + HWREG(hwAttrsUdma->baseAddr + UDMA_O_SETBURST) = 1 << dmaChannelNum(hwAttrs->rxChannelMask); + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->rxChannelMask); + + uartDmaEnable(hwAttrs->baseAddr, UART_DMA_RX); + } +} + +/* + * ======== UART2Support_dmaStartTx ======== + * For mutual exclusion, must be called with HWI disabled. + */ +void UART2Support_dmaStartTx(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + volatile tDMAControlTable *txDmaEntry; + unsigned char *srcAddr; + + if (object->txSize > 0) + { + /* DMA TX already in progress */ + return; + } + + /* If nonblocking, set txSize to available bytes in ring buffer. Set source address to the ring buffer. */ + if (object->state.writeMode == UART2_Mode_NONBLOCKING) + { + object->txSize = RingBuf_getPointer(&object->txBuffer, &srcAddr); + } + else + { + /* Blocking or callback mode */ + object->txSize = object->writeCount; + srcAddr = (unsigned char *)object->writeBuf + object->bytesWritten; + } + + if (object->txSize > 0) + { + UARTIntDisable(hwAttrs->baseAddr, UART_INT_EOT); + + /* Invoke UART2_EVENT_TX_BEGIN callback when first enabling TX */ + if ((object->eventMask & UART2_EVENT_TX_BEGIN) && object->eventCallback && (object->state.txEnabled == false)) + { + + Log_printf(LogModule_UART2, + Log_INFO, + "UART2Support_dmaStartTx: Entering event callback with event = 0x%x and user argument = 0x%x", + UART2_EVENT_TX_BEGIN, + object->userArg); + + object->eventCallback(handle, UART2_EVENT_TX_BEGIN, 0, object->userArg); + } + + if (object->txSize > MAX_DMA_SIZE) + { + object->txSize = MAX_DMA_SIZE; + } + + Log_printf(LogModule_UART2, + Log_VERBOSE, + "UART2Support_dmaStartTx: Starting DMA transfer of %d byte(s) from address 0x%x", + object->txSize, + srcAddr); + + txDmaEntry = hwAttrs->dmaTxTableEntryPri; + txDmaEntry->pvSrcEndAddr = srcAddr + object->txSize - 1; + + txDmaEntry->ui32Control = TX_CONTROL_OPTS; + + /* Set the size in the control options */ + txDmaEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE(object->txSize); + + UDMACC26XX_channelEnable(object->udmaHandle, hwAttrs->txChannelMask); + + uartDmaEnable(hwAttrs->baseAddr, UART_DMA_TX); + + if (object->state.txEnabled == false) + { + /* Set standby constraint to guarantee transaction. Also set flash constraint if necessary */ + UART2Support_powerSetConstraint(handle, true); + object->state.txEnabled = true; + } + } +} + +/* + * ======== UART2Support_dmaStopRx ======== + * For mutual exclusion, must be called with HWI disabled. + */ +void UART2Support_dmaStopRx(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UDMACC26XX_HWAttrs const *hwAttrsUdma = object->udmaHandle->hwAttrs; + uint32_t bytesRemaining; + uint32_t rxCount; + + /* If there is a currently active DMA RX transaction */ + if (object->rxSize > 0) + { + /* Disable the RX DMA channel and stop the transfer. Disable and clear interrupts */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelMask); + uartDmaDisable(hwAttrs->baseAddr, UART_DMA_RX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelMask); + + /* Get the number of bytes that remain to be transferred */ + bytesRemaining = uDMAChannelSizeGet(hwAttrsUdma->baseAddr, dmaChannelNum(hwAttrs->rxChannelMask)); + rxCount = object->rxSize - bytesRemaining; + + Log_printf(LogModule_UART2, + Log_VERBOSE, + "UART2Support_dmaStopRx: Stop DMA transfer. Remaining number of bytes: %d", + bytesRemaining); + + /* If the driver is currently reading data into the ring buffer, update the ring buffer count with the + * number of bytes transferred into it through DMA + */ + if (object->state.readToRingbuf) + { + RingBuf_putAdvance(&object->rxBuffer, rxCount); + Log_printf(LogModule_UART2, Log_VERBOSE, + "UART2Support_dmaStopRx: Data read into ring buffer by DMA: %d byte(s)", + rxCount); + } + else + { + /* If the driver was reading data into the user-buffer, we update the number of bytes read, + * and number of bytes still to read + */ + object->readCount -= rxCount; + object->bytesRead += rxCount; + } + + /* Set the DMA rxsize to 0 to indicate that there is no active DMA transaction ongoing */ + object->rxSize = 0; + } +} + +/* + * ======== UART2Support_dmaStopTx ======== + * For mutual exclusion, must be called with HWI disabled. + */ +uint32_t UART2Support_dmaStopTx(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UDMACC26XX_HWAttrs const *hwAttrsUdma = object->udmaHandle->hwAttrs; + uint32_t bytesRemaining = 0; + uint32_t txCount; + + /* If there is currently an active DMA TX transaction */ + if (object->txSize > 0) + { + /* Disable the TX DMA channel and stop the transfer. Disable and clear interrupts */ + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->txChannelMask); + uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelMask); + + /* Get the number of bytes that remain to be transferred */ + bytesRemaining = uDMAChannelSizeGet(hwAttrsUdma->baseAddr, dmaChannelNum(hwAttrs->txChannelMask)); + txCount = object->txSize - bytesRemaining; + + Log_printf(LogModule_UART2, + Log_VERBOSE, + "UART2Support_dmaStopTx: Stop DMA transfer. Remaining number of bytes: %d", + bytesRemaining); + + /* If the driver is currently doing a nonblocking write, update the ring buffer */ + if (object->state.writeMode == UART2_Mode_NONBLOCKING) + { + Log_printf(LogModule_UART2, Log_VERBOSE, + "UART2Support_dmaStopTx: Attempt to consume %d byte(s) in the ring buffer", + txCount); + RingBuf_getConsume(&object->txBuffer, txCount); + } + else + { + /* If the driver was writing data from the user-buffer, we update the number of bytes written, + * and number of bytes still to write + */ + object->bytesWritten += txCount; + object->writeCount -= txCount; + } + + /* Set the DMA txSize to 0 to indicate that there is no active DMA transaction ongoing */ + object->txSize = 0; + } + + return bytesRemaining; +} + +/* + * ======== UART2Support_enableInts ======== + * Function to enable receive, receive timeout, and error interrupts + */ +void UART2Support_enableInts(UART2_Handle handle) +{ + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + if (object->eventCallback) + { + if (object->eventMask & UART2_EVENT_OVERRUN) + { + UARTIntClear(hwAttrs->baseAddr, UART_INT_OE); + UARTIntEnable(hwAttrs->baseAddr, UART_INT_OE); + } + } + UARTIntEnable(hwAttrs->baseAddr, UART_INT_RT); +} + +/* + * ======== UART2Support_enableRx ======== + * Call with interrupts disabled + */ +void UART2Support_enableRx(UART2_HWAttrs const *hwAttrs) +{ + /* Enable RX but not interrupts, since we may be using DMA */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_RXE; +} + +/* + * ======== UART2Support_enableTx ======== + * Enable TX - interrupts must be disabled + */ +void UART2Support_enableTx(UART2_HWAttrs const *hwAttrs) +{ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_TXE; +} + +/* + * ======== UART2Support_powerRelConstraint ======== + */ +void UART2Support_powerRelConstraint(UART2_Handle handle, bool relFlashConstraint) +{ + UART2_Object *object = handle->object; + + Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* If most significant byte of writeBuf is 0, it must be in flash */ + if (relFlashConstraint && ((((uint32_t)(object->writeBuf) & 0xF0000000) == 0x0))) + { + Power_releaseConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + + /* Reset writeBuf pointer so it wont be accidentally released again */ + object->writeBuf = INVALID_ADDR_NOT_IN_FLASH; + } +} + +/* + * ======== UART2Support_powerSetConstraint ======== + */ +void UART2Support_powerSetConstraint(UART2_Handle handle, bool setFlashConstraint) +{ + UART2_Object *object = handle->object; + + Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY); + + /* If most significant byte of writeBuf is 0, it must be in flash */ + if (setFlashConstraint && ((((uint32_t)(object->writeBuf) & 0xF0000000) == 0x0))) + { + Power_setConstraint(PowerCC26XX_NEED_FLASH_IN_IDLE); + } +} + +/* + * ======== UART2Support_rxStatus2ErrorCode ======== + * Convert RX status (OE, BE, PE, FE) to a UART2 error code. + */ +int_fast16_t UART2Support_rxStatus2ErrorCode(uint32_t errorData) +{ + uint32_t status; + + status = UART2CC26X2_getRxStatus(errorData); + return -((int_fast16_t)status); +} + +/* + * ======== UART2Support_sendData ======== + * Function to send data + */ +uint32_t UART2Support_sendData(UART2_HWAttrs const *hwAttrs, size_t size, uint8_t *buf) +{ + uint32_t writeCount = 0; + + while (size) + { + if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, *buf)) + { + break; + } + + buf++; + writeCount++; + size--; + } + + return writeCount; +} + +/* + * ======== UART2Support_txDone ======== + * Used when interrupts are not enabled. + */ +bool UART2Support_txDone(UART2_HWAttrs const *hwAttrs) +{ + if (UARTBusy(hwAttrs->baseAddr)) + { + return false; + } + + return true; +} + +/* + * ======== UART2Support_uartRxError ======== + * Function to clear RX errors + */ +int UART2Support_uartRxError(UART2_HWAttrs const *hwAttrs) +{ + int status = UART2_STATUS_SUCCESS; + uint32_t errStatus; + + /* Check for RX error since the last read */ + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + status = UART2Support_rxStatus2ErrorCode(errStatus); + UARTRxErrorClear(hwAttrs->baseAddr); /* Clear receive errors */ + + return status; +} + +/* + * ======== UART2CC26X2_eventCallback ======== + * A dummy event callback function in case the user didn't provide one + */ +static void UART2CC26X2_eventCallback(UART2_Handle handle, uint32_t event, uint32_t data, void *userArg) +{} + +/* + * ======== UART2CC26X2_hwiIntRead ======== + * Function called by Hwi to handle read-related interrupt + */ +static void UART2CC26X2_hwiIntRead(uintptr_t arg, uint32_t status) +{ + UART2_Handle handle = (UART2_Handle)arg; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UART2CC26X2_Object *object = handle->object; + void *readBufCopy; + + /* Temporarily stop RX transaction */ + UART2Support_dmaStopRx(handle); + + /* Read timeout interrupt */ + if (status & UART_INT_RT) + { + /* If the read transaction has a user buffer as destination, + * copy as much as we can from the FIFO to the buffer + */ + if (!(object->state.readToRingbuf)) + { + while (UARTCharsAvail(hwAttrs->baseAddr) && object->readCount) + { + uint8_t data = HWREG(hwAttrs->baseAddr + UART_O_DR); + *(object->readBuf + object->bytesRead) = data; + object->bytesRead++; + object->readCount--; + } + } + + /* If the read transaction is setup with the ring buffer as destination then copy as much + * as we can can from the FIFO into the ring buffer + */ + if (object->state.readToRingbuf) + { + UART2CC26X2_getRxData(handle, RingBuf_space(&object->rxBuffer)); + } + } + + /* Do not invoke callback or post semaphore if there is no active read, or readMode is nonblocking */ + if (object->readInUse && object->state.readMode != UART2_Mode_NONBLOCKING) + { + /* Read-transaction is complete if either + * a) ReadReturnMode is partial and we received a read-timeout + * b) There are no more bytes to read + */ + if (((object->state.readReturnMode == UART2_ReadReturnMode_PARTIAL) && (status & UART_INT_RT)) || + (object->readCount == 0)) + { + object->readInUse = false; + object->readCount = 0; + /* Set readBuf to NULL, but first make a copy to pass to the callback. We cannot set it to NULL after + * the callback in case another read was issued from the callback. + */ + readBufCopy = object->readBuf; + object->readBuf = NULL; + + if (object->state.readMode == UART2_Mode_CALLBACK) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2CC26X2_hwiIntRead: Entering read callback. Function pointer = 0x%x", + object->readCallback); + + object->readCallback(handle, readBufCopy, object->bytesRead, object->userArg, UART2_STATUS_SUCCESS); + } + else + { + /* Blocking mode. Post semaphore to unblock reading task */ + SemaphoreP_post(&object->readSem); + } + } + } + + /* Start another RX transaction */ + UART2Support_dmaStartRx(handle); +} + +/* + * ======== UART2CC26X2_hwiIntWrite ======== + * Function called by Hwi to handle write-related interrupt + */ +static void UART2CC26X2_hwiIntWrite(uintptr_t arg) +{ + UART2_Handle handle = (UART2_Handle)arg; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UART2CC26X2_Object *object = handle->object; + + /* DMA transaction finished. Restart in case there are more bytes to write */ + UART2Support_dmaStopTx(handle); + UART2Support_dmaStartTx(handle); + + if ((object->state.writeMode == UART2_Mode_CALLBACK) && (object->writeCount == 0) && object->writeInUse) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2CC26X2_hwiIntWrite: Entering write callback. Function pointer = 0x%x", + object->writeCallback); + + object->writeInUse = false; + object->writeCallback(handle, + (void *)object->writeBuf, + object->bytesWritten, + object->userArg, + UART2_STATUS_SUCCESS); + } + + if (object->txSize == 0) + { + /* No more data pending in the TX buffer, wait for it to finish shifting out of the transmit shift register. */ + UARTIntEnable(hwAttrs->baseAddr, UART_INT_EOT); + } +} + +/* + * ======== UART2CC26X2_hwiIntFxn ======== + * Hwi function that processes UART interrupts. + */ +static void UART2CC26X2_hwiIntFxn(uintptr_t arg) +{ + uint32_t status; + uint32_t errStatus = 0; + uint32_t event; + UART2_Handle handle = (UART2_Handle)arg; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + UART2CC26X2_Object *object = handle->object; + + /* Clear interrupts */ + status = UARTIntStatus(hwAttrs->baseAddr, true); + UARTIntClear(hwAttrs->baseAddr, status); + + Log_printf(LogModule_UART2, + Log_INFO, + "UART2CC26X2_hwiIntFxn: Entering ISR. MIS register = 0x%x", + status); + + if (status & (UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE)) + { + if (status & UART_INT_OE) + { + /* Overrun error occurred, get what we can. No need to stop + * the DMA, should already have stopped by now. + */ + UART2CC26X2_getRxData(handle, RingBuf_space(&object->rxBuffer)); + /* Throw away the rest in order to clear the overrun */ + while (!(HWREG(hwAttrs->baseAddr + UART_O_FR) & UART_FR_RXFE)) + { + volatile uint8_t data = HWREG(hwAttrs->baseAddr + UART_O_DR); + (void)data; + } + object->state.overrunCount++; + if (object->state.overrunActive == false) + { + object->state.overrunActive = true; + } + } + + errStatus = UARTRxErrorGet(hwAttrs->baseAddr); + event = UART2CC26X2_getRxStatus(errStatus & object->eventMask); + + if (event && object->eventCallback) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2CC26X2_hwiIntFxn: Entering event callback with event = 0x%x and user argument = 0x%x", + event, + object->userArg); + + object->eventCallback(handle, event, object->state.overrunCount, object->userArg); + } + object->rxStatus = UART2Support_rxStatus2ErrorCode(errStatus); + } + + /* UDMACC26XX_channelDone() checks for rxChannel bit set in REQDONE */ + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->rxChannelMask) || (status & UART_INT_RT)) + { + UART2CC26X2_hwiIntRead(arg, status); + } + + if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelMask) && (object->txSize > 0)) + { + UART2CC26X2_hwiIntWrite(arg); + } + + if (status & (UART_INT_EOT)) + { + /* End of Transmission occurred. Make sure TX FIFO is truly empty before disabling TX */ + while (HWREG(hwAttrs->baseAddr + UART_O_FR) & UART_FR_BUSY) {} + /* Disable TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) &= ~UART_CTL_TXE; + + if (object->state.txEnabled) + { + object->state.txEnabled = false; + + if ((object->eventMask & UART2_EVENT_TX_FINISHED) && object->eventCallback) + { + Log_printf(LogModule_UART2, + Log_INFO, + "UART2CC26X2_hwiIntFxn: Entering event callback with event = 0x%x and user argument = 0x%x", + UART2_EVENT_TX_FINISHED, + object->userArg); + + object->eventCallback(handle, UART2_EVENT_TX_FINISHED, 0, object->userArg); + } + + /* Release standby constraint because there are no active transactions. Also release flash constraint */ + UART2Support_powerRelConstraint(handle, true); + } + + UARTIntDisable(hwAttrs->baseAddr, UART_INT_EOT); + + if (object->state.writeMode == UART2_Mode_BLOCKING) + { + /* Unblock write-function, which is waiting for EOT */ + SemaphoreP_post(&object->writeSem); + } + } +} + +/* + * ======== UART2CC26X2_initHw ======== + */ +static void UART2CC26X2_initHw(UART2_Handle handle) +{ + ClockP_FreqHz freq; + UART2CC26X2_Object *object = handle->object; + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Configure frame format and baudrate. UARTConfigSetExpClk() disables + * the UART and does not re-enable it, so call this function first. + */ + ClockP_getCpuFreq(&freq); + UARTConfigSetExpClk(hwAttrs->baseAddr, + freq.lo, + object->baudRate, + dataLength[object->dataLength] | stopBits[object->stopBits] | parityType[object->parityType]); + + /* Clear all UART interrupts */ + UARTIntClear(hwAttrs->baseAddr, + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX | + UART_INT_CTS); + + /* Set TX interrupt FIFO level and RX interrupt FIFO level */ + UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr], rxFifoThreshold[hwAttrs->rxIntFifoThr]); + + /* If Flow Control is enabled, configure hardware flow control for CTS and/or RTS. */ + if (UART2CC26X2_isFlowControlEnabled(hwAttrs) && (hwAttrs->ctsPin != GPIO_INVALID_INDEX)) + { + uartEnableCTS(hwAttrs->baseAddr); + } + else + { + uartDisableCTS(hwAttrs->baseAddr); + } + + if (UART2CC26X2_isFlowControlEnabled(hwAttrs) && (hwAttrs->rtsPin != GPIO_INVALID_INDEX)) + { + uartEnableRTS(hwAttrs->baseAddr); + } + else + { + uartDisableRTS(hwAttrs->baseAddr); + } + + /* Enable UART FIFOs */ + HWREG(hwAttrs->baseAddr + UART_O_LCRH) |= UART_LCRH_FEN; + + /* Enable the UART module, but not RX or TX */ + HWREG(hwAttrs->baseAddr + UART_O_CTL) |= UART_CTL_UARTEN; + + if ((hwAttrs->rxChannelMask > 0) && (hwAttrs->txChannelMask > 0)) + { + /* Prevent DMA interrupt on UART2CC26X2_open() */ + uartDmaDisable(hwAttrs->baseAddr, UART_DMA_RX); + UDMACC26XX_channelDisable(object->udmaHandle, hwAttrs->rxChannelMask); + UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelMask); + + /* Disable the alternate DMA structure */ + UDMACC26XX_disableAttribute(object->udmaHandle, dmaChannelNum(hwAttrs->rxChannelMask), UDMA_ATTR_ALTSELECT); + UDMACC26XX_disableAttribute(object->udmaHandle, dmaChannelNum(hwAttrs->txChannelMask), UDMA_ATTR_ALTSELECT); + } +} + +/* + * ======== UART2CC26X2_initIO ======== + */ +static void UART2CC26X2_initIO(UART2_Handle handle) +{ + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + /* Make sure RX and CTS pins have their input buffers enabled, then apply the correct mux */ + GPIO_setConfigAndMux(hwAttrs->txPin, GPIO_CFG_NO_DIR, hwAttrs->txPinMux); + GPIO_setConfigAndMux(hwAttrs->rxPin, GPIO_CFG_INPUT, hwAttrs->rxPinMux); + + if (UART2CC26X2_isFlowControlEnabled(hwAttrs)) + { + GPIO_setConfigAndMux(hwAttrs->ctsPin, GPIO_CFG_INPUT, hwAttrs->ctsPinMux); + GPIO_setConfigAndMux(hwAttrs->rtsPin, GPIO_CFG_NO_DIR, hwAttrs->rtsPinMux); + } +} + +/* + * ======== UART2CC26X2_finalizeIO ======== + */ +static void UART2CC26X2_finalizeIO(UART2_Handle handle) +{ + UART2CC26X2_HWAttrs const *hwAttrs = handle->hwAttrs; + + GPIO_resetConfig(hwAttrs->txPin); + GPIO_resetConfig(hwAttrs->rxPin); + + if (UART2CC26X2_isFlowControlEnabled(hwAttrs)) + { + GPIO_resetConfig(hwAttrs->ctsPin); + GPIO_resetConfig(hwAttrs->rtsPin); + } +} + +/* + * ======== UART2CC26X2_postNotifyFxn ======== + * Called by Power module when waking up from LPDS. + */ +static int UART2CC26X2_postNotifyFxn(unsigned int eventType, uintptr_t eventArg, uintptr_t clientArg) +{ + /* Reconfigure the hardware if returning from sleep */ + if (eventType == PowerCC26XX_AWAKE_STANDBY) + { + UART2CC26X2_initHw((UART2_Handle)clientArg); + } + + return Power_NOTIFYDONE; +} diff --git a/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.h b/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.h new file mode 100644 index 00000000..0b7313c0 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/uart2/UART2CC26X2.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UART2CC26X2.h + * + * @brief UART driver implementation for a CC26X2 UART controller + * + * The UART header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref UART2.h for a complete description of APIs and examples + * of use. + * + * # Unsupported Functionality # + * The UART2 driver is unable to access flash memory in the address range 0x0000 - 0x2000 + * on devices based on the Cortex M33+ core (CC26X3/CC26X4) due to security constraints. + * + * ============================================================================ + */ + +#ifndef ti_drivers_uart2_UART2CC26X2__include +#define ti_drivers_uart2_UART2CC26X2__include + +#include +#include + +#include +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(driverlib/udma.h) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Size of the TX and RX FIFOs is 32 items */ +#define UART2CC26X2_FIFO_SIZE 32 + +/*! + * @brief UART TX/RX interrupt FIFO threshold select + * + * Defined FIFO thresholds for generation of both TX interrupt and RX interrupt. + * + * @note UART2CC26X2_FIFO_THRESHOLD_1_8 should be avoided as RX FIFO threshold + * as it can lead to unreliable read operations when using UART2_ReadReturnMode_PARTIAL + */ +typedef enum +{ + UART2CC26X2_FIFO_THRESHOLD_1_8 = 0, /*!< FIFO threshold of 1/8 full */ + UART2CC26X2_FIFO_THRESHOLD_2_8 = 1, /*!< FIFO threshold of 2/8 full */ + UART2CC26X2_FIFO_THRESHOLD_4_8 = 2, /*!< FIFO threshold of 4/8 full */ + UART2CC26X2_FIFO_THRESHOLD_6_8 = 3, /*!< FIFO threshold of 6/8 full */ + UART2CC26X2_FIFO_THRESHOLD_7_8 = 4 /*!< FIFO threshold of 7/8 full */ +} UART2CC26X2_FifoThreshold; + +/*! + * @brief UART2CC26X2 Hardware attributes + * + * The fields, baseAddr and intNum are used by driverlib + * APIs and therefore must be populated by + * driverlib macro definitions. These definitions are found under the + * device family in: + * - inc/hw_memmap.h + * - inc/hw_ints.h + * - driverlib/uart.h + * + * intPriority is the UART peripheral's interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's interrupt + * handler creation code, so you need to refer to the OS documentation + * for usage. For example, for SYS/BIOS applications, refer to the + * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of + * interrupt priorities. If the driver uses the ti.dpl interface + * instead of making OS calls directly, then the HwiP port handles the + * interrupt priority in an OS specific way. In the case of the SYS/BIOS + * port, intPriority is passed unmodified to Hwi_create(). + * The CC26x2 uses three of the priority bits, meaning ~0 has the same + * effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. HWI's with + * priority 0 ignore the HWI dispatcher to support zero-latency interrupts, + * thus invalidating the critical sections in this driver. + * + * A sample structure is shown below: + * @code + * const UART2CC26X2_HWAttrs uartCC26X2HWAttrs[] = { + * { + * .baseAddr = UARTA0_BASE, + * .intNum = INT_UART0_COMB, + * .intPriority = (~0), + * .flowControl = UART2_FLOWCTRL_NONE, + * .rxPin = IOID_2, + * .txPin = IOID_3, + * .ctsPin = GPIO_INVALID_INDEX, + * .rtsPin = GPIO_INVALID_INDEX, + * .rxChannelMask = 1 << UDMA_CHAN_UART0_RX, + * .txChannelMask = 1 << UDMA_CHAN_UART0_TX, + * .txIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_4_8, + * }, + * { + * .baseAddr = UART1_BASE, + * .intNum = INT_UART1_COMB, + * .intPriority = (~0), + * .flowControl = UART2_FLOWCTRL_NONE, + * .rxPin = GPIO_INVALID_INDEX, + * .txPin = GPIO_INVALID_INDEX, + * .ctsPin = GPIO_INVALID_INDEX, + * .rtsPin = GPIO_INVALID_INDEX, + * .rxChannelMask = 1 << UDMA_CHAN_UART1_RX, + * .txChannelMask = 1 << UDMA_CHAN_UART1_TX, + * .txIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_1_8, + * .rxIntFifoThr = UART2CC26X2_FIFO_THRESHOLD_4_8, + * }, + * }; + * @endcode + * + * To enable flow control, the .ctsPin and/or .rtsPin must be assigned. + * In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE. + */ + +typedef struct +{ + UART2_BASE_HWATTRS + volatile tDMAControlTable *dmaTxTableEntryPri; /*!< uDMA controlTable primary TX entry */ + volatile tDMAControlTable *dmaRxTableEntryPri; /*!< uDMA controlTable primary RX entry */ + uint32_t txChannelMask; /*!< Mask for uDMA TX channel number (1 << channel number) */ + uint32_t rxChannelMask; /*!< Mask for uDMA RX channel number (1 << channel number) */ + PowerCC26XX_Resource powerId; /*!< Power driver ID of the UART instance */ + int32_t txPinMux; /*!< TX PIN mux value */ + int32_t rxPinMux; /*!< RX PIN mux value */ + int32_t ctsPinMux; /*!< CTS PIN mux value for flow control */ + int32_t rtsPinMux; /*!< RTS PIN mux value for flow control */ + UART2CC26X2_FifoThreshold txIntFifoThr; /*!< UART TX interrupt FIFO threshold select */ + UART2CC26X2_FifoThreshold rxIntFifoThr; /*!< UART RX interrupt FIFO threshold select */ +} UART2CC26X2_HWAttrs; + +/*! + * @brief UART2CC26X2 Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + UART2_BASE_OBJECT + + UDMACC26XX_Handle udmaHandle; /*!< For setting power dependency */ + Power_NotifyObj postNotify; /*!< For Standby reconfiguration */ +} UART2CC26X2_Object, *UART2CC26X2_Handle; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_uart2_UART2CC26X2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/uart2/UART2Support.h b/simplelink_lpf2/source/ti/drivers/uart2/UART2Support.h new file mode 100644 index 00000000..4995face --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/uart2/UART2Support.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2020-2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file UART2Support.h + * + * @brief Holder of common helper functions for the UART driver + * + * ============================================================================ + */ + +#ifndef ti_drivers_UART2Support__include +#define ti_drivers_UART2Support__include + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Function to disable the receive and receive interrupts + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + */ +extern void UART2Support_disableRx(UART2_HWAttrs const *hwAttrs); + +/*! + * @brief Function to disable the transmit interrupt + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + */ +extern void UART2Support_disableTx(UART2_HWAttrs const *hwAttrs); + +/*! + * @brief Function to update RX ring buffer state + * + * @param[in] handle A UART2_Handle returned from UART2_open() + */ +extern void UART2Support_dmaRefreshRx(UART2_Handle handle); + +/*! + * @brief Function to configure the receive DMA + * + * @param[in] handle A UART2_Handle returned from UART2_open() + */ +extern void UART2Support_dmaStartRx(UART2_Handle handle); + +/*! + * @brief Function to configure the tramsit DMA + * + * @param[in] handle A UART2_Handle returned from UART2_open() + */ +extern void UART2Support_dmaStartTx(UART2_Handle handle); + +/*! + * @brief Function to disable the RX DMA + * + * @param[in] handle A UART2_Handle returned from UART2_open() + */ +extern void UART2Support_dmaStopRx(UART2_Handle handle); + +/*! + * @brief Function to disable the TX DMA + * + * @param[in] handle A UART2_Handle returned from UART2_open() + * + * @return Returns the number of bytes that were not transacted + * + */ +extern uint32_t UART2Support_dmaStopTx(UART2_Handle handle); + +/*! + * @brief Function to enable receive, receive timeout, and error interrupts + * + * @param[in] handle A UART2_Handle returned from UART2_open() + */ +extern void UART2Support_enableInts(UART2_Handle handle); + +/*! + * @brief Function to enable the receive + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + */ +extern void UART2Support_enableRx(UART2_HWAttrs const *hwAttrs); + +/*! + * @brief Function to enable the transmit interrupt + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + */ +extern void UART2Support_enableTx(UART2_HWAttrs const *hwAttrs); + +/*! + * @brief Function to set power constraints + * + * @param[in] handle A UART2_Handle returned from UART2_open() + * @param[in] setFlashConstraint A boolean value, on whether or not to conditionally set a "keep flash in idle" power + * constraint + */ +extern void UART2Support_powerSetConstraint(UART2_Handle handle, bool setFlashConstraint); + +/*! + * @brief Function to release power constraints + * + * @param[in] handle A UART2_Handle returned from UART2_open() + * @param[in] relFlashConstraint A boolean value, on whether or not to conditionally release a "keep flash in idle" + * power constraint + */ +extern void UART2Support_powerRelConstraint(UART2_Handle handle, bool relFlashConstraint); + +/*! + * @brief Function to convert RX error status to a UART2 error code + * + * @param[in] errorData Data indicating the UART RX error status + * + * @return Returns a status indicating success or failure of the read. + * + * @retval UART2_STATUS_SUCCESS The call was successful. + * @retval UART2_STATUS_EOVERRUN A fifo overrun occurred. + * @retval UART2_STATUS_EFRAMING A framinig error occurred. + * @retval UART2_STATUS_EBREAK A break error occurred. + * @retval UART2_STATUS_EPARITY A parity error occurred. + */ +extern int_fast16_t UART2Support_rxStatus2ErrorCode(uint32_t errorData); + +/*! + * @brief Function to send data + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + * @param[in] size The number of bytes in the buffer that should be + * written to the UART + * + * @param[in] buf A pointer to buffer containing data to be written + * to the UART + * + * @return Returns the number of bytes written + */ +extern uint32_t UART2Support_sendData(UART2_HWAttrs const *hwAttrs, size_t size, uint8_t *buf); + +/*! + * @brief Function to determine if TX is in progress + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + * + * @return Returns true if there is no TX in progress, otherwise false + */ +extern bool UART2Support_txDone(UART2_HWAttrs const *hwAttrs); + +/*! + * @brief Function to clear receive errors + * + * @param[in] hwAttrs A pointer to a UART2_HWAttrs structure + * + * @return Returns a status indicating success or failure of the read. + * + * @retval UART2_STATUS_SUCCESS The call was successful. + * @retval UART2_STATUS_EOVERRUN A fifo overrun occurred. + * @retval UART2_STATUS_EFRAMING A framinig error occurred. + * @retval UART2_STATUS_EBREAK A break error occurred. + * @retval UART2_STATUS_EPARITY A parity error occurred. + */ +extern int UART2Support_uartRxError(UART2_HWAttrs const *hwAttrs); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_UART2__include */ diff --git a/simplelink_lpf2/source/ti/drivers/utils/List.c b/simplelink_lpf2/source/ti/drivers/utils/List.c new file mode 100644 index 00000000..7e7ca480 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/List.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2015, 2017 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== List.c ======== + */ +#include +#include + +#include +#include +#include + +/* + * ======== List_clearList ======== + */ +void List_clearList(List_List *list) +{ + uintptr_t key; + + key = HwiP_disable(); + + list->head = list->tail = NULL; + + HwiP_restore(key); +} + +/* + * ======== List_get ======== + */ +List_Elem *List_get(List_List *list) +{ + List_Elem *elem; + uintptr_t key; + + key = HwiP_disable(); + + elem = list->head; + + /* See if the List was empty */ + if (elem != NULL) + { + list->head = elem->next; + if (elem->next != NULL) + { + elem->next->prev = NULL; + } + else + { + list->tail = NULL; + } + } + + HwiP_restore(key); + + return (elem); +} + +/* + * ======== List_insert ======== + */ +void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) +{ + uintptr_t key; + + key = HwiP_disable(); + + newElem->next = curElem; + newElem->prev = curElem->prev; + if (curElem->prev != NULL) + { + curElem->prev->next = newElem; + } + else + { + list->head = newElem; + } + curElem->prev = newElem; + + HwiP_restore(key); +} + +/* + * ======== List_put ======== + */ +void List_put(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = NULL; + elem->prev = list->tail; + if (list->tail != NULL) + { + list->tail->next = elem; + } + else + { + list->head = elem; + } + + list->tail = elem; + + HwiP_restore(key); +} + +/* + * ======== List_putHead ======== + */ +void List_putHead(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + elem->next = list->head; + elem->prev = NULL; + if (list->head != NULL) + { + list->head->prev = elem; + } + else + { + list->tail = elem; + } + + list->head = elem; + + HwiP_restore(key); +} + +/* + * ======== List_remove ======== + */ +void List_remove(List_List *list, List_Elem *elem) +{ + uintptr_t key; + + key = HwiP_disable(); + + /* Handle the case where the elem to remove is the last one */ + if (elem->next == NULL) + { + list->tail = elem->prev; + } + else + { + elem->next->prev = elem->prev; + } + + /* Handle the case where the elem to remove is the first one */ + if (elem->prev == NULL) + { + list->head = elem->next; + } + else + { + elem->prev->next = elem->next; + } + + HwiP_restore(key); +} diff --git a/simplelink_lpf2/source/ti/drivers/utils/List.h b/simplelink_lpf2/source/ti/drivers/utils/List.h new file mode 100644 index 00000000..8baf0dbd --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/List.h @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file List.h + * + * @brief Linked List interface for use in drivers + * + * This module provides simple doubly-link list implementation. There are two + * main structures: + * - ::List_List: The structure that holds the start of a linked list. There + * is no API to create one. It is up to the driver to provide the structure + * itself. + * - ::List_Elem: The structure that must be in the structure that is placed + * onto a linked list. Generally it is the first field in the structure. For + * example: + * @code + * typedef struct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * @endcode + * + * The following shows how to create a linked list with three elements. + * + * @code + * + denotes null-terminated + * _______ _______ _______ _______ + * |_______|----->|_______|----->|_______|--->|_______|--//---, + * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + + * | List + elem elem elem | + * |_____________________________________________________________| + * @endcode + * + * The APIs ::List_get, ::List_put, and ::List_putHead are + * atomic. The other APIs are not necessarily atomic. In other words, when + * traversing a linked list, it is up to the application to provide + * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). + * + * Initializing and adding an element to the tail and removing it + * @code + * typedef struct { + * List_Elem elem; + * void *buffer; + * } MyStruct; + * + * List_List list; + * MyStruct foo; + * MyStruct *bar; + * + * List_clearList(&list); + * List_put(&list, (List_Elem *)&foo); + * bar = (MyStruct *)List_get(&list); + * @endcode + * + * The ::List_put and ::List_get APIs are used to maintain a first-in first-out + * (FIFO) linked list. + * + * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out + * (LIFO) linked list. + * + * Traversing a list from head to tail. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * Traversing a list from tail to head. Note: thread-safety calls are + * not shown here. + * @code + * List_List list; + * List_Elem *temp; + * + * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { + * printf("address = 0x%x\n", temp); + * } + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_drivers_utils_List__include +#define ti_drivers_utils_List__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct List_Elem_ +{ + struct List_Elem_ *next; + struct List_Elem_ *prev; +} List_Elem; + +typedef struct +{ + List_Elem *head; + List_Elem *tail; +} List_List; + +/*! + * @brief Function to initialize the contents of a List_List + * + * @param list Pointer to a List_List structure that will be used to + * maintain a linked list + */ +extern void List_clearList(List_List *list); + +/*! + * @brief Function to test whether a linked list is empty + * + * @param list A pointer to a linked list + * + * @return true if empty, false if not empty + */ +static inline bool List_empty(List_List *list) +{ + return (list->head == NULL); +} + +/*! + * @brief Function to atomically get the first elem in a linked list + * + * @param list A pointer to a linked list + * + * @return Pointer the first elem in the linked list or NULL if empty + */ +extern List_Elem *List_get(List_List *list); + +/*! + * @brief Function to return the head of a linked list + * + * This function does not remove the head, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the first elem in the linked list or NULL if empty + */ +static inline List_Elem *List_head(List_List *list) +{ + return (list->head); +} + +/*! + * @brief Function to insert an elem into a linked list + * + * @param list A pointer to the linked list + * + * @param newElem New elem to insert + * + * @param curElem Elem to insert the newElem in front of. + * This value cannot be NULL. + */ +extern void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem); + +/*! + * @brief Function to return the next elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * next one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the next elem in linked list or NULL if at the end + */ +static inline List_Elem *List_next(List_Elem *elem) +{ + return (elem->next); +} + +/*! + * @brief Function to return the prev elem in a linked list + * + * This function does not remove the elem, it simply returns a pointer to + * prev one. This function is typically used when traversing a linked list. + * + * @param elem Elem in the list + * + * @return Pointer to the prev elem in linked list or NULL if at the beginning + */ +static inline List_Elem *List_prev(List_Elem *elem) +{ + return (elem->prev); +} + +/*! + * @brief Function to atomically put an elem onto the end of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the end of the linked list + */ +extern void List_put(List_List *list, List_Elem *elem); + +/*! + * @brief Function to atomically put an elem onto the head of a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to place onto the beginning of the linked list + */ +extern void List_putHead(List_List *list, List_Elem *elem); + +/*! + * @brief Function to remove an elem from a linked list + * + * @param list A pointer to the linked list + * + * @param elem Element to be removed from a linked list + */ +extern void List_remove(List_List *list, List_Elem *elem); + +/*! + * @brief Function to return the tail of a linked list + * + * This function does not remove the tail, it simply returns a pointer to + * it. This function is typically used when traversing a linked list. + * + * @param list A pointer to the linked list + * + * @return Pointer to the last elem in the linked list or NULL if empty + */ +static inline List_Elem *List_tail(List_List *list) +{ + return (list->tail); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_List__include */ diff --git a/simplelink_lpf2/source/ti/drivers/utils/Math.c b/simplelink_lpf2/source/ti/drivers/utils/Math.c new file mode 100644 index 00000000..21ae62b3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/Math.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Math.c ======== + */ + +#include + +/* + * ======== Math_divideBy1000 ======== + */ +uint32_t Math_divideBy1000(uint32_t dividend) +{ + uint32_t p1 = (dividend >> 16) * (0x83126E98 >> 16); + uint32_t p2 = (dividend & 0xFFFF) * (0x83126E98 >> 16); + p2 += (dividend >> 16) * (0x83126E98 & 0xFFFF); + p2 >>= 7; + p2 += 222; + p1 += p2 >> 9; + return p1 >> 9; +} diff --git a/simplelink_lpf2/source/ti/drivers/utils/Math.h b/simplelink_lpf2/source/ti/drivers/utils/Math.h new file mode 100644 index 00000000..3893f667 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/Math.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file Math.h + * + * @brief Math utility functions + * + */ + +#ifndef ti_drivers_utils_Math__include +#define ti_drivers_utils_Math__include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Macro to determine the minimum of two numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The first number. Either an integer or a floating point type. + * @param y The second number. Must be the same type as @c x. + * + * @return The minimum of @c x and @c y + */ +#define Math_MIN(x, y) (((x) < (y)) ? (x) : (y)) + +/*! + * @brief Macro to determine the maximum of two numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The first number. Either an integer or a floating point type. + * @param y The second number. Must be the same type as @c x. + * + * @return The maximum of @c x and @c y + */ +#define Math_MAX(x, y) (((x) > (y)) ? (x) : (y)) + +/*! + * @brief Macro to calculate the absolute value of a numbers. + * + * @warning Do not use arguments that have a side effect. For example do not + * use pre- and post-increment operators. + * + * @param x The number to calculate the absolute value of. + * Either a signed integer or a floating point type. + * + * @return The absolute value of @c x + */ +#define Math_ABS(x) ((x) < 0 ? -(x) : (x)) + +/*! + * @brief Divide a number by 1000 + * + * This function is intended for devices without a hardware divider (for example CC23X0) + * that must run divisions (that are not a power of 2) in software. + * The generic software division implementations provided by compilers are + * relatively slow. This function only supports dividing by 1000, but + * does so in ~16 cycles vs. ~95 cycles for the generic implementations. + * + * @warning Limitations: The division is only accurate for + * @c dividend < 754515999, and off by 1 for values of + * @c dividend = 754515999 + 1000*n. + * + * @param dividend The dividend to be divided by 1000. Must be below + * 754515999 for division to be accurate. + * + * @return Returns @c dividend / 1000 (see limitations) + */ +extern uint32_t Math_divideBy1000(uint32_t dividend); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_Math__include */ \ No newline at end of file diff --git a/simplelink_lpf2/source/ti/drivers/utils/Random.c b/simplelink_lpf2/source/ti/drivers/utils/Random.c new file mode 100644 index 00000000..1d45e4d9 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/Random.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== Random.c ======== + */ + +#include +#include + +#include +#include +#include +#include + +#include + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + #include + #include + #include +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + #include + #include +#endif + +#define STATE_SIZE_IN_WORDS 5 + +static uint32_t state[STATE_SIZE_IN_WORDS]; + +/* + * ======== Random_seedAutomatic ======== + */ +int_fast16_t Random_seedAutomatic(void) +{ + +#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X1_CC26X1 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 || \ + DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X4_CC26X3_CC26X4) + + TRNGCC26XX_Object object = {0}; + TRNG_Params params; + CryptoKey seedKey; + int_fast16_t status; + + /* Use minimum TRNGCC26XX_SAMPLES_PER_CYCLE_MIN since + * we do not need the full amount of entropy and only need + * to kickstart the PRNG. + */ + const TRNGCC26XX_HWAttrs hwAttrs = { + .samplesPerCycle = TRNGCC26XX_SAMPLES_PER_CYCLE_MIN, + .intPriority = ~0, + }; + + /* Allocate TRNG instance on the stack since we will not need it + * hereafter. This also helps avoid problems with hardcoded indexes. + */ + TRNG_Config config = {.object = &object, .hwAttrs = &hwAttrs}; + + params.returnBehavior = TRNG_RETURN_BEHAVIOR_POLLING; + + TRNG_init(); + + TRNG_Handle handle = TRNG_construct(&config, ¶ms); + + if (!handle) + { + return Random_STATUS_ERROR; + } + + CryptoKeyPlaintext_initBlankKey(&seedKey, (uint8_t *)state, sizeof(state)); + + status = TRNG_generateEntropy(handle, &seedKey); + + TRNG_close(handle); + + if (status != TRNG_STATUS_SUCCESS) + { + return Random_STATUS_ERROR; + } + + return Random_STATUS_SUCCESS; + +#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC23X0) + RNG_Config rngConfig; + RNG_Handle rngHandle; + RNG_Params rngParams; + RNGLPF3RF_Object rngObject = {0}; + + int_fast16_t status; + + /* + * Note: For CC23X0, RNG must be initialized by application in a task context with interrupts enabled + * using the following steps, before using Random_seedAutomatic() and prior to the use of the Radio. + * 1. Read radio noise using RCL_AdcNoise_get_samples_blocking(). This RCL function must + * be called from a task context with interrupts enabled and therefore cannot be called + * by startup code. This must be executed prior to the use of the radio. + * 2. Condition the noise to seed the RNG using RNGLPF3RF_conditionNoiseToGenerateSeed(). + * 3. Initialize the RNG from the application with RNG_init() + * RNG_init() need not be called again here or by any other code. + */ + rngConfig.object = &rngObject; + rngConfig.hwAttrs = NULL; + + RNG_Params_init(&rngParams); + + rngHandle = RNG_construct(&rngConfig, &rngParams); + + if (!rngHandle) + { + return Random_STATUS_ERROR; + } + + status = RNG_getRandomBits(rngHandle, &state, sizeof(state) * 8); + + RNG_close(rngHandle); + + if (status != RNG_STATUS_SUCCESS) + { + return Random_STATUS_ERROR; + } + + return Random_STATUS_SUCCESS; +#else + + /* If neither a TRNG nor a unique ID are available, use a constant */ + state[0] = 0x00000001; + state[1] = 0x00000002; + state[2] = 0x00000003; + state[3] = 0x00000004; + state[4] = 0x00000005; + + return Random_STATUS_SUCCESS; +#endif +} + +/* + * ======== Random_seedManual ======== + */ +void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]) +{ + uintptr_t key; + + key = HwiP_disable(); + + memcpy(state, seed, sizeof(state)); + + HwiP_restore(key); +} + +/* + * ======== Random_getNumber ======== + */ +uint32_t Random_getNumber(void) +{ + uintptr_t key; + uint32_t s; + uint32_t v; + uint32_t result; + + key = HwiP_disable(); + + /* "xorwow" XOR shift PRNG from section 3.1 of Marsaglia's "Xorshift RNGs" paper */ + v = state[3]; + + v ^= v >> 2; + v ^= v << 1; + + state[3] = state[2]; + state[2] = state[1]; + state[1] = state[0]; + s = state[0]; + + v ^= s; + v ^= s << 4; + + state[0] = v; + + state[4] += 362437; + + result = v + state[4]; + + HwiP_restore(key); + + return result; +} + +/* + * ======== Random_getBytes ======== + */ +void Random_getBytes(void *buffer, size_t bufferSize) +{ + uint32_t i; + uint32_t randomNumber; + + for (i = 0; i < bufferSize / sizeof(uint32_t); i++) + { + ((uint32_t *)buffer)[i] = Random_getNumber(); + } + + randomNumber = Random_getNumber(); + + memcpy((uint32_t *)buffer + bufferSize / sizeof(uint32_t), &randomNumber, bufferSize % sizeof(uint32_t)); +} diff --git a/simplelink_lpf2/source/ti/drivers/utils/Random.h b/simplelink_lpf2/source/ti/drivers/utils/Random.h new file mode 100644 index 00000000..d2e452a3 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/Random.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2018-2023, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file Random.h + * + * @brief Interface to generate pseudo-random numbers + * + * @warning The numbers generated by this module are not crpytographically-secure! + * Do not use this module to generate keying material or for other + * security-related purposes! + * + * This module generates non-cryptographically-secure random numbers in an + * easy to use and fast way. + * + * There is a single global state that must be initialised by calling + * Random_seedAutomatic() or Random_seedManual(). Afterwards, you can call + * Random_getNumber() or Random_getBytes() as desired. Both are thread-safe + * and protect the internal state. + * + * The pseudo-random number generator used is the "xorwow" algorithm specified in + * Marsaglia's "Xorshift RNGs" paper. It keeps 20 bytes of state that must be + * seeded and has a period of 2^160 - 2^32 before a sequence wraps. + * + * Generating a random number with this algorithm is quite fast. Random_getNumber() + * only requires 82 instructions which is 1.7us on a 48MHz Cortex M4. That includes + * disabling interrupts. + * + * @code + * + * int_fast16_t status; + * uint32_t randomNumber; + * + * status = Random_seedAutomatic(); + * + * if (status != Random_STATUS_SUCCESS) { + * while(1); + * } + * + * randomNumber = Random_getNumber(); + * + * @endcode + * + * + */ + +#ifndef ti_drivers_utils_Random__include +#define ti_drivers_utils_Random__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define Random_STATUS_SUCCESS (0) +#define Random_STATUS_ERROR (-1) + +/*! @brief Length of the seed in bytes */ +#define Random_SEED_LENGTH (20) + +/** + * @brief Seed internal state automatically + * + * This function seeds or reseeds the internal state. + * The method for generating the seed is device dependent. + * + * If a TRNG is available, it will be used to generate the seed. + * + * If a TRNG is not available, information unique to the device running + * the code will be used. This may be a unique device identifier or other + * information such as a MAC address. + * Since the seed is constant per device for devices without a TRNG, the + * number sequence will restart after each call to Random_seedAutomatic(). + * This will usually occur after rebooting the device. + * + * For CC23X0, RNG will be used to generate the seed, where the application needs to + * perform additional steps for initializing the RNG driver. + * + * If neither a TRNG nor a unique device identifier is available, + * a constant will be used. + * + * @return Returns a status code + * + * @sa Random_seedManual() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern int_fast16_t Random_seedAutomatic(void); + +/** + * @brief Set the internal state to a specified seed + * + * This function sets the internal state to the seed specified + * by the application. + * + * @param seed Seed to set the internal state to + * + * @sa Random_seedAutomatic() + * + * @post Random_getNumber() + * + * @post Random_getBytes() + */ +extern void Random_seedManual(uint8_t seed[Random_SEED_LENGTH]); + +/** + * @brief Returns a random number + * + * This function returns a random number and updates the + * internal state. + * + * @return Returns random number + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern uint32_t Random_getNumber(void); + +/** + * Returns a number of random bytes + * + * This is a convenience function that fills the specified + * array with random bytes by repeatedly calling Random_getNumber(). + * + * @param buffer Buffer to fill with random bytes + * + * @param bufferSize Size of buffer. Any value is permitted, including + * those that are not multiples of sizeof(uint32_t). + * + * @pre Random_seedAutomatic() + * @pre Random_seedManual() + */ +extern void Random_getBytes(void *buffer, size_t bufferSize); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_Random__include */ diff --git a/simplelink_lpf2/source/ti/drivers/utils/RingBuf.c b/simplelink_lpf2/source/ti/drivers/utils/RingBuf.c new file mode 100644 index 00000000..1aaeb0ed --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/RingBuf.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2015-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * ======== RingBuf_construct ======== + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, size_t bufSize) +{ + object->buffer = bufPtr; + object->length = bufSize; + object->count = 0; + object->head = bufSize - 1; + object->tail = 0; + object->maxCount = 0; +} + +/* + * ======== RingBuf_get ======== + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + + key = HwiP_disable(); + + if (!object->count) + { + HwiP_restore(key); + return -1; + } + + *data = object->buffer[object->tail]; + object->tail = (object->tail + 1) % object->length; + object->count--; + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== RingBuf_getConsume ======== + */ +int RingBuf_getConsume(RingBuf_Handle object, size_t size) +{ + unsigned int key; + + key = HwiP_disable(); + + if (object->count < size) + { + size = object->count; + } + object->count -= size; + object->tail += size; + object->tail %= object->length; + + HwiP_restore(key); + + return (size); +} + +/* + * ======== RingBuf_getCount ======== + */ +int RingBuf_getCount(RingBuf_Handle object) +{ + return (object->count); +} + +/* + * ======== RingBuf_getMaxCount ======== + */ +int RingBuf_getMaxCount(RingBuf_Handle object) +{ + return (object->maxCount); +} + +/* + * ======== RingBuf_getn ======== + */ +int RingBuf_getn(RingBuf_Handle object, unsigned char *data, size_t n) +{ + unsigned int key; + size_t removed = 0; + + key = HwiP_disable(); + if (n > object->count) + { + n = object->count; + } + while (n) + { + *data++ = object->buffer[object->tail++]; + object->tail %= object->length; + --object->count; + --n; + ++removed; + } + HwiP_restore(key); + + return (removed); +} + +/* + * ======== RingBuf_getPointer ======== + */ +int RingBuf_getPointer(RingBuf_Handle object, unsigned char **data) +{ + size_t result; + unsigned int key; + + key = HwiP_disable(); + + result = object->length - object->tail; + if (object->count < result) + { + result = object->count; + } + *data = object->buffer + object->tail; + + HwiP_restore(key); + + return (result); +} + +/* + * ======== RingBuf_flush ======== + */ +void RingBuf_flush(RingBuf_Handle object) +{ + uintptr_t key; + size_t maxCount; + + key = HwiP_disable(); + maxCount = object->maxCount; + RingBuf_construct(object, object->buffer, object->length); + object->maxCount = maxCount; + HwiP_restore(key); +} + +/* + * ======== RingBuf_isFull ======== + */ +bool RingBuf_isFull(RingBuf_Handle object) +{ + return (object->count == object->length); +} + +/* + * ======== RingBuf_peek ======== + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data) +{ + unsigned int key; + int retCount; + + key = HwiP_disable(); + + *data = object->buffer[object->tail]; + retCount = object->count; + + HwiP_restore(key); + + return (retCount); +} + +/* + * ======== RingBuf_put ======== + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data) +{ + unsigned int key; + unsigned int next; + + key = HwiP_disable(); + + if (object->count != object->length) + { + next = (object->head + 1) % object->length; + object->buffer[next] = data; + object->head = next; + object->count++; + object->maxCount = (object->count > object->maxCount) ? object->count : object->maxCount; + } + else + { + + HwiP_restore(key); + return (-1); + } + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== RingBuf_putAdvance ======== + */ +int RingBuf_putAdvance(RingBuf_Handle object, size_t size) +{ + unsigned int key; + + key = HwiP_disable(); + + if (RingBuf_space(object) < size) + { + size = RingBuf_space(object); + } + object->count += size; + object->head += size; + object->head %= object->length; + + object->maxCount = (object->count > object->maxCount) ? object->count : object->maxCount; + + HwiP_restore(key); + + return (size); +} + +/* + * ======== RingBuf_putn ======== + */ +int RingBuf_putn(RingBuf_Handle object, unsigned char *data, size_t n) +{ + unsigned int key; + size_t next; + size_t added = 0; + + key = HwiP_disable(); + if (n > RingBuf_space(object)) + { + n = RingBuf_space(object); + } + while (n) + { + next = (object->head + 1) % object->length; + object->buffer[next] = *data++; + object->head = next; + ++object->count; + --n; + ++added; + } + if (object->maxCount < object->count) + { + object->maxCount = object->count; + } + HwiP_restore(key); + + return (added); +} + +/* + * ======== RingBuf_putPointer ======== + */ +int RingBuf_putPointer(RingBuf_Handle object, unsigned char **data) +{ + size_t result; + size_t next; + unsigned int key; + + key = HwiP_disable(); + + next = (object->head + 1) % object->length; + result = object->length - next; + if (RingBuf_space(object) < result) + { + result = RingBuf_space(object); + } + *data = object->buffer + next; + + HwiP_restore(key); + + return (result); +} diff --git a/simplelink_lpf2/source/ti/drivers/utils/RingBuf.h b/simplelink_lpf2/source/ti/drivers/utils/RingBuf.h new file mode 100644 index 00000000..c836391f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/RingBuf.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_utils_RingBuf__include +#define ti_drivers_utils_RingBuf__include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + unsigned char *buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; +} RingBuf_Object, *RingBuf_Handle; + +/*! + * @brief Initialize circular buffer + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param bufPtr Pointer to data buffer to be used for the circular buffer. + * The buffer is NOT stored in RingBuf_Object. + * + * @param bufSize The size of bufPtr in number of unsigned chars. + */ +void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, size_t bufSize); + +/*! + * @brief Flush all the data from the buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + */ +void RingBuf_flush(RingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer and remove + * it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. + * + * @return Number of unsigned chars on the buffer after taking it out + * of the circular buffer. If it returns -1, the circular + * buffer was already empty and data is invalid. + */ +int RingBuf_get(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Advance the get index and decrement the buffer count. This function + * should normally be called from a context where HWI is disabled. For + * efficiency, it is incumbent on the caller to ensure mutual exclusion + * with the proper HWI lock. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param size Number of unsigned characters to advance the get index. + * + * @return Number of unsigned chars that we were able to be advanced. + */ +int RingBuf_getConsume(RingBuf_Handle object, size_t size); + +/*! + * @brief Get the number of unsigned chars currently stored on the circular + * buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return Number of unsigned chars on the circular buffer. + */ +int RingBuf_getCount(RingBuf_Handle object); + +/*! + * @brief A high-water mark indicating the largest number of unsigned chars + * stored on the circular buffer since it was constructed. + * + * @return Get the largest number of unsigned chars that were at one + * point in the circular buffer. + */ +int RingBuf_getMaxCount(RingBuf_Handle object); + +/*! + * @brief Get one or more unsigned chars from the end of the circular buffer and + * remove them. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. + * + * @param n number of unsigned chars to try and remove. + * + * @return Number of unsigned chars successfully removed from the buffer + * and copied into \a data. May be 0 or less than \a n. + */ +int RingBuf_getn(RingBuf_Handle object, unsigned char *data, size_t n); + +/*! + * @brief Get a pointer reference to the next chunk of linear memory available for + * accessing data in the buffer. This function should + * normally be called from a context where HWI is disabled. For + * efficiency, it is incumbent on the caller to ensure mutual + * exclusion with the proper HWI lock. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Reference to a pointer to set for the memory location in the + * buffer where data can accessed. + * + * @return Number of unsigned chars in linear memory where data + * can be accessed, or 0 if it's empty. + */ +int RingBuf_getPointer(RingBuf_Handle object, unsigned char **data); + +/*! + * @brief Function to determine if the circular buffer is full or not. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return true if circular buffer is full, else false. + */ +bool RingBuf_isFull(RingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer without + * removing it. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from + * the front of the circular buffer. This function does not + * remove the data from the circular buffer. Do not evaluate + * data if the count returned is equal to 0. + * + * @return Number of unsigned chars on the circular buffer. If the + * number != 0, then data will contain the unsigned char at the + * end of the circular buffer. + */ +int RingBuf_peek(RingBuf_Handle object, unsigned char *data); + +/*! + * @brief Put an unsigned char into the end of the circular buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data unsigned char to be placed at the end of the circular + * buffer. + * + * @return Number of unsigned chars on the buffer after it was added, + * or -1 if it's already full. + */ +int RingBuf_put(RingBuf_Handle object, unsigned char data); + +/*! + * @brief Advance the committed put index and increment the buffer count. This + * function should normally be called from a context where HWI is disabled. + * For efficiency, it is incumbent on the caller to ensure mutual + * exclusion with the proper HWI lock. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param size Number of unsigned characters to commit to the put index. + * + * @return Number of unsigned chars that we were able to be committed. + */ +int RingBuf_putAdvance(RingBuf_Handle object, size_t size); + +/*! + * @brief Put one or more unsigned chars into the end of the circular buffer. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data unsigned chars to be placed at the end of the circular + * buffer. + * + * @param n number of unsigned chars to try and remove. + * + * @return Number of unsigned chars placed into the buffer. May be 0 or + * less than \a n. + */ +int RingBuf_putn(RingBuf_Handle object, unsigned char *data, size_t n); + +/*! + * @brief Get a pointer reference to the next chunk of linear memory available for + * adding data to the buffer. This function should normally be called from + * a context where HWI is disabled. For efficiency, it is incumbent on the + * caller to ensure mutual exclusion with the proper HWI lock. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @param data Reference to a pointer to set for the memory location in the + * buffer where more data can be added. + * + * @return Number of unsigned chars available in linear memory where data + * can be added, or 0 if it's already full. + */ +int RingBuf_putPointer(RingBuf_Handle object, unsigned char **data); + +/*! + * @brief Return the number of unsigned characters that the buffer has space for. + * This function should normally be called from a context where HWI is + * disabled. For efficiency, it is incumbent on the caller to ensure mutual + * exclusion with the proper HWI lock. + * + * @param object Pointer to a RingBuf Object that contains the member + * variables to operate a circular buffer. + * + * @return Number of unsigned chars that the buffer has space for. + */ +static inline size_t RingBuf_space(RingBuf_Handle object) +{ + return (object->length - object->count); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_RingBuf__include */ diff --git a/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.c b/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.c new file mode 100644 index 00000000..b6eaf680 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +/* + * ======== StructRingBuf_construct ======== + */ +void StructRingBuf_construct(StructRingBuf_Handle object, void *bufPtr, size_t bufSize, size_t structSize) +{ + object->buffer = bufPtr; + object->length = bufSize; + object->count = 0; + object->head = bufSize - 1; + object->tail = 0; + object->maxCount = 0; + object->structSize = structSize; +} + +/* + * ======== StructRingBuf_get ======== + */ +int StructRingBuf_get(StructRingBuf_Handle object, void *data) +{ + unsigned int key; + + key = HwiP_disable(); + + if (!object->count) + { + HwiP_restore(key); + return -1; + } + + memcpy(data, &object->buffer[object->structSize * object->tail], object->structSize); + object->tail = (object->tail + 1) % object->length; + object->count--; + + HwiP_restore(key); + + return (object->count); +} + +/* + * ======== StructRingBuf_getCount ======== + */ +int StructRingBuf_getCount(StructRingBuf_Handle object) +{ + return (object->count); +} + +/* + * ======== StructRingBuf_isFull ======== + */ +bool StructRingBuf_isFull(StructRingBuf_Handle object) +{ + return (object->count == object->length); +} + +/* + * ======== StructRingBuf_getMaxCount ======== + */ +int StructRingBuf_getMaxCount(StructRingBuf_Handle object) +{ + return (object->maxCount); +} + +/* + * ======== StructRingBuf_peek ======== + */ +int StructRingBuf_peek(StructRingBuf_Handle object, void **data) +{ + *data = &object->buffer[object->structSize * object->tail]; + + return (object->count); +} + +/* + * ======== StructRingBuf_put ======== + */ +int StructRingBuf_put(StructRingBuf_Handle object, const void *data) +{ + unsigned int key; + unsigned int next; + + key = HwiP_disable(); + + if (object->count != object->length) + { + next = (object->head + 1) % object->length; + memcpy(&object->buffer[object->structSize * next], data, object->structSize); + object->head = next; + object->count++; + object->maxCount = (object->count > object->maxCount) ? object->count : object->maxCount; + } + else + { + + HwiP_restore(key); + return (-1); + } + + HwiP_restore(key); + + return (object->count); +} diff --git a/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.h b/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.h new file mode 100644 index 00000000..96a7de9f --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/utils/StructRingBuf.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2018-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ti_drivers_utils_StructRingBuf__include +#define ti_drivers_utils_StructRingBuf__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + uint8_t *buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; + size_t structSize; +} StructRingBuf_Object, *StructRingBuf_Handle; + +/*! + * @brief Initialize circular buffer + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @param bufPtr Pointer to data buffer to be used for the circular buffer. The + * buffer is NOT stored in StructRingBuf_Object. + * + * @param bufSize The size of bufPtr in number of structures + * + * @param structSize The size of a member structure in bytes + */ +void StructRingBuf_construct(StructRingBuf_Handle object, void *bufPtr, size_t bufSize, size_t structSize); + +/*! + * @brief Get an unsigned char from the end of the circular buffer and remove + * it. + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from the + * front of the circular buffer. + * + * @return Number of unsigned chars on the buffer after taking it out of the + * circular buffer. If it returns -1, the circular buffer was already + * empty and data is invalid. + */ +int StructRingBuf_get(StructRingBuf_Handle object, void *data); + +/*! + * @brief Get the number of unsigned chars currently stored on the circular + * buffer. + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @return Number of unsigned chars on the circular buffer. + */ +int StructRingBuf_getCount(StructRingBuf_Handle object); + +/*! + * @brief Function to determine if the circular buffer is full or not. + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @return true if circular buffer is full, else false. + */ +bool StructRingBuf_isFull(StructRingBuf_Handle object); + +/*! + * @brief A high-water mark indicating the largest number of unsigned chars + * stored on the circular buffer since it was constructed. + * + * @return Get the largest number of unsigned chars that were at one point in + * the circular buffer. + */ +int StructRingBuf_getMaxCount(StructRingBuf_Handle object); + +/*! + * @brief Get an unsigned char from the end of the circular buffer without + * remove it. + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @param data Pointer to an unsigned char to be filled with the data from the + * front of the circular buffer. This function does not remove the data + * from the circular buffer. Do not evaluate data if the count returned + * is equal to 0. + * + * @return Number of unsigned chars on the circular buffer. If the number != 0, + * then data will contain the unsigned char at the end of the circular + * buffer. + */ +int StructRingBuf_peek(StructRingBuf_Handle object, void **data); + +/*! + * @brief Put an unsigned char into the end of the circular buffer. + * + * @param object Pointer to a StructRingBuf Object that contains the member variables to + * operate a circular buffer. + * + * @param data unsigned char to be placed at the end of the circular buffer. + * + * @return Number of unsigned chars on the buffer after it was added, or -1 if + * it's already full. + */ +int StructRingBuf_put(StructRingBuf_Handle object, const void *data); + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_utils_StructRingBuf__include */ diff --git a/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.c b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.c new file mode 100644 index 00000000..d16fa81e --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.c @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(inc/hw_types.h) +#include DeviceFamily_constructPath(inc/hw_memmap.h) +#include DeviceFamily_constructPath(inc/hw_aon_pmctl.h) +#include DeviceFamily_constructPath(driverlib/ccfgread.h) + +/* Function prototypes */ +void WatchdogCC26X4_clear(Watchdog_Handle handle); +void WatchdogCC26X4_close(Watchdog_Handle handle); +int_fast16_t WatchdogCC26X4_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg); +void WatchdogCC26X4_init(Watchdog_Handle handle); +Watchdog_Handle WatchdogCC26X4_open(Watchdog_Handle handle, Watchdog_Params *params); +int_fast16_t WatchdogCC26X4_setReload(Watchdog_Handle handle, uint32_t ticks); +uint32_t WatchdogCC26X4_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds); + +/* WatchdogCC26X4 internal functions */ +static void WatchdogCC26X4_initHw(Watchdog_Handle handle); + +/* WatchdogCC26X4 global variables */ +static volatile uint32_t reloadValue; /* Reload value in ticks */ +static volatile uint32_t sclkLfFreqHz; /* SCLK_LF frequency in Hz clocking Watchdog */ + +/* Watchdog function table for CC26X4 implementation */ +const Watchdog_FxnTable WatchdogCC26X4_fxnTable = {WatchdogCC26X4_clear, + WatchdogCC26X4_close, + WatchdogCC26X4_control, + WatchdogCC26X4_init, + WatchdogCC26X4_open, + WatchdogCC26X4_setReload, + WatchdogCC26X4_convertMsToTicks}; + +#define MAX_RELOAD_VALUE 0xFFFFFFFF /* Maximum allowable reload value */ +#define MS_RATIO 1000 /* millisecond to second ratio */ +#define WATCHDOG_UNLOCK 0x1ACCE551 /* Watchdog unlocking value */ + +/* + * ======== WatchdogCC26X4_lock ======== + */ +static inline void WatchdogCC26X4_lock(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTLOCK) = 0x0; +} + +/* + * ======== WatchdogCC26X4_unlock ======== + */ +static inline void WatchdogCC26X4_unlock(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTLOCK) = WATCHDOG_UNLOCK; +} + +/* + * ======== WatchdogCC26X4_isLocked ======== + */ +static inline bool WatchdogCC26X4_isLocked(void) +{ + return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTLOCK) ? false : true); +} + +/* + * ======== WatchdogCC26X4_setReloadValue ======== + */ +static inline void WatchdogCC26X4_setReloadValue(uint32_t ticks) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTLOAD) = ticks; +} + +/* + * ======== WatchdogCC26X4_enableStall ======== + */ +static inline void WatchdogCC26X4_enableStall(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTTEST) = AON_PMCTL_WDTTEST_STALLEN; +} + +/* + * ======== WatchdogCC26X4_disableStall ======== + */ +static inline void WatchdogCC26X4_disableStall(void) +{ + HWREG(AON_PMCTL_BASE + AON_PMCTL_O_WDTTEST) = 0x0; +} + +/* + * ======== WatchdogCC26X4_clear ======== + */ +void WatchdogCC26X4_clear(Watchdog_Handle handle) +{ + unsigned int key; + + /* disable preemption while unlocking Watchdog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogCC26X4_unlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while (WatchdogCC26X4_isLocked()) {} + + WatchdogCC26X4_setReloadValue(reloadValue); + + /* lock the Watchdog configuration registers */ + WatchdogCC26X4_lock(); + + HwiP_restore(key); +} + +/* + * ======== WatchdogCC26X4_close ======== + */ +void WatchdogCC26X4_close(Watchdog_Handle handle) +{ + /* + * Not supported for CC13X4/CC26X4 - Once the Watchdog module is started + * it can only be stopped by a device reset. + */ + DebugP_assert(false); +} + +/* + * ======== WatchdogCC26X4_control ======== + * @pre Function assumes that the handle is not NULL + */ +int_fast16_t WatchdogCC26X4_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg) +{ + /* Not supported on CC13X4/CC26X4 */ + return (Watchdog_STATUS_UNDEFINEDCMD); +} + +/* + * ======== Watchdog_init ======== + */ +void WatchdogCC26X4_init(Watchdog_Handle handle) +{ + WatchdogCC26X4_Object *object = handle->object; + object->isOpen = false; +} + +/* + * ======== WatchdogCC26X4_open ======== + */ +Watchdog_Handle WatchdogCC26X4_open(Watchdog_Handle handle, Watchdog_Params *params) +{ + unsigned int key; + WatchdogCC26X4_Object *object; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + + /* disable preemption while checking if the Watchdog is open. */ + key = HwiP_disable(); + + /* Check if the Watchdog is open already with the hwAttrs */ + if (object->isOpen == true) + { + HwiP_restore(key); + DebugP_log1("Watchdog: Handle %x already in use.", (uintptr_t)handle); + return (NULL); + } + + object->isOpen = true; + HwiP_restore(key); + + /* initialize the Watchdog object */ + object->debugStallMode = params->debugStallMode; + + /* + * Register SCLK_LF source frequency. SCLK_LF sources have slightly different + * CLK frequencies and this has to be accounted for when converting milliseconds + * into watchdog ticks. + */ + switch (CCFGRead_SCLK_LF_OPTION()) + { + case CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF: + sclkLfFreqHz = 31250; + break; + case CCFGREAD_SCLK_LF_OPTION_XOSC_LF: + case CCFGREAD_SCLK_LF_OPTION_RCOSC_LF: + case CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF: + default: + sclkLfFreqHz = 32768; + break; + } + + /* initialize the watchdog hardware */ + WatchdogCC26X4_initHw(handle); + + DebugP_log1("Watchdog: handle %x opened", (uintptr_t)handle); + + /* return handle of the Watchdog object */ + return (handle); +} + +/* + * ======== WatchdogCC26X4_setReload ======== + */ +int_fast16_t WatchdogCC26X4_setReload(Watchdog_Handle handle, uint32_t ticks) +{ + unsigned int key; + + /* disable preemption while unlocking Watchdog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogCC26X4_unlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while (WatchdogCC26X4_isLocked()) {} + + /* update the reload value */ + reloadValue = ticks; + WatchdogCC26X4_setReloadValue(reloadValue); + + /* lock register access */ + WatchdogCC26X4_lock(); + + HwiP_restore(key); + + DebugP_log2("Watchdog: WDT with handle 0x%x has been set to reload to 0x%x", (uintptr_t)handle, ticks); + + return (Watchdog_STATUS_SUCCESS); +} + +/* + * ======== WatchdogCC26X4_hwInit ======== + * This function initializes the Watchdog hardware module. + * + * @pre Function assumes that the Watchdog handle is pointing to a hardware + * module which has already been opened. + */ +static void WatchdogCC26X4_initHw(Watchdog_Handle handle) +{ + unsigned int key; + uint32_t tickValue; + WatchdogCC26X4_Object *object; + WatchdogCC26X4_HWAttrs const *hwAttrs; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* convert milliseconds to watchdog timer ticks */ + tickValue = WatchdogCC26X4_convertMsToTicks(handle, hwAttrs->reloadValue); + + /* disable preemption while unlocking WatchDog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogCC26X4_unlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while (WatchdogCC26X4_isLocked()) {} + + /* set debug stall mode */ + if (object->debugStallMode == Watchdog_DEBUG_STALL_ON) + { + WatchdogCC26X4_enableStall(); + } + else + { + WatchdogCC26X4_disableStall(); + } + + /* store reloadValue for future clear() operations */ + reloadValue = tickValue; + WatchdogCC26X4_setReloadValue(reloadValue); + + /* lock the Watchdog configuration registers */ + WatchdogCC26X4_lock(); + + HwiP_restore(key); +} + +/* + * ======== WatchdogCC26X4_convertMsToTicks ======== + * This function converts the input value from milliseconds to + * Watchdog clock ticks. + */ +uint32_t WatchdogCC26X4_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds) +{ + uint32_t tickValue; + uint32_t maxConvertMs; + + /* Determine maximum allowed period with the current SCLK_LF frequency */ + maxConvertMs = (MAX_RELOAD_VALUE / sclkLfFreqHz) * MS_RATIO; + + /* convert milliseconds to watchdog timer ticks */ + /* check if value exceeds maximum */ + if (milliseconds > maxConvertMs) + { + tickValue = 0; /* return zero to indicate overflow */ + } + else + { + /* avoid overflow of the intermediate multiplication when calculating tickValue */ + tickValue = (uint32_t)(((uint64_t)milliseconds * sclkLfFreqHz) / MS_RATIO); + } + + return (tickValue); +} diff --git a/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.h b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.h new file mode 100644 index 00000000..0a14bdd5 --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26X4.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2022, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file WatchdogCC26X4.h + * + * @brief Watchdog driver implementation for CC13X4/CC26X4 + * + * # Driver include # + * The Watchdog header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Watchdog.h for a complete description of APIs. + * + * # Overview # + * + * The general Watchdog API should be used in application code, i.e. + * #Watchdog_open() should be used instead of WatchdogCC26X4_open(). The board + * file will define the device specific config, and casting in the general API + * will ensure that the correct device specific functions are called. + * + * # General Behavior # + * This Watchdog driver implementation is designed to operate on a CC13X4/CC26X4 + * device. Before using the Watchdog on CC13X4/CC26X4, the Watchdog driver is + * initialized by calling #Watchdog_init(). The Watchdog HW is configured by + * calling #Watchdog_open(). Once opened, the Watchdog will count down from + * the reload value specified in #WatchdogCC26X4_HWAttrs. If it times out, a reset + * signal will be generated. To prevent a reset, #Watchdog_clear() must be called + * to reload the timer. + * + * The Watchdog counts down at the rate of the device clock SCLK_LF. SCLK_LF will + * tick at different rates depending on the SCLK_LF source selected in CCFG, + * ranging between 31250 Hz and 32768 Hz. The Watchdog driver internally calculates + * the correct tick value depending on the target SCLK_LF source selected in CCFG. + * RCOSC_LF is an inherently inaccurate clock source and will present variations + * around the target 32768 Hz frequency. These inaccuracies have to be taken into + * consideration at the application level if RSCOC_LF is selected as the source + * of SCLK_LF. + * + * The reload value from which the Watchdog timer counts down may be changed + * during runtime using #Watchdog_setReload(). This value should be specified + * in Watchdog clock ticks and should not exceed "2^32 - 1". This corresponds to + * a timeout period of 131071 seconds, calculated at the highest rate of 32768 + * kHz. If the reload value is set to zero, the Watchdog reset is immediately + * generated. + * + * Watchdog_close() is not supported by this driver implementation. Once + * started, the Watchdog timer can only be stopped by a hardware reset. + * + * No CC13X4/CC26X4 specific command has been implemented. Any call to + * Watchdog_control() will receive the return code Watchdog_STATUS_UNDEFINEDCMD. + * + * The Watchdog module available on CC13X4/CC26X4 devices does not support reset + * masking or interrupt generation. Therefore, the two parameters \ref + * Watchdog_Params.resetMode and \ref Watchdog_Params.callbackFxn in the \ref + * Watchdog_Params struct are not supported and will be ignored by the Watchdog + * driver. + * + * # Power Management # + * Once started, the Watchdog will keep running in Active, Idle and Standby mode. + * + * # Supported Functions # + * | Generic API Function | API Function | Description | + * |------------------------------ |---------------------------------- + * |--------------------------------------------------- | | #Watchdog_init() | WatchdogCC26X4_init() | + * Initialize Watchdog driver | | #Watchdog_open() | WatchdogCC26X4_open() | + * Initialize Watchdog HW and set system dependencies | | #Watchdog_clear() | WatchdogCC26X4_clear() | + * Reload Watchdog counter | | #Watchdog_setReload() | WatchdogCC26X4_setReload() | + * Update Watchdog timer reload value in clock ticks | | #Watchdog_convertMsToTicks() | + * WatchdogCC26X4_convertMsToTicks() | Converts milliseconds to clock ticks | + * + * @note All calls should go through the generic API. Please refer to @ref Watchdog.h for a + * complete description of the generic APIs. + * + * # Use Cases # + * ## Basic Watchdog # + * In this basic watchdog example, the application is expected to start the Watchdog + * timer by calling #Watchdog_open(). If needed, #Watchdog_setReload() may be + * called to change the timeout period. If all monitored tasks are doing alright, + * #Watchdog_clear() should be called regularly to reload the counter so as to + * restart the timeout period and to avoid the Watchdog resetting the device. + * If the #Watchdog_clear() is missed and the Watchdog timer is allowed to + * timeout, the device will be reset. + * + * The following code example shows how to correctly initialize the driver's + * parameters, start the Watchdog timer and modify at runtime the timeout period. + * @code + * + * Watchdog_Handle handle; + * Watchdog_Params params; + * uint32_t tickValue; + * + * Watchdog_init(); + * Watchdog_Params_init(¶ms); + * handle = Watchdog_open(Watchdog_configIndex, ¶ms); + * // set timeout period to 100 ms + * tickValue = Watchdog_convertMsToTicks(handle, 100); + * Watchdog_setReload(handle, tickValue); + * + * @endcode + */ + +#ifndef ti_drivers_watchdog_WatchdogCC26X4__include +#define ti_drivers_watchdog_WatchdogCC26X4__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup Watchdog_STATUS + * WatchdogCC26X4_STATUS_* macros are command codes only defined in the + * WatchdogCC26X4.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26X4_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup Watchdog_CMD + * WatchdogCC26X4_CMD_* macros are command codes only defined in the + * WatchdogCC26X4.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26X4_CMD_* macros here */ + +/** @}*/ + +/*! @brief Watchdog function table for CC26X4 */ +extern const Watchdog_FxnTable WatchdogCC26X4_fxnTable; + +/*! + * @brief Watchdog hardware attributes for CC26X4 + */ +typedef struct +{ + unsigned long reloadValue; /*!< Reload value in milliseconds for Watchdog */ +} WatchdogCC26X4_HWAttrs; + +/*! + * @brief Watchdog Object for CC26X4 + * + * Not to be accessed by the user. + */ +typedef struct +{ + bool isOpen; /* Flag for open/close status */ + Watchdog_DebugMode debugStallMode; /* Mode to stall Watchdog at breakpoints */ + /* Watchdog SYS/BIOS objects */ + HwiP_Struct hwi; /* Hwi object */ +} WatchdogCC26X4_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_watchdog_WatchdogCC26X4__include */ diff --git a/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.c b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.c new file mode 100644 index 00000000..3d72804c --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2015-2020, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include DeviceFamily_constructPath(driverlib/watchdog.h) + +/* Function prototypes */ +void WatchdogCC26XX_clear(Watchdog_Handle handle); +void WatchdogCC26XX_close(Watchdog_Handle handle); +int_fast16_t WatchdogCC26XX_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg); +void WatchdogCC26XX_init(Watchdog_Handle handle); +Watchdog_Handle WatchdogCC26XX_open(Watchdog_Handle handle, Watchdog_Params *params); +int_fast16_t WatchdogCC26XX_setReload(Watchdog_Handle handle, uint32_t ticks); +uint32_t WatchdogCC26XX_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds); + +/* WatchdogCC26XX internal functions */ +static void WatchdogCC26XX_initHw(Watchdog_Handle handle); + +/* WatchdogCC26XX internal callback function */ +static void WatchdogCC26XX_callbackFxn(void); + +/* WatchdogCC26XX global variables */ +static Watchdog_Handle watchdogHandle; +static Watchdog_Callback watchdogUserCallback; + +/* Watchdog function table for CC26XX implementation */ +const Watchdog_FxnTable WatchdogCC26XX_fxnTable = {WatchdogCC26XX_clear, + WatchdogCC26XX_close, + WatchdogCC26XX_control, + WatchdogCC26XX_init, + WatchdogCC26XX_open, + WatchdogCC26XX_setReload, + WatchdogCC26XX_convertMsToTicks}; + +/* Maximum allowable setReload value */ +#define MAX_RELOAD_VALUE 0xFFFFFFFF +#define WATCHDOG_DIV_RATIO 32 /* Watchdog division ratio */ +#define MS_RATIO 1000 /* millisecond to second ratio */ + +/* + * ======== WatchdogCC26XX_callbackFxn ======== + */ +static void WatchdogCC26XX_callbackFxn(void) +{ + /* Call user callback function */ + (watchdogUserCallback)((uintptr_t)watchdogHandle); +} + +/* + * ======== WatchdogCC26XX_clear ======== + */ +void WatchdogCC26XX_clear(Watchdog_Handle handle) +{ + WatchdogIntClear(); +} + +/* + * ======== WatchdogCC26XX_close ======== + */ +void WatchdogCC26XX_close(Watchdog_Handle handle) +{ + /* + * Not supported for CC26XX - Once the INTEN bit of the WDTCTL + * register has been set, it can only be cleared by a hardware + * reset. + */ + DebugP_assert(false); +} + +/* + * ======== WatchdogCC26XX_control ======== + * @pre Function assumes that the handle is not NULL + */ +int_fast16_t WatchdogCC26XX_control(Watchdog_Handle handle, uint_fast16_t cmd, void *arg) +{ + /* No implementation yet */ + return (Watchdog_STATUS_UNDEFINEDCMD); +} + +/* + * ======== Watchdog_init ======== + */ +void WatchdogCC26XX_init(Watchdog_Handle handle) +{ + WatchdogCC26XX_Object *object = handle->object; + + object->isOpen = false; +} + +/* + * ======== WatchdogCC26XX_open ======== + */ +Watchdog_Handle WatchdogCC26XX_open(Watchdog_Handle handle, Watchdog_Params *params) +{ + unsigned int key; + WatchdogCC26XX_Object *object; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + + /* disable preemption while checking if the WatchDog is open. */ + key = HwiP_disable(); + + /* Check if the Watchdog is open already with the HWAttrs */ + if (object->isOpen == true) + { + HwiP_restore(key); + DebugP_log1("Watchdog: Handle %x already in use.", (uintptr_t)handle); + return (NULL); + } + + object->isOpen = true; + HwiP_restore(key); + + /* initialize the Watchdog object */ + object->debugStallMode = params->debugStallMode; + object->resetMode = params->resetMode; + + /* setup callback function if defined */ + if (params->callbackFxn != NULL) + { + watchdogHandle = handle; + watchdogUserCallback = params->callbackFxn; + HwiP_plug(INT_NMI_FAULT, (void *)WatchdogCC26XX_callbackFxn); + } + + /* initialize the watchdog hardware */ + WatchdogCC26XX_initHw(handle); + + DebugP_log1("Watchdog: handle %x opened", (uintptr_t)handle); + + /* return handle of the Watchdog object */ + return (handle); +} + +/* + * ======== WatchdogCC26XX_setReload ======== + */ +int_fast16_t WatchdogCC26XX_setReload(Watchdog_Handle handle, uint32_t ticks) +{ + unsigned int key; + + /* disable preemption while unlocking WatchDog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogUnlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while (WatchdogLockState() == WATCHDOG_LOCK_LOCKED) {} + + /* update the reload value */ + WatchdogReloadSet(ticks); + + /* lock register access */ + WatchdogLock(); + + HwiP_restore(key); + + DebugP_log2("Watchdog: WDT with handle 0x%x has been set to " + "reload to 0x%x", + (uintptr_t)handle, + ticks); + + return (Watchdog_STATUS_SUCCESS); +} + +/* + * ======== WatchdogCC26XX_hwInit ======== + * This function initializes the Watchdog hardware module. + * + * @pre Function assumes that the Watchdog handle is pointing to a hardware + * module which has already been opened. + */ +static void WatchdogCC26XX_initHw(Watchdog_Handle handle) +{ + unsigned int key; + uint32_t tickValue; + WatchdogCC26XX_Object *object; + WatchdogCC26XX_HWAttrs const *hwAttrs; + + /* get the pointer to the object and hwAttrs */ + object = handle->object; + hwAttrs = handle->hwAttrs; + + /* convert milliseconds to watchdog timer ticks */ + tickValue = WatchdogCC26XX_convertMsToTicks(handle, hwAttrs->reloadValue); + + /* disable preemption while unlocking WatchDog registers */ + key = HwiP_disable(); + + /* unlock the Watchdog configuration registers */ + WatchdogUnlock(); + + /* make sure the Watchdog is unlocked before continuing */ + while (WatchdogLockState() == WATCHDOG_LOCK_LOCKED) {} + + WatchdogReloadSet(tickValue); + + /* set reset mode */ + if (object->resetMode == Watchdog_RESET_ON) + { + WatchdogResetEnable(); + } + else + { + WatchdogResetDisable(); + } + + /* set debug stall mode */ + if (object->debugStallMode == Watchdog_DEBUG_STALL_ON) + { + WatchdogStallEnable(); + } + else + { + WatchdogStallDisable(); + } + + /* enable the Watchdog interrupt as a non-maskable interrupt */ + WatchdogIntTypeSet(WATCHDOG_INT_TYPE_NMI); + + /* enable the Watchdog */ + WatchdogEnable(); + + /* lock the Watchdog configuration registers */ + WatchdogLock(); + + HwiP_restore(key); +} + +/* + * ======== WatchdogCC26XX_convertMsToTicks ======== + * This function converts the input value from milliseconds to + * Watchdog clock ticks. + */ +uint32_t WatchdogCC26XX_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds) +{ + uint32_t tickValue; + uint32_t convertRatio; + uint32_t maxConvertMs; + ClockP_FreqHz freq; + + /* Determine milliseconds to clock ticks conversion ratio */ + /* Watchdog clock ticks/sec = CPU clock / WATCHDOG_DIV_RATIO */ + /* Watchdog clock ticks/ms = CPU clock / WATCHDOG_DIV_RATIO / 1000 */ + ClockP_getCpuFreq(&freq); + convertRatio = freq.lo / WATCHDOG_DIV_RATIO / MS_RATIO; + maxConvertMs = MAX_RELOAD_VALUE / convertRatio; + + /* convert milliseconds to watchdog timer ticks */ + /* check if value exceeds maximum */ + if (milliseconds > maxConvertMs) + { + tickValue = 0; /* return zero to indicate overflow */ + } + else + { + tickValue = (uint32_t)(milliseconds * convertRatio); + } + + return (tickValue); +} diff --git a/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.h b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.h new file mode 100644 index 00000000..fc8731cf --- /dev/null +++ b/simplelink_lpf2/source/ti/drivers/watchdog/WatchdogCC26XX.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2015-2021, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*!**************************************************************************** + * @file WatchdogCC26XX.h + * + * @brief Watchdog driver implementation for CC13XX/CC26XX + * + * # Driver include # + * The Watchdog header file should be included in an application as follows: + * @code + * #include + * #include + * @endcode + * + * Refer to @ref Watchdog.h for a complete description of APIs. + * + * # Overview # + * + * The general Watchdog API should be used in application code, i.e. + * #Watchdog_open() should be used instead of WatchdogCC26XX_open(). The board + * file will define the device specific config, and casting in the general API + * will ensure that the correct device specific functions are called. + * + * # General Behavior # + * This Watchdog driver implementation is designed to operate on a CC13XX/CC26XX + * device. Before using the Watchdog in CC13XX/CC26XX, the Watchdog driver is + * initialized by calling #Watchdog_init(). The Watchdog HW is configured by + * calling #Watchdog_open(). Once opened, the Watchdog will count down from + * the reload value specified in #WatchdogCC26XX_HWAttrs. If it times out, a + * non-maskable interrupt will be triggered, the Watchdog interrupt flag will + * be set, and a user-provided callback function will be called. If reset is + * enabled in the #Watchdog_Params and the Watchdog timer is allowed to time + * out again while the interrupt flag is still pending, a reset signal will be + * generated. To prevent a reset, #Watchdog_clear() must be called to clear the + * interrupt flag and to reload the timer. + * + * The Watchdog counts down at a rate of the device clock SCLK_HF (48 MHz) + * divided by a fixed-division ratio of 32, which equals to 1.5 MHz. The + * Watchdog rate will change if SCLK_HF deviates from 48 MHz. + * + * @note The Watchdog interrupt is configured as a non-maskable interrupt + * (NMI) and the user-defined callback function is called in the context of + * NMI. Because the Watchdog interrupt is non-maskable, it is not safe to call + * any BIOS APIs from the Watchdog callback function. Calls to DPL and TIDRIVERS + * APIs should also be avoided given that they may indirectly make calls to BIOS + * APIs. Furthermore, the watchdog callback should only be reached if the + * watchdog times out. This should indicate an error event and allow logging + * or other housekeeping before resetting the device. Clearing of the watchdog + * and checking alive signals should be done in another execution context. + * + * The reload value from which the Watchdog timer counts down may be changed + * during runtime using #Watchdog_setReload(). This value should be specified + * in Watchdog clock ticks and should not exceed the maximum value of 32 bits, + * which corresponds to a timeout period of 2863.3 seconds at the Watchdog rate + * of 1.5 MHz. If the reload value is set to zero, the Watchdog interrupt is + * immediately generated. + * + * Since the device is not reset on the first Watchdog timeout, the maximum + * time lapse between the time when the device gets locked up and the time when + * it is reset can be up to two Watchdog timeout periods. + * + * Watchdog_close() is not supported by this driver implementation. Once + * started, the Watchdog timer can only be stopped by a hardware reset. + * + * No CC13XX/CC26XX specific command has been implemented. Any call to + * Watchdog_control() will receive the return code Watchdog_STATUS_UNDEFINEDCMD. + * + * By default the Watchdog driver has reset enabled. However, it may be + * disabled in the #Watchdog_Params which allows the Watchdog Timer to be used + * like another timer interrupt. This functionality is not supported by + * all platforms, refer to device specific documentation for details. + * + * # Power Management # + * Once started, the Watchdog will keep running in Active or Idle mode. When + * the device enters Standby mode, the Watchdog timer will stop counting down + * but the counter value will be preserved. When the device wakes up from + * Standby, the Watchdog timer will continue to count down from the previous + * counter value. + * + * This means that if a system goes into Standby 50% of the time and the + * Watchdog reload value is set to 1 second, the Watchdog timer will actually + * time out in 2 seconds. A system which is only in Active/Idle mode for 1% of + * the time, the Watchdog timer will time out in 100 seconds. However, if a bug + * locks up the application in Active mode, the Watchdog timer will time out in + * the configured time. + * + * + * # Supported Functions # + * | Generic API Function | API Function | Description | + * |------------------------------ |---------------------------------- + * |---------------------------------------------------| | #Watchdog_init() | WatchdogCC26XX_init() | + * Initialize Watchdog driver | | #Watchdog_open() | WatchdogCC26XX_open() | + * Initialize Watchdog HW and set system dependencies| | #Watchdog_clear() | WatchdogCC26XX_clear() | Clear + * Watchdog interrupt flag and reload counter | | #Watchdog_setReload() | WatchdogCC26XX_setReload() | + * Set Watchdog timer reload value in clock ticnks | | #Watchdog_convertMsToTicks() | + * WatchdogCC26XX_convertMsToTicks() | Converts milliseconds to clock ticks | + * + * @note All calls should go through the generic API. Please refer to @ref Watchdog.h for a + * complete description of the generic APIs. + * + * # Use Cases # + * ## Basic Watchdog # + * In this basic watchdog example, the application is expected to define a + * Watchdog callback function and start the Watchdog timer by calling #Watchdog_open(). + * If needed, #Watchdog_setReload() may be called to change the timeout period. + * If all monitored tasks are doing alright, #Watchdog_clear() should be called + * regularly to reload the counter so as to restart the timeout period and to + * avoid the Watchdog interrupt being triggered. If the #Watchdog_clear() is + * missed and the Watchdog timer is allowed to timeout, the user-defined + * callback function is called. In this function, the user may do whatever is + * appropriate for the application. + * Here are some suggestions: + * - do nothing so that the timer will timeout again and trigger the reset + * - immediately reset the device + * - do self-test to check the integrity of the application + * + * @note The Watchdog interrupt is configured as a non-maskable interrupt + * (NMI) and the user-defined callback function is called in NMI context. + * Therefore it is not safe to call any OS APIs from the Watchdog callback + * function. This includes any driver calls that rely on OS APIs. + * + * The following code example shows how to define the callback function and to + * start the Watchdog timer. + * @code + * void watchdogCallback(uintptr_t handle); + * + * ... + * + * Watchdog_Handle handle; + * Watchdog_Params params; + * uint32_t tickValue; + * + * Watchdog_Params_init(¶ms); + * params.callbackFxn = watchdogCallback; + * handle = Watchdog_open(Watchdog_configIndex, ¶ms); + * // set timeout period to 100 ms + * tickValue = Watchdog_convertMsToTicks(handle, 100); + * Watchdog_setReload(handle, tickValue); + * + * ... + * + * void watchdogCallback(uintptr_t handle) + * { + * // User-defined code here + * ... + * } + * + * @endcode + */ + +#ifndef ti_drivers_watchdog_WatchdogCC26XX__include +#define ti_drivers_watchdog_WatchdogCC26XX__include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup Watchdog_STATUS + * WatchdogCC26XX_STATUS_* macros are command codes only defined in the + * WatchdogCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26XX_STATUS_* macros here */ + +/** @}*/ + +/** + * @addtogroup Watchdog_CMD + * WatchdogCC26XX_CMD_* macros are command codes only defined in the + * WatchdogCC26XX.h driver implementation and need to: + * @code + * #include + * @endcode + * @{ + */ + +/* Add WatchdogCC26XX_CMD_* macros here */ + +/** @}*/ + +/*! @brief Watchdog function table for CC26XX */ +extern const Watchdog_FxnTable WatchdogCC26XX_fxnTable; + +/*! + * @brief Watchdog hardware attributes for CC26XX + */ +typedef struct +{ + unsigned int baseAddr; /*!< Base address for Watchdog */ + unsigned long reloadValue; /*!< Reload value in milliseconds for Watchdog */ +} WatchdogCC26XX_HWAttrs; + +/*! + * @brief Watchdog Object for CC26XX + * + * Not to be accessed by the user. + */ +typedef struct +{ + bool isOpen; /* Flag for open/close status */ + Watchdog_Callback callbackFxn; /* Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /* Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /* Mode to stall Watchdog at breakpoints. + Not supported on all targets. */ + /* Watchdog SYS/BIOS objects */ + HwiP_Struct hwi; /* Hwi object */ +} WatchdogCC26XX_Object; + +#ifdef __cplusplus +} +#endif + +#endif /* ti_drivers_watchdog_WatchdogCC26XX__include */ diff --git a/simplelink_lpf2/source/ti/log/Log.h b/simplelink_lpf2/source/ti/log/Log.h new file mode 100644 index 00000000..21e1d77f --- /dev/null +++ b/simplelink_lpf2/source/ti/log/Log.h @@ -0,0 +1,1164 @@ +/* + * Copyright (c) 2019-2024 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file ti/log/Log.h + * + * @addtogroup ti_log_LOG Log Interface + * + * @brief The Log module provides APIs to instrument source code + * + * To access the LOG APIs, the application should include its header file as + * follows: + * @code + * #include + * @endcode + * + * ## Definitions ## + * + * The following terms are used throughout the log documentation. + * + * - `Log module`: A parameter passed to Log APIs to indicate which software + * module the log statement originated from. Modules also control the + * routing of logs to sinks. + * - `Log level`: The severity or importance of a given log statement. + * - `Log sink`: Also simply called a logger. This is a transport-specific + * logger implementation on the target side.
The Logging framework is + * flexible such that multiple sinks may exist in a single firmware image. + * - `Call site`: A specific invocation of a Log API in a given file or program. + * - `Record`: The binary representation of a log when it is stored or + * transported by a given sink. The log record format varies slightly with + * each sink depending on their implementation and needs. However, they all + * convey the same information. + * - Link Time Optimization (LTO): A feature of some toolchains that can + * significantly reduce the code overhead of the log statements through a + * process called dead code elimination. In order to maximize the benefits + * of this, all static libraries and application files should have LTO + * enabled. + * + * ## Summary ## + * + * The following sections describe the usage of the TI logging system + * implementation. This document will focus on the target (i.e. code that runs) + * on the embedded device. For associated PC tooling, please see the + * [README](../../../tools/log/tiutils/Readme.html) in the tools/log/tiutils/ + * folder. + * + * Design Philosophy: + * + * * Logs target code should be as efficient as possible. + * * This means that Log APIs should minimize FLASH, RAM, and execution + * overhead. + * * Complexity should be pushed to host side tooling where possible. + * * Even if this means that PC setup/tooling requirements are more complex. + * * Multiple log sink implementations shall be able to exist in a system. + * * Where applicable, multiple instances should be supported (e.g. multiple + * circular buffers to collect logs) + * * It shall be possible to remove logging entirely using the preprocessor + * * Configuration of logging should be deferred to application compile and + * link time. + * * That means that the end application builder should make decisions about + * the logging settings. This means that TI provided libraries are not + * opinionated about what log levels should be enabled or how modules + * should be routed to sinks. + * * TI's logging system will leverage SysConfig out of the box, but it should + * be possible to configure and use logging easily without the needing + * SysConfig. + * + * ## Stated Limitations ## + * + * * It is not possible to control which log sink is used for each call site. + * Routing of logs is controlled at a module level. + * * A maximum of 8 arguments is supported for variadic APIs. + * * Users may not add log statements to functions that are direct dependencies + * of delegate log functions. Not respecting this will lead to recursive + * emissions of the log statements added to the dependencies. The + * dependencies of the configured delegate function depends on which log sink + * is selected for a given log module. For example, if an application using + * the UART log sink has a Log_printf() at the application level and another + * in HwiP_disable(), the first call will be delegated to + * LogSinkUART_printf(), which then calls HwiP_disable(). This, in turn, + * triggers another Log_printf() that loops back to LogSinkUART_printf(), + * creating an endless cycle. Note that SysConfig will prevent users from + * adding such log statements. + * + * ## Anatomy of Log Statement ## + * + * At the core of the logging implementation is heavy use of the C + * preprocessor. When reading an application, the Log APIs may look like + * function calls, but the preprocessor expands them heavily. + * + * There are several ways in which the preprocessor is used. + * + * ### Global ### + * 1. To enable/disable logs globally. If `ti_log_Log_ENABLE` is not defined, + * all statements are removed by the preprocessor. This does not rely on LTO + * or any other optimization. It removes any traces of logs from the + * program. + * + * This define is pushed to `ti_utils_build_compiler.opt` whenever any Log + * module is enabled in SysConfig. + * + * ### Module ### + * 1. To enable/disable logs by module. If + * `ti_log_Log_ENABLE_=1` is not defined, all statements + * using that Log module are removed by the preprocessor. This does not rely + * on LTO or any other optimization. Removing the define removes all traces + * of the log from the compiled code. Just defining the symbol name + * `ti_log_Log_ENABLE_` without setting it to 1 will not + * include Log statements during compilation. + * + * These defines are automatically pushed to `ti_utils_build_compiler.opt` + * for all modules configured in SysConfig. + * + * Some TI libraries that have logging enabled also contain multiple log + * modules. Enabling only a subset of Log modules via the preprocessor will + * not cause the Log statements associated with the remaining Log modules to + * be removed since this is a compile-time event. The Log statements + * associated with individual modules can be removed from logging-enabled TI + * libraries by recompiling those libraries without the module-level flags + * in question. + * + * 2. If a Log Module's #Log_Module.dynamicLevelsPtr is set to NULL, dynamic + * module log levels will be disabled for the module and only the constant + * defined 'levels' bitmap will be used for the Log Module. If a Log Module's + * #Log_Module.dynamicLevelsPtr is not NULL, it will be set to a separate, + * volatile, `levels` bitmap for the Log Module. This separate bitmap will + * replace the previous, constant defined 'levels' bitmap for all module log + * level comparisons. In doing so, the log module's log levels will be + * dynamic and can be changed at runtime by the logging macro + * #Log_MODULE_SET_LEVELS(). Changing a module's log levels as a runtime + * operation enables total control over which log levels are enabled. + * + * As mentioned, if dynamic module log levels are enabled, comparisons done + * by the Log APIs on a module's `levels` bitmap will be at runtime instead + * of compile-time. This will both increase code size and increase logging + * execution time. Before enabling dynamic module log levels, these tradeoffs + * should be considered. + * + * ### Per Log Statement ### + * 1. (Level filtering): Insert the if statement that checks if the log level + * of the statement has been enabled in its module configuration. If the log + * level is not enabled, the process ends here. + * + * 2. (String declaration): Automate placement of constant strings, format + * strings, and pointers to these strings in the the nonloadable metadata + * section of the out file. This saves FLASH on the target. Each string + * contains a large amount of data, including the following: + * + * * File and line number of the log statement + * * The log level and module of the log statement + * * The format string + * * The number of arguments + * + * 3. (Argument counting): Log APIs are variadic in nature, up to 8 arguments + * are supported. However, at preprocess time, the number of arguments must + * be known. + * + * 4. (Name spacing): Routing from module to sink. The module parameter of the + * Log API controls which sink its log statements will be routed to. The + * preprocessor does name expansion to look up the enabled log levels and + * selected sink function pointers from the module's configuration + * structure. NOTE: The used sink may require initialization. Please verify + * with the specific sink documentation on how to initialize the sink. + * + * 5. (Sink API Invocation): With the names resolved and levels checked, the + * logger is now ready to execute the sink function. This is done via + * function pointer. + * + * An simplified pseudo-C implementation of what `Log_printf(LogModule_App1, + * Log_DEBUG, "Hello World!");` would expand to is shown below. This will not + * compile and is not extensive, just for illustration. + * + * @code + * // Global log enable check, wrapped around each log site + * #if defined(ti_log_Log_ENABLE) + * #if ti_log_Log_ENABLE_LogModule_App1 == 1 + * // Check if the level of this specific log statement has been enabled by the module + * if (LogMod_LogModule_App1.levels & level) { + * // Note that ^^ is the record separator. + * // Pack meta information into format string. This is stored off target. + * const string logMeta = + * "LOG_OPCODE_FORMATED_TEXT^^"../../log.c"^^80^^Log_DEBUG^^LogMod_LogModule_App1^^"Hello World!"^^0"; + * // Route log to the selected sink implementation. + * // This is done via function pointer. + * // The 0 indicates no arguments. If runtime arguments were + * // provided, they would follow. + * LogMod_LogModule_App1.printf(pointerToModuleConfig, 0); + * } + * #endif + * #endif + * @endcode + * + * From here, the logger has transferred control over to the sink + * implementation, which varies based on the transport (e.g. circular buffer in + * memory or UART). + * + * ## Modules ## + * + * When adding log statements to the target software, it is recommended to + * create a logging module for each software component in the image. Modules + * enable the reader to understand where the log record originated from. Some + * log visualizers may allow the reader to filter or sort log statements by + * module. It is also recommended to namespace modules. + * + * For example, a good module name for the `UART` driver that exists in + * `source/ti/drivers`, could be `ti_drivers_UART`. + * + * Modules also control the routing of log records to a sink. Routing is + * controlled via the Log Modules panel in SysConfig, but can be changed in + * plain C code - despite this being generally discouraged. To do it, use the + * macro @ref Log_MODULE_DEFINE and pass the sink specific `Log_MODULE_INIT_` + * to the `init` parameter within the @ref Log_MODULE_DEFINE macro. + * `Log_MODULE_INIT_` uses delegate functions for printf and buf that are + * implementation dependent for each sink based on the available hardware and + * whether the function is implemented for optimization. An example for the + * LogBuf sink is below, it will do the following + * + * 1. Create a module called `LogModule_App1`. + * 2. Initialize the module for use with the buffer based LogSink. Use buffer + * instance called `CONFIG_ti_log_LogSinkBuf_0`. + * 3. Enable only the `Log_ERROR` level. Other logs will not be stored. + * 4. Add the delegate function `LogSinkBuf_printfSingleton` for printf and `LogSinkBuf_bufDepInjection` for buf. + * 6. Disable dynamic log levels with `NULL`. + * + * @code + * #include + * #include + * Log_MODULE_DEFINE(LogModule_App1, + * Log_MODULE_INIT_SINK_BUF(CONFIG_ti_log_LogSinkBuf_0, + * Log_ERROR, LogSinkBuf_printfSingleton, LogSinkBuf_bufDepInjection, NULL)); + * @endcode + * + * TI created libraries will never use @ref Log_MODULE_DEFINE. This leaves the + * choice of routing logs to their sinks to the end application writer. This is + * recommended when creating any static libraries to defer the final logging + * decisions to link time. + * + * Each new module will instantiate a Log_Module structure with a `levels` + * bitmap and pointers to the selected sink implementation and sink + * configuration. See the @ref Log_Module structure for more information. + * + * If dynamic module log levels are enabled, each new Log_Module structure will + * include a pointer to a separate, volatile, `levels` bitmap. This new bitmap + * will be used for runtime comparisons of a module's log level. Two logging + * macros can be used to both set and get a module's log level. + * Log_MODULE_SET_LEVELS can be used to set the log level of a specific log + * module and Log_MODULE_GET_LEVELS can be used to retrieve the log level of a + * specific log module. + * + * ## Levels ## + * Log levels are a way to indicate the severity or importance of the contents + * of a particular log call site. Each call site takes an argument that allows + * the user to specify the level. As with modules, log visualization tools + * allow the user to sort or filter on a given level. This can help the reader + * to find important or relevant log statements in visualization. + * + * Log levels are also used to control the emission of logs. Each call site + * will check that the level is enabled before calling the underlying log API. + * + * Depending on optimization, the check at each log statement for whether the + * given level is enabled or not may end up being optimized away, and the + * entire log statement may be optimized away if the log level is not enabled. + * + * Additionally, depending whether dynamic module log levels are enabled or not, + * checking the level at each log statement will be evaluated at runtime or + * compile-time. Enabling dynamic module log levels or disabling + * Link-Time-Optimisation (LTO) will cause each log statement to perform a + * runtime check and will also increase the code size. + * + * @code + * if ((level) & module.levels) { + * // Call Log API + * } + * @endcode + * + * Optimization level `-flto` for both the TICLANG toolchain and GCC will + * typically be able to optimize the above statement. + * + * ## Log Metadata ## + * + * Each time a Log API is invoked, a metadata string is placed in the .out + * file. This string contains information about the API type, file, line + * module, level, and other information associated with the log call site. Each + * call site emits a string to a specific memory section called `.log_data`. In + * addition to this, a pointer to the string in .log_data is stored in another + * section called `.log_ptr`. Because the .log_ptr section is always in the + * same location, and each entry is the same size, an indexing-scheme can be + * used to refer to each log-string. Entry 0 in .log_ptr would point to the + * first string, entry 1 would point to the second string, etc. This Is + * necessary on some devices where transmitting an entire 32-bit address as a + * reference to the string is not possible, and instead an 8-bit index can be + * transmitted across the Log sink implementation instead. In order to use + * logging, this section should be added to the linker command file. By + * default, this section points to a nonloadable region of memory. Meaning that + * the metadata will not be loaded on the target device. Instead, the various + * logging visualization tools such as wireshark and TI ROV will read the + * metadata from this section and properly decode the log statements. The + * benefit of this approach is that very little memory is consumed on target. + * Additionally, the log transport only needs to store or send pointers to this + * meta section when a log API is called. + * + * This approach minimizes the amount of memory consumed on device and bytes + * sent over the transport. This section can be loaded on target if desired or + * if you are creating a custom logger. The design does not preclude this. + * + * In order to use the logging framework, the log section must be added to the + * linker command file. Here is a sample for the TI linker. Other examples can + * be found in the TI provided linker files for each toolchain. + * + * @code + * MEMORY + * { + * // List other memory regions here + * LOG_DATA (R) : origin = 0x90000000, length = 0x40000 + * LOG_PTR (R) : origin = 0x94000008, length = 0x40000 + * } + * SECTIONS + * { + * .log_data : > LOG_DATA, type = COPY + * .log_ptr : { *(.log_ptr*) } > LOG_PTR align 4, type = COPY + * } + * @endcode + * + * ## Sinks ## + * + * Sinks are responsible for storing or transporting the log record. In general + * there are two categories of sinks: + * + * 1. Those that perform storage of logs. + * 2. Those that stream logs over a transport medium, and thus do not perform + * storage. + * + * Sinks may vary in their implementation based on the nature of the storage or + * transport that they support, but they all have the following in common: + * + * * Are named ti_log_LogSink. Where `` is the name of the + * sink. + * * Must implement the Log_printf and Log_buf APIs from this file. + * * Must provide _USE, _INIT, and _DEFINE macros. + * + * In addition, some sinks require initialization. This will be listed in the + * documentation for the sink implementation. Sinks are closely tied to their + * associated host side tooling. Since the log statements are not parsed at all + * by the target code, this must be delegated to a program running on a PC. + * While the binary format of log records may vary across sink implementations, + * it is suggested that each log record contain: + * + * 1. Timestamp + * 2. Pointer to metadata string. This will be looked up by the PC side tooling + * in the out file. + * 3. Runtime arguments + * + * This is the minimum amount of information needed to decode a log statement. + * + * # Usage # + * This section provides a basic @ref ti_log_LOG_Synopsis "usage summary" and a + * set of @ref ti_log_LOG_Examples "examples" in the form of commented code + * fragments. Detailed descriptions of the LOG APIs are provided in subsequent + * sections. + * + * @anchor ti_log_LOG_Synopsis + * ### Synopsis ### + * + * @code + * // Import the Log header + * #include + * + * // Define your log module and log sink + * // If using SysConfig, it will be done automatically, or it can be done + * // manually: + * // Use helper macro from to make a sink instance + * // (buffer + config) with 100 entries. + * Log_SINK_BUF_DEFINE(MyBufferSink, LogSinkBuf_Type_CIRCULAR, 100); + * + * // Use helper macro from to make a module pointing at the new + * // sink instance. + * // This example will enable all log levels and disable dynamic log levels + * Log_MODULE_DEFINE(MyModule, Log_MODULE_INIT_SINK_BUF(MyBufferSink, Log_ALL, LogSinkBuf_printfSingleton, LogSinkBuf_bufDepInjection, NULL)) + * + * // Some log sinks may require special initialization to configure hardware. + * // Refer to the documentation of the sink you wish to use. For example, + * // LogSinkITM must be initialised like this before it can be used: + * // LogSinkITM_init(); + * + * // Invoke one of the log APIs you want to use for either formatted strings + * // or large buffers + * Log_printf(MyModule, Log_DEBUG, "The answer is %d", 42); + * uint8_t buffer[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + * Log_buf(MyModule, + * Log_VERBOSE, + * "The buffer values are:", + * buffer, + * sizeof(buffer)); + * @endcode + * + * @anchor ti_log_LOG_Examples + * ### Examples ### + * * @ref ti_utils_LOG_Example_printf "Log printf" + * * @ref ti_utils_LOG_Example_buf "Logging buffers" + * + * @anchor ti_utils_LOG_Example_printf **Log Printf**: + * + * The following example demonstrates use of the #Log_printf API in code. Log + * will embed the format string in the call site and will take arguments using + * varadic arguments. + * + * @code + * Log_printf(MyModule, Log_DEBUG, "Hello World!"); + * @endcode + * + * The arguments are type-cast to a uintptr_t, which is an unsigned integer + * type. This limits the supported format specifiers to the following: + * - Unsigned decimal integer: \%u + * - Unsigned hexadecimal integer: \%x + * - Unsigned hexadecimal integer (capital letters): \%X + * - Character: \%c + * - Signed decimal integer for positive values: \%i, \%d + * - Signed octal for positive values: \%o + * + * @anchor ti_utils_LOG_Example_buf **Log Buf**: + * + * The following example demonstrates use of the Log buf API in code. + * + * Buf will embed the format string in the call site and will take the buffer + * as a pointer and length. Buffers are treated as arrays of bytes. The buffer + * API should only be used when it is necessary to log data that is only + * available at runtime. It will actually send or store the entire contents of + * the buffer, so this API should be used sparingly as it is costly in terms of + * runtime and memory overhead. + * + * @code + * uint8_t bufferToLog[] = {0, 1, 2, 3, 4, 5}; + * Log_buf(ti_log_LogMain, + * Log_DEBUG, + * "The contents of bufferToLog are: ", + * bufferToLog, + * sizeof(bufferToLog)); + * @endcode + * + * @anchor ti_utils_LOG_Example_guide **Log API usage**: + * + * For a uniform experience with the logging tool, users are recommended to + * follow certain guidelines regarding the Log API. Typical use-cases for each + * API call is described below + * + * #### Log_printf #### + * + * #Log_printf should be the default mechanism for generating a log statement + * within an application. Along with the log levels, #Log_printf should be used + * to communicate debug information as a formatted string, which accepts + * variadic arguments. In this case, a pointer to the string and the arguments + * themselves are transported by the Log sink. + * + * @code + * Log_printf(MyLibraryLogModule, + * Log_ERROR, + * "Library function received illegal argument: %d", + * arg); + * @endcode + * + * #### Log_buf #### + * + * When the debug-information to be emitted is a large amount of dynamic data, + * and is not suitable as an argument to printf, then #Log_buf should be used. + * #Log_buf can transport the contents of large dynamic buffers, and as a + * consequence has a larger overhead and should be used sparsely. + */ + +#ifndef ti_log_Log__include +#define ti_log_Log__include + +/*! @ingroup ti_log_LOG */ +/*@{*/ + +#include +#include + +#if defined (__cplusplus) +extern "C" { +#endif + +/* + * ======== ti_log_Log_ENABLE ======== + * Enable instrumentation using link-time optimization implementation + * + * Define this symbol to add instrumentation at compile time. + * It must be defined before including this header file. + */ + +#if defined(DOXYGEN) || ti_log_Log_ENABLE +/* + * ============================= + * ======== Log Enabled ======== + * ============================= + */ + +/*! + * @brief Log version + */ +#define Log_TI_LOG_VERSION 0.1.0 + +/** + * @brief Defines a log module + * + * Log modules are like namespaces for log statements, but also controls the + * enabled log levels and decides where the log statement is redirected. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + * @param[in] init Initialization macro from the wanted sink + * + * This is a helper to define `Log_Module LogMod_yourName` and initialize it + * with the configuration and functions of the wanted log sink. + * + * For example, you have already used the sink definition macros found in + * LogSinkITM.h, and now you want to define a new module that uses this: + * + * `Log_MODULE_DEFINE(MyDriver, + * Log_MODULE_INIT_SINK_ITM(Log_DEBUG | Log_ERROR, + * LogSinkBuf_printfSingleton, + * LogSinkBuf_bufSingleton, + * Null))` + * + * Perhaps you used the LogSinkBuf.h helper macro which needs a unique name + * per instance and made a separate buffer for critical errors: + * + * `Log_MODULE_DEFINE(MyCritical, + * Log_MODULE_INIT_SINK_BUF(criticalBuf, + * Log_ERROR, + * LogSinkBuf_printfDepInjection, + * LogSinkBuf_bufDepInjection, + * NULL)` + * + * You would use this in your application via + * `Log_printf(MyCritical, Log_ERROR, "Oops")` + */ +#define Log_MODULE_DEFINE(name, init) const Log_Module LogMod_ ## name = init + +/** + * @brief Defines Log module as weak + * + * If there are multiple modules containing Log statements per library, + * special care must be taken not to create link-time failures. + * Whether Log statements from a library are present in the final binary is + * determined by the library configuration the application links against + * (instrumented vs uninstrumented). + * Each Log statement has a link-time dependency on its Log module. Enabling + * only a subset of Log modules contained within the library will cause any + * Log statements from other Log modules of that library to fail at link-time. + * This is avoided by declaring a weak instance of each Log module in C code + * that is compiled into the library. That way, the SysConfig-generated Log + * module definitions will override the weak library ones but they are there + * if SysConfig does not define that particular module. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + * @param[in] init Initialization value of the Log_Module struct. + */ +#if defined(DOXYGEN) || defined(__IAR_SYSTEMS_ICC__) +#define Log_MODULE_DEFINE_WEAK(name, init) const __weak Log_Module LogMod_ ## name = init +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define Log_MODULE_DEFINE_WEAK(name, init) const Log_Module LogMod_ ## name __attribute__((weak)) = init +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +supported compiler." +#endif + +/** + * @brief Declares a reference to a log module + * + * Declares that a log module is defined in another file so that it can be + * used in the file with this macro in it. + * + * @note This is done automatically for `Log` and `Log_buf` statements. + * + * @param[in] name Name of the log module. Gets prefixed with `LogMod_`. + */ +#define Log_MODULE_USE(name) extern const Log_Module LogMod_ ## name + +/** + * @brief Resolves to the symbol name of the log module + * + * Provided for forward compatibility purposes should you have a need to + * reference the log module symbol directly. + */ +#define LOG_MODULE_SYM(name) LogMod_ ## name + +/** @cond NODOC */ + +/* This macro protects against side effects of the C preprocessor expansion + * of log statements. Each log API should be guarded by it. + * An article explaining this behavior can be found here: + * https://gcc.gnu.org/onlinedocs/cpp/Swallowing-the-Semicolon.html + */ +#define _Log_GUARD_MACRO(x) do{ x }while(0) + +/* + * + * ======== Log Private Macros ======== + * + * The following macros are intended to be private to the log module and + * are not intended for use by the user. Private macros will start with _Log. + * + * In the case of multi level macros (macros that invoke other macros), a + * letter is appended at the end of the definition. With each level of nesting, + * the appended letter is incremented. + * + * For example: _Log_test --> _Log_test_A --> _Log_test_B + */ +/* Extracts the first/remaining argument from __VA_ARGS__ */ +#define _Log_CAR_ARG(N, ...) N +#define _Log_CDR_ARG(N, ...) __VA_ARGS__ + + +/* + * ======== Meta string tokenization macros ======== + */ +/* Helper macro to concatenate two symbols */ +#define _Log_CONCAT2_A(x,y) x ## _ ## y +#define _Log_CONCAT2(x,y) _Log_CONCAT2_A(x,y) +#define _Log_CONCAT3(x,y,z) _Log_CONCAT2(x,_Log_CONCAT2(y,z)) + +/* Helper macro to concatenate two symbols */ +#define _Log__TOKEN2STRING_A(x) #x +#define _Log_TOKEN2STRING(x) _Log__TOKEN2STRING_A(x) + +/* Macro to place meta string in a memory section separated by record separator */ +#define _Log_APPEND_META_TO_FORMAT(opcode, \ + file, \ + line, \ + level, \ + module, \ + format, \ + nargs) \ + _Log_TOKEN2STRING(opcode) "\x1e" \ + _Log_TOKEN2STRING(file) "\x1e" \ + _Log_TOKEN2STRING(line) "\x1e" \ + _Log_TOKEN2STRING(level) "\x1e" \ + _Log_TOKEN2STRING(module) "\x1e" \ + _Log_TOKEN2STRING(format) "\x1e" \ + _Log_TOKEN2STRING(nargs) + +/* Place a string in trace format section named ".log_data" locally + * This section must exist in the linker file + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define _Log_PLACE_FORMAT_IN_SECTOR(name, opcode, level, module, format, nargs)\ + __root static const char name[] @ ".log_data" = \ + _Log_APPEND_META_TO_FORMAT(opcode, \ + __FILE__, \ + __LINE__, \ + level, \ + module, \ + format, \ + nargs); \ + __root static const char * const _Log_CONCAT2(Ptr, name) @ _Log_TOKEN2STRING(_Log_CONCAT2(.log_ptr, module)) = name; +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define _Log_PLACE_FORMAT_IN_SECTOR(name, opcode, level, module, format, nargs)\ + static const char name[] \ + __attribute__((used,section(".log_data"))) = \ + _Log_APPEND_META_TO_FORMAT(opcode, \ + __FILE__, \ + __LINE__, \ + level, \ + module, \ + format, \ + nargs); \ + static const char * const _Log_CONCAT2(Ptr, name) \ + __attribute__((used,section(_Log_TOKEN2STRING(_Log_CONCAT3(.log_ptr, __LINE__, module))))) = name; +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +supported compiler." +#endif + +/* + * ======== Variadic macro workaround ======== + */ +/* Helper macro to count the number of arguments in __VA_ARGS_ */ +#define _Log_NUMARGS(...) _Log_NUMARGS_A(__VA_ARGS__, 8, 7, 6, 5, 4, 3, 2, 1, 0) +#define _Log_NUMARGS_A(...) _Log_NUMARGS_B(__VA_ARGS__) +#define _Log_NUMARGS_B(_first, _8, _7, _6, _5, _4, _3, _2, _1, N, ...) N + +/* + * Helper to select arg/noarg variant macro since empty va_arg fails + * when arguments are expected. Eg + * Log_VARIANT(test, A, 7, "Hello") -> test__noarg(A, 7, "Hello") + * Log_VARIANT(test, A, 7, "Hello %d", 42) -> test__arg1(A, 7, "Hello %d", 42) + */ +#define _Log_VARIANT(x, module, level, ...) \ + _Log_CONCAT2(x, _Log_NUMARGS_B(__VA_ARGS__, _arg8, _arg7, _arg6, _arg5, _arg4, _arg3, _arg2, _arg1, _noarg)) ( module, level, __VA_ARGS__ ) + +/* + * ======== Module-level preprocessor include macros ======== + */ + +/* Helper macro to extract the second argument of a variable number of input + * args + */ +#define _Log_SECOND_ARG(x, y, ...) y + +/* Temporary token name. + * Name must end in "1" for preprocessor substitution below to work. + */ +#define _Log_TOKEN_1 0, + +/* Helper macro to check whether a symbol is defined with a non-zero value. + * If x is a preprocessor define, the conversion below shows the macro output: + * x = 0 -> 0 + * x = 1 -> 1 + * x (no value) -> 0 + * (undefined) -> 0 + */ +#define _Log_DEFINED(x) _Log_DEFINED_A(x) + +/* If x is 1, _Log_TOKEN_##y turns into _Log_TOKEN_1 and is replaced with "0," + * If x is anything else, _Log_TOKEN_##y turns into _Log_TOKEN_y. + */ +#define _Log_DEFINED_A(y) _Log_DEFINED_B(_Log_TOKEN_##y) + +/* If z is "0,", _Log_SECOND_ARG is called with the triplet "0, 1, 0" and + * selects the second item in it, 1. + * If z is anything else, _Log_SECOND_ARG is called with the tuple "z 1, 0" and + * selects the second item in it, 0. + */ +#define _Log_DEFINED_B(z) _Log_SECOND_ARG(z 1, 0) + +/* Empty Log buf macro to use when a log module is not enabled in the + * preprocessor during compilation + */ +#define _Log_buf_C_0(module, level, format, data, size) + +/* Log_buf macro to use when a log module is enabled in the preprocessor during + * compilation. + */ +#define _Log_buf_C_1(module, level, format, data, size) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if ((level) & LogMod_ ## module.levels) { \ + _Log_PLACE_FORMAT_IN_SECTOR(_Log_CONCAT2(LogSymbol, __LINE__), \ + LOG_OPCODE_BUFFER, \ + level, \ + LogMod_ ## module, \ + format, \ + 0); \ + LogMod_ ## module.buf(&LogMod_ ## module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + data, \ + size); \ + } \ + ) + +/* First level indirection macro for Log_buf that delegates between an empty + * implementation and the actual log emission based on whether a module is + * enabled in the preprocessor during compilation. + * + * The _Log_DEFINED() macro generates a token output of [0, 1] that is then + * concatenated with "_Log_buf_C" to form the correct delegate macro name. + * + * The expected module define name is ti_log_Log_ENABLE_ | and must be + * set to 1. E.g. "-Dti_log_Log_ENABLE_MyLogModule=1". Just defining the symbol in + * the preprocessor will not emit any logs. + */ +#define _Log_buf_B(module, level, format, data, size) \ + _Log_CONCAT2(_Log_buf_C, _Log_DEFINED(ti_log_Log_ENABLE_ ## module))(module, level, format, data, size) + +/* Redirects to cast all printf arguments to uintptr_t to avoid surprises if + * passing wider values and the compiler silently allows it. + * + * These redirects also allow us to select which delegate function pointer to + * load from the #Log_Module. There are dedicated wrappers for certain printf + * argument counts. + * + * - 0-3 args redirect to dedicated functions to avoid loading the argument + * count when LTO is enabled. + * - 4-8 args redirect to a generic implementation. + * + * The 4-8 args break point is a compromise between how often the wrapper can + * be expected to be used in an average application and the constant overhead + * associated with providing it at all. There is also overhead per Log_Module + * for each additional arg count wrapper used. This overhead is eliminated when + * LTO is enabled though. + */ +#define _Log_printf__arg1(module, level, fmt, a0) \ + module.printf1(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + (uintptr_t)a0) +#define _Log_printf__arg2(module, level, fmt, a0, a1) \ + module.printf2(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + (uintptr_t)a0, \ + (uintptr_t)a1) +#define _Log_printf__arg3(module, level, fmt, a0, a1, a2) \ + module.printf3(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2) +#define _Log_printf__arg4(module, level, fmt, a0, a1, a2, a3) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3) +#define _Log_printf__arg5(module, level, fmt, a0, a1, a2, a3, a4) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4) +#define _Log_printf__arg6(module, level, fmt, a0, a1, a2, a3, a4, a5) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5) +#define _Log_printf__arg7(module, level, fmt, a0, a1, a2, a3, a4, a5, a6) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5, \ + (uintptr_t)a6) +#define _Log_printf__arg8(module, level, fmt, a0, a1, a2, a3, a4, a5, a6, a7) \ + _Log_printf__arg(module, level, fmt, (uintptr_t)a0, \ + (uintptr_t)a1, \ + (uintptr_t)a2, \ + (uintptr_t)a3, \ + (uintptr_t)a4, \ + (uintptr_t)a5, \ + (uintptr_t)a6, \ + (uintptr_t)a7) + +#define _Log_printf__arg(module, level, ...) \ + module.printf(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__), \ + _Log_NUMARGS(__VA_ARGS__), \ + _Log_CDR_ARG(__VA_ARGS__)) + +#define _Log_printf__noarg(module, level, ...) \ + module.printf0(&module, \ + (uint32_t)&_Log_CONCAT2(LogSymbol, __LINE__), \ + (uint32_t)&_Log_CONCAT3(Ptr, LogSymbol, __LINE__)) + +/* Empty Log_printf macro to use when a log module is not enabled in the + * preprocessor during compilation + */ +#define _Log_printf_C_0(opcode, module, level, ...) + +/* Log_printf macro to use when a log module is enabled in the preprocessor during + * compilation. + */ +#define _Log_printf_C_1(opcode, module, level, ...) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if (((LogMod_ ## module.dynamicLevelsPtr != NULL) && ((level) & *LogMod_ ## module.dynamicLevelsPtr)) || \ + ((level) & LogMod_ ## module.levels)) { \ + _Log_PLACE_FORMAT_IN_SECTOR(_Log_CONCAT2(LogSymbol, __LINE__), \ + opcode, \ + level, \ + LogMod_ ## module, \ + _Log_CAR_ARG(__VA_ARGS__), \ + _Log_NUMARGS(__VA_ARGS__)) \ + _Log_VARIANT(_Log_printf, LogMod_ ## module, level, __VA_ARGS__); \ + } \ + ) + +/* First level indirection macro for Log_printf that delegates between an empty + * implementation and the actual log emission based on whether a module is + * enabled in the preprocessor during compilation. + * + * The _Log_DEFINED() macro generates a token output of [0, 1] that is then + * concatenated with "_Log_buf_C" to form the correct delegate macro name. + * + * The expected module define name is ti_log_Log_ENABLE_ | and must be + * set to 1. E.g. "-Dti_log_Log_ENABLE_MyLogModule=1". Just defining the symbol + * in the preprocessor will not emit any logs. + */ +#define _Log_printf_B(opcode, module, level, ...) \ + _Log_CONCAT2(_Log_printf_C, _Log_DEFINED(ti_log_Log_ENABLE_ ## module))(opcode, module, level, __VA_ARGS__) + +/** @endcond */ + +/** + * @brief Log a continuous block of memory + * + * Use this macro to send out runtime data from the device. This API should be + * used when the data is non constant and can only be derived at runtime. It + * is the most intrusive in terms of record overhead and instructions used. + * + * @param[in] module Log module that the buffer originated from + * @param[in] level Log level of type @ref Log_Level + * @param[in] format Restricted format string + * @param[in] data Pointer to array of bytes (uint8_t *) + * @param[in] size Size in bytes of array to send + * + */ +#define Log_buf(module, level, format, data, size) _Log_buf_B(module, level, format, data, size) + +/** + * @brief Log an event with a printf-formatted string + * + * Use this macro to enable printf style logging. This API offers the most + * flexibility as the construction of the format string is embedded in the call + * site of the API. It also supports true variadic arguments. + * + * @param[in] module Log module that the buffer originated from + * @param[in] level Log level of type @ref Log_Level + * @param[in] ... Variable amount of arguments. Must match your + * event or format-string. + * + * Examples: + * - `Log_printf(MyModule, Log_INFO, "Hello World")` + * - `Log_printf(MyModule, Log_DEBUG, "Age: %d", 42)` + * + * @note All arguments are treated as 32-bit wide and are promoted or + * truncated accordingly. + */ +#define Log_printf(module, level, ...) _Log_printf_B(LOG_OPCODE_FORMATED_TEXT, module, level, __VA_ARGS__) + +/** + * @cond NODOC + * Macro for defining the version of the Log API + */ +#if defined(__IAR_SYSTEMS_ICC__) +#define _Log_DEFINE_LOG_VERSION(module, version) \ + __root static const char _Log_CONCAT2(Log_ti_log_version, __COUNTER__)[] @ ".log_data" = \ + _Log_APPEND_META_TO_FORMAT(LOG_OPCODE_VERSION, \ + module, \ + version, \ + 0, \ + 0, \ + 0, \ + 0) +#elif defined(__TI_COMPILER_VERSION__) || (defined(__clang__) && defined(__ti_version__)) || defined(__GNUC__) +#define _Log_DEFINE_LOG_VERSION(module, version) \ + static const char _Log_CONCAT2(Log_ti_log_version, __COUNTER__)[] \ + __attribute__((used,section(".log_data"))) = \ + _Log_APPEND_META_TO_FORMAT(LOG_OPCODE_VERSION, \ + module, \ + version, \ + 0, \ + 0, \ + 0, \ + 0) +#else +#error "Incompatible compiler: Logging is currently supported by the following \ +compilers: TI ARM Compiler, TI CLANG Compiler, GCC, IAR. Please migrate to a \ +supported compiler." +#endif + +/* Generate a symbol in the elf file that defines the version of the Log API */ +_Log_DEFINE_LOG_VERSION(Log, Log_TI_LOG_VERSION); + +/*! @endcond */ + +/** + * @brief Set a log module's log level bitmask + * + * If dynamic module log levels is enabled, use this macro to set a specific + * log module's log level bitmask as a runtime operation. + * + * @param[in] module Name of the log module. Gets prefixed with `LogMod_`. + * @param[in] levels Log level bitmask containing zero or more @ref Log_Level + * + */ +#define Log_MODULE_SET_LEVELS(module, levels) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if (LogMod_ ## module.dynamicLevelsPtr != NULL) { \ + *LogMod_ ## module.dynamicLevelsPtr = levels; \ + } \ + ) + +/** + * @brief Get a log module's log level bitmask + * + * If dynamic module log levels is enabled, use this macro to get a specific + * log module's log level bitmask as a runtime operation. + * + * @param[in] module Name of the log module. Gets prefixed with `LogMod_`. + * + */ +#define Log_MODULE_GET_LEVELS(module) \ + _Log_GUARD_MACRO( \ + Log_MODULE_USE(module); \ + if (LogMod_ ## module.dynamicLevelsPtr != NULL) { \ + *LogMod_ ## module.dynamicLevelsPtr; \ + } \ + else { \ + LogMod_ ## module.levels; \ + } \ + ) + +#else /* defined(DOXYGEN) || ti_log_Log_ENABLE */ + +/* + * ================================================= + * ======== Log Disabled (default behavior) ======== + * ================================================= + */ + +#define Log_MODULE_DEFINE(...) +#define Log_MODULE_DEFINE_WEAK(name, init) +#define Log_MODULE_USE(...) +#define Log_printf(module, level, ...) +#define Log_buf(module, level, ...) +#define _Log_DEFINE_LOG_VERSION(module, version) +#define Log_MODULE_SET_LEVELS(module, levels) +#define Log_MODULE_GET_LEVELS(module) + +#endif /* defined(DOXYGEN) || ti_log_Log_ENABLE */ + + + +/** + * @brief Log level bitmask values + * + * One of these enum values should be used in each #Log_printf and #Log_buf call + * and one or more should be used in each #Log_Module definition. + */ +typedef enum Log_Level { + /*! This should be the default level, reserved to be used by users to insert + * into applications for debugging. Exported libraries should avoid using + * this level. + */ + Log_DEBUG = 1 << 0, + + /*! This level is recommended to be used in libraries to emit verbose + * information about the operation of the system and system state. This + * level is typically used for very frequently emitted logs or for very + * detailed context and state information. + * + * Enabling this level in multiple #Log_Module may impact the operation of + * the application or saturate available log sink bandwidth and cause + * stalls in log record emission. + */ + Log_VERBOSE = 1 << 2, + + /*! This level is recommended to be used in libraries to emit simple + * information about the operation of the system and the system state. + * + * Enabling this level in multiple #Log_Module may impact the operation of + * the application or saturate available log sink bandwidth and cause + * stalls in log record emission. + */ + Log_INFO = 1 << 4, + + /*! This level is recommended to be used in libraries to emit warnings. It + * should typically indicate something unexpected, but not something that + * automatically leads to system failure. Warnings may be generated during + * the regular operation of an application. Frequent warnings may indicate + * a temporary or systemic issue with the system that may require + * intervention such as a reset or alteration to the software or hardware + * design. + * + * The typical usecase for this level is a recoverable failure such as a + * failed heap allocation or CRC error in a wireless transmission. + * + * Enabling this level in a #Log_Module will not impact regular device + * operation or impact available log sink bandwidth. + */ + Log_WARNING = 1 << 6, + + /*! This level is recommended to be used in libraries to emit errors. + * Typically, this should be used when something has failed and the system + * is unable to continue correct operation. Errors are not generated during + * regular system operation. An error record being generated always + * indicates an issue with system that requires intervention. The + * intervention depends on the error but could be a system reset or changes + * to the software or hardware of the system. + * + * Enabling this level in a #Log_Module will not impact regular device + * operation or impact available log sink bandwidth. + */ + Log_ERROR = 1 << 8, + + /*! This value enables all levels. Should only be used in #Log_Module + * definitions. + */ + Log_ALL = Log_DEBUG + Log_VERBOSE + Log_INFO + Log_WARNING + Log_ERROR, + + /*! This value disables all levels when used by itself. Should only be used + * in #Log_Module definitions. + */ + Log_NONE = 0, +} Log_Level; + +typedef const struct Log_Module Log_Module; + +typedef void (*Log_printf_fxn)(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...); + +typedef void (*Log_printfN_fxn)(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + ...); + +typedef void (*Log_buf_fxn)(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint8_t *data, + size_t size); + +/*! + * @brief Log module + * + * The application must not access any member variables of this structure! + */ +struct Log_Module { + void *sinkConfig; /*!< Pointer to the selected sink implementation and sink configuration */ + const Log_printf_fxn printf; /*!< Pointer to printf implementation with 4 to 8 arguments*/ + const Log_printfN_fxn printf0; /*!< Pointer to printf implementation with 0 arguments */ + const Log_printfN_fxn printf1; /*!< Pointer to printf implementation with 1 arguments */ + const Log_printfN_fxn printf2; /*!< Pointer to printf implementation with 2 arguments */ + const Log_printfN_fxn printf3; /*!< Pointer to printf implementation with 3 arguments */ + const Log_buf_fxn buf; /*!< Pointer to buf implementation */ + uint32_t levels; /*!< Log levels bitmap */ + uint32_t* const dynamicLevelsPtr; /*!< Pointer to a new volatile levels bitmap */ +}; + +/*! @} */ +#if defined (__cplusplus) +} +#endif + +#endif // ti_log_Log__include diff --git a/simplelink_lpf2/source/ti/log/LogSinkBuf.c b/simplelink_lpf2/source/ti/log/LogSinkBuf.c new file mode 100644 index 00000000..7f0f1c94 --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkBuf.c @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== LogSinkBuf.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#define LogSinkBuf_FULL -1 +#define LogSinkBuf_MAX_ARGS (LogSinkBuf_WORDS_PER_RECORD - 1) + +/* Global LogSinkBuf instance reference for use with singleton implementations + * of printf. + */ +Log_SINK_BUF_USE(CONFIG_ti_log_LogSinkBuf_0); + +static void findNextRecord(LogSinkBuf_Handle inst, LogSinkBuf_Rec **rec) +{ + /* compute next available record */ + *rec = inst->curEntry; + if (*rec == inst->endEntry) + { + if (inst->advance == LogSinkBuf_Type_CIRCULAR) + { + inst->curEntry = inst->buffer; + } + else + { + inst->advance = LogSinkBuf_FULL; + } + } + else + { + inst->curEntry = (LogSinkBuf_Rec *)((char *)*rec + sizeof(LogSinkBuf_Rec)); + } +} + +/* + * ======== LogSinkBuf_printf ======== + */ +void LogSinkBuf_printf(LogSinkBuf_Handle inst, uint32_t header, uint32_t index, uint32_t numArgs, va_list argptr) +{ + uintptr_t key; + uint32_t serial; + LogSinkBuf_Rec *rec; + uint32_t argsToCopy = numArgs; + + /* disable interrupts */ + key = HwiP_disable(); + + /* increment serial even when full */ + serial = ++(inst->serial); + + if (inst->advance == LogSinkBuf_FULL) + { + HwiP_restore(key); + return; + } + + /* compute next available record */ + findNextRecord(inst, &rec); + + rec->timestampLow = TimestampP_getNative32(); + + /* enable interrupts */ + HwiP_restore(key); + + /* write data to record */ + rec->serial = serial; + rec->type = LogSinkBuf_PRINTF; + + rec->data[0] = header; + + uint32_t i; + for (i = 0; i < argsToCopy; i++) + { + rec->data[1 + i] = va_arg(argptr, uintptr_t); + } + + return; +} + +/* + * ======== LogSinkBuf_printfDepInjection ======== + * + * This printf implementation is for use when multiple LogSinkBuf_Instance + * instances should be supported within an application. + * + * The implementation will read out the LogSinkBuf_Instance address at runtime + * from the handle argument. + */ +void LogSinkBuf_printfDepInjection(const Log_Module *handle, uint32_t header, uint32_t index, uint32_t numArgs, ...) +{ + va_list argptr; + + /* Guard against more arguments being passed in than supported */ + if (numArgs > LogSinkBuf_MAX_ARGS) + { + numArgs = LogSinkBuf_MAX_ARGS; + } + + LogSinkBuf_Handle inst = (LogSinkBuf_Handle)handle->sinkConfig; + + /* Get the VA args pointer in the initial wrapper since you cannot pass VA + * args to further functions using elipses (...) syntax. + * + * All va_start() does is get us the pointer to the first VA arg on the + * stack. That value will still be valid when passed on further. + */ + va_start(argptr, numArgs); + + LogSinkBuf_printf(inst, header, index, numArgs, argptr); + + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfDepInjection0 ======== + */ +void LogSinkBuf_printfDepInjection0(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf((LogSinkBuf_Handle)handle->sinkConfig, header, index, 0, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfDepInjection1 ======== + */ +void LogSinkBuf_printfDepInjection1(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf((LogSinkBuf_Handle)handle->sinkConfig, header, index, 1, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfDepInjection2 ======== + */ +void LogSinkBuf_printfDepInjection2(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf((LogSinkBuf_Handle)handle->sinkConfig, header, index, 2, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfDepInjection3 ======== + */ +void LogSinkBuf_printfDepInjection3(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf((LogSinkBuf_Handle)handle->sinkConfig, header, index, 3, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfSingleton ======== + * + * This implementation purposefully does not use the handle argument but + * instead references a single, global LogSinkBuf_Instance structure. When LTO + * is enabled, this allows the compiler to avoid loading the handle at the + * call site, saving on flash. + * + * Use of this printf implementation has the limitation that only one + * LogSinkBuf instance may be used and it will be assigned the + * LogsinkBuf_Instance name LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config + */ +void LogSinkBuf_printfSingleton(const Log_Module *handle, uint32_t header, uint32_t index, uint32_t numArgs, ...) +{ + va_list argptr; + + /* Guard against more arguments being passed in than supported */ + if (numArgs > LogSinkBuf_MAX_ARGS) + { + numArgs = LogSinkBuf_MAX_ARGS; + } + + /* Get the VA args pointer in the initial wrapper since you cannot pass VA + * args to further functions using elipses (...) syntax. + * + * All va_start() does is get us the pointer to the first VA arg on the + * stack. That value will still be valid when passed on further. + */ + va_start(argptr, numArgs); + LogSinkBuf_printf(&LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config, header, index, numArgs, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfSingleton0 ======== + */ +void LogSinkBuf_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf(&LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config, header, index, 0, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfSingleton1 ======== + */ +void LogSinkBuf_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf(&LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config, header, index, 1, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfSingleton2 ======== + */ +void LogSinkBuf_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf(&LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config, header, index, 2, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_printfSingleton3 ======== + */ +void LogSinkBuf_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t index, ...) +{ + va_list argptr; + + va_start(argptr, index); + LogSinkBuf_printf(&LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config, header, index, 3, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkBuf_buf ======== + */ +void LogSinkBuf_bufDepInjection(const Log_Module *handle, uint32_t header, uint32_t index, uint8_t *data, size_t size) +{ + uintptr_t key; + uint32_t serial; + LogSinkBuf_Rec *rec; + uint32_t numRecords = ((size) / LogSinkBuf_SIZEOF_RECORD) + ((size % LogSinkBuf_SIZEOF_RECORD) != 0); + numRecords += 1; + uint32_t i; + + if (handle == NULL) + { + return; + } + + LogSinkBuf_Handle inst = (LogSinkBuf_Handle)handle->sinkConfig; + + /* disable interrupts */ + key = HwiP_disable(); + + /* Here we acquire records as contiguous memory. + * This approach leads to long critical sections for large buffers + * and can be improved in the future once all hosts support fragmentation + * of packets + */ + for (i = 0; i < numRecords; i++) + { + /* increment serial even when full */ + serial = ++(inst->serial); + + if (inst->advance == LogSinkBuf_FULL) + { + HwiP_restore(key); + return; + } + + /* compute next available record */ + findNextRecord(inst, &rec); + + rec->timestampLow = TimestampP_getNative32(); + + /* write data to record */ + rec->serial = serial; + if (i == 0) + { + rec->type = LogSinkBuf_BUFFER_START; + rec->data[0] = header; + rec->data[1] = size; + } + else + { + rec->type = LogSinkBuf_BUFFER_CONTINUED; + memcpy(rec->data, &data[(i - 1) * LogSinkBuf_SIZEOF_RECORD], LogSinkBuf_SIZEOF_RECORD); + } + } + + /* enable interrupts */ + HwiP_restore(key); +} diff --git a/simplelink_lpf2/source/ti/log/LogSinkBuf.h b/simplelink_lpf2/source/ti/log/LogSinkBuf.h new file mode 100644 index 00000000..6b7b58d7 --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkBuf.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2019-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== LogSinkBuf.h ======== + */ + +#ifndef ti_loggers_utils_LogSinkBuf__include +#define ti_loggers_utils_LogSinkBuf__include + +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +#define Log_TI_LOG_SINK_BUF_VERSION 0.2.0 + +#define LogSinkBuf_Type_LINEAR (1) +#define LogSinkBuf_Type_CIRCULAR (2) +#define LogSinkBuf_WORDS_PER_RECORD (5) +#define LogSinkBuf_BUF_HEADER_SIZE sizeof(LogSinkBuf_RecordType) + sizeof(uint32_t) +#define LogSinkBuf_SIZEOF_RECORD (sizeof(uint32_t) * LogSinkBuf_WORDS_PER_RECORD) + +typedef enum +{ + LogSinkBuf_EVENT = 0, + LogSinkBuf_PRINTF = 1, + LogSinkBuf_BUFFER_START = 2, + LogSinkBuf_BUFFER_CONTINUED = 3 +} LogSinkBuf_RecordType; + +/* + * ======== LogSinkBuf_Rec ======== + */ +typedef struct LogSinkBuf_Rec +{ + uint32_t serial; + uint32_t timestampHigh; /* Upper 32 bits of timestamp */ + uint32_t timestampLow; /* Lower 32 bits of timestamp */ + LogSinkBuf_RecordType type; + uint32_t data[LogSinkBuf_WORDS_PER_RECORD]; +} LogSinkBuf_Rec; + +/* + * ======== LogSinkBuf_Instance ======== + */ +typedef struct LogSinkBuf_Instance +{ + uint8_t bufType; + int8_t advance; + uint16_t numEntries; + uint32_t serial; + LogSinkBuf_Rec *buffer; + LogSinkBuf_Rec *curEntry; /* next record to write */ + LogSinkBuf_Rec *endEntry; +} LogSinkBuf_Instance; + +/* + * ======== LogSinkBuf_Handle ======== + */ +typedef LogSinkBuf_Instance *LogSinkBuf_Handle; + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_printf statement into a ring buffer. + * + * Function to marshal a #Log_printf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer, it will overwrite a previous entry. + * + * This is a singleton implementation. It assumes that there is only one + * #LogSinkBuf_Instance object in the application and that this instance is called + * LogSinkBuf_CONFIG_ti_log_LogSinkBuf_0_config. + * + * This allows the toolchain in an LTO-enabled application to avoid generating + * instructions that load the @c handle since it is not needed. + * + * This implementation should not be used when multiple #LogSinkBuf_Instance + * instances are present within the system. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_printf + * + * @param[in] handle Unused handle + * + * @param[in] header Metadata pointer + * + * @param[in] headerPtr Unused pointer to metadata pointer + * + * @param[in] numArgs Number of arguments + * + * @param[in] ... Variable number of arguments + */ +extern void LogSinkBuf_printfSingleton(const Log_Module *handle, + uint32_t header, + uint32_t index, + uint32_t numArgs, + ...); + +extern void LogSinkBuf_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t index, ...); +/*! @endcond NODOC */ + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_printf statement into a ring buffer. + * + * Function to marshal a #Log_printf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer, it will overwrite a previous entry. + * + * This is a dependency injection implementation. It is able to support an + * arbitrary number of LogSinkBuf instances by passing in the sink state + * through @c handle. This requires additional flash to load @c handle in each + * #Log_printf though. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_printf + * + * @param[in] handle Handle to the module and sink instance + * + * @param[in] header Metadata pointer + * + * @param[in] headerPtr Unused pointer to metadata pointer + * + * @param[in] numArgs Number of arguments + * + * @param[in] ... Variable number of arguments + */ +extern void LogSinkBuf_printfDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t index, + uint32_t numArgs, + ...); + +extern void LogSinkBuf_printfDepInjection0(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfDepInjection1(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfDepInjection2(const Log_Module *handle, uint32_t header, uint32_t index, ...); + +extern void LogSinkBuf_printfDepInjection3(const Log_Module *handle, uint32_t header, uint32_t index, ...); +/*! @endcond NODOC */ + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_buf statement into a ring buffer. + * + * Function to marshal a #Log_buf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer, it will overwrite a previous entry. + * + * This is a dependency injection implementation. It is able to support an + * arbitrary number of LogSinkBuf instances by passing in the sink state + * through @c handle. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_buf + * + * @param[in] handle LogSinkBuf sink handle + * + * @param[in] header Metadata pointer + * + * @param[in] headerPtr Unused pointer to metadata pointer + * + * @param[in] data Data buffer to log + * + * @param[in] size Size in bytes of array to store + */ +extern void LogSinkBuf_bufDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t index, + uint8_t *data, + size_t size); +/*! @endcond NODOC */ + +/* + * Helpers to define/use instance. + */ +#define Log_SINK_BUF_DEFINE(name, type, num_entries) \ + static LogSinkBuf_Rec logSinkBuf_##name##_buffer[num_entries]; \ + LogSinkBuf_Instance LogSinkBuf_##name##_config = {.serial = 0, \ + .bufType = type, \ + .advance = type, \ + .numEntries = num_entries, \ + .buffer = logSinkBuf_##name##_buffer, \ + .curEntry = logSinkBuf_##name##_buffer, \ + .endEntry = logSinkBuf_##name##_buffer + (num_entries - 1)} +#define Log_SINK_BUF_USE(name) extern LogSinkBuf_Instance LogSinkBuf_##name##_config +#define Log_MODULE_INIT_SINK_BUF(name, _levels, printfDelegate, bufDelegate, _dynamicLevelsPtr) \ + { \ + .sinkConfig = &LogSinkBuf_##name##_config, .printf = printfDelegate, .printf0 = printfDelegate##0, \ + .printf1 = printfDelegate##1, .printf2 = printfDelegate##2, .printf3 = printfDelegate##3, .buf = bufDelegate, \ + .levels = _levels, .dynamicLevelsPtr = _dynamicLevelsPtr, \ + } + +_Log_DEFINE_LOG_VERSION(LogSinkBuf, Log_TI_LOG_SINK_BUF_VERSION); + +#if defined(__cplusplus) +} +#endif + +#endif /* ti_loggers_utils_LogSinkBuf__include */ diff --git a/simplelink_lpf2/source/ti/log/LogSinkITM.c b/simplelink_lpf2/source/ti/log/LogSinkITM.c new file mode 100644 index 00000000..ba8252f0 --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkITM.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2022-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== LogSinkITM.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#define LogSinkITM_RESET_FRAME (0xBBBBBBBB) + +/* + * ======== LogSinkITM_sendTimeSync ======== + */ +void LogSinkITM_sendTimeSync(void) +{ + uint64_t ts = TimestampP_getNative64(); + ITM_send32Polling(LogSinkITM_STIM_TIME_SYNC, ts & 0xffffffff); + ITM_send32Polling(LogSinkITM_STIM_TIME_SYNC, ts >> 32); +} + +/* + * ======== LogSinkITM_init ======== + */ +void LogSinkITM_init(void) +{ + /* disable interrupts */ + uint32_t key = HwiP_disable(); + /* Setup and enable ITM driver */ + bool itmOpened = ITM_open(); + + if (itmOpened) + { + /* Send the reset sequence */ + ITM_send32Atomic(LogSinkITM_STIM_INFO, LogSinkITM_RESET_FRAME); + /* Enable generation of time stamps based on system CPU */ + ITM_enableTimestamps(ITM_TS_DIV_16, false); + + /* Send information about timer resync */ + ITM_send16Polling(LogSinkITM_STIM_INFO, LogSinkITM_Info_Timing | ITM_TS_DIV_16 << 8); + ITM_send32Polling(LogSinkITM_STIM_INFO, TimestampP_nativeFormat64.value); + + /* Initial timestamp sync */ + LogSinkITM_sendTimeSync(); + } + + /* enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== LogSinkITM_printf ======== + */ +void LogSinkITM_printf(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint32_t numArgs, va_list argptr) +{ + uint32_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* Send header */ + ITM_send32Polling(LogSinkITM_STIM_HEADER, headerPtr); + + uint32_t i; + for (i = 0; i < numArgs; ++i) + { + uintptr_t arg = va_arg(argptr, uintptr_t); + ITM_send32Polling(LogSinkITM_STIM_TRACE, arg); + } + + /* enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== LogSinkITM_printfSingleton0 ======== + */ +void LogSinkITM_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkITM_printf(handle, header, headerPtr, 0, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkITM_printfSingleton1 ======== + */ +void LogSinkITM_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkITM_printf(handle, header, headerPtr, 1, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkITM_printfSingleton2 ======== + */ +void LogSinkITM_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkITM_printf(handle, header, headerPtr, 2, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkITM_printfSingleton1 ======== + */ +void LogSinkITM_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkITM_printf(handle, header, headerPtr, 3, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkITM_printfSingleton ======== + */ +void LogSinkITM_printfSingleton(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint32_t numArgs, ...) +{ + va_list argptr; + + va_start(argptr, numArgs); + LogSinkITM_printf(handle, header, headerPtr, numArgs, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkITM_buf ======== + */ +void LogSinkITM_bufSingleton(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint8_t *data, size_t size) +{ + uint32_t key; + + /* disable interrupts */ + key = HwiP_disable(); + + /* Send header */ + ITM_send32Polling(LogSinkITM_STIM_HEADER, headerPtr); + /* We always send the size of the expected buffer */ + ITM_send32Polling(LogSinkITM_STIM_TRACE, size); + /* Send out the actual data */ + ITM_sendBufferAtomic(LogSinkITM_STIM_TRACE, (const char *)data, size); + + /* enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== LogSinkITM_finalize ======== + */ +void LogSinkITM_finalize(void) +{ + /* disable interrupts */ + uint32_t key = HwiP_disable(); + + ITM_close(); + + /* enable interrupts */ + HwiP_restore(key); +} diff --git a/simplelink_lpf2/source/ti/log/LogSinkITM.h b/simplelink_lpf2/source/ti/log/LogSinkITM.h new file mode 100644 index 00000000..e43c0571 --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkITM.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2020-2024, Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file LogSinkITM.h + * @brief PRELIMINARY LogSinkITM interface + * + * WARNING These APIs are PRELIMINARY, and subject to + * change in the next few months. + * + * The LogSinkITM module is a sink that can be used in conjunction with the + * Log.h API. The API defined in this file should not be used directly, but + * is made available to the Logging framework and used as a transport layer + * for Log.h + * + * To use the ITM sink, ensure that the correct library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * Additionally, LogSinkITM_init must be called before LogSinkITM can be used. + * It is called from Board_init(). + * @code + * // Initialize ITM sink + * LogSinkITM_init(); + * @endcode + * + * This module implements two functions that are required by the Log API: + * - printf(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint32_t numArgs, ...); + * - buf(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint8_t *data, size_t size); + * + * Whenever a log-statement is invoked, that uses LogSinkITM as its sink, the functions above are ultimately invoked. + * + * @anchor ti_log_LogSinkITM_Overview + * # Overview + * LogSinkITM is a sink/transport layer that is able to output log-statements over ITM. + * It uses the ITM driver to stream data out onto a user-selectable pin, which can be received and processed + * by a host-side tool. For more information about the host-side tool, see tools/log/tiutils. + * For more information about the Log API, see the @ref log "Log documentation" + * + * @anchor ti_log_LogSinkITM_Channels + * # ITM Channels + * LogSinkITM uses certain channels for different purposes. Separate channels are used for data transfer, + * time synchronization, etc. For a complete overview, refer to LogSinkITM_StimulusPorts + * + * @anchor ti_log_LogSinkITM_Timestamps + * # ITM Timestamps + * Timestamps are automatically generated by the ITM hardware, and a synchronization timestamp is sent + * over the time-sync channel when the ITM sink is initiated. The timestamp is taken from the RTC, but the format + * depends on the device. Refer to TimestampP.h for implementation details + * + * ============================================================================ + */ + +#ifndef ti_log_LogSinkITM__include +#define ti_log_LogSinkITM__include + +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +#define Log_TI_LOG_SINK_ITM_VERSION 0.1.0 + +/* + * ======== LogSinkITM_StimulusPorts ======== + */ +typedef enum +{ + LogSinkITM_STIM_RAW0 = 0, //!< Port 0. Reserved for future use + LogSinkITM_STIM_RAW1, //!< Port 1. Reserved for future use + LogSinkITM_STIM_RAW2, //!< Port 2. Reserved for future use + LogSinkITM_STIM_RAW3, //!< Port 3. Reserved for future use + LogSinkITM_STIM_RAW4, //!< Port 4. Reserved for future use + LogSinkITM_STIM_RAW5, //!< Port 5. Reserved for future use + LogSinkITM_STIM_RAW6, //!< Port 6. Reserved for future use + LogSinkITM_STIM_RAW7, //!< Port 7. Reserved for future use + LogSinkITM_STIM_RAW8, //!< Port 8. Reserved for future use + LogSinkITM_STIM_RAW9, //!< Port 9. Reserved for future use + LogSinkITM_STIM_RAW10, //!< Port 10. Reserved for future use + LogSinkITM_STIM_RAW11, //!< Port 11. Reserved for logger time sync + LogSinkITM_STIM_RAW12, //!< Port 12. Used to notify logger states + LogSinkITM_STIM_RAW13, //!< Port 13. Reserved for future use + LogSinkITM_STIM_RAW14, //!< Port 14. Reserved for logger header messages + LogSinkITM_STIM_RAW15, //!< Port 15. Reserved for logger main data transfer + + /* Ports 16-31 reserved for LogSinkITM and dependents */ + LogSinkITM_STIM_RESV16 = 16, //!< Port 16. Reserved for raw ITM data + LogSinkITM_STIM_RESV17, //!< Port 17. Reserved for raw ITM data + LogSinkITM_STIM_RESV18, //!< Port 18. Reserved for raw ITM data + LogSinkITM_STIM_RESV19, //!< Port 19. Reserved for raw ITM data + LogSinkITM_STIM_RESV20, //!< Port 20. Reserved for raw ITM data + LogSinkITM_STIM_RESV21, //!< Port 21. Reserved for raw ITM data + LogSinkITM_STIM_RESV22, //!< Port 22. Reserved for raw ITM data + LogSinkITM_STIM_RESV23, //!< Port 23. Reserved for raw ITM data + LogSinkITM_STIM_RESV24, //!< Port 24. Reserved for raw ITM data + LogSinkITM_STIM_RESV25, //!< Port 25. Reserved for raw ITM data + LogSinkITM_STIM_RESV26, //!< Port 26. Reserved for raw ITM data + LogSinkITM_STIM_RESV27, //!< Port 27. Reserved for raw ITM data + LogSinkITM_STIM_TRACE, //!< Port 28. Reserved for logger main data transfer + LogSinkITM_STIM_HEADER, //!< Port 29. Reserved for logger header messages + LogSinkITM_STIM_TIME_SYNC, //!< Port 30. Reserved for logger time sync + LogSinkITM_STIM_INFO //!< Port 31. Reserved for logger control/info packets +} LogSinkITM_StimulusPorts; + +/* + * ======== LogSinkITM_ControlWord ======== + */ +typedef enum LogSinkITM_ControlWord +{ + LogSinkITM_Info_Timing = 3, +} LogSinkITM_ControlWord; + +/* + * ======== LogSinkITM_Instance ======== + */ +typedef struct LogSinkITM_Instance +{ + uint32_t serial; +} LogSinkITM_Instance; + +/* + * ======== LogSinkITM_Handle ======== + */ +typedef LogSinkITM_Instance *LogSinkITM_Handle; + +/* + * ======== LogSinkITM_init ======== + */ +extern void LogSinkITM_init(void); + +/* + * ======== LogSinkITM_finalize ======== + */ +extern void LogSinkITM_finalize(void); + +/*! + * @cond NODOC + * @brief Create a packet from a #Log_printf call and send it out over ITM. + * + * Function to create a packet from a #Log_printf call and send it out over + * ITM. + * + * This is a singleton implementation. It assumes that there is only one + * LogSinkITM instance in the application. + * This allows the compiler in an LTO-enabled application to avoid generating + * instructions that load the @c handle since it is not needed. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_printf + * + * @param[in] handle Unused handle + * + * @param[in] header Unused metadata pointer + * + * @param[in] headerPtr Pointer to metadata pointer + * + * @param[in] numArgs Number of arguments + * + * @param[in] ... Variable number of arguments + * + * @endcond + */ +extern void LogSinkITM_printfSingleton(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...); + +extern void LogSinkITM_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkITM_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkITM_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkITM_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); +/*! @endcond NODOC */ + +/*! + * @cond NODOC + * @brief Create a packet from a #Log_buf call and send it out over ITM. + * + * Function to create a packet from a #Log_buf call and send it out over + * ITM. + * + * This is a singleton implementation. It assumes that there is only one + * LogSinkITM instance in the application. + * This allows the compiler in an LTO-enabled application to avoid generating + * instructions that load the @c handle since it is not needed. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_buf + * + * @param[in] handle Unused handle + * + * @param[in] header Unused metadata pointer + * + * @param[in] headerPtr Pointer to metadata pointer + * + * @param[in] data Pointer to data to send out + * + * @param[in] size Size of @c data in bytes + * + * @endcond + */ +extern void LogSinkITM_bufSingleton(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint8_t *data, + size_t size); +/*! @endcond NODOC */ + +/* + * Helpers to define/use instance. ITM is a singleton so no arguments are taken. + */ +#define Log_SINK_ITM_DEFINE() LogSinkITM_Instance LogSinkITM_singletonConfig = {.serial = 0} +#define Log_SINK_ITM_USE() extern LogSinkITM_Instance LogSinkITM_singletonConfig +#define Log_MODULE_INIT_SINK_ITM(name, _levels, printfDelegate, bufDelegate, _dynamicLevelsPtr) \ + { \ + .sinkConfig = &LogSinkITM_singletonConfig, .printf = LogSinkITM_printfSingleton, \ + .printf0 = LogSinkITM_printfSingleton0, .printf1 = LogSinkITM_printfSingleton1, \ + .printf2 = LogSinkITM_printfSingleton2, .printf3 = LogSinkITM_printfSingleton3, \ + .buf = LogSinkITM_bufSingleton, .levels = _levels, .dynamicLevelsPtr = _dynamicLevelsPtr, \ + } + +_Log_DEFINE_LOG_VERSION(LogSinkITM, Log_TI_LOG_SINK_ITM_VERSION); + +#if defined(__cplusplus) +} +#endif + +#endif /* ti_log_LogSinkITM__include */ diff --git a/simplelink_lpf2/source/ti/log/LogSinkUART.c b/simplelink_lpf2/source/ti/log/LogSinkUART.c new file mode 100644 index 00000000..d4a0b9dc --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkUART.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2023-2024 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== LogSinkUART.c ======== + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +/* Each log packet is build with fields that are 4 bytes long */ +#define LogSinkUART_BYTES_PER_FIELD (4) + +/* A log_printf packet will always have a metadata pointer and a timestamp field + * followed by a variable amount of arguments. If no arguments are added, the + * packet will have 2 fields. + */ +#define LogSinkUART_PRINTF_MIN_FIELDS (2) + +/* A log_printf packet can have up to 8 arguments. Therefore, the maximum fields + * a packet can have is 10. + */ +#define LogSinkUART_PRINTF_MAX_FIELDS (10) + +/* A log_buf packet will always have a metadata pointer, timestamp and size + * field, followed by a buffer of variable size. Therefore, the minimum fixed + * fields a packet can have is 3. + */ +#define LogSinkUART_BUF_MIN_FIELDS (3) + +/* An overflow packet consists on a single metadata pointer field that occupies + * 4 bytes. + */ +#define LogSinkUART_OVERFLOW_PACKET_SIZE (4) + +/* Mask to change a metadata pointer from 0x9... to 0x8... */ +#define LogSinkUART_OVERFLOW_MASK (0xEFFFFFFF) + +extern const uint_least8_t LogSinkUART_count; + +/* + * =========== LogSinkUART_storePacket ========== + * Helper function to store a log packet into an intermediate ring buffer. To + * make the function thread-safe it should be called from a context where HWI + * is disabled. + */ +static void LogSinkUART_storePacket(RingBuf_Handle ringObject, unsigned char *packet, size_t packetLength) +{ + int linearSpace; /* Number of unsigned chars available in linear memory of ring buffer */ + unsigned char *dstAddr; /* Pointer reference to the next chunk of linear memory available */ + size_t bytesWritten = 0; /* Number of bytes written in the ring buffer */ + size_t writeCount = packetLength; /* Number of bytes left to write in the ring buffer */ + + /* Store packet in a Ring Buffer */ + do + { + /* Get the number of contiguous bytes we can copy to the ring + * buffer and the location where we can start the copy into the + * ring buffer. + */ + linearSpace = RingBuf_putPointer(ringObject, &dstAddr); + if (linearSpace > writeCount) + { + linearSpace = writeCount; + } + + memcpy(dstAddr, packet + bytesWritten, linearSpace); + + /* Update the ring buffer state with the number of bytes copied */ + RingBuf_putAdvance(ringObject, linearSpace); + + writeCount -= linearSpace; + bytesWritten += linearSpace; + } while ((linearSpace > 0) && (writeCount > 0)); +} + +/* + * ======== LogSinkUART_flush ======== + */ +void LogSinkUART_flush(void) +{ + /* Loop through all the UART2 LogSinks and flush each ring buffer */ + for (size_t i = 0; i < LogSinkUART_count; i++) + { + uint32_t key; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[i]; + LogSinkUART_Object *object = config->object; + + size_t bytesWritten; /* Number of bytes written to the UART */ + int available; /* Number of available linear bytes in ring buffer */ + unsigned char *srcAddr; /* Address in ring buffer where data can be read from */ + size_t readCount; /* Number of bytes left to read */ + + key = HwiP_disable(); + + /* If there is no data to flush go to the next ring buffer */ + readCount = RingBuf_getCount(&object->ringObj); + if (readCount == 0) + { + HwiP_restore(key); + continue; + } + + /* Read data from the ring buffer and put as much as possible on the UART */ + available = RingBuf_getPointer(&object->ringObj, &srcAddr); + UART2_write(object->uartHandle, srcAddr, available, &bytesWritten); + RingBuf_getConsume(&object->ringObj, bytesWritten); + + HwiP_restore(key); + } +} + +/* + * ======== LogSinkUART_init ======== + */ +void LogSinkUART_init(uint_least8_t index) +{ + uint32_t key; + UART2_Params uartParams; + + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[index]; + LogSinkUART_Object *object = config->object; + LogSinkUART_HWAttrs const *hwAttrs = config->hwAttrs; + + /* Disable interrupts */ + key = HwiP_disable(); + + /* Construct ring buffer for intermediate storage */ + RingBuf_construct(&object->ringObj, hwAttrs->bufPtr, hwAttrs->bufSize); + + /* Setup and open UART2 */ + UART2_Params_init(&uartParams); + + uartParams.writeMode = UART2_Mode_NONBLOCKING; + uartParams.baudRate = hwAttrs->baudRate; + uartParams.parityType = hwAttrs->parity; + + object->uartHandle = UART2_open(hwAttrs->uartIndex, &uartParams); + + if (object->uartHandle == NULL) + { + /* UART2_open() failed */ + while (1) {} + } + + /* enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== LogSinkUART_printf ======== + */ +void LogSinkUART_printf(LogSinkUART_Config *config, uint32_t headerPtr, uint32_t numArgs, va_list argptr) +{ + uintptr_t key; + uint32_t packet[LogSinkUART_PRINTF_MAX_FIELDS]; + + LogSinkUART_Object *object = config->object; + + size_t packetSize = (LogSinkUART_PRINTF_MIN_FIELDS + numArgs) * LogSinkUART_BYTES_PER_FIELD; + + /* Get faithful timestamp and ensure that we check + * if we have space for this packet. + */ + key = HwiP_disable(); + + packet[1] = TimestampP_getNative32(); + + /* Check if the ring buffer is full */ + if (RingBuf_isFull(&object->ringObj)) + { + HwiP_restore(key); + return; + } + + /* Assuming that the ring buffer is not full, we check if we + * have space for the current packet and the overflow packet. + * + * If there is space, we proceed normally, and we ensure that + * if there were not space for the next message, at least there + * would be space for the overflow message. + * + * If there is not enough space, we put an overflow packet into + * the ring buffer. + */ + if (RingBuf_space(&object->ringObj) >= packetSize + LogSinkUART_OVERFLOW_PACKET_SIZE) + { + /* Construct packet to be sent over UART */ + packet[0] = headerPtr; + + for (uint32_t i = 0; i < numArgs; i++) + { + packet[LogSinkUART_PRINTF_MIN_FIELDS + i] = va_arg(argptr, uintptr_t); + } + } + else + { + /* Construct overflow packet to be sent over UART. + * This packet is the header of the original printf + * but we mask it so it points to an invalid region. + * This can then be detected by the host tool. Information + * about which printf it is is conserved. + */ + packet[0] = headerPtr & LogSinkUART_OVERFLOW_MASK; + packetSize = LogSinkUART_OVERFLOW_PACKET_SIZE; + } + + /* Store packet in intermediate storage */ + LogSinkUART_storePacket(&object->ringObj, (unsigned char *)packet, packetSize); + + HwiP_restore(key); +} + +/* + * ======== LogSinkUART_printfSingleton ======== + */ +void LogSinkUART_printfSingleton(const Log_Module *handle, uint32_t header, uint32_t headerPtr, uint32_t numArgs, ...) +{ + va_list argptr; + + /* Since we assume LogSinkUART is a singleton in this implementation, we can + * access the zeroth array element directly. + */ + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[0]; + + /* Get the VA args pointer in the initial wrapper since you cannot pass VA + * args to further functions using elipses (...) syntax. + * + * All va_start() does is get us the pointer to the first VA arg on the + * stack. That value will still be valid when passed on further. + */ + va_start(argptr, numArgs); + + LogSinkUART_printf(config, headerPtr, numArgs, argptr); + + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfSingleton0 ======== + */ +void LogSinkUART_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkUART_printf((LogSinkUART_Config *)&LogSinkUART_config[0], headerPtr, 0, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfSingleton1 ======== + */ +void LogSinkUART_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkUART_printf((LogSinkUART_Config *)&LogSinkUART_config[0], headerPtr, 1, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfSingleton2 ======== + */ +void LogSinkUART_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkUART_printf((LogSinkUART_Config *)&LogSinkUART_config[0], headerPtr, 2, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfSingleton3 ======== + */ +void LogSinkUART_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + va_start(argptr, headerPtr); + LogSinkUART_printf((LogSinkUART_Config *)&LogSinkUART_config[0], headerPtr, 3, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfDepInjection ======== + */ +void LogSinkUART_printfDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...) +{ + va_list argptr; + + /* Since this is a dependency injection implementation, we need to fetch the + * config pointer from the Log_Module handle. + */ + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + + /* Get the VA args pointer in the initial wrapper since you cannot pass VA + * args to further functions using elipses (...) syntax. + * + * All va_start() does is get us the pointer to the first VA arg on the + * stack. That value will still be valid when passed on further. + */ + va_start(argptr, numArgs); + + LogSinkUART_printf(config, headerPtr, numArgs, argptr); + + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfDepInjection0 ======== + */ +void LogSinkUART_printfDepInjection0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + + va_start(argptr, headerPtr); + LogSinkUART_printf(config, headerPtr, 0, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfDepInjection1 ======== + */ +void LogSinkUART_printfDepInjection1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + + va_start(argptr, headerPtr); + LogSinkUART_printf(config, headerPtr, 1, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfDepInjection2 ======== + */ +void LogSinkUART_printfDepInjection2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + + va_start(argptr, headerPtr); + LogSinkUART_printf(config, headerPtr, 2, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_printfDepInjection3 ======== + */ +void LogSinkUART_printfDepInjection3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...) +{ + va_list argptr; + + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + + va_start(argptr, headerPtr); + LogSinkUART_printf(config, headerPtr, 3, argptr); + va_end(argptr); +} + +/* + * ======== LogSinkUART_bufDepInjection ======== + */ +void LogSinkUART_bufDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint8_t *data, + size_t size) +{ + uintptr_t key; + uint32_t packet[LogSinkUART_BUF_MIN_FIELDS]; + + LogSinkUART_Handle inst = (LogSinkUART_Handle)handle->sinkConfig; + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[inst->index]; + LogSinkUART_Object *object = config->object; + + size_t packetSize = LogSinkUART_BUF_MIN_FIELDS * LogSinkUART_BYTES_PER_FIELD; + + /* Get faithful timestamp and ensure that we check + * if we have space for this packet. + */ + key = HwiP_disable(); + + packet[1] = TimestampP_getNative32(); + + /* Check if the ring buffer is full */ + if (RingBuf_isFull(&object->ringObj)) + { + HwiP_restore(key); + return; + } + + /* Assuming that the ring buffer is not full, we check if we + * have space for the current packet and the overflow packet. + * + * If there is space, we proceed normally, and we ensure that + * if there were not space for the next message, at least there + * would be space for the overflow message. + * + * If there is not enough space, we put an overflow packet into + * the ring buffer. + */ + if (RingBuf_space(&object->ringObj) >= packetSize + size + LogSinkUART_OVERFLOW_PACKET_SIZE) + { + /* Construct and store packet to be sent over UART */ + packet[0] = headerPtr; + packet[2] = size; + LogSinkUART_storePacket(&object->ringObj, (unsigned char *)packet, packetSize); + LogSinkUART_storePacket(&object->ringObj, data, size); + } + else + { + /* Construct overflow packet to be sent over UART. + * This packet is the header of the original buffer + * but we mask it so it points to an invalid region. + * This can then be detected by the host tool. Information + * about which buffer it is is conserved. + */ + packet[0] = headerPtr & LogSinkUART_OVERFLOW_MASK; + LogSinkUART_storePacket(&object->ringObj, (unsigned char *)packet, LogSinkUART_OVERFLOW_PACKET_SIZE); + } + + /* enable interrupts */ + HwiP_restore(key); +} + +/* + * ======== LogSinkUART_finalize ======== + */ +void LogSinkUART_finalize(uint_least8_t index) +{ + LogSinkUART_Config *config = (LogSinkUART_Config *)&LogSinkUART_config[index]; + LogSinkUART_Object *object = config->object; + + /* Close the UART peripheral making sure that there are no ongoing writes*/ + UART2_writeCancel(object->uartHandle); + UART2_close(object->uartHandle); +} diff --git a/simplelink_lpf2/source/ti/log/LogSinkUART.h b/simplelink_lpf2/source/ti/log/LogSinkUART.h new file mode 100644 index 00000000..e379748a --- /dev/null +++ b/simplelink_lpf2/source/ti/log/LogSinkUART.h @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2023-2024 Texas Instruments Incorporated - http://www.ti.com + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*!***************************************************************************** + * @file LogSinkUART.h + * @brief PRELIMINARY LogSinkUART interface + * + * @warning These APIs are PRELIMINARY + * + * The LogSinkUART module is a sink that can be used in conjunction with the + * Log.h API in source/ti/log/ and the logging tools available in + * tools/log/tiutils. The API defined in this file is made available to the + * Logging framework and used as a transport layer for Log.h. For more + * information about the Log API, see the @ref log "Log documentation". + * + * To use the UART sink, ensure that the correct library for your + * device is linked in and include this header file as follows: + * @code + * #include + * @endcode + * + * This module implements two functions that are required by the Log API: + * - printf(const Log_Module *handle, uint32_t header, uint32_t headerPtr, + * uint32_t numArgs, ...); + * - buf(const Log_Module *handle, uint32_t header, uint32_t headerPtr, + * uint8_t *data, size_t size); + * + * Whenever a log statement that uses LogSinkUART as its sink is called, the + * log module delegates to one of the functions above. + * + * @anchor ti_log_LogSinkUART_Overview + * # Overview + * LogSinkUART is a sink/transport layer that asynchronously outputs encoded + * log statements over UART. It uses the UART2 driver to stream data out onto a + * user-selectable pin, which can be received and processed by a host-side + * tool. For more information about the host-side tool, see tools/log/tiutils. + * + * At the log-site the sink separates the generation of the log record from the + * transportation of the record off the device. Deferring the transportation to + * a later point of the program execution is done to minimize the runtime + * intrusion that would be caused by synchronously outputting the log + * statements through the relatively slow UART. The first part generates and + * stores the log statements into an intermediate storage synchronously. The + * second part uses the idle task of the OS, executed when no other tasks or + * interrupts are running, to move the data stored in the intermediate storage + * off the device. + * + * By transmitting messages asynchronously the readout at the host-side is + * also asynchronous. As a consequence, the receiving of log statements at the + * host-side can be deferred from their execution in the program. + * + * This sink requires no special hardware to capture and decode the logs beyond + * a basic UART-to-USB bridge. + * + * The data flow at a high level is: + * 1. Log statement captured at the log site with timestamp + * 2. Log data marshalled into a log packet + * 3. Log packet moved to ring buffer working as intermediate storage + * 4. Intermediate storage flushed via the UART2 driver when nothing else + * is happening through a function installed in the Idle-loop/task + * 5. Data sent out on the UART line + * 6. Data received by listening COM port on host + * 7. Data decoded by host and fed through remainder of host logging + * infrastructure + * 8. Logs visualised in Wireshark or dumped to console / log file + * + * @note Throughout this documentation and API the term "packet" is used + * instead of the term "record". Both terms are equivalent and can be used + * interchangeably. + * + *
+ * @anchor ti_log_LogSinkUART_Considerations + * # Considerations + * + * When using this sink consider the following: + * - The number of sinks is limited by the number of UART peripherals in + * the device. + * - When a UART instance is consumed for a sink it can not be used for + * other operations. + * - When a single UART LogSink instance is used, an optimised printf is + * used that reduces the footprint of each #Log_printf statement. + * - Each UART LogSink will create its own Ring Buffer. + * - If any part of the transmission is lost/not received by the + * logging-tool, the rest of the data might not be interpreted correctly. + * - 9.54 hours of logging timestamps are available before overflowing in a + * system where 1 bit = 8 us. The tick period for each device can be read + * from the multiplier variable in TimestamP.c under + * kernel/freertos/dpl. If the timestamp overflows it will go back to 0. + * - The LogSinkUART sinks are flushed in the order they are instantiated.  + * - If performance issues are observed either increase the size of the + * UART2 ring buffer to increase throughput or increase the size of the + * intermediate ring buffer size for more log statements. Also note that + * the device needs to have idle-time to automatically flush data. If the + * software is always doing something then nothing will ever be output. + * - SRAM requirements scale with the number of log records to store in + * between flushing the buffer. + * - A #Log_printf call has an execution time of 20 us to 27.8 us depending + * on the number of arguments. + * - A Log_buf call has a minimum execution time of 32.8 us and an + * approximate increase of 0.183 us per byte in the buffer. + * + *
+ * @anchor ti_log_LogSinkUART_DesignArchitecture + * # Design Architecture + * + * The LogSinkUART implementation is based on the following architecture. + * + * ## Packet Transmission Format + * All log packets begin with a 32-bit metadata pointer followed by a 32-bit + * timestamp. The next fields depend on the type of log statement: + * - Log_printf: Variable number of 32-bit arguments that range from 0 to + * 8. + * - Log_buf: 32-bit field with the size of the buffer being sent followed + * by the buffer data. + * + * @startuml + * skinparam useBetaStyle true + * + * + * + * concise "Log_printf packet" as LP + * concise "Log_buf packet" as LB + * hide time-axis + * + * scale 1 as 50 pixels + * + * @LP + * 0 is Metadata_Pointer #FFCC99: 0:31 + * +4 is Timestamp #CC99FF: 32:63 + * +4 is VA_Arg_0 #99CCFF: 64:95 + * +4 is {-} #99CCFF: ... + * +1 is VA_Arg_n #99CCFF: 32-bits + * +4 is {-} + * + * @LB + * 0 is Metadata_Pointer #FFCC99: 0:31 + * +4 is Timestamp #CC99FF: 32:63 + * +4 is Buffer_Size #97D077: 64:95 + * +4 is Buffer_Data #99CCFF + * +5 is {-} + * @enduml + * + * If a packet would overflow the ring buffer, a 32-bit overflow packet is + * placed instead. It is the original metadata pointer modified to be + * identified as an overflow packet. The host-side tool decodes it and displays + * an overflow message, indicating that at least that message would have + * overflowed. When this is observed, it is recommended to either resize the + * ring buffer or disable some log statements. + * @note If the intermediate ring buffer is full, no new overflow or log + * packets will be stored. + * + * Each log statement used will occupy the following amount of SRAM: + * + * Log statement type | Log statement size (bytes) | + * ------------------ | --------------------------- | + * Log_printf | 8 + 4 * number_of_arguments | + * Log_buf | 12 + buffer_size | + * Overflow | 4 | + * + * ## Packet Framing + * The host-side must receive and properly handle a continuous stream of packets. + * It is able to decode and synchronize packets. If the first 32 bits is not a + * valid metadata-pointer address, it will left-shift byte-by-byte until it detects + * a valid one. Once a metadata-pointer address is verified, the host-side tool + * knows that it is followed by a timestamp. The number of arguments for each + * frame is extracted from the .out file. This determines the length of the + * current packet and when the metadata-pointer address from the next packet is + * expected. + * + * ## Flushing the data + * A hook function installed in the Idle-loop/task is run when no other tasks + * or interrupts are running. It flushes as many log packets as possible from + * the intermediate storage via the UART2 driver set in nonblocking mode. In + * this mode, UART2_write() will copy as much data into the transmit buffer as + * space allows and return immediately. The maximum space allowed, and + * therefore the amount of data sent out every time that the hook function is + * called, is determined by the size of the TX Ring Buffer. + * + * The Idle-loop/task will always be run before the power management loop. + * + * Since each OS has a different implementation of the Idle-loop/task, the + * installation of the hook function will also be different for each OS. The + * automatic installation is currently supported for FreeRTOS and TI-RTOS 7 + * when using SysConfig. + * + *
+ * @anchor ti_log_LogSinkUART_Usage + * # Usage + * + * To use the UART LogSink the application calls the following APIs: + * - LogSinkUART_init(): Initialize a UART sink. This function takes as + * argument an index that describes the sink that has to be initialized. + * - LogSinkUART_flush(): Function to flush all the LogSinkUART sinks in the + * order they are added. For each sink it will read data from the ring + * buffer and put as much as possible on the UART interface. + * - LogSinkUART_finalize(): Finalize a UART sink. This function takes as + * argument an index that describes the sink that has to be finalized. + * + * Details on usage are provided in the following subsections. + * + * @anchor ti_log_LogSinkUART_Examples + * ## Examples # + * * @ref ti_log_LogSinkUART_initialize "Initializing a UART LogSink" + * * @ref ti_log_LogSinkUART_flush "Flushing UART sinks" + * * @ref ti_log_LogSinkUART_finalize "Finalizing a UART LogSink" + * * @ref ti_log_LogSinkUART_protect "Protect log statements" + * + * @anchor ti_log_LogSinkUART_initialize + * ### Initializing a UART LogSink + * If LogSinkUART is enabled through SysConfig, then LogSinkUART_init() will be + * automatically called from Board_init(). If SysConfig is not used, the user + * must initialize the log sink. LogSinkUART_init() can also be called after a + * sink has been finalized with LogSinkUART_finalize(). To initialize a sink, + * first include the ti_log_config.h library containing the expansion of the + * sink name. Afterwards, call the initialize function passing as an argument + * the name of the sink to be initialized. + * + * @code + * #include "ti_log_config.h" + * + * LogSinkUART_init(sink_name); + * @endcode + * + * @anchor ti_log_LogSinkUART_flush + * ### Flushing UART sinks + * LogSinkUART_flush() will be called automatically in the Idle-loop/task for + * FreeRTOS and TI-RTOS 7. Despite this, the user can still manually call the + * function to send out as much data as possible from all the existing ring + * buffers when desired. The flush function can be called from either a task or + * interrupt context. + * + * @anchor ti_log_LogSinkUART_finalize + * ### Finalizing a UART LogSink + * LogSinkUART_finalize() will cancel all ongoing UART writes and call + * UART2_close(). All log packets remaining in the intermediate storage will be + * lost when calling LogSinkUART_init() because the ring buffer will be reset. + * All log statements after a finalize call will also be lost due to the reset + * of the ring buffer when initializing the sink. To finalize a sink first + * include the ti_log_config.h library containing the expansion of the sink + * name. Afterwards, call the finalize function passing as an argument the + * name of the sink to be finalized. + * + * @code + * #include "ti_log_config.h" + * + * LogSinkUART_finalize(sink_name); + * @endcode + * + * @anchor ti_log_LogSinkUART_protect + * ### Protect log statements + * To ensure that logs are correctly ordered when put back together on the + * host, log statements can be called from a context where HWI are disabled. + * This also ensures that the recorded timestamp is faithful to when the log + * statement was executed. + * + * Logs can end up ordered out as a consequence of a log call being preempted + * by a higher priority task with other log statements. The following example + * shows how a log statement can be protected to ensure that the execution + * sequence is maintained in the ordering on the host-side. + * + * @code + * #include + * uint32_t key; + * + * key = HwiP_disable(); + * Log_printf(MyModule, Log_DEBUG, "The answer is %d", 42); + * HwiP_restore(key); + * @endcode + * + *
+ * @anchor ti_log_LogSinkUART_Configuration + * # Configuration + * + * In order to use the LogSinkUART APIs, the application is required to provide + * sink-specific configuration in the ti_log_config.c file. The LogSinkUART + * interface defines a configuration data structure: + * + * @code + * typedef struct { + * void *object; + * void const *hwAttrs; + * } LogSinkUART_Config; + * @endcode + * + * The application must declare an array of #LogSinkUART_Config elements, named + * @p LogSinkUART_config[]. Each element of @p LogSinkUART_config[] must be + * populated with pointers to a sink specific object, and hardware attributes. + * The hardware attributes define properties such as the UART peripheral's + * attributes, and a pointer to the intermediate ring buffer and its size. + * These are automatically assigned through SysConfig. Each element in + * @p LogSinkUART_config[] corresponds to a UART sink instance, and none of the + * elements should have NULL pointers. + * + * + * The configuration for the UART LogSink is based on the driver's + * configuration. Refer to the @ref driver_configuration + * "Driver's Configuration" section for driver configuration information. + * + * To automatically initialize a UART sink when initializing the board, + * LogSinkUART_init() is called inside Board_init() in ti_drivers_config.c. To + * have access to the function and get the expansion of the sink name, include + * the following libraries: + * + * @code + * #include "ti_log_config.h" + * #include + * @endcode + * + * ============================================================================ + */ + +#ifndef ti_log_LogSinkUART__include +#define ti_log_LogSinkUART__include + +#include +#include +#include +#include +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief LogSinkUART version + */ +#define Log_TI_LOG_SINK_UART_VERSION 0.1.0 + +/*! + * @brief LogSinkUART Hardware attributes + */ +typedef struct +{ + unsigned char *bufPtr; /*!< Pointer to intermediate ring buffer */ + size_t bufSize; /*!< Size of bufPtr */ + uint32_t baudRate; /*!< UART2 baudRate */ + UART2_Parity parity; /*!< UART2 parity */ + uint32_t uartIndex; /*!< UART2 instance index */ +} LogSinkUART_HWAttrs; + +/*! + * @brief LogSinkUART Object + * + * The application must not access any member variables of this structure! + */ +typedef struct +{ + UART2_Handle uartHandle; /*!< UART2 handle */ + RingBuf_Object ringObj; /*!< Intermediate ring buffer */ +} LogSinkUART_Object; + +/*! + * @brief LogSinkUART Global configuration + * + * The LogSinkUART_Config structure contains a set of pointers used to + * characterize a LogSinkUART implementation. + * + */ +typedef struct +{ + /*! Pointer to a driver specific data object */ + void *object; + /*! Pointer to a driver specific hardware attributes structure */ + void const *hwAttrs; +} LogSinkUART_Config; + +/*! + * @brief Array with the configuration of each sink. + */ +extern const LogSinkUART_Config LogSinkUART_config[]; + +/*! + * @brief LogSinkUART Sink parameters + * + * The LogSinkUART_Instance structure contains a set of parameters used to + * characterize a LogSinkUART sink. + */ +typedef struct +{ + /*! Index of the LogSinkUART sink instance used to index + * @p LogSinkUART_config[] */ + uint_least8_t index; +} LogSinkUART_Instance; + +/*! + * @brief A handle for the LogSinkUART_Instance structure. + */ +typedef LogSinkUART_Instance *LogSinkUART_Handle; + +/*! + * @brief Flush all the LogSinkUART sinks. + * + * Function to flush each of the LogSinkUART sinks in the order they are added. + * For each sink it will read its ring buffer and put as much data as possible + * on the UART interface. The flush can occur in task or interrupt context. + */ +extern void LogSinkUART_flush(void); + +/*! + * @brief Initialize a given LogSinkUART sink. + * + * Function to initialize a given LogSinkUART sink specified by the + * particular index value. It constructs a ring buffer, sets up the + * UART2 attributes and opens the given UART peripheral + * + * @param[in] index Logical sink number for the LogSinkUART indexed into + * the LogSinkUART_config table + * + * The UART peripheral is set to send only mode, with the following fixed + * parameters: + * @code + * writeMode = UART2_Mode_NONBLOCKING; + * dataLength = UART2_DataLen_8; + * stopBits = UART2_StopBits_1; + * @endcode + * + * The baudRate and parityType can be configured from SysConfig. The size of + * the ring buffer can also be set from the SysConfig. + */ +extern void LogSinkUART_init(uint_least8_t index); + +/*! + * @brief Finalize a given LogSinkUART sink. + * + * Function to finalize a given LogSinkUART sink specified by the + * particular index value. It cancels any ongoing write operation over the + * given UART peripheral and closes it. + * + * @param[in] index Logical sink number for the LogSinkUART indexed into + * the LogSinkUART_config table + */ +extern void LogSinkUART_finalize(uint_least8_t index); + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_printf statement into a ring buffer. + * + * Function to marshal a #Log_printf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer it stores an overflow packet instead. + * + * This implementation is optimised for use with LTO when there is only a + * single UART LogSink instance to reduce the footprint of #Log_printf + * statements. + * + * It should not be used when multiple UART LogSink instances are present + * within the system. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_printf + * + * @param[in] handle LogSinkUART sink handle + * + * @param[in] header Metadata pointer + * + * @param[in] headerPtr Pointer to metadata pointer + * + * @param[in] numArgs Number of arguments + * + * @param[in] ... Variable amount of arguments + */ +extern void LogSinkUART_printfSingleton(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...); + +extern void LogSinkUART_printfSingleton0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfSingleton1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfSingleton2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfSingleton3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); +/*! @endcond NODOC */ + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_printf statement into a ring buffer. + * + * Function to marshal a #Log_printf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer it stores an overflow packet instead. + * + * This is a dependency injection implementation. It is able to support an + * arbitrary number of LogSinkUART_Instance instances by passing in the sink + * state though @c handle. This requires additional flash to load @c handle in + * each #Log_printf though. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_printf + * + * @param[in] handle LogSinkUART sink handle + * + * @param[in] header Metadata pointer + * + * @param[in] headerPtr Pointer to metadata pointer + * + * @param[in] numArgs Number of arguments + * + * @param[in] ... Variable amount of arguments + */ +extern void LogSinkUART_printfDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint32_t numArgs, + ...); + +extern void LogSinkUART_printfDepInjection0(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfDepInjection1(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfDepInjection2(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); + +extern void LogSinkUART_printfDepInjection3(const Log_Module *handle, uint32_t header, uint32_t headerPtr, ...); +/*! @endcond NODOC */ + +/*! + * @cond NODOC + * @brief Marshal and store a #Log_buf statement into a ring buffer. + * + * Function to marshal a #Log_buf statement into a packet + * and store it into a ring buffer. If the packet would overflow + * the ring buffer it stores an overflow packet instead. + * + * This is a dependency injection implementation. It is able to support an + * arbitrary number of LogSinkUART_Instance instances by passing in the sink + * state though @c handle. + * + * @note Applications must not call this function directly. This is a helper + * function to implement #Log_buf + * + * @param[in] handle LogSinkUART sink handle + * + * @param[in] header Unused metadata pointer + * + * @param[in] headerPtr Pointer to metadata pointer + * + * @param[in] data Data buffer to log + * + * @param[in] size Size in bytes of array to store + */ +extern void LogSinkUART_bufDepInjection(const Log_Module *handle, + uint32_t header, + uint32_t headerPtr, + uint8_t *data, + size_t size); +/*! @endcond NODOC */ + +/*! + * @brief Create a LogSinkUART instance called @c name + */ +#define Log_SINK_UART_DEFINE(name) LogSinkUART_Instance LogSinkUART_##name##_Config = {.index = name} + +/*! + * @brief Use a LogSinkUART instance called @c name when not created in the same + file + */ +#define Log_SINK_UART_USE(name) extern LogSinkUART_Instance LogSinkUART_##name##_Config + +/*! + * @brief Initialize a LogSinkUART instance called @c name with log @c _levels , + * printf delegate function @c printfDelegate , buf delegate function @c bufDelegate + * and dynamic log level @c _dynamicLevelsPtr + */ +#define Log_MODULE_INIT_SINK_UART(name, _levels, printfDelegate, bufDelegate, _dynamicLevelsPtr) \ + { \ + .sinkConfig = &LogSinkUART_##name##_Config, .printf = printfDelegate, .printf0 = printfDelegate##0, \ + .printf1 = printfDelegate##1, .printf2 = printfDelegate##2, .printf3 = printfDelegate##3, .buf = bufDelegate, \ + .levels = _levels, .dynamicLevelsPtr = _dynamicLevelsPtr, \ + } + +/*! + * @cond NODOC + * Define log sink version. + * + * @note Applications must not call this function directly. This is a helper + * function. + */ +_Log_DEFINE_LOG_VERSION(LogSinkUART, Log_TI_LOG_SINK_UART_VERSION); +/*! @endcond NODOC */ + +#if defined(__cplusplus) +} +#endif + +#endif /* ti_log_LogSinkUART__include */